From 71f349799b34c8b6ce3df42126b4de6cfa16456d Mon Sep 17 00:00:00 2001 From: David Gibson Date: Thu, 15 May 2008 16:46:39 +1000 Subject: [POWERPC] Convert remaining dts-v0 files to v1 At the moment we have a mixture of left-over version 0 and new-format version 1 files in arch/powerpc/boot/dts. This is potentially confusing to people new to the dts format attempting to figure it out. So, this patch converts all the as-yet unconverted dts v0 files and converts them to v1. They're mechanically-converted, and not hand tweaked so in some cases they're not 100% in keeping with usual v1 style, but the convertor program does have some heuristics so the discrepancies aren't too bad. I have checked that this patch produces no changes to the resulting dtb binaries. Signed-off-by: David Gibson Acked-by: Josh Boyer Acked-by: Geoff Levand Signed-off-by: Josh Boyer --- arch/powerpc/boot/dts/bamboo.dts | 142 +++++++++--------- arch/powerpc/boot/dts/canyonlands.dts | 222 ++++++++++++++-------------- arch/powerpc/boot/dts/ebony.dts | 164 ++++++++++----------- arch/powerpc/boot/dts/ep405.dts | 100 ++++++------- arch/powerpc/boot/dts/glacier.dts | 262 +++++++++++++++++----------------- arch/powerpc/boot/dts/haleakala.dts | 136 +++++++++--------- arch/powerpc/boot/dts/holly.dts | 122 ++++++++-------- arch/powerpc/boot/dts/katmai.dts | 210 +++++++++++++-------------- arch/powerpc/boot/dts/kilauea.dts | 182 +++++++++++------------ arch/powerpc/boot/dts/makalu.dts | 182 +++++++++++------------ arch/powerpc/boot/dts/ps3.dts | 16 ++- arch/powerpc/boot/dts/rainier.dts | 162 ++++++++++----------- arch/powerpc/boot/dts/sequoia.dts | 172 +++++++++++----------- arch/powerpc/boot/dts/taishan.dts | 212 +++++++++++++-------------- arch/powerpc/boot/dts/walnut.dts | 118 +++++++-------- arch/powerpc/boot/dts/warp.dts | 106 +++++++------- arch/powerpc/boot/dts/yosemite.dts | 146 +++++++++---------- 17 files changed, 1344 insertions(+), 1310 deletions(-) (limited to 'arch/powerpc/boot') diff --git a/arch/powerpc/boot/dts/bamboo.dts b/arch/powerpc/boot/dts/bamboo.dts index ba2521b..6ce0cc2 100644 --- a/arch/powerpc/boot/dts/bamboo.dts +++ b/arch/powerpc/boot/dts/bamboo.dts @@ -11,12 +11,14 @@ * any warranty of any kind, whether express or implied. */ +/dts-v1/; + / { #address-cells = <2>; #size-cells = <1>; model = "amcc,bamboo"; compatible = "amcc,bamboo"; - dcr-parent = <&/cpus/cpu@0>; + dcr-parent = <&{/cpus/cpu@0}>; aliases { ethernet0 = &EMAC0; @@ -34,13 +36,13 @@ cpu@0 { device_type = "cpu"; model = "PowerPC,440EP"; - reg = <0>; + reg = <0x00000000>; clock-frequency = <0>; /* Filled in by zImage */ timebase-frequency = <0>; /* Filled in by zImage */ - i-cache-line-size = <20>; - d-cache-line-size = <20>; - i-cache-size = <8000>; - d-cache-size = <8000>; + i-cache-line-size = <32>; + d-cache-line-size = <32>; + i-cache-size = <32768>; + d-cache-size = <32768>; dcr-controller; dcr-access-method = "native"; }; @@ -48,14 +50,14 @@ memory { device_type = "memory"; - reg = <0 0 0>; /* Filled in by zImage */ + reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by zImage */ }; UIC0: interrupt-controller0 { compatible = "ibm,uic-440ep","ibm,uic"; interrupt-controller; cell-index = <0>; - dcr-reg = <0c0 009>; + dcr-reg = <0x0c0 0x009>; #address-cells = <0>; #size-cells = <0>; #interrupt-cells = <2>; @@ -65,22 +67,22 @@ compatible = "ibm,uic-440ep","ibm,uic"; interrupt-controller; cell-index = <1>; - dcr-reg = <0d0 009>; + dcr-reg = <0x0d0 0x009>; #address-cells = <0>; #size-cells = <0>; #interrupt-cells = <2>; - interrupts = <1e 4 1f 4>; /* cascade */ + interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */ interrupt-parent = <&UIC0>; }; SDR0: sdr { compatible = "ibm,sdr-440ep"; - dcr-reg = <00e 002>; + dcr-reg = <0x00e 0x002>; }; CPR0: cpr { compatible = "ibm,cpr-440ep"; - dcr-reg = <00c 002>; + dcr-reg = <0x00c 0x002>; }; plb { @@ -92,29 +94,29 @@ SDRAM0: sdram { compatible = "ibm,sdram-440ep", "ibm,sdram-405gp"; - dcr-reg = <010 2>; + dcr-reg = <0x010 0x002>; }; DMA0: dma { compatible = "ibm,dma-440ep", "ibm,dma-440gp"; - dcr-reg = <100 027>; + dcr-reg = <0x100 0x027>; }; MAL0: mcmal { compatible = "ibm,mcmal-440ep", "ibm,mcmal-440gp", "ibm,mcmal"; - dcr-reg = <180 62>; + dcr-reg = <0x180 0x062>; num-tx-chans = <4>; num-rx-chans = <2>; interrupt-parent = <&MAL0>; - interrupts = <0 1 2 3 4>; + interrupts = <0x0 0x1 0x2 0x3 0x4>; #interrupt-cells = <1>; #address-cells = <0>; #size-cells = <0>; - interrupt-map = ; + interrupt-map = ; }; POB0: opb { @@ -124,101 +126,101 @@ /* Bamboo is oddball in the 44x world and doesn't use the ERPN * bits. */ - ranges = <00000000 0 00000000 80000000 - 80000000 0 80000000 80000000>; + ranges = <0x00000000 0x00000000 0x00000000 0x80000000 + 0x80000000 0x00000000 0x80000000 0x80000000>; interrupt-parent = <&UIC1>; - interrupts = <7 4>; + interrupts = <0x7 0x4>; clock-frequency = <0>; /* Filled in by zImage */ EBC0: ebc { compatible = "ibm,ebc-440ep", "ibm,ebc-440gp", "ibm,ebc"; - dcr-reg = <012 2>; + dcr-reg = <0x012 0x002>; #address-cells = <2>; #size-cells = <1>; clock-frequency = <0>; /* Filled in by zImage */ - interrupts = <5 1>; + interrupts = <0x5 0x1>; interrupt-parent = <&UIC1>; }; UART0: serial@ef600300 { device_type = "serial"; compatible = "ns16550"; - reg = ; - virtual-reg = ; + reg = <0xef600300 0x00000008>; + virtual-reg = <0xef600300>; clock-frequency = <0>; /* Filled in by zImage */ - current-speed = <1c200>; + current-speed = <115200>; interrupt-parent = <&UIC0>; - interrupts = <0 4>; + interrupts = <0x0 0x4>; }; UART1: serial@ef600400 { device_type = "serial"; compatible = "ns16550"; - reg = ; - virtual-reg = ; + reg = <0xef600400 0x00000008>; + virtual-reg = <0xef600400>; clock-frequency = <0>; current-speed = <0>; interrupt-parent = <&UIC0>; - interrupts = <1 4>; + interrupts = <0x1 0x4>; }; UART2: serial@ef600500 { device_type = "serial"; compatible = "ns16550"; - reg = ; - virtual-reg = ; + reg = <0xef600500 0x00000008>; + virtual-reg = <0xef600500>; clock-frequency = <0>; current-speed = <0>; interrupt-parent = <&UIC0>; - interrupts = <3 4>; + interrupts = <0x3 0x4>; }; UART3: serial@ef600600 { device_type = "serial"; compatible = "ns16550"; - reg = ; - virtual-reg = ; + reg = <0xef600600 0x00000008>; + virtual-reg = <0xef600600>; clock-frequency = <0>; current-speed = <0>; interrupt-parent = <&UIC0>; - interrupts = <4 4>; + interrupts = <0x4 0x4>; }; IIC0: i2c@ef600700 { compatible = "ibm,iic-440ep", "ibm,iic-440gp", "ibm,iic"; - reg = ; + reg = <0xef600700 0x00000014>; interrupt-parent = <&UIC0>; - interrupts = <2 4>; + interrupts = <0x2 0x4>; }; IIC1: i2c@ef600800 { compatible = "ibm,iic-440ep", "ibm,iic-440gp", "ibm,iic"; - reg = ; + reg = <0xef600800 0x00000014>; interrupt-parent = <&UIC0>; - interrupts = <7 4>; + interrupts = <0x7 0x4>; }; ZMII0: emac-zmii@ef600d00 { compatible = "ibm,zmii-440ep", "ibm,zmii-440gp", "ibm,zmii"; - reg = ; + reg = <0xef600d00 0x0000000c>; }; EMAC0: ethernet@ef600e00 { device_type = "network"; compatible = "ibm,emac-440ep", "ibm,emac-440gp", "ibm,emac"; interrupt-parent = <&UIC1>; - interrupts = <1c 4 1d 4>; - reg = ; + interrupts = <0x1c 0x4 0x1d 0x4>; + reg = <0xef600e00 0x00000070>; local-mac-address = [000000000000]; mal-device = <&MAL0>; mal-tx-channel = <0 1>; mal-rx-channel = <0>; cell-index = <0>; - max-frame-size = <5dc>; - rx-fifo-size = <1000>; - tx-fifo-size = <800>; + max-frame-size = <1500>; + rx-fifo-size = <4096>; + tx-fifo-size = <2048>; phy-mode = "rmii"; - phy-map = <00000000>; + phy-map = <0x00000000>; zmii-device = <&ZMII0>; zmii-channel = <0>; }; @@ -227,26 +229,26 @@ device_type = "network"; compatible = "ibm,emac-440ep", "ibm,emac-440gp", "ibm,emac"; interrupt-parent = <&UIC1>; - interrupts = <1e 4 1f 4>; - reg = ; + interrupts = <0x1e 0x4 0x1f 0x4>; + reg = <0xef600f00 0x00000070>; local-mac-address = [000000000000]; mal-device = <&MAL0>; mal-tx-channel = <2 3>; mal-rx-channel = <1>; cell-index = <1>; - max-frame-size = <5dc>; - rx-fifo-size = <1000>; - tx-fifo-size = <800>; + max-frame-size = <1500>; + rx-fifo-size = <4096>; + tx-fifo-size = <2048>; phy-mode = "rmii"; - phy-map = <00000000>; + phy-map = <0x00000000>; zmii-device = <&ZMII0>; zmii-channel = <1>; }; usb@ef601000 { compatible = "ohci-be"; - reg = ; - interrupts = <8 1 9 1>; + reg = <0xef601000 0x00000080>; + interrupts = <0x8 0x1 0x9 0x1>; interrupt-parent = < &UIC1 >; }; }; @@ -258,35 +260,35 @@ #address-cells = <3>; compatible = "ibm,plb440ep-pci", "ibm,plb-pci"; primary; - reg = <0 eec00000 8 /* Config space access */ - 0 eed00000 4 /* IACK */ - 0 eed00000 4 /* Special cycle */ - 0 ef400000 40>; /* Internal registers */ + reg = <0x00000000 0xeec00000 0x00000008 /* Config space access */ + 0x00000000 0xeed00000 0x00000004 /* IACK */ + 0x00000000 0xeed00000 0x00000004 /* Special cycle */ + 0x00000000 0xef400000 0x00000040>; /* Internal registers */ /* Outbound ranges, one memory and one IO, * later cannot be changed. Chip supports a second * IO range but we don't use it for now */ - ranges = <02000000 0 a0000000 0 a0000000 0 20000000 - 01000000 0 00000000 0 e8000000 0 00010000>; + ranges = <0x02000000 0x00000000 0xa0000000 0x00000000 0xa0000000 0x00000000 0x20000000 + 0x01000000 0x00000000 0x00000000 0x00000000 0xe8000000 0x00000000 0x00010000>; /* Inbound 2GB range starting at 0 */ - dma-ranges = <42000000 0 0 0 0 0 80000000>; + dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>; /* Bamboo has all 4 IRQ pins tied together per slot */ - interrupt-map-mask = ; + interrupt-map-mask = <0xf800 0x0 0x0 0x0>; interrupt-map = < /* IDSEL 1 */ - 0800 0 0 0 &UIC0 1c 8 + 0x800 0x0 0x0 0x0 &UIC0 0x1c 0x8 /* IDSEL 2 */ - 1000 0 0 0 &UIC0 1b 8 + 0x1000 0x0 0x0 0x0 &UIC0 0x1b 0x8 /* IDSEL 3 */ - 1800 0 0 0 &UIC0 1a 8 + 0x1800 0x0 0x0 0x0 &UIC0 0x1a 0x8 /* IDSEL 4 */ - 2000 0 0 0 &UIC0 19 8 + 0x2000 0x0 0x0 0x0 &UIC0 0x19 0x8 >; }; }; diff --git a/arch/powerpc/boot/dts/canyonlands.dts b/arch/powerpc/boot/dts/canyonlands.dts index 3963412..f9fe032 100644 --- a/arch/powerpc/boot/dts/canyonlands.dts +++ b/arch/powerpc/boot/dts/canyonlands.dts @@ -8,12 +8,14 @@ * any warranty of any kind, whether express or implied. */ +/dts-v1/; + / { #address-cells = <2>; #size-cells = <1>; model = "amcc,canyonlands"; compatible = "amcc,canyonlands"; - dcr-parent = <&/cpus/cpu@0>; + dcr-parent = <&{/cpus/cpu@0}>; aliases { ethernet0 = &EMAC0; @@ -29,13 +31,13 @@ cpu@0 { device_type = "cpu"; model = "PowerPC,460EX"; - reg = <0>; + reg = <0x00000000>; clock-frequency = <0>; /* Filled in by U-Boot */ timebase-frequency = <0>; /* Filled in by U-Boot */ - i-cache-line-size = <20>; - d-cache-line-size = <20>; - i-cache-size = <8000>; - d-cache-size = <8000>; + i-cache-line-size = <32>; + d-cache-line-size = <32>; + i-cache-size = <32768>; + d-cache-size = <32768>; dcr-controller; dcr-access-method = "native"; }; @@ -43,14 +45,14 @@ memory { device_type = "memory"; - reg = <0 0 0>; /* Filled in by U-Boot */ + reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by U-Boot */ }; UIC0: interrupt-controller0 { compatible = "ibm,uic-460ex","ibm,uic"; interrupt-controller; cell-index = <0>; - dcr-reg = <0c0 009>; + dcr-reg = <0x0c0 0x009>; #address-cells = <0>; #size-cells = <0>; #interrupt-cells = <2>; @@ -60,11 +62,11 @@ compatible = "ibm,uic-460ex","ibm,uic"; interrupt-controller; cell-index = <1>; - dcr-reg = <0d0 009>; + dcr-reg = <0x0d0 0x009>; #address-cells = <0>; #size-cells = <0>; #interrupt-cells = <2>; - interrupts = <1e 4 1f 4>; /* cascade */ + interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */ interrupt-parent = <&UIC0>; }; @@ -72,11 +74,11 @@ compatible = "ibm,uic-460ex","ibm,uic"; interrupt-controller; cell-index = <2>; - dcr-reg = <0e0 009>; + dcr-reg = <0x0e0 0x009>; #address-cells = <0>; #size-cells = <0>; #interrupt-cells = <2>; - interrupts = ; /* cascade */ + interrupts = <0xa 0x4 0xb 0x4>; /* cascade */ interrupt-parent = <&UIC0>; }; @@ -84,22 +86,22 @@ compatible = "ibm,uic-460ex","ibm,uic"; interrupt-controller; cell-index = <3>; - dcr-reg = <0f0 009>; + dcr-reg = <0x0f0 0x009>; #address-cells = <0>; #size-cells = <0>; #interrupt-cells = <2>; - interrupts = <10 4 11 4>; /* cascade */ + interrupts = <0x10 0x4 0x11 0x4>; /* cascade */ interrupt-parent = <&UIC0>; }; SDR0: sdr { compatible = "ibm,sdr-460ex"; - dcr-reg = <00e 002>; + dcr-reg = <0x00e 0x002>; }; CPR0: cpr { compatible = "ibm,cpr-460ex"; - dcr-reg = <00c 002>; + dcr-reg = <0x00c 0x002>; }; plb { @@ -111,74 +113,74 @@ SDRAM0: sdram { compatible = "ibm,sdram-460ex", "ibm,sdram-405gp"; - dcr-reg = <010 2>; + dcr-reg = <0x010 0x002>; }; MAL0: mcmal { compatible = "ibm,mcmal-460ex", "ibm,mcmal2"; - dcr-reg = <180 62>; + dcr-reg = <0x180 0x062>; num-tx-chans = <2>; - num-rx-chans = <10>; + num-rx-chans = <16>; #address-cells = <0>; #size-cells = <0>; interrupt-parent = <&UIC2>; - interrupts = < /*TXEOB*/ 6 4 - /*RXEOB*/ 7 4 - /*SERR*/ 3 4 - /*TXDE*/ 4 4 - /*RXDE*/ 5 4>; + interrupts = < /*TXEOB*/ 0x6 0x4 + /*RXEOB*/ 0x7 0x4 + /*SERR*/ 0x3 0x4 + /*TXDE*/ 0x4 0x4 + /*RXDE*/ 0x5 0x4>; }; POB0: opb { compatible = "ibm,opb-460ex", "ibm,opb"; #address-cells = <1>; #size-cells = <1>; - ranges = ; + ranges = <0xb0000000 0x00000004 0xb0000000 0x50000000>; clock-frequency = <0>; /* Filled in by U-Boot */ EBC0: ebc { compatible = "ibm,ebc-460ex", "ibm,ebc"; - dcr-reg = <012 2>; + dcr-reg = <0x012 0x002>; #address-cells = <2>; #size-cells = <1>; clock-frequency = <0>; /* Filled in by U-Boot */ /* ranges property is supplied by U-Boot */ - interrupts = <6 4>; + interrupts = <0x6 0x4>; interrupt-parent = <&UIC1>; nor_flash@0,0 { compatible = "amd,s29gl512n", "cfi-flash"; bank-width = <2>; - reg = <0 000000 4000000>; + reg = <0x00000000 0x00000000 0x04000000>; #address-cells = <1>; #size-cells = <1>; partition@0 { label = "kernel"; - reg = <0 1e0000>; + reg = <0x00000000 0x001e0000>; }; partition@1e0000 { label = "dtb"; - reg = <1e0000 20000>; + reg = <0x001e0000 0x00020000>; }; partition@200000 { label = "ramdisk"; - reg = <200000 1400000>; + reg = <0x00200000 0x01400000>; }; partition@1600000 { label = "jffs2"; - reg = <1600000 400000>; + reg = <0x01600000 0x00400000>; }; partition@1a00000 { label = "user"; - reg = <1a00000 2560000>; + reg = <0x01a00000 0x02560000>; }; partition@3f60000 { label = "env"; - reg = <3f60000 40000>; + reg = <0x03f60000 0x00040000>; }; partition@3fa0000 { label = "u-boot"; - reg = <3fa0000 60000>; + reg = <0x03fa0000 0x00060000>; }; }; }; @@ -186,103 +188,103 @@ UART0: serial@ef600300 { device_type = "serial"; compatible = "ns16550"; - reg = ; - virtual-reg = ; + reg = <0xef600300 0x00000008>; + virtual-reg = <0xef600300>; clock-frequency = <0>; /* Filled in by U-Boot */ current-speed = <0>; /* Filled in by U-Boot */ interrupt-parent = <&UIC1>; - interrupts = <1 4>; + interrupts = <0x1 0x4>; }; UART1: serial@ef600400 { device_type = "serial"; compatible = "ns16550"; - reg = ; - virtual-reg = ; + reg = <0xef600400 0x00000008>; + virtual-reg = <0xef600400>; clock-frequency = <0>; /* Filled in by U-Boot */ current-speed = <0>; /* Filled in by U-Boot */ interrupt-parent = <&UIC0>; - interrupts = <1 4>; + interrupts = <0x1 0x4>; }; UART2: serial@ef600500 { device_type = "serial"; compatible = "ns16550"; - reg = ; - virtual-reg = ; + reg = <0xef600500 0x00000008>; + virtual-reg = <0xef600500>; clock-frequency = <0>; /* Filled in by U-Boot */ current-speed = <0>; /* Filled in by U-Boot */ interrupt-parent = <&UIC1>; - interrupts = <1d 4>; + interrupts = <0x1d 0x4>; }; UART3: serial@ef600600 { device_type = "serial"; compatible = "ns16550"; - reg = ; - virtual-reg = ; + reg = <0xef600600 0x00000008>; + virtual-reg = <0xef600600>; clock-frequency = <0>; /* Filled in by U-Boot */ current-speed = <0>; /* Filled in by U-Boot */ interrupt-parent = <&UIC1>; - interrupts = <1e 4>; + interrupts = <0x1e 0x4>; }; IIC0: i2c@ef600700 { compatible = "ibm,iic-460ex", "ibm,iic"; - reg = ; + reg = <0xef600700 0x00000014>; interrupt-parent = <&UIC0>; - interrupts = <2 4>; + interrupts = <0x2 0x4>; }; IIC1: i2c@ef600800 { compatible = "ibm,iic-460ex", "ibm,iic"; - reg = ; + reg = <0xef600800 0x00000014>; interrupt-parent = <&UIC0>; - interrupts = <3 4>; + interrupts = <0x3 0x4>; }; ZMII0: emac-zmii@ef600d00 { compatible = "ibm,zmii-460ex", "ibm,zmii"; - reg = ; + reg = <0xef600d00 0x0000000c>; }; RGMII0: emac-rgmii@ef601500 { compatible = "ibm,rgmii-460ex", "ibm,rgmii"; - reg = ; + reg = <0xef601500 0x00000008>; has-mdio; }; TAH0: emac-tah@ef601350 { compatible = "ibm,tah-460ex", "ibm,tah"; - reg = ; + reg = <0xef601350 0x00000030>; }; TAH1: emac-tah@ef601450 { compatible = "ibm,tah-460ex", "ibm,tah"; - reg = ; + reg = <0xef601450 0x00000030>; }; EMAC0: ethernet@ef600e00 { device_type = "network"; compatible = "ibm,emac-460ex", "ibm,emac4"; interrupt-parent = <&EMAC0>; - interrupts = <0 1>; + interrupts = <0x0 0x1>; #interrupt-cells = <1>; #address-cells = <0>; #size-cells = <0>; - interrupt-map = ; - reg = ; + interrupt-map = ; + reg = <0xef600e00 0x00000070>; local-mac-address = [000000000000]; /* Filled in by U-Boot */ mal-device = <&MAL0>; mal-tx-channel = <0>; mal-rx-channel = <0>; cell-index = <0>; - max-frame-size = <2328>; - rx-fifo-size = <1000>; - tx-fifo-size = <800>; + max-frame-size = <9000>; + rx-fifo-size = <4096>; + tx-fifo-size = <2048>; phy-mode = "rgmii"; - phy-map = <00000000>; + phy-map = <0x00000000>; rgmii-device = <&RGMII0>; rgmii-channel = <0>; tah-device = <&TAH0>; @@ -295,23 +297,23 @@ device_type = "network"; compatible = "ibm,emac-460ex", "ibm,emac4"; interrupt-parent = <&EMAC1>; - interrupts = <0 1>; + interrupts = <0x0 0x1>; #interrupt-cells = <1>; #address-cells = <0>; #size-cells = <0>; - interrupt-map = ; - reg = ; + interrupt-map = ; + reg = <0xef600f00 0x00000070>; local-mac-address = [000000000000]; /* Filled in by U-Boot */ mal-device = <&MAL0>; mal-tx-channel = <1>; mal-rx-channel = <8>; cell-index = <1>; - max-frame-size = <2328>; - rx-fifo-size = <1000>; - tx-fifo-size = <800>; + max-frame-size = <9000>; + rx-fifo-size = <4096>; + tx-fifo-size = <2048>; phy-mode = "rgmii"; - phy-map = <00000000>; + phy-map = <0x00000000>; rgmii-device = <&RGMII0>; rgmii-channel = <1>; tah-device = <&TAH1>; @@ -331,27 +333,27 @@ primary; large-inbound-windows; enable-msi-hole; - reg = ; /* Internal messaging registers */ + reg = <0x0000000c 0x0ec00000 0x00000008 /* Config space access */ + 0x00000000 0x00000000 0x00000000 /* no IACK cycles */ + 0x0000000c 0x0ed00000 0x00000004 /* Special cycles */ + 0x0000000c 0x0ec80000 0x00000100 /* Internal registers */ + 0x0000000c 0x0ec80100 0x000000fc>; /* Internal messaging registers */ /* Outbound ranges, one memory and one IO, * later cannot be changed */ - ranges = <02000000 0 80000000 0000000d 80000000 0 80000000 - 01000000 0 00000000 0000000c 08000000 0 00010000>; + ranges = <0x02000000 0x00000000 0x80000000 0x0000000d 0x80000000 0x00000000 0x80000000 + 0x01000000 0x00000000 0x00000000 0x0000000c 0x08000000 0x00000000 0x00010000>; /* Inbound 2GB range starting at 0 */ - dma-ranges = <42000000 0 0 0 0 0 80000000>; + dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>; /* This drives busses 0 to 0x3f */ - bus-range = <0 3f>; + bus-range = <0x0 0x3f>; /* All PCI interrupts are routed to ext IRQ 2 -> UIC1-0 */ - interrupt-map-mask = <0000 0 0 0>; - interrupt-map = < 0000 0 0 0 &UIC1 0 8 >; + interrupt-map-mask = <0x0 0x0 0x0 0x0>; + interrupt-map = < 0x0 0x0 0x0 0x0 &UIC1 0x0 0x8 >; }; PCIE0: pciex@d00000000 { @@ -361,23 +363,23 @@ #address-cells = <3>; compatible = "ibm,plb-pciex-460ex", "ibm,plb-pciex"; primary; - port = <0>; /* port number */ - reg = ; /* Registers */ - dcr-reg = <100 020>; - sdr-base = <300>; + port = <0x0>; /* port number */ + reg = <0x0000000d 0x00000000 0x20000000 /* Config space access */ + 0x0000000c 0x08010000 0x00001000>; /* Registers */ + dcr-reg = <0x100 0x020>; + sdr-base = <0x300>; /* Outbound ranges, one memory and one IO, * later cannot be changed */ - ranges = <02000000 0 80000000 0000000e 00000000 0 80000000 - 01000000 0 00000000 0000000f 80000000 0 00010000>; + ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x00000000 0x00000000 0x80000000 + 0x01000000 0x00000000 0x00000000 0x0000000f 0x80000000 0x00000000 0x00010000>; /* Inbound 2GB range starting at 0 */ - dma-ranges = <42000000 0 0 0 0 0 80000000>; + dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>; /* This drives busses 40 to 0x7f */ - bus-range = <40 7f>; + bus-range = <0x40 0x7f>; /* Legacy interrupts (note the weird polarity, the bridge seems * to invert PCIe legacy interrupts). @@ -387,12 +389,12 @@ * below are basically de-swizzled numbers. * The real slot is on idsel 0, so the swizzling is 1:1 */ - interrupt-map-mask = <0000 0 0 7>; + interrupt-map-mask = <0x0 0x0 0x0 0x7>; interrupt-map = < - 0000 0 0 1 &UIC3 c 4 /* swizzled int A */ - 0000 0 0 2 &UIC3 d 4 /* swizzled int B */ - 0000 0 0 3 &UIC3 e 4 /* swizzled int C */ - 0000 0 0 4 &UIC3 f 4 /* swizzled int D */>; + 0x0 0x0 0x0 0x1 &UIC3 0xc 0x4 /* swizzled int A */ + 0x0 0x0 0x0 0x2 &UIC3 0xd 0x4 /* swizzled int B */ + 0x0 0x0 0x0 0x3 &UIC3 0xe 0x4 /* swizzled int C */ + 0x0 0x0 0x0 0x4 &UIC3 0xf 0x4 /* swizzled int D */>; }; PCIE1: pciex@d20000000 { @@ -402,23 +404,23 @@ #address-cells = <3>; compatible = "ibm,plb-pciex-460ex", "ibm,plb-pciex"; primary; - port = <1>; /* port number */ - reg = ; /* Registers */ - dcr-reg = <120 020>; - sdr-base = <340>; + port = <0x1>; /* port number */ + reg = <0x0000000d 0x20000000 0x20000000 /* Config space access */ + 0x0000000c 0x08011000 0x00001000>; /* Registers */ + dcr-reg = <0x120 0x020>; + sdr-base = <0x340>; /* Outbound ranges, one memory and one IO, * later cannot be changed */ - ranges = <02000000 0 80000000 0000000e 80000000 0 80000000 - 01000000 0 00000000 0000000f 80010000 0 00010000>; + ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x80000000 0x00000000 0x80000000 + 0x01000000 0x00000000 0x00000000 0x0000000f 0x80010000 0x00000000 0x00010000>; /* Inbound 2GB range starting at 0 */ - dma-ranges = <42000000 0 0 0 0 0 80000000>; + dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>; /* This drives busses 80 to 0xbf */ - bus-range = <80 bf>; + bus-range = <0x80 0xbf>; /* Legacy interrupts (note the weird polarity, the bridge seems * to invert PCIe legacy interrupts). @@ -428,12 +430,12 @@ * below are basically de-swizzled numbers. * The real slot is on idsel 0, so the swizzling is 1:1 */ - interrupt-map-mask = <0000 0 0 7>; + interrupt-map-mask = <0x0 0x0 0x0 0x7>; interrupt-map = < - 0000 0 0 1 &UIC3 10 4 /* swizzled int A */ - 0000 0 0 2 &UIC3 11 4 /* swizzled int B */ - 0000 0 0 3 &UIC3 12 4 /* swizzled int C */ - 0000 0 0 4 &UIC3 13 4 /* swizzled int D */>; + 0x0 0x0 0x0 0x1 &UIC3 0x10 0x4 /* swizzled int A */ + 0x0 0x0 0x0 0x2 &UIC3 0x11 0x4 /* swizzled int B */ + 0x0 0x0 0x0 0x3 &UIC3 0x12 0x4 /* swizzled int C */ + 0x0 0x0 0x0 0x4 &UIC3 0x13 0x4 /* swizzled int D */>; }; }; }; diff --git a/arch/powerpc/boot/dts/ebony.dts b/arch/powerpc/boot/dts/ebony.dts index 5079dc8..ec2d142 100644 --- a/arch/powerpc/boot/dts/ebony.dts +++ b/arch/powerpc/boot/dts/ebony.dts @@ -11,12 +11,14 @@ * any warranty of any kind, whether express or implied. */ +/dts-v1/; + / { #address-cells = <2>; #size-cells = <1>; model = "ibm,ebony"; compatible = "ibm,ebony"; - dcr-parent = <&/cpus/cpu@0>; + dcr-parent = <&{/cpus/cpu@0}>; aliases { ethernet0 = &EMAC0; @@ -32,13 +34,13 @@ cpu@0 { device_type = "cpu"; model = "PowerPC,440GP"; - reg = <0>; + reg = <0x00000000>; clock-frequency = <0>; // Filled in by zImage timebase-frequency = <0>; // Filled in by zImage - i-cache-line-size = <20>; - d-cache-line-size = <20>; - i-cache-size = <8000>; /* 32 kB */ - d-cache-size = <8000>; /* 32 kB */ + i-cache-line-size = <32>; + d-cache-line-size = <32>; + i-cache-size = <32768>; /* 32 kB */ + d-cache-size = <32768>; /* 32 kB */ dcr-controller; dcr-access-method = "native"; }; @@ -46,14 +48,14 @@ memory { device_type = "memory"; - reg = <0 0 0>; // Filled in by zImage + reg = <0x00000000 0x00000000 0x00000000>; // Filled in by zImage }; UIC0: interrupt-controller0 { compatible = "ibm,uic-440gp", "ibm,uic"; interrupt-controller; cell-index = <0>; - dcr-reg = <0c0 009>; + dcr-reg = <0x0c0 0x009>; #address-cells = <0>; #size-cells = <0>; #interrupt-cells = <2>; @@ -64,17 +66,17 @@ compatible = "ibm,uic-440gp", "ibm,uic"; interrupt-controller; cell-index = <1>; - dcr-reg = <0d0 009>; + dcr-reg = <0x0d0 0x009>; #address-cells = <0>; #size-cells = <0>; #interrupt-cells = <2>; - interrupts = <1e 4 1f 4>; /* cascade */ + interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */ interrupt-parent = <&UIC0>; }; CPC0: cpc { compatible = "ibm,cpc-440gp"; - dcr-reg = <0b0 003 0e0 010>; + dcr-reg = <0x0b0 0x003 0x0e0 0x010>; // FIXME: anything else? }; @@ -87,37 +89,37 @@ SDRAM0: memory-controller { compatible = "ibm,sdram-440gp"; - dcr-reg = <010 2>; + dcr-reg = <0x010 0x002>; // FIXME: anything else? }; SRAM0: sram { compatible = "ibm,sram-440gp"; - dcr-reg = <020 8 00a 1>; + dcr-reg = <0x020 0x008 0x00a 0x001>; }; DMA0: dma { // FIXME: ??? compatible = "ibm,dma-440gp"; - dcr-reg = <100 027>; + dcr-reg = <0x100 0x027>; }; MAL0: mcmal { compatible = "ibm,mcmal-440gp", "ibm,mcmal"; - dcr-reg = <180 62>; + dcr-reg = <0x180 0x062>; num-tx-chans = <4>; num-rx-chans = <4>; interrupt-parent = <&MAL0>; - interrupts = <0 1 2 3 4>; + interrupts = <0x0 0x1 0x2 0x3 0x4>; #interrupt-cells = <1>; #address-cells = <0>; #size-cells = <0>; - interrupt-map = ; - interrupt-map-mask = ; + interrupt-map = ; + interrupt-map-mask = <0xffffffff>; }; POB0: opb { @@ -126,34 +128,34 @@ #size-cells = <1>; /* Wish there was a nicer way of specifying a full 32-bit range */ - ranges = <00000000 1 00000000 80000000 - 80000000 1 80000000 80000000>; - dcr-reg = <090 00b>; + ranges = <0x00000000 0x00000001 0x00000000 0x80000000 + 0x80000000 0x00000001 0x80000000 0x80000000>; + dcr-reg = <0x090 0x00b>; interrupt-parent = <&UIC1>; - interrupts = <7 4>; + interrupts = <0x7 0x4>; clock-frequency = <0>; // Filled in by zImage EBC0: ebc { compatible = "ibm,ebc-440gp", "ibm,ebc"; - dcr-reg = <012 2>; + dcr-reg = <0x012 0x002>; #address-cells = <2>; #size-cells = <1>; clock-frequency = <0>; // Filled in by zImage // ranges property is supplied by zImage // based on firmware's configuration of the // EBC bridge - interrupts = <5 4>; + interrupts = <0x5 0x4>; interrupt-parent = <&UIC1>; small-flash@0,80000 { compatible = "jedec-flash"; bank-width = <1>; - reg = <0 80000 80000>; + reg = <0x00000000 0x00080000 0x00080000>; #address-cells = <1>; #size-cells = <1>; partition@0 { label = "OpenBIOS"; - reg = <0 80000>; + reg = <0x00000000 0x00080000>; read-only; }; }; @@ -161,101 +163,101 @@ nvram@1,0 { /* NVRAM & RTC */ compatible = "ds1743-nvram"; - #bytes = <2000>; - reg = <1 0 2000>; + #bytes = <0x2000>; + reg = <0x00000001 0x00000000 0x00002000>; }; large-flash@2,0 { compatible = "jedec-flash"; bank-width = <1>; - reg = <2 0 400000>; + reg = <0x00000002 0x00000000 0x00400000>; #address-cells = <1>; #size-cells = <1>; partition@0 { label = "fs"; - reg = <0 380000>; + reg = <0x00000000 0x00380000>; }; partition@380000 { label = "firmware"; - reg = <380000 80000>; + reg = <0x00380000 0x00080000>; }; }; ir@3,0 { - reg = <3 0 10>; + reg = <0x00000003 0x00000000 0x00000010>; }; fpga@7,0 { compatible = "Ebony-FPGA"; - reg = <7 0 10>; - virtual-reg = ; + reg = <0x00000007 0x00000000 0x00000010>; + virtual-reg = <0xe8300000>; }; }; UART0: serial@40000200 { device_type = "serial"; compatible = "ns16550"; - reg = <40000200 8>; - virtual-reg = ; - clock-frequency = ; - current-speed = <2580>; + reg = <0x40000200 0x00000008>; + virtual-reg = <0xe0000200>; + clock-frequency = <11059200>; + current-speed = <9600>; interrupt-parent = <&UIC0>; - interrupts = <0 4>; + interrupts = <0x0 0x4>; }; UART1: serial@40000300 { device_type = "serial"; compatible = "ns16550"; - reg = <40000300 8>; - virtual-reg = ; - clock-frequency = ; - current-speed = <2580>; + reg = <0x40000300 0x00000008>; + virtual-reg = <0xe0000300>; + clock-frequency = <11059200>; + current-speed = <9600>; interrupt-parent = <&UIC0>; - interrupts = <1 4>; + interrupts = <0x1 0x4>; }; IIC0: i2c@40000400 { /* FIXME */ compatible = "ibm,iic-440gp", "ibm,iic"; - reg = <40000400 14>; + reg = <0x40000400 0x00000014>; interrupt-parent = <&UIC0>; - interrupts = <2 4>; + interrupts = <0x2 0x4>; }; IIC1: i2c@40000500 { /* FIXME */ compatible = "ibm,iic-440gp", "ibm,iic"; - reg = <40000500 14>; + reg = <0x40000500 0x00000014>; interrupt-parent = <&UIC0>; - interrupts = <3 4>; + interrupts = <0x3 0x4>; }; GPIO0: gpio@40000700 { /* FIXME */ compatible = "ibm,gpio-440gp"; - reg = <40000700 20>; + reg = <0x40000700 0x00000020>; }; ZMII0: emac-zmii@40000780 { compatible = "ibm,zmii-440gp", "ibm,zmii"; - reg = <40000780 c>; + reg = <0x40000780 0x0000000c>; }; EMAC0: ethernet@40000800 { device_type = "network"; compatible = "ibm,emac-440gp", "ibm,emac"; interrupt-parent = <&UIC1>; - interrupts = <1c 4 1d 4>; - reg = <40000800 70>; + interrupts = <0x1c 0x4 0x1d 0x4>; + reg = <0x40000800 0x00000070>; local-mac-address = [000000000000]; // Filled in by zImage mal-device = <&MAL0>; mal-tx-channel = <0 1>; mal-rx-channel = <0>; cell-index = <0>; - max-frame-size = <5dc>; - rx-fifo-size = <1000>; - tx-fifo-size = <800>; + max-frame-size = <1500>; + rx-fifo-size = <4096>; + tx-fifo-size = <2048>; phy-mode = "rmii"; - phy-map = <00000001>; + phy-map = <0x00000001>; zmii-device = <&ZMII0>; zmii-channel = <0>; }; @@ -263,18 +265,18 @@ device_type = "network"; compatible = "ibm,emac-440gp", "ibm,emac"; interrupt-parent = <&UIC1>; - interrupts = <1e 4 1f 4>; - reg = <40000900 70>; + interrupts = <0x1e 0x4 0x1f 0x4>; + reg = <0x40000900 0x00000070>; local-mac-address = [000000000000]; // Filled in by zImage mal-device = <&MAL0>; mal-tx-channel = <2 3>; mal-rx-channel = <1>; cell-index = <1>; - max-frame-size = <5dc>; - rx-fifo-size = <1000>; - tx-fifo-size = <800>; + max-frame-size = <1500>; + rx-fifo-size = <4096>; + tx-fifo-size = <2048>; phy-mode = "rmii"; - phy-map = <00000001>; + phy-map = <0x00000001>; zmii-device = <&ZMII0>; zmii-channel = <1>; }; @@ -282,9 +284,9 @@ GPT0: gpt@40000a00 { /* FIXME */ - reg = <40000a00 d4>; + reg = <0x40000a00 0x000000d4>; interrupt-parent = <&UIC0>; - interrupts = <12 4 13 4 14 4 15 4 16 4>; + interrupts = <0x12 0x4 0x13 0x4 0x14 0x4 0x15 0x4 0x16 0x4>; }; }; @@ -296,35 +298,35 @@ #address-cells = <3>; compatible = "ibm,plb440gp-pcix", "ibm,plb-pcix"; primary; - reg = <2 0ec00000 8 /* Config space access */ - 0 0 0 /* no IACK cycles */ - 2 0ed00000 4 /* Special cycles */ - 2 0ec80000 f0 /* Internal registers */ - 2 0ec80100 fc>; /* Internal messaging registers */ + reg = <0x00000002 0x0ec00000 0x00000008 /* Config space access */ + 0x00000000 0x00000000 0x00000000 /* no IACK cycles */ + 0x00000002 0x0ed00000 0x00000004 /* Special cycles */ + 0x00000002 0x0ec80000 0x000000f0 /* Internal registers */ + 0x00000002 0x0ec80100 0x000000fc>; /* Internal messaging registers */ /* Outbound ranges, one memory and one IO, * later cannot be changed */ - ranges = <02000000 0 80000000 00000003 80000000 0 80000000 - 01000000 0 00000000 00000002 08000000 0 00010000>; + ranges = <0x02000000 0x00000000 0x80000000 0x00000003 0x80000000 0x00000000 0x80000000 + 0x01000000 0x00000000 0x00000000 0x00000002 0x08000000 0x00000000 0x00010000>; /* Inbound 2GB range starting at 0 */ - dma-ranges = <42000000 0 0 0 0 0 80000000>; + dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>; /* Ebony has all 4 IRQ pins tied together per slot */ - interrupt-map-mask = ; + interrupt-map-mask = <0xf800 0x0 0x0 0x0>; interrupt-map = < /* IDSEL 1 */ - 0800 0 0 0 &UIC0 17 8 + 0x800 0x0 0x0 0x0 &UIC0 0x17 0x8 /* IDSEL 2 */ - 1000 0 0 0 &UIC0 18 8 + 0x1000 0x0 0x0 0x0 &UIC0 0x18 0x8 /* IDSEL 3 */ - 1800 0 0 0 &UIC0 19 8 + 0x1800 0x0 0x0 0x0 &UIC0 0x19 0x8 /* IDSEL 4 */ - 2000 0 0 0 &UIC0 1a 8 + 0x2000 0x0 0x0 0x0 &UIC0 0x1a 0x8 >; }; }; diff --git a/arch/powerpc/boot/dts/ep405.dts b/arch/powerpc/boot/dts/ep405.dts index 9293855..53ef06c 100644 --- a/arch/powerpc/boot/dts/ep405.dts +++ b/arch/powerpc/boot/dts/ep405.dts @@ -9,12 +9,14 @@ * any warranty of any kind, whether express or implied. */ +/dts-v1/; + / { #address-cells = <1>; #size-cells = <1>; model = "ep405"; compatible = "ep405"; - dcr-parent = <&/cpus/cpu@0>; + dcr-parent = <&{/cpus/cpu@0}>; aliases { ethernet0 = &EMAC; @@ -29,13 +31,13 @@ cpu@0 { device_type = "cpu"; model = "PowerPC,405GP"; - reg = <0>; - clock-frequency = ; /* Filled in by zImage */ + reg = <0x00000000>; + clock-frequency = <200000000>; /* Filled in by zImage */ timebase-frequency = <0>; /* Filled in by zImage */ - i-cache-line-size = <20>; - d-cache-line-size = <20>; - i-cache-size = <4000>; - d-cache-size = <4000>; + i-cache-line-size = <32>; + d-cache-line-size = <32>; + i-cache-size = <16384>; + d-cache-size = <16384>; dcr-controller; dcr-access-method = "native"; }; @@ -43,14 +45,14 @@ memory { device_type = "memory"; - reg = <0 0>; /* Filled in by zImage */ + reg = <0x00000000 0x00000000>; /* Filled in by zImage */ }; UIC0: interrupt-controller { compatible = "ibm,uic"; interrupt-controller; cell-index = <0>; - dcr-reg = <0c0 9>; + dcr-reg = <0x0c0 0x009>; #address-cells = <0>; #size-cells = <0>; #interrupt-cells = <2>; @@ -65,91 +67,91 @@ SDRAM0: memory-controller { compatible = "ibm,sdram-405gp"; - dcr-reg = <010 2>; + dcr-reg = <0x010 0x002>; }; MAL: mcmal { compatible = "ibm,mcmal-405gp", "ibm,mcmal"; - dcr-reg = <180 62>; + dcr-reg = <0x180 0x062>; num-tx-chans = <1>; num-rx-chans = <1>; interrupt-parent = <&UIC0>; interrupts = < - b 4 /* TXEOB */ - c 4 /* RXEOB */ - a 4 /* SERR */ - d 4 /* TXDE */ - e 4 /* RXDE */>; + 0xb 0x4 /* TXEOB */ + 0xc 0x4 /* RXEOB */ + 0xa 0x4 /* SERR */ + 0xd 0x4 /* TXDE */ + 0xe 0x4 /* RXDE */>; }; POB0: opb { compatible = "ibm,opb-405gp", "ibm,opb"; #address-cells = <1>; #size-cells = <1>; - ranges = ; - dcr-reg = <0a0 5>; + ranges = <0xef600000 0xef600000 0x00a00000>; + dcr-reg = <0x0a0 0x005>; clock-frequency = <0>; /* Filled in by zImage */ UART0: serial@ef600300 { device_type = "serial"; compatible = "ns16550"; - reg = ; - virtual-reg = ; + reg = <0xef600300 0x00000008>; + virtual-reg = <0xef600300>; clock-frequency = <0>; /* Filled in by zImage */ - current-speed = <2580>; + current-speed = <9600>; interrupt-parent = <&UIC0>; - interrupts = <0 4>; + interrupts = <0x0 0x4>; }; UART1: serial@ef600400 { device_type = "serial"; compatible = "ns16550"; - reg = ; - virtual-reg = ; + reg = <0xef600400 0x00000008>; + virtual-reg = <0xef600400>; clock-frequency = <0>; /* Filled in by zImage */ - current-speed = <2580>; + current-speed = <9600>; interrupt-parent = <&UIC0>; - interrupts = <1 4>; + interrupts = <0x1 0x4>; }; IIC: i2c@ef600500 { compatible = "ibm,iic-405gp", "ibm,iic"; - reg = ; + reg = <0xef600500 0x00000011>; interrupt-parent = <&UIC0>; - interrupts = <2 4>; + interrupts = <0x2 0x4>; }; GPIO: gpio@ef600700 { compatible = "ibm,gpio-405gp"; - reg = ; + reg = <0xef600700 0x00000020>; }; EMAC: ethernet@ef600800 { - linux,network-index = <0>; + linux,network-index = <0x0>; device_type = "network"; compatible = "ibm,emac-405gp", "ibm,emac"; interrupt-parent = <&UIC0>; interrupts = < - f 4 /* Ethernet */ - 9 4 /* Ethernet Wake Up */>; + 0xf 0x4 /* Ethernet */ + 0x9 0x4 /* Ethernet Wake Up */>; local-mac-address = [000000000000]; /* Filled in by zImage */ - reg = ; + reg = <0xef600800 0x00000070>; mal-device = <&MAL>; mal-tx-channel = <0>; mal-rx-channel = <0>; cell-index = <0>; - max-frame-size = <5dc>; - rx-fifo-size = <1000>; - tx-fifo-size = <800>; + max-frame-size = <1500>; + rx-fifo-size = <4096>; + tx-fifo-size = <2048>; phy-mode = "rmii"; - phy-map = <00000000>; + phy-map = <0x00000000>; }; }; EBC0: ebc { compatible = "ibm,ebc-405gp", "ibm,ebc"; - dcr-reg = <012 2>; + dcr-reg = <0x012 0x002>; #address-cells = <2>; #size-cells = <1>; @@ -163,13 +165,13 @@ /* NVRAM and RTC */ nvrtc@4,200000 { compatible = "ds1742"; - reg = <4 200000 0>; /* size fixed up by zImage */ + reg = <0x00000004 0x00200000 0x00000000>; /* size fixed up by zImage */ }; /* "BCSR" CPLD contains a PCI irq controller */ bcsr@4,0 { compatible = "ep405-bcsr"; - reg = <4 0 10>; + reg = <0x00000004 0x00000000 0x00000010>; interrupt-controller; /* Routing table */ irq-routing = [ 00 /* SYSERR */ @@ -198,26 +200,26 @@ #address-cells = <3>; compatible = "ibm,plb405gp-pci", "ibm,plb-pci"; primary; - reg = ; /* Internal registers */ + reg = <0xeec00000 0x00000008 /* Config space access */ + 0xeed80000 0x00000004 /* IACK */ + 0xeed80000 0x00000004 /* Special cycle */ + 0xef480000 0x00000040>; /* Internal registers */ /* Outbound ranges, one memory and one IO, * later cannot be changed. Chip supports a second * IO range but we don't use it for now */ - ranges = <02000000 0 80000000 80000000 0 20000000 - 01000000 0 00000000 e8000000 0 00010000>; + ranges = <0x02000000 0x00000000 0x80000000 0x80000000 0x00000000 0x20000000 + 0x01000000 0x00000000 0x00000000 0xe8000000 0x00000000 0x00010000>; /* Inbound 2GB range starting at 0 */ - dma-ranges = <42000000 0 0 0 0 80000000>; + dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x80000000>; /* That's all I know about IRQs on that thing ... */ - interrupt-map-mask = ; + interrupt-map-mask = <0xf800 0x0 0x0 0x0>; interrupt-map = < /* USB */ - 7000 0 0 0 &UIC0 1e 8 /* IRQ5 */ + 0x7000 0x0 0x0 0x0 &UIC0 0x1e 0x8 /* IRQ5 */ >; }; }; diff --git a/arch/powerpc/boot/dts/glacier.dts b/arch/powerpc/boot/dts/glacier.dts index 0f2fc07..463650c 100644 --- a/arch/powerpc/boot/dts/glacier.dts +++ b/arch/powerpc/boot/dts/glacier.dts @@ -8,12 +8,14 @@ * any warranty of any kind, whether express or implied. */ +/dts-v1/; + / { #address-cells = <2>; #size-cells = <1>; model = "amcc,glacier"; compatible = "amcc,glacier", "amcc,canyonlands"; - dcr-parent = <&/cpus/cpu@0>; + dcr-parent = <&{/cpus/cpu@0}>; aliases { ethernet0 = &EMAC0; @@ -31,13 +33,13 @@ cpu@0 { device_type = "cpu"; model = "PowerPC,460GT"; - reg = <0>; + reg = <0x00000000>; clock-frequency = <0>; /* Filled in by U-Boot */ timebase-frequency = <0>; /* Filled in by U-Boot */ - i-cache-line-size = <20>; - d-cache-line-size = <20>; - i-cache-size = <8000>; - d-cache-size = <8000>; + i-cache-line-size = <32>; + d-cache-line-size = <32>; + i-cache-size = <32768>; + d-cache-size = <32768>; dcr-controller; dcr-access-method = "native"; }; @@ -45,14 +47,14 @@ memory { device_type = "memory"; - reg = <0 0 0>; /* Filled in by U-Boot */ + reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by U-Boot */ }; UIC0: interrupt-controller0 { compatible = "ibm,uic-460gt","ibm,uic"; interrupt-controller; cell-index = <0>; - dcr-reg = <0c0 009>; + dcr-reg = <0x0c0 0x009>; #address-cells = <0>; #size-cells = <0>; #interrupt-cells = <2>; @@ -62,11 +64,11 @@ compatible = "ibm,uic-460gt","ibm,uic"; interrupt-controller; cell-index = <1>; - dcr-reg = <0d0 009>; + dcr-reg = <0x0d0 0x009>; #address-cells = <0>; #size-cells = <0>; #interrupt-cells = <2>; - interrupts = <1e 4 1f 4>; /* cascade */ + interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */ interrupt-parent = <&UIC0>; }; @@ -74,11 +76,11 @@ compatible = "ibm,uic-460gt","ibm,uic"; interrupt-controller; cell-index = <2>; - dcr-reg = <0e0 009>; + dcr-reg = <0x0e0 0x009>; #address-cells = <0>; #size-cells = <0>; #interrupt-cells = <2>; - interrupts = ; /* cascade */ + interrupts = <0xa 0x4 0xb 0x4>; /* cascade */ interrupt-parent = <&UIC0>; }; @@ -86,22 +88,22 @@ compatible = "ibm,uic-460gt","ibm,uic"; interrupt-controller; cell-index = <3>; - dcr-reg = <0f0 009>; + dcr-reg = <0x0f0 0x009>; #address-cells = <0>; #size-cells = <0>; #interrupt-cells = <2>; - interrupts = <10 4 11 4>; /* cascade */ + interrupts = <0x10 0x4 0x11 0x4>; /* cascade */ interrupt-parent = <&UIC0>; }; SDR0: sdr { compatible = "ibm,sdr-460gt"; - dcr-reg = <00e 002>; + dcr-reg = <0x00e 0x002>; }; CPR0: cpr { compatible = "ibm,cpr-460gt"; - dcr-reg = <00c 002>; + dcr-reg = <0x00c 0x002>; }; plb { @@ -113,75 +115,75 @@ SDRAM0: sdram { compatible = "ibm,sdram-460gt", "ibm,sdram-405gp"; - dcr-reg = <010 2>; + dcr-reg = <0x010 0x002>; }; MAL0: mcmal { compatible = "ibm,mcmal-460gt", "ibm,mcmal2"; - dcr-reg = <180 62>; + dcr-reg = <0x180 0x062>; num-tx-chans = <4>; - num-rx-chans = <20>; + num-rx-chans = <32>; #address-cells = <0>; #size-cells = <0>; interrupt-parent = <&UIC2>; - interrupts = < /*TXEOB*/ 6 4 - /*RXEOB*/ 7 4 - /*SERR*/ 3 4 - /*TXDE*/ 4 4 - /*RXDE*/ 5 4>; - desc-base-addr-high = <8>; + interrupts = < /*TXEOB*/ 0x6 0x4 + /*RXEOB*/ 0x7 0x4 + /*SERR*/ 0x3 0x4 + /*TXDE*/ 0x4 0x4 + /*RXDE*/ 0x5 0x4>; + desc-base-addr-high = <0x8>; }; POB0: opb { compatible = "ibm,opb-460gt", "ibm,opb"; #address-cells = <1>; #size-cells = <1>; - ranges = ; + ranges = <0xb0000000 0x00000004 0xb0000000 0x50000000>; clock-frequency = <0>; /* Filled in by U-Boot */ EBC0: ebc { compatible = "ibm,ebc-460gt", "ibm,ebc"; - dcr-reg = <012 2>; + dcr-reg = <0x012 0x002>; #address-cells = <2>; #size-cells = <1>; clock-frequency = <0>; /* Filled in by U-Boot */ /* ranges property is supplied by U-Boot */ - interrupts = <6 4>; + interrupts = <0x6 0x4>; interrupt-parent = <&UIC1>; nor_flash@0,0 { compatible = "amd,s29gl512n", "cfi-flash"; bank-width = <2>; - reg = <0 000000 4000000>; + reg = <0x00000000 0x00000000 0x04000000>; #address-cells = <1>; #size-cells = <1>; partition@0 { label = "kernel"; - reg = <0 1e0000>; + reg = <0x00000000 0x001e0000>; }; partition@1e0000 { label = "dtb"; - reg = <1e0000 20000>; + reg = <0x001e0000 0x00020000>; }; partition@200000 { label = "ramdisk"; - reg = <200000 1400000>; + reg = <0x00200000 0x01400000>; }; partition@1600000 { label = "jffs2"; - reg = <1600000 400000>; + reg = <0x01600000 0x00400000>; }; partition@1a00000 { label = "user"; - reg = <1a00000 2560000>; + reg = <0x01a00000 0x02560000>; }; partition@3f60000 { label = "env"; - reg = <3f60000 40000>; + reg = <0x03f60000 0x00040000>; }; partition@3fa0000 { label = "u-boot"; - reg = <3fa0000 60000>; + reg = <0x03fa0000 0x00060000>; }; }; }; @@ -189,109 +191,109 @@ UART0: serial@ef600300 { device_type = "serial"; compatible = "ns16550"; - reg = ; - virtual-reg = ; + reg = <0xef600300 0x00000008>; + virtual-reg = <0xef600300>; clock-frequency = <0>; /* Filled in by U-Boot */ current-speed = <0>; /* Filled in by U-Boot */ interrupt-parent = <&UIC1>; - interrupts = <1 4>; + interrupts = <0x1 0x4>; }; UART1: serial@ef600400 { device_type = "serial"; compatible = "ns16550"; - reg = ; - virtual-reg = ; + reg = <0xef600400 0x00000008>; + virtual-reg = <0xef600400>; clock-frequency = <0>; /* Filled in by U-Boot */ current-speed = <0>; /* Filled in by U-Boot */ interrupt-parent = <&UIC0>; - interrupts = <1 4>; + interrupts = <0x1 0x4>; }; UART2: serial@ef600500 { device_type = "serial"; compatible = "ns16550"; - reg = ; - virtual-reg = ; + reg = <0xef600500 0x00000008>; + virtual-reg = <0xef600500>; clock-frequency = <0>; /* Filled in by U-Boot */ current-speed = <0>; /* Filled in by U-Boot */ interrupt-parent = <&UIC1>; - interrupts = <1d 4>; + interrupts = <0x1d 0x4>; }; UART3: serial@ef600600 { device_type = "serial"; compatible = "ns16550"; - reg = ; - virtual-reg = ; + reg = <0xef600600 0x00000008>; + virtual-reg = <0xef600600>; clock-frequency = <0>; /* Filled in by U-Boot */ current-speed = <0>; /* Filled in by U-Boot */ interrupt-parent = <&UIC1>; - interrupts = <1e 4>; + interrupts = <0x1e 0x4>; }; IIC0: i2c@ef600700 { compatible = "ibm,iic-460gt", "ibm,iic"; - reg = ; + reg = <0xef600700 0x00000014>; interrupt-parent = <&UIC0>; - interrupts = <2 4>; + interrupts = <0x2 0x4>; }; IIC1: i2c@ef600800 { compatible = "ibm,iic-460gt", "ibm,iic"; - reg = ; + reg = <0xef600800 0x00000014>; interrupt-parent = <&UIC0>; - interrupts = <3 4>; + interrupts = <0x3 0x4>; }; ZMII0: emac-zmii@ef600d00 { compatible = "ibm,zmii-460gt", "ibm,zmii"; - reg = ; + reg = <0xef600d00 0x0000000c>; }; RGMII0: emac-rgmii@ef601500 { compatible = "ibm,rgmii-460gt", "ibm,rgmii"; - reg = ; + reg = <0xef601500 0x00000008>; has-mdio; }; RGMII1: emac-rgmii@ef601600 { compatible = "ibm,rgmii-460gt", "ibm,rgmii"; - reg = ; + reg = <0xef601600 0x00000008>; has-mdio; }; TAH0: emac-tah@ef601350 { compatible = "ibm,tah-460gt", "ibm,tah"; - reg = ; + reg = <0xef601350 0x00000030>; }; TAH1: emac-tah@ef601450 { compatible = "ibm,tah-460gt", "ibm,tah"; - reg = ; + reg = <0xef601450 0x00000030>; }; EMAC0: ethernet@ef600e00 { device_type = "network"; compatible = "ibm,emac-460gt", "ibm,emac4"; interrupt-parent = <&EMAC0>; - interrupts = <0 1>; + interrupts = <0x0 0x1>; #interrupt-cells = <1>; #address-cells = <0>; #size-cells = <0>; - interrupt-map = ; - reg = ; + interrupt-map = ; + reg = <0xef600e00 0x00000070>; local-mac-address = [000000000000]; /* Filled in by U-Boot */ mal-device = <&MAL0>; mal-tx-channel = <0>; mal-rx-channel = <0>; cell-index = <0>; - max-frame-size = <2328>; - rx-fifo-size = <1000>; - tx-fifo-size = <800>; + max-frame-size = <9000>; + rx-fifo-size = <4096>; + tx-fifo-size = <2048>; phy-mode = "rgmii"; - phy-map = <00000000>; + phy-map = <0x00000000>; rgmii-device = <&RGMII0>; rgmii-channel = <0>; tah-device = <&TAH0>; @@ -304,23 +306,23 @@ device_type = "network"; compatible = "ibm,emac-460gt", "ibm,emac4"; interrupt-parent = <&EMAC1>; - interrupts = <0 1>; + interrupts = <0x0 0x1>; #interrupt-cells = <1>; #address-cells = <0>; #size-cells = <0>; - interrupt-map = ; - reg = ; + interrupt-map = ; + reg = <0xef600f00 0x00000070>; local-mac-address = [000000000000]; /* Filled in by U-Boot */ mal-device = <&MAL0>; mal-tx-channel = <1>; mal-rx-channel = <8>; cell-index = <1>; - max-frame-size = <2328>; - rx-fifo-size = <1000>; - tx-fifo-size = <800>; + max-frame-size = <9000>; + rx-fifo-size = <4096>; + tx-fifo-size = <2048>; phy-mode = "rgmii"; - phy-map = <00000000>; + phy-map = <0x00000000>; rgmii-device = <&RGMII0>; rgmii-channel = <1>; tah-device = <&TAH1>; @@ -334,23 +336,23 @@ device_type = "network"; compatible = "ibm,emac-460gt", "ibm,emac4"; interrupt-parent = <&EMAC2>; - interrupts = <0 1>; + interrupts = <0x0 0x1>; #interrupt-cells = <1>; #address-cells = <0>; #size-cells = <0>; - interrupt-map = ; - reg = ; + interrupt-map = ; + reg = <0xef601100 0x00000070>; local-mac-address = [000000000000]; /* Filled in by U-Boot */ mal-device = <&MAL0>; mal-tx-channel = <2>; - mal-rx-channel = <10>; + mal-rx-channel = <16>; cell-index = <2>; - max-frame-size = <2328>; - rx-fifo-size = <1000>; - tx-fifo-size = <800>; + max-frame-size = <9000>; + rx-fifo-size = <4096>; + tx-fifo-size = <2048>; phy-mode = "rgmii"; - phy-map = <00000000>; + phy-map = <0x00000000>; rgmii-device = <&RGMII1>; rgmii-channel = <0>; has-inverted-stacr-oc; @@ -362,23 +364,23 @@ device_type = "network"; compatible = "ibm,emac-460gt", "ibm,emac4"; interrupt-parent = <&EMAC3>; - interrupts = <0 1>; + interrupts = <0x0 0x1>; #interrupt-cells = <1>; #address-cells = <0>; #size-cells = <0>; - interrupt-map = ; - reg = ; + interrupt-map = ; + reg = <0xef601200 0x00000070>; local-mac-address = [000000000000]; /* Filled in by U-Boot */ mal-device = <&MAL0>; mal-tx-channel = <3>; - mal-rx-channel = <18>; + mal-rx-channel = <24>; cell-index = <3>; - max-frame-size = <2328>; - rx-fifo-size = <1000>; - tx-fifo-size = <800>; + max-frame-size = <9000>; + rx-fifo-size = <4096>; + tx-fifo-size = <2048>; phy-mode = "rgmii"; - phy-map = <00000000>; + phy-map = <0x00000000>; rgmii-device = <&RGMII1>; rgmii-channel = <1>; has-inverted-stacr-oc; @@ -396,27 +398,27 @@ primary; large-inbound-windows; enable-msi-hole; - reg = ; /* Internal messaging registers */ + reg = <0x0000000c 0x0ec00000 0x00000008 /* Config space access */ + 0x00000000 0x00000000 0x00000000 /* no IACK cycles */ + 0x0000000c 0x0ed00000 0x00000004 /* Special cycles */ + 0x0000000c 0x0ec80000 0x00000100 /* Internal registers */ + 0x0000000c 0x0ec80100 0x000000fc>; /* Internal messaging registers */ /* Outbound ranges, one memory and one IO, * later cannot be changed */ - ranges = <02000000 0 80000000 0000000d 80000000 0 80000000 - 01000000 0 00000000 0000000c 08000000 0 00010000>; + ranges = <0x02000000 0x00000000 0x80000000 0x0000000d 0x80000000 0x00000000 0x80000000 + 0x01000000 0x00000000 0x00000000 0x0000000c 0x08000000 0x00000000 0x00010000>; /* Inbound 2GB range starting at 0 */ - dma-ranges = <42000000 0 0 0 0 0 80000000>; + dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>; /* This drives busses 0 to 0x3f */ - bus-range = <0 3f>; + bus-range = <0x0 0x3f>; /* All PCI interrupts are routed to ext IRQ 2 -> UIC1-0 */ - interrupt-map-mask = <0000 0 0 0>; - interrupt-map = < 0000 0 0 0 &UIC1 0 8 >; + interrupt-map-mask = <0x0 0x0 0x0 0x0>; + interrupt-map = < 0x0 0x0 0x0 0x0 &UIC1 0x0 0x8 >; }; PCIE0: pciex@d00000000 { @@ -426,23 +428,23 @@ #address-cells = <3>; compatible = "ibm,plb-pciex-460ex", "ibm,plb-pciex"; primary; - port = <0>; /* port number */ - reg = ; /* Registers */ - dcr-reg = <100 020>; - sdr-base = <300>; + port = <0x0>; /* port number */ + reg = <0x0000000d 0x00000000 0x20000000 /* Config space access */ + 0x0000000c 0x08010000 0x00001000>; /* Registers */ + dcr-reg = <0x100 0x020>; + sdr-base = <0x300>; /* Outbound ranges, one memory and one IO, * later cannot be changed */ - ranges = <02000000 0 80000000 0000000e 00000000 0 80000000 - 01000000 0 00000000 0000000f 80000000 0 00010000>; + ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x00000000 0x00000000 0x80000000 + 0x01000000 0x00000000 0x00000000 0x0000000f 0x80000000 0x00000000 0x00010000>; /* Inbound 2GB range starting at 0 */ - dma-ranges = <42000000 0 0 0 0 0 80000000>; + dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>; /* This drives busses 40 to 0x7f */ - bus-range = <40 7f>; + bus-range = <0x40 0x7f>; /* Legacy interrupts (note the weird polarity, the bridge seems * to invert PCIe legacy interrupts). @@ -452,12 +454,12 @@ * below are basically de-swizzled numbers. * The real slot is on idsel 0, so the swizzling is 1:1 */ - interrupt-map-mask = <0000 0 0 7>; + interrupt-map-mask = <0x0 0x0 0x0 0x7>; interrupt-map = < - 0000 0 0 1 &UIC3 c 4 /* swizzled int A */ - 0000 0 0 2 &UIC3 d 4 /* swizzled int B */ - 0000 0 0 3 &UIC3 e 4 /* swizzled int C */ - 0000 0 0 4 &UIC3 f 4 /* swizzled int D */>; + 0x0 0x0 0x0 0x1 &UIC3 0xc 0x4 /* swizzled int A */ + 0x0 0x0 0x0 0x2 &UIC3 0xd 0x4 /* swizzled int B */ + 0x0 0x0 0x0 0x3 &UIC3 0xe 0x4 /* swizzled int C */ + 0x0 0x0 0x0 0x4 &UIC3 0xf 0x4 /* swizzled int D */>; }; PCIE1: pciex@d20000000 { @@ -467,23 +469,23 @@ #address-cells = <3>; compatible = "ibm,plb-pciex-460ex", "ibm,plb-pciex"; primary; - port = <1>; /* port number */ - reg = ; /* Registers */ - dcr-reg = <120 020>; - sdr-base = <340>; + port = <0x1>; /* port number */ + reg = <0x0000000d 0x20000000 0x20000000 /* Config space access */ + 0x0000000c 0x08011000 0x00001000>; /* Registers */ + dcr-reg = <0x120 0x020>; + sdr-base = <0x340>; /* Outbound ranges, one memory and one IO, * later cannot be changed */ - ranges = <02000000 0 80000000 0000000e 80000000 0 80000000 - 01000000 0 00000000 0000000f 80010000 0 00010000>; + ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x80000000 0x00000000 0x80000000 + 0x01000000 0x00000000 0x00000000 0x0000000f 0x80010000 0x00000000 0x00010000>; /* Inbound 2GB range starting at 0 */ - dma-ranges = <42000000 0 0 0 0 0 80000000>; + dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>; /* This drives busses 80 to 0xbf */ - bus-range = <80 bf>; + bus-range = <0x80 0xbf>; /* Legacy interrupts (note the weird polarity, the bridge seems * to invert PCIe legacy interrupts). @@ -493,12 +495,12 @@ * below are basically de-swizzled numbers. * The real slot is on idsel 0, so the swizzling is 1:1 */ - interrupt-map-mask = <0000 0 0 7>; + interrupt-map-mask = <0x0 0x0 0x0 0x7>; interrupt-map = < - 0000 0 0 1 &UIC3 10 4 /* swizzled int A */ - 0000 0 0 2 &UIC3 11 4 /* swizzled int B */ - 0000 0 0 3 &UIC3 12 4 /* swizzled int C */ - 0000 0 0 4 &UIC3 13 4 /* swizzled int D */>; + 0x0 0x0 0x0 0x1 &UIC3 0x10 0x4 /* swizzled int A */ + 0x0 0x0 0x0 0x2 &UIC3 0x11 0x4 /* swizzled int B */ + 0x0 0x0 0x0 0x3 &UIC3 0x12 0x4 /* swizzled int C */ + 0x0 0x0 0x0 0x4 &UIC3 0x13 0x4 /* swizzled int D */>; }; }; }; diff --git a/arch/powerpc/boot/dts/haleakala.dts b/arch/powerpc/boot/dts/haleakala.dts index b5d95ac..2c2fcea 100644 --- a/arch/powerpc/boot/dts/haleakala.dts +++ b/arch/powerpc/boot/dts/haleakala.dts @@ -8,12 +8,14 @@ * any warranty of any kind, whether express or implied. */ +/dts-v1/; + / { #address-cells = <1>; #size-cells = <1>; model = "amcc,haleakala"; compatible = "amcc,haleakala", "amcc,kilauea"; - dcr-parent = <&/cpus/cpu@0>; + dcr-parent = <&{/cpus/cpu@0}>; aliases { ethernet0 = &EMAC0; @@ -28,13 +30,13 @@ cpu@0 { device_type = "cpu"; model = "PowerPC,405EXr"; - reg = <0>; + reg = <0x00000000>; clock-frequency = <0>; /* Filled in by U-Boot */ timebase-frequency = <0>; /* Filled in by U-Boot */ - i-cache-line-size = <20>; - d-cache-line-size = <20>; - i-cache-size = <4000>; /* 16 kB */ - d-cache-size = <4000>; /* 16 kB */ + i-cache-line-size = <32>; + d-cache-line-size = <32>; + i-cache-size = <16384>; /* 16 kB */ + d-cache-size = <16384>; /* 16 kB */ dcr-controller; dcr-access-method = "native"; }; @@ -42,14 +44,14 @@ memory { device_type = "memory"; - reg = <0 0>; /* Filled in by U-Boot */ + reg = <0x00000000 0x00000000>; /* Filled in by U-Boot */ }; UIC0: interrupt-controller { compatible = "ibm,uic-405exr", "ibm,uic"; interrupt-controller; cell-index = <0>; - dcr-reg = <0c0 009>; + dcr-reg = <0x0c0 0x009>; #address-cells = <0>; #size-cells = <0>; #interrupt-cells = <2>; @@ -59,11 +61,11 @@ compatible = "ibm,uic-405exr","ibm,uic"; interrupt-controller; cell-index = <1>; - dcr-reg = <0d0 009>; + dcr-reg = <0x0d0 0x009>; #address-cells = <0>; #size-cells = <0>; #interrupt-cells = <2>; - interrupts = <1e 4 1f 4>; /* cascade */ + interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */ interrupt-parent = <&UIC0>; }; @@ -71,11 +73,11 @@ compatible = "ibm,uic-405exr","ibm,uic"; interrupt-controller; cell-index = <2>; - dcr-reg = <0e0 009>; + dcr-reg = <0x0e0 0x009>; #address-cells = <0>; #size-cells = <0>; #interrupt-cells = <2>; - interrupts = <1c 4 1d 4>; /* cascade */ + interrupts = <0x1c 0x4 0x1d 0x4>; /* cascade */ interrupt-parent = <&UIC0>; }; @@ -88,72 +90,72 @@ SDRAM0: memory-controller { compatible = "ibm,sdram-405exr"; - dcr-reg = <010 2>; + dcr-reg = <0x010 0x002>; }; MAL0: mcmal { compatible = "ibm,mcmal-405exr", "ibm,mcmal2"; - dcr-reg = <180 62>; + dcr-reg = <0x180 0x062>; num-tx-chans = <2>; num-rx-chans = <2>; interrupt-parent = <&MAL0>; - interrupts = <0 1 2 3 4>; + interrupts = <0x0 0x1 0x2 0x3 0x4>; #interrupt-cells = <1>; #address-cells = <0>; #size-cells = <0>; - interrupt-map = ; - interrupt-map-mask = ; + interrupt-map = ; + interrupt-map-mask = <0xffffffff>; }; POB0: opb { compatible = "ibm,opb-405exr", "ibm,opb"; #address-cells = <1>; #size-cells = <1>; - ranges = <80000000 80000000 10000000 - ef600000 ef600000 a00000 - f0000000 f0000000 10000000>; - dcr-reg = <0a0 5>; + ranges = <0x80000000 0x80000000 0x10000000 + 0xef600000 0xef600000 0x00a00000 + 0xf0000000 0xf0000000 0x10000000>; + dcr-reg = <0x0a0 0x005>; clock-frequency = <0>; /* Filled in by U-Boot */ EBC0: ebc { compatible = "ibm,ebc-405exr", "ibm,ebc"; - dcr-reg = <012 2>; + dcr-reg = <0x012 0x002>; #address-cells = <2>; #size-cells = <1>; clock-frequency = <0>; /* Filled in by U-Boot */ /* ranges property is supplied by U-Boot */ - interrupts = <5 1>; + interrupts = <0x5 0x1>; interrupt-parent = <&UIC1>; nor_flash@0,0 { compatible = "amd,s29gl512n", "cfi-flash"; bank-width = <2>; - reg = <0 000000 4000000>; + reg = <0x00000000 0x00000000 0x04000000>; #address-cells = <1>; #size-cells = <1>; partition@0 { label = "kernel"; - reg = <0 200000>; + reg = <0x00000000 0x00200000>; }; partition@200000 { label = "root"; - reg = <200000 200000>; + reg = <0x00200000 0x00200000>; }; partition@400000 { label = "user"; - reg = <400000 3b60000>; + reg = <0x00400000 0x03b60000>; }; partition@3f60000 { label = "env"; - reg = <3f60000 40000>; + reg = <0x03f60000 0x00040000>; }; partition@3fa0000 { label = "u-boot"; - reg = <3fa0000 60000>; + reg = <0x03fa0000 0x00060000>; }; }; }; @@ -161,68 +163,68 @@ UART0: serial@ef600200 { device_type = "serial"; compatible = "ns16550"; - reg = ; - virtual-reg = ; + reg = <0xef600200 0x00000008>; + virtual-reg = <0xef600200>; clock-frequency = <0>; /* Filled in by U-Boot */ current-speed = <0>; interrupt-parent = <&UIC0>; - interrupts = <1a 4>; + interrupts = <0x1a 0x4>; }; UART1: serial@ef600300 { device_type = "serial"; compatible = "ns16550"; - reg = ; - virtual-reg = ; + reg = <0xef600300 0x00000008>; + virtual-reg = <0xef600300>; clock-frequency = <0>; /* Filled in by U-Boot */ current-speed = <0>; interrupt-parent = <&UIC0>; - interrupts = <1 4>; + interrupts = <0x1 0x4>; }; IIC0: i2c@ef600400 { compatible = "ibm,iic-405exr", "ibm,iic"; - reg = ; + reg = <0xef600400 0x00000014>; interrupt-parent = <&UIC0>; - interrupts = <2 4>; + interrupts = <0x2 0x4>; }; IIC1: i2c@ef600500 { compatible = "ibm,iic-405exr", "ibm,iic"; - reg = ; + reg = <0xef600500 0x00000014>; interrupt-parent = <&UIC0>; - interrupts = <7 4>; + interrupts = <0x7 0x4>; }; RGMII0: emac-rgmii@ef600b00 { compatible = "ibm,rgmii-405exr", "ibm,rgmii"; - reg = ; + reg = <0xef600b00 0x00000104>; has-mdio; }; EMAC0: ethernet@ef600900 { - linux,network-index = <0>; + linux,network-index = <0x0>; device_type = "network"; compatible = "ibm,emac-405exr", "ibm,emac4"; interrupt-parent = <&EMAC0>; - interrupts = <0 1>; + interrupts = <0x0 0x1>; #interrupt-cells = <1>; #address-cells = <0>; #size-cells = <0>; - interrupt-map = ; - reg = ; + interrupt-map = ; + reg = <0xef600900 0x00000070>; local-mac-address = [000000000000]; /* Filled in by U-Boot */ mal-device = <&MAL0>; mal-tx-channel = <0>; mal-rx-channel = <0>; cell-index = <0>; - max-frame-size = <2328>; - rx-fifo-size = <1000>; - tx-fifo-size = <800>; + max-frame-size = <9000>; + rx-fifo-size = <4096>; + tx-fifo-size = <2048>; phy-mode = "rgmii"; - phy-map = <00000000>; + phy-map = <0x00000000>; rgmii-device = <&RGMII0>; rgmii-channel = <0>; has-inverted-stacr-oc; @@ -237,23 +239,23 @@ #address-cells = <3>; compatible = "ibm,plb-pciex-405ex", "ibm,plb-pciex"; primary; - port = <0>; /* port number */ - reg = ; /* Registers */ - dcr-reg = <040 020>; - sdr-base = <400>; + port = <0x0>; /* port number */ + reg = <0xa0000000 0x20000000 /* Config space access */ + 0xef000000 0x00001000>; /* Registers */ + dcr-reg = <0x040 0x020>; + sdr-base = <0x400>; /* Outbound ranges, one memory and one IO, * later cannot be changed */ - ranges = <02000000 0 80000000 90000000 0 08000000 - 01000000 0 00000000 e0000000 0 00010000>; + ranges = <0x02000000 0x00000000 0x80000000 0x90000000 0x00000000 0x08000000 + 0x01000000 0x00000000 0x00000000 0xe0000000 0x00000000 0x00010000>; /* Inbound 2GB range starting at 0 */ - dma-ranges = <42000000 0 0 0 0 80000000>; + dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x80000000>; /* This drives busses 0x00 to 0x3f */ - bus-range = <00 3f>; + bus-range = <0x0 0x3f>; /* Legacy interrupts (note the weird polarity, the bridge seems * to invert PCIe legacy interrupts). @@ -263,12 +265,12 @@ * below are basically de-swizzled numbers. * The real slot is on idsel 0, so the swizzling is 1:1 */ - interrupt-map-mask = <0000 0 0 7>; + interrupt-map-mask = <0x0 0x0 0x0 0x7>; interrupt-map = < - 0000 0 0 1 &UIC2 0 4 /* swizzled int A */ - 0000 0 0 2 &UIC2 1 4 /* swizzled int B */ - 0000 0 0 3 &UIC2 2 4 /* swizzled int C */ - 0000 0 0 4 &UIC2 3 4 /* swizzled int D */>; + 0x0 0x0 0x0 0x1 &UIC2 0x0 0x4 /* swizzled int A */ + 0x0 0x0 0x0 0x2 &UIC2 0x1 0x4 /* swizzled int B */ + 0x0 0x0 0x0 0x3 &UIC2 0x2 0x4 /* swizzled int C */ + 0x0 0x0 0x0 0x4 &UIC2 0x3 0x4 /* swizzled int D */>; }; }; }; diff --git a/arch/powerpc/boot/dts/holly.dts b/arch/powerpc/boot/dts/holly.dts index b5d8789..f87fe7b 100644 --- a/arch/powerpc/boot/dts/holly.dts +++ b/arch/powerpc/boot/dts/holly.dts @@ -10,6 +10,8 @@ * any warranty of any kind, whether express or implied. */ +/dts-v1/; + / { model = "41K7339"; compatible = "ibm,holly"; @@ -21,22 +23,22 @@ #size-cells =<0>; PowerPC,750CL@0 { device_type = "cpu"; - reg = <0>; - d-cache-line-size = <20>; - i-cache-line-size = <20>; - d-cache-size = <8000>; - i-cache-size = <8000>; - d-cache-sets = <80>; - i-cache-sets = <80>; - timebase-frequency = <2faf080>; - clock-frequency = <23c34600>; - bus-frequency = ; + reg = <0x00000000>; + d-cache-line-size = <32>; + i-cache-line-size = <32>; + d-cache-size = <32768>; + i-cache-size = <32768>; + d-cache-sets = <128>; + i-cache-sets = <128>; + timebase-frequency = <50000000>; + clock-frequency = <600000000>; + bus-frequency = <200000000>; }; }; memory@0 { device_type = "memory"; - reg = <00000000 20000000>; + reg = <0x00000000 0x20000000>; }; tsi109@c0000000 { @@ -44,33 +46,33 @@ compatible = "tsi109-bridge", "tsi108-bridge"; #address-cells = <1>; #size-cells = <1>; - ranges = <00000000 c0000000 00010000>; - reg = ; + ranges = <0x00000000 0xc0000000 0x00010000>; + reg = <0xc0000000 0x00010000>; i2c@7000 { device_type = "i2c"; compatible = "tsi109-i2c", "tsi108-i2c"; interrupt-parent = <&MPIC>; - interrupts = ; - reg = <7000 400>; + interrupts = <0xe 0x2>; + reg = <0x00007000 0x00000400>; }; MDIO: mdio@6000 { device_type = "mdio"; compatible = "tsi109-mdio", "tsi108-mdio"; - reg = <6000 50>; + reg = <0x00006000 0x00000050>; #address-cells = <1>; #size-cells = <0>; PHY1: ethernet-phy@1 { compatible = "bcm5461a"; - reg = <1>; + reg = <0x00000001>; txc-rxc-delay-disable; }; PHY2: ethernet-phy@2 { compatible = "bcm5461a"; - reg = <2>; + reg = <0x00000002>; txc-rxc-delay-disable; }; }; @@ -80,10 +82,10 @@ compatible = "tsi109-ethernet", "tsi108-ethernet"; #address-cells = <1>; #size-cells = <0>; - reg = <6000 200>; + reg = <0x00006000 0x00000200>; local-mac-address = [ 00 00 00 00 00 00 ]; interrupt-parent = <&MPIC>; - interrupts = <10 2>; + interrupts = <0x10 0x2>; mdio-handle = <&MDIO>; phy-handle = <&PHY1>; }; @@ -93,10 +95,10 @@ compatible = "tsi109-ethernet", "tsi108-ethernet"; #address-cells = <1>; #size-cells = <0>; - reg = <6400 200>; + reg = <0x00006400 0x00000200>; local-mac-address = [ 00 00 00 00 00 00 ]; interrupt-parent = <&MPIC>; - interrupts = <11 2>; + interrupts = <0x11 0x2>; mdio-handle = <&MDIO>; phy-handle = <&PHY2>; }; @@ -104,23 +106,23 @@ serial@7808 { device_type = "serial"; compatible = "ns16550"; - reg = <7808 200>; - virtual-reg = ; - clock-frequency = <3F9C6000>; - current-speed = <1c200>; + reg = <0x00007808 0x00000200>; + virtual-reg = <0xc0007808>; + clock-frequency = <1067212800>; + current-speed = <115200>; interrupt-parent = <&MPIC>; - interrupts = ; + interrupts = <0xc 0x2>; }; serial@7c08 { device_type = "serial"; compatible = "ns16550"; - reg = <7c08 200>; - virtual-reg = ; - clock-frequency = <3F9C6000>; - current-speed = <1c200>; + reg = <0x00007c08 0x00000200>; + virtual-reg = <0xc0007c08>; + clock-frequency = <1067212800>; + current-speed = <115200>; interrupt-parent = <&MPIC>; - interrupts = ; + interrupts = <0xd 0x2>; }; MPIC: pic@7400 { @@ -128,7 +130,7 @@ compatible = "chrp,open-pic"; interrupt-controller; #interrupt-cells = <2>; - reg = <7400 400>; + reg = <0x00007400 0x00000400>; big-endian; }; @@ -138,42 +140,42 @@ #interrupt-cells = <1>; #size-cells = <2>; #address-cells = <3>; - reg = <1000 1000>; - bus-range = <0 0>; + reg = <0x00001000 0x00001000>; + bus-range = <0x0 0x0>; /*----------------------------------------------------+ | PCI memory range. | 01 denotes I/O space | 02 denotes 32-bit memory space +----------------------------------------------------*/ - ranges = <02000000 0 40000000 40000000 0 10000000 - 01000000 0 00000000 7e000000 0 00010000>; - clock-frequency = <7f28154>; + ranges = <0x02000000 0x00000000 0x40000000 0x40000000 0x00000000 0x10000000 + 0x01000000 0x00000000 0x00000000 0x7e000000 0x00000000 0x00010000>; + clock-frequency = <133333332>; interrupt-parent = <&MPIC>; - interrupts = <17 2>; - interrupt-map-mask = ; + interrupts = <0x17 0x2>; + interrupt-map-mask = <0xf800 0x0 0x0 0x7>; /*----------------------------------------------------+ | The INTA, INTB, INTC, INTD are shared. +----------------------------------------------------*/ interrupt-map = < - 0800 0 0 1 &RT0 24 0 - 0800 0 0 2 &RT0 25 0 - 0800 0 0 3 &RT0 26 0 - 0800 0 0 4 &RT0 27 0 - - 1000 0 0 1 &RT0 25 0 - 1000 0 0 2 &RT0 26 0 - 1000 0 0 3 &RT0 27 0 - 1000 0 0 4 &RT0 24 0 - - 1800 0 0 1 &RT0 26 0 - 1800 0 0 2 &RT0 27 0 - 1800 0 0 3 &RT0 24 0 - 1800 0 0 4 &RT0 25 0 - - 2000 0 0 1 &RT0 27 0 - 2000 0 0 2 &RT0 24 0 - 2000 0 0 3 &RT0 25 0 - 2000 0 0 4 &RT0 26 0 + 0x800 0x0 0x0 0x1 &RT0 0x24 0x0 + 0x800 0x0 0x0 0x2 &RT0 0x25 0x0 + 0x800 0x0 0x0 0x3 &RT0 0x26 0x0 + 0x800 0x0 0x0 0x4 &RT0 0x27 0x0 + + 0x1000 0x0 0x0 0x1 &RT0 0x25 0x0 + 0x1000 0x0 0x0 0x2 &RT0 0x26 0x0 + 0x1000 0x0 0x0 0x3 &RT0 0x27 0x0 + 0x1000 0x0 0x0 0x4 &RT0 0x24 0x0 + + 0x1800 0x0 0x0 0x1 &RT0 0x26 0x0 + 0x1800 0x0 0x0 0x2 &RT0 0x27 0x0 + 0x1800 0x0 0x0 0x3 &RT0 0x24 0x0 + 0x1800 0x0 0x0 0x4 &RT0 0x25 0x0 + + 0x2000 0x0 0x0 0x1 &RT0 0x27 0x0 + 0x2000 0x0 0x0 0x2 &RT0 0x24 0x0 + 0x2000 0x0 0x0 0x3 &RT0 0x25 0x0 + 0x2000 0x0 0x0 0x4 &RT0 0x26 0x0 >; RT0: router@1180 { @@ -183,7 +185,7 @@ clock-frequency = <0>; #address-cells = <0>; #interrupt-cells = <2>; - interrupts = <17 2>; + interrupts = <0x17 0x2>; interrupt-parent = <&MPIC>; }; }; diff --git a/arch/powerpc/boot/dts/katmai.dts b/arch/powerpc/boot/dts/katmai.dts index cc2873a..b94bf61 100644 --- a/arch/powerpc/boot/dts/katmai.dts +++ b/arch/powerpc/boot/dts/katmai.dts @@ -12,12 +12,14 @@ * any warranty of any kind, whether express or implied. */ +/dts-v1/; + / { #address-cells = <2>; #size-cells = <1>; model = "amcc,katmai"; compatible = "amcc,katmai"; - dcr-parent = <&/cpus/cpu@0>; + dcr-parent = <&{/cpus/cpu@0}>; aliases { ethernet0 = &EMAC0; @@ -33,13 +35,13 @@ cpu@0 { device_type = "cpu"; model = "PowerPC,440SPe"; - reg = <0>; + reg = <0x00000000>; clock-frequency = <0>; /* Filled in by zImage */ timebase-frequency = <0>; /* Filled in by zImage */ - i-cache-line-size = <20>; - d-cache-line-size = <20>; - i-cache-size = <8000>; - d-cache-size = <8000>; + i-cache-line-size = <32>; + d-cache-line-size = <32>; + i-cache-size = <32768>; + d-cache-size = <32768>; dcr-controller; dcr-access-method = "native"; }; @@ -47,14 +49,14 @@ memory { device_type = "memory"; - reg = <0 0 0>; /* Filled in by zImage */ + reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by zImage */ }; UIC0: interrupt-controller0 { compatible = "ibm,uic-440spe","ibm,uic"; interrupt-controller; cell-index = <0>; - dcr-reg = <0c0 009>; + dcr-reg = <0x0c0 0x009>; #address-cells = <0>; #size-cells = <0>; #interrupt-cells = <2>; @@ -64,11 +66,11 @@ compatible = "ibm,uic-440spe","ibm,uic"; interrupt-controller; cell-index = <1>; - dcr-reg = <0d0 009>; + dcr-reg = <0x0d0 0x009>; #address-cells = <0>; #size-cells = <0>; #interrupt-cells = <2>; - interrupts = <1e 4 1f 4>; /* cascade */ + interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */ interrupt-parent = <&UIC0>; }; @@ -76,11 +78,11 @@ compatible = "ibm,uic-440spe","ibm,uic"; interrupt-controller; cell-index = <2>; - dcr-reg = <0e0 009>; + dcr-reg = <0x0e0 0x009>; #address-cells = <0>; #size-cells = <0>; #interrupt-cells = <2>; - interrupts = ; /* cascade */ + interrupts = <0xa 0x4 0xb 0x4>; /* cascade */ interrupt-parent = <&UIC0>; }; @@ -88,22 +90,22 @@ compatible = "ibm,uic-440spe","ibm,uic"; interrupt-controller; cell-index = <3>; - dcr-reg = <0f0 009>; + dcr-reg = <0x0f0 0x009>; #address-cells = <0>; #size-cells = <0>; #interrupt-cells = <2>; - interrupts = <10 4 11 4>; /* cascade */ + interrupts = <0x10 0x4 0x11 0x4>; /* cascade */ interrupt-parent = <&UIC0>; }; SDR0: sdr { compatible = "ibm,sdr-440spe"; - dcr-reg = <00e 002>; + dcr-reg = <0x00e 0x002>; }; CPR0: cpr { compatible = "ibm,cpr-440spe"; - dcr-reg = <00c 002>; + dcr-reg = <0x00c 0x002>; }; plb { @@ -115,108 +117,108 @@ SDRAM0: sdram { compatible = "ibm,sdram-440spe", "ibm,sdram-405gp"; - dcr-reg = <010 2>; + dcr-reg = <0x010 0x002>; }; MAL0: mcmal { compatible = "ibm,mcmal-440spe", "ibm,mcmal2"; - dcr-reg = <180 62>; + dcr-reg = <0x180 0x062>; num-tx-chans = <2>; num-rx-chans = <1>; interrupt-parent = <&MAL0>; - interrupts = <0 1 2 3 4>; + interrupts = <0x0 0x1 0x2 0x3 0x4>; #interrupt-cells = <1>; #address-cells = <0>; #size-cells = <0>; - interrupt-map = ; + interrupt-map = ; }; POB0: opb { compatible = "ibm,opb-440spe", "ibm,opb-440gp", "ibm,opb"; #address-cells = <1>; #size-cells = <1>; - ranges = <00000000 4 e0000000 20000000>; + ranges = <0x00000000 0x00000004 0xe0000000 0x20000000>; clock-frequency = <0>; /* Filled in by zImage */ EBC0: ebc { compatible = "ibm,ebc-440spe", "ibm,ebc-440gp", "ibm,ebc"; - dcr-reg = <012 2>; + dcr-reg = <0x012 0x002>; #address-cells = <2>; #size-cells = <1>; clock-frequency = <0>; /* Filled in by zImage */ - interrupts = <5 1>; + interrupts = <0x5 0x1>; interrupt-parent = <&UIC1>; }; UART0: serial@10000200 { device_type = "serial"; compatible = "ns16550"; - reg = <10000200 8>; - virtual-reg = ; + reg = <0x10000200 0x00000008>; + virtual-reg = <0xa0000200>; clock-frequency = <0>; /* Filled in by zImage */ - current-speed = <1c200>; + current-speed = <115200>; interrupt-parent = <&UIC0>; - interrupts = <0 4>; + interrupts = <0x0 0x4>; }; UART1: serial@10000300 { device_type = "serial"; compatible = "ns16550"; - reg = <10000300 8>; - virtual-reg = ; + reg = <0x10000300 0x00000008>; + virtual-reg = <0xa0000300>; clock-frequency = <0>; current-speed = <0>; interrupt-parent = <&UIC0>; - interrupts = <1 4>; + interrupts = <0x1 0x4>; }; UART2: serial@10000600 { device_type = "serial"; compatible = "ns16550"; - reg = <10000600 8>; - virtual-reg = ; + reg = <0x10000600 0x00000008>; + virtual-reg = <0xa0000600>; clock-frequency = <0>; current-speed = <0>; interrupt-parent = <&UIC1>; - interrupts = <5 4>; + interrupts = <0x5 0x4>; }; IIC0: i2c@10000400 { compatible = "ibm,iic-440spe", "ibm,iic-440gp", "ibm,iic"; - reg = <10000400 14>; + reg = <0x10000400 0x00000014>; interrupt-parent = <&UIC0>; - interrupts = <2 4>; + interrupts = <0x2 0x4>; }; IIC1: i2c@10000500 { compatible = "ibm,iic-440spe", "ibm,iic-440gp", "ibm,iic"; - reg = <10000500 14>; + reg = <0x10000500 0x00000014>; interrupt-parent = <&UIC0>; - interrupts = <3 4>; + interrupts = <0x3 0x4>; }; EMAC0: ethernet@10000800 { - linux,network-index = <0>; + linux,network-index = <0x0>; device_type = "network"; compatible = "ibm,emac-440spe", "ibm,emac4"; interrupt-parent = <&UIC1>; - interrupts = <1c 4 1d 4>; - reg = <10000800 70>; + interrupts = <0x1c 0x4 0x1d 0x4>; + reg = <0x10000800 0x00000070>; local-mac-address = [000000000000]; mal-device = <&MAL0>; mal-tx-channel = <0>; mal-rx-channel = <0>; cell-index = <0>; - max-frame-size = <2328>; - rx-fifo-size = <1000>; - tx-fifo-size = <800>; + max-frame-size = <9000>; + rx-fifo-size = <4096>; + tx-fifo-size = <2048>; phy-mode = "gmii"; - phy-map = <00000000>; + phy-map = <0x00000000>; has-inverted-stacr-oc; has-new-stacr-staopc; }; @@ -231,23 +233,23 @@ primary; large-inbound-windows; enable-msi-hole; - reg = ; /* Internal messaging registers */ + reg = <0x0000000c 0x0ec00000 0x00000008 /* Config space access */ + 0x00000000 0x00000000 0x00000000 /* no IACK cycles */ + 0x0000000c 0x0ed00000 0x00000004 /* Special cycles */ + 0x0000000c 0x0ec80000 0x00000100 /* Internal registers */ + 0x0000000c 0x0ec80100 0x000000fc>; /* Internal messaging registers */ /* Outbound ranges, one memory and one IO, * later cannot be changed */ - ranges = <02000000 0 80000000 0000000d 80000000 0 80000000 - 01000000 0 00000000 0000000c 08000000 0 00010000>; + ranges = <0x02000000 0x00000000 0x80000000 0x0000000d 0x80000000 0x00000000 0x80000000 + 0x01000000 0x00000000 0x00000000 0x0000000c 0x08000000 0x00000000 0x00010000>; /* Inbound 2GB range starting at 0 */ - dma-ranges = <42000000 0 0 0 0 0 80000000>; + dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>; /* This drives busses 0 to 0xf */ - bus-range = <0 f>; + bus-range = <0x0 0xf>; /* * On Katmai, the following PCI-X interrupts signals @@ -258,13 +260,13 @@ * INTC: J2: 1-2 * INTD: J1: 1-2 */ - interrupt-map-mask = ; + interrupt-map-mask = <0xf800 0x0 0x0 0x7>; interrupt-map = < /* IDSEL 1 */ - 0800 0 0 1 &UIC1 14 8 - 0800 0 0 2 &UIC1 13 8 - 0800 0 0 3 &UIC1 12 8 - 0800 0 0 4 &UIC1 11 8 + 0x800 0x0 0x0 0x1 &UIC1 0x14 0x8 + 0x800 0x0 0x0 0x2 &UIC1 0x13 0x8 + 0x800 0x0 0x0 0x3 &UIC1 0x12 0x8 + 0x800 0x0 0x0 0x4 &UIC1 0x11 0x8 >; }; @@ -275,23 +277,23 @@ #address-cells = <3>; compatible = "ibm,plb-pciex-440spe", "ibm,plb-pciex"; primary; - port = <0>; /* port number */ - reg = ; /* Registers */ - dcr-reg = <100 020>; - sdr-base = <300>; + port = <0x0>; /* port number */ + reg = <0x0000000d 0x00000000 0x20000000 /* Config space access */ + 0x0000000c 0x10000000 0x00001000>; /* Registers */ + dcr-reg = <0x100 0x020>; + sdr-base = <0x300>; /* Outbound ranges, one memory and one IO, * later cannot be changed */ - ranges = <02000000 0 80000000 0000000e 00000000 0 80000000 - 01000000 0 00000000 0000000f 80000000 0 00010000>; + ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x00000000 0x00000000 0x80000000 + 0x01000000 0x00000000 0x00000000 0x0000000f 0x80000000 0x00000000 0x00010000>; /* Inbound 2GB range starting at 0 */ - dma-ranges = <42000000 0 0 0 0 0 80000000>; + dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>; /* This drives busses 10 to 0x1f */ - bus-range = <10 1f>; + bus-range = <0x10 0x1f>; /* Legacy interrupts (note the weird polarity, the bridge seems * to invert PCIe legacy interrupts). @@ -301,12 +303,12 @@ * below are basically de-swizzled numbers. * The real slot is on idsel 0, so the swizzling is 1:1 */ - interrupt-map-mask = <0000 0 0 7>; + interrupt-map-mask = <0x0 0x0 0x0 0x7>; interrupt-map = < - 0000 0 0 1 &UIC3 0 4 /* swizzled int A */ - 0000 0 0 2 &UIC3 1 4 /* swizzled int B */ - 0000 0 0 3 &UIC3 2 4 /* swizzled int C */ - 0000 0 0 4 &UIC3 3 4 /* swizzled int D */>; + 0x0 0x0 0x0 0x1 &UIC3 0x0 0x4 /* swizzled int A */ + 0x0 0x0 0x0 0x2 &UIC3 0x1 0x4 /* swizzled int B */ + 0x0 0x0 0x0 0x3 &UIC3 0x2 0x4 /* swizzled int C */ + 0x0 0x0 0x0 0x4 &UIC3 0x3 0x4 /* swizzled int D */>; }; PCIE1: pciex@d20000000 { @@ -316,23 +318,23 @@ #address-cells = <3>; compatible = "ibm,plb-pciex-440spe", "ibm,plb-pciex"; primary; - port = <1>; /* port number */ - reg = ; /* Registers */ - dcr-reg = <120 020>; - sdr-base = <340>; + port = <0x1>; /* port number */ + reg = <0x0000000d 0x20000000 0x20000000 /* Config space access */ + 0x0000000c 0x10001000 0x00001000>; /* Registers */ + dcr-reg = <0x120 0x020>; + sdr-base = <0x340>; /* Outbound ranges, one memory and one IO, * later cannot be changed */ - ranges = <02000000 0 80000000 0000000e 80000000 0 80000000 - 01000000 0 00000000 0000000f 80010000 0 00010000>; + ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x80000000 0x00000000 0x80000000 + 0x01000000 0x00000000 0x00000000 0x0000000f 0x80010000 0x00000000 0x00010000>; /* Inbound 2GB range starting at 0 */ - dma-ranges = <42000000 0 0 0 0 0 80000000>; + dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>; /* This drives busses 10 to 0x1f */ - bus-range = <20 2f>; + bus-range = <0x20 0x2f>; /* Legacy interrupts (note the weird polarity, the bridge seems * to invert PCIe legacy interrupts). @@ -342,12 +344,12 @@ * below are basically de-swizzled numbers. * The real slot is on idsel 0, so the swizzling is 1:1 */ - interrupt-map-mask = <0000 0 0 7>; + interrupt-map-mask = <0x0 0x0 0x0 0x7>; interrupt-map = < - 0000 0 0 1 &UIC3 4 4 /* swizzled int A */ - 0000 0 0 2 &UIC3 5 4 /* swizzled int B */ - 0000 0 0 3 &UIC3 6 4 /* swizzled int C */ - 0000 0 0 4 &UIC3 7 4 /* swizzled int D */>; + 0x0 0x0 0x0 0x1 &UIC3 0x4 0x4 /* swizzled int A */ + 0x0 0x0 0x0 0x2 &UIC3 0x5 0x4 /* swizzled int B */ + 0x0 0x0 0x0 0x3 &UIC3 0x6 0x4 /* swizzled int C */ + 0x0 0x0 0x0 0x4 &UIC3 0x7 0x4 /* swizzled int D */>; }; PCIE2: pciex@d40000000 { @@ -357,23 +359,23 @@ #address-cells = <3>; compatible = "ibm,plb-pciex-440spe", "ibm,plb-pciex"; primary; - port = <2>; /* port number */ - reg = ; /* Registers */ - dcr-reg = <140 020>; - sdr-base = <370>; + port = <0x2>; /* port number */ + reg = <0x0000000d 0x40000000 0x20000000 /* Config space access */ + 0x0000000c 0x10002000 0x00001000>; /* Registers */ + dcr-reg = <0x140 0x020>; + sdr-base = <0x370>; /* Outbound ranges, one memory and one IO, * later cannot be changed */ - ranges = <02000000 0 80000000 0000000f 00000000 0 80000000 - 01000000 0 00000000 0000000f 80020000 0 00010000>; + ranges = <0x02000000 0x00000000 0x80000000 0x0000000f 0x00000000 0x00000000 0x80000000 + 0x01000000 0x00000000 0x00000000 0x0000000f 0x80020000 0x00000000 0x00010000>; /* Inbound 2GB range starting at 0 */ - dma-ranges = <42000000 0 0 0 0 0 80000000>; + dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>; /* This drives busses 10 to 0x1f */ - bus-range = <30 3f>; + bus-range = <0x30 0x3f>; /* Legacy interrupts (note the weird polarity, the bridge seems * to invert PCIe legacy interrupts). @@ -383,12 +385,12 @@ * below are basically de-swizzled numbers. * The real slot is on idsel 0, so the swizzling is 1:1 */ - interrupt-map-mask = <0000 0 0 7>; + interrupt-map-mask = <0x0 0x0 0x0 0x7>; interrupt-map = < - 0000 0 0 1 &UIC3 8 4 /* swizzled int A */ - 0000 0 0 2 &UIC3 9 4 /* swizzled int B */ - 0000 0 0 3 &UIC3 a 4 /* swizzled int C */ - 0000 0 0 4 &UIC3 b 4 /* swizzled int D */>; + 0x0 0x0 0x0 0x1 &UIC3 0x8 0x4 /* swizzled int A */ + 0x0 0x0 0x0 0x2 &UIC3 0x9 0x4 /* swizzled int B */ + 0x0 0x0 0x0 0x3 &UIC3 0xa 0x4 /* swizzled int C */ + 0x0 0x0 0x0 0x4 &UIC3 0xb 0x4 /* swizzled int D */>; }; }; diff --git a/arch/powerpc/boot/dts/kilauea.dts b/arch/powerpc/boot/dts/kilauea.dts index 48c9a6e..3ed6a8f 100644 --- a/arch/powerpc/boot/dts/kilauea.dts +++ b/arch/powerpc/boot/dts/kilauea.dts @@ -8,12 +8,14 @@ * any warranty of any kind, whether express or implied. */ +/dts-v1/; + / { #address-cells = <1>; #size-cells = <1>; model = "amcc,kilauea"; compatible = "amcc,kilauea"; - dcr-parent = <&/cpus/cpu@0>; + dcr-parent = <&{/cpus/cpu@0}>; aliases { ethernet0 = &EMAC0; @@ -29,13 +31,13 @@ cpu@0 { device_type = "cpu"; model = "PowerPC,405EX"; - reg = <0>; + reg = <0x00000000>; clock-frequency = <0>; /* Filled in by U-Boot */ timebase-frequency = <0>; /* Filled in by U-Boot */ - i-cache-line-size = <20>; - d-cache-line-size = <20>; - i-cache-size = <4000>; /* 16 kB */ - d-cache-size = <4000>; /* 16 kB */ + i-cache-line-size = <32>; + d-cache-line-size = <32>; + i-cache-size = <16384>; /* 16 kB */ + d-cache-size = <16384>; /* 16 kB */ dcr-controller; dcr-access-method = "native"; }; @@ -43,14 +45,14 @@ memory { device_type = "memory"; - reg = <0 0>; /* Filled in by U-Boot */ + reg = <0x00000000 0x00000000>; /* Filled in by U-Boot */ }; UIC0: interrupt-controller { compatible = "ibm,uic-405ex", "ibm,uic"; interrupt-controller; cell-index = <0>; - dcr-reg = <0c0 009>; + dcr-reg = <0x0c0 0x009>; #address-cells = <0>; #size-cells = <0>; #interrupt-cells = <2>; @@ -60,11 +62,11 @@ compatible = "ibm,uic-405ex","ibm,uic"; interrupt-controller; cell-index = <1>; - dcr-reg = <0d0 009>; + dcr-reg = <0x0d0 0x009>; #address-cells = <0>; #size-cells = <0>; #interrupt-cells = <2>; - interrupts = <1e 4 1f 4>; /* cascade */ + interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */ interrupt-parent = <&UIC0>; }; @@ -72,11 +74,11 @@ compatible = "ibm,uic-405ex","ibm,uic"; interrupt-controller; cell-index = <2>; - dcr-reg = <0e0 009>; + dcr-reg = <0x0e0 0x009>; #address-cells = <0>; #size-cells = <0>; #interrupt-cells = <2>; - interrupts = <1c 4 1d 4>; /* cascade */ + interrupts = <0x1c 0x4 0x1d 0x4>; /* cascade */ interrupt-parent = <&UIC0>; }; @@ -89,72 +91,72 @@ SDRAM0: memory-controller { compatible = "ibm,sdram-405ex"; - dcr-reg = <010 2>; + dcr-reg = <0x010 0x002>; }; MAL0: mcmal { compatible = "ibm,mcmal-405ex", "ibm,mcmal2"; - dcr-reg = <180 62>; + dcr-reg = <0x180 0x062>; num-tx-chans = <2>; num-rx-chans = <2>; interrupt-parent = <&MAL0>; - interrupts = <0 1 2 3 4>; + interrupts = <0x0 0x1 0x2 0x3 0x4>; #interrupt-cells = <1>; #address-cells = <0>; #size-cells = <0>; - interrupt-map = ; - interrupt-map-mask = ; + interrupt-map = ; + interrupt-map-mask = <0xffffffff>; }; POB0: opb { compatible = "ibm,opb-405ex", "ibm,opb"; #address-cells = <1>; #size-cells = <1>; - ranges = <80000000 80000000 10000000 - ef600000 ef600000 a00000 - f0000000 f0000000 10000000>; - dcr-reg = <0a0 5>; + ranges = <0x80000000 0x80000000 0x10000000 + 0xef600000 0xef600000 0x00a00000 + 0xf0000000 0xf0000000 0x10000000>; + dcr-reg = <0x0a0 0x005>; clock-frequency = <0>; /* Filled in by U-Boot */ EBC0: ebc { compatible = "ibm,ebc-405ex", "ibm,ebc"; - dcr-reg = <012 2>; + dcr-reg = <0x012 0x002>; #address-cells = <2>; #size-cells = <1>; clock-frequency = <0>; /* Filled in by U-Boot */ /* ranges property is supplied by U-Boot */ - interrupts = <5 1>; + interrupts = <0x5 0x1>; interrupt-parent = <&UIC1>; nor_flash@0,0 { compatible = "amd,s29gl512n", "cfi-flash"; bank-width = <2>; - reg = <0 000000 4000000>; + reg = <0x00000000 0x00000000 0x04000000>; #address-cells = <1>; #size-cells = <1>; partition@0 { label = "kernel"; - reg = <0 200000>; + reg = <0x00000000 0x00200000>; }; partition@200000 { label = "root"; - reg = <200000 200000>; + reg = <0x00200000 0x00200000>; }; partition@400000 { label = "user"; - reg = <400000 3b60000>; + reg = <0x00400000 0x03b60000>; }; partition@3f60000 { label = "env"; - reg = <3f60000 40000>; + reg = <0x03f60000 0x00040000>; }; partition@3fa0000 { label = "u-boot"; - reg = <3fa0000 60000>; + reg = <0x03fa0000 0x00060000>; }; }; }; @@ -162,68 +164,68 @@ UART0: serial@ef600200 { device_type = "serial"; compatible = "ns16550"; - reg = ; - virtual-reg = ; + reg = <0xef600200 0x00000008>; + virtual-reg = <0xef600200>; clock-frequency = <0>; /* Filled in by U-Boot */ current-speed = <0>; interrupt-parent = <&UIC0>; - interrupts = <1a 4>; + interrupts = <0x1a 0x4>; }; UART1: serial@ef600300 { device_type = "serial"; compatible = "ns16550"; - reg = ; - virtual-reg = ; + reg = <0xef600300 0x00000008>; + virtual-reg = <0xef600300>; clock-frequency = <0>; /* Filled in by U-Boot */ current-speed = <0>; interrupt-parent = <&UIC0>; - interrupts = <1 4>; + interrupts = <0x1 0x4>; }; IIC0: i2c@ef600400 { compatible = "ibm,iic-405ex", "ibm,iic"; - reg = ; + reg = <0xef600400 0x00000014>; interrupt-parent = <&UIC0>; - interrupts = <2 4>; + interrupts = <0x2 0x4>; }; IIC1: i2c@ef600500 { compatible = "ibm,iic-405ex", "ibm,iic"; - reg = ; + reg = <0xef600500 0x00000014>; interrupt-parent = <&UIC0>; - interrupts = <7 4>; + interrupts = <0x7 0x4>; }; RGMII0: emac-rgmii@ef600b00 { compatible = "ibm,rgmii-405ex", "ibm,rgmii"; - reg = ; + reg = <0xef600b00 0x00000104>; has-mdio; }; EMAC0: ethernet@ef600900 { - linux,network-index = <0>; + linux,network-index = <0x0>; device_type = "network"; compatible = "ibm,emac-405ex", "ibm,emac4"; interrupt-parent = <&EMAC0>; - interrupts = <0 1>; + interrupts = <0x0 0x1>; #interrupt-cells = <1>; #address-cells = <0>; #size-cells = <0>; - interrupt-map = ; - reg = ; + interrupt-map = ; + reg = <0xef600900 0x00000070>; local-mac-address = [000000000000]; /* Filled in by U-Boot */ mal-device = <&MAL0>; mal-tx-channel = <0>; mal-rx-channel = <0>; cell-index = <0>; - max-frame-size = <2328>; - rx-fifo-size = <1000>; - tx-fifo-size = <800>; + max-frame-size = <9000>; + rx-fifo-size = <4096>; + tx-fifo-size = <2048>; phy-mode = "rgmii"; - phy-map = <00000000>; + phy-map = <0x00000000>; rgmii-device = <&RGMII0>; rgmii-channel = <0>; has-inverted-stacr-oc; @@ -231,27 +233,27 @@ }; EMAC1: ethernet@ef600a00 { - linux,network-index = <1>; + linux,network-index = <0x1>; device_type = "network"; compatible = "ibm,emac-405ex", "ibm,emac4"; interrupt-parent = <&EMAC1>; - interrupts = <0 1>; + interrupts = <0x0 0x1>; #interrupt-cells = <1>; #address-cells = <0>; #size-cells = <0>; - interrupt-map = ; - reg = ; + interrupt-map = ; + reg = <0xef600a00 0x00000070>; local-mac-address = [000000000000]; /* Filled in by U-Boot */ mal-device = <&MAL0>; mal-tx-channel = <1>; mal-rx-channel = <1>; cell-index = <1>; - max-frame-size = <2328>; - rx-fifo-size = <1000>; - tx-fifo-size = <800>; + max-frame-size = <9000>; + rx-fifo-size = <4096>; + tx-fifo-size = <2048>; phy-mode = "rgmii"; - phy-map = <00000000>; + phy-map = <0x00000000>; rgmii-device = <&RGMII0>; rgmii-channel = <1>; has-inverted-stacr-oc; @@ -266,23 +268,23 @@ #address-cells = <3>; compatible = "ibm,plb-pciex-405ex", "ibm,plb-pciex"; primary; - port = <0>; /* port number */ - reg = ; /* Registers */ - dcr-reg = <040 020>; - sdr-base = <400>; + port = <0x0>; /* port number */ + reg = <0xa0000000 0x20000000 /* Config space access */ + 0xef000000 0x00001000>; /* Registers */ + dcr-reg = <0x040 0x020>; + sdr-base = <0x400>; /* Outbound ranges, one memory and one IO, * later cannot be changed */ - ranges = <02000000 0 80000000 90000000 0 08000000 - 01000000 0 00000000 e0000000 0 00010000>; + ranges = <0x02000000 0x00000000 0x80000000 0x90000000 0x00000000 0x08000000 + 0x01000000 0x00000000 0x00000000 0xe0000000 0x00000000 0x00010000>; /* Inbound 2GB range starting at 0 */ - dma-ranges = <42000000 0 0 0 0 80000000>; + dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x80000000>; /* This drives busses 0x00 to 0x3f */ - bus-range = <00 3f>; + bus-range = <0x0 0x3f>; /* Legacy interrupts (note the weird polarity, the bridge seems * to invert PCIe legacy interrupts). @@ -292,12 +294,12 @@ * below are basically de-swizzled numbers. * The real slot is on idsel 0, so the swizzling is 1:1 */ - interrupt-map-mask = <0000 0 0 7>; + interrupt-map-mask = <0x0 0x0 0x0 0x7>; interrupt-map = < - 0000 0 0 1 &UIC2 0 4 /* swizzled int A */ - 0000 0 0 2 &UIC2 1 4 /* swizzled int B */ - 0000 0 0 3 &UIC2 2 4 /* swizzled int C */ - 0000 0 0 4 &UIC2 3 4 /* swizzled int D */>; + 0x0 0x0 0x0 0x1 &UIC2 0x0 0x4 /* swizzled int A */ + 0x0 0x0 0x0 0x2 &UIC2 0x1 0x4 /* swizzled int B */ + 0x0 0x0 0x0 0x3 &UIC2 0x2 0x4 /* swizzled int C */ + 0x0 0x0 0x0 0x4 &UIC2 0x3 0x4 /* swizzled int D */>; }; PCIE1: pciex@0c0000000 { @@ -307,23 +309,23 @@ #address-cells = <3>; compatible = "ibm,plb-pciex-405ex", "ibm,plb-pciex"; primary; - port = <1>; /* port number */ - reg = ; /* Registers */ - dcr-reg = <060 020>; - sdr-base = <440>; + port = <0x1>; /* port number */ + reg = <0xc0000000 0x20000000 /* Config space access */ + 0xef001000 0x00001000>; /* Registers */ + dcr-reg = <0x060 0x020>; + sdr-base = <0x440>; /* Outbound ranges, one memory and one IO, * later cannot be changed */ - ranges = <02000000 0 80000000 98000000 0 08000000 - 01000000 0 00000000 e0010000 0 00010000>; + ranges = <0x02000000 0x00000000 0x80000000 0x98000000 0x00000000 0x08000000 + 0x01000000 0x00000000 0x00000000 0xe0010000 0x00000000 0x00010000>; /* Inbound 2GB range starting at 0 */ - dma-ranges = <42000000 0 0 0 0 80000000>; + dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x80000000>; /* This drives busses 0x40 to 0x7f */ - bus-range = <40 7f>; + bus-range = <0x40 0x7f>; /* Legacy interrupts (note the weird polarity, the bridge seems * to invert PCIe legacy interrupts). @@ -333,12 +335,12 @@ * below are basically de-swizzled numbers. * The real slot is on idsel 0, so the swizzling is 1:1 */ - interrupt-map-mask = <0000 0 0 7>; + interrupt-map-mask = <0x0 0x0 0x0 0x7>; interrupt-map = < - 0000 0 0 1 &UIC2 b 4 /* swizzled int A */ - 0000 0 0 2 &UIC2 c 4 /* swizzled int B */ - 0000 0 0 3 &UIC2 d 4 /* swizzled int C */ - 0000 0 0 4 &UIC2 e 4 /* swizzled int D */>; + 0x0 0x0 0x0 0x1 &UIC2 0xb 0x4 /* swizzled int A */ + 0x0 0x0 0x0 0x2 &UIC2 0xc 0x4 /* swizzled int B */ + 0x0 0x0 0x0 0x3 &UIC2 0xd 0x4 /* swizzled int C */ + 0x0 0x0 0x0 0x4 &UIC2 0xe 0x4 /* swizzled int D */>; }; }; }; diff --git a/arch/powerpc/boot/dts/makalu.dts b/arch/powerpc/boot/dts/makalu.dts index 84cc5e7..1dfcd7e 100644 --- a/arch/powerpc/boot/dts/makalu.dts +++ b/arch/powerpc/boot/dts/makalu.dts @@ -8,12 +8,14 @@ * any warranty of any kind, whether express or implied. */ +/dts-v1/; + / { #address-cells = <1>; #size-cells = <1>; model = "amcc,makalu"; compatible = "amcc,makalu"; - dcr-parent = <&/cpus/cpu@0>; + dcr-parent = <&{/cpus/cpu@0}>; aliases { ethernet0 = &EMAC0; @@ -29,13 +31,13 @@ cpu@0 { device_type = "cpu"; model = "PowerPC,405EX"; - reg = <0>; + reg = <0x00000000>; clock-frequency = <0>; /* Filled in by U-Boot */ timebase-frequency = <0>; /* Filled in by U-Boot */ - i-cache-line-size = <20>; - d-cache-line-size = <20>; - i-cache-size = <4000>; /* 16 kB */ - d-cache-size = <4000>; /* 16 kB */ + i-cache-line-size = <32>; + d-cache-line-size = <32>; + i-cache-size = <16384>; /* 16 kB */ + d-cache-size = <16384>; /* 16 kB */ dcr-controller; dcr-access-method = "native"; }; @@ -43,14 +45,14 @@ memory { device_type = "memory"; - reg = <0 0>; /* Filled in by U-Boot */ + reg = <0x00000000 0x00000000>; /* Filled in by U-Boot */ }; UIC0: interrupt-controller { compatible = "ibm,uic-405ex", "ibm,uic"; interrupt-controller; cell-index = <0>; - dcr-reg = <0c0 009>; + dcr-reg = <0x0c0 0x009>; #address-cells = <0>; #size-cells = <0>; #interrupt-cells = <2>; @@ -60,11 +62,11 @@ compatible = "ibm,uic-405ex","ibm,uic"; interrupt-controller; cell-index = <1>; - dcr-reg = <0d0 009>; + dcr-reg = <0x0d0 0x009>; #address-cells = <0>; #size-cells = <0>; #interrupt-cells = <2>; - interrupts = <1e 4 1f 4>; /* cascade */ + interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */ interrupt-parent = <&UIC0>; }; @@ -72,11 +74,11 @@ compatible = "ibm,uic-405ex","ibm,uic"; interrupt-controller; cell-index = <2>; - dcr-reg = <0e0 009>; + dcr-reg = <0x0e0 0x009>; #address-cells = <0>; #size-cells = <0>; #interrupt-cells = <2>; - interrupts = <1c 4 1d 4>; /* cascade */ + interrupts = <0x1c 0x4 0x1d 0x4>; /* cascade */ interrupt-parent = <&UIC0>; }; @@ -89,72 +91,72 @@ SDRAM0: memory-controller { compatible = "ibm,sdram-405ex"; - dcr-reg = <010 2>; + dcr-reg = <0x010 0x002>; }; MAL0: mcmal { compatible = "ibm,mcmal-405ex", "ibm,mcmal2"; - dcr-reg = <180 62>; + dcr-reg = <0x180 0x062>; num-tx-chans = <2>; num-rx-chans = <2>; interrupt-parent = <&MAL0>; - interrupts = <0 1 2 3 4>; + interrupts = <0x0 0x1 0x2 0x3 0x4>; #interrupt-cells = <1>; #address-cells = <0>; #size-cells = <0>; - interrupt-map = ; - interrupt-map-mask = ; + interrupt-map = ; + interrupt-map-mask = <0xffffffff>; }; POB0: opb { compatible = "ibm,opb-405ex", "ibm,opb"; #address-cells = <1>; #size-cells = <1>; - ranges = <80000000 80000000 10000000 - ef600000 ef600000 a00000 - f0000000 f0000000 10000000>; - dcr-reg = <0a0 5>; + ranges = <0x80000000 0x80000000 0x10000000 + 0xef600000 0xef600000 0x00a00000 + 0xf0000000 0xf0000000 0x10000000>; + dcr-reg = <0x0a0 0x005>; clock-frequency = <0>; /* Filled in by U-Boot */ EBC0: ebc { compatible = "ibm,ebc-405ex", "ibm,ebc"; - dcr-reg = <012 2>; + dcr-reg = <0x012 0x002>; #address-cells = <2>; #size-cells = <1>; clock-frequency = <0>; /* Filled in by U-Boot */ /* ranges property is supplied by U-Boot */ - interrupts = <5 1>; + interrupts = <0x5 0x1>; interrupt-parent = <&UIC1>; nor_flash@0,0 { compatible = "amd,s29gl512n", "cfi-flash"; bank-width = <2>; - reg = <0 000000 4000000>; + reg = <0x00000000 0x00000000 0x04000000>; #address-cells = <1>; #size-cells = <1>; partition@0 { label = "kernel"; - reg = <0 200000>; + reg = <0x00000000 0x00200000>; }; partition@200000 { label = "root"; - reg = <200000 200000>; + reg = <0x00200000 0x00200000>; }; partition@400000 { label = "user"; - reg = <400000 3b60000>; + reg = <0x00400000 0x03b60000>; }; partition@3f60000 { label = "env"; - reg = <3f60000 40000>; + reg = <0x03f60000 0x00040000>; }; partition@3fa0000 { label = "u-boot"; - reg = <3fa0000 60000>; + reg = <0x03fa0000 0x00060000>; }; }; }; @@ -162,68 +164,68 @@ UART0: serial@ef600200 { device_type = "serial"; compatible = "ns16550"; - reg = ; - virtual-reg = ; + reg = <0xef600200 0x00000008>; + virtual-reg = <0xef600200>; clock-frequency = <0>; /* Filled in by U-Boot */ current-speed = <0>; interrupt-parent = <&UIC0>; - interrupts = <1a 4>; + interrupts = <0x1a 0x4>; }; UART1: serial@ef600300 { device_type = "serial"; compatible = "ns16550"; - reg = ; - virtual-reg = ; + reg = <0xef600300 0x00000008>; + virtual-reg = <0xef600300>; clock-frequency = <0>; /* Filled in by U-Boot */ current-speed = <0>; interrupt-parent = <&UIC0>; - interrupts = <1 4>; + interrupts = <0x1 0x4>; }; IIC0: i2c@ef600400 { compatible = "ibm,iic-405ex", "ibm,iic"; - reg = ; + reg = <0xef600400 0x00000014>; interrupt-parent = <&UIC0>; - interrupts = <2 4>; + interrupts = <0x2 0x4>; }; IIC1: i2c@ef600500 { compatible = "ibm,iic-405ex", "ibm,iic"; - reg = ; + reg = <0xef600500 0x00000014>; interrupt-parent = <&UIC0>; - interrupts = <7 4>; + interrupts = <0x7 0x4>; }; RGMII0: emac-rgmii@ef600b00 { compatible = "ibm,rgmii-405ex", "ibm,rgmii"; - reg = ; + reg = <0xef600b00 0x00000104>; has-mdio; }; EMAC0: ethernet@ef600900 { - linux,network-index = <0>; + linux,network-index = <0x0>; device_type = "network"; compatible = "ibm,emac-405ex", "ibm,emac4"; interrupt-parent = <&EMAC0>; - interrupts = <0 1>; + interrupts = <0x0 0x1>; #interrupt-cells = <1>; #address-cells = <0>; #size-cells = <0>; - interrupt-map = ; - reg = ; + interrupt-map = ; + reg = <0xef600900 0x00000070>; local-mac-address = [000000000000]; /* Filled in by U-Boot */ mal-device = <&MAL0>; mal-tx-channel = <0>; mal-rx-channel = <0>; cell-index = <0>; - max-frame-size = <2328>; - rx-fifo-size = <1000>; - tx-fifo-size = <800>; + max-frame-size = <9000>; + rx-fifo-size = <4096>; + tx-fifo-size = <2048>; phy-mode = "rgmii"; - phy-map = <0000003f>; /* Start at 6 */ + phy-map = <0x0000003f>; /* Start at 6 */ rgmii-device = <&RGMII0>; rgmii-channel = <0>; has-inverted-stacr-oc; @@ -231,27 +233,27 @@ }; EMAC1: ethernet@ef600a00 { - linux,network-index = <1>; + linux,network-index = <0x1>; device_type = "network"; compatible = "ibm,emac-405ex", "ibm,emac4"; interrupt-parent = <&EMAC1>; - interrupts = <0 1>; + interrupts = <0x0 0x1>; #interrupt-cells = <1>; #address-cells = <0>; #size-cells = <0>; - interrupt-map = ; - reg = ; + interrupt-map = ; + reg = <0xef600a00 0x00000070>; local-mac-address = [000000000000]; /* Filled in by U-Boot */ mal-device = <&MAL0>; mal-tx-channel = <1>; mal-rx-channel = <1>; cell-index = <1>; - max-frame-size = <2328>; - rx-fifo-size = <1000>; - tx-fifo-size = <800>; + max-frame-size = <9000>; + rx-fifo-size = <4096>; + tx-fifo-size = <2048>; phy-mode = "rgmii"; - phy-map = <00000000>; + phy-map = <0x00000000>; rgmii-device = <&RGMII0>; rgmii-channel = <1>; has-inverted-stacr-oc; @@ -266,23 +268,23 @@ #address-cells = <3>; compatible = "ibm,plb-pciex-405ex", "ibm,plb-pciex"; primary; - port = <0>; /* port number */ - reg = ; /* Registers */ - dcr-reg = <040 020>; - sdr-base = <400>; + port = <0x0>; /* port number */ + reg = <0xa0000000 0x20000000 /* Config space access */ + 0xef000000 0x00001000>; /* Registers */ + dcr-reg = <0x040 0x020>; + sdr-base = <0x400>; /* Outbound ranges, one memory and one IO, * later cannot be changed */ - ranges = <02000000 0 80000000 90000000 0 08000000 - 01000000 0 00000000 e0000000 0 00010000>; + ranges = <0x02000000 0x00000000 0x80000000 0x90000000 0x00000000 0x08000000 + 0x01000000 0x00000000 0x00000000 0xe0000000 0x00000000 0x00010000>; /* Inbound 2GB range starting at 0 */ - dma-ranges = <42000000 0 0 0 0 80000000>; + dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x80000000>; /* This drives busses 0x00 to 0x3f */ - bus-range = <00 3f>; + bus-range = <0x0 0x3f>; /* Legacy interrupts (note the weird polarity, the bridge seems * to invert PCIe legacy interrupts). @@ -292,12 +294,12 @@ * below are basically de-swizzled numbers. * The real slot is on idsel 0, so the swizzling is 1:1 */ - interrupt-map-mask = <0000 0 0 7>; + interrupt-map-mask = <0x0 0x0 0x0 0x7>; interrupt-map = < - 0000 0 0 1 &UIC2 0 4 /* swizzled int A */ - 0000 0 0 2 &UIC2 1 4 /* swizzled int B */ - 0000 0 0 3 &UIC2 2 4 /* swizzled int C */ - 0000 0 0 4 &UIC2 3 4 /* swizzled int D */>; + 0x0 0x0 0x0 0x1 &UIC2 0x0 0x4 /* swizzled int A */ + 0x0 0x0 0x0 0x2 &UIC2 0x1 0x4 /* swizzled int B */ + 0x0 0x0 0x0 0x3 &UIC2 0x2 0x4 /* swizzled int C */ + 0x0 0x0 0x0 0x4 &UIC2 0x3 0x4 /* swizzled int D */>; }; PCIE1: pciex@0c0000000 { @@ -307,23 +309,23 @@ #address-cells = <3>; compatible = "ibm,plb-pciex-405ex", "ibm,plb-pciex"; primary; - port = <1>; /* port number */ - reg = ; /* Registers */ - dcr-reg = <060 020>; - sdr-base = <440>; + port = <0x1>; /* port number */ + reg = <0xc0000000 0x20000000 /* Config space access */ + 0xef001000 0x00001000>; /* Registers */ + dcr-reg = <0x060 0x020>; + sdr-base = <0x440>; /* Outbound ranges, one memory and one IO, * later cannot be changed */ - ranges = <02000000 0 80000000 98000000 0 08000000 - 01000000 0 00000000 e0010000 0 00010000>; + ranges = <0x02000000 0x00000000 0x80000000 0x98000000 0x00000000 0x08000000 + 0x01000000 0x00000000 0x00000000 0xe0010000 0x00000000 0x00010000>; /* Inbound 2GB range starting at 0 */ - dma-ranges = <42000000 0 0 0 0 80000000>; + dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x80000000>; /* This drives busses 0x40 to 0x7f */ - bus-range = <40 7f>; + bus-range = <0x40 0x7f>; /* Legacy interrupts (note the weird polarity, the bridge seems * to invert PCIe legacy interrupts). @@ -333,12 +335,12 @@ * below are basically de-swizzled numbers. * The real slot is on idsel 0, so the swizzling is 1:1 */ - interrupt-map-mask = <0000 0 0 7>; + interrupt-map-mask = <0x0 0x0 0x0 0x7>; interrupt-map = < - 0000 0 0 1 &UIC2 b 4 /* swizzled int A */ - 0000 0 0 2 &UIC2 c 4 /* swizzled int B */ - 0000 0 0 3 &UIC2 d 4 /* swizzled int C */ - 0000 0 0 4 &UIC2 e 4 /* swizzled int D */>; + 0x0 0x0 0x0 0x1 &UIC2 0xb 0x4 /* swizzled int A */ + 0x0 0x0 0x0 0x2 &UIC2 0xc 0x4 /* swizzled int B */ + 0x0 0x0 0x0 0x3 &UIC2 0xd 0x4 /* swizzled int C */ + 0x0 0x0 0x0 0x4 &UIC2 0xe 0x4 /* swizzled int D */>; }; }; }; diff --git a/arch/powerpc/boot/dts/ps3.dts b/arch/powerpc/boot/dts/ps3.dts index 379ded2..96ba5b5 100644 --- a/arch/powerpc/boot/dts/ps3.dts +++ b/arch/powerpc/boot/dts/ps3.dts @@ -18,6 +18,8 @@ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ +/dts-v1/; + / { model = "SonyPS3"; compatible = "sony,ps3"; @@ -34,7 +36,7 @@ memory { device_type = "memory"; - reg = <0 0 0 0>; + reg = <0x00000000 0x00000000 0x00000000 0x00000000>; }; /* @@ -55,14 +57,14 @@ cpu@0 { device_type = "cpu"; - reg = <0>; - ibm,ppc-interrupt-server#s = <0 1>; + reg = <0x00000000>; + ibm,ppc-interrupt-server#s = <0x0 0x1>; clock-frequency = <0>; timebase-frequency = <0>; - i-cache-size = <8000>; - d-cache-size = <8000>; - i-cache-line-size = <80>; - d-cache-line-size = <80>; + i-cache-size = <32768>; + d-cache-size = <32768>; + i-cache-line-size = <128>; + d-cache-line-size = <128>; }; }; }; diff --git a/arch/powerpc/boot/dts/rainier.dts b/arch/powerpc/boot/dts/rainier.dts index 6a8fa70..2cd87f6 100644 --- a/arch/powerpc/boot/dts/rainier.dts +++ b/arch/powerpc/boot/dts/rainier.dts @@ -12,12 +12,14 @@ * */ +/dts-v1/; + / { #address-cells = <2>; #size-cells = <1>; model = "amcc,rainier"; compatible = "amcc,rainier"; - dcr-parent = <&/cpus/cpu@0>; + dcr-parent = <&{/cpus/cpu@0}>; aliases { ethernet0 = &EMAC0; @@ -35,13 +37,13 @@ cpu@0 { device_type = "cpu"; model = "PowerPC,440GRx"; - reg = <0>; + reg = <0x00000000>; clock-frequency = <0>; /* Filled in by zImage */ timebase-frequency = <0>; /* Filled in by zImage */ - i-cache-line-size = <20>; - d-cache-line-size = <20>; - i-cache-size = <8000>; - d-cache-size = <8000>; + i-cache-line-size = <32>; + d-cache-line-size = <32>; + i-cache-size = <32768>; + d-cache-size = <32768>; dcr-controller; dcr-access-method = "native"; }; @@ -49,14 +51,14 @@ memory { device_type = "memory"; - reg = <0 0 0>; /* Filled in by zImage */ + reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by zImage */ }; UIC0: interrupt-controller0 { compatible = "ibm,uic-440grx","ibm,uic"; interrupt-controller; cell-index = <0>; - dcr-reg = <0c0 009>; + dcr-reg = <0x0c0 0x009>; #address-cells = <0>; #size-cells = <0>; #interrupt-cells = <2>; @@ -66,11 +68,11 @@ compatible = "ibm,uic-440grx","ibm,uic"; interrupt-controller; cell-index = <1>; - dcr-reg = <0d0 009>; + dcr-reg = <0x0d0 0x009>; #address-cells = <0>; #size-cells = <0>; #interrupt-cells = <2>; - interrupts = <1e 4 1f 4>; /* cascade */ + interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */ interrupt-parent = <&UIC0>; }; @@ -78,22 +80,22 @@ compatible = "ibm,uic-440grx","ibm,uic"; interrupt-controller; cell-index = <2>; - dcr-reg = <0e0 009>; + dcr-reg = <0x0e0 0x009>; #address-cells = <0>; #size-cells = <0>; #interrupt-cells = <2>; - interrupts = <1c 4 1d 4>; /* cascade */ + interrupts = <0x1c 0x4 0x1d 0x4>; /* cascade */ interrupt-parent = <&UIC0>; }; SDR0: sdr { compatible = "ibm,sdr-440grx", "ibm,sdr-440ep"; - dcr-reg = <00e 002>; + dcr-reg = <0x00e 0x002>; }; CPR0: cpr { compatible = "ibm,cpr-440grx", "ibm,cpr-440ep"; - dcr-reg = <00c 002>; + dcr-reg = <0x00c 0x002>; }; plb { @@ -105,80 +107,80 @@ SDRAM0: sdram { compatible = "ibm,sdram-440grx", "ibm,sdram-44x-ddr2denali"; - dcr-reg = <010 2>; + dcr-reg = <0x010 0x002>; }; DMA0: dma { compatible = "ibm,dma-440grx", "ibm,dma-4xx"; - dcr-reg = <100 027>; + dcr-reg = <0x100 0x027>; }; MAL0: mcmal { compatible = "ibm,mcmal-440grx", "ibm,mcmal2"; - dcr-reg = <180 62>; + dcr-reg = <0x180 0x062>; num-tx-chans = <2>; num-rx-chans = <2>; interrupt-parent = <&MAL0>; - interrupts = <0 1 2 3 4>; + interrupts = <0x0 0x1 0x2 0x3 0x4>; #interrupt-cells = <1>; #address-cells = <0>; #size-cells = <0>; - interrupt-map = ; - interrupt-map-mask = ; + interrupt-map = ; + interrupt-map-mask = <0xffffffff>; }; POB0: opb { compatible = "ibm,opb-440grx", "ibm,opb"; #address-cells = <1>; #size-cells = <1>; - ranges = <00000000 1 00000000 80000000 - 80000000 1 80000000 80000000>; + ranges = <0x00000000 0x00000001 0x00000000 0x80000000 + 0x80000000 0x00000001 0x80000000 0x80000000>; interrupt-parent = <&UIC1>; - interrupts = <7 4>; + interrupts = <0x7 0x4>; clock-frequency = <0>; /* Filled in by zImage */ EBC0: ebc { compatible = "ibm,ebc-440grx", "ibm,ebc"; - dcr-reg = <012 2>; + dcr-reg = <0x012 0x002>; #address-cells = <2>; #size-cells = <1>; clock-frequency = <0>; /* Filled in by zImage */ - interrupts = <5 1>; + interrupts = <0x5 0x1>; interrupt-parent = <&UIC1>; nor_flash@0,0 { compatible = "amd,s29gl256n", "cfi-flash"; bank-width = <2>; - reg = <0 000000 4000000>; + reg = <0x00000000 0x00000000 0x04000000>; #address-cells = <1>; #size-cells = <1>; partition@0 { label = "Kernel"; - reg = <0 180000>; + reg = <0x00000000 0x00180000>; }; partition@180000 { label = "ramdisk"; - reg = <180000 200000>; + reg = <0x00180000 0x00200000>; }; partition@380000 { label = "file system"; - reg = <380000 3aa0000>; + reg = <0x00380000 0x03aa0000>; }; partition@3e20000 { label = "kozio"; - reg = <3e20000 140000>; + reg = <0x03e20000 0x00140000>; }; partition@3f60000 { label = "env"; - reg = <3f60000 40000>; + reg = <0x03f60000 0x00040000>; }; partition@3fa0000 { label = "u-boot"; - reg = <3fa0000 60000>; + reg = <0x03fa0000 0x00060000>; }; }; @@ -187,69 +189,69 @@ UART0: serial@ef600300 { device_type = "serial"; compatible = "ns16550"; - reg = ; - virtual-reg = ; + reg = <0xef600300 0x00000008>; + virtual-reg = <0xef600300>; clock-frequency = <0>; /* Filled in by zImage */ - current-speed = <1c200>; + current-speed = <115200>; interrupt-parent = <&UIC0>; - interrupts = <0 4>; + interrupts = <0x0 0x4>; }; UART1: serial@ef600400 { device_type = "serial"; compatible = "ns16550"; - reg = ; - virtual-reg = ; + reg = <0xef600400 0x00000008>; + virtual-reg = <0xef600400>; clock-frequency = <0>; current-speed = <0>; interrupt-parent = <&UIC0>; - interrupts = <1 4>; + interrupts = <0x1 0x4>; }; UART2: serial@ef600500 { device_type = "serial"; compatible = "ns16550"; - reg = ; - virtual-reg = ; + reg = <0xef600500 0x00000008>; + virtual-reg = <0xef600500>; clock-frequency = <0>; current-speed = <0>; interrupt-parent = <&UIC1>; - interrupts = <3 4>; + interrupts = <0x3 0x4>; }; UART3: serial@ef600600 { device_type = "serial"; compatible = "ns16550"; - reg = ; - virtual-reg = ; + reg = <0xef600600 0x00000008>; + virtual-reg = <0xef600600>; clock-frequency = <0>; current-speed = <0>; interrupt-parent = <&UIC1>; - interrupts = <4 4>; + interrupts = <0x4 0x4>; }; IIC0: i2c@ef600700 { compatible = "ibm,iic-440grx", "ibm,iic"; - reg = ; + reg = <0xef600700 0x00000014>; interrupt-parent = <&UIC0>; - interrupts = <2 4>; + interrupts = <0x2 0x4>; }; IIC1: i2c@ef600800 { compatible = "ibm,iic-440grx", "ibm,iic"; - reg = ; + reg = <0xef600800 0x00000014>; interrupt-parent = <&UIC0>; - interrupts = <7 4>; + interrupts = <0x7 0x4>; }; ZMII0: emac-zmii@ef600d00 { compatible = "ibm,zmii-440grx", "ibm,zmii"; - reg = ; + reg = <0xef600d00 0x0000000c>; }; RGMII0: emac-rgmii@ef601000 { compatible = "ibm,rgmii-440grx", "ibm,rgmii"; - reg = ; + reg = <0xef601000 0x00000008>; has-mdio; }; @@ -257,23 +259,23 @@ device_type = "network"; compatible = "ibm,emac-440grx", "ibm,emac-440epx", "ibm,emac4"; interrupt-parent = <&EMAC0>; - interrupts = <0 1>; + interrupts = <0x0 0x1>; #interrupt-cells = <1>; #address-cells = <0>; #size-cells = <0>; - interrupt-map = ; - reg = ; + interrupt-map = ; + reg = <0xef600e00 0x00000070>; local-mac-address = [000000000000]; mal-device = <&MAL0>; mal-tx-channel = <0>; mal-rx-channel = <0>; cell-index = <0>; - max-frame-size = <2328>; - rx-fifo-size = <1000>; - tx-fifo-size = <800>; + max-frame-size = <9000>; + rx-fifo-size = <4096>; + tx-fifo-size = <2048>; phy-mode = "rgmii"; - phy-map = <00000000>; + phy-map = <0x00000000>; zmii-device = <&ZMII0>; zmii-channel = <0>; rgmii-device = <&RGMII0>; @@ -286,23 +288,23 @@ device_type = "network"; compatible = "ibm,emac-440grx", "ibm,emac-440epx", "ibm,emac4"; interrupt-parent = <&EMAC1>; - interrupts = <0 1>; + interrupts = <0x0 0x1>; #interrupt-cells = <1>; #address-cells = <0>; #size-cells = <0>; - interrupt-map = ; - reg = ; + interrupt-map = ; + reg = <0xef600f00 0x00000070>; local-mac-address = [000000000000]; mal-device = <&MAL0>; mal-tx-channel = <1>; mal-rx-channel = <1>; cell-index = <1>; - max-frame-size = <2328>; - rx-fifo-size = <1000>; - tx-fifo-size = <800>; + max-frame-size = <9000>; + rx-fifo-size = <4096>; + tx-fifo-size = <2048>; phy-mode = "rgmii"; - phy-map = <00000000>; + phy-map = <0x00000000>; zmii-device = <&ZMII0>; zmii-channel = <1>; rgmii-device = <&RGMII0>; @@ -319,24 +321,24 @@ #address-cells = <3>; compatible = "ibm,plb440grx-pci", "ibm,plb-pci"; primary; - reg = <1 eec00000 8 /* Config space access */ - 1 eed00000 4 /* IACK */ - 1 eed00000 4 /* Special cycle */ - 1 ef400000 40>; /* Internal registers */ + reg = <0x00000001 0xeec00000 0x00000008 /* Config space access */ + 0x00000001 0xeed00000 0x00000004 /* IACK */ + 0x00000001 0xeed00000 0x00000004 /* Special cycle */ + 0x00000001 0xef400000 0x00000040>; /* Internal registers */ /* Outbound ranges, one memory and one IO, * later cannot be changed. Chip supports a second * IO range but we don't use it for now */ - ranges = <02000000 0 80000000 1 80000000 0 10000000 - 01000000 0 00000000 1 e8000000 0 00100000>; + ranges = <0x02000000 0x00000000 0x80000000 0x00000001 0x80000000 0x00000000 0x10000000 + 0x01000000 0x00000000 0x00000000 0x00000001 0xe8000000 0x00000000 0x00100000>; /* Inbound 2GB range starting at 0 */ - dma-ranges = <42000000 0 0 0 0 0 80000000>; + dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>; /* All PCI interrupts are routed to IRQ 67 */ - interrupt-map-mask = <0000 0 0 0>; - interrupt-map = < 0000 0 0 0 &UIC2 3 8 >; + interrupt-map-mask = <0x0 0x0 0x0 0x0>; + interrupt-map = < 0x0 0x0 0x0 0x0 &UIC2 0x3 0x8 >; }; }; diff --git a/arch/powerpc/boot/dts/sequoia.dts b/arch/powerpc/boot/dts/sequoia.dts index 72d6756..149dabc 100644 --- a/arch/powerpc/boot/dts/sequoia.dts +++ b/arch/powerpc/boot/dts/sequoia.dts @@ -12,12 +12,14 @@ * */ +/dts-v1/; + / { #address-cells = <2>; #size-cells = <1>; model = "amcc,sequoia"; compatible = "amcc,sequoia"; - dcr-parent = <&/cpus/cpu@0>; + dcr-parent = <&{/cpus/cpu@0}>; aliases { ethernet0 = &EMAC0; @@ -35,13 +37,13 @@ cpu@0 { device_type = "cpu"; model = "PowerPC,440EPx"; - reg = <0>; + reg = <0x00000000>; clock-frequency = <0>; /* Filled in by zImage */ timebase-frequency = <0>; /* Filled in by zImage */ - i-cache-line-size = <20>; - d-cache-line-size = <20>; - i-cache-size = <8000>; - d-cache-size = <8000>; + i-cache-line-size = <32>; + d-cache-line-size = <32>; + i-cache-size = <32768>; + d-cache-size = <32768>; dcr-controller; dcr-access-method = "native"; }; @@ -49,14 +51,14 @@ memory { device_type = "memory"; - reg = <0 0 0>; /* Filled in by zImage */ + reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by zImage */ }; UIC0: interrupt-controller0 { compatible = "ibm,uic-440epx","ibm,uic"; interrupt-controller; cell-index = <0>; - dcr-reg = <0c0 009>; + dcr-reg = <0x0c0 0x009>; #address-cells = <0>; #size-cells = <0>; #interrupt-cells = <2>; @@ -66,11 +68,11 @@ compatible = "ibm,uic-440epx","ibm,uic"; interrupt-controller; cell-index = <1>; - dcr-reg = <0d0 009>; + dcr-reg = <0x0d0 0x009>; #address-cells = <0>; #size-cells = <0>; #interrupt-cells = <2>; - interrupts = <1e 4 1f 4>; /* cascade */ + interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */ interrupt-parent = <&UIC0>; }; @@ -78,22 +80,22 @@ compatible = "ibm,uic-440epx","ibm,uic"; interrupt-controller; cell-index = <2>; - dcr-reg = <0e0 009>; + dcr-reg = <0x0e0 0x009>; #address-cells = <0>; #size-cells = <0>; #interrupt-cells = <2>; - interrupts = <1c 4 1d 4>; /* cascade */ + interrupts = <0x1c 0x4 0x1d 0x4>; /* cascade */ interrupt-parent = <&UIC0>; }; SDR0: sdr { compatible = "ibm,sdr-440epx", "ibm,sdr-440ep"; - dcr-reg = <00e 002>; + dcr-reg = <0x00e 0x002>; }; CPR0: cpr { compatible = "ibm,cpr-440epx", "ibm,cpr-440ep"; - dcr-reg = <00c 002>; + dcr-reg = <0x00c 0x002>; }; plb { @@ -105,44 +107,44 @@ SDRAM0: sdram { compatible = "ibm,sdram-440epx", "ibm,sdram-44x-ddr2denali"; - dcr-reg = <010 2>; + dcr-reg = <0x010 0x002>; }; DMA0: dma { compatible = "ibm,dma-440epx", "ibm,dma-4xx"; - dcr-reg = <100 027>; + dcr-reg = <0x100 0x027>; }; MAL0: mcmal { compatible = "ibm,mcmal-440epx", "ibm,mcmal2"; - dcr-reg = <180 62>; + dcr-reg = <0x180 0x062>; num-tx-chans = <2>; num-rx-chans = <2>; interrupt-parent = <&MAL0>; - interrupts = <0 1 2 3 4>; + interrupts = <0x0 0x1 0x2 0x3 0x4>; #interrupt-cells = <1>; #address-cells = <0>; #size-cells = <0>; - interrupt-map = ; - interrupt-map-mask = ; + interrupt-map = ; + interrupt-map-mask = <0xffffffff>; }; USB1: usb@e0000400 { compatible = "ohci-be"; - reg = <0 e0000400 60>; + reg = <0x00000000 0xe0000400 0x00000060>; interrupt-parent = <&UIC0>; - interrupts = <15 8>; + interrupts = <0x15 0x8>; }; USB0: ehci@e0000300 { compatible = "ibm,usb-ehci-440epx", "usb-ehci"; interrupt-parent = <&UIC0>; - interrupts = <1a 4>; - reg = <0 e0000300 90 0 e0000390 70>; + interrupts = <0x1a 0x4>; + reg = <0x00000000 0xe0000300 0x00000090 0x00000000 0xe0000390 0x00000070>; big-endian; }; @@ -150,50 +152,50 @@ compatible = "ibm,opb-440epx", "ibm,opb"; #address-cells = <1>; #size-cells = <1>; - ranges = <00000000 1 00000000 80000000 - 80000000 1 80000000 80000000>; + ranges = <0x00000000 0x00000001 0x00000000 0x80000000 + 0x80000000 0x00000001 0x80000000 0x80000000>; interrupt-parent = <&UIC1>; - interrupts = <7 4>; + interrupts = <0x7 0x4>; clock-frequency = <0>; /* Filled in by zImage */ EBC0: ebc { compatible = "ibm,ebc-440epx", "ibm,ebc"; - dcr-reg = <012 2>; + dcr-reg = <0x012 0x002>; #address-cells = <2>; #size-cells = <1>; clock-frequency = <0>; /* Filled in by zImage */ - interrupts = <5 1>; + interrupts = <0x5 0x1>; interrupt-parent = <&UIC1>; nor_flash@0,0 { compatible = "amd,s29gl256n", "cfi-flash"; bank-width = <2>; - reg = <0 000000 4000000>; + reg = <0x00000000 0x00000000 0x04000000>; #address-cells = <1>; #size-cells = <1>; partition@0 { label = "Kernel"; - reg = <0 180000>; + reg = <0x00000000 0x00180000>; }; partition@180000 { label = "ramdisk"; - reg = <180000 200000>; + reg = <0x00180000 0x00200000>; }; partition@380000 { label = "file system"; - reg = <380000 3aa0000>; + reg = <0x00380000 0x03aa0000>; }; partition@3e20000 { label = "kozio"; - reg = <3e20000 140000>; + reg = <0x03e20000 0x00140000>; }; partition@3f60000 { label = "env"; - reg = <3f60000 40000>; + reg = <0x03f60000 0x00040000>; }; partition@3fa0000 { label = "u-boot"; - reg = <3fa0000 60000>; + reg = <0x03fa0000 0x00060000>; }; }; @@ -202,69 +204,69 @@ UART0: serial@ef600300 { device_type = "serial"; compatible = "ns16550"; - reg = ; - virtual-reg = ; + reg = <0xef600300 0x00000008>; + virtual-reg = <0xef600300>; clock-frequency = <0>; /* Filled in by zImage */ - current-speed = <1c200>; + current-speed = <115200>; interrupt-parent = <&UIC0>; - interrupts = <0 4>; + interrupts = <0x0 0x4>; }; UART1: serial@ef600400 { device_type = "serial"; compatible = "ns16550"; - reg = ; - virtual-reg = ; + reg = <0xef600400 0x00000008>; + virtual-reg = <0xef600400>; clock-frequency = <0>; current-speed = <0>; interrupt-parent = <&UIC0>; - interrupts = <1 4>; + interrupts = <0x1 0x4>; }; UART2: serial@ef600500 { device_type = "serial"; compatible = "ns16550"; - reg = ; - virtual-reg = ; + reg = <0xef600500 0x00000008>; + virtual-reg = <0xef600500>; clock-frequency = <0>; current-speed = <0>; interrupt-parent = <&UIC1>; - interrupts = <3 4>; + interrupts = <0x3 0x4>; }; UART3: serial@ef600600 { device_type = "serial"; compatible = "ns16550"; - reg = ; - virtual-reg = ; + reg = <0xef600600 0x00000008>; + virtual-reg = <0xef600600>; clock-frequency = <0>; current-speed = <0>; interrupt-parent = <&UIC1>; - interrupts = <4 4>; + interrupts = <0x4 0x4>; }; IIC0: i2c@ef600700 { compatible = "ibm,iic-440epx", "ibm,iic"; - reg = ; + reg = <0xef600700 0x00000014>; interrupt-parent = <&UIC0>; - interrupts = <2 4>; + interrupts = <0x2 0x4>; }; IIC1: i2c@ef600800 { compatible = "ibm,iic-440epx", "ibm,iic"; - reg = ; + reg = <0xef600800 0x00000014>; interrupt-parent = <&UIC0>; - interrupts = <7 4>; + interrupts = <0x7 0x4>; }; ZMII0: emac-zmii@ef600d00 { compatible = "ibm,zmii-440epx", "ibm,zmii"; - reg = ; + reg = <0xef600d00 0x0000000c>; }; RGMII0: emac-rgmii@ef601000 { compatible = "ibm,rgmii-440epx", "ibm,rgmii"; - reg = ; + reg = <0xef601000 0x00000008>; has-mdio; }; @@ -272,23 +274,23 @@ device_type = "network"; compatible = "ibm,emac-440epx", "ibm,emac4"; interrupt-parent = <&EMAC0>; - interrupts = <0 1>; + interrupts = <0x0 0x1>; #interrupt-cells = <1>; #address-cells = <0>; #size-cells = <0>; - interrupt-map = ; - reg = ; + interrupt-map = ; + reg = <0xef600e00 0x00000070>; local-mac-address = [000000000000]; mal-device = <&MAL0>; mal-tx-channel = <0>; mal-rx-channel = <0>; cell-index = <0>; - max-frame-size = <2328>; - rx-fifo-size = <1000>; - tx-fifo-size = <800>; + max-frame-size = <9000>; + rx-fifo-size = <4096>; + tx-fifo-size = <2048>; phy-mode = "rgmii"; - phy-map = <00000000>; + phy-map = <0x00000000>; zmii-device = <&ZMII0>; zmii-channel = <0>; rgmii-device = <&RGMII0>; @@ -301,23 +303,23 @@ device_type = "network"; compatible = "ibm,emac-440epx", "ibm,emac4"; interrupt-parent = <&EMAC1>; - interrupts = <0 1>; + interrupts = <0x0 0x1>; #interrupt-cells = <1>; #address-cells = <0>; #size-cells = <0>; - interrupt-map = ; - reg = ; + interrupt-map = ; + reg = <0xef600f00 0x00000070>; local-mac-address = [000000000000]; mal-device = <&MAL0>; mal-tx-channel = <1>; mal-rx-channel = <1>; cell-index = <1>; - max-frame-size = <2328>; - rx-fifo-size = <1000>; - tx-fifo-size = <800>; + max-frame-size = <9000>; + rx-fifo-size = <4096>; + tx-fifo-size = <2048>; phy-mode = "rgmii"; - phy-map = <00000000>; + phy-map = <0x00000000>; zmii-device = <&ZMII0>; zmii-channel = <1>; rgmii-device = <&RGMII0>; @@ -334,10 +336,10 @@ #address-cells = <3>; compatible = "ibm,plb440epx-pci", "ibm,plb-pci"; primary; - reg = <1 eec00000 8 /* Config space access */ - 1 eed00000 4 /* IACK */ - 1 eed00000 4 /* Special cycle */ - 1 ef400000 40>; /* Internal registers */ + reg = <0x00000001 0xeec00000 0x00000008 /* Config space access */ + 0x00000001 0xeed00000 0x00000004 /* IACK */ + 0x00000001 0xeed00000 0x00000004 /* Special cycle */ + 0x00000001 0xef400000 0x00000040>; /* Internal registers */ /* Outbound ranges, one memory and one IO, * later cannot be changed. Chip supports a second @@ -347,16 +349,16 @@ * I/O 1 E800 0000 1 E800 FFFF 64KB * I/O 1 E880 0000 1 EBFF FFFF 56MB */ - ranges = <02000000 0 80000000 1 80000000 0 40000000 - 01000000 0 00000000 1 e8000000 0 00010000 - 01000000 0 00000000 1 e8800000 0 03800000>; + ranges = <0x02000000 0x00000000 0x80000000 0x00000001 0x80000000 0x00000000 0x40000000 + 0x01000000 0x00000000 0x00000000 0x00000001 0xe8000000 0x00000000 0x00010000 + 0x01000000 0x00000000 0x00000000 0x00000001 0xe8800000 0x00000000 0x03800000>; /* Inbound 2GB range starting at 0 */ - dma-ranges = <42000000 0 0 0 0 0 80000000>; + dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>; /* All PCI interrupts are routed to IRQ 67 */ - interrupt-map-mask = <0000 0 0 0>; - interrupt-map = < 0000 0 0 0 &UIC2 3 8 >; + interrupt-map-mask = <0x0 0x0 0x0 0x0>; + interrupt-map = < 0x0 0x0 0x0 0x0 &UIC2 0x3 0x8 >; }; }; diff --git a/arch/powerpc/boot/dts/taishan.dts b/arch/powerpc/boot/dts/taishan.dts index e808e1c..dcb7498 100644 --- a/arch/powerpc/boot/dts/taishan.dts +++ b/arch/powerpc/boot/dts/taishan.dts @@ -10,12 +10,14 @@ * any warranty of any kind, whether express or implied. */ +/dts-v1/; + / { #address-cells = <2>; #size-cells = <1>; model = "amcc,taishan"; compatible = "amcc,taishan"; - dcr-parent = <&/cpus/cpu@0>; + dcr-parent = <&{/cpus/cpu@0}>; aliases { ethernet0 = &EMAC2; @@ -31,13 +33,13 @@ cpu@0 { device_type = "cpu"; model = "PowerPC,440GX"; - reg = <0>; - clock-frequency = <2FAF0800>; // 800MHz + reg = <0x00000000>; + clock-frequency = <800000000>; // 800MHz timebase-frequency = <0>; // Filled in by zImage - i-cache-line-size = <32>; - d-cache-line-size = <32>; - i-cache-size = <8000>; /* 32 kB */ - d-cache-size = <8000>; /* 32 kB */ + i-cache-line-size = <50>; + d-cache-line-size = <50>; + i-cache-size = <32768>; /* 32 kB */ + d-cache-size = <32768>; /* 32 kB */ dcr-controller; dcr-access-method = "native"; }; @@ -45,7 +47,7 @@ memory { device_type = "memory"; - reg = <0 0 0>; // Filled in by zImage + reg = <0x00000000 0x00000000 0x00000000>; // Filled in by zImage }; @@ -53,7 +55,7 @@ compatible = "ibm,uic-440gx", "ibm,uic"; interrupt-controller; cell-index = <3>; - dcr-reg = <200 009>; + dcr-reg = <0x200 0x009>; #address-cells = <0>; #size-cells = <0>; #interrupt-cells = <2>; @@ -64,11 +66,11 @@ compatible = "ibm,uic-440gx", "ibm,uic"; interrupt-controller; cell-index = <0>; - dcr-reg = <0c0 009>; + dcr-reg = <0x0c0 0x009>; #address-cells = <0>; #size-cells = <0>; #interrupt-cells = <2>; - interrupts = <01 4 00 4>; /* cascade - first non-critical */ + interrupts = <0x1 0x4 0x0 0x4>; /* cascade - first non-critical */ interrupt-parent = <&UICB0>; }; @@ -77,11 +79,11 @@ compatible = "ibm,uic-440gx", "ibm,uic"; interrupt-controller; cell-index = <1>; - dcr-reg = <0d0 009>; + dcr-reg = <0x0d0 0x009>; #address-cells = <0>; #size-cells = <0>; #interrupt-cells = <2>; - interrupts = <03 4 02 4>; /* cascade */ + interrupts = <0x3 0x4 0x2 0x4>; /* cascade */ interrupt-parent = <&UICB0>; }; @@ -89,29 +91,29 @@ compatible = "ibm,uic-440gx", "ibm,uic"; interrupt-controller; cell-index = <2>; /* was 1 */ - dcr-reg = <210 009>; + dcr-reg = <0x210 0x009>; #address-cells = <0>; #size-cells = <0>; #interrupt-cells = <2>; - interrupts = <05 4 04 4>; /* cascade */ + interrupts = <0x5 0x4 0x4 0x4>; /* cascade */ interrupt-parent = <&UICB0>; }; CPC0: cpc { compatible = "ibm,cpc-440gp"; - dcr-reg = <0b0 003 0e0 010>; + dcr-reg = <0x0b0 0x003 0x0e0 0x010>; // FIXME: anything else? }; L2C0: l2c { compatible = "ibm,l2-cache-440gx", "ibm,l2-cache"; - dcr-reg = <20 8 /* Internal SRAM DCR's */ - 30 8>; /* L2 cache DCR's */ - cache-line-size = <20>; /* 32 bytes */ - cache-size = <40000>; /* L2, 256K */ + dcr-reg = <0x020 0x008 /* Internal SRAM DCR's */ + 0x030 0x008>; /* L2 cache DCR's */ + cache-line-size = <32>; /* 32 bytes */ + cache-size = <262144>; /* L2, 256K */ interrupt-parent = <&UIC2>; - interrupts = <17 1>; + interrupts = <0x17 0x1>; }; plb { @@ -119,41 +121,41 @@ #address-cells = <2>; #size-cells = <1>; ranges; - clock-frequency = <9896800>; // 160MHz + clock-frequency = <160000000>; // 160MHz SDRAM0: memory-controller { compatible = "ibm,sdram-440gp"; - dcr-reg = <010 2>; + dcr-reg = <0x010 0x002>; // FIXME: anything else? }; SRAM0: sram { compatible = "ibm,sram-440gp"; - dcr-reg = <020 8 00a 1>; + dcr-reg = <0x020 0x008 0x00a 0x001>; }; DMA0: dma { // FIXME: ??? compatible = "ibm,dma-440gp"; - dcr-reg = <100 027>; + dcr-reg = <0x100 0x027>; }; MAL0: mcmal { compatible = "ibm,mcmal-440gx", "ibm,mcmal2"; - dcr-reg = <180 62>; + dcr-reg = <0x180 0x062>; num-tx-chans = <4>; num-rx-chans = <4>; interrupt-parent = <&MAL0>; - interrupts = <0 1 2 3 4>; + interrupts = <0x0 0x1 0x2 0x3 0x4>; #interrupt-cells = <1>; #address-cells = <0>; #size-cells = <0>; - interrupt-map = ; - interrupt-map-mask = ; + interrupt-map = ; + interrupt-map-mask = <0xffffffff>; }; POB0: opb { @@ -162,26 +164,26 @@ #size-cells = <1>; /* Wish there was a nicer way of specifying a full 32-bit range */ - ranges = <00000000 1 00000000 80000000 - 80000000 1 80000000 80000000>; - dcr-reg = <090 00b>; + ranges = <0x00000000 0x00000001 0x00000000 0x80000000 + 0x80000000 0x00000001 0x80000000 0x80000000>; + dcr-reg = <0x090 0x00b>; interrupt-parent = <&UIC1>; - interrupts = <7 4>; - clock-frequency = <4C4B400>; // 80MHz + interrupts = <0x7 0x4>; + clock-frequency = <80000000>; // 80MHz EBC0: ebc { compatible = "ibm,ebc-440gx", "ibm,ebc"; - dcr-reg = <012 2>; + dcr-reg = <0x012 0x002>; #address-cells = <2>; #size-cells = <1>; - clock-frequency = <4C4B400>; // 80MHz + clock-frequency = <80000000>; // 80MHz /* ranges property is supplied by zImage * based on firmware's configuration of the * EBC bridge */ - interrupts = <5 4>; + interrupts = <0x5 0x4>; interrupt-parent = <&UIC1>; /* TODO: Add other EBC devices */ @@ -192,103 +194,103 @@ UART0: serial@40000200 { device_type = "serial"; compatible = "ns16550"; - reg = <40000200 8>; - virtual-reg = ; - clock-frequency = ; - current-speed = <1C200>; /* 115200 */ + reg = <0x40000200 0x00000008>; + virtual-reg = <0xe0000200>; + clock-frequency = <11059200>; + current-speed = <115200>; /* 115200 */ interrupt-parent = <&UIC0>; - interrupts = <0 4>; + interrupts = <0x0 0x4>; }; UART1: serial@40000300 { device_type = "serial"; compatible = "ns16550"; - reg = <40000300 8>; - virtual-reg = ; - clock-frequency = ; - current-speed = <1C200>; /* 115200 */ + reg = <0x40000300 0x00000008>; + virtual-reg = <0xe0000300>; + clock-frequency = <11059200>; + current-speed = <115200>; /* 115200 */ interrupt-parent = <&UIC0>; - interrupts = <1 4>; + interrupts = <0x1 0x4>; }; IIC0: i2c@40000400 { /* FIXME */ compatible = "ibm,iic-440gp", "ibm,iic"; - reg = <40000400 14>; + reg = <0x40000400 0x00000014>; interrupt-parent = <&UIC0>; - interrupts = <2 4>; + interrupts = <0x2 0x4>; }; IIC1: i2c@40000500 { /* FIXME */ compatible = "ibm,iic-440gp", "ibm,iic"; - reg = <40000500 14>; + reg = <0x40000500 0x00000014>; interrupt-parent = <&UIC0>; - interrupts = <3 4>; + interrupts = <0x3 0x4>; }; GPIO0: gpio@40000700 { /* FIXME */ compatible = "ibm,gpio-440gp"; - reg = <40000700 20>; + reg = <0x40000700 0x00000020>; }; ZMII0: emac-zmii@40000780 { compatible = "ibm,zmii-440gx", "ibm,zmii"; - reg = <40000780 c>; + reg = <0x40000780 0x0000000c>; }; RGMII0: emac-rgmii@40000790 { compatible = "ibm,rgmii"; - reg = <40000790 8>; + reg = <0x40000790 0x00000008>; }; TAH0: emac-tah@40000b50 { compatible = "ibm,tah-440gx", "ibm,tah"; - reg = <40000b50 30>; + reg = <0x40000b50 0x00000030>; }; TAH1: emac-tah@40000d50 { compatible = "ibm,tah-440gx", "ibm,tah"; - reg = <40000d50 30>; + reg = <0x40000d50 0x00000030>; }; EMAC0: ethernet@40000800 { - unused = <1>; + unused = <0x1>; device_type = "network"; compatible = "ibm,emac-440gx", "ibm,emac4"; interrupt-parent = <&UIC1>; - interrupts = <1c 4 1d 4>; - reg = <40000800 70>; + interrupts = <0x1c 0x4 0x1d 0x4>; + reg = <0x40000800 0x00000070>; local-mac-address = [000000000000]; // Filled in by zImage mal-device = <&MAL0>; mal-tx-channel = <0>; mal-rx-channel = <0>; cell-index = <0>; - max-frame-size = <5dc>; - rx-fifo-size = <1000>; - tx-fifo-size = <800>; + max-frame-size = <1500>; + rx-fifo-size = <4096>; + tx-fifo-size = <2048>; phy-mode = "rmii"; - phy-map = <00000001>; + phy-map = <0x00000001>; zmii-device = <&ZMII0>; zmii-channel = <0>; }; EMAC1: ethernet@40000900 { - unused = <1>; + unused = <0x1>; device_type = "network"; compatible = "ibm,emac-440gx", "ibm,emac4"; interrupt-parent = <&UIC1>; - interrupts = <1e 4 1f 4>; - reg = <40000900 70>; + interrupts = <0x1e 0x4 0x1f 0x4>; + reg = <0x40000900 0x00000070>; local-mac-address = [000000000000]; // Filled in by zImage mal-device = <&MAL0>; mal-tx-channel = <1>; mal-rx-channel = <1>; cell-index = <1>; - max-frame-size = <5dc>; - rx-fifo-size = <1000>; - tx-fifo-size = <800>; + max-frame-size = <1500>; + rx-fifo-size = <4096>; + tx-fifo-size = <2048>; phy-mode = "rmii"; - phy-map = <00000001>; + phy-map = <0x00000001>; zmii-device = <&ZMII0>; zmii-channel = <1>; }; @@ -297,18 +299,18 @@ device_type = "network"; compatible = "ibm,emac-440gx", "ibm,emac4"; interrupt-parent = <&UIC2>; - interrupts = <0 4 1 4>; - reg = <40000c00 70>; + interrupts = <0x0 0x4 0x1 0x4>; + reg = <0x40000c00 0x00000070>; local-mac-address = [000000000000]; // Filled in by zImage mal-device = <&MAL0>; mal-tx-channel = <2>; mal-rx-channel = <2>; cell-index = <2>; - max-frame-size = <2328>; - rx-fifo-size = <1000>; - tx-fifo-size = <800>; + max-frame-size = <9000>; + rx-fifo-size = <4096>; + tx-fifo-size = <2048>; phy-mode = "rgmii"; - phy-map = <00000001>; + phy-map = <0x00000001>; rgmii-device = <&RGMII0>; rgmii-channel = <0>; zmii-device = <&ZMII0>; @@ -321,18 +323,18 @@ device_type = "network"; compatible = "ibm,emac-440gx", "ibm,emac4"; interrupt-parent = <&UIC2>; - interrupts = <2 4 3 4>; - reg = <40000e00 70>; + interrupts = <0x2 0x4 0x3 0x4>; + reg = <0x40000e00 0x00000070>; local-mac-address = [000000000000]; // Filled in by zImage mal-device = <&MAL0>; mal-tx-channel = <3>; mal-rx-channel = <3>; cell-index = <3>; - max-frame-size = <2328>; - rx-fifo-size = <1000>; - tx-fifo-size = <800>; + max-frame-size = <9000>; + rx-fifo-size = <4096>; + tx-fifo-size = <2048>; phy-mode = "rgmii"; - phy-map = <00000003>; + phy-map = <0x00000003>; rgmii-device = <&RGMII0>; rgmii-channel = <1>; zmii-device = <&ZMII0>; @@ -344,9 +346,9 @@ GPT0: gpt@40000a00 { /* FIXME */ - reg = <40000a00 d4>; + reg = <0x40000a00 0x000000d4>; interrupt-parent = <&UIC0>; - interrupts = <12 4 13 4 14 4 15 4 16 4>; + interrupts = <0x12 0x4 0x13 0x4 0x14 0x4 0x15 0x4 0x16 0x4>; }; }; @@ -360,34 +362,34 @@ primary; large-inbound-windows; enable-msi-hole; - reg = <2 0ec00000 8 /* Config space access */ - 0 0 0 /* no IACK cycles */ - 2 0ed00000 4 /* Special cycles */ - 2 0ec80000 100 /* Internal registers */ - 2 0ec80100 fc>; /* Internal messaging registers */ + reg = <0x00000002 0x0ec00000 0x00000008 /* Config space access */ + 0x00000000 0x00000000 0x00000000 /* no IACK cycles */ + 0x00000002 0x0ed00000 0x00000004 /* Special cycles */ + 0x00000002 0x0ec80000 0x00000100 /* Internal registers */ + 0x00000002 0x0ec80100 0x000000fc>; /* Internal messaging registers */ /* Outbound ranges, one memory and one IO, * later cannot be changed */ - ranges = <02000000 0 80000000 00000003 80000000 0 80000000 - 01000000 0 00000000 00000002 08000000 0 00010000>; + ranges = <0x02000000 0x00000000 0x80000000 0x00000003 0x80000000 0x00000000 0x80000000 + 0x01000000 0x00000000 0x00000000 0x00000002 0x08000000 0x00000000 0x00010000>; /* Inbound 2GB range starting at 0 */ - dma-ranges = <42000000 0 0 0 0 0 80000000>; + dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>; - interrupt-map-mask = ; + interrupt-map-mask = <0xf800 0x0 0x0 0x7>; interrupt-map = < /* IDSEL 1 */ - 0800 0 0 1 &UIC0 17 8 - 0800 0 0 2 &UIC0 18 8 - 0800 0 0 3 &UIC0 19 8 - 0800 0 0 4 &UIC0 1a 8 + 0x800 0x0 0x0 0x1 &UIC0 0x17 0x8 + 0x800 0x0 0x0 0x2 &UIC0 0x18 0x8 + 0x800 0x0 0x0 0x3 &UIC0 0x19 0x8 + 0x800 0x0 0x0 0x4 &UIC0 0x1a 0x8 /* IDSEL 2 */ - 1000 0 0 1 &UIC0 18 8 - 1000 0 0 2 &UIC0 19 8 - 1000 0 0 3 &UIC0 1a 8 - 1000 0 0 4 &UIC0 17 8 + 0x1000 0x0 0x0 0x1 &UIC0 0x18 0x8 + 0x1000 0x0 0x0 0x2 &UIC0 0x19 0x8 + 0x1000 0x0 0x0 0x3 &UIC0 0x1a 0x8 + 0x1000 0x0 0x0 0x4 &UIC0 0x17 0x8 >; }; }; diff --git a/arch/powerpc/boot/dts/walnut.dts b/arch/powerpc/boot/dts/walnut.dts index a328607..4a9f726 100644 --- a/arch/powerpc/boot/dts/walnut.dts +++ b/arch/powerpc/boot/dts/walnut.dts @@ -9,12 +9,14 @@ * any warranty of any kind, whether express or implied. */ +/dts-v1/; + / { #address-cells = <1>; #size-cells = <1>; model = "ibm,walnut"; compatible = "ibm,walnut"; - dcr-parent = <&/cpus/cpu@0>; + dcr-parent = <&{/cpus/cpu@0}>; aliases { ethernet0 = &EMAC; @@ -29,13 +31,13 @@ cpu@0 { device_type = "cpu"; model = "PowerPC,405GP"; - reg = <0>; - clock-frequency = ; /* Filled in by zImage */ + reg = <0x00000000>; + clock-frequency = <200000000>; /* Filled in by zImage */ timebase-frequency = <0>; /* Filled in by zImage */ - i-cache-line-size = <20>; - d-cache-line-size = <20>; - i-cache-size = <4000>; - d-cache-size = <4000>; + i-cache-line-size = <32>; + d-cache-line-size = <32>; + i-cache-size = <16384>; + d-cache-size = <16384>; dcr-controller; dcr-access-method = "native"; }; @@ -43,14 +45,14 @@ memory { device_type = "memory"; - reg = <0 0>; /* Filled in by zImage */ + reg = <0x00000000 0x00000000>; /* Filled in by zImage */ }; UIC0: interrupt-controller { compatible = "ibm,uic"; interrupt-controller; cell-index = <0>; - dcr-reg = <0c0 9>; + dcr-reg = <0x0c0 0x009>; #address-cells = <0>; #size-cells = <0>; #interrupt-cells = <2>; @@ -65,63 +67,63 @@ SDRAM0: memory-controller { compatible = "ibm,sdram-405gp"; - dcr-reg = <010 2>; + dcr-reg = <0x010 0x002>; }; MAL: mcmal { compatible = "ibm,mcmal-405gp", "ibm,mcmal"; - dcr-reg = <180 62>; + dcr-reg = <0x180 0x062>; num-tx-chans = <1>; num-rx-chans = <1>; interrupt-parent = <&UIC0>; interrupts = < - b 4 /* TXEOB */ - c 4 /* RXEOB */ - a 4 /* SERR */ - d 4 /* TXDE */ - e 4 /* RXDE */>; + 0xb 0x4 /* TXEOB */ + 0xc 0x4 /* RXEOB */ + 0xa 0x4 /* SERR */ + 0xd 0x4 /* TXDE */ + 0xe 0x4 /* RXDE */>; }; POB0: opb { compatible = "ibm,opb-405gp", "ibm,opb"; #address-cells = <1>; #size-cells = <1>; - ranges = ; - dcr-reg = <0a0 5>; + ranges = <0xef600000 0xef600000 0x00a00000>; + dcr-reg = <0x0a0 0x005>; clock-frequency = <0>; /* Filled in by zImage */ UART0: serial@ef600300 { device_type = "serial"; compatible = "ns16550"; - reg = ; - virtual-reg = ; + reg = <0xef600300 0x00000008>; + virtual-reg = <0xef600300>; clock-frequency = <0>; /* Filled in by zImage */ - current-speed = <2580>; + current-speed = <9600>; interrupt-parent = <&UIC0>; - interrupts = <0 4>; + interrupts = <0x0 0x4>; }; UART1: serial@ef600400 { device_type = "serial"; compatible = "ns16550"; - reg = ; - virtual-reg = ; + reg = <0xef600400 0x00000008>; + virtual-reg = <0xef600400>; clock-frequency = <0>; /* Filled in by zImage */ - current-speed = <2580>; + current-speed = <9600>; interrupt-parent = <&UIC0>; - interrupts = <1 4>; + interrupts = <0x1 0x4>; }; IIC: i2c@ef600500 { compatible = "ibm,iic-405gp", "ibm,iic"; - reg = ; + reg = <0xef600500 0x00000011>; interrupt-parent = <&UIC0>; - interrupts = <2 4>; + interrupts = <0x2 0x4>; }; GPIO: gpio@ef600700 { compatible = "ibm,gpio-405gp"; - reg = ; + reg = <0xef600700 0x00000020>; }; EMAC: ethernet@ef600800 { @@ -129,26 +131,26 @@ compatible = "ibm,emac-405gp", "ibm,emac"; interrupt-parent = <&UIC0>; interrupts = < - f 4 /* Ethernet */ - 9 4 /* Ethernet Wake Up */>; + 0xf 0x4 /* Ethernet */ + 0x9 0x4 /* Ethernet Wake Up */>; local-mac-address = [000000000000]; /* Filled in by zImage */ - reg = ; + reg = <0xef600800 0x00000070>; mal-device = <&MAL>; mal-tx-channel = <0>; mal-rx-channel = <0>; cell-index = <0>; - max-frame-size = <5dc>; - rx-fifo-size = <1000>; - tx-fifo-size = <800>; + max-frame-size = <1500>; + rx-fifo-size = <4096>; + tx-fifo-size = <2048>; phy-mode = "rmii"; - phy-map = <00000001>; + phy-map = <0x00000001>; }; }; EBC0: ebc { compatible = "ibm,ebc-405gp", "ibm,ebc"; - dcr-reg = <012 2>; + dcr-reg = <0x012 0x002>; #address-cells = <2>; #size-cells = <1>; /* The ranges property is supplied by the bootwrapper @@ -158,18 +160,18 @@ clock-frequency = <0>; /* Filled in by zImage */ sram@0,0 { - reg = <0 0 80000>; + reg = <0x00000000 0x00000000 0x00080000>; }; flash@0,80000 { compatible = "jedec-flash"; bank-width = <1>; - reg = <0 80000 80000>; + reg = <0x00000000 0x00080000 0x00080000>; #address-cells = <1>; #size-cells = <1>; partition@0 { label = "OpenBIOS"; - reg = <0 80000>; + reg = <0x00000000 0x00080000>; read-only; }; }; @@ -177,24 +179,24 @@ nvram@1,0 { /* NVRAM and RTC */ compatible = "ds1743-nvram"; - #bytes = <2000>; - reg = <1 0 2000>; + #bytes = <0x2000>; + reg = <0x00000001 0x00000000 0x00002000>; }; keyboard@2,0 { compatible = "intel,82C42PC"; - reg = <2 0 2>; + reg = <0x00000002 0x00000000 0x00000002>; }; ir@3,0 { compatible = "ti,TIR2000PAG"; - reg = <3 0 10>; + reg = <0x00000003 0x00000000 0x00000010>; }; fpga@7,0 { compatible = "Walnut-FPGA"; - reg = <7 0 10>; - virtual-reg = ; + reg = <0x00000007 0x00000000 0x00000010>; + virtual-reg = <0xf0300005>; }; }; @@ -205,35 +207,35 @@ #address-cells = <3>; compatible = "ibm,plb405gp-pci", "ibm,plb-pci"; primary; - reg = ; /* Internal registers */ + reg = <0xeec00000 0x00000008 /* Config space access */ + 0xeed80000 0x00000004 /* IACK */ + 0xeed80000 0x00000004 /* Special cycle */ + 0xef480000 0x00000040>; /* Internal registers */ /* Outbound ranges, one memory and one IO, * later cannot be changed. Chip supports a second * IO range but we don't use it for now */ - ranges = <02000000 0 80000000 80000000 0 20000000 - 01000000 0 00000000 e8000000 0 00010000>; + ranges = <0x02000000 0x00000000 0x80000000 0x80000000 0x00000000 0x20000000 + 0x01000000 0x00000000 0x00000000 0xe8000000 0x00000000 0x00010000>; /* Inbound 2GB range starting at 0 */ - dma-ranges = <42000000 0 0 0 0 80000000>; + dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x80000000>; /* Walnut has all 4 IRQ pins tied together per slot */ - interrupt-map-mask = ; + interrupt-map-mask = <0xf800 0x0 0x0 0x0>; interrupt-map = < /* IDSEL 1 */ - 0800 0 0 0 &UIC0 1c 8 + 0x800 0x0 0x0 0x0 &UIC0 0x1c 0x8 /* IDSEL 2 */ - 1000 0 0 0 &UIC0 1d 8 + 0x1000 0x0 0x0 0x0 &UIC0 0x1d 0x8 /* IDSEL 3 */ - 1800 0 0 0 &UIC0 1e 8 + 0x1800 0x0 0x0 0x0 &UIC0 0x1e 0x8 /* IDSEL 4 */ - 2000 0 0 0 &UIC0 1f 8 + 0x2000 0x0 0x0 0x0 &UIC0 0x1f 0x8 >; }; }; diff --git a/arch/powerpc/boot/dts/warp.dts b/arch/powerpc/boot/dts/warp.dts index b04a52e..c52e4fb 100644 --- a/arch/powerpc/boot/dts/warp.dts +++ b/arch/powerpc/boot/dts/warp.dts @@ -9,12 +9,14 @@ * any warranty of any kind, whether express or implied. */ +/dts-v1/; + / { #address-cells = <2>; #size-cells = <1>; model = "pika,warp"; compatible = "pika,warp"; - dcr-parent = <&/cpus/cpu@0>; + dcr-parent = <&{/cpus/cpu@0}>; aliases { ethernet0 = &EMAC0; @@ -28,13 +30,13 @@ cpu@0 { device_type = "cpu"; model = "PowerPC,440EP"; - reg = <0>; + reg = <0x00000000>; clock-frequency = <0>; /* Filled in by zImage */ timebase-frequency = <0>; /* Filled in by zImage */ - i-cache-line-size = <20>; - d-cache-line-size = <20>; - i-cache-size = <8000>; - d-cache-size = <8000>; + i-cache-line-size = <32>; + d-cache-line-size = <32>; + i-cache-size = <32768>; + d-cache-size = <32768>; dcr-controller; dcr-access-method = "native"; }; @@ -42,14 +44,14 @@ memory { device_type = "memory"; - reg = <0 0 0>; /* Filled in by zImage */ + reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by zImage */ }; UIC0: interrupt-controller0 { compatible = "ibm,uic-440ep","ibm,uic"; interrupt-controller; cell-index = <0>; - dcr-reg = <0c0 009>; + dcr-reg = <0x0c0 0x009>; #address-cells = <0>; #size-cells = <0>; #interrupt-cells = <2>; @@ -59,22 +61,22 @@ compatible = "ibm,uic-440ep","ibm,uic"; interrupt-controller; cell-index = <1>; - dcr-reg = <0d0 009>; + dcr-reg = <0x0d0 0x009>; #address-cells = <0>; #size-cells = <0>; #interrupt-cells = <2>; - interrupts = <1e 4 1f 4>; /* cascade */ + interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */ interrupt-parent = <&UIC0>; }; SDR0: sdr { compatible = "ibm,sdr-440ep"; - dcr-reg = <00e 002>; + dcr-reg = <0x00e 0x002>; }; CPR0: cpr { compatible = "ibm,cpr-440ep"; - dcr-reg = <00c 002>; + dcr-reg = <0x00c 0x002>; }; plb { @@ -86,86 +88,86 @@ SDRAM0: sdram { compatible = "ibm,sdram-440ep", "ibm,sdram-405gp"; - dcr-reg = <010 2>; + dcr-reg = <0x010 0x002>; }; DMA0: dma { compatible = "ibm,dma-440ep", "ibm,dma-440gp"; - dcr-reg = <100 027>; + dcr-reg = <0x100 0x027>; }; MAL0: mcmal { compatible = "ibm,mcmal-440ep", "ibm,mcmal-440gp", "ibm,mcmal"; - dcr-reg = <180 62>; + dcr-reg = <0x180 0x062>; num-tx-chans = <4>; num-rx-chans = <2>; interrupt-parent = <&MAL0>; - interrupts = <0 1 2 3 4>; + interrupts = <0x0 0x1 0x2 0x3 0x4>; #interrupt-cells = <1>; #address-cells = <0>; #size-cells = <0>; - interrupt-map = ; + interrupt-map = ; }; POB0: opb { compatible = "ibm,opb-440ep", "ibm,opb-440gp", "ibm,opb"; #address-cells = <1>; #size-cells = <1>; - ranges = <00000000 0 00000000 80000000 - 80000000 0 80000000 80000000>; + ranges = <0x00000000 0x00000000 0x00000000 0x80000000 + 0x80000000 0x00000000 0x80000000 0x80000000>; interrupt-parent = <&UIC1>; - interrupts = <7 4>; + interrupts = <0x7 0x4>; clock-frequency = <0>; /* Filled in by zImage */ EBC0: ebc { compatible = "ibm,ebc-440ep", "ibm,ebc-440gp", "ibm,ebc"; - dcr-reg = <012 2>; + dcr-reg = <0x012 0x002>; #address-cells = <2>; #size-cells = <1>; clock-frequency = <0>; /* Filled in by zImage */ - interrupts = <5 1>; + interrupts = <0x5 0x1>; interrupt-parent = <&UIC1>; fpga@2,0 { compatible = "pika,fpga"; - reg = <2 0 2200>; - interrupts = <18 8>; + reg = <0x00000002 0x00000000 0x00002200>; + interrupts = <0x18 0x8>; interrupt-parent = <&UIC0>; }; nor_flash@0,0 { compatible = "amd,s29gl512n", "cfi-flash"; bank-width = <2>; - reg = <0 0 4000000>; + reg = <0x00000000 0x00000000 0x04000000>; #address-cells = <1>; #size-cells = <1>; partition@0 { label = "kernel"; - reg = <0 180000>; + reg = <0x00000000 0x00180000>; }; partition@180000 { label = "root"; - reg = <180000 3480000>; + reg = <0x00180000 0x03480000>; }; partition@3600000 { label = "user"; - reg = <3600000 900000>; + reg = <0x03600000 0x00900000>; }; partition@3f00000 { label = "fpga"; - reg = <3f00000 40000>; + reg = <0x03f00000 0x00040000>; }; partition@3f40000 { label = "env"; - reg = <3f40000 40000>; + reg = <0x03f40000 0x00040000>; }; partition@3f80000 { label = "u-boot"; - reg = <3f80000 80000>; + reg = <0x03f80000 0x00080000>; }; }; }; @@ -173,60 +175,60 @@ UART0: serial@ef600300 { device_type = "serial"; compatible = "ns16550"; - reg = ; - virtual-reg = ; + reg = <0xef600300 0x00000008>; + virtual-reg = <0xef600300>; clock-frequency = <0>; /* Filled in by zImage */ - current-speed = <1c200>; + current-speed = <115200>; interrupt-parent = <&UIC0>; - interrupts = <0 4>; + interrupts = <0x0 0x4>; }; IIC0: i2c@ef600700 { compatible = "ibm,iic-440ep", "ibm,iic-440gp", "ibm,iic"; - reg = ; + reg = <0xef600700 0x00000014>; interrupt-parent = <&UIC0>; - interrupts = <2 4>; + interrupts = <0x2 0x4>; }; GPIO0: gpio@ef600b00 { compatible = "ibm,gpio-440ep"; - reg = ; + reg = <0xef600b00 0x00000048>; }; GPIO1: gpio@ef600c00 { compatible = "ibm,gpio-440ep"; - reg = ; + reg = <0xef600c00 0x00000048>; }; ZMII0: emac-zmii@ef600d00 { compatible = "ibm,zmii-440ep", "ibm,zmii-440gp", "ibm,zmii"; - reg = ; + reg = <0xef600d00 0x0000000c>; }; EMAC0: ethernet@ef600e00 { device_type = "network"; compatible = "ibm,emac-440ep", "ibm,emac-440gp", "ibm,emac"; interrupt-parent = <&UIC1>; - interrupts = <1c 4 1d 4>; - reg = ; + interrupts = <0x1c 0x4 0x1d 0x4>; + reg = <0xef600e00 0x00000070>; local-mac-address = [000000000000]; mal-device = <&MAL0>; mal-tx-channel = <0 1>; mal-rx-channel = <0>; cell-index = <0>; - max-frame-size = <5dc>; - rx-fifo-size = <1000>; - tx-fifo-size = <800>; + max-frame-size = <1500>; + rx-fifo-size = <4096>; + tx-fifo-size = <2048>; phy-mode = "rmii"; - phy-map = <00000000>; + phy-map = <0x00000000>; zmii-device = <&ZMII0>; zmii-channel = <0>; }; usb@ef601000 { compatible = "ohci-be"; - reg = ; - interrupts = <8 1 9 1>; + reg = <0xef601000 0x00000080>; + interrupts = <0x8 0x1 0x9 0x1>; interrupt-parent = < &UIC1 >; }; }; diff --git a/arch/powerpc/boot/dts/yosemite.dts b/arch/powerpc/boot/dts/yosemite.dts index 0d6d332..e39422a 100644 --- a/arch/powerpc/boot/dts/yosemite.dts +++ b/arch/powerpc/boot/dts/yosemite.dts @@ -9,12 +9,14 @@ * any warranty of any kind, whether express or implied. */ +/dts-v1/; + / { #address-cells = <2>; #size-cells = <1>; model = "amcc,yosemite"; compatible = "amcc,yosemite","amcc,bamboo"; - dcr-parent = <&/cpus/cpu@0>; + dcr-parent = <&{/cpus/cpu@0}>; aliases { ethernet0 = &EMAC0; @@ -32,13 +34,13 @@ cpu@0 { device_type = "cpu"; model = "PowerPC,440EP"; - reg = <0>; + reg = <0x00000000>; clock-frequency = <0>; /* Filled in by zImage */ timebase-frequency = <0>; /* Filled in by zImage */ - i-cache-line-size = <20>; - d-cache-line-size = <20>; - i-cache-size = <8000>; - d-cache-size = <8000>; + i-cache-line-size = <32>; + d-cache-line-size = <32>; + i-cache-size = <32768>; + d-cache-size = <32768>; dcr-controller; dcr-access-method = "native"; }; @@ -46,14 +48,14 @@ memory { device_type = "memory"; - reg = <0 0 0>; /* Filled in by zImage */ + reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by zImage */ }; UIC0: interrupt-controller0 { compatible = "ibm,uic-440ep","ibm,uic"; interrupt-controller; cell-index = <0>; - dcr-reg = <0c0 009>; + dcr-reg = <0x0c0 0x009>; #address-cells = <0>; #size-cells = <0>; #interrupt-cells = <2>; @@ -63,22 +65,22 @@ compatible = "ibm,uic-440ep","ibm,uic"; interrupt-controller; cell-index = <1>; - dcr-reg = <0d0 009>; + dcr-reg = <0x0d0 0x009>; #address-cells = <0>; #size-cells = <0>; #interrupt-cells = <2>; - interrupts = <1e 4 1f 4>; /* cascade */ + interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */ interrupt-parent = <&UIC0>; }; SDR0: sdr { compatible = "ibm,sdr-440ep"; - dcr-reg = <00e 002>; + dcr-reg = <0x00e 0x002>; }; CPR0: cpr { compatible = "ibm,cpr-440ep"; - dcr-reg = <00c 002>; + dcr-reg = <0x00c 0x002>; }; plb { @@ -90,29 +92,29 @@ SDRAM0: sdram { compatible = "ibm,sdram-440ep", "ibm,sdram-405gp"; - dcr-reg = <010 2>; + dcr-reg = <0x010 0x002>; }; DMA0: dma { compatible = "ibm,dma-440ep", "ibm,dma-440gp"; - dcr-reg = <100 027>; + dcr-reg = <0x100 0x027>; }; MAL0: mcmal { compatible = "ibm,mcmal-440ep", "ibm,mcmal-440gp", "ibm,mcmal"; - dcr-reg = <180 62>; + dcr-reg = <0x180 0x062>; num-tx-chans = <4>; num-rx-chans = <2>; interrupt-parent = <&MAL0>; - interrupts = <0 1 2 3 4>; + interrupts = <0x0 0x1 0x2 0x3 0x4>; #interrupt-cells = <1>; #address-cells = <0>; #size-cells = <0>; - interrupt-map = ; + interrupt-map = ; }; POB0: opb { @@ -122,110 +124,110 @@ /* Bamboo is oddball in the 44x world and doesn't use the ERPN * bits. */ - ranges = <00000000 0 00000000 80000000 - 80000000 0 80000000 80000000>; + ranges = <0x00000000 0x00000000 0x00000000 0x80000000 + 0x80000000 0x00000000 0x80000000 0x80000000>; interrupt-parent = <&UIC1>; - interrupts = <7 4>; + interrupts = <0x7 0x4>; clock-frequency = <0>; /* Filled in by zImage */ EBC0: ebc { compatible = "ibm,ebc-440ep", "ibm,ebc-440gp", "ibm,ebc"; - dcr-reg = <012 2>; + dcr-reg = <0x012 0x002>; #address-cells = <2>; #size-cells = <1>; clock-frequency = <0>; /* Filled in by zImage */ - interrupts = <5 1>; + interrupts = <0x5 0x1>; interrupt-parent = <&UIC1>; }; UART0: serial@ef600300 { device_type = "serial"; compatible = "ns16550"; - reg = ; - virtual-reg = ; + reg = <0xef600300 0x00000008>; + virtual-reg = <0xef600300>; clock-frequency = <0>; /* Filled in by zImage */ - current-speed = <1c200>; + current-speed = <115200>; interrupt-parent = <&UIC0>; - interrupts = <0 4>; + interrupts = <0x0 0x4>; }; UART1: serial@ef600400 { device_type = "serial"; compatible = "ns16550"; - reg = ; - virtual-reg = ; + reg = <0xef600400 0x00000008>; + virtual-reg = <0xef600400>; clock-frequency = <0>; current-speed = <0>; interrupt-parent = <&UIC0>; - interrupts = <1 4>; + interrupts = <0x1 0x4>; }; UART2: serial@ef600500 { device_type = "serial"; compatible = "ns16550"; - reg = ; - virtual-reg = ; + reg = <0xef600500 0x00000008>; + virtual-reg = <0xef600500>; clock-frequency = <0>; current-speed = <0>; interrupt-parent = <&UIC0>; - interrupts = <3 4>; + interrupts = <0x3 0x4>; status = "disabled"; }; UART3: serial@ef600600 { device_type = "serial"; compatible = "ns16550"; - reg = ; - virtual-reg = ; + reg = <0xef600600 0x00000008>; + virtual-reg = <0xef600600>; clock-frequency = <0>; current-speed = <0>; interrupt-parent = <&UIC0>; - interrupts = <4 4>; + interrupts = <0x4 0x4>; status = "disabled"; }; IIC0: i2c@ef600700 { compatible = "ibm,iic-440ep", "ibm,iic-440gp", "ibm,iic"; - reg = ; + reg = <0xef600700 0x00000014>; interrupt-parent = <&UIC0>; - interrupts = <2 4>; + interrupts = <0x2 0x4>; }; IIC1: i2c@ef600800 { compatible = "ibm,iic-440ep", "ibm,iic-440gp", "ibm,iic"; - reg = ; + reg = <0xef600800 0x00000014>; interrupt-parent = <&UIC0>; - interrupts = <7 4>; + interrupts = <0x7 0x4>; }; spi@ef600900 { compatible = "amcc,spi-440ep"; - reg = ; - interrupts = <8 4>; + reg = <0xef600900 0x00000006>; + interrupts = <0x8 0x4>; interrupt-parent = <&UIC0>; }; ZMII0: emac-zmii@ef600d00 { compatible = "ibm,zmii-440ep", "ibm,zmii-440gp", "ibm,zmii"; - reg = ; + reg = <0xef600d00 0x0000000c>; }; EMAC0: ethernet@ef600e00 { device_type = "network"; compatible = "ibm,emac-440ep", "ibm,emac-440gp", "ibm,emac"; interrupt-parent = <&UIC1>; - interrupts = <1c 4 1d 4>; - reg = ; + interrupts = <0x1c 0x4 0x1d 0x4>; + reg = <0xef600e00 0x00000070>; local-mac-address = [000000000000]; mal-device = <&MAL0>; mal-tx-channel = <0 1>; mal-rx-channel = <0>; cell-index = <0>; - max-frame-size = <5dc>; - rx-fifo-size = <1000>; - tx-fifo-size = <800>; + max-frame-size = <1500>; + rx-fifo-size = <4096>; + tx-fifo-size = <2048>; phy-mode = "rmii"; - phy-map = <00000000>; + phy-map = <0x00000000>; zmii-device = <&ZMII0>; zmii-channel = <0>; }; @@ -234,26 +236,26 @@ device_type = "network"; compatible = "ibm,emac-440ep", "ibm,emac-440gp", "ibm,emac"; interrupt-parent = <&UIC1>; - interrupts = <1e 4 1f 4>; - reg = ; + interrupts = <0x1e 0x4 0x1f 0x4>; + reg = <0xef600f00 0x00000070>; local-mac-address = [000000000000]; mal-device = <&MAL0>; mal-tx-channel = <2 3>; mal-rx-channel = <1>; cell-index = <1>; - max-frame-size = <5dc>; - rx-fifo-size = <1000>; - tx-fifo-size = <800>; + max-frame-size = <1500>; + rx-fifo-size = <4096>; + tx-fifo-size = <2048>; phy-mode = "rmii"; - phy-map = <00000000>; + phy-map = <0x00000000>; zmii-device = <&ZMII0>; zmii-channel = <1>; }; usb@ef601000 { compatible = "ohci-be"; - reg = ; - interrupts = <8 4 9 4>; + reg = <0xef601000 0x00000080>; + interrupts = <0x8 0x4 0x9 0x4>; interrupt-parent = < &UIC1 >; }; }; @@ -265,35 +267,35 @@ #address-cells = <3>; compatible = "ibm,plb440ep-pci", "ibm,plb-pci"; primary; - reg = <0 eec00000 8 /* Config space access */ - 0 eed00000 4 /* IACK */ - 0 eed00000 4 /* Special cycle */ - 0 ef400000 40>; /* Internal registers */ + reg = <0x00000000 0xeec00000 0x00000008 /* Config space access */ + 0x00000000 0xeed00000 0x00000004 /* IACK */ + 0x00000000 0xeed00000 0x00000004 /* Special cycle */ + 0x00000000 0xef400000 0x00000040>; /* Internal registers */ /* Outbound ranges, one memory and one IO, * later cannot be changed. Chip supports a second * IO range but we don't use it for now */ - ranges = <02000000 0 a0000000 0 a0000000 0 20000000 - 01000000 0 00000000 0 e8000000 0 00010000>; + ranges = <0x02000000 0x00000000 0xa0000000 0x00000000 0xa0000000 0x00000000 0x20000000 + 0x01000000 0x00000000 0x00000000 0x00000000 0xe8000000 0x00000000 0x00010000>; /* Inbound 2GB range starting at 0 */ - dma-ranges = <42000000 0 0 0 0 0 80000000>; + dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>; /* Bamboo has all 4 IRQ pins tied together per slot */ - interrupt-map-mask = ; + interrupt-map-mask = <0xf800 0x0 0x0 0x0>; interrupt-map = < /* IDSEL 1 */ - 0800 0 0 0 &UIC0 1c 8 + 0x800 0x0 0x0 0x0 &UIC0 0x1c 0x8 /* IDSEL 2 */ - 1000 0 0 0 &UIC0 1b 8 + 0x1000 0x0 0x0 0x0 &UIC0 0x1b 0x8 /* IDSEL 3 */ - 1800 0 0 0 &UIC0 1a 8 + 0x1800 0x0 0x0 0x0 &UIC0 0x1a 0x8 /* IDSEL 4 */ - 2000 0 0 0 &UIC0 19 8 + 0x2000 0x0 0x0 0x0 &UIC0 0x19 0x8 >; }; }; -- cgit v1.1 From 6f031101f5c6bb44762911909da575127f676eb8 Mon Sep 17 00:00:00 2001 From: Josh Boyer Date: Fri, 16 May 2008 00:41:23 +1000 Subject: [POWERPC] 4xx: Fix PCI mem in rainier DTS This fixes the PCI node in the Rainier to match the spec from AMCC. A similar fix was done for 440EPx, which shares the same values as 440GRx. Signed-off-by: Josh Boyer --- arch/powerpc/boot/dts/rainier.dts | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'arch/powerpc/boot') diff --git a/arch/powerpc/boot/dts/rainier.dts b/arch/powerpc/boot/dts/rainier.dts index 2cd87f6..2afb63a 100644 --- a/arch/powerpc/boot/dts/rainier.dts +++ b/arch/powerpc/boot/dts/rainier.dts @@ -330,8 +330,9 @@ * later cannot be changed. Chip supports a second * IO range but we don't use it for now */ - ranges = <0x02000000 0x00000000 0x80000000 0x00000001 0x80000000 0x00000000 0x10000000 - 0x01000000 0x00000000 0x00000000 0x00000001 0xe8000000 0x00000000 0x00100000>; + ranges = <0x02000000 0x0 0x80000000 0x1 0x80000000 0x0 0x40000000 + 0x01000000 0x0 0x00000000 0x1 0xe8000000 0x0 0x00010000 + 0x01000000 0x0 0x00000000 0x1 0xe8800000 0x0 0x03800000>; /* Inbound 2GB range starting at 0 */ dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>; -- cgit v1.1 From 0393cb615f369b6ea0e636dd4d1e25675657dc75 Mon Sep 17 00:00:00 2001 From: Sean MacLennan Date: Tue, 29 Apr 2008 13:27:46 +1000 Subject: [POWERPC] PIKA Warp: Update DTS to support Rev B boards * Switched from 64M NOR/64M NAND to 4M NOR/256M NAND. * Added led entries. * Added fpga-sd entry. * Added ad7414 entry. Signed-off-by: Sean MacLennan Acked-by: Grant Likely Signed-off-by: Josh Boyer --- arch/powerpc/boot/dts/warp.dts | 55 ++++++++++++++++++++++++++---------------- 1 file changed, 34 insertions(+), 21 deletions(-) (limited to 'arch/powerpc/boot') diff --git a/arch/powerpc/boot/dts/warp.dts b/arch/powerpc/boot/dts/warp.dts index c52e4fb..340018c 100644 --- a/arch/powerpc/boot/dts/warp.dts +++ b/arch/powerpc/boot/dts/warp.dts @@ -134,40 +134,33 @@ fpga@2,0 { compatible = "pika,fpga"; - reg = <0x00000002 0x00000000 0x00002200>; + reg = <0x00000002 0x00000000 0x00001000>; interrupts = <0x18 0x8>; interrupt-parent = <&UIC0>; }; + fpga@2,4000 { + compatible = "pika,fpga-sd"; + reg = <0x00000002 0x00004000 0x00000A00>; + }; + nor_flash@0,0 { - compatible = "amd,s29gl512n", "cfi-flash"; + compatible = "amd,s29gl032a", "cfi-flash"; bank-width = <2>; - reg = <0x00000000 0x00000000 0x04000000>; + reg = <0x00000000 0x00000000 0x00400000>; #address-cells = <1>; #size-cells = <1>; - partition@0 { - label = "kernel"; - reg = <0x00000000 0x00180000>; - }; - partition@180000 { - label = "root"; - reg = <0x00180000 0x03480000>; - }; - partition@3600000 { - label = "user"; - reg = <0x03600000 0x00900000>; - }; - partition@3f00000 { + partition@300000 { label = "fpga"; - reg = <0x03f00000 0x00040000>; + reg = <0x0030000 0x00040000>; }; - partition@3f40000 { + partition@340000 { label = "env"; - reg = <0x03f40000 0x00040000>; + reg = <0x0340000 0x00040000>; }; - partition@3f80000 { + partition@380000 { label = "u-boot"; - reg = <0x03f80000 0x00080000>; + reg = <0x0380000 0x00080000>; }; }; }; @@ -188,16 +181,36 @@ reg = <0xef600700 0x00000014>; interrupt-parent = <&UIC0>; interrupts = <0x2 0x4>; + index = <0x0>; + #address-cells = <1>; + #size-cells = <0>; + + ad7414@4a { + compatible = "adi,ad7414"; + reg = <0x4a>; + interrupts = <0x19 0x8>; + interrupt-parent = <&UIC0>; + }; }; GPIO0: gpio@ef600b00 { compatible = "ibm,gpio-440ep"; reg = <0xef600b00 0x00000048>; + #gpio-cells = <2>; + gpio-controller; }; GPIO1: gpio@ef600c00 { compatible = "ibm,gpio-440ep"; reg = <0xef600c00 0x00000048>; + #gpio-cells = <2>; + gpio-controller; + + led@31 { + compatible = "linux,gpio-led"; + linux,name = ":green:"; + gpios = <&GPIO1 0x30 0>; + }; }; ZMII0: emac-zmii@ef600d00 { -- cgit v1.1 From 4ebef31fa6e013e5cd3d4522e6018eb6d55046be Mon Sep 17 00:00:00 2001 From: Sean MacLennan Date: Tue, 20 May 2008 08:28:52 -0500 Subject: [POWERPC] PIKA Warp: Update platform code to support Rev B boards * Switched from 64M NOR/64M NAND to 4M NOR/256M NAND. * Full DTM support including critical temperature. * Added POST information. * Removed LED function, moved to new LED driver. * Moved ad7414 to new style I2C initialization. Signed-off-by: Sean MacLennan Signed-off-by: Josh Boyer --- arch/powerpc/boot/cuboot-warp.c | 47 ++++++++++++++++++++++++++++++++++++++--- 1 file changed, 44 insertions(+), 3 deletions(-) (limited to 'arch/powerpc/boot') diff --git a/arch/powerpc/boot/cuboot-warp.c b/arch/powerpc/boot/cuboot-warp.c index eb108a8..2178021 100644 --- a/arch/powerpc/boot/cuboot-warp.c +++ b/arch/powerpc/boot/cuboot-warp.c @@ -10,6 +10,7 @@ #include "ops.h" #include "4xx.h" #include "cuboot.h" +#include "stdio.h" #define TARGET_4xx #define TARGET_44x @@ -17,14 +18,54 @@ static bd_t bd; -static void warp_fixups(void) +static void warp_fixup_one_nor(u32 from, u32 to) { - unsigned long sysclk = 66000000; + void *devp; + char name[50]; + u32 v[2]; + + sprintf(name, "/plb/opb/ebc/nor_flash@0,0/partition@%x", from); + + devp = finddevice(name); + if (!devp) + return; + + if (getprop(devp, "reg", v, sizeof(v)) == sizeof(v)) { + v[0] = to; + setprop(devp, "reg", v, sizeof(v)); + + printf("NOR 64M fixup %x -> %x\r\n", from, to); + } +} + - ibm440ep_fixup_clocks(sysclk, 11059200, 50000000); +static void warp_fixups(void) +{ + ibm440ep_fixup_clocks(66000000, 11059200, 50000000); ibm4xx_sdram_fixup_memsize(); ibm4xx_fixup_ebc_ranges("/plb/opb/ebc"); dt_fixup_mac_address_by_alias("ethernet0", bd.bi_enetaddr); + + /* Fixup for 64M flash on Rev A boards. */ + if (bd.bi_flashsize == 0x4000000) { + void *devp; + u32 v[3]; + + devp = finddevice("/plb/opb/ebc/nor_flash@0,0"); + if (!devp) + return; + + /* Fixup the size */ + if (getprop(devp, "reg", v, sizeof(v)) == sizeof(v)) { + v[2] = bd.bi_flashsize; + setprop(devp, "reg", v, sizeof(v)); + } + + /* Fixup parition offsets */ + warp_fixup_one_nor(0x300000, 0x3f00000); + warp_fixup_one_nor(0x340000, 0x3f40000); + warp_fixup_one_nor(0x380000, 0x3f80000); + } } -- cgit v1.1 From 0023352f56f90d01de67f995e248fe4c5308a497 Mon Sep 17 00:00:00 2001 From: Jason Jin Date: Fri, 23 May 2008 16:32:47 +0800 Subject: [POWERPC] 86xx: Enable MSI support for MPC8610HPCD board This patch enable the MSI on 8610hpcd board. Through the msi-available-ranges property, All the 256 msi interrupts can be tested on this board. Signed-off-by: Jason Jin Signed-off-by: Kumar Gala --- arch/powerpc/boot/dts/mpc8610_hpcd.dts | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) (limited to 'arch/powerpc/boot') diff --git a/arch/powerpc/boot/dts/mpc8610_hpcd.dts b/arch/powerpc/boot/dts/mpc8610_hpcd.dts index 08a780d..fa9c297 100644 --- a/arch/powerpc/boot/dts/mpc8610_hpcd.dts +++ b/arch/powerpc/boot/dts/mpc8610_hpcd.dts @@ -182,6 +182,22 @@ big-endian; }; + msi@41600 { + compatible = "fsl,mpc8610-msi", "fsl,mpic-msi"; + reg = <0x41600 0x80>; + msi-available-ranges = <0 0x100>; + interrupts = < + 0xe0 0 + 0xe1 0 + 0xe2 0 + 0xe3 0 + 0xe4 0 + 0xe5 0 + 0xe6 0 + 0xe7 0>; + interrupt-parent = <&mpic>; + }; + global-utilities@e0000 { compatible = "fsl,mpc8610-guts"; reg = <0xe0000 0x1000>; -- cgit v1.1 From 741edc494978bc2770e891b8cfadbca3246a3d1a Mon Sep 17 00:00:00 2001 From: Jason Jin Date: Fri, 23 May 2008 16:32:48 +0800 Subject: [POWERPC] 85xx: Enable MSI support for 85xxds board This patch enabled MSI on 8544ds and 8572ds board. So far only one MSI interrupt can generate on 8544 board. Signed-off-by: Jason Jin Signed-off-by: Kumar Gala --- arch/powerpc/boot/dts/mpc8544ds.dts | 16 ++++++++++++++++ arch/powerpc/boot/dts/mpc8572ds.dts | 16 ++++++++++++++++ 2 files changed, 32 insertions(+) (limited to 'arch/powerpc/boot') diff --git a/arch/powerpc/boot/dts/mpc8544ds.dts b/arch/powerpc/boot/dts/mpc8544ds.dts index 6a0d8db..1cfd970 100644 --- a/arch/powerpc/boot/dts/mpc8544ds.dts +++ b/arch/powerpc/boot/dts/mpc8544ds.dts @@ -219,6 +219,22 @@ device_type = "open-pic"; big-endian; }; + + msi@41600 { + compatible = "fsl,mpc8544-msi", "fsl,mpic-msi"; + reg = <0x41600 0x80>; + msi-available-ranges = <0 0x100>; + interrupts = < + 0xe0 0 + 0xe1 0 + 0xe2 0 + 0xe3 0 + 0xe4 0 + 0xe5 0 + 0xe6 0 + 0xe7 0>; + interrupt-parent = <&mpic>; + }; }; pci0: pci@e0008000 { diff --git a/arch/powerpc/boot/dts/mpc8572ds.dts b/arch/powerpc/boot/dts/mpc8572ds.dts index 66f27ab..174d51a 100644 --- a/arch/powerpc/boot/dts/mpc8572ds.dts +++ b/arch/powerpc/boot/dts/mpc8572ds.dts @@ -221,6 +221,22 @@ fsl,has-rstcr; }; + msi@41600 { + compatible = "fsl,mpc8572-msi", "fsl,mpic-msi"; + reg = <0x41600 0x80>; + msi-available-ranges = <0 0x100>; + interrupts = < + 0xe0 0 + 0xe1 0 + 0xe2 0 + 0xe3 0 + 0xe4 0 + 0xe5 0 + 0xe6 0 + 0xe7 0>; + interrupt-parent = <&mpic>; + }; + mpic: pic@40000 { clock-frequency = <0>; interrupt-controller; -- cgit v1.1 From 59d13f9dba56c444e5356b42d3d57b46e44ef975 Mon Sep 17 00:00:00 2001 From: Bryan O'Donoghue Date: Thu, 8 May 2008 13:47:00 +0100 Subject: [POWERPC] 83xx: Add support for Analogue & Micro ASP837E board The following adds support for the Analogue & Micro ASP 8347E, running Redboot. http://www.analogue-micro.com/ASP8347.html Signed-off-by: Bryan O'Donoghue Signed-off-by: Kumar Gala --- arch/powerpc/boot/Makefile | 3 +- arch/powerpc/boot/dts/asp834x-redboot.dts | 247 ++++++++++++++++++++++++++++++ arch/powerpc/boot/redboot-83xx.c | 60 ++++++++ arch/powerpc/boot/wrapper | 6 +- 4 files changed, 314 insertions(+), 2 deletions(-) create mode 100644 arch/powerpc/boot/dts/asp834x-redboot.dts create mode 100644 arch/powerpc/boot/redboot-83xx.c (limited to 'arch/powerpc/boot') diff --git a/arch/powerpc/boot/Makefile b/arch/powerpc/boot/Makefile index f5e0b2a..c40fb82 100644 --- a/arch/powerpc/boot/Makefile +++ b/arch/powerpc/boot/Makefile @@ -66,7 +66,7 @@ src-plat := of.c cuboot-52xx.c cuboot-824x.c cuboot-83xx.c cuboot-85xx.c holly.c fixed-head.S ep88xc.c ep405.c \ cuboot-katmai.c cuboot-rainier.c redboot-8xx.c ep8248e.c \ cuboot-warp.c cuboot-85xx-cpm2.c cuboot-yosemite.c simpleboot.c \ - virtex405-head.S + virtex405-head.S redboot-83xx.c src-boot := $(src-wlib) $(src-plat) empty.c src-boot := $(addprefix $(obj)/, $(src-boot)) @@ -242,6 +242,7 @@ image-$(CONFIG_MPC834x_ITX) += cuImage.mpc8349emitx \ cuImage.mpc8349emitxgp image-$(CONFIG_MPC834x_MDS) += cuImage.mpc834x_mds image-$(CONFIG_MPC836x_MDS) += cuImage.mpc836x_mds +image-$(CONFIG_ASP834x) += dtbImage.asp834x-redboot # Board ports in arch/powerpc/platform/85xx/Kconfig image-$(CONFIG_MPC8540_ADS) += cuImage.mpc8540ads diff --git a/arch/powerpc/boot/dts/asp834x-redboot.dts b/arch/powerpc/boot/dts/asp834x-redboot.dts new file mode 100644 index 0000000..972cf78 --- /dev/null +++ b/arch/powerpc/boot/dts/asp834x-redboot.dts @@ -0,0 +1,247 @@ +/* + * Analogue & Micro ASP8347 Device Tree Source + * + * Copyright 2008 Codehermit + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +/dts-v1/; + +/ { + model = "Analogue & Micro ASP8347E"; + compatible = "analogue-and-micro,asp8347e"; + #address-cells = <1>; + #size-cells = <1>; + + aliases { + ethernet0 = &enet0; + ethernet1 = &enet1; + serial0 = &serial0; + serial1 = &serial1; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + PowerPC,8347@0 { + device_type = "cpu"; + reg = <0x0>; + d-cache-line-size = <32>; + i-cache-line-size = <32>; + d-cache-size = <32768>; + i-cache-size = <32768>; + timebase-frequency = <0>; // from bootloader + bus-frequency = <0>; // from bootloader + clock-frequency = <0>; // from bootloader + }; + }; + + memory { + device_type = "memory"; + reg = <0x00000000 0x8000000>; // 128MB at 0 + }; + + localbus@ff005000 { + #address-cells = <2>; + #size-cells = <1>; + compatible = "fsl,mpc8347e-localbus", + "fsl,pq2pro-localbus", + "simple-bus"; + reg = <0xff005000 0x1000>; + interrupts = <77 0x8>; + interrupt-parent = <&ipic>; + + ranges = < + 0 0 0xf0000000 0x02000000 + >; + + flash@0,0 { + compatible = "cfi-flash"; + reg = <0 0 0x02000000>; + bank-width = <2>; + device-width = <2>; + }; + }; + + soc8349@ff000000 { + #address-cells = <1>; + #size-cells = <1>; + device_type = "soc"; + ranges = <0x0 0xff000000 0x00100000>; + reg = <0xff000000 0x00000200>; + bus-frequency = <0>; + + wdt@200 { + device_type = "watchdog"; + compatible = "mpc83xx_wdt"; + reg = <0x200 0x100>; + }; + + i2c@3000 { + #address-cells = <1>; + #size-cells = <0>; + cell-index = <0>; + compatible = "fsl-i2c"; + reg = <0x3000 0x100>; + interrupts = <14 0x8>; + interrupt-parent = <&ipic>; + dfsrr; + + rtc@68 { + compatible = "dallas,ds1374"; + reg = <0x68>; + }; + }; + + i2c@3100 { + #address-cells = <1>; + #size-cells = <0>; + cell-index = <1>; + compatible = "fsl-i2c"; + reg = <0x3100 0x100>; + interrupts = <15 0x8>; + interrupt-parent = <&ipic>; + dfsrr; + }; + + spi@7000 { + cell-index = <0>; + compatible = "fsl,spi"; + reg = <0x7000 0x1000>; + interrupts = <16 0x8>; + interrupt-parent = <&ipic>; + mode = "cpu"; + }; + + /* phy type (ULPI or SERIAL) are only types supported for MPH */ + /* port = 0 or 1 */ + usb@22000 { + compatible = "fsl-usb2-mph"; + reg = <0x22000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupt-parent = <&ipic>; + interrupts = <39 0x8>; + phy_type = "ulpi"; + port1; + }; + /* phy type (ULPI, UTMI, UTMI_WIDE, SERIAL) */ + usb@23000 { + compatible = "fsl-usb2-dr"; + reg = <0x23000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupt-parent = <&ipic>; + interrupts = <38 0x8>; + dr_mode = "otg"; + phy_type = "ulpi"; + }; + + mdio@24520 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,gianfar-mdio"; + reg = <0x24520 0x20>; + + phy0: ethernet-phy@0 { + interrupt-parent = <&ipic>; + interrupts = <17 0x8>; + reg = <0x1>; + device_type = "ethernet-phy"; + }; + phy1: ethernet-phy@1 { + interrupt-parent = <&ipic>; + interrupts = <18 0x8>; + reg = <0x2>; + device_type = "ethernet-phy"; + }; + }; + + enet0: ethernet@24000 { + cell-index = <0>; + device_type = "network"; + model = "TSEC"; + compatible = "gianfar"; + reg = <0x24000 0x1000>; + local-mac-address = [ 00 08 e5 11 32 33 ]; + interrupts = <32 0x8 33 0x8 34 0x8>; + interrupt-parent = <&ipic>; + phy-handle = <&phy0>; + linux,network-index = <0>; + }; + + enet1: ethernet@25000 { + cell-index = <1>; + device_type = "network"; + model = "TSEC"; + compatible = "gianfar"; + reg = <0x25000 0x1000>; + local-mac-address = [ 00 08 e5 11 32 34 ]; + interrupts = <35 0x8 36 0x8 37 0x8>; + interrupt-parent = <&ipic>; + phy-handle = <&phy1>; + linux,network-index = <1>; + }; + + serial0: serial@4500 { + cell-index = <0>; + device_type = "serial"; + compatible = "ns16550"; + reg = <0x4500 0x100>; + clock-frequency = <400000000>; + interrupts = <9 0x8>; + interrupt-parent = <&ipic>; + }; + + serial1: serial@4600 { + cell-index = <1>; + device_type = "serial"; + compatible = "ns16550"; + reg = <0x4600 0x100>; + clock-frequency = <400000000>; + interrupts = <10 0x8>; + interrupt-parent = <&ipic>; + }; + + /* May need to remove if on a part without crypto engine */ + crypto@30000 { + device_type = "crypto"; + model = "SEC2"; + compatible = "talitos"; + reg = <0x30000 0x10000>; + interrupts = <11 0x8>; + interrupt-parent = <&ipic>; + num-channels = <4>; + channel-fifo-len = <24>; + exec-units-mask = <0x0000007e>; + /* desc mask is for rev2.0, + * we need runtime fixup for >2.0 */ + descriptor-types-mask = <0x01010ebf>; + }; + + /* IPIC + * interrupts cell = + * sense values match linux IORESOURCE_IRQ_* defines: + * sense == 8: Level, low assertion + * sense == 2: Edge, high-to-low change + */ + ipic: pic@700 { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <2>; + reg = <0x700 0x100>; + device_type = "ipic"; + }; + }; + + chosen { + bootargs = "console=ttyS0,38400 root=/dev/mtdblock3 rootfstype=jffs2"; + linux,stdout-path = &serial0; + }; + +}; diff --git a/arch/powerpc/boot/redboot-83xx.c b/arch/powerpc/boot/redboot-83xx.c new file mode 100644 index 0000000..79aa9e1 --- /dev/null +++ b/arch/powerpc/boot/redboot-83xx.c @@ -0,0 +1,60 @@ +/* + * RedBoot firmware support + * + * Author: Scott Wood + * + * Copyright (c) 2007 Freescale Semiconductor, Inc. + * Copyright (c) 2008 Codehermit + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include "ops.h" +#include "stdio.h" +#include "redboot.h" +#include "fsl-soc.h" +#include "io.h" + +static bd_t bd; +BSS_STACK(4096); + +#define MHZ(x) ((x + 500000) / 1000000) + +static void platform_fixups(void) +{ + void *node; + + dt_fixup_memory(bd.bi_memstart, bd.bi_memsize); + dt_fixup_mac_addresses(bd.bi_enetaddr); + dt_fixup_cpu_clocks(bd.bi_intfreq, bd.bi_busfreq / 16, bd.bi_busfreq); + + node = finddevice("/soc/cpm/brg"); + if (node) { + printf("BRG clock-frequency <- 0x%x (%dMHz)\r\n", + bd.bi_busfreq, MHZ(bd.bi_busfreq)); + setprop(node, "clock-frequency", &bd.bi_busfreq, 4); + } + +} + +void platform_init(unsigned long r3, unsigned long r4, unsigned long r5, + unsigned long r6, unsigned long r7) +{ + memcpy(&bd, (char *)r3, sizeof(bd)); + + if (bd.bi_tag != 0x42444944) + return; + + simple_alloc_init(_end, + bd.bi_memstart + bd.bi_memsize - (unsigned long)_end, + 32, 64); + + fdt_init(_dtb_start); + serial_console_init(); + platform_ops.fixups = platform_fixups; + + loader_info.cmdline = (char *)bd.bi_cmdline; + loader_info.cmdline_len = strlen((char *)bd.bi_cmdline); +} diff --git a/arch/powerpc/boot/wrapper b/arch/powerpc/boot/wrapper index d6c96d9..4832be8 100755 --- a/arch/powerpc/boot/wrapper +++ b/arch/powerpc/boot/wrapper @@ -171,7 +171,7 @@ cuboot*) *-mpc824*) platformo=$object/cuboot-824x.o ;; - *-mpc83*) + *-mpc83*|*-asp834x*) platformo=$object/cuboot-83xx.o ;; *-tqm8541|*-mpc8560*|*-tqm8560|*-tqm8555|*-ksi8560*) @@ -203,6 +203,10 @@ simpleboot-virtex405-*) platformo="$object/virtex405-head.o $object/simpleboot.o" binary=y ;; +asp834x-redboot) + platformo="$object/fixed-head.o $object/redboot-83xx.o" + binary=y + ;; esac vmz="$tmpdir/`basename \"$kernel\"`.$ext" -- cgit v1.1 From acd4b715ec83e451990bb82bdbf28ecaeab1b67d Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Fri, 30 May 2008 12:12:26 -0500 Subject: [POWERPC] Cleanup mpic nodes in .dts Removed clock-frequency, big-endian, and built-in props as they aren't specified anywhere. Also added compatible = "chrp,open-pic" in the places it was missing. Signed-off-by: Kumar Gala --- arch/powerpc/boot/dts/mpc7448hpc2.dts | 2 -- arch/powerpc/boot/dts/mpc8540ads.dts | 2 -- arch/powerpc/boot/dts/mpc8541cds.dts | 2 -- arch/powerpc/boot/dts/mpc8544ds.dts | 2 -- arch/powerpc/boot/dts/mpc8548cds.dts | 2 -- arch/powerpc/boot/dts/mpc8555cds.dts | 2 -- arch/powerpc/boot/dts/mpc8560ads.dts | 1 + arch/powerpc/boot/dts/mpc8568mds.dts | 2 -- arch/powerpc/boot/dts/mpc8572ds.dts | 2 -- arch/powerpc/boot/dts/mpc8610_hpcd.dts | 2 -- arch/powerpc/boot/dts/mpc8641_hpcn.dts | 2 -- arch/powerpc/boot/dts/sbc8548.dts | 2 -- arch/powerpc/boot/dts/sbc8560.dts | 2 +- arch/powerpc/boot/dts/storcenter.dts | 1 + arch/powerpc/boot/dts/stx_gp3_8560.dts | 1 + arch/powerpc/boot/dts/tqm8540.dts | 1 + arch/powerpc/boot/dts/tqm8541.dts | 1 + arch/powerpc/boot/dts/tqm8555.dts | 1 + arch/powerpc/boot/dts/tqm8560.dts | 1 + 19 files changed, 8 insertions(+), 23 deletions(-) (limited to 'arch/powerpc/boot') diff --git a/arch/powerpc/boot/dts/mpc7448hpc2.dts b/arch/powerpc/boot/dts/mpc7448hpc2.dts index 4936349..705c23c 100644 --- a/arch/powerpc/boot/dts/mpc7448hpc2.dts +++ b/arch/powerpc/boot/dts/mpc7448hpc2.dts @@ -124,14 +124,12 @@ }; mpic: pic@7400 { - clock-frequency = <0>; interrupt-controller; #address-cells = <0>; #interrupt-cells = <2>; reg = <0x7400 0x400>; compatible = "chrp,open-pic"; device_type = "open-pic"; - big-endian; }; pci@1000 { compatible = "tsi108-pci"; diff --git a/arch/powerpc/boot/dts/mpc8540ads.dts b/arch/powerpc/boot/dts/mpc8540ads.dts index 18033ed..58e165e 100644 --- a/arch/powerpc/boot/dts/mpc8540ads.dts +++ b/arch/powerpc/boot/dts/mpc8540ads.dts @@ -165,14 +165,12 @@ interrupt-parent = <&mpic>; }; mpic: pic@40000 { - clock-frequency = <0>; interrupt-controller; #address-cells = <0>; #interrupt-cells = <2>; reg = <0x40000 0x40000>; compatible = "chrp,open-pic"; device_type = "open-pic"; - big-endian; }; }; diff --git a/arch/powerpc/boot/dts/mpc8541cds.dts b/arch/powerpc/boot/dts/mpc8541cds.dts index 663c7c5..21ebe7c 100644 --- a/arch/powerpc/boot/dts/mpc8541cds.dts +++ b/arch/powerpc/boot/dts/mpc8541cds.dts @@ -148,14 +148,12 @@ }; mpic: pic@40000 { - clock-frequency = <0>; interrupt-controller; #address-cells = <0>; #interrupt-cells = <2>; reg = <0x40000 0x40000>; compatible = "chrp,open-pic"; device_type = "open-pic"; - big-endian; }; cpm@919c0 { diff --git a/arch/powerpc/boot/dts/mpc8544ds.dts b/arch/powerpc/boot/dts/mpc8544ds.dts index 1cfd970..921f9f6 100644 --- a/arch/powerpc/boot/dts/mpc8544ds.dts +++ b/arch/powerpc/boot/dts/mpc8544ds.dts @@ -210,14 +210,12 @@ }; mpic: pic@40000 { - clock-frequency = <0>; interrupt-controller; #address-cells = <0>; #interrupt-cells = <2>; reg = <0x40000 0x40000>; compatible = "chrp,open-pic"; device_type = "open-pic"; - big-endian; }; msi@41600 { diff --git a/arch/powerpc/boot/dts/mpc8548cds.dts b/arch/powerpc/boot/dts/mpc8548cds.dts index fa298a8..213c88e 100644 --- a/arch/powerpc/boot/dts/mpc8548cds.dts +++ b/arch/powerpc/boot/dts/mpc8548cds.dts @@ -208,14 +208,12 @@ }; mpic: pic@40000 { - clock-frequency = <0>; interrupt-controller; #address-cells = <0>; #interrupt-cells = <2>; reg = <0x40000 0x40000>; compatible = "chrp,open-pic"; device_type = "open-pic"; - big-endian; }; }; diff --git a/arch/powerpc/boot/dts/mpc8555cds.dts b/arch/powerpc/boot/dts/mpc8555cds.dts index b025c56..400f6db 100644 --- a/arch/powerpc/boot/dts/mpc8555cds.dts +++ b/arch/powerpc/boot/dts/mpc8555cds.dts @@ -148,14 +148,12 @@ }; mpic: pic@40000 { - clock-frequency = <0>; interrupt-controller; #address-cells = <0>; #interrupt-cells = <2>; reg = <0x40000 0x40000>; compatible = "chrp,open-pic"; device_type = "open-pic"; - big-endian; }; cpm@919c0 { diff --git a/arch/powerpc/boot/dts/mpc8560ads.dts b/arch/powerpc/boot/dts/mpc8560ads.dts index 0cc16ab..f0b1f98 100644 --- a/arch/powerpc/boot/dts/mpc8560ads.dts +++ b/arch/powerpc/boot/dts/mpc8560ads.dts @@ -134,6 +134,7 @@ #address-cells = <0>; #interrupt-cells = <2>; reg = <0x40000 0x40000>; + compatible = "chrp,open-pic"; device_type = "open-pic"; }; diff --git a/arch/powerpc/boot/dts/mpc8568mds.dts b/arch/powerpc/boot/dts/mpc8568mds.dts index a025a8e..d9064ee 100644 --- a/arch/powerpc/boot/dts/mpc8568mds.dts +++ b/arch/powerpc/boot/dts/mpc8568mds.dts @@ -202,14 +202,12 @@ }; mpic: pic@40000 { - clock-frequency = <0>; interrupt-controller; #address-cells = <0>; #interrupt-cells = <2>; reg = <0x40000 0x40000>; compatible = "chrp,open-pic"; device_type = "open-pic"; - big-endian; }; par_io@e0100 { diff --git a/arch/powerpc/boot/dts/mpc8572ds.dts b/arch/powerpc/boot/dts/mpc8572ds.dts index 174d51a..3ca8cae 100644 --- a/arch/powerpc/boot/dts/mpc8572ds.dts +++ b/arch/powerpc/boot/dts/mpc8572ds.dts @@ -238,14 +238,12 @@ }; mpic: pic@40000 { - clock-frequency = <0>; interrupt-controller; #address-cells = <0>; #interrupt-cells = <2>; reg = <0x40000 0x40000>; compatible = "chrp,open-pic"; device_type = "open-pic"; - big-endian; }; }; diff --git a/arch/powerpc/boot/dts/mpc8610_hpcd.dts b/arch/powerpc/boot/dts/mpc8610_hpcd.dts index fa9c297..186f102 100644 --- a/arch/powerpc/boot/dts/mpc8610_hpcd.dts +++ b/arch/powerpc/boot/dts/mpc8610_hpcd.dts @@ -172,14 +172,12 @@ }; mpic: interrupt-controller@40000 { - clock-frequency = <0>; interrupt-controller; #address-cells = <0>; #interrupt-cells = <2>; reg = <0x40000 0x40000>; compatible = "chrp,open-pic"; device_type = "open-pic"; - big-endian; }; msi@41600 { diff --git a/arch/powerpc/boot/dts/mpc8641_hpcn.dts b/arch/powerpc/boot/dts/mpc8641_hpcn.dts index 1e4bfe9..14f718d 100644 --- a/arch/powerpc/boot/dts/mpc8641_hpcn.dts +++ b/arch/powerpc/boot/dts/mpc8641_hpcn.dts @@ -239,14 +239,12 @@ }; mpic: pic@40000 { - clock-frequency = <0>; interrupt-controller; #address-cells = <0>; #interrupt-cells = <2>; reg = <0x40000 0x40000>; compatible = "chrp,open-pic"; device_type = "open-pic"; - big-endian; }; global-utilities@e0000 { diff --git a/arch/powerpc/boot/dts/sbc8548.dts b/arch/powerpc/boot/dts/sbc8548.dts index 22d9671..ce496fb 100644 --- a/arch/powerpc/boot/dts/sbc8548.dts +++ b/arch/powerpc/boot/dts/sbc8548.dts @@ -265,12 +265,10 @@ mpic: pic@40000 { interrupt-controller; #address-cells = <0>; - #size-cells = <0>; #interrupt-cells = <2>; reg = <0x40000 0x40000>; compatible = "chrp,open-pic"; device_type = "open-pic"; - big-endian; }; }; diff --git a/arch/powerpc/boot/dts/sbc8560.dts b/arch/powerpc/boot/dts/sbc8560.dts index 0476802..2663501 100644 --- a/arch/powerpc/boot/dts/sbc8560.dts +++ b/arch/powerpc/boot/dts/sbc8560.dts @@ -155,8 +155,8 @@ mpic: pic@40000 { interrupt-controller; #address-cells = <0>; - #size-cells = <0>; #interrupt-cells = <2>; + compatible = "chrp,open-pic"; reg = <0x40000 0x40000>; device_type = "open-pic"; }; diff --git a/arch/powerpc/boot/dts/storcenter.dts b/arch/powerpc/boot/dts/storcenter.dts index 5893816..eab680c 100644 --- a/arch/powerpc/boot/dts/storcenter.dts +++ b/arch/powerpc/boot/dts/storcenter.dts @@ -95,6 +95,7 @@ mpic: interrupt-controller@40000 { #interrupt-cells = <2>; + #address-cells = <0>; device_type = "open-pic"; compatible = "chrp,open-pic"; interrupt-controller; diff --git a/arch/powerpc/boot/dts/stx_gp3_8560.dts b/arch/powerpc/boot/dts/stx_gp3_8560.dts index f81fd7f..096277b 100644 --- a/arch/powerpc/boot/dts/stx_gp3_8560.dts +++ b/arch/powerpc/boot/dts/stx_gp3_8560.dts @@ -131,6 +131,7 @@ #address-cells = <0>; #interrupt-cells = <2>; reg = <0x40000 0x40000>; + compatible = "chrp,open-pic"; device_type = "open-pic"; }; diff --git a/arch/powerpc/boot/dts/tqm8540.dts b/arch/powerpc/boot/dts/tqm8540.dts index 1addb3a..8ee4664 100644 --- a/arch/powerpc/boot/dts/tqm8540.dts +++ b/arch/powerpc/boot/dts/tqm8540.dts @@ -177,6 +177,7 @@ #interrupt-cells = <2>; reg = <0x40000 0x40000>; device_type = "open-pic"; + compatible = "chrp,open-pic"; }; }; diff --git a/arch/powerpc/boot/dts/tqm8541.dts b/arch/powerpc/boot/dts/tqm8541.dts index 9e01093..cadbebf 100644 --- a/arch/powerpc/boot/dts/tqm8541.dts +++ b/arch/powerpc/boot/dts/tqm8541.dts @@ -164,6 +164,7 @@ #interrupt-cells = <2>; reg = <0x40000 0x40000>; device_type = "open-pic"; + compatible = "chrp,open-pic"; }; cpm@919c0 { diff --git a/arch/powerpc/boot/dts/tqm8555.dts b/arch/powerpc/boot/dts/tqm8555.dts index a20eb06..9d6dc04 100644 --- a/arch/powerpc/boot/dts/tqm8555.dts +++ b/arch/powerpc/boot/dts/tqm8555.dts @@ -164,6 +164,7 @@ #interrupt-cells = <2>; reg = <0x40000 0x40000>; device_type = "open-pic"; + compatible = "chrp,open-pic"; }; cpm@919c0 { diff --git a/arch/powerpc/boot/dts/tqm8560.dts b/arch/powerpc/boot/dts/tqm8560.dts index b9ac6c9..358cbd7 100644 --- a/arch/powerpc/boot/dts/tqm8560.dts +++ b/arch/powerpc/boot/dts/tqm8560.dts @@ -145,6 +145,7 @@ #interrupt-cells = <2>; reg = <0x40000 0x40000>; device_type = "open-pic"; + compatible = "chrp,open-pic"; }; cpm@919c0 { -- cgit v1.1 From c054065bc10a7ee2bcf78b5bc95f4b4d9bdc923a Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Fri, 30 May 2008 13:43:43 -0500 Subject: [POWERPC] 85xx: Add next-level-cache property Added next-level-cache to the L1 and a reference to the new L2 label. This is per the ePAPR 0.94 spec. Since we are't really dependent on this today we aren't supporting the "legacy" l2-cache phandle that is specified in the PPC v2.1 OF Binding spec. Signed-off-by: Kumar Gala --- arch/powerpc/boot/dts/ksi8560.dts | 3 ++- arch/powerpc/boot/dts/mpc8540ads.dts | 3 ++- arch/powerpc/boot/dts/mpc8541cds.dts | 3 ++- arch/powerpc/boot/dts/mpc8544ds.dts | 3 ++- arch/powerpc/boot/dts/mpc8548cds.dts | 3 ++- arch/powerpc/boot/dts/mpc8555cds.dts | 3 ++- arch/powerpc/boot/dts/mpc8560ads.dts | 2 +- arch/powerpc/boot/dts/mpc8568mds.dts | 3 ++- arch/powerpc/boot/dts/mpc8572ds.dts | 4 +++- arch/powerpc/boot/dts/sbc8548.dts | 3 ++- arch/powerpc/boot/dts/sbc8560.dts | 3 ++- arch/powerpc/boot/dts/stx_gp3_8560.dts | 3 ++- arch/powerpc/boot/dts/tqm8540.dts | 3 ++- arch/powerpc/boot/dts/tqm8541.dts | 3 ++- arch/powerpc/boot/dts/tqm8555.dts | 3 ++- arch/powerpc/boot/dts/tqm8560.dts | 3 ++- 16 files changed, 32 insertions(+), 16 deletions(-) (limited to 'arch/powerpc/boot') diff --git a/arch/powerpc/boot/dts/ksi8560.dts b/arch/powerpc/boot/dts/ksi8560.dts index f869ce3c..6eb7c77 100644 --- a/arch/powerpc/boot/dts/ksi8560.dts +++ b/arch/powerpc/boot/dts/ksi8560.dts @@ -40,6 +40,7 @@ timebase-frequency = <0>; /* From U-boot */ bus-frequency = <0>; /* From U-boot */ clock-frequency = <0>; /* From U-boot */ + next-level-cache = <&L2>; }; }; @@ -62,7 +63,7 @@ interrupts = <0x12 0x2>; }; - l2-cache-controller@20000 { + L2: l2-cache-controller@20000 { compatible = "fsl,8540-l2-cache-controller"; reg = <0x20000 0x1000>; cache-line-size = <0x20>; /* 32 bytes */ diff --git a/arch/powerpc/boot/dts/mpc8540ads.dts b/arch/powerpc/boot/dts/mpc8540ads.dts index 58e165e..79881a1 100644 --- a/arch/powerpc/boot/dts/mpc8540ads.dts +++ b/arch/powerpc/boot/dts/mpc8540ads.dts @@ -40,6 +40,7 @@ timebase-frequency = <0>; // 33 MHz, from uboot bus-frequency = <0>; // 166 MHz clock-frequency = <0>; // 825 MHz, from uboot + next-level-cache = <&L2>; }; }; @@ -63,7 +64,7 @@ interrupts = <18 2>; }; - l2-cache-controller@20000 { + L2: l2-cache-controller@20000 { compatible = "fsl,8540-l2-cache-controller"; reg = <0x20000 0x1000>; cache-line-size = <32>; // 32 bytes diff --git a/arch/powerpc/boot/dts/mpc8541cds.dts b/arch/powerpc/boot/dts/mpc8541cds.dts index 21ebe7c..66192aa 100644 --- a/arch/powerpc/boot/dts/mpc8541cds.dts +++ b/arch/powerpc/boot/dts/mpc8541cds.dts @@ -40,6 +40,7 @@ timebase-frequency = <0>; // 33 MHz, from uboot bus-frequency = <0>; // 166 MHz clock-frequency = <0>; // 825 MHz, from uboot + next-level-cache = <&L2>; }; }; @@ -63,7 +64,7 @@ interrupts = <18 2>; }; - l2-cache-controller@20000 { + L2: l2-cache-controller@20000 { compatible = "fsl,8541-l2-cache-controller"; reg = <0x20000 0x1000>; cache-line-size = <32>; // 32 bytes diff --git a/arch/powerpc/boot/dts/mpc8544ds.dts b/arch/powerpc/boot/dts/mpc8544ds.dts index 921f9f6..6cf533f 100644 --- a/arch/powerpc/boot/dts/mpc8544ds.dts +++ b/arch/powerpc/boot/dts/mpc8544ds.dts @@ -41,6 +41,7 @@ timebase-frequency = <0>; bus-frequency = <0>; clock-frequency = <0>; + next-level-cache = <&L2>; }; }; @@ -65,7 +66,7 @@ interrupts = <18 2>; }; - l2-cache-controller@20000 { + L2: l2-cache-controller@20000 { compatible = "fsl,8544-l2-cache-controller"; reg = <0x20000 0x1000>; cache-line-size = <32>; // 32 bytes diff --git a/arch/powerpc/boot/dts/mpc8548cds.dts b/arch/powerpc/boot/dts/mpc8548cds.dts index 213c88e..205598d 100644 --- a/arch/powerpc/boot/dts/mpc8548cds.dts +++ b/arch/powerpc/boot/dts/mpc8548cds.dts @@ -45,6 +45,7 @@ timebase-frequency = <0>; // 33 MHz, from uboot bus-frequency = <0>; // 166 MHz clock-frequency = <0>; // 825 MHz, from uboot + next-level-cache = <&L2>; }; }; @@ -68,7 +69,7 @@ interrupts = <18 2>; }; - l2-cache-controller@20000 { + L2: l2-cache-controller@20000 { compatible = "fsl,8548-l2-cache-controller"; reg = <0x20000 0x1000>; cache-line-size = <32>; // 32 bytes diff --git a/arch/powerpc/boot/dts/mpc8555cds.dts b/arch/powerpc/boot/dts/mpc8555cds.dts index 400f6db..7c9d0b1 100644 --- a/arch/powerpc/boot/dts/mpc8555cds.dts +++ b/arch/powerpc/boot/dts/mpc8555cds.dts @@ -40,6 +40,7 @@ timebase-frequency = <0>; // 33 MHz, from uboot bus-frequency = <0>; // 166 MHz clock-frequency = <0>; // 825 MHz, from uboot + next-level-cache = <&L2>; }; }; @@ -63,7 +64,7 @@ interrupts = <18 2>; }; - l2-cache-controller@20000 { + L2: l2-cache-controller@20000 { compatible = "fsl,8555-l2-cache-controller"; reg = <0x20000 0x1000>; cache-line-size = <32>; // 32 bytes diff --git a/arch/powerpc/boot/dts/mpc8560ads.dts b/arch/powerpc/boot/dts/mpc8560ads.dts index f0b1f98..5d9f3c4 100644 --- a/arch/powerpc/boot/dts/mpc8560ads.dts +++ b/arch/powerpc/boot/dts/mpc8560ads.dts @@ -64,7 +64,7 @@ interrupts = <18 2>; }; - l2-cache-controller@20000 { + L2: l2-cache-controller@20000 { compatible = "fsl,8540-l2-cache-controller"; reg = <0x20000 0x1000>; cache-line-size = <32>; // 32 bytes diff --git a/arch/powerpc/boot/dts/mpc8568mds.dts b/arch/powerpc/boot/dts/mpc8568mds.dts index d9064ee..d7af8db 100644 --- a/arch/powerpc/boot/dts/mpc8568mds.dts +++ b/arch/powerpc/boot/dts/mpc8568mds.dts @@ -42,6 +42,7 @@ timebase-frequency = <0>; bus-frequency = <0>; clock-frequency = <0>; + next-level-cache = <&L2>; }; }; @@ -70,7 +71,7 @@ interrupts = <18 2>; }; - l2-cache-controller@20000 { + L2: l2-cache-controller@20000 { compatible = "fsl,8568-l2-cache-controller"; reg = <0x20000 0x1000>; cache-line-size = <32>; // 32 bytes diff --git a/arch/powerpc/boot/dts/mpc8572ds.dts b/arch/powerpc/boot/dts/mpc8572ds.dts index 3ca8cae..a444e6a 100644 --- a/arch/powerpc/boot/dts/mpc8572ds.dts +++ b/arch/powerpc/boot/dts/mpc8572ds.dts @@ -42,6 +42,7 @@ timebase-frequency = <0>; bus-frequency = <0>; clock-frequency = <0>; + next-level-cache = <&L2>; }; PowerPC,8572@1 { @@ -54,6 +55,7 @@ timebase-frequency = <0>; bus-frequency = <0>; clock-frequency = <0>; + next-level-cache = <&L2>; }; }; @@ -84,7 +86,7 @@ interrupts = <18 2>; }; - l2-cache-controller@20000 { + L2: l2-cache-controller@20000 { compatible = "fsl,mpc8572-l2-cache-controller"; reg = <0x20000 0x1000>; cache-line-size = <32>; // 32 bytes diff --git a/arch/powerpc/boot/dts/sbc8548.dts b/arch/powerpc/boot/dts/sbc8548.dts index ce496fb..d252e38 100644 --- a/arch/powerpc/boot/dts/sbc8548.dts +++ b/arch/powerpc/boot/dts/sbc8548.dts @@ -44,6 +44,7 @@ timebase-frequency = <0>; // From uboot bus-frequency = <0>; clock-frequency = <0>; + next-level-cache = <&L2>; }; }; @@ -161,7 +162,7 @@ interrupts = <0x12 0x2>; }; - l2-cache-controller@20000 { + L2: l2-cache-controller@20000 { compatible = "fsl,8548-l2-cache-controller"; reg = <0x20000 0x1000>; cache-line-size = <0x20>; // 32 bytes diff --git a/arch/powerpc/boot/dts/sbc8560.dts b/arch/powerpc/boot/dts/sbc8560.dts index 2663501..e556c5a 100644 --- a/arch/powerpc/boot/dts/sbc8560.dts +++ b/arch/powerpc/boot/dts/sbc8560.dts @@ -43,6 +43,7 @@ timebase-frequency = <0>; // From uboot bus-frequency = <0>; clock-frequency = <0>; + next-level-cache = <&L2>; }; }; @@ -66,7 +67,7 @@ interrupts = <0x12 0x2>; }; - l2-cache-controller@20000 { + L2: l2-cache-controller@20000 { compatible = "fsl,8560-l2-cache-controller"; reg = <0x20000 0x1000>; cache-line-size = <0x20>; // 32 bytes diff --git a/arch/powerpc/boot/dts/stx_gp3_8560.dts b/arch/powerpc/boot/dts/stx_gp3_8560.dts index 096277b..1e61283 100644 --- a/arch/powerpc/boot/dts/stx_gp3_8560.dts +++ b/arch/powerpc/boot/dts/stx_gp3_8560.dts @@ -38,6 +38,7 @@ timebase-frequency = <0>; bus-frequency = <0>; clock-frequency = <0>; + next-level-cache = <&L2>; }; }; @@ -62,7 +63,7 @@ interrupts = <18 2>; }; - l2-cache-controller@20000 { + L2: l2-cache-controller@20000 { compatible = "fsl,8540-l2-cache-controller"; reg = <0x20000 0x1000>; cache-line-size = <32>; diff --git a/arch/powerpc/boot/dts/tqm8540.dts b/arch/powerpc/boot/dts/tqm8540.dts index 8ee4664..7b653a5 100644 --- a/arch/powerpc/boot/dts/tqm8540.dts +++ b/arch/powerpc/boot/dts/tqm8540.dts @@ -40,6 +40,7 @@ timebase-frequency = <0>; bus-frequency = <0>; clock-frequency = <0>; + next-level-cache = <&L2>; }; }; @@ -64,7 +65,7 @@ interrupts = <18 2>; }; - l2-cache-controller@20000 { + L2: l2-cache-controller@20000 { compatible = "fsl,8540-l2-cache-controller"; reg = <0x20000 0x1000>; cache-line-size = <32>; diff --git a/arch/powerpc/boot/dts/tqm8541.dts b/arch/powerpc/boot/dts/tqm8541.dts index cadbebf..8fe73ef 100644 --- a/arch/powerpc/boot/dts/tqm8541.dts +++ b/arch/powerpc/boot/dts/tqm8541.dts @@ -39,6 +39,7 @@ timebase-frequency = <0>; bus-frequency = <0>; clock-frequency = <0>; + next-level-cache = <&L2>; }; }; @@ -63,7 +64,7 @@ interrupts = <18 2>; }; - l2-cache-controller@20000 { + L2: l2-cache-controller@20000 { compatible = "fsl,8540-l2-cache-controller"; reg = <0x20000 0x1000>; cache-line-size = <32>; diff --git a/arch/powerpc/boot/dts/tqm8555.dts b/arch/powerpc/boot/dts/tqm8555.dts index 9d6dc04..0a53bb9 100644 --- a/arch/powerpc/boot/dts/tqm8555.dts +++ b/arch/powerpc/boot/dts/tqm8555.dts @@ -39,6 +39,7 @@ timebase-frequency = <0>; bus-frequency = <0>; clock-frequency = <0>; + next-level-cache = <&L2>; }; }; @@ -63,7 +64,7 @@ interrupts = <18 2>; }; - l2-cache-controller@20000 { + L2: l2-cache-controller@20000 { compatible = "fsl,8540-l2-cache-controller"; reg = <0x20000 0x1000>; cache-line-size = <32>; diff --git a/arch/powerpc/boot/dts/tqm8560.dts b/arch/powerpc/boot/dts/tqm8560.dts index 358cbd7..a4ee596 100644 --- a/arch/powerpc/boot/dts/tqm8560.dts +++ b/arch/powerpc/boot/dts/tqm8560.dts @@ -40,6 +40,7 @@ timebase-frequency = <0>; bus-frequency = <0>; clock-frequency = <0>; + next-level-cache = <&L2>; }; }; @@ -64,7 +65,7 @@ interrupts = <18 2>; }; - l2-cache-controller@20000 { + L2: l2-cache-controller@20000 { compatible = "fsl,8540-l2-cache-controller"; reg = <0x20000 0x1000>; cache-line-size = <32>; -- cgit v1.1 From 61586476cda599c64ab2b8f4f808d6a615a2fab2 Mon Sep 17 00:00:00 2001 From: Remi Machet Date: Wed, 21 May 2008 03:30:24 +1000 Subject: powerpc: DTS file for the C2K Support for the C2K cPCI Single Board Computer from GEFanuc (PowerPC MPC7448 with a Marvell MV64460 chipset). All features of the board are not supported yet, but the board boots, flash works, all Ethernet ports are working and PCI devices are all found (USB and SATA on PCI1 do not work yet). Part 1 of 5: DTS file describing the board peripherals. As far as I know all peripherals except the FPGA are listed in there (I did not include the FPGA because a lot of work is needed there). Signed-off-by: Remi Machet Signed-off-by: Paul Mackerras --- arch/powerpc/boot/dts/c2k.dts | 371 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 371 insertions(+) create mode 100644 arch/powerpc/boot/dts/c2k.dts (limited to 'arch/powerpc/boot') diff --git a/arch/powerpc/boot/dts/c2k.dts b/arch/powerpc/boot/dts/c2k.dts new file mode 100644 index 0000000..f5d625f --- /dev/null +++ b/arch/powerpc/boot/dts/c2k.dts @@ -0,0 +1,371 @@ +/* Device Tree Source for GEFanuc C2K + * + * Author: Remi Machet + * + * Originated from prpmc2800.dts + * + * 2008 (c) Stanford University + * 2007 (c) MontaVista, Software, Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +/dts-v1/; + +/ { + #address-cells = <1>; + #size-cells = <1>; + model = "C2K"; + compatible = "GEFanuc,C2K"; + coherency-off; + + aliases { + pci0 = &PCI0; + pci1 = &PCI1; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "PowerPC,7447"; + reg = <0>; + clock-frequency = <996000000>; /* 996 MHz */ + bus-frequency = <166666667>; /* 166.6666 MHz */ + timebase-frequency = <41666667>; /* 166.6666/4 MHz */ + i-cache-line-size = <32>; + d-cache-line-size = <32>; + i-cache-size = <32768>; + d-cache-size = <32768>; + }; + }; + + memory { + device_type = "memory"; + reg = <0x00000000 0x40000000>; /* 1GB */ + }; + + system-controller@d8000000 { /* Marvell Discovery */ + #address-cells = <1>; + #size-cells = <1>; + model = "mv64460"; + compatible = "marvell,mv64360"; + clock-frequency = <166666667>; /* 166.66... MHz */ + reg = <0xd8000000 0x00010000>; + virtual-reg = <0xd8000000>; + ranges = <0xd4000000 0xd4000000 0x01000000 /* PCI 0 I/O Space */ + 0x80000000 0x80000000 0x08000000 /* PCI 0 MEM Space */ + 0xd0000000 0xd0000000 0x01000000 /* PCI 1 I/O Space */ + 0xa0000000 0xa0000000 0x08000000 /* PCI 1 MEM Space */ + 0xd8100000 0xd8100000 0x00010000 /* FPGA */ + 0xd8110000 0xd8110000 0x00010000 /* FPGA USARTs */ + 0xf8000000 0xf8000000 0x08000000 /* User FLASH */ + 0x00000000 0xd8000000 0x00010000 /* Bridge's regs */ + 0xd8140000 0xd8140000 0x00040000>; /* Integrated SRAM */ + + mdio@2000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "marvell,mv64360-mdio"; + reg = <0x2000 4>; + PHY0: ethernet-phy@0 { + device_type = "ethernet-phy"; + interrupts = <76>; /* GPP 12 */ + interrupt-parent = <&PIC>; + reg = <0>; + }; + PHY1: ethernet-phy@1 { + device_type = "ethernet-phy"; + interrupts = <76>; /* GPP 12 */ + interrupt-parent = <&PIC>; + reg = <1>; + }; + PHY2: ethernet-phy@2 { + device_type = "ethernet-phy"; + interrupts = <76>; /* GPP 12 */ + interrupt-parent = <&PIC>; + reg = <2>; + }; + }; + + ethernet-group@2000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "marvell,mv64360-eth-group"; + reg = <0x2000 0x2000>; + ethernet@0 { + device_type = "network"; + compatible = "marvell,mv64360-eth"; + reg = <0>; + interrupts = <32>; + interrupt-parent = <&PIC>; + phy = <&PHY0>; + local-mac-address = [ 00 00 00 00 00 00 ]; + }; + ethernet@1 { + device_type = "network"; + compatible = "marvell,mv64360-eth"; + reg = <1>; + interrupts = <33>; + interrupt-parent = <&PIC>; + phy = <&PHY1>; + local-mac-address = [ 00 00 00 00 00 00 ]; + }; + ethernet@2 { + device_type = "network"; + compatible = "marvell,mv64360-eth"; + reg = <2>; + interrupts = <34>; + interrupt-parent = <&PIC>; + phy = <&PHY2>; + local-mac-address = [ 00 00 00 00 00 00 ]; + }; + }; + + SDMA0: sdma@4000 { + compatible = "marvell,mv64360-sdma"; + reg = <0x4000 0xc18>; + virtual-reg = <0xd8004000>; + interrupt-base = <0>; + interrupts = <36>; + interrupt-parent = <&PIC>; + }; + + SDMA1: sdma@6000 { + compatible = "marvell,mv64360-sdma"; + reg = <0x6000 0xc18>; + virtual-reg = <0xd8006000>; + interrupt-base = <0>; + interrupts = <38>; + interrupt-parent = <&PIC>; + }; + + BRG0: brg@b200 { + compatible = "marvell,mv64360-brg"; + reg = <0xb200 0x8>; + clock-src = <8>; + clock-frequency = <133333333>; + current-speed = <115200>; + }; + + BRG1: brg@b208 { + compatible = "marvell,mv64360-brg"; + reg = <0xb208 0x8>; + clock-src = <8>; + clock-frequency = <133333333>; + current-speed = <115200>; + }; + + CUNIT: cunit@f200 { + reg = <0xf200 0x200>; + }; + + MPSCROUTING: mpscrouting@b400 { + reg = <0xb400 0xc>; + }; + + MPSCINTR: mpscintr@b800 { + reg = <0xb800 0x100>; + virtual-reg = <0xd800b800>; + }; + + MPSC0: mpsc@8000 { + device_type = "serial"; + compatible = "marvell,mv64360-mpsc"; + reg = <0x8000 0x38>; + virtual-reg = <0xd8008000>; + sdma = <&SDMA0>; + brg = <&BRG0>; + cunit = <&CUNIT>; + mpscrouting = <&MPSCROUTING>; + mpscintr = <&MPSCINTR>; + cell-index = <0>; + interrupts = <40>; + interrupt-parent = <&PIC>; + }; + + MPSC1: mpsc@9000 { + device_type = "serial"; + compatible = "marvell,mv64360-mpsc"; + reg = <0x9000 0x38>; + virtual-reg = <0xd8009000>; + sdma = <&SDMA1>; + brg = <&BRG1>; + cunit = <&CUNIT>; + mpscrouting = <&MPSCROUTING>; + mpscintr = <&MPSCINTR>; + cell-index = <1>; + interrupts = <42>; + interrupt-parent = <&PIC>; + }; + + wdt@b410 { /* watchdog timer */ + compatible = "marvell,mv64360-wdt"; + reg = <0xb410 0x8>; + }; + + i2c@c000 { + compatible = "marvell,mv64360-i2c"; + reg = <0xc000 0x20>; + virtual-reg = <0xd800c000>; + interrupts = <37>; + interrupt-parent = <&PIC>; + }; + + PIC: pic { + #interrupt-cells = <1>; + #address-cells = <0>; + compatible = "marvell,mv64360-pic"; + reg = <0x0000 0x88>; + interrupt-controller; + }; + + mpp@f000 { + compatible = "marvell,mv64360-mpp"; + reg = <0xf000 0x10>; + }; + + gpp@f100 { + compatible = "marvell,mv64360-gpp"; + reg = <0xf100 0x20>; + }; + + PCI0: pci@80000000 { + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + device_type = "pci"; + compatible = "marvell,mv64360-pci"; + reg = <0x0cf8 0x8>; + ranges = <0x01000000 0x0 0x00000000 0xd4000000 0x0 0x01000000 + 0x02000000 0x0 0x80000000 0x80000000 0x0 0x08000000>; + bus-range = <0 255>; + clock-frequency = <66000000>; + interrupt-pci-iack = <0x0c34>; + interrupt-parent = <&PIC>; + interrupt-map-mask = <0x0000 0x0 0x0 0x7>; + interrupt-map = < + /* Only one interrupt line for PMC0 slot (INTA) */ + 0x0000 0 0 1 &PIC 88 + >; + }; + + + PCI1: pci@a0000000 { + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + device_type = "pci"; + compatible = "marvell,mv64360-pci"; + reg = <0x0c78 0x8>; + ranges = <0x01000000 0x0 0x00000000 0xd0000000 0x0 0x01000000 + 0x02000000 0x0 0x80000000 0xa0000000 0x0 0x08000000>; + bus-range = <0 255>; + clock-frequency = <66000000>; + interrupt-pci-iack = <0x0cb4>; + interrupt-parent = <&PIC>; + interrupt-map-mask = <0xf800 0x00 0x00 0x7>; + interrupt-map = < + /* IDSEL 0x01: PMC1 ? */ + 0x0800 0 0 1 &PIC 88 + /* IDSEL 0x02: cPCI bridge */ + 0x1000 0 0 1 &PIC 88 + /* IDSEL 0x03: USB controller */ + 0x1800 0 0 1 &PIC 91 + /* IDSEL 0x04: SATA controller */ + 0x2000 0 0 1 &PIC 95 + >; + }; + + cpu-error@0070 { + compatible = "marvell,mv64360-cpu-error"; + reg = <0x0070 0x10 0x0128 0x28>; + interrupts = <3>; + interrupt-parent = <&PIC>; + }; + + sram-ctrl@0380 { + compatible = "marvell,mv64360-sram-ctrl"; + reg = <0x0380 0x80>; + interrupts = <13>; + interrupt-parent = <&PIC>; + }; + + pci-error@1d40 { + compatible = "marvell,mv64360-pci-error"; + reg = <0x1d40 0x40 0x0c28 0x4>; + interrupts = <12>; + interrupt-parent = <&PIC>; + }; + + pci-error@1dc0 { + compatible = "marvell,mv64360-pci-error"; + reg = <0x1dc0 0x40 0x0ca8 0x4>; + interrupts = <16>; + interrupt-parent = <&PIC>; + }; + + mem-ctrl@1400 { + compatible = "marvell,mv64360-mem-ctrl"; + reg = <0x1400 0x60>; + interrupts = <17>; + interrupt-parent = <&PIC>; + }; + /* Devices attached to the device controller */ + devicebus@045c { + #address-cells = <2>; + #size-cells = <1>; + compatible = "marvell,mv64306-devctrl"; + reg = <0x45C 0x88>; + interrupts = <1>; + interrupt-parent = <&PIC>; + ranges = <0 0 0xd8100000 0x10000 + 2 0 0xd8110000 0x10000 + 4 0 0xf8000000 0x8000000>; + fpga@0,0 { + compatible = "sbs,fpga-c2k"; + reg = <0 0 0x10000>; + }; + fpga_usart@2,0 { + compatible = "sbs,fpga_usart-c2k"; + reg = <2 0 0x10000>; + }; + nor_flash@4,0 { + compatible = "cfi-flash"; + reg = <4 0 0x8000000>; /* 128MB */ + bank-width = <4>; + device-width = <1>; + #address-cells = <1>; + #size-cells = <1>; + partition@0 { + label = "boot"; + reg = <0x00000000 0x00080000>; + }; + partition@40000 { + label = "kernel"; + reg = <0x00080000 0x00400000>; + }; + partition@440000 { + label = "initrd"; + reg = <0x00480000 0x00B80000>; + }; + partition@1000000 { + label = "rootfs"; + reg = <0x01000000 0x06800000>; + }; + partition@7800000 { + label = "recovery"; + reg = <0x07800000 0x00800000>; + read-only; + }; + }; + }; + }; + chosen { + linux,stdout-path = &MPSC0; + }; +}; -- cgit v1.1 From c6ec08e03dd06b8dfa3f6d938b0a89c6ed8475c9 Mon Sep 17 00:00:00 2001 From: Remi Machet Date: Wed, 21 May 2008 06:50:10 +1000 Subject: powerpc: Boot code for the C2K Support for the C2K cPCI Single Board Computer from GEFanuc (PowerPC MPC7448 with a Marvell MV64460 chipset). All features of the board are not supported yet, but the board boots, flash works, all Ethernet ports are working and PCI devices are all found (USB and SATA on PCI1 do not work yet). Part 2 of 5: support for the board in arch/powerpc/boot. Signed-off-by: Remi Machet Signed-off-by: Paul Mackerras --- arch/powerpc/boot/Makefile | 3 +- arch/powerpc/boot/cuboot-c2k.c | 190 +++++++++++++++++++++++++++++++++++++++++ 2 files changed, 192 insertions(+), 1 deletion(-) create mode 100644 arch/powerpc/boot/cuboot-c2k.c (limited to 'arch/powerpc/boot') diff --git a/arch/powerpc/boot/Makefile b/arch/powerpc/boot/Makefile index c3585be..e02fe36 100644 --- a/arch/powerpc/boot/Makefile +++ b/arch/powerpc/boot/Makefile @@ -63,7 +63,7 @@ src-plat := of.c cuboot-52xx.c cuboot-824x.c cuboot-83xx.c cuboot-85xx.c holly.c ps3-head.S ps3-hvcall.S ps3.c treeboot-bamboo.c cuboot-8xx.c \ cuboot-pq2.c cuboot-sequoia.c treeboot-walnut.c \ cuboot-bamboo.c cuboot-mpc7448hpc2.c cuboot-taishan.c \ - fixed-head.S ep88xc.c ep405.c \ + fixed-head.S ep88xc.c ep405.c cuboot-c2k.c \ cuboot-katmai.c cuboot-rainier.c redboot-8xx.c ep8248e.c \ cuboot-warp.c cuboot-85xx-cpm2.c cuboot-yosemite.c simpleboot.c \ virtex405-head.S redboot-83xx.c @@ -264,6 +264,7 @@ image-$(CONFIG_KSI8560) += cuImage.ksi8560 # Board ports in arch/powerpc/platform/embedded6xx/Kconfig image-$(CONFIG_STORCENTER) += cuImage.storcenter image-$(CONFIG_MPC7448HPC2) += cuImage.mpc7448hpc2 +image-$(CONFIG_PPC_C2K) += cuImage.c2k # For 32-bit powermacs, build the COFF and miboot images # as well as the ELF images. diff --git a/arch/powerpc/boot/cuboot-c2k.c b/arch/powerpc/boot/cuboot-c2k.c new file mode 100644 index 0000000..e435949 --- /dev/null +++ b/arch/powerpc/boot/cuboot-c2k.c @@ -0,0 +1,190 @@ +/* + * GEFanuc C2K platform code. + * + * Author: Remi Machet + * + * Originated from prpmc2800.c + * + * 2008 (c) Stanford University + * 2007 (c) MontaVista, Software, Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include "types.h" +#include "stdio.h" +#include "io.h" +#include "ops.h" +#include "elf.h" +#include "gunzip_util.h" +#include "mv64x60.h" +#include "cuboot.h" +#include "ppcboot.h" + +static u8 *bridge_base; + +static void c2k_bridge_setup(u32 mem_size) +{ + u32 i, v[30], enables, acc_bits; + u32 pci_base_hi, pci_base_lo, size, buf[2]; + unsigned long cpu_base; + int rc; + void *devp, *mv64x60_devp; + u8 *bridge_pbase, is_coherent; + struct mv64x60_cpu2pci_win *tbl; + int bus; + + bridge_pbase = mv64x60_get_bridge_pbase(); + is_coherent = mv64x60_is_coherent(); + + if (is_coherent) + acc_bits = MV64x60_PCI_ACC_CNTL_SNOOP_WB + | MV64x60_PCI_ACC_CNTL_SWAP_NONE + | MV64x60_PCI_ACC_CNTL_MBURST_32_BYTES + | MV64x60_PCI_ACC_CNTL_RDSIZE_32_BYTES; + else + acc_bits = MV64x60_PCI_ACC_CNTL_SNOOP_NONE + | MV64x60_PCI_ACC_CNTL_SWAP_NONE + | MV64x60_PCI_ACC_CNTL_MBURST_128_BYTES + | MV64x60_PCI_ACC_CNTL_RDSIZE_256_BYTES; + + mv64x60_config_ctlr_windows(bridge_base, bridge_pbase, is_coherent); + mv64x60_devp = find_node_by_compatible(NULL, "marvell,mv64360"); + if (mv64x60_devp == NULL) + fatal("Error: Missing marvell,mv64360 device tree node\n\r"); + + enables = in_le32((u32 *)(bridge_base + MV64x60_CPU_BAR_ENABLE)); + enables |= 0x007ffe00; /* Disable all cpu->pci windows */ + out_le32((u32 *)(bridge_base + MV64x60_CPU_BAR_ENABLE), enables); + + /* Get the cpu -> pci i/o & mem mappings from the device tree */ + devp = NULL; + for (bus = 0; ; bus++) { + char name[] = "pci "; + + name[strlen(name)-1] = bus+'0'; + + devp = find_node_by_alias(name); + if (devp == NULL) + break; + + if (bus >= 2) + fatal("Error: Only 2 PCI controllers are supported at" \ + " this time.\n"); + + mv64x60_config_pci_windows(bridge_base, bridge_pbase, bus, 0, + mem_size, acc_bits); + + rc = getprop(devp, "ranges", v, sizeof(v)); + if (rc == 0) + fatal("Error: Can't find marvell,mv64360-pci ranges" + " property\n\r"); + + /* Get the cpu -> pci i/o & mem mappings from the device tree */ + + for (i = 0; i < rc; i += 6) { + switch (v[i] & 0xff000000) { + case 0x01000000: /* PCI I/O Space */ + tbl = mv64x60_cpu2pci_io; + break; + case 0x02000000: /* PCI MEM Space */ + tbl = mv64x60_cpu2pci_mem; + break; + default: + continue; + } + + pci_base_hi = v[i+1]; + pci_base_lo = v[i+2]; + cpu_base = v[i+3]; + size = v[i+5]; + + buf[0] = cpu_base; + buf[1] = size; + + if (!dt_xlate_addr(devp, buf, sizeof(buf), &cpu_base)) + fatal("Error: Can't translate PCI address " \ + "0x%x\n\r", (u32)cpu_base); + + mv64x60_config_cpu2pci_window(bridge_base, bus, + pci_base_hi, pci_base_lo, cpu_base, size, tbl); + } + + enables &= ~(3<<(9+bus*5)); /* Enable cpu->pci i/o, + cpu->pci mem0 */ + out_le32((u32 *)(bridge_base + MV64x60_CPU_BAR_ENABLE), + enables); + }; +} + +static void c2k_fixups(void) +{ + u32 mem_size; + + mem_size = mv64x60_get_mem_size(bridge_base); + c2k_bridge_setup(mem_size); /* Do necessary bridge setup */ +} + +#define MV64x60_MPP_CNTL_0 0xf000 +#define MV64x60_MPP_CNTL_2 0xf008 +#define MV64x60_GPP_IO_CNTL 0xf100 +#define MV64x60_GPP_LEVEL_CNTL 0xf110 +#define MV64x60_GPP_VALUE_SET 0xf118 + +static void c2k_reset(void) +{ + u32 temp; + + udelay(5000000); + + if (bridge_base != 0) { + temp = in_le32((u32 *)(bridge_base + MV64x60_MPP_CNTL_0)); + temp &= 0xFFFF0FFF; + out_le32((u32 *)(bridge_base + MV64x60_MPP_CNTL_0), temp); + + temp = in_le32((u32 *)(bridge_base + MV64x60_GPP_LEVEL_CNTL)); + temp |= 0x00000004; + out_le32((u32 *)(bridge_base + MV64x60_GPP_LEVEL_CNTL), temp); + + temp = in_le32((u32 *)(bridge_base + MV64x60_GPP_IO_CNTL)); + temp |= 0x00000004; + out_le32((u32 *)(bridge_base + MV64x60_GPP_IO_CNTL), temp); + + temp = in_le32((u32 *)(bridge_base + MV64x60_MPP_CNTL_2)); + temp &= 0xFFFF0FFF; + out_le32((u32 *)(bridge_base + MV64x60_MPP_CNTL_2), temp); + + temp = in_le32((u32 *)(bridge_base + MV64x60_GPP_LEVEL_CNTL)); + temp |= 0x00080000; + out_le32((u32 *)(bridge_base + MV64x60_GPP_LEVEL_CNTL), temp); + + temp = in_le32((u32 *)(bridge_base + MV64x60_GPP_IO_CNTL)); + temp |= 0x00080000; + out_le32((u32 *)(bridge_base + MV64x60_GPP_IO_CNTL), temp); + + out_le32((u32 *)(bridge_base + MV64x60_GPP_VALUE_SET), + 0x00080004); + } + + for (;;); +} + +static bd_t bd; + +void platform_init(unsigned long r3, unsigned long r4, unsigned long r5, + unsigned long r6, unsigned long r7) +{ + CUBOOT_INIT(); + + fdt_init(_dtb_start); + + bridge_base = mv64x60_get_bridge_base(); + + platform_ops.fixups = c2k_fixups; + platform_ops.exit = c2k_reset; + + if (serial_console_init() < 0) + exit(); +} -- cgit v1.1 From 4fb035f69e3d08506b65d33b97be1b0e78af39a2 Mon Sep 17 00:00:00 2001 From: Wolfgang Grandegger Date: Fri, 6 Jun 2008 13:50:03 +0200 Subject: powerpc/85xx: correct vendor prefix in DTS files for TQM85xx modules Like for the TQM5200, the vendor prefix "tqc," is now used for all TQM85xx modules from TQ-Components GmbH (http://www.tqc.de) in the corresponding DTS files. Signed-off-by: Wolfgang Grandegger Signed-off-by: Kumar Gala --- arch/powerpc/boot/dts/tqm8540.dts | 4 ++-- arch/powerpc/boot/dts/tqm8541.dts | 4 ++-- arch/powerpc/boot/dts/tqm8555.dts | 4 ++-- arch/powerpc/boot/dts/tqm8560.dts | 4 ++-- 4 files changed, 8 insertions(+), 8 deletions(-) (limited to 'arch/powerpc/boot') diff --git a/arch/powerpc/boot/dts/tqm8540.dts b/arch/powerpc/boot/dts/tqm8540.dts index 7b653a5..3504db3 100644 --- a/arch/powerpc/boot/dts/tqm8540.dts +++ b/arch/powerpc/boot/dts/tqm8540.dts @@ -12,8 +12,8 @@ /dts-v1/; / { - model = "tqm,8540"; - compatible = "tqm,8540", "tqm,85xx"; + model = "tqc,tqm8540"; + compatible = "tqc,tqm8540"; #address-cells = <1>; #size-cells = <1>; diff --git a/arch/powerpc/boot/dts/tqm8541.dts b/arch/powerpc/boot/dts/tqm8541.dts index 8fe73ef..8241ae3 100644 --- a/arch/powerpc/boot/dts/tqm8541.dts +++ b/arch/powerpc/boot/dts/tqm8541.dts @@ -12,8 +12,8 @@ /dts-v1/; / { - model = "tqm,8541"; - compatible = "tqm,8541", "tqm,85xx"; + model = "tqc,tqm8541"; + compatible = "tqc,tqm8541"; #address-cells = <1>; #size-cells = <1>; diff --git a/arch/powerpc/boot/dts/tqm8555.dts b/arch/powerpc/boot/dts/tqm8555.dts index 0a53bb9..5a57cef 100644 --- a/arch/powerpc/boot/dts/tqm8555.dts +++ b/arch/powerpc/boot/dts/tqm8555.dts @@ -12,8 +12,8 @@ /dts-v1/; / { - model = "tqm,8555"; - compatible = "tqm,8555", "tqm,85xx"; + model = "tqc,tqm8555"; + compatible = "tqc,tqm8555"; #address-cells = <1>; #size-cells = <1>; diff --git a/arch/powerpc/boot/dts/tqm8560.dts b/arch/powerpc/boot/dts/tqm8560.dts index a4ee596..979058c 100644 --- a/arch/powerpc/boot/dts/tqm8560.dts +++ b/arch/powerpc/boot/dts/tqm8560.dts @@ -12,8 +12,8 @@ /dts-v1/; / { - model = "tqm,8560"; - compatible = "tqm,8560", "tqm,85xx"; + model = "tqc,tqm8560"; + compatible = "tqc,tqm8560"; #address-cells = <1>; #size-cells = <1>; -- cgit v1.1 From 6dd1b64a26d9209c09488e9fa257e7744823bf29 Mon Sep 17 00:00:00 2001 From: Wolfgang Grandegger Date: Fri, 6 Jun 2008 13:50:04 +0200 Subject: powerpc/85xx: add board support for the TQM8548 modules This patch adds support for the TQM8548 modules from TQ-Components GmbH (http://www.tqc.de). Signed-off-by: Wolfgang Grandegger Signed-off-by: Kumar Gala --- arch/powerpc/boot/Makefile | 1 + arch/powerpc/boot/dts/tqm8548.dts | 365 ++++++++++++++++++++++++++++++++++++++ arch/powerpc/boot/wrapper | 2 +- 3 files changed, 367 insertions(+), 1 deletion(-) create mode 100644 arch/powerpc/boot/dts/tqm8548.dts (limited to 'arch/powerpc/boot') diff --git a/arch/powerpc/boot/Makefile b/arch/powerpc/boot/Makefile index e02fe36..25d9fb0 100644 --- a/arch/powerpc/boot/Makefile +++ b/arch/powerpc/boot/Makefile @@ -255,6 +255,7 @@ image-$(CONFIG_MPC85xx_DS) += cuImage.mpc8544ds \ cuImage.mpc8572ds image-$(CONFIG_TQM8540) += cuImage.tqm8540 image-$(CONFIG_TQM8541) += cuImage.tqm8541 +image-$(CONFIG_TQM8548) += cuImage.tqm8548 image-$(CONFIG_TQM8555) += cuImage.tqm8555 image-$(CONFIG_TQM8560) += cuImage.tqm8560 image-$(CONFIG_SBC8548) += cuImage.sbc8548 diff --git a/arch/powerpc/boot/dts/tqm8548.dts b/arch/powerpc/boot/dts/tqm8548.dts new file mode 100644 index 0000000..e80b450 --- /dev/null +++ b/arch/powerpc/boot/dts/tqm8548.dts @@ -0,0 +1,365 @@ +/* + * TQM8548 Device Tree Source + * + * Copyright 2006 Freescale Semiconductor Inc. + * Copyright 2008 Wolfgang Grandegger + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +/dts-v1/; + +/ { + model = "tqc,tqm8548"; + compatible = "tqc,tqm8548"; + #address-cells = <1>; + #size-cells = <1>; + + aliases { + ethernet0 = &enet0; + ethernet1 = &enet1; + ethernet2 = &enet2; + ethernet3 = &enet3; + + serial0 = &serial0; + serial1 = &serial1; + pci0 = &pci0; + pci1 = &pci1; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + PowerPC,8548@0 { + device_type = "cpu"; + reg = <0>; + d-cache-line-size = <32>; // 32 bytes + i-cache-line-size = <32>; // 32 bytes + d-cache-size = <0x8000>; // L1, 32K + i-cache-size = <0x8000>; // L1, 32K + next-level-cache = <&L2>; + }; + }; + + memory { + device_type = "memory"; + reg = <0x00000000 0x00000000>; // Filled in by U-Boot + }; + + soc8548@e0000000 { + #address-cells = <1>; + #size-cells = <1>; + device_type = "soc"; + ranges = <0x0 0xe0000000 0x100000>; + reg = <0xe0000000 0x1000>; // CCSRBAR + bus-frequency = <0>; + + memory-controller@2000 { + compatible = "fsl,mpc8548-memory-controller"; + reg = <0x2000 0x1000>; + interrupt-parent = <&mpic>; + interrupts = <18 2>; + }; + + L2: l2-cache-controller@20000 { + compatible = "fsl,mpc8548-l2-cache-controller"; + reg = <0x20000 0x1000>; + cache-line-size = <32>; // 32 bytes + cache-size = <0x80000>; // L2, 512K + interrupt-parent = <&mpic>; + interrupts = <16 2>; + }; + + i2c@3000 { + #address-cells = <1>; + #size-cells = <0>; + cell-index = <0>; + compatible = "fsl-i2c"; + reg = <0x3000 0x100>; + interrupts = <43 2>; + interrupt-parent = <&mpic>; + dfsrr; + }; + + i2c@3100 { + #address-cells = <1>; + #size-cells = <0>; + cell-index = <1>; + compatible = "fsl-i2c"; + reg = <0x3100 0x100>; + interrupts = <43 2>; + interrupt-parent = <&mpic>; + dfsrr; + }; + + mdio@24520 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,gianfar-mdio"; + reg = <0x24520 0x20>; + + phy1: ethernet-phy@0 { + interrupt-parent = <&mpic>; + interrupts = <8 1>; + reg = <1>; + device_type = "ethernet-phy"; + }; + phy2: ethernet-phy@1 { + interrupt-parent = <&mpic>; + interrupts = <8 1>; + reg = <2>; + device_type = "ethernet-phy"; + }; + phy3: ethernet-phy@3 { + interrupt-parent = <&mpic>; + interrupts = <8 1>; + reg = <3>; + device_type = "ethernet-phy"; + }; + phy4: ethernet-phy@4 { + interrupt-parent = <&mpic>; + interrupts = <8 1>; + reg = <4>; + device_type = "ethernet-phy"; + }; + phy5: ethernet-phy@5 { + interrupt-parent = <&mpic>; + interrupts = <8 1>; + reg = <5>; + device_type = "ethernet-phy"; + }; + }; + + enet0: ethernet@24000 { + cell-index = <0>; + device_type = "network"; + model = "eTSEC"; + compatible = "gianfar"; + reg = <0x24000 0x1000>; + local-mac-address = [ 00 00 00 00 00 00 ]; + interrupts = <29 2 30 2 34 2>; + interrupt-parent = <&mpic>; + phy-handle = <&phy2>; + }; + + enet1: ethernet@25000 { + cell-index = <1>; + device_type = "network"; + model = "eTSEC"; + compatible = "gianfar"; + reg = <0x25000 0x1000>; + local-mac-address = [ 00 00 00 00 00 00 ]; + interrupts = <35 2 36 2 40 2>; + interrupt-parent = <&mpic>; + phy-handle = <&phy1>; + }; + + enet2: ethernet@26000 { + cell-index = <2>; + device_type = "network"; + model = "eTSEC"; + compatible = "gianfar"; + reg = <0x26000 0x1000>; + local-mac-address = [ 00 00 00 00 00 00 ]; + interrupts = <31 2 32 2 33 2>; + interrupt-parent = <&mpic>; + phy-handle = <&phy3>; + }; + + enet3: ethernet@27000 { + cell-index = <3>; + device_type = "network"; + model = "eTSEC"; + compatible = "gianfar"; + reg = <0x27000 0x1000>; + local-mac-address = [ 00 00 00 00 00 00 ]; + interrupts = <37 2 38 2 39 2>; + interrupt-parent = <&mpic>; + phy-handle = <&phy4>; + }; + + serial0: serial@4500 { + cell-index = <0>; + device_type = "serial"; + compatible = "ns16550"; + reg = <0x4500 0x100>; // reg base, size + clock-frequency = <0>; // should we fill in in uboot? + current-speed = <115200>; + interrupts = <42 2>; + interrupt-parent = <&mpic>; + }; + + serial1: serial@4600 { + cell-index = <1>; + device_type = "serial"; + compatible = "ns16550"; + reg = <0x4600 0x100>; // reg base, size + clock-frequency = <0>; // should we fill in in uboot? + current-speed = <115200>; + interrupts = <42 2>; + interrupt-parent = <&mpic>; + }; + + global-utilities@e0000 { // global utilities reg + compatible = "fsl,mpc8548-guts"; + reg = <0xe0000 0x1000>; + fsl,has-rstcr; + }; + + mpic: pic@40000 { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <2>; + reg = <0x40000 0x40000>; + compatible = "chrp,open-pic"; + device_type = "open-pic"; + }; + }; + + localbus@e0005000 { + compatible = "fsl,mpc8548-localbus", "fsl,pq3-localbus", + "simple-bus"; + #address-cells = <2>; + #size-cells = <1>; + reg = <0xe0005000 0x100>; // BRx, ORx, etc. + + ranges = < + 0 0x0 0xfc000000 0x04000000 // NOR FLASH bank 1 + 1 0x0 0xf8000000 0x08000000 // NOR FLASH bank 0 + 2 0x0 0xe3000000 0x00008000 // CAN (2 x i82527) + 3 0x0 0xe3010000 0x00008000 // NAND FLASH + + >; + + flash@1,0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "cfi-flash"; + reg = <1 0x0 0x8000000>; + bank-width = <4>; + device-width = <1>; + + partition@0 { + label = "kernel"; + reg = <0x00000000 0x00200000>; + }; + partition@200000 { + label = "root"; + reg = <0x00200000 0x00300000>; + }; + partition@500000 { + label = "user"; + reg = <0x00500000 0x07a00000>; + }; + partition@7f00000 { + label = "env1"; + reg = <0x07f00000 0x00040000>; + }; + partition@7f40000 { + label = "env2"; + reg = <0x07f40000 0x00040000>; + }; + partition@7f80000 { + label = "u-boot"; + reg = <0x07f80000 0x00080000>; + read-only; + }; + }; + + /* Note: CAN support needs be enabled in U-Boot */ + can0@2,0 { + compatible = "intel,82527"; // Bosch CC770 + reg = <2 0x0 0x100>; + interrupts = <4 0>; + interrupt-parent = <&mpic>; + }; + + can1@2,100 { + compatible = "intel,82527"; // Bosch CC770 + reg = <2 0x100 0x100>; + interrupts = <4 0>; + interrupt-parent = <&mpic>; + }; + + /* Note: NAND support needs to be enabled in U-Boot */ + upm@3,0 { + #address-cells = <0>; + #size-cells = <0>; + compatible = "fsl,upm-nand"; + reg = <3 0x0 0x800>; + fsl,upm-addr-offset = <0x10>; + fsl,upm-cmd-offset = <0x08>; + chip-delay = <25>; // in micro-seconds + + nand@0 { + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "fs"; + reg = <0x00000000 0x01000000>; + }; + }; + }; + }; + + pci0: pci@e0008000 { + cell-index = <0>; + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci"; + device_type = "pci"; + reg = <0xe0008000 0x1000>; + clock-frequency = <33333333>; + interrupt-map-mask = <0xf800 0x0 0x0 0x7>; + interrupt-map = < + /* IDSEL 28 */ + 0xe000 0 0 1 &mpic 2 1 + 0xe000 0 0 2 &mpic 3 1>; + + interrupt-parent = <&mpic>; + interrupts = <24 2>; + bus-range = <0 0>; + ranges = <0x02000000 0 0x80000000 0x80000000 0 0x20000000 + 0x01000000 0 0x00000000 0xe2000000 0 0x01000000>; + }; + + pci1: pcie@e000a000 { + cell-index = <2>; + interrupt-map-mask = <0xf800 0x0 0x0 0x7>; + interrupt-map = < + /* IDSEL 0x0 (PEX) */ + 0x00000 0 0 1 &mpic 0 1 + 0x00000 0 0 2 &mpic 1 1 + 0x00000 0 0 3 &mpic 2 1 + 0x00000 0 0 4 &mpic 3 1>; + + interrupt-parent = <&mpic>; + interrupts = <26 2>; + bus-range = <0 0xff>; + ranges = <0x02000000 0 0xc0000000 0xc0000000 0 0x20000000 + 0x01000000 0 0x00000000 0xef000000 0 0x08000000>; + clock-frequency = <33333333>; + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + reg = <0xe000a000 0x1000>; + compatible = "fsl,mpc8548-pcie"; + device_type = "pci"; + pcie@0 { + reg = <0 0 0 0 0>; + #size-cells = <2>; + #address-cells = <3>; + device_type = "pci"; + ranges = <0x02000000 0 0xc0000000 0x02000000 0 + 0xc0000000 0 0x20000000 + 0x01000000 0 0x00000000 0x01000000 0 + 0x00000000 0 0x08000000>; + }; + }; +}; diff --git a/arch/powerpc/boot/wrapper b/arch/powerpc/boot/wrapper index 4832be8..cb87a01 100755 --- a/arch/powerpc/boot/wrapper +++ b/arch/powerpc/boot/wrapper @@ -177,7 +177,7 @@ cuboot*) *-tqm8541|*-mpc8560*|*-tqm8560|*-tqm8555|*-ksi8560*) platformo=$object/cuboot-85xx-cpm2.o ;; - *-mpc85*|*-tqm8540|*-sbc85*) + *-mpc85*|*-tqm85*|*-sbc85*) platformo=$object/cuboot-85xx.o ;; esac -- cgit v1.1 From 02b8a3d1eb2ae6353cfbce627ded22e299cf1989 Mon Sep 17 00:00:00 2001 From: Wolfgang Grandegger Date: Fri, 6 Jun 2008 13:50:05 +0200 Subject: powerpc/85xx: support for the TQM8548 module using the big Flash Some TQM85xx boards could be equipped with up to 1 GiB (NOR) flash memory and therefore a modified memory map is required and setup by the board loader. This patch adds an appropriate DTS file. Signed-off-by: Wolfgang Grandegger Signed-off-by: Kumar Gala --- arch/powerpc/boot/dts/tqm8548-bigflash.dts | 365 +++++++++++++++++++++++++++++ 1 file changed, 365 insertions(+) create mode 100644 arch/powerpc/boot/dts/tqm8548-bigflash.dts (limited to 'arch/powerpc/boot') diff --git a/arch/powerpc/boot/dts/tqm8548-bigflash.dts b/arch/powerpc/boot/dts/tqm8548-bigflash.dts new file mode 100644 index 0000000..d8a1b19 --- /dev/null +++ b/arch/powerpc/boot/dts/tqm8548-bigflash.dts @@ -0,0 +1,365 @@ +/* + * TQM8548 Device Tree Source + * + * Copyright 2006 Freescale Semiconductor Inc. + * Copyright 2008 Wolfgang Grandegger + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +/dts-v1/; + +/ { + model = "tqc,tqm8548"; + compatible = "tqc,tqm8548"; + #address-cells = <1>; + #size-cells = <1>; + + aliases { + ethernet0 = &enet0; + ethernet1 = &enet1; + ethernet2 = &enet2; + ethernet3 = &enet3; + + serial0 = &serial0; + serial1 = &serial1; + pci0 = &pci0; + pci1 = &pci1; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + PowerPC,8548@0 { + device_type = "cpu"; + reg = <0>; + d-cache-line-size = <32>; // 32 bytes + i-cache-line-size = <32>; // 32 bytes + d-cache-size = <0x8000>; // L1, 32K + i-cache-size = <0x8000>; // L1, 32K + next-level-cache = <&L2>; + }; + }; + + memory { + device_type = "memory"; + reg = <0x00000000 0x00000000>; // Filled in by U-Boot + }; + + soc8548@a0000000 { + #address-cells = <1>; + #size-cells = <1>; + device_type = "soc"; + ranges = <0x0 0xa0000000 0x100000>; + reg = <0xa0000000 0x1000>; // CCSRBAR + bus-frequency = <0>; + + memory-controller@2000 { + compatible = "fsl,mpc8548-memory-controller"; + reg = <0x2000 0x1000>; + interrupt-parent = <&mpic>; + interrupts = <18 2>; + }; + + L2: l2-cache-controller@20000 { + compatible = "fsl,mpc8548-l2-cache-controller"; + reg = <0x20000 0x1000>; + cache-line-size = <32>; // 32 bytes + cache-size = <0x80000>; // L2, 512K + interrupt-parent = <&mpic>; + interrupts = <16 2>; + }; + + i2c@3000 { + #address-cells = <1>; + #size-cells = <0>; + cell-index = <0>; + compatible = "fsl-i2c"; + reg = <0x3000 0x100>; + interrupts = <43 2>; + interrupt-parent = <&mpic>; + dfsrr; + }; + + i2c@3100 { + #address-cells = <1>; + #size-cells = <0>; + cell-index = <1>; + compatible = "fsl-i2c"; + reg = <0x3100 0x100>; + interrupts = <43 2>; + interrupt-parent = <&mpic>; + dfsrr; + }; + + mdio@24520 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,gianfar-mdio"; + reg = <0x24520 0x20>; + + phy1: ethernet-phy@0 { + interrupt-parent = <&mpic>; + interrupts = <8 1>; + reg = <1>; + device_type = "ethernet-phy"; + }; + phy2: ethernet-phy@1 { + interrupt-parent = <&mpic>; + interrupts = <8 1>; + reg = <2>; + device_type = "ethernet-phy"; + }; + phy3: ethernet-phy@3 { + interrupt-parent = <&mpic>; + interrupts = <8 1>; + reg = <3>; + device_type = "ethernet-phy"; + }; + phy4: ethernet-phy@4 { + interrupt-parent = <&mpic>; + interrupts = <8 1>; + reg = <4>; + device_type = "ethernet-phy"; + }; + phy5: ethernet-phy@5 { + interrupt-parent = <&mpic>; + interrupts = <8 1>; + reg = <5>; + device_type = "ethernet-phy"; + }; + }; + + enet0: ethernet@24000 { + cell-index = <0>; + device_type = "network"; + model = "eTSEC"; + compatible = "gianfar"; + reg = <0x24000 0x1000>; + local-mac-address = [ 00 00 00 00 00 00 ]; + interrupts = <29 2 30 2 34 2>; + interrupt-parent = <&mpic>; + phy-handle = <&phy2>; + }; + + enet1: ethernet@25000 { + cell-index = <1>; + device_type = "network"; + model = "eTSEC"; + compatible = "gianfar"; + reg = <0x25000 0x1000>; + local-mac-address = [ 00 00 00 00 00 00 ]; + interrupts = <35 2 36 2 40 2>; + interrupt-parent = <&mpic>; + phy-handle = <&phy1>; + }; + + enet2: ethernet@26000 { + cell-index = <2>; + device_type = "network"; + model = "eTSEC"; + compatible = "gianfar"; + reg = <0x26000 0x1000>; + local-mac-address = [ 00 00 00 00 00 00 ]; + interrupts = <31 2 32 2 33 2>; + interrupt-parent = <&mpic>; + phy-handle = <&phy3>; + }; + + enet3: ethernet@27000 { + cell-index = <3>; + device_type = "network"; + model = "eTSEC"; + compatible = "gianfar"; + reg = <0x27000 0x1000>; + local-mac-address = [ 00 00 00 00 00 00 ]; + interrupts = <37 2 38 2 39 2>; + interrupt-parent = <&mpic>; + phy-handle = <&phy4>; + }; + + serial0: serial@4500 { + cell-index = <0>; + device_type = "serial"; + compatible = "ns16550"; + reg = <0x4500 0x100>; // reg base, size + clock-frequency = <0>; // should we fill in in uboot? + current-speed = <115200>; + interrupts = <42 2>; + interrupt-parent = <&mpic>; + }; + + serial1: serial@4600 { + cell-index = <1>; + device_type = "serial"; + compatible = "ns16550"; + reg = <0x4600 0x100>; // reg base, size + clock-frequency = <0>; // should we fill in in uboot? + current-speed = <115200>; + interrupts = <42 2>; + interrupt-parent = <&mpic>; + }; + + global-utilities@e0000 { // global utilities reg + compatible = "fsl,mpc8548-guts"; + reg = <0xe0000 0x1000>; + fsl,has-rstcr; + }; + + mpic: pic@40000 { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <2>; + reg = <0x40000 0x40000>; + compatible = "chrp,open-pic"; + device_type = "open-pic"; + }; + }; + + localbus@a0005000 { + compatible = "fsl,mpc8548-localbus", "fsl,pq3-localbus", + "simple-bus"; + #address-cells = <2>; + #size-cells = <1>; + reg = <0xa0005000 0x100>; // BRx, ORx, etc. + + ranges = < + 0 0x0 0xfc000000 0x04000000 // NOR FLASH bank 1 + 1 0x0 0xf8000000 0x08000000 // NOR FLASH bank 0 + 2 0x0 0xa3000000 0x00008000 // CAN (2 x i82527) + 3 0x0 0xa3010000 0x00008000 // NAND FLASH + + >; + + flash@1,0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "cfi-flash"; + reg = <1 0x0 0x8000000>; + bank-width = <4>; + device-width = <1>; + + partition@0 { + label = "kernel"; + reg = <0x00000000 0x00200000>; + }; + partition@200000 { + label = "root"; + reg = <0x00200000 0x00300000>; + }; + partition@500000 { + label = "user"; + reg = <0x00500000 0x07a00000>; + }; + partition@7f00000 { + label = "env1"; + reg = <0x07f00000 0x00040000>; + }; + partition@7f40000 { + label = "env2"; + reg = <0x07f40000 0x00040000>; + }; + partition@7f80000 { + label = "u-boot"; + reg = <0x07f80000 0x00080000>; + read-only; + }; + }; + + /* Note: CAN support needs be enabled in U-Boot */ + can0@2,0 { + compatible = "intel,82527"; // Bosch CC770 + reg = <2 0x0 0x100>; + interrupts = <4 0>; + interrupt-parent = <&mpic>; + }; + + can1@2,100 { + compatible = "intel,82527"; // Bosch CC770 + reg = <2 0x100 0x100>; + interrupts = <4 0>; + interrupt-parent = <&mpic>; + }; + + /* Note: NAND support needs to be enabled in U-Boot */ + upm@3,0 { + #address-cells = <0>; + #size-cells = <0>; + compatible = "fsl,upm-nand"; + reg = <3 0x0 0x800>; + fsl,upm-addr-offset = <0x10>; + fsl,upm-cmd-offset = <0x08>; + chip-delay = <25>; // in micro-seconds + + nand@0 { + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "fs"; + reg = <0x00000000 0x01000000>; + }; + }; + }; + }; + + pci0: pci@a0008000 { + cell-index = <0>; + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci"; + device_type = "pci"; + reg = <0xa0008000 0x1000>; + clock-frequency = <33333333>; + interrupt-map-mask = <0xf800 0x0 0x0 0x7>; + interrupt-map = < + /* IDSEL 28 */ + 0xe000 0 0 1 &mpic 2 1 + 0xe000 0 0 2 &mpic 3 1>; + + interrupt-parent = <&mpic>; + interrupts = <24 2>; + bus-range = <0 0>; + ranges = <0x02000000 0 0x80000000 0x80000000 0 0x20000000 + 0x01000000 0 0x00000000 0xa2000000 0 0x01000000>; + }; + + pci1: pcie@a000a000 { + cell-index = <2>; + interrupt-map-mask = <0xf800 0x0 0x0 0x7>; + interrupt-map = < + /* IDSEL 0x0 (PEX) */ + 0x00000 0 0 1 &mpic 0 1 + 0x00000 0 0 2 &mpic 1 1 + 0x00000 0 0 3 &mpic 2 1 + 0x00000 0 0 4 &mpic 3 1>; + + interrupt-parent = <&mpic>; + interrupts = <26 2>; + bus-range = <0 0xff>; + ranges = <0x02000000 0 0xb0000000 0xb0000000 0 0x10000000 + 0x01000000 0 0x00000000 0xaf000000 0 0x08000000>; + clock-frequency = <33333333>; + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + reg = <0xa000a000 0x1000>; + compatible = "fsl,mpc8548-pcie"; + device_type = "pci"; + pcie@0 { + reg = <0 0 0 0 0>; + #size-cells = <2>; + #address-cells = <3>; + device_type = "pci"; + ranges = <0x02000000 0 0xb0000000 0x02000000 0 + 0xb0000000 0 0x10000000 + 0x01000000 0 0x00000000 0x01000000 0 + 0x00000000 0 0x08000000>; + }; + }; +}; -- cgit v1.1 From 5399be7f4679251e8c4c6637fde240f7ac8efdb9 Mon Sep 17 00:00:00 2001 From: Wolfgang Grandegger Date: Fri, 6 Jun 2008 13:50:06 +0200 Subject: powerpc/85xx: add local bus nodes for Flash and CAN to tqm8560.dts This patch adds local bus nodes for Flash and CAN to the DTS file of the TQM8560 module (tqm8560.dts). Signed-off-by: Wolfgang Grandegger Signed-off-by: Kumar Gala --- arch/powerpc/boot/dts/tqm8560.dts | 65 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 65 insertions(+) (limited to 'arch/powerpc/boot') diff --git a/arch/powerpc/boot/dts/tqm8560.dts b/arch/powerpc/boot/dts/tqm8560.dts index 979058c..6794882 100644 --- a/arch/powerpc/boot/dts/tqm8560.dts +++ b/arch/powerpc/boot/dts/tqm8560.dts @@ -2,6 +2,7 @@ * TQM 8560 Device Tree Source * * Copyright 2008 Freescale Semiconductor Inc. + * Copyright 2008 Wolfgang Grandegger * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License as published by the @@ -223,6 +224,70 @@ }; }; + localbus@e0005000 { + compatible = "fsl,mpc8560-localbus", "fsl,pq3-localbus", + "simple-bus"; + #address-cells = <2>; + #size-cells = <1>; + reg = <0xe0005000 0x100>; // BRx, ORx, etc. + + ranges = < + 0 0x0 0xfc000000 0x04000000 // NOR FLASH bank 1 + 1 0x0 0xf8000000 0x08000000 // NOR FLASH bank 0 + 2 0x0 0xe3000000 0x00008000 // CAN (2 x i82527) + >; + + flash@1,0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "cfi-flash"; + reg = <1 0x0 0x8000000>; + bank-width = <4>; + device-width = <1>; + + partition@0 { + label = "kernel"; + reg = <0x00000000 0x00200000>; + }; + partition@200000 { + label = "root"; + reg = <0x00200000 0x00300000>; + }; + partition@500000 { + label = "user"; + reg = <0x00500000 0x07a00000>; + }; + partition@7f00000 { + label = "env1"; + reg = <0x07f00000 0x00040000>; + }; + partition@7f40000 { + label = "env2"; + reg = <0x07f40000 0x00040000>; + }; + partition@7f80000 { + label = "u-boot"; + reg = <0x07f80000 0x00080000>; + read-only; + }; + }; + + /* Note: CAN support needs be enabled in U-Boot */ + can0@2,0 { + compatible = "intel,82527"; // Bosch CC770 + reg = <2 0x0 0x100>; + interrupts = <4 0>; + interrupt-parent = <&mpic>; + }; + + can1@2,100 { + compatible = "intel,82527"; // Bosch CC770 + reg = <2 0x100 0x100>; + interrupts = <4 0>; + interrupt-parent = <&mpic>; + }; + }; + pci0: pci@e0008000 { cell-index = <0>; #interrupt-cells = <1>; -- cgit v1.1 From b13e930906b313d787f4dd07fe78b74a3a8c22c4 Mon Sep 17 00:00:00 2001 From: Anton Vorontsov Date: Fri, 23 May 2008 20:39:01 +0400 Subject: powerpc/83xx: new board support: MPC8360E-RDK This is patch adds board file, device tree, and defconfig for the new board, made by Freescale Semiconductor Inc. and Logic Product Development. Currently supported: 1. UEC{1,2,7,4}; 2. I2C; 3. SPI; 4. NS16550 serial; 5. PCI and miniPCI; 6. Intel NOR StrataFlash X16 64Mbit PC28F640P30T85; 7. Graphics controller, Fujitsu MB86277. Not supported in this patch: 1. StMICRO NAND512W3A2BN6E, 512 Mbit (supported with FSL UPM NAND driver); 2. FHCI USB (supported with FHCI driver). 3. QE Serial UCCs (tested to not work with ucc_uart driver, reason unknown, yet); 4. ADC AD7843 (tested to work, but support via device tree depends on major SPI rework, GPIO API, etc); Signed-off-by: Anton Vorontsov Signed-off-by: Kumar Gala --- arch/powerpc/boot/dts/mpc836x_rdk.dts | 397 ++++++++++++++++++++++++++++++++++ 1 file changed, 397 insertions(+) create mode 100644 arch/powerpc/boot/dts/mpc836x_rdk.dts (limited to 'arch/powerpc/boot') diff --git a/arch/powerpc/boot/dts/mpc836x_rdk.dts b/arch/powerpc/boot/dts/mpc836x_rdk.dts new file mode 100644 index 0000000..3402d26 --- /dev/null +++ b/arch/powerpc/boot/dts/mpc836x_rdk.dts @@ -0,0 +1,397 @@ +/* + * MPC8360E RDK Device Tree Source + * + * Copyright 2006 Freescale Semiconductor Inc. + * Copyright 2007-2008 MontaVista Software, Inc. + * + * Author: Anton Vorontsov + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +/dts-v1/; + +/ { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,mpc8360rdk"; + + aliases { + serial0 = &serial0; + serial1 = &serial1; + serial2 = &serial2; + serial3 = &serial3; + ethernet0 = &enet0; + ethernet1 = &enet1; + ethernet2 = &enet2; + ethernet3 = &enet3; + pci0 = &pci0; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + PowerPC,8360@0 { + device_type = "cpu"; + reg = <0>; + d-cache-line-size = <32>; + i-cache-line-size = <32>; + d-cache-size = <32768>; + i-cache-size = <32768>; + /* filled by u-boot */ + timebase-frequency = <0>; + bus-frequency = <0>; + clock-frequency = <0>; + }; + }; + + memory { + device_type = "memory"; + /* filled by u-boot */ + reg = <0 0>; + }; + + soc@e0000000 { + #address-cells = <1>; + #size-cells = <1>; + device_type = "soc"; + compatible = "fsl,mpc8360-immr", "fsl,immr", "fsl,soc", + "simple-bus"; + ranges = <0 0xe0000000 0x200000>; + reg = <0xe0000000 0x200>; + /* filled by u-boot */ + bus-frequency = <0>; + + wdt@200 { + compatible = "mpc83xx_wdt"; + reg = <0x200 0x100>; + }; + + i2c@3000 { + #address-cells = <1>; + #size-cells = <0>; + cell-index = <0>; + compatible = "fsl-i2c"; + reg = <0x3000 0x100>; + interrupts = <14 8>; + interrupt-parent = <&ipic>; + dfsrr; + }; + + i2c@3100 { + #address-cells = <1>; + #size-cells = <0>; + cell-index = <1>; + compatible = "fsl-i2c"; + reg = <0x3100 0x100>; + interrupts = <16 8>; + interrupt-parent = <&ipic>; + dfsrr; + }; + + serial0: serial@4500 { + device_type = "serial"; + compatible = "ns16550"; + reg = <0x4500 0x100>; + interrupts = <9 8>; + interrupt-parent = <&ipic>; + /* filled by u-boot */ + clock-frequency = <0>; + }; + + serial1: serial@4600 { + device_type = "serial"; + compatible = "ns16550"; + reg = <0x4600 0x100>; + interrupts = <10 8>; + interrupt-parent = <&ipic>; + /* filled by u-boot */ + clock-frequency = <0>; + }; + + crypto@30000 { + compatible = "fsl,sec2-crypto"; + reg = <0x30000 0x10000>; + interrupts = <11 8>; + interrupt-parent = <&ipic>; + num-channels = <4>; + channel-fifo-len = <24>; + exec-units-mask = <0x7e>; + /* + * desc mask is for rev1.x, we need runtime fixup + * for >=2.x + */ + descriptor-types-mask = <0x1010ebf>; + }; + + ipic: interrupt-controller@700 { + #address-cells = <0>; + #interrupt-cells = <2>; + compatible = "fsl,pq2pro-pic", "fsl,ipic"; + interrupt-controller; + reg = <0x700 0x100>; + }; + + qe_pio_b: gpio-controller@1418 { + #gpio-cells = <2>; + compatible = "fsl,mpc8360-qe-pario-bank", + "fsl,mpc8323-qe-pario-bank"; + reg = <0x1418 0x18>; + gpio-controller; + }; + + qe_pio_e: gpio-controller@1460 { + #gpio-cells = <2>; + compatible = "fsl,mpc8360-qe-pario-bank", + "fsl,mpc8323-qe-pario-bank"; + reg = <0x1460 0x18>; + gpio-controller; + }; + + qe@100000 { + #address-cells = <1>; + #size-cells = <1>; + device_type = "qe"; + compatible = "fsl,qe", "simple-bus"; + ranges = <0 0x100000 0x100000>; + reg = <0x100000 0x480>; + /* filled by u-boot */ + clock-frequency = <0>; + bus-frequency = <0>; + brg-frequency = <0>; + + muram@10000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,qe-muram", "fsl,cpm-muram"; + ranges = <0 0x10000 0xc000>; + + data-only@0 { + compatible = "fsl,qe-muram-data", + "fsl,cpm-muram-data"; + reg = <0 0xc000>; + }; + }; + + timer@440 { + compatible = "fsl,mpc8360-qe-gtm", + "fsl,qe-gtm", "fsl,gtm"; + reg = <0x440 0x40>; + interrupts = <12 13 14 15>; + interrupt-parent = <&qeic>; + /* filled by u-boot */ + clock-frequency = <0>; + }; + + spi@4c0 { + cell-index = <0>; + compatible = "fsl,spi"; + reg = <0x4c0 0x40>; + interrupts = <2>; + interrupt-parent = <&qeic>; + mode = "cpu-qe"; + }; + + spi@500 { + cell-index = <1>; + compatible = "fsl,spi"; + reg = <0x500 0x40>; + interrupts = <1>; + interrupt-parent = <&qeic>; + mode = "cpu-qe"; + }; + + enet0: ucc@2000 { + device_type = "network"; + compatible = "ucc_geth"; + cell-index = <1>; + reg = <0x2000 0x200>; + interrupts = <32>; + interrupt-parent = <&qeic>; + rx-clock-name = "none"; + tx-clock-name = "clk9"; + phy-handle = <&phy2>; + phy-connection-type = "rgmii-rxid"; + /* filled by u-boot */ + local-mac-address = [ 00 00 00 00 00 00 ]; + }; + + enet1: ucc@3000 { + device_type = "network"; + compatible = "ucc_geth"; + cell-index = <2>; + reg = <0x3000 0x200>; + interrupts = <33>; + interrupt-parent = <&qeic>; + rx-clock-name = "none"; + tx-clock-name = "clk4"; + phy-handle = <&phy4>; + phy-connection-type = "rgmii-rxid"; + /* filled by u-boot */ + local-mac-address = [ 00 00 00 00 00 00 ]; + }; + + enet2: ucc@2600 { + device_type = "network"; + compatible = "ucc_geth"; + cell-index = <7>; + reg = <0x2600 0x200>; + interrupts = <42>; + interrupt-parent = <&qeic>; + rx-clock-name = "clk20"; + tx-clock-name = "clk19"; + phy-handle = <&phy1>; + phy-connection-type = "mii"; + /* filled by u-boot */ + local-mac-address = [ 00 00 00 00 00 00 ]; + }; + + enet3: ucc@3200 { + device_type = "network"; + compatible = "ucc_geth"; + cell-index = <4>; + reg = <0x3200 0x200>; + interrupts = <35>; + interrupt-parent = <&qeic>; + rx-clock-name = "clk8"; + tx-clock-name = "clk7"; + phy-handle = <&phy3>; + phy-connection-type = "mii"; + /* filled by u-boot */ + local-mac-address = [ 00 00 00 00 00 00 ]; + }; + + mdio@2120 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,ucc-mdio"; + reg = <0x2120 0x18>; + + phy1: ethernet-phy@1 { + device_type = "ethernet-phy"; + compatible = "national,DP83848VV"; + reg = <1>; + }; + + phy2: ethernet-phy@2 { + device_type = "ethernet-phy"; + compatible = "broadcom,BCM5481UA2KMLG"; + reg = <2>; + }; + + phy3: ethernet-phy@3 { + device_type = "ethernet-phy"; + compatible = "national,DP83848VV"; + reg = <3>; + }; + + phy4: ethernet-phy@4 { + device_type = "ethernet-phy"; + compatible = "broadcom,BCM5481UA2KMLG"; + reg = <4>; + }; + }; + + serial2: ucc@2400 { + device_type = "serial"; + compatible = "ucc_uart"; + reg = <0x2400 0x200>; + cell-index = <5>; + port-number = <0>; + rx-clock-name = "brg7"; + tx-clock-name = "brg8"; + interrupts = <40>; + interrupt-parent = <&qeic>; + soft-uart; + }; + + serial3: ucc@3400 { + device_type = "serial"; + compatible = "ucc_uart"; + reg = <0x3400 0x200>; + cell-index = <6>; + port-number = <1>; + rx-clock-name = "brg13"; + tx-clock-name = "brg14"; + interrupts = <41>; + interrupt-parent = <&qeic>; + soft-uart; + }; + + qeic: interrupt-controller@80 { + #address-cells = <0>; + #interrupt-cells = <1>; + compatible = "fsl,qe-ic"; + interrupt-controller; + reg = <0x80 0x80>; + big-endian; + interrupts = <32 8 33 8>; + interrupt-parent = <&ipic>; + }; + }; + }; + + localbus@e0005000 { + #address-cells = <2>; + #size-cells = <1>; + compatible = "fsl,mpc8360-localbus", "fsl,pq2pro-localbus", + "simple-bus"; + reg = <0xe0005000 0xd8>; + ranges = <0 0 0xff800000 0x0800000 + 1 0 0x60000000 0x0001000 + 2 0 0x70000000 0x4000000>; + + flash@0,0 { + compatible = "intel,PC28F640P30T85", "cfi-flash"; + reg = <0 0 0x800000>; + bank-width = <2>; + device-width = <1>; + }; + + display@2,0 { + device_type = "display"; + compatible = "fujitsu,MB86277", "fujitsu,mint"; + reg = <2 0 0x4000000>; + fujitsu,sh3; + little-endian; + /* filled by u-boot */ + address = <0>; + depth = <0>; + width = <0>; + height = <0>; + linebytes = <0>; + /* linux,opened; - added by uboot */ + }; + }; + + pci0: pci@e0008500 { + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + device_type = "pci"; + compatible = "fsl,mpc8360-pci", "fsl,mpc8349-pci"; + reg = <0xe0008500 0x100>; + ranges = <0x02000000 0 0x90000000 0x90000000 0 0x10000000 + 0x42000000 0 0x80000000 0x80000000 0 0x10000000 + 0x01000000 0 0xe0300000 0xe0300000 0 0x00100000>; + interrupts = <66 8>; + interrupt-parent = <&ipic>; + interrupt-map-mask = <0xf800 0 0 7>; + interrupt-map = ; + /* filled by u-boot */ + bus-range = <0 0>; + clock-frequency = <0>; + }; +}; -- cgit v1.1 From 887942d7d62499999f7868f194d7f41fd6e88795 Mon Sep 17 00:00:00 2001 From: Imre Kaloz Date: Wed, 11 Jun 2008 08:03:41 -0400 Subject: powerpc/4xx: MTD support for the AMCC Taishan Board Add support for the NOR flash found on the AMCC Taishan Board and enable MTD support in the defconfig. Signed-off-by: Imre Kaloz Acked-by: Stefan Roese Signed-off-by: Josh Boyer --- arch/powerpc/boot/dts/taishan.dts | 29 ++++++++++++++++++++++++++++- 1 file changed, 28 insertions(+), 1 deletion(-) (limited to 'arch/powerpc/boot') diff --git a/arch/powerpc/boot/dts/taishan.dts b/arch/powerpc/boot/dts/taishan.dts index dcb7498..d4867de 100644 --- a/arch/powerpc/boot/dts/taishan.dts +++ b/arch/powerpc/boot/dts/taishan.dts @@ -186,7 +186,34 @@ interrupts = <0x5 0x4>; interrupt-parent = <&UIC1>; - /* TODO: Add other EBC devices */ + nor_flash@0,0 { + compatible = "cfi-flash"; + bank-width = <4>; + device-width = <2>; + reg = <0x0 0x0 0x4000000>; + #address-cells = <1>; + #size-cells = <1>; + partition@0 { + label = "kernel"; + reg = <0x0 0x180000>; + }; + partition@180000 { + label = "root"; + reg = <0x180000 0x200000>; + }; + partition@380000 { + label = "user"; + reg = <0x380000 0x3bc0000>; + }; + partition@3f40000 { + label = "env"; + reg = <0x3f40000 0x80000>; + }; + partition@3fc0000 { + label = "u-boot"; + reg = <0x3fc0000 0x40000>; + }; + }; }; -- cgit v1.1 From b6014e15bc38a33cf9591d33674dd870027cb623 Mon Sep 17 00:00:00 2001 From: Giuseppe Coviello Date: Tue, 20 May 2008 01:20:47 +1000 Subject: powerpc/4xx: Sam440ep support The Sam440ep is an high customizable general purpose mini-itx board, based on the AMCC 440EP and with a LatticeXP FPGA onboard. It's poduced by ACube Systems Srl (Bassano del Grappa, Italy), http://www.acube-systems.biz. Signed-off-by: Giuseppe Coviello Signed-off-by: Josh Boyer --- arch/powerpc/boot/Makefile | 3 +- arch/powerpc/boot/cuboot-sam440ep.c | 49 ++++++ arch/powerpc/boot/dts/sam440ep.dts | 292 ++++++++++++++++++++++++++++++++++++ 3 files changed, 343 insertions(+), 1 deletion(-) create mode 100644 arch/powerpc/boot/cuboot-sam440ep.c create mode 100644 arch/powerpc/boot/dts/sam440ep.dts (limited to 'arch/powerpc/boot') diff --git a/arch/powerpc/boot/Makefile b/arch/powerpc/boot/Makefile index e02fe36..e98841d 100644 --- a/arch/powerpc/boot/Makefile +++ b/arch/powerpc/boot/Makefile @@ -66,7 +66,7 @@ src-plat := of.c cuboot-52xx.c cuboot-824x.c cuboot-83xx.c cuboot-85xx.c holly.c fixed-head.S ep88xc.c ep405.c cuboot-c2k.c \ cuboot-katmai.c cuboot-rainier.c redboot-8xx.c ep8248e.c \ cuboot-warp.c cuboot-85xx-cpm2.c cuboot-yosemite.c simpleboot.c \ - virtex405-head.S redboot-83xx.c + virtex405-head.S redboot-83xx.c cuboot-sam440ep.c src-boot := $(src-wlib) $(src-plat) empty.c src-boot := $(addprefix $(obj)/, $(src-boot)) @@ -213,6 +213,7 @@ image-$(CONFIG_WALNUT) += treeImage.walnut # Board ports in arch/powerpc/platform/44x/Kconfig image-$(CONFIG_EBONY) += treeImage.ebony cuImage.ebony image-$(CONFIG_BAMBOO) += treeImage.bamboo cuImage.bamboo +image-$(CONFIG_SAM440EP) += cuImage.sam440ep image-$(CONFIG_SEQUOIA) += cuImage.sequoia image-$(CONFIG_RAINIER) += cuImage.rainier image-$(CONFIG_TAISHAN) += cuImage.taishan diff --git a/arch/powerpc/boot/cuboot-sam440ep.c b/arch/powerpc/boot/cuboot-sam440ep.c new file mode 100644 index 0000000..ec10a47 --- /dev/null +++ b/arch/powerpc/boot/cuboot-sam440ep.c @@ -0,0 +1,49 @@ +/* + * Old U-boot compatibility for Sam440ep based off bamboo.c code + * original copyrights below + * + * Author: Josh Boyer + * + * Copyright 2007 IBM Corporation + * + * Based on cuboot-ebony.c + * + * Modified from cuboot-bamboo.c for sam440ep: + * Copyright 2008 Giuseppe Coviello + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include "ops.h" +#include "stdio.h" +#include "44x.h" +#include "4xx.h" +#include "cuboot.h" + +#define TARGET_4xx +#define TARGET_44x +#include "ppcboot.h" + +static bd_t bd; + +static void sam440ep_fixups(void) +{ + unsigned long sysclk = 66666666; + + ibm440ep_fixup_clocks(sysclk, 11059200, 25000000); + ibm4xx_sdram_fixup_memsize(); + ibm4xx_quiesce_eth((u32 *)0xef600e00, (u32 *)0xef600f00); + dt_fixup_mac_addresses(&bd.bi_enetaddr, &bd.bi_enet1addr); +} + +void platform_init(unsigned long r3, unsigned long r4, unsigned long r5, + unsigned long r6, unsigned long r7) +{ + CUBOOT_INIT(); + platform_ops.fixups = sam440ep_fixups; + platform_ops.exit = ibm44x_dbcr_reset; + fdt_init(_dtb_start); + serial_console_init(); +} diff --git a/arch/powerpc/boot/dts/sam440ep.dts b/arch/powerpc/boot/dts/sam440ep.dts new file mode 100644 index 0000000..b0984d5 --- /dev/null +++ b/arch/powerpc/boot/dts/sam440ep.dts @@ -0,0 +1,292 @@ +/* + * Device Tree Source for ACube Sam440ep based off bamboo.dts code + * original copyrights below + * + * Copyright (c) 2006, 2007 IBM Corp. + * Josh Boyer + * + * Modified from bamboo.dts for sam440ep: + * Copyright 2008 Giuseppe Coviello + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without + * any warranty of any kind, whether express or implied. + */ + +/ { + #address-cells = <2>; + #size-cells = <1>; + model = "acube,sam440ep"; + compatible = "acube,sam440ep"; + dcr-parent = <&/cpus/cpu@0>; + + aliases { + ethernet0 = &EMAC0; + ethernet1 = &EMAC1; + serial0 = &UART0; + serial1 = &UART1; + serial2 = &UART2; + serial3 = &UART3; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + model = "PowerPC,440EP"; + reg = <0>; + clock-frequency = <0>; /* Filled in by zImage */ + timebase-frequency = <0>; /* Filled in by zImage */ + i-cache-line-size = <20>; + d-cache-line-size = <20>; + i-cache-size = <8000>; + d-cache-size = <8000>; + dcr-controller; + dcr-access-method = "native"; + }; + }; + + memory { + device_type = "memory"; + reg = <0 0 0>; /* Filled in by zImage */ + }; + + UIC0: interrupt-controller0 { + compatible = "ibm,uic-440ep","ibm,uic"; + interrupt-controller; + cell-index = <0>; + dcr-reg = <0c0 009>; + #address-cells = <0>; + #size-cells = <0>; + #interrupt-cells = <2>; + }; + + UIC1: interrupt-controller1 { + compatible = "ibm,uic-440ep","ibm,uic"; + interrupt-controller; + cell-index = <1>; + dcr-reg = <0d0 009>; + #address-cells = <0>; + #size-cells = <0>; + #interrupt-cells = <2>; + interrupts = <1e 4 1f 4>; /* cascade */ + interrupt-parent = <&UIC0>; + }; + + SDR0: sdr { + compatible = "ibm,sdr-440ep"; + dcr-reg = <00e 002>; + }; + + CPR0: cpr { + compatible = "ibm,cpr-440ep"; + dcr-reg = <00c 002>; + }; + + plb { + compatible = "ibm,plb-440ep", "ibm,plb-440gp", "ibm,plb4"; + #address-cells = <2>; + #size-cells = <1>; + ranges; + clock-frequency = <0>; /* Filled in by zImage */ + + SDRAM0: sdram { + compatible = "ibm,sdram-440ep", "ibm,sdram-405gp"; + dcr-reg = <010 2>; + }; + + DMA0: dma { + compatible = "ibm,dma-440ep", "ibm,dma-440gp"; + dcr-reg = <100 027>; + }; + + MAL0: mcmal { + compatible = "ibm,mcmal-440ep", "ibm,mcmal-440gp", "ibm,mcmal"; + dcr-reg = <180 62>; + num-tx-chans = <4>; + num-rx-chans = <2>; + interrupt-parent = <&MAL0>; + interrupts = <0 1 2 3 4>; + #interrupt-cells = <1>; + #address-cells = <0>; + #size-cells = <0>; + interrupt-map = ; + }; + + POB0: opb { + compatible = "ibm,opb-440ep", "ibm,opb-440gp", "ibm,opb"; + #address-cells = <1>; + #size-cells = <1>; + /* Bamboo is oddball in the 44x world and doesn't use the ERPN + * bits. + */ + ranges = <00000000 0 00000000 80000000 + 80000000 0 80000000 80000000>; + interrupt-parent = <&UIC1>; + interrupts = <7 4>; + clock-frequency = <0>; /* Filled in by zImage */ + + EBC0: ebc { + compatible = "ibm,ebc-440ep", "ibm,ebc-440gp", "ibm,ebc"; + dcr-reg = <012 2>; + #address-cells = <2>; + #size-cells = <1>; + clock-frequency = <0>; /* Filled in by zImage */ + interrupts = <5 1>; + interrupt-parent = <&UIC1>; + }; + + UART0: serial@ef600300 { + device_type = "serial"; + compatible = "ns16550"; + reg = ; + virtual-reg = ; + clock-frequency = <0>; /* Filled in by zImage */ + current-speed = <1c200>; + interrupt-parent = <&UIC0>; + interrupts = <0 4>; + }; + + UART1: serial@ef600400 { + device_type = "serial"; + compatible = "ns16550"; + reg = ; + virtual-reg = ; + clock-frequency = <0>; + current-speed = <0>; + interrupt-parent = <&UIC0>; + interrupts = <1 4>; + }; + + UART2: serial@ef600500 { + device_type = "serial"; + compatible = "ns16550"; + reg = ; + virtual-reg = ; + clock-frequency = <0>; + current-speed = <0>; + interrupt-parent = <&UIC0>; + interrupts = <3 4>; + }; + + UART3: serial@ef600600 { + device_type = "serial"; + compatible = "ns16550"; + reg = ; + virtual-reg = ; + clock-frequency = <0>; + current-speed = <0>; + interrupt-parent = <&UIC0>; + interrupts = <4 4>; + }; + + IIC0: i2c@ef600700 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "ibm,iic-440ep", "ibm,iic-440gp", "ibm,iic"; + index = <0>; + reg = ; + interrupt-parent = <&UIC0>; + interrupts = <2 4>; + rtc@68 { + compatible = "stm,m41t80"; + reg = <68>; + }; + }; + + IIC1: i2c@ef600800 { + compatible = "ibm,iic-440ep", "ibm,iic-440gp", "ibm,iic"; + index = <5>; + reg = ; + interrupt-parent = <&UIC0>; + interrupts = <7 4>; + }; + + ZMII0: emac-zmii@ef600d00 { + compatible = "ibm,zmii-440ep", "ibm,zmii-440gp", "ibm,zmii"; + reg = ; + }; + + EMAC0: ethernet@ef600e00 { + linux,network-index = <0>; + device_type = "network"; + compatible = "ibm,emac-440ep", "ibm,emac-440gp", "ibm,emac"; + interrupt-parent = <&UIC1>; + interrupts = <1c 4 1d 4>; + reg = ; + local-mac-address = [000000000000]; + mal-device = <&MAL0>; + mal-tx-channel = <0 1>; + mal-rx-channel = <0>; + cell-index = <0>; + max-frame-size = <5dc>; + rx-fifo-size = <1000>; + tx-fifo-size = <800>; + phy-mode = "rmii"; + phy-map = <00000000>; + zmii-device = <&ZMII0>; + zmii-channel = <0>; + }; + + EMAC1: ethernet@ef600f00 { + linux,network-index = <1>; + device_type = "network"; + compatible = "ibm,emac-440ep", "ibm,emac-440gp", "ibm,emac"; + interrupt-parent = <&UIC1>; + interrupts = <1e 4 1f 4>; + reg = ; + local-mac-address = [000000000000]; + mal-device = <&MAL0>; + mal-tx-channel = <2 3>; + mal-rx-channel = <1>; + cell-index = <1>; + max-frame-size = <5dc>; + rx-fifo-size = <1000>; + tx-fifo-size = <800>; + phy-mode = "rmii"; + phy-map = <00000000>; + zmii-device = <&ZMII0>; + zmii-channel = <1>; + }; + usb@ef601000 { + compatible = "ohci-be"; + reg = ; + interrupts = <8 4 9 4>; + interrupt-parent = < &UIC1 >; + }; + }; + + PCI0: pci@ec000000 { + device_type = "pci"; + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + compatible = "ibm,plb440ep-pci", "ibm,plb-pci"; + primary; + reg = <0 eec00000 8 /* Config space access */ + 0 eed00000 4 /* IACK */ + 0 eed00000 4 /* Special cycle */ + 0 ef400000 40>; /* Internal registers */ + + /* Outbound ranges, one memory and one IO, + * later cannot be changed. Chip supports a second + * IO range but we don't use it for now + */ + ranges = <02000000 0 a0000000 0 a0000000 0 20000000 + 01000000 0 00000000 0 e8000000 0 00010000>; + + /* Inbound 2GB range starting at 0 */ + dma-ranges = <42000000 0 0 0 0 0 80000000>; + }; + }; + + chosen { + linux,stdout-path = "/plb/opb/serial@ef600300"; + }; +}; -- cgit v1.1 From d2146cb274e494dd14e50f5b4cdeb7a5e5af5421 Mon Sep 17 00:00:00 2001 From: Giuseppe Coviello Date: Fri, 23 May 2008 03:51:37 +1000 Subject: powerpc/4xx: Convert Sam440ep DTS to dts-v1 This makes the sam440ep.dts dts-v1 compliant. Signed-off-by: Giuseppe Coviello Signed-off-by: Josh Boyer --- arch/powerpc/boot/dts/sam440ep.dts | 101 +++++++++++++++++++------------------ 1 file changed, 51 insertions(+), 50 deletions(-) (limited to 'arch/powerpc/boot') diff --git a/arch/powerpc/boot/dts/sam440ep.dts b/arch/powerpc/boot/dts/sam440ep.dts index b0984d5..f0663be 100644 --- a/arch/powerpc/boot/dts/sam440ep.dts +++ b/arch/powerpc/boot/dts/sam440ep.dts @@ -13,12 +13,13 @@ * any warranty of any kind, whether express or implied. */ +/dts-v1/; + / { #address-cells = <2>; #size-cells = <1>; model = "acube,sam440ep"; compatible = "acube,sam440ep"; - dcr-parent = <&/cpus/cpu@0>; aliases { ethernet0 = &EMAC0; @@ -39,10 +40,10 @@ reg = <0>; clock-frequency = <0>; /* Filled in by zImage */ timebase-frequency = <0>; /* Filled in by zImage */ - i-cache-line-size = <20>; - d-cache-line-size = <20>; - i-cache-size = <8000>; - d-cache-size = <8000>; + i-cache-line-size = <32>; + d-cache-line-size = <32>; + i-cache-size = <32768>; + d-cache-size = <32768>; dcr-controller; dcr-access-method = "native"; }; @@ -57,7 +58,7 @@ compatible = "ibm,uic-440ep","ibm,uic"; interrupt-controller; cell-index = <0>; - dcr-reg = <0c0 009>; + dcr-reg = <0x0c0 9>; #address-cells = <0>; #size-cells = <0>; #interrupt-cells = <2>; @@ -67,22 +68,22 @@ compatible = "ibm,uic-440ep","ibm,uic"; interrupt-controller; cell-index = <1>; - dcr-reg = <0d0 009>; + dcr-reg = <0x0d0 9>; #address-cells = <0>; #size-cells = <0>; #interrupt-cells = <2>; - interrupts = <1e 4 1f 4>; /* cascade */ + interrupts = <0x1e 4 0x1f 4>; /* cascade */ interrupt-parent = <&UIC0>; }; SDR0: sdr { compatible = "ibm,sdr-440ep"; - dcr-reg = <00e 002>; + dcr-reg = <0x00e 2>; }; CPR0: cpr { compatible = "ibm,cpr-440ep"; - dcr-reg = <00c 002>; + dcr-reg = <0x00c 2>; }; plb { @@ -94,17 +95,17 @@ SDRAM0: sdram { compatible = "ibm,sdram-440ep", "ibm,sdram-405gp"; - dcr-reg = <010 2>; + dcr-reg = <0x010 2>; }; DMA0: dma { compatible = "ibm,dma-440ep", "ibm,dma-440gp"; - dcr-reg = <100 027>; + dcr-reg = <0x100 0x027>; }; MAL0: mcmal { compatible = "ibm,mcmal-440ep", "ibm,mcmal-440gp", "ibm,mcmal"; - dcr-reg = <180 62>; + dcr-reg = <0x180 0x062>; num-tx-chans = <4>; num-rx-chans = <2>; interrupt-parent = <&MAL0>; @@ -112,8 +113,8 @@ #interrupt-cells = <1>; #address-cells = <0>; #size-cells = <0>; - interrupt-map = ; @@ -126,15 +127,15 @@ /* Bamboo is oddball in the 44x world and doesn't use the ERPN * bits. */ - ranges = <00000000 0 00000000 80000000 - 80000000 0 80000000 80000000>; + ranges = <0x00000000 0 0x00000000 0x80000000 + 0x80000000 0 0x80000000 0x80000000>; interrupt-parent = <&UIC1>; interrupts = <7 4>; clock-frequency = <0>; /* Filled in by zImage */ EBC0: ebc { compatible = "ibm,ebc-440ep", "ibm,ebc-440gp", "ibm,ebc"; - dcr-reg = <012 2>; + dcr-reg = <0x012 2>; #address-cells = <2>; #size-cells = <1>; clock-frequency = <0>; /* Filled in by zImage */ @@ -145,10 +146,10 @@ UART0: serial@ef600300 { device_type = "serial"; compatible = "ns16550"; - reg = ; - virtual-reg = ; + reg = <0xef600300 8>; + virtual-reg = <0xef600300>; clock-frequency = <0>; /* Filled in by zImage */ - current-speed = <1c200>; + current-speed = <0x1c200>; interrupt-parent = <&UIC0>; interrupts = <0 4>; }; @@ -156,8 +157,8 @@ UART1: serial@ef600400 { device_type = "serial"; compatible = "ns16550"; - reg = ; - virtual-reg = ; + reg = <0xef600400 8>; + virtual-reg = <0xef600400>; clock-frequency = <0>; current-speed = <0>; interrupt-parent = <&UIC0>; @@ -167,8 +168,8 @@ UART2: serial@ef600500 { device_type = "serial"; compatible = "ns16550"; - reg = ; - virtual-reg = ; + reg = <0xef600500 8>; + virtual-reg = <0xef600500>; clock-frequency = <0>; current-speed = <0>; interrupt-parent = <&UIC0>; @@ -178,8 +179,8 @@ UART3: serial@ef600600 { device_type = "serial"; compatible = "ns16550"; - reg = ; - virtual-reg = ; + reg = <0xef600600 8>; + virtual-reg = <0xef600600>; clock-frequency = <0>; current-speed = <0>; interrupt-parent = <&UIC0>; @@ -191,26 +192,26 @@ #size-cells = <0>; compatible = "ibm,iic-440ep", "ibm,iic-440gp", "ibm,iic"; index = <0>; - reg = ; + reg = <0xef600700 0x14>; interrupt-parent = <&UIC0>; interrupts = <2 4>; rtc@68 { compatible = "stm,m41t80"; - reg = <68>; + reg = <0x68>; }; }; IIC1: i2c@ef600800 { compatible = "ibm,iic-440ep", "ibm,iic-440gp", "ibm,iic"; index = <5>; - reg = ; + reg = <0xef600800 0x14>; interrupt-parent = <&UIC0>; interrupts = <7 4>; }; ZMII0: emac-zmii@ef600d00 { compatible = "ibm,zmii-440ep", "ibm,zmii-440gp", "ibm,zmii"; - reg = ; + reg = <0xef600d00 0xc>; }; EMAC0: ethernet@ef600e00 { @@ -218,16 +219,16 @@ device_type = "network"; compatible = "ibm,emac-440ep", "ibm,emac-440gp", "ibm,emac"; interrupt-parent = <&UIC1>; - interrupts = <1c 4 1d 4>; - reg = ; + interrupts = <0x1c 4 0x1d 4>; + reg = <0xef600e00 0x70>; local-mac-address = [000000000000]; mal-device = <&MAL0>; mal-tx-channel = <0 1>; mal-rx-channel = <0>; cell-index = <0>; - max-frame-size = <5dc>; - rx-fifo-size = <1000>; - tx-fifo-size = <800>; + max-frame-size = <0x5dc>; + rx-fifo-size = <0x1000>; + tx-fifo-size = <0x800>; phy-mode = "rmii"; phy-map = <00000000>; zmii-device = <&ZMII0>; @@ -239,16 +240,16 @@ device_type = "network"; compatible = "ibm,emac-440ep", "ibm,emac-440gp", "ibm,emac"; interrupt-parent = <&UIC1>; - interrupts = <1e 4 1f 4>; - reg = ; + interrupts = <0x1e 4 0x1f 4>; + reg = <0xef600f00 0x70>; local-mac-address = [000000000000]; mal-device = <&MAL0>; mal-tx-channel = <2 3>; mal-rx-channel = <1>; cell-index = <1>; - max-frame-size = <5dc>; - rx-fifo-size = <1000>; - tx-fifo-size = <800>; + max-frame-size = <0x5dc>; + rx-fifo-size = <0x1000>; + tx-fifo-size = <0x800>; phy-mode = "rmii"; phy-map = <00000000>; zmii-device = <&ZMII0>; @@ -256,9 +257,9 @@ }; usb@ef601000 { compatible = "ohci-be"; - reg = ; + reg = <0xef601000 0x80>; interrupts = <8 4 9 4>; - interrupt-parent = < &UIC1 >; + interrupt-parent = <&UIC1>; }; }; @@ -269,20 +270,20 @@ #address-cells = <3>; compatible = "ibm,plb440ep-pci", "ibm,plb-pci"; primary; - reg = <0 eec00000 8 /* Config space access */ - 0 eed00000 4 /* IACK */ - 0 eed00000 4 /* Special cycle */ - 0 ef400000 40>; /* Internal registers */ + reg = <0 0xeec00000 8 /* Config space access */ + 0 0xeed00000 4 /* IACK */ + 0 0xeed00000 4 /* Special cycle */ + 0 0xef400000 0x40>; /* Internal registers */ /* Outbound ranges, one memory and one IO, * later cannot be changed. Chip supports a second * IO range but we don't use it for now */ - ranges = <02000000 0 a0000000 0 a0000000 0 20000000 - 01000000 0 00000000 0 e8000000 0 00010000>; + ranges = <0x02000000 0 0xa0000000 0 0xa0000000 0 0x20000000 + 0x01000000 0 0x00000000 0 0xe8000000 0 0x00010000>; /* Inbound 2GB range starting at 0 */ - dma-ranges = <42000000 0 0 0 0 0 80000000>; + dma-ranges = <0x42000000 0 0 0 0 0 0x80000000>; }; }; -- cgit v1.1 From dee805532a30183c4462305b4614e58bd83a7bc1 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Fri, 27 Jun 2008 13:45:19 -0500 Subject: powerpc: Add dma nodes to 83xx, 85xx and 86xx boards Added DMA nodes for the elo/elo-plus DMA engines. Renamed the interrupt controller alias in mpc832x_rdb.dts to ipic so that its the same as all the other boards. Signed-off-by: Kumar Gala --- arch/powerpc/boot/dts/asp834x-redboot.dts | 35 +++++++++++++ arch/powerpc/boot/dts/ksi8560.dts | 41 +++++++++++++++ arch/powerpc/boot/dts/mpc8313erdb.dts | 35 +++++++++++++ arch/powerpc/boot/dts/mpc8315erdb.dts | 35 +++++++++++++ arch/powerpc/boot/dts/mpc832x_mds.dts | 35 +++++++++++++ arch/powerpc/boot/dts/mpc832x_rdb.dts | 71 +++++++++++++++++++------- arch/powerpc/boot/dts/mpc8349emitx.dts | 35 +++++++++++++ arch/powerpc/boot/dts/mpc8349emitxgp.dts | 35 +++++++++++++ arch/powerpc/boot/dts/mpc834x_mds.dts | 35 +++++++++++++ arch/powerpc/boot/dts/mpc836x_mds.dts | 35 +++++++++++++ arch/powerpc/boot/dts/mpc836x_rdk.dts | 35 +++++++++++++ arch/powerpc/boot/dts/mpc8377_mds.dts | 70 ++++++++++++------------- arch/powerpc/boot/dts/mpc8377_rdb.dts | 35 +++++++++++++ arch/powerpc/boot/dts/mpc8378_mds.dts | 35 +++++++++++++ arch/powerpc/boot/dts/mpc8378_rdb.dts | 35 +++++++++++++ arch/powerpc/boot/dts/mpc8379_mds.dts | 35 +++++++++++++ arch/powerpc/boot/dts/mpc8379_rdb.dts | 35 +++++++++++++ arch/powerpc/boot/dts/mpc8540ads.dts | 41 +++++++++++++++ arch/powerpc/boot/dts/mpc8541cds.dts | 41 +++++++++++++++ arch/powerpc/boot/dts/mpc8548cds.dts | 41 +++++++++++++++ arch/powerpc/boot/dts/mpc8555cds.dts | 41 +++++++++++++++ arch/powerpc/boot/dts/mpc8560ads.dts | 41 +++++++++++++++ arch/powerpc/boot/dts/mpc8568mds.dts | 41 +++++++++++++++ arch/powerpc/boot/dts/mpc8572ds.dts | 82 ++++++++++++++++++++++++++++++ arch/powerpc/boot/dts/mpc8641_hpcn.dts | 41 +++++++++++++++ arch/powerpc/boot/dts/sbc8349.dts | 35 +++++++++++++ arch/powerpc/boot/dts/sbc8548.dts | 41 +++++++++++++++ arch/powerpc/boot/dts/sbc8560.dts | 41 +++++++++++++++ arch/powerpc/boot/dts/sbc8641d.dts | 41 +++++++++++++++ arch/powerpc/boot/dts/stx_gp3_8560.dts | 41 +++++++++++++++ arch/powerpc/boot/dts/tqm8540.dts | 41 +++++++++++++++ arch/powerpc/boot/dts/tqm8541.dts | 41 +++++++++++++++ arch/powerpc/boot/dts/tqm8548-bigflash.dts | 41 +++++++++++++++ arch/powerpc/boot/dts/tqm8548.dts | 41 +++++++++++++++ arch/powerpc/boot/dts/tqm8555.dts | 41 +++++++++++++++ arch/powerpc/boot/dts/tqm8560.dts | 41 +++++++++++++++ 36 files changed, 1433 insertions(+), 53 deletions(-) (limited to 'arch/powerpc/boot') diff --git a/arch/powerpc/boot/dts/asp834x-redboot.dts b/arch/powerpc/boot/dts/asp834x-redboot.dts index 972cf78..8b1bb0e 100644 --- a/arch/powerpc/boot/dts/asp834x-redboot.dts +++ b/arch/powerpc/boot/dts/asp834x-redboot.dts @@ -118,6 +118,41 @@ mode = "cpu"; }; + dma@82a8 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,mpc8347-dma", "fsl,elo-dma"; + reg = <0x82a8 4>; + ranges = <0 0x8100 0x1a8>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + cell-index = <0>; + dma-channel@0 { + compatible = "fsl,mpc8347-dma-channel", "fsl,elo-dma-channel"; + reg = <0 0x80>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + }; + dma-channel@80 { + compatible = "fsl,mpc8347-dma-channel", "fsl,elo-dma-channel"; + reg = <0x80 0x80>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + }; + dma-channel@100 { + compatible = "fsl,mpc8347-dma-channel", "fsl,elo-dma-channel"; + reg = <0x100 0x80>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + }; + dma-channel@180 { + compatible = "fsl,mpc8347-dma-channel", "fsl,elo-dma-channel"; + reg = <0x180 0x28>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + }; + }; + /* phy type (ULPI or SERIAL) are only types supported for MPH */ /* port = 0 or 1 */ usb@22000 { diff --git a/arch/powerpc/boot/dts/ksi8560.dts b/arch/powerpc/boot/dts/ksi8560.dts index 6eb7c77..fd58043 100644 --- a/arch/powerpc/boot/dts/ksi8560.dts +++ b/arch/powerpc/boot/dts/ksi8560.dts @@ -83,6 +83,47 @@ dfsrr; }; + dma@21300 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,mpc8560-dma", "fsl,eloplus-dma"; + reg = <0x21300 0x4>; + ranges = <0x0 0x21100 0x200>; + cell-index = <0>; + dma-channel@0 { + compatible = "fsl,mpc8560-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x0 0x80>; + cell-index = <0>; + interrupt-parent = <&mpic>; + interrupts = <20 2>; + }; + dma-channel@80 { + compatible = "fsl,mpc8560-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x80 0x80>; + cell-index = <1>; + interrupt-parent = <&mpic>; + interrupts = <21 2>; + }; + dma-channel@100 { + compatible = "fsl,mpc8560-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x100 0x80>; + cell-index = <2>; + interrupt-parent = <&mpic>; + interrupts = <22 2>; + }; + dma-channel@180 { + compatible = "fsl,mpc8560-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x180 0x80>; + cell-index = <3>; + interrupt-parent = <&mpic>; + interrupts = <23 2>; + }; + }; + mdio@24520 { /* For TSECs */ #address-cells = <1>; #size-cells = <0>; diff --git a/arch/powerpc/boot/dts/mpc8313erdb.dts b/arch/powerpc/boot/dts/mpc8313erdb.dts index e1f0dca..b206843 100644 --- a/arch/powerpc/boot/dts/mpc8313erdb.dts +++ b/arch/powerpc/boot/dts/mpc8313erdb.dts @@ -144,6 +144,41 @@ mode = "cpu"; }; + dma@82a8 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,mpc8313-dma", "fsl,elo-dma"; + reg = <0x82a8 4>; + ranges = <0 0x8100 0x1a8>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + cell-index = <0>; + dma-channel@0 { + compatible = "fsl,mpc8313-dma-channel", "fsl,elo-dma-channel"; + reg = <0 0x80>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + }; + dma-channel@80 { + compatible = "fsl,mpc8313-dma-channel", "fsl,elo-dma-channel"; + reg = <0x80 0x80>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + }; + dma-channel@100 { + compatible = "fsl,mpc8313-dma-channel", "fsl,elo-dma-channel"; + reg = <0x100 0x80>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + }; + dma-channel@180 { + compatible = "fsl,mpc8313-dma-channel", "fsl,elo-dma-channel"; + reg = <0x180 0x28>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + }; + }; + /* phy type (ULPI, UTMI, UTMI_WIDE, SERIAL) */ usb@23000 { compatible = "fsl-usb2-dr"; diff --git a/arch/powerpc/boot/dts/mpc8315erdb.dts b/arch/powerpc/boot/dts/mpc8315erdb.dts index d7a1ece..a40e806 100644 --- a/arch/powerpc/boot/dts/mpc8315erdb.dts +++ b/arch/powerpc/boot/dts/mpc8315erdb.dts @@ -132,6 +132,41 @@ mode = "cpu"; }; + dma@82a8 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,mpc8315-dma", "fsl,elo-dma"; + reg = <0x82a8 4>; + ranges = <0 0x8100 0x1a8>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + cell-index = <0>; + dma-channel@0 { + compatible = "fsl,mpc8315-dma-channel", "fsl,elo-dma-channel"; + reg = <0 0x80>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + }; + dma-channel@80 { + compatible = "fsl,mpc8315-dma-channel", "fsl,elo-dma-channel"; + reg = <0x80 0x80>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + }; + dma-channel@100 { + compatible = "fsl,mpc8315-dma-channel", "fsl,elo-dma-channel"; + reg = <0x100 0x80>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + }; + dma-channel@180 { + compatible = "fsl,mpc8315-dma-channel", "fsl,elo-dma-channel"; + reg = <0x180 0x28>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + }; + }; + usb@23000 { compatible = "fsl-usb2-dr"; reg = <0x23000 0x1000>; diff --git a/arch/powerpc/boot/dts/mpc832x_mds.dts b/arch/powerpc/boot/dts/mpc832x_mds.dts index 539e02f..b5968b6 100644 --- a/arch/powerpc/boot/dts/mpc832x_mds.dts +++ b/arch/powerpc/boot/dts/mpc832x_mds.dts @@ -114,6 +114,41 @@ interrupt-parent = <&ipic>; }; + dma@82a8 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,mpc8323-dma", "fsl,elo-dma"; + reg = <0x82a8 4>; + ranges = <0 0x8100 0x1a8>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + cell-index = <0>; + dma-channel@0 { + compatible = "fsl,mpc8323-dma-channel", "fsl,elo-dma-channel"; + reg = <0 0x80>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + }; + dma-channel@80 { + compatible = "fsl,mpc8323-dma-channel", "fsl,elo-dma-channel"; + reg = <0x80 0x80>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + }; + dma-channel@100 { + compatible = "fsl,mpc8323-dma-channel", "fsl,elo-dma-channel"; + reg = <0x100 0x80>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + }; + dma-channel@180 { + compatible = "fsl,mpc8323-dma-channel", "fsl,elo-dma-channel"; + reg = <0x180 0x28>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + }; + }; + crypto@30000 { device_type = "crypto"; model = "SEC2"; diff --git a/arch/powerpc/boot/dts/mpc832x_rdb.dts b/arch/powerpc/boot/dts/mpc832x_rdb.dts index 179c81c..a798d86 100644 --- a/arch/powerpc/boot/dts/mpc832x_rdb.dts +++ b/arch/powerpc/boot/dts/mpc832x_rdb.dts @@ -68,7 +68,7 @@ compatible = "fsl-i2c"; reg = <0x3000 0x100>; interrupts = <14 0x8>; - interrupt-parent = <&pic>; + interrupt-parent = <&ipic>; dfsrr; }; @@ -79,7 +79,7 @@ reg = <0x4500 0x100>; clock-frequency = <0>; interrupts = <9 0x8>; - interrupt-parent = <&pic>; + interrupt-parent = <&ipic>; }; serial1: serial@4600 { @@ -89,7 +89,42 @@ reg = <0x4600 0x100>; clock-frequency = <0>; interrupts = <10 0x8>; - interrupt-parent = <&pic>; + interrupt-parent = <&ipic>; + }; + + dma@82a8 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,mpc8323-dma", "fsl,elo-dma"; + reg = <0x82a8 4>; + ranges = <0 0x8100 0x1a8>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + cell-index = <0>; + dma-channel@0 { + compatible = "fsl,mpc8323-dma-channel", "fsl,elo-dma-channel"; + reg = <0 0x80>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + }; + dma-channel@80 { + compatible = "fsl,mpc8323-dma-channel", "fsl,elo-dma-channel"; + reg = <0x80 0x80>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + }; + dma-channel@100 { + compatible = "fsl,mpc8323-dma-channel", "fsl,elo-dma-channel"; + reg = <0x100 0x80>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + }; + dma-channel@180 { + compatible = "fsl,mpc8323-dma-channel", "fsl,elo-dma-channel"; + reg = <0x180 0x28>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + }; }; crypto@30000 { @@ -98,7 +133,7 @@ compatible = "talitos"; reg = <0x30000 0x7000>; interrupts = <11 0x8>; - interrupt-parent = <&pic>; + interrupt-parent = <&ipic>; /* Rev. 2.2 */ num-channels = <1>; channel-fifo-len = <24>; @@ -106,7 +141,7 @@ descriptor-types-mask = <0x0122003f>; }; - pic:pic@700 { + ipic:pic@700 { interrupt-controller; #address-cells = <0>; #interrupt-cells = <2>; @@ -240,13 +275,13 @@ compatible = "fsl,ucc-mdio"; phy00:ethernet-phy@00 { - interrupt-parent = <&pic>; + interrupt-parent = <&ipic>; interrupts = <0>; reg = <0x0>; device_type = "ethernet-phy"; }; phy04:ethernet-phy@04 { - interrupt-parent = <&pic>; + interrupt-parent = <&ipic>; interrupts = <0>; reg = <0x4>; device_type = "ethernet-phy"; @@ -261,7 +296,7 @@ reg = <0x80 0x80>; big-endian; interrupts = <32 0x8 33 0x8>; //high:32 low:33 - interrupt-parent = <&pic>; + interrupt-parent = <&ipic>; }; }; @@ -270,21 +305,21 @@ interrupt-map-mask = <0xf800 0x0 0x0 0x7>; interrupt-map = < /* IDSEL 0x10 AD16 (USB) */ - 0x8000 0x0 0x0 0x1 &pic 17 0x8 + 0x8000 0x0 0x0 0x1 &ipic 17 0x8 /* IDSEL 0x11 AD17 (Mini1)*/ - 0x8800 0x0 0x0 0x1 &pic 18 0x8 - 0x8800 0x0 0x0 0x2 &pic 19 0x8 - 0x8800 0x0 0x0 0x3 &pic 20 0x8 - 0x8800 0x0 0x0 0x4 &pic 48 0x8 + 0x8800 0x0 0x0 0x1 &ipic 18 0x8 + 0x8800 0x0 0x0 0x2 &ipic 19 0x8 + 0x8800 0x0 0x0 0x3 &ipic 20 0x8 + 0x8800 0x0 0x0 0x4 &ipic 48 0x8 /* IDSEL 0x12 AD18 (PCI/Mini2) */ - 0x9000 0x0 0x0 0x1 &pic 19 0x8 - 0x9000 0x0 0x0 0x2 &pic 20 0x8 - 0x9000 0x0 0x0 0x3 &pic 48 0x8 - 0x9000 0x0 0x0 0x4 &pic 17 0x8>; + 0x9000 0x0 0x0 0x1 &ipic 19 0x8 + 0x9000 0x0 0x0 0x2 &ipic 20 0x8 + 0x9000 0x0 0x0 0x3 &ipic 48 0x8 + 0x9000 0x0 0x0 0x4 &ipic 17 0x8>; - interrupt-parent = <&pic>; + interrupt-parent = <&ipic>; interrupts = <66 0x8>; bus-range = <0x0 0x0>; ranges = <0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000 diff --git a/arch/powerpc/boot/dts/mpc8349emitx.dts b/arch/powerpc/boot/dts/mpc8349emitx.dts index 9426676..fc0f4c9 100644 --- a/arch/powerpc/boot/dts/mpc8349emitx.dts +++ b/arch/powerpc/boot/dts/mpc8349emitx.dts @@ -93,6 +93,41 @@ mode = "cpu"; }; + dma@82a8 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,mpc8349-dma", "fsl,elo-dma"; + reg = <0x82a8 4>; + ranges = <0 0x8100 0x1a8>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + cell-index = <0>; + dma-channel@0 { + compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel"; + reg = <0 0x80>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + }; + dma-channel@80 { + compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel"; + reg = <0x80 0x80>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + }; + dma-channel@100 { + compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel"; + reg = <0x100 0x80>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + }; + dma-channel@180 { + compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel"; + reg = <0x180 0x28>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + }; + }; + usb@22000 { compatible = "fsl-usb2-mph"; reg = <0x22000 0x1000>; diff --git a/arch/powerpc/boot/dts/mpc8349emitxgp.dts b/arch/powerpc/boot/dts/mpc8349emitxgp.dts index f81d735..e6afb1d 100644 --- a/arch/powerpc/boot/dts/mpc8349emitxgp.dts +++ b/arch/powerpc/boot/dts/mpc8349emitxgp.dts @@ -91,6 +91,41 @@ mode = "cpu"; }; + dma@82a8 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,mpc8349-dma", "fsl,elo-dma"; + reg = <0x82a8 4>; + ranges = <0 0x8100 0x1a8>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + cell-index = <0>; + dma-channel@0 { + compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel"; + reg = <0 0x80>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + }; + dma-channel@80 { + compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel"; + reg = <0x80 0x80>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + }; + dma-channel@100 { + compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel"; + reg = <0x100 0x80>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + }; + dma-channel@180 { + compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel"; + reg = <0x180 0x28>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + }; + }; + usb@23000 { compatible = "fsl-usb2-dr"; reg = <0x23000 0x1000>; diff --git a/arch/powerpc/boot/dts/mpc834x_mds.dts b/arch/powerpc/boot/dts/mpc834x_mds.dts index 0199c5c..9c75c7c 100644 --- a/arch/powerpc/boot/dts/mpc834x_mds.dts +++ b/arch/powerpc/boot/dts/mpc834x_mds.dts @@ -103,6 +103,41 @@ mode = "cpu"; }; + dma@82a8 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,mpc8349-dma", "fsl,elo-dma"; + reg = <0x82a8 4>; + ranges = <0 0x8100 0x1a8>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + cell-index = <0>; + dma-channel@0 { + compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel"; + reg = <0 0x80>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + }; + dma-channel@80 { + compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel"; + reg = <0x80 0x80>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + }; + dma-channel@100 { + compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel"; + reg = <0x100 0x80>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + }; + dma-channel@180 { + compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel"; + reg = <0x180 0x28>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + }; + }; + /* phy type (ULPI or SERIAL) are only types supported for MPH */ /* port = 0 or 1 */ usb@22000 { diff --git a/arch/powerpc/boot/dts/mpc836x_mds.dts b/arch/powerpc/boot/dts/mpc836x_mds.dts index 8160ff2..8e33b15 100644 --- a/arch/powerpc/boot/dts/mpc836x_mds.dts +++ b/arch/powerpc/boot/dts/mpc836x_mds.dts @@ -118,6 +118,41 @@ interrupt-parent = <&ipic>; }; + dma@82a8 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,mpc8360-dma", "fsl,elo-dma"; + reg = <0x82a8 4>; + ranges = <0 0x8100 0x1a8>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + cell-index = <0>; + dma-channel@0 { + compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel"; + reg = <0 0x80>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + }; + dma-channel@80 { + compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel"; + reg = <0x80 0x80>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + }; + dma-channel@100 { + compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel"; + reg = <0x100 0x80>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + }; + dma-channel@180 { + compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel"; + reg = <0x180 0x28>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + }; + }; + crypto@30000 { device_type = "crypto"; model = "SEC2"; diff --git a/arch/powerpc/boot/dts/mpc836x_rdk.dts b/arch/powerpc/boot/dts/mpc836x_rdk.dts index 3402d26..8acd1d6 100644 --- a/arch/powerpc/boot/dts/mpc836x_rdk.dts +++ b/arch/powerpc/boot/dts/mpc836x_rdk.dts @@ -113,6 +113,41 @@ clock-frequency = <0>; }; + dma@82a8 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,mpc8360-dma", "fsl,elo-dma"; + reg = <0x82a8 4>; + ranges = <0 0x8100 0x1a8>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + cell-index = <0>; + dma-channel@0 { + compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel"; + reg = <0 0x80>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + }; + dma-channel@80 { + compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel"; + reg = <0x80 0x80>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + }; + dma-channel@100 { + compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel"; + reg = <0x100 0x80>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + }; + dma-channel@180 { + compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel"; + reg = <0x180 0x28>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + }; + }; + crypto@30000 { compatible = "fsl,sec2-crypto"; reg = <0x30000 0x10000>; diff --git a/arch/powerpc/boot/dts/mpc8377_mds.dts b/arch/powerpc/boot/dts/mpc8377_mds.dts index fea5925..49a38cb 100644 --- a/arch/powerpc/boot/dts/mpc8377_mds.dts +++ b/arch/powerpc/boot/dts/mpc8377_mds.dts @@ -233,41 +233,6 @@ interrupt-parent = <&ipic>; }; - crypto@30000 { - model = "SEC3"; - compatible = "talitos"; - reg = <0x30000 0x10000>; - interrupts = <11 0x8>; - interrupt-parent = <&ipic>; - /* Rev. 3.0 geometry */ - num-channels = <4>; - channel-fifo-len = <24>; - exec-units-mask = <0x000001fe>; - descriptor-types-mask = <0x03ab0ebf>; - }; - - sdhc@2e000 { - model = "eSDHC"; - compatible = "fsl,esdhc"; - reg = <0x2e000 0x1000>; - interrupts = <42 0x8>; - interrupt-parent = <&ipic>; - }; - - sata@18000 { - compatible = "fsl,mpc8379-sata", "fsl,pq-sata"; - reg = <0x18000 0x1000>; - interrupts = <44 0x8>; - interrupt-parent = <&ipic>; - }; - - sata@19000 { - compatible = "fsl,mpc8379-sata", "fsl,pq-sata"; - reg = <0x19000 0x1000>; - interrupts = <45 0x8>; - interrupt-parent = <&ipic>; - }; - dma@82a8 { #address-cells = <1>; #size-cells = <1>; @@ -303,6 +268,41 @@ }; }; + crypto@30000 { + model = "SEC3"; + compatible = "talitos"; + reg = <0x30000 0x10000>; + interrupts = <11 0x8>; + interrupt-parent = <&ipic>; + /* Rev. 3.0 geometry */ + num-channels = <4>; + channel-fifo-len = <24>; + exec-units-mask = <0x000001fe>; + descriptor-types-mask = <0x03ab0ebf>; + }; + + sdhc@2e000 { + model = "eSDHC"; + compatible = "fsl,esdhc"; + reg = <0x2e000 0x1000>; + interrupts = <42 0x8>; + interrupt-parent = <&ipic>; + }; + + sata@18000 { + compatible = "fsl,mpc8379-sata", "fsl,pq-sata"; + reg = <0x18000 0x1000>; + interrupts = <44 0x8>; + interrupt-parent = <&ipic>; + }; + + sata@19000 { + compatible = "fsl,mpc8379-sata", "fsl,pq-sata"; + reg = <0x19000 0x1000>; + interrupts = <45 0x8>; + interrupt-parent = <&ipic>; + }; + /* IPIC * interrupts cell = * sense values match linux IORESOURCE_IRQ_* defines: diff --git a/arch/powerpc/boot/dts/mpc8377_rdb.dts b/arch/powerpc/boot/dts/mpc8377_rdb.dts index 5bc09ad..e05743a 100644 --- a/arch/powerpc/boot/dts/mpc8377_rdb.dts +++ b/arch/powerpc/boot/dts/mpc8377_rdb.dts @@ -143,6 +143,41 @@ mode = "cpu"; }; + dma@82a8 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,mpc8377-dma", "fsl,elo-dma"; + reg = <0x82a8 4>; + ranges = <0 0x8100 0x1a8>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + cell-index = <0>; + dma-channel@0 { + compatible = "fsl,mpc8377-dma-channel", "fsl,elo-dma-channel"; + reg = <0 0x80>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + }; + dma-channel@80 { + compatible = "fsl,mpc8377-dma-channel", "fsl,elo-dma-channel"; + reg = <0x80 0x80>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + }; + dma-channel@100 { + compatible = "fsl,mpc8377-dma-channel", "fsl,elo-dma-channel"; + reg = <0x100 0x80>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + }; + dma-channel@180 { + compatible = "fsl,mpc8377-dma-channel", "fsl,elo-dma-channel"; + reg = <0x180 0x28>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + }; + }; + usb@23000 { compatible = "fsl-usb2-dr"; reg = <0x23000 0x1000>; diff --git a/arch/powerpc/boot/dts/mpc8378_mds.dts b/arch/powerpc/boot/dts/mpc8378_mds.dts index 1d6ea08..99ad49d 100644 --- a/arch/powerpc/boot/dts/mpc8378_mds.dts +++ b/arch/powerpc/boot/dts/mpc8378_mds.dts @@ -157,6 +157,41 @@ mode = "cpu"; }; + dma@82a8 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,mpc8378-dma", "fsl,elo-dma"; + reg = <0x82a8 4>; + ranges = <0 0x8100 0x1a8>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + cell-index = <0>; + dma-channel@0 { + compatible = "fsl,mpc8378-dma-channel", "fsl,elo-dma-channel"; + reg = <0 0x80>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + }; + dma-channel@80 { + compatible = "fsl,mpc8378-dma-channel", "fsl,elo-dma-channel"; + reg = <0x80 0x80>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + }; + dma-channel@100 { + compatible = "fsl,mpc8378-dma-channel", "fsl,elo-dma-channel"; + reg = <0x100 0x80>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + }; + dma-channel@180 { + compatible = "fsl,mpc8378-dma-channel", "fsl,elo-dma-channel"; + reg = <0x180 0x28>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + }; + }; + usb@23000 { compatible = "fsl-usb2-dr"; reg = <0x23000 0x1000>; diff --git a/arch/powerpc/boot/dts/mpc8378_rdb.dts b/arch/powerpc/boot/dts/mpc8378_rdb.dts index 711f9a3..a8bdbaa 100644 --- a/arch/powerpc/boot/dts/mpc8378_rdb.dts +++ b/arch/powerpc/boot/dts/mpc8378_rdb.dts @@ -143,6 +143,41 @@ mode = "cpu"; }; + dma@82a8 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,mpc8378-dma", "fsl,elo-dma"; + reg = <0x82a8 4>; + ranges = <0 0x8100 0x1a8>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + cell-index = <0>; + dma-channel@0 { + compatible = "fsl,mpc8378-dma-channel", "fsl,elo-dma-channel"; + reg = <0 0x80>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + }; + dma-channel@80 { + compatible = "fsl,mpc8378-dma-channel", "fsl,elo-dma-channel"; + reg = <0x80 0x80>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + }; + dma-channel@100 { + compatible = "fsl,mpc8378-dma-channel", "fsl,elo-dma-channel"; + reg = <0x100 0x80>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + }; + dma-channel@180 { + compatible = "fsl,mpc8378-dma-channel", "fsl,elo-dma-channel"; + reg = <0x180 0x28>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + }; + }; + usb@23000 { compatible = "fsl-usb2-dr"; reg = <0x23000 0x1000>; diff --git a/arch/powerpc/boot/dts/mpc8379_mds.dts b/arch/powerpc/boot/dts/mpc8379_mds.dts index 6f78a9f..980be81 100644 --- a/arch/powerpc/boot/dts/mpc8379_mds.dts +++ b/arch/powerpc/boot/dts/mpc8379_mds.dts @@ -157,6 +157,41 @@ mode = "cpu"; }; + dma@82a8 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,mpc8379-dma", "fsl,elo-dma"; + reg = <0x82a8 4>; + ranges = <0 0x8100 0x1a8>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + cell-index = <0>; + dma-channel@0 { + compatible = "fsl,mpc8379-dma-channel", "fsl,elo-dma-channel"; + reg = <0 0x80>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + }; + dma-channel@80 { + compatible = "fsl,mpc8379-dma-channel", "fsl,elo-dma-channel"; + reg = <0x80 0x80>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + }; + dma-channel@100 { + compatible = "fsl,mpc8379-dma-channel", "fsl,elo-dma-channel"; + reg = <0x100 0x80>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + }; + dma-channel@180 { + compatible = "fsl,mpc8379-dma-channel", "fsl,elo-dma-channel"; + reg = <0x180 0x28>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + }; + }; + usb@23000 { compatible = "fsl-usb2-dr"; reg = <0x23000 0x1000>; diff --git a/arch/powerpc/boot/dts/mpc8379_rdb.dts b/arch/powerpc/boot/dts/mpc8379_rdb.dts index c11ceb7..9d636e3 100644 --- a/arch/powerpc/boot/dts/mpc8379_rdb.dts +++ b/arch/powerpc/boot/dts/mpc8379_rdb.dts @@ -143,6 +143,41 @@ mode = "cpu"; }; + dma@82a8 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,mpc8379-dma", "fsl,elo-dma"; + reg = <0x82a8 4>; + ranges = <0 0x8100 0x1a8>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + cell-index = <0>; + dma-channel@0 { + compatible = "fsl,mpc8379-dma-channel", "fsl,elo-dma-channel"; + reg = <0 0x80>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + }; + dma-channel@80 { + compatible = "fsl,mpc8379-dma-channel", "fsl,elo-dma-channel"; + reg = <0x80 0x80>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + }; + dma-channel@100 { + compatible = "fsl,mpc8379-dma-channel", "fsl,elo-dma-channel"; + reg = <0x100 0x80>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + }; + dma-channel@180 { + compatible = "fsl,mpc8379-dma-channel", "fsl,elo-dma-channel"; + reg = <0x180 0x28>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + }; + }; + usb@23000 { compatible = "fsl-usb2-dr"; reg = <0x23000 0x1000>; diff --git a/arch/powerpc/boot/dts/mpc8540ads.dts b/arch/powerpc/boot/dts/mpc8540ads.dts index 79881a1..f2273a8 100644 --- a/arch/powerpc/boot/dts/mpc8540ads.dts +++ b/arch/powerpc/boot/dts/mpc8540ads.dts @@ -84,6 +84,47 @@ dfsrr; }; + dma@21300 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,mpc8540-dma", "fsl,eloplus-dma"; + reg = <0x21300 0x4>; + ranges = <0x0 0x21100 0x200>; + cell-index = <0>; + dma-channel@0 { + compatible = "fsl,mpc8540-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x0 0x80>; + cell-index = <0>; + interrupt-parent = <&mpic>; + interrupts = <20 2>; + }; + dma-channel@80 { + compatible = "fsl,mpc8540-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x80 0x80>; + cell-index = <1>; + interrupt-parent = <&mpic>; + interrupts = <21 2>; + }; + dma-channel@100 { + compatible = "fsl,mpc8540-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x100 0x80>; + cell-index = <2>; + interrupt-parent = <&mpic>; + interrupts = <22 2>; + }; + dma-channel@180 { + compatible = "fsl,mpc8540-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x180 0x80>; + cell-index = <3>; + interrupt-parent = <&mpic>; + interrupts = <23 2>; + }; + }; + mdio@24520 { #address-cells = <1>; #size-cells = <0>; diff --git a/arch/powerpc/boot/dts/mpc8541cds.dts b/arch/powerpc/boot/dts/mpc8541cds.dts index 66192aa..21ad71b 100644 --- a/arch/powerpc/boot/dts/mpc8541cds.dts +++ b/arch/powerpc/boot/dts/mpc8541cds.dts @@ -84,6 +84,47 @@ dfsrr; }; + dma@21300 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,mpc8541-dma", "fsl,eloplus-dma"; + reg = <0x21300 0x4>; + ranges = <0x0 0x21100 0x200>; + cell-index = <0>; + dma-channel@0 { + compatible = "fsl,mpc8541-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x0 0x80>; + cell-index = <0>; + interrupt-parent = <&mpic>; + interrupts = <20 2>; + }; + dma-channel@80 { + compatible = "fsl,mpc8541-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x80 0x80>; + cell-index = <1>; + interrupt-parent = <&mpic>; + interrupts = <21 2>; + }; + dma-channel@100 { + compatible = "fsl,mpc8541-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x100 0x80>; + cell-index = <2>; + interrupt-parent = <&mpic>; + interrupts = <22 2>; + }; + dma-channel@180 { + compatible = "fsl,mpc8541-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x180 0x80>; + cell-index = <3>; + interrupt-parent = <&mpic>; + interrupts = <23 2>; + }; + }; + mdio@24520 { #address-cells = <1>; #size-cells = <0>; diff --git a/arch/powerpc/boot/dts/mpc8548cds.dts b/arch/powerpc/boot/dts/mpc8548cds.dts index 205598d..621388d 100644 --- a/arch/powerpc/boot/dts/mpc8548cds.dts +++ b/arch/powerpc/boot/dts/mpc8548cds.dts @@ -100,6 +100,47 @@ dfsrr; }; + dma@21300 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,mpc8548-dma", "fsl,eloplus-dma"; + reg = <0x21300 0x4>; + ranges = <0x0 0x21100 0x200>; + cell-index = <0>; + dma-channel@0 { + compatible = "fsl,mpc8548-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x0 0x80>; + cell-index = <0>; + interrupt-parent = <&mpic>; + interrupts = <20 2>; + }; + dma-channel@80 { + compatible = "fsl,mpc8548-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x80 0x80>; + cell-index = <1>; + interrupt-parent = <&mpic>; + interrupts = <21 2>; + }; + dma-channel@100 { + compatible = "fsl,mpc8548-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x100 0x80>; + cell-index = <2>; + interrupt-parent = <&mpic>; + interrupts = <22 2>; + }; + dma-channel@180 { + compatible = "fsl,mpc8548-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x180 0x80>; + cell-index = <3>; + interrupt-parent = <&mpic>; + interrupts = <23 2>; + }; + }; + mdio@24520 { #address-cells = <1>; #size-cells = <0>; diff --git a/arch/powerpc/boot/dts/mpc8555cds.dts b/arch/powerpc/boot/dts/mpc8555cds.dts index 7c9d0b1..6fc8059 100644 --- a/arch/powerpc/boot/dts/mpc8555cds.dts +++ b/arch/powerpc/boot/dts/mpc8555cds.dts @@ -84,6 +84,47 @@ dfsrr; }; + dma@21300 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,mpc8555-dma", "fsl,eloplus-dma"; + reg = <0x21300 0x4>; + ranges = <0x0 0x21100 0x200>; + cell-index = <0>; + dma-channel@0 { + compatible = "fsl,mpc8555-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x0 0x80>; + cell-index = <0>; + interrupt-parent = <&mpic>; + interrupts = <20 2>; + }; + dma-channel@80 { + compatible = "fsl,mpc8555-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x80 0x80>; + cell-index = <1>; + interrupt-parent = <&mpic>; + interrupts = <21 2>; + }; + dma-channel@100 { + compatible = "fsl,mpc8555-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x100 0x80>; + cell-index = <2>; + interrupt-parent = <&mpic>; + interrupts = <22 2>; + }; + dma-channel@180 { + compatible = "fsl,mpc8555-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x180 0x80>; + cell-index = <3>; + interrupt-parent = <&mpic>; + interrupts = <23 2>; + }; + }; + mdio@24520 { #address-cells = <1>; #size-cells = <0>; diff --git a/arch/powerpc/boot/dts/mpc8560ads.dts b/arch/powerpc/boot/dts/mpc8560ads.dts index 5d9f3c4..ba8159d 100644 --- a/arch/powerpc/boot/dts/mpc8560ads.dts +++ b/arch/powerpc/boot/dts/mpc8560ads.dts @@ -73,6 +73,47 @@ interrupts = <16 2>; }; + dma@21300 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,mpc8560-dma", "fsl,eloplus-dma"; + reg = <0x21300 0x4>; + ranges = <0x0 0x21100 0x200>; + cell-index = <0>; + dma-channel@0 { + compatible = "fsl,mpc8560-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x0 0x80>; + cell-index = <0>; + interrupt-parent = <&mpic>; + interrupts = <20 2>; + }; + dma-channel@80 { + compatible = "fsl,mpc8560-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x80 0x80>; + cell-index = <1>; + interrupt-parent = <&mpic>; + interrupts = <21 2>; + }; + dma-channel@100 { + compatible = "fsl,mpc8560-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x100 0x80>; + cell-index = <2>; + interrupt-parent = <&mpic>; + interrupts = <22 2>; + }; + dma-channel@180 { + compatible = "fsl,mpc8560-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x180 0x80>; + cell-index = <3>; + interrupt-parent = <&mpic>; + interrupts = <23 2>; + }; + }; + mdio@24520 { #address-cells = <1>; #size-cells = <0>; diff --git a/arch/powerpc/boot/dts/mpc8568mds.dts b/arch/powerpc/boot/dts/mpc8568mds.dts index d7af8db..be9a289 100644 --- a/arch/powerpc/boot/dts/mpc8568mds.dts +++ b/arch/powerpc/boot/dts/mpc8568mds.dts @@ -107,6 +107,47 @@ dfsrr; }; + dma@21300 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,mpc8568-dma", "fsl,eloplus-dma"; + reg = <0x21300 0x4>; + ranges = <0x0 0x21100 0x200>; + cell-index = <0>; + dma-channel@0 { + compatible = "fsl,mpc8568-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x0 0x80>; + cell-index = <0>; + interrupt-parent = <&mpic>; + interrupts = <20 2>; + }; + dma-channel@80 { + compatible = "fsl,mpc8568-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x80 0x80>; + cell-index = <1>; + interrupt-parent = <&mpic>; + interrupts = <21 2>; + }; + dma-channel@100 { + compatible = "fsl,mpc8568-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x100 0x80>; + cell-index = <2>; + interrupt-parent = <&mpic>; + interrupts = <22 2>; + }; + dma-channel@180 { + compatible = "fsl,mpc8568-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x180 0x80>; + cell-index = <3>; + interrupt-parent = <&mpic>; + interrupts = <23 2>; + }; + }; + mdio@24520 { #address-cells = <1>; #size-cells = <0>; diff --git a/arch/powerpc/boot/dts/mpc8572ds.dts b/arch/powerpc/boot/dts/mpc8572ds.dts index a444e6a..cb06325 100644 --- a/arch/powerpc/boot/dts/mpc8572ds.dts +++ b/arch/powerpc/boot/dts/mpc8572ds.dts @@ -117,6 +117,88 @@ dfsrr; }; + dma@c300 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma"; + reg = <0xc300 0x4>; + ranges = <0x0 0xc100 0x200>; + cell-index = <1>; + dma-channel@0 { + compatible = "fsl,mpc8572-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x0 0x80>; + cell-index = <0>; + interrupt-parent = <&mpic>; + interrupts = <76 2>; + }; + dma-channel@80 { + compatible = "fsl,mpc8572-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x80 0x80>; + cell-index = <1>; + interrupt-parent = <&mpic>; + interrupts = <77 2>; + }; + dma-channel@100 { + compatible = "fsl,mpc8572-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x100 0x80>; + cell-index = <2>; + interrupt-parent = <&mpic>; + interrupts = <78 2>; + }; + dma-channel@180 { + compatible = "fsl,mpc8572-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x180 0x80>; + cell-index = <3>; + interrupt-parent = <&mpic>; + interrupts = <79 2>; + }; + }; + + dma@21300 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma"; + reg = <0x21300 0x4>; + ranges = <0x0 0x21100 0x200>; + cell-index = <0>; + dma-channel@0 { + compatible = "fsl,mpc8572-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x0 0x80>; + cell-index = <0>; + interrupt-parent = <&mpic>; + interrupts = <20 2>; + }; + dma-channel@80 { + compatible = "fsl,mpc8572-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x80 0x80>; + cell-index = <1>; + interrupt-parent = <&mpic>; + interrupts = <21 2>; + }; + dma-channel@100 { + compatible = "fsl,mpc8572-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x100 0x80>; + cell-index = <2>; + interrupt-parent = <&mpic>; + interrupts = <22 2>; + }; + dma-channel@180 { + compatible = "fsl,mpc8572-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x180 0x80>; + cell-index = <3>; + interrupt-parent = <&mpic>; + interrupts = <23 2>; + }; + }; + mdio@24520 { #address-cells = <1>; #size-cells = <0>; diff --git a/arch/powerpc/boot/dts/mpc8641_hpcn.dts b/arch/powerpc/boot/dts/mpc8641_hpcn.dts index 14f718d..ae08761 100644 --- a/arch/powerpc/boot/dts/mpc8641_hpcn.dts +++ b/arch/powerpc/boot/dts/mpc8641_hpcn.dts @@ -134,6 +134,47 @@ dfsrr; }; + dma@21300 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,mpc8641-dma", "fsl,eloplus-dma"; + reg = <0x21300 0x4>; + ranges = <0x0 0x21100 0x200>; + cell-index = <0>; + dma-channel@0 { + compatible = "fsl,mpc8641-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x0 0x80>; + cell-index = <0>; + interrupt-parent = <&mpic>; + interrupts = <20 2>; + }; + dma-channel@80 { + compatible = "fsl,mpc8641-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x80 0x80>; + cell-index = <1>; + interrupt-parent = <&mpic>; + interrupts = <21 2>; + }; + dma-channel@100 { + compatible = "fsl,mpc8641-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x100 0x80>; + cell-index = <2>; + interrupt-parent = <&mpic>; + interrupts = <22 2>; + }; + dma-channel@180 { + compatible = "fsl,mpc8641-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x180 0x80>; + cell-index = <3>; + interrupt-parent = <&mpic>; + interrupts = <23 2>; + }; + }; + mdio@24520 { #address-cells = <1>; #size-cells = <0>; diff --git a/arch/powerpc/boot/dts/sbc8349.dts b/arch/powerpc/boot/dts/sbc8349.dts index 3839d4b..5b76bb2 100644 --- a/arch/powerpc/boot/dts/sbc8349.dts +++ b/arch/powerpc/boot/dts/sbc8349.dts @@ -95,6 +95,41 @@ mode = "cpu"; }; + dma@82a8 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,mpc8349-dma", "fsl,elo-dma"; + reg = <0x82a8 4>; + ranges = <0 0x8100 0x1a8>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + cell-index = <0>; + dma-channel@0 { + compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel"; + reg = <0 0x80>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + }; + dma-channel@80 { + compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel"; + reg = <0x80 0x80>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + }; + dma-channel@100 { + compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel"; + reg = <0x100 0x80>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + }; + dma-channel@180 { + compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel"; + reg = <0x180 0x28>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + }; + }; + /* phy type (ULPI or SERIAL) are only types supported for MPH */ /* port = 0 or 1 */ usb@22000 { diff --git a/arch/powerpc/boot/dts/sbc8548.dts b/arch/powerpc/boot/dts/sbc8548.dts index d252e38..21cbacb 100644 --- a/arch/powerpc/boot/dts/sbc8548.dts +++ b/arch/powerpc/boot/dts/sbc8548.dts @@ -193,6 +193,47 @@ dfsrr; }; + dma@21300 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,mpc8548-dma", "fsl,eloplus-dma"; + reg = <0x21300 0x4>; + ranges = <0x0 0x21100 0x200>; + cell-index = <0>; + dma-channel@0 { + compatible = "fsl,mpc8548-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x0 0x80>; + cell-index = <0>; + interrupt-parent = <&mpic>; + interrupts = <20 2>; + }; + dma-channel@80 { + compatible = "fsl,mpc8548-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x80 0x80>; + cell-index = <1>; + interrupt-parent = <&mpic>; + interrupts = <21 2>; + }; + dma-channel@100 { + compatible = "fsl,mpc8548-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x100 0x80>; + cell-index = <2>; + interrupt-parent = <&mpic>; + interrupts = <22 2>; + }; + dma-channel@180 { + compatible = "fsl,mpc8548-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x180 0x80>; + cell-index = <3>; + interrupt-parent = <&mpic>; + interrupts = <23 2>; + }; + }; + mdio@24520 { #address-cells = <1>; #size-cells = <0>; diff --git a/arch/powerpc/boot/dts/sbc8560.dts b/arch/powerpc/boot/dts/sbc8560.dts index e556c5a..db3632e 100644 --- a/arch/powerpc/boot/dts/sbc8560.dts +++ b/arch/powerpc/boot/dts/sbc8560.dts @@ -98,6 +98,47 @@ dfsrr; }; + dma@21300 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,mpc8560-dma", "fsl,eloplus-dma"; + reg = <0x21300 0x4>; + ranges = <0x0 0x21100 0x200>; + cell-index = <0>; + dma-channel@0 { + compatible = "fsl,mpc8560-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x0 0x80>; + cell-index = <0>; + interrupt-parent = <&mpic>; + interrupts = <20 2>; + }; + dma-channel@80 { + compatible = "fsl,mpc8560-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x80 0x80>; + cell-index = <1>; + interrupt-parent = <&mpic>; + interrupts = <21 2>; + }; + dma-channel@100 { + compatible = "fsl,mpc8560-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x100 0x80>; + cell-index = <2>; + interrupt-parent = <&mpic>; + interrupts = <22 2>; + }; + dma-channel@180 { + compatible = "fsl,mpc8560-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x180 0x80>; + cell-index = <3>; + interrupt-parent = <&mpic>; + interrupts = <23 2>; + }; + }; + mdio@24520 { #address-cells = <1>; #size-cells = <0>; diff --git a/arch/powerpc/boot/dts/sbc8641d.dts b/arch/powerpc/boot/dts/sbc8641d.dts index 3eebeec..9652456 100644 --- a/arch/powerpc/boot/dts/sbc8641d.dts +++ b/arch/powerpc/boot/dts/sbc8641d.dts @@ -151,6 +151,47 @@ dfsrr; }; + dma@21300 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,mpc8641-dma", "fsl,eloplus-dma"; + reg = <0x21300 0x4>; + ranges = <0x0 0x21100 0x200>; + cell-index = <0>; + dma-channel@0 { + compatible = "fsl,mpc8641-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x0 0x80>; + cell-index = <0>; + interrupt-parent = <&mpic>; + interrupts = <20 2>; + }; + dma-channel@80 { + compatible = "fsl,mpc8641-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x80 0x80>; + cell-index = <1>; + interrupt-parent = <&mpic>; + interrupts = <21 2>; + }; + dma-channel@100 { + compatible = "fsl,mpc8641-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x100 0x80>; + cell-index = <2>; + interrupt-parent = <&mpic>; + interrupts = <22 2>; + }; + dma-channel@180 { + compatible = "fsl,mpc8641-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x180 0x80>; + cell-index = <3>; + interrupt-parent = <&mpic>; + interrupts = <23 2>; + }; + }; + mdio@24520 { #address-cells = <1>; #size-cells = <0>; diff --git a/arch/powerpc/boot/dts/stx_gp3_8560.dts b/arch/powerpc/boot/dts/stx_gp3_8560.dts index 1e61283..fcd1db6 100644 --- a/arch/powerpc/boot/dts/stx_gp3_8560.dts +++ b/arch/powerpc/boot/dts/stx_gp3_8560.dts @@ -83,6 +83,47 @@ dfsrr; }; + dma@21300 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,mpc8560-dma", "fsl,eloplus-dma"; + reg = <0x21300 0x4>; + ranges = <0x0 0x21100 0x200>; + cell-index = <0>; + dma-channel@0 { + compatible = "fsl,mpc8560-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x0 0x80>; + cell-index = <0>; + interrupt-parent = <&mpic>; + interrupts = <20 2>; + }; + dma-channel@80 { + compatible = "fsl,mpc8560-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x80 0x80>; + cell-index = <1>; + interrupt-parent = <&mpic>; + interrupts = <21 2>; + }; + dma-channel@100 { + compatible = "fsl,mpc8560-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x100 0x80>; + cell-index = <2>; + interrupt-parent = <&mpic>; + interrupts = <22 2>; + }; + dma-channel@180 { + compatible = "fsl,mpc8560-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x180 0x80>; + cell-index = <3>; + interrupt-parent = <&mpic>; + interrupts = <23 2>; + }; + }; + mdio@24520 { #address-cells = <1>; #size-cells = <0>; diff --git a/arch/powerpc/boot/dts/tqm8540.dts b/arch/powerpc/boot/dts/tqm8540.dts index 3504db3..e1d260b 100644 --- a/arch/powerpc/boot/dts/tqm8540.dts +++ b/arch/powerpc/boot/dts/tqm8540.dts @@ -90,6 +90,47 @@ }; }; + dma@21300 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,mpc8540-dma", "fsl,eloplus-dma"; + reg = <0x21300 0x4>; + ranges = <0x0 0x21100 0x200>; + cell-index = <0>; + dma-channel@0 { + compatible = "fsl,mpc8540-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x0 0x80>; + cell-index = <0>; + interrupt-parent = <&mpic>; + interrupts = <20 2>; + }; + dma-channel@80 { + compatible = "fsl,mpc8540-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x80 0x80>; + cell-index = <1>; + interrupt-parent = <&mpic>; + interrupts = <21 2>; + }; + dma-channel@100 { + compatible = "fsl,mpc8540-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x100 0x80>; + cell-index = <2>; + interrupt-parent = <&mpic>; + interrupts = <22 2>; + }; + dma-channel@180 { + compatible = "fsl,mpc8540-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x180 0x80>; + cell-index = <3>; + interrupt-parent = <&mpic>; + interrupts = <23 2>; + }; + }; + mdio@24520 { #address-cells = <1>; #size-cells = <0>; diff --git a/arch/powerpc/boot/dts/tqm8541.dts b/arch/powerpc/boot/dts/tqm8541.dts index 8241ae3..d083a64 100644 --- a/arch/powerpc/boot/dts/tqm8541.dts +++ b/arch/powerpc/boot/dts/tqm8541.dts @@ -89,6 +89,47 @@ }; }; + dma@21300 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,mpc8541-dma", "fsl,eloplus-dma"; + reg = <0x21300 0x4>; + ranges = <0x0 0x21100 0x200>; + cell-index = <0>; + dma-channel@0 { + compatible = "fsl,mpc8541-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x0 0x80>; + cell-index = <0>; + interrupt-parent = <&mpic>; + interrupts = <20 2>; + }; + dma-channel@80 { + compatible = "fsl,mpc8541-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x80 0x80>; + cell-index = <1>; + interrupt-parent = <&mpic>; + interrupts = <21 2>; + }; + dma-channel@100 { + compatible = "fsl,mpc8541-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x100 0x80>; + cell-index = <2>; + interrupt-parent = <&mpic>; + interrupts = <22 2>; + }; + dma-channel@180 { + compatible = "fsl,mpc8541-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x180 0x80>; + cell-index = <3>; + interrupt-parent = <&mpic>; + interrupts = <23 2>; + }; + }; + mdio@24520 { #address-cells = <1>; #size-cells = <0>; diff --git a/arch/powerpc/boot/dts/tqm8548-bigflash.dts b/arch/powerpc/boot/dts/tqm8548-bigflash.dts index d8a1b19..64d2d5b 100644 --- a/arch/powerpc/boot/dts/tqm8548-bigflash.dts +++ b/arch/powerpc/boot/dts/tqm8548-bigflash.dts @@ -96,6 +96,47 @@ dfsrr; }; + dma@21300 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,mpc8548-dma", "fsl,eloplus-dma"; + reg = <0x21300 0x4>; + ranges = <0x0 0x21100 0x200>; + cell-index = <0>; + dma-channel@0 { + compatible = "fsl,mpc8548-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x0 0x80>; + cell-index = <0>; + interrupt-parent = <&mpic>; + interrupts = <20 2>; + }; + dma-channel@80 { + compatible = "fsl,mpc8548-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x80 0x80>; + cell-index = <1>; + interrupt-parent = <&mpic>; + interrupts = <21 2>; + }; + dma-channel@100 { + compatible = "fsl,mpc8548-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x100 0x80>; + cell-index = <2>; + interrupt-parent = <&mpic>; + interrupts = <22 2>; + }; + dma-channel@180 { + compatible = "fsl,mpc8548-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x180 0x80>; + cell-index = <3>; + interrupt-parent = <&mpic>; + interrupts = <23 2>; + }; + }; + mdio@24520 { #address-cells = <1>; #size-cells = <0>; diff --git a/arch/powerpc/boot/dts/tqm8548.dts b/arch/powerpc/boot/dts/tqm8548.dts index e80b450..13cd728 100644 --- a/arch/powerpc/boot/dts/tqm8548.dts +++ b/arch/powerpc/boot/dts/tqm8548.dts @@ -96,6 +96,47 @@ dfsrr; }; + dma@21300 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,mpc8548-dma", "fsl,eloplus-dma"; + reg = <0x21300 0x4>; + ranges = <0x0 0x21100 0x200>; + cell-index = <0>; + dma-channel@0 { + compatible = "fsl,mpc8548-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x0 0x80>; + cell-index = <0>; + interrupt-parent = <&mpic>; + interrupts = <20 2>; + }; + dma-channel@80 { + compatible = "fsl,mpc8548-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x80 0x80>; + cell-index = <1>; + interrupt-parent = <&mpic>; + interrupts = <21 2>; + }; + dma-channel@100 { + compatible = "fsl,mpc8548-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x100 0x80>; + cell-index = <2>; + interrupt-parent = <&mpic>; + interrupts = <22 2>; + }; + dma-channel@180 { + compatible = "fsl,mpc8548-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x180 0x80>; + cell-index = <3>; + interrupt-parent = <&mpic>; + interrupts = <23 2>; + }; + }; + mdio@24520 { #address-cells = <1>; #size-cells = <0>; diff --git a/arch/powerpc/boot/dts/tqm8555.dts b/arch/powerpc/boot/dts/tqm8555.dts index 5a57cef..96b0b94 100644 --- a/arch/powerpc/boot/dts/tqm8555.dts +++ b/arch/powerpc/boot/dts/tqm8555.dts @@ -89,6 +89,47 @@ }; }; + dma@21300 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,mpc8555-dma", "fsl,eloplus-dma"; + reg = <0x21300 0x4>; + ranges = <0x0 0x21100 0x200>; + cell-index = <0>; + dma-channel@0 { + compatible = "fsl,mpc8555-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x0 0x80>; + cell-index = <0>; + interrupt-parent = <&mpic>; + interrupts = <20 2>; + }; + dma-channel@80 { + compatible = "fsl,mpc8555-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x80 0x80>; + cell-index = <1>; + interrupt-parent = <&mpic>; + interrupts = <21 2>; + }; + dma-channel@100 { + compatible = "fsl,mpc8555-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x100 0x80>; + cell-index = <2>; + interrupt-parent = <&mpic>; + interrupts = <22 2>; + }; + dma-channel@180 { + compatible = "fsl,mpc8555-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x180 0x80>; + cell-index = <3>; + interrupt-parent = <&mpic>; + interrupts = <23 2>; + }; + }; + mdio@24520 { #address-cells = <1>; #size-cells = <0>; diff --git a/arch/powerpc/boot/dts/tqm8560.dts b/arch/powerpc/boot/dts/tqm8560.dts index 6794882..3fe3520 100644 --- a/arch/powerpc/boot/dts/tqm8560.dts +++ b/arch/powerpc/boot/dts/tqm8560.dts @@ -91,6 +91,47 @@ }; }; + dma@21300 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,mpc8560-dma", "fsl,eloplus-dma"; + reg = <0x21300 0x4>; + ranges = <0x0 0x21100 0x200>; + cell-index = <0>; + dma-channel@0 { + compatible = "fsl,mpc8560-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x0 0x80>; + cell-index = <0>; + interrupt-parent = <&mpic>; + interrupts = <20 2>; + }; + dma-channel@80 { + compatible = "fsl,mpc8560-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x80 0x80>; + cell-index = <1>; + interrupt-parent = <&mpic>; + interrupts = <21 2>; + }; + dma-channel@100 { + compatible = "fsl,mpc8560-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x100 0x80>; + cell-index = <2>; + interrupt-parent = <&mpic>; + interrupts = <22 2>; + }; + dma-channel@180 { + compatible = "fsl,mpc8560-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x180 0x80>; + cell-index = <3>; + interrupt-parent = <&mpic>; + interrupts = <23 2>; + }; + }; + mdio@24520 { #address-cells = <1>; #size-cells = <0>; -- cgit v1.1 From 9b09c6d909dfd8de96b99b9b9c808b94b0a71614 Mon Sep 17 00:00:00 2001 From: Tony Breeds Date: Tue, 24 Jun 2008 14:20:29 +1000 Subject: powerpc: Change the default link address for pSeries zImage kernels Currently we set the start of the .text section to be 4Mb for pSeries. In situations where the zImage is > 8Mb we'll fail to boot (due to overlapping with OF). Move .text in a zImage from 4MB to 64MB (well past OF). We still will not be able to load large zImage unless we also move OF, to that end, add a note to the zImage ELF to move OF to 32Mb. If this is the very first kernel booted then we'll need to move OF manually by setting real-base. Signed-off-by: Tony Breeds Signed-off-by: Paul Mackerras --- arch/powerpc/boot/addnote.c | 2 +- arch/powerpc/boot/oflib.c | 15 +++++++++++++-- arch/powerpc/boot/wrapper | 14 ++++++++++++-- arch/powerpc/boot/zImage.coff.lds.S | 1 - arch/powerpc/boot/zImage.lds.S | 1 - 5 files changed, 26 insertions(+), 7 deletions(-) (limited to 'arch/powerpc/boot') diff --git a/arch/powerpc/boot/addnote.c b/arch/powerpc/boot/addnote.c index 8041a98..b1e5611 100644 --- a/arch/powerpc/boot/addnote.c +++ b/arch/powerpc/boot/addnote.c @@ -25,7 +25,7 @@ char arch[] = "PowerPC"; #define N_DESCR 6 unsigned int descr[N_DESCR] = { 0xffffffff, /* real-mode = true */ - 0x00c00000, /* real-base, i.e. where we expect OF to be */ + 0x02000000, /* real-base, i.e. where we expect OF to be */ 0xffffffff, /* real-size */ 0xffffffff, /* virt-base */ 0xffffffff, /* virt-size */ diff --git a/arch/powerpc/boot/oflib.c b/arch/powerpc/boot/oflib.c index 95b8fd6..b0ec9cf 100644 --- a/arch/powerpc/boot/oflib.c +++ b/arch/powerpc/boot/oflib.c @@ -168,8 +168,19 @@ void *of_claim(unsigned long virt, unsigned long size, unsigned long align) void *of_vmlinux_alloc(unsigned long size) { - void *p = malloc(size); - + unsigned long start = (unsigned long)_start, end = (unsigned long)_end; + void *addr; + void *p; + + /* With some older POWER4 firmware we need to claim the area the kernel + * will reside in. Newer firmwares don't need this so we just ignore + * the return value. + */ + addr = of_claim(start, end - start, 0); + printf("Trying to claim from 0x%lx to 0x%lx (0x%lx) got %p\r\n", + start, end, end - start, addr); + + p = malloc(size); if (!p) fatal("Can't allocate memory for kernel image!\n\r"); diff --git a/arch/powerpc/boot/wrapper b/arch/powerpc/boot/wrapper index cb87a01..df2358e 100755 --- a/arch/powerpc/boot/wrapper +++ b/arch/powerpc/boot/wrapper @@ -138,14 +138,20 @@ objflags=-S tmp=$tmpdir/zImage.$$.o ksection=.kernel:vmlinux.strip isection=.kernel:initrd +link_address='0x400000' case "$platform" in -pmac|pseries|chrp) +pseries) + platformo=$object/of.o + link_address='0x4000000' + ;; +pmac|chrp) platformo=$object/of.o ;; coff) platformo=$object/of.o lds=$object/zImage.coff.lds + link_address='0x500000' ;; miboot|uboot) # miboot and U-boot want just the bare bits, not an ELF binary @@ -190,6 +196,7 @@ ps3) objflags="-O binary --set-section-flags=.bss=contents,alloc,load,data" ksection=.kernel:vmlinux.bin isection=.kernel:initrd + link_address='' ;; ep88xc|ep405|ep8248e) platformo="$object/fixed-head.o $object/$platform.o" @@ -272,7 +279,10 @@ if [ -n "$dtb" ]; then fi if [ "$platform" != "miboot" ]; then - ${CROSS}ld -m elf32ppc -T $lds -o "$ofile" \ + if [ -n "$link_address" ] ; then + text_start="-Ttext $link_address --defsym _start=$link_address" + fi + ${CROSS}ld -m elf32ppc -T $lds $text_start -o "$ofile" \ $platformo $tmp $object/wrapper.a rm $tmp fi diff --git a/arch/powerpc/boot/zImage.coff.lds.S b/arch/powerpc/boot/zImage.coff.lds.S index fe87a90..856dc78 100644 --- a/arch/powerpc/boot/zImage.coff.lds.S +++ b/arch/powerpc/boot/zImage.coff.lds.S @@ -3,7 +3,6 @@ ENTRY(_zimage_start_opd) EXTERN(_zimage_start_opd) SECTIONS { - . = (5*1024*1024); _start = .; .text : { diff --git a/arch/powerpc/boot/zImage.lds.S b/arch/powerpc/boot/zImage.lds.S index f6e380f..0962d62 100644 --- a/arch/powerpc/boot/zImage.lds.S +++ b/arch/powerpc/boot/zImage.lds.S @@ -3,7 +3,6 @@ ENTRY(_zimage_start) EXTERN(_zimage_start) SECTIONS { - . = (4*1024*1024); _start = .; .text : { -- cgit v1.1 From 9d4ae9fc92f347b93b42c9c0ccde7138c1202e36 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Thu, 26 Jun 2008 18:58:11 +1000 Subject: powerpc/bootwrapper: Pad .dtb by default Since most bootloaders or wrappers tend to update or add some information to the .dtb they a handled they need some working space to do that in. By default add 1K of padding via a default setting of DTS_FLAGS. Signed-off-by: Kumar Gala Signed-off-by: Paul Mackerras --- arch/powerpc/boot/Makefile | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/powerpc/boot') diff --git a/arch/powerpc/boot/Makefile b/arch/powerpc/boot/Makefile index 4721baf..751a6e6 100644 --- a/arch/powerpc/boot/Makefile +++ b/arch/powerpc/boot/Makefile @@ -35,6 +35,8 @@ endif BOOTCFLAGS += -I$(obj) -I$(srctree)/$(obj) -I$(srctree)/$(src)/libfdt +DTS_FLAGS ?= -p 1024 + $(obj)/4xx.o: BOOTCFLAGS += -mcpu=405 $(obj)/ebony.o: BOOTCFLAGS += -mcpu=405 $(obj)/cuboot-taishan.o: BOOTCFLAGS += -mcpu=405 -- cgit v1.1 From dc568ec4906ac2478e2d692adc6b12fbb6e4657e Mon Sep 17 00:00:00 2001 From: John Linn Date: Tue, 1 Jul 2008 16:02:54 -0700 Subject: powerpc/virtex: add dts file for ML507 reference design This new file adds support for the ML507 reference design. The ML507 uses the Virtex 5 FXT FPGA which embeds a ppc440 core. Signed-off-by: John Linn Signed-off-by: Grant Likely --- arch/powerpc/boot/dts/virtex440-ml507.dts | 238 ++++++++++++++++++++++++++++++ 1 file changed, 238 insertions(+) create mode 100644 arch/powerpc/boot/dts/virtex440-ml507.dts (limited to 'arch/powerpc/boot') diff --git a/arch/powerpc/boot/dts/virtex440-ml507.dts b/arch/powerpc/boot/dts/virtex440-ml507.dts new file mode 100644 index 0000000..f1b3344 --- /dev/null +++ b/arch/powerpc/boot/dts/virtex440-ml507.dts @@ -0,0 +1,238 @@ +/* + * This file supports the Xilinx ML507 board with the 440 processor. + * A reference design for the FPGA is provided at http://git.xilinx.com. + * + * (C) Copyright 2008 Xilinx, Inc. + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +/ { + #address-cells = <1>; + #size-cells = <1>; + compatible = "xlnx,virtex440"; + dcr-parent = <&ppc440_virtex5_0>; + model = "testing"; + chosen { + bootargs = "console=ttyS0 ip=on root=/dev/ram"; + linux,stdout-path = "/plb@0/serial@d0000000"; + } ; + cpus { + #address-cells = <1>; + #cpus = <1>; + #size-cells = <0>; + ppc440_virtex5_0: cpu@0 { + clock-frequency = <17d78400>; + compatible = "PowerPC,440", "ibm,ppc440"; + d-cache-line-size = <20>; + d-cache-size = <8000>; + dcr-access-method = "native"; + dcr-controller ; + device_type = "cpu"; + i-cache-line-size = <20>; + i-cache-size = <8000>; + model = "PowerPC,440"; + reg = <0>; + timebase-frequency = <17d78400>; + xlnx,apu-control = <1>; + xlnx,apu-udi-0 = ; + xlnx,apu-udi-1 = ; + xlnx,apu-udi-10 = <0>; + xlnx,apu-udi-11 = <0>; + xlnx,apu-udi-12 = <0>; + xlnx,apu-udi-13 = <0>; + xlnx,apu-udi-14 = <0>; + xlnx,apu-udi-15 = <0>; + xlnx,apu-udi-2 = <0>; + xlnx,apu-udi-3 = <0>; + xlnx,apu-udi-4 = <0>; + xlnx,apu-udi-5 = <0>; + xlnx,apu-udi-6 = <0>; + xlnx,apu-udi-7 = <0>; + xlnx,apu-udi-8 = <0>; + xlnx,apu-udi-9 = <0>; + xlnx,dcr-autolock-enable = <1>; + xlnx,dcu-rd-ld-cache-plb-prio = <0>; + xlnx,dcu-rd-noncache-plb-prio = <0>; + xlnx,dcu-rd-touch-plb-prio = <0>; + xlnx,dcu-rd-urgent-plb-prio = <0>; + xlnx,dcu-wr-flush-plb-prio = <0>; + xlnx,dcu-wr-store-plb-prio = <0>; + xlnx,dcu-wr-urgent-plb-prio = <0>; + xlnx,dma0-control = <0>; + xlnx,dma0-plb-prio = <0>; + xlnx,dma0-rxchannelctrl = <1010000>; + xlnx,dma0-rxirqtimer = <3ff>; + xlnx,dma0-txchannelctrl = <1010000>; + xlnx,dma0-txirqtimer = <3ff>; + xlnx,dma1-control = <0>; + xlnx,dma1-plb-prio = <0>; + xlnx,dma1-rxchannelctrl = <1010000>; + xlnx,dma1-rxirqtimer = <3ff>; + xlnx,dma1-txchannelctrl = <1010000>; + xlnx,dma1-txirqtimer = <3ff>; + xlnx,dma2-control = <0>; + xlnx,dma2-plb-prio = <0>; + xlnx,dma2-rxchannelctrl = <1010000>; + xlnx,dma2-rxirqtimer = <3ff>; + xlnx,dma2-txchannelctrl = <1010000>; + xlnx,dma2-txirqtimer = <3ff>; + xlnx,dma3-control = <0>; + xlnx,dma3-plb-prio = <0>; + xlnx,dma3-rxchannelctrl = <1010000>; + xlnx,dma3-rxirqtimer = <3ff>; + xlnx,dma3-txchannelctrl = <1010000>; + xlnx,dma3-txirqtimer = <3ff>; + xlnx,endian-reset = <0>; + xlnx,generate-plb-timespecs = <1>; + xlnx,icu-rd-fetch-plb-prio = <0>; + xlnx,icu-rd-spec-plb-prio = <0>; + xlnx,icu-rd-touch-plb-prio = <0>; + xlnx,interconnect-imask = ; + xlnx,mplb-allow-lock-xfer = <1>; + xlnx,mplb-arb-mode = <0>; + xlnx,mplb-awidth = <20>; + xlnx,mplb-counter = <500>; + xlnx,mplb-dwidth = <80>; + xlnx,mplb-max-burst = <8>; + xlnx,mplb-native-dwidth = <80>; + xlnx,mplb-p2p = <0>; + xlnx,mplb-prio-dcur = <2>; + xlnx,mplb-prio-dcuw = <3>; + xlnx,mplb-prio-icu = <4>; + xlnx,mplb-prio-splb0 = <1>; + xlnx,mplb-prio-splb1 = <0>; + xlnx,mplb-read-pipe-enable = <1>; + xlnx,mplb-sync-tattribute = <0>; + xlnx,mplb-wdog-enable = <1>; + xlnx,mplb-write-pipe-enable = <1>; + xlnx,mplb-write-post-enable = <1>; + xlnx,num-dma = <1>; + xlnx,pir = ; + xlnx,ppc440mc-addr-base = <0>; + xlnx,ppc440mc-addr-high = <1fffffff>; + xlnx,ppc440mc-arb-mode = <0>; + xlnx,ppc440mc-bank-conflict-mask = ; + xlnx,ppc440mc-control = ; + xlnx,ppc440mc-max-burst = <8>; + xlnx,ppc440mc-prio-dcur = <2>; + xlnx,ppc440mc-prio-dcuw = <3>; + xlnx,ppc440mc-prio-icu = <4>; + xlnx,ppc440mc-prio-splb0 = <1>; + xlnx,ppc440mc-prio-splb1 = <0>; + xlnx,ppc440mc-row-conflict-mask = <3ffe00>; + xlnx,ppcdm-asyncmode = <0>; + xlnx,ppcds-asyncmode = <0>; + xlnx,user-reset = <0>; + DMA0: sdma@80 { + compatible = "xlnx,ll-dma-1.00.a"; + dcr-reg = < 80 11 >; + interrupt-parent = <&opb_intc_0>; + interrupts = < 5 2 6 2 >; + } ; + } ; + } ; + plb_v46_cfb_0: plb@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "xlnx,plb-v46-1.02.a"; + ranges ; + iic_bus: i2c@d0020000 { + compatible = "xlnx,xps-iic-2.00.a"; + interrupt-parent = <&opb_intc_0>; + interrupts = < 7 2 >; + reg = < d0020000 200 >; + xlnx,clk-freq = <5f5e100>; + xlnx,family = "virtex5"; + xlnx,gpo-width = <1>; + xlnx,iic-freq = <186a0>; + xlnx,scl-inertial-delay = <0>; + xlnx,sda-inertial-delay = <0>; + xlnx,ten-bit-adr = <0>; + } ; + leds_8bit: gpio@d0010200 { + compatible = "xlnx,xps-gpio-1.00.a"; + interrupt-parent = <&opb_intc_0>; + interrupts = < 1 2 >; + reg = < d0010200 200 >; + xlnx,all-inputs = <0>; + xlnx,all-inputs-2 = <0>; + xlnx,dout-default = <0>; + xlnx,dout-default-2 = <0>; + xlnx,family = "virtex5"; + xlnx,gpio-width = <8>; + xlnx,interrupt-present = <1>; + xlnx,is-bidir = <1>; + xlnx,is-bidir-2 = <1>; + xlnx,is-dual = <0>; + xlnx,tri-default = ; + xlnx,tri-default-2 = ; + } ; + ll_temac_0: xps-ll-temac@91200000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "xlnx,compound"; + ethernet@91200000 { + compatible = "xlnx,xps-ll-temac-1.01.a"; + device_type = "network"; + interrupt-parent = <&opb_intc_0>; + interrupts = < 4 2 >; + llink-connected = <&DMA0>; + local-mac-address = [ 02 00 00 00 00 00 ]; + reg = < 91200000 40 >; + xlnx,bus2core-clk-ratio = <1>; + xlnx,phy-type = <1>; + xlnx,phyaddr = <1>; + xlnx,rxcsum = <0>; + xlnx,rxfifo = <4000>; + xlnx,temac-type = <0>; + xlnx,txcsum = <0>; + xlnx,txfifo = <4000>; + } ; + } ; + opb_intc_0: interrupt-controller@d0020200 { + #interrupt-cells = <2>; + compatible = "xlnx,xps-intc-1.00.a"; + interrupt-controller ; + reg = < d0020200 20 >; + xlnx,num-intr-inputs = <8>; + } ; + plb_bram_if_cntlr_0: xps-bram-if-cntlr@ffff0000 { + compatible = "xlnx,xps-bram-if-cntlr-1.00.a"; + reg = < ffff0000 10000 >; + xlnx,family = "virtex5"; + } ; + plb_bram_if_cntlr_1: xps-bram-if-cntlr@eee00000 { + compatible = "xlnx,xps-bram-if-cntlr-1.00.a"; + reg = < eee00000 2000 >; + xlnx,family = "virtex5"; + } ; + rs232_uart_0: serial@d0000000 { + clock-frequency = <1312d00>; + compatible = "xlnx,xps-uart16550-2.00.a", "ns16550"; + current-speed = <2580>; + device_type = "serial"; + interrupt-parent = <&opb_intc_0>; + interrupts = < 0 2 >; + reg = < d0000000 2000 >; + reg-offset = <1003>; + reg-shift = <2>; + xlnx,family = "virtex5"; + xlnx,has-external-rclk = <0>; + xlnx,has-external-xin = <1>; + xlnx,is-a-16550 = <1>; + } ; + sysace_compactflash: sysace@d0030100 { + compatible = "xlnx,xps-sysace-1.00.a"; + reg = < d0030100 80 >; + xlnx,family = "virtex5"; + xlnx,mem-width = <10>; + } ; + } ; + ppc440mc_ddr2_0: memory@0 { + device_type = "memory"; + reg = < 0 20000000 >; + } ; +} ; -- cgit v1.1 From d58577d8f36f66dbb5dec30fc01dfddda0cfd1fa Mon Sep 17 00:00:00 2001 From: John Linn Date: Wed, 2 Jul 2008 15:11:28 -0700 Subject: powerpc/virtex: Fix booting of Xilinx FPGAs with 16550 for 405 and 440 The following changes add processing to initialize the Xilinx 16550 UART in the boot wrapper for Virtex targets without firmware. Normally the boot wrapper assumes that the serial port has already been initialized by firmware. The wrapper was also modified to add the 440 build. Signed-off-by: John Linn Signed-off-by: Grant Likely --- arch/powerpc/boot/Makefile | 2 +- arch/powerpc/boot/simpleboot.c | 6 +++ arch/powerpc/boot/virtex.c | 100 +++++++++++++++++++++++++++++++++++++++++ arch/powerpc/boot/wrapper | 6 ++- 4 files changed, 112 insertions(+), 2 deletions(-) create mode 100644 arch/powerpc/boot/virtex.c (limited to 'arch/powerpc/boot') diff --git a/arch/powerpc/boot/Makefile b/arch/powerpc/boot/Makefile index 751a6e6..df6e621 100644 --- a/arch/powerpc/boot/Makefile +++ b/arch/powerpc/boot/Makefile @@ -68,7 +68,7 @@ src-plat := of.c cuboot-52xx.c cuboot-824x.c cuboot-83xx.c cuboot-85xx.c holly.c fixed-head.S ep88xc.c ep405.c cuboot-c2k.c \ cuboot-katmai.c cuboot-rainier.c redboot-8xx.c ep8248e.c \ cuboot-warp.c cuboot-85xx-cpm2.c cuboot-yosemite.c simpleboot.c \ - virtex405-head.S redboot-83xx.c cuboot-sam440ep.c + virtex405-head.S virtex.c redboot-83xx.c cuboot-sam440ep.c src-boot := $(src-wlib) $(src-plat) empty.c src-boot := $(addprefix $(obj)/, $(src-boot)) diff --git a/arch/powerpc/boot/simpleboot.c b/arch/powerpc/boot/simpleboot.c index 86cd285..c58a0da 100644 --- a/arch/powerpc/boot/simpleboot.c +++ b/arch/powerpc/boot/simpleboot.c @@ -23,6 +23,8 @@ BSS_STACK(4*1024); +extern int platform_specific_init(void) __attribute__((weak)); + void platform_init(unsigned long r3, unsigned long r4, unsigned long r5, unsigned long r6, unsigned long r7) { @@ -80,5 +82,9 @@ void platform_init(unsigned long r3, unsigned long r4, unsigned long r5, /* prepare the device tree and find the console */ fdt_init(_dtb_start); + + if (platform_specific_init) + platform_specific_init(); + serial_console_init(); } diff --git a/arch/powerpc/boot/virtex.c b/arch/powerpc/boot/virtex.c new file mode 100644 index 0000000..f622805 --- /dev/null +++ b/arch/powerpc/boot/virtex.c @@ -0,0 +1,100 @@ +/* + * The platform specific code for virtex devices since a boot loader is not + * always used. + * + * (C) Copyright 2008 Xilinx, Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include "ops.h" +#include "io.h" +#include "stdio.h" + +#define UART_DLL 0 /* Out: Divisor Latch Low */ +#define UART_DLM 1 /* Out: Divisor Latch High */ +#define UART_FCR 2 /* Out: FIFO Control Register */ +#define UART_FCR_CLEAR_RCVR 0x02 /* Clear the RCVR FIFO */ +#define UART_FCR_CLEAR_XMIT 0x04 /* Clear the XMIT FIFO */ +#define UART_LCR 3 /* Out: Line Control Register */ +#define UART_MCR 4 /* Out: Modem Control Register */ +#define UART_MCR_RTS 0x02 /* RTS complement */ +#define UART_MCR_DTR 0x01 /* DTR complement */ +#define UART_LCR_DLAB 0x80 /* Divisor latch access bit */ +#define UART_LCR_WLEN8 0x03 /* Wordlength: 8 bits */ + +static int virtex_ns16550_console_init(void *devp) +{ + unsigned char *reg_base; + u32 reg_shift, reg_offset, clk, spd; + u16 divisor; + int n; + + if (dt_get_virtual_reg(devp, (void **)®_base, 1) < 1) + return -1; + + n = getprop(devp, "reg-offset", ®_offset, sizeof(reg_offset)); + if (n == sizeof(reg_offset)) + reg_base += reg_offset; + + n = getprop(devp, "reg-shift", ®_shift, sizeof(reg_shift)); + if (n != sizeof(reg_shift)) + reg_shift = 0; + + n = getprop(devp, "current-speed", (void *)&spd, sizeof(spd)); + if (n != sizeof(spd)) + spd = 9600; + + /* should there be a default clock rate?*/ + n = getprop(devp, "clock-frequency", (void *)&clk, sizeof(clk)); + if (n != sizeof(clk)) + return -1; + + divisor = clk / (16 * spd); + + /* Access baud rate */ + out_8(reg_base + (UART_LCR << reg_shift), UART_LCR_DLAB); + + /* Baud rate based on input clock */ + out_8(reg_base + (UART_DLL << reg_shift), divisor & 0xFF); + out_8(reg_base + (UART_DLM << reg_shift), divisor >> 8); + + /* 8 data, 1 stop, no parity */ + out_8(reg_base + (UART_LCR << reg_shift), UART_LCR_WLEN8); + + /* RTS/DTR */ + out_8(reg_base + (UART_MCR << reg_shift), UART_MCR_RTS | UART_MCR_DTR); + + /* Clear transmitter and receiver */ + out_8(reg_base + (UART_FCR << reg_shift), + UART_FCR_CLEAR_XMIT | UART_FCR_CLEAR_RCVR); + return 0; +} + +/* For virtex, the kernel may be loaded without using a bootloader and if so + some UARTs need more setup than is provided in the normal console init +*/ +int platform_specific_init(void) +{ + void *devp; + char devtype[MAX_PROP_LEN]; + char path[MAX_PATH_LEN]; + + devp = finddevice("/chosen"); + if (devp == NULL) + return -1; + + if (getprop(devp, "linux,stdout-path", path, MAX_PATH_LEN) > 0) { + devp = finddevice(path); + if (devp == NULL) + return -1; + + if ((getprop(devp, "device_type", devtype, sizeof(devtype)) > 0) + && !strcmp(devtype, "serial") + && (dt_is_compatible(devp, "ns16550"))) + virtex_ns16550_console_init(devp); + } + return 0; +} diff --git a/arch/powerpc/boot/wrapper b/arch/powerpc/boot/wrapper index df2358e..592a6ea 100755 --- a/arch/powerpc/boot/wrapper +++ b/arch/powerpc/boot/wrapper @@ -207,7 +207,11 @@ adder875-redboot) binary=y ;; simpleboot-virtex405-*) - platformo="$object/virtex405-head.o $object/simpleboot.o" + platformo="$object/virtex405-head.o $object/simpleboot.o $object/virtex.o" + binary=y + ;; +simpleboot-virtex440-*) + platformo="$object/simpleboot.o $object/virtex.o" binary=y ;; asp834x-redboot) -- cgit v1.1 From 1d46e379aae7349069f459618f53fd5193c2fd29 Mon Sep 17 00:00:00 2001 From: Grant Likely Date: Fri, 4 Jul 2008 00:59:37 -0600 Subject: powerpc/bootwrapper: add missing bit of simpleImage target The wrapper script is missing the bits needed for building generic simpleImage targets (targets which don't depend on any particular firmware interface and retrieve all their data from the device tree). Signed-off-by: Grant Likely --- arch/powerpc/boot/wrapper | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/powerpc/boot') diff --git a/arch/powerpc/boot/wrapper b/arch/powerpc/boot/wrapper index 592a6ea..644bf9d 100755 --- a/arch/powerpc/boot/wrapper +++ b/arch/powerpc/boot/wrapper @@ -214,6 +214,10 @@ simpleboot-virtex440-*) platformo="$object/simpleboot.o $object/virtex.o" binary=y ;; +simpleboot-*) + platformo="$object/simpleboot.o" + binary=y + ;; asp834x-redboot) platformo="$object/fixed-head.o $object/redboot-83xx.o" binary=y -- cgit v1.1 From 05781ccd74c63c6c8567f99101587d5c07c163e0 Mon Sep 17 00:00:00 2001 From: Grant Erickson Date: Tue, 8 Jul 2008 08:03:11 +1000 Subject: ibm_newemac: Parameterize EMAC Multicast Match Handling Various instances of the EMAC core have varying: 1) number of address match slots, 2) width of the registers for handling address match slots, 3) number of registers for handling address match slots and 4) base offset for those registers. As the driver stands today, it assumes that all EMACs have 4 IAHT and GAHT 32-bit registers, starting at offset 0x30 from the register base, with only 16-bits of each used for a total of 64 match slots. The 405EX(r) and 460EX now use the EMAC4SYNC core rather than the EMAC4 core. This core has 8 IAHT and GAHT registers, starting at offset 0x80 from the register base, with ALL 32-bits of each used for a total of 256 match slots. This adds a new compatible device tree entry "emac4sync" and a new, related feature flag "EMAC_FTR_EMAC4SYNC" along with a series of macros and inlines which supply the appropriate parameterized value based on the presence or absence of the EMAC4SYNC feature. The code has further been reworked where appropriate to use those macros and inlines. In addition, the register size passed to ioremap is now taken from the device tree: c4 for EMAC4SYNC cores 74 for EMAC4 cores 70 for EMAC cores rather than sizeof (emac_regs). Finally, the device trees have been updated with the appropriate compatible entries and resource sizes. This has been tested on an AMCC Haleakala board such that: 1) inbound ICMP requests to 'haleakala.local' via MDNS from both Mac OS X 10.4.11 and Ubuntu 8.04 systems as well as 2) outbound ICMP requests from 'haleakala.local' to those same systems in the '.local' domain via MDNS now work. Signed-off-by: Grant Erickson Acked-by: Jeff Garzik Signed-off-by: Benjamin Herrenschmidt --- arch/powerpc/boot/dts/canyonlands.dts | 8 ++++---- arch/powerpc/boot/dts/glacier.dts | 8 ++++---- arch/powerpc/boot/dts/haleakala.dts | 4 ++-- arch/powerpc/boot/dts/katmai.dts | 2 +- arch/powerpc/boot/dts/kilauea.dts | 8 ++++---- arch/powerpc/boot/dts/makalu.dts | 8 ++++---- arch/powerpc/boot/dts/rainier.dts | 4 ++-- arch/powerpc/boot/dts/sequoia.dts | 4 ++-- arch/powerpc/boot/dts/taishan.dts | 8 ++++---- 9 files changed, 27 insertions(+), 27 deletions(-) (limited to 'arch/powerpc/boot') diff --git a/arch/powerpc/boot/dts/canyonlands.dts b/arch/powerpc/boot/dts/canyonlands.dts index f9fe032..79fe412 100644 --- a/arch/powerpc/boot/dts/canyonlands.dts +++ b/arch/powerpc/boot/dts/canyonlands.dts @@ -266,7 +266,7 @@ EMAC0: ethernet@ef600e00 { device_type = "network"; - compatible = "ibm,emac-460ex", "ibm,emac4"; + compatible = "ibm,emac-460ex", "ibm,emac4sync"; interrupt-parent = <&EMAC0>; interrupts = <0x0 0x1>; #interrupt-cells = <1>; @@ -274,7 +274,7 @@ #size-cells = <0>; interrupt-map = ; - reg = <0xef600e00 0x00000070>; + reg = <0xef600e00 0x000000c4>; local-mac-address = [000000000000]; /* Filled in by U-Boot */ mal-device = <&MAL0>; mal-tx-channel = <0>; @@ -295,7 +295,7 @@ EMAC1: ethernet@ef600f00 { device_type = "network"; - compatible = "ibm,emac-460ex", "ibm,emac4"; + compatible = "ibm,emac-460ex", "ibm,emac4sync"; interrupt-parent = <&EMAC1>; interrupts = <0x0 0x1>; #interrupt-cells = <1>; @@ -303,7 +303,7 @@ #size-cells = <0>; interrupt-map = ; - reg = <0xef600f00 0x00000070>; + reg = <0xef600f00 0x000000c4>; local-mac-address = [000000000000]; /* Filled in by U-Boot */ mal-device = <&MAL0>; mal-tx-channel = <1>; diff --git a/arch/powerpc/boot/dts/glacier.dts b/arch/powerpc/boot/dts/glacier.dts index 463650c..24cf0db 100644 --- a/arch/powerpc/boot/dts/glacier.dts +++ b/arch/powerpc/boot/dts/glacier.dts @@ -283,7 +283,7 @@ #size-cells = <0>; interrupt-map = ; - reg = <0xef600e00 0x00000070>; + reg = <0xef600e00 0x00000074>; local-mac-address = [000000000000]; /* Filled in by U-Boot */ mal-device = <&MAL0>; mal-tx-channel = <0>; @@ -312,7 +312,7 @@ #size-cells = <0>; interrupt-map = ; - reg = <0xef600f00 0x00000070>; + reg = <0xef600f00 0x00000074>; local-mac-address = [000000000000]; /* Filled in by U-Boot */ mal-device = <&MAL0>; mal-tx-channel = <1>; @@ -342,7 +342,7 @@ #size-cells = <0>; interrupt-map = ; - reg = <0xef601100 0x00000070>; + reg = <0xef601100 0x00000074>; local-mac-address = [000000000000]; /* Filled in by U-Boot */ mal-device = <&MAL0>; mal-tx-channel = <2>; @@ -370,7 +370,7 @@ #size-cells = <0>; interrupt-map = ; - reg = <0xef601200 0x00000070>; + reg = <0xef601200 0x00000074>; local-mac-address = [000000000000]; /* Filled in by U-Boot */ mal-device = <&MAL0>; mal-tx-channel = <3>; diff --git a/arch/powerpc/boot/dts/haleakala.dts b/arch/powerpc/boot/dts/haleakala.dts index 2c2fcea..513bc43 100644 --- a/arch/powerpc/boot/dts/haleakala.dts +++ b/arch/powerpc/boot/dts/haleakala.dts @@ -206,7 +206,7 @@ EMAC0: ethernet@ef600900 { linux,network-index = <0x0>; device_type = "network"; - compatible = "ibm,emac-405exr", "ibm,emac4"; + compatible = "ibm,emac-405exr", "ibm,emac4sync"; interrupt-parent = <&EMAC0>; interrupts = <0x0 0x1>; #interrupt-cells = <1>; @@ -214,7 +214,7 @@ #size-cells = <0>; interrupt-map = ; - reg = <0xef600900 0x00000070>; + reg = <0xef600900 0x000000c4>; local-mac-address = [000000000000]; /* Filled in by U-Boot */ mal-device = <&MAL0>; mal-tx-channel = <0>; diff --git a/arch/powerpc/boot/dts/katmai.dts b/arch/powerpc/boot/dts/katmai.dts index b94bf61..077819b 100644 --- a/arch/powerpc/boot/dts/katmai.dts +++ b/arch/powerpc/boot/dts/katmai.dts @@ -208,7 +208,7 @@ compatible = "ibm,emac-440spe", "ibm,emac4"; interrupt-parent = <&UIC1>; interrupts = <0x1c 0x4 0x1d 0x4>; - reg = <0x10000800 0x00000070>; + reg = <0x10000800 0x00000074>; local-mac-address = [000000000000]; mal-device = <&MAL0>; mal-tx-channel = <0>; diff --git a/arch/powerpc/boot/dts/kilauea.dts b/arch/powerpc/boot/dts/kilauea.dts index 3ed6a8f..dececc4 100644 --- a/arch/powerpc/boot/dts/kilauea.dts +++ b/arch/powerpc/boot/dts/kilauea.dts @@ -207,7 +207,7 @@ EMAC0: ethernet@ef600900 { linux,network-index = <0x0>; device_type = "network"; - compatible = "ibm,emac-405ex", "ibm,emac4"; + compatible = "ibm,emac-405ex", "ibm,emac4sync"; interrupt-parent = <&EMAC0>; interrupts = <0x0 0x1>; #interrupt-cells = <1>; @@ -215,7 +215,7 @@ #size-cells = <0>; interrupt-map = ; - reg = <0xef600900 0x00000070>; + reg = <0xef600900 0x000000c4>; local-mac-address = [000000000000]; /* Filled in by U-Boot */ mal-device = <&MAL0>; mal-tx-channel = <0>; @@ -235,7 +235,7 @@ EMAC1: ethernet@ef600a00 { linux,network-index = <0x1>; device_type = "network"; - compatible = "ibm,emac-405ex", "ibm,emac4"; + compatible = "ibm,emac-405ex", "ibm,emac4sync"; interrupt-parent = <&EMAC1>; interrupts = <0x0 0x1>; #interrupt-cells = <1>; @@ -243,7 +243,7 @@ #size-cells = <0>; interrupt-map = ; - reg = <0xef600a00 0x00000070>; + reg = <0xef600a00 0x000000c4>; local-mac-address = [000000000000]; /* Filled in by U-Boot */ mal-device = <&MAL0>; mal-tx-channel = <1>; diff --git a/arch/powerpc/boot/dts/makalu.dts b/arch/powerpc/boot/dts/makalu.dts index 1dfcd7e..945508c 100644 --- a/arch/powerpc/boot/dts/makalu.dts +++ b/arch/powerpc/boot/dts/makalu.dts @@ -207,7 +207,7 @@ EMAC0: ethernet@ef600900 { linux,network-index = <0x0>; device_type = "network"; - compatible = "ibm,emac-405ex", "ibm,emac4"; + compatible = "ibm,emac-405ex", "ibm,emac4sync"; interrupt-parent = <&EMAC0>; interrupts = <0x0 0x1>; #interrupt-cells = <1>; @@ -215,7 +215,7 @@ #size-cells = <0>; interrupt-map = ; - reg = <0xef600900 0x00000070>; + reg = <0xef600900 0x000000c4>; local-mac-address = [000000000000]; /* Filled in by U-Boot */ mal-device = <&MAL0>; mal-tx-channel = <0>; @@ -235,7 +235,7 @@ EMAC1: ethernet@ef600a00 { linux,network-index = <0x1>; device_type = "network"; - compatible = "ibm,emac-405ex", "ibm,emac4"; + compatible = "ibm,emac-405ex", "ibm,emac4sync"; interrupt-parent = <&EMAC1>; interrupts = <0x0 0x1>; #interrupt-cells = <1>; @@ -243,7 +243,7 @@ #size-cells = <0>; interrupt-map = ; - reg = <0xef600a00 0x00000070>; + reg = <0xef600a00 0x000000c4>; local-mac-address = [000000000000]; /* Filled in by U-Boot */ mal-device = <&MAL0>; mal-tx-channel = <1>; diff --git a/arch/powerpc/boot/dts/rainier.dts b/arch/powerpc/boot/dts/rainier.dts index 2afb63a..9684c80 100644 --- a/arch/powerpc/boot/dts/rainier.dts +++ b/arch/powerpc/boot/dts/rainier.dts @@ -265,7 +265,7 @@ #size-cells = <0>; interrupt-map = ; - reg = <0xef600e00 0x00000070>; + reg = <0xef600e00 0x00000074>; local-mac-address = [000000000000]; mal-device = <&MAL0>; mal-tx-channel = <0>; @@ -294,7 +294,7 @@ #size-cells = <0>; interrupt-map = ; - reg = <0xef600f00 0x00000070>; + reg = <0xef600f00 0x00000074>; local-mac-address = [000000000000]; mal-device = <&MAL0>; mal-tx-channel = <1>; diff --git a/arch/powerpc/boot/dts/sequoia.dts b/arch/powerpc/boot/dts/sequoia.dts index 149dabc..72d15f0 100644 --- a/arch/powerpc/boot/dts/sequoia.dts +++ b/arch/powerpc/boot/dts/sequoia.dts @@ -280,7 +280,7 @@ #size-cells = <0>; interrupt-map = ; - reg = <0xef600e00 0x00000070>; + reg = <0xef600e00 0x00000074>; local-mac-address = [000000000000]; mal-device = <&MAL0>; mal-tx-channel = <0>; @@ -309,7 +309,7 @@ #size-cells = <0>; interrupt-map = ; - reg = <0xef600f00 0x00000070>; + reg = <0xef600f00 0x00000074>; local-mac-address = [000000000000]; mal-device = <&MAL0>; mal-tx-channel = <1>; diff --git a/arch/powerpc/boot/dts/taishan.dts b/arch/powerpc/boot/dts/taishan.dts index d4867de..058438f 100644 --- a/arch/powerpc/boot/dts/taishan.dts +++ b/arch/powerpc/boot/dts/taishan.dts @@ -287,7 +287,7 @@ compatible = "ibm,emac-440gx", "ibm,emac4"; interrupt-parent = <&UIC1>; interrupts = <0x1c 0x4 0x1d 0x4>; - reg = <0x40000800 0x00000070>; + reg = <0x40000800 0x00000074>; local-mac-address = [000000000000]; // Filled in by zImage mal-device = <&MAL0>; mal-tx-channel = <0>; @@ -307,7 +307,7 @@ compatible = "ibm,emac-440gx", "ibm,emac4"; interrupt-parent = <&UIC1>; interrupts = <0x1e 0x4 0x1f 0x4>; - reg = <0x40000900 0x00000070>; + reg = <0x40000900 0x00000074>; local-mac-address = [000000000000]; // Filled in by zImage mal-device = <&MAL0>; mal-tx-channel = <1>; @@ -327,7 +327,7 @@ compatible = "ibm,emac-440gx", "ibm,emac4"; interrupt-parent = <&UIC2>; interrupts = <0x0 0x4 0x1 0x4>; - reg = <0x40000c00 0x00000070>; + reg = <0x40000c00 0x00000074>; local-mac-address = [000000000000]; // Filled in by zImage mal-device = <&MAL0>; mal-tx-channel = <2>; @@ -351,7 +351,7 @@ compatible = "ibm,emac-440gx", "ibm,emac4"; interrupt-parent = <&UIC2>; interrupts = <0x2 0x4 0x3 0x4>; - reg = <0x40000e00 0x00000070>; + reg = <0x40000e00 0x00000074>; local-mac-address = [000000000000]; // Filled in by zImage mal-device = <&MAL0>; mal-tx-channel = <3>; -- cgit v1.1 From c356aa456e8677682aa3cdb4b81d08e814b1a379 Mon Sep 17 00:00:00 2001 From: Grant Likely Date: Wed, 9 Jul 2008 09:41:52 -0600 Subject: powerpc/bootwrapper: Allow user to specify additional default targets It is inconvenient to add additional default targets to the bootwrapper Makefile for each new board supported which just needs a different dts file. This change allows the defconfig to specify additional build targets. Signed-off-by: Grant Likely Acked-by: Josh Boyer --- arch/powerpc/boot/Makefile | 3 +++ 1 file changed, 3 insertions(+) (limited to 'arch/powerpc/boot') diff --git a/arch/powerpc/boot/Makefile b/arch/powerpc/boot/Makefile index df6e621..88d30db 100644 --- a/arch/powerpc/boot/Makefile +++ b/arch/powerpc/boot/Makefile @@ -276,6 +276,9 @@ ifeq ($(CONFIG_PPC32),y) image-$(CONFIG_PPC_PMAC) += zImage.coff zImage.miboot endif +# Allow extra targets to be added to the defconfig +image-y += $(subst ",,$(CONFIG_EXTRA_TARGETS)) + initrd- := $(patsubst zImage%, zImage.initrd%, $(image-n) $(image-)) initrd-y := $(patsubst zImage%, zImage.initrd%, \ $(patsubst dtbImage%, dtbImage.initrd%, \ -- cgit v1.1 From 9fde9bdd3023854f7b03cc425ff4a0ed51bd1eb3 Mon Sep 17 00:00:00 2001 From: Grant Likely Date: Wed, 9 Jul 2008 10:56:11 -0600 Subject: powerpc/440: Convert Virtex ML507 device tree to dts-v1 Signed-off-by: Grant Likely --- arch/powerpc/boot/dts/virtex440-ml507.dts | 256 ++++++++++++++++++------------ 1 file changed, 157 insertions(+), 99 deletions(-) (limited to 'arch/powerpc/boot') diff --git a/arch/powerpc/boot/dts/virtex440-ml507.dts b/arch/powerpc/boot/dts/virtex440-ml507.dts index f1b3344..dc8e78e 100644 --- a/arch/powerpc/boot/dts/virtex440-ml507.dts +++ b/arch/powerpc/boot/dts/virtex440-ml507.dts @@ -9,36 +9,42 @@ * kind, whether express or implied. */ +/dts-v1/; + / { #address-cells = <1>; #size-cells = <1>; compatible = "xlnx,virtex440"; - dcr-parent = <&ppc440_virtex5_0>; + dcr-parent = <&ppc440_0>; model = "testing"; + DDR2_SDRAM: memory@0 { + device_type = "memory"; + reg = < 0 0x10000000 >; + } ; chosen { bootargs = "console=ttyS0 ip=on root=/dev/ram"; - linux,stdout-path = "/plb@0/serial@d0000000"; + linux,stdout-path = "/plb@0/serial@83e00000"; } ; cpus { #address-cells = <1>; #cpus = <1>; #size-cells = <0>; - ppc440_virtex5_0: cpu@0 { - clock-frequency = <17d78400>; + ppc440_0: cpu@0 { + clock-frequency = <400000000>; compatible = "PowerPC,440", "ibm,ppc440"; - d-cache-line-size = <20>; - d-cache-size = <8000>; + d-cache-line-size = <0x20>; + d-cache-size = <0x8000>; dcr-access-method = "native"; dcr-controller ; device_type = "cpu"; - i-cache-line-size = <20>; - i-cache-size = <8000>; + i-cache-line-size = <0x20>; + i-cache-size = <0x8000>; model = "PowerPC,440"; reg = <0>; - timebase-frequency = <17d78400>; + timebase-frequency = <400000000>; xlnx,apu-control = <1>; - xlnx,apu-udi-0 = ; - xlnx,apu-udi-1 = ; + xlnx,apu-udi-0 = <0>; + xlnx,apu-udi-1 = <0>; xlnx,apu-udi-10 = <0>; xlnx,apu-udi-11 = <0>; xlnx,apu-udi-12 = <0>; @@ -63,41 +69,41 @@ xlnx,dcu-wr-urgent-plb-prio = <0>; xlnx,dma0-control = <0>; xlnx,dma0-plb-prio = <0>; - xlnx,dma0-rxchannelctrl = <1010000>; - xlnx,dma0-rxirqtimer = <3ff>; - xlnx,dma0-txchannelctrl = <1010000>; - xlnx,dma0-txirqtimer = <3ff>; + xlnx,dma0-rxchannelctrl = <0x1010000>; + xlnx,dma0-rxirqtimer = <0x3ff>; + xlnx,dma0-txchannelctrl = <0x1010000>; + xlnx,dma0-txirqtimer = <0x3ff>; xlnx,dma1-control = <0>; xlnx,dma1-plb-prio = <0>; - xlnx,dma1-rxchannelctrl = <1010000>; - xlnx,dma1-rxirqtimer = <3ff>; - xlnx,dma1-txchannelctrl = <1010000>; - xlnx,dma1-txirqtimer = <3ff>; + xlnx,dma1-rxchannelctrl = <0x1010000>; + xlnx,dma1-rxirqtimer = <0x3ff>; + xlnx,dma1-txchannelctrl = <0x1010000>; + xlnx,dma1-txirqtimer = <0x3ff>; xlnx,dma2-control = <0>; xlnx,dma2-plb-prio = <0>; - xlnx,dma2-rxchannelctrl = <1010000>; - xlnx,dma2-rxirqtimer = <3ff>; - xlnx,dma2-txchannelctrl = <1010000>; - xlnx,dma2-txirqtimer = <3ff>; + xlnx,dma2-rxchannelctrl = <0x1010000>; + xlnx,dma2-rxirqtimer = <0x3ff>; + xlnx,dma2-txchannelctrl = <0x1010000>; + xlnx,dma2-txirqtimer = <0x3ff>; xlnx,dma3-control = <0>; xlnx,dma3-plb-prio = <0>; - xlnx,dma3-rxchannelctrl = <1010000>; - xlnx,dma3-rxirqtimer = <3ff>; - xlnx,dma3-txchannelctrl = <1010000>; - xlnx,dma3-txirqtimer = <3ff>; + xlnx,dma3-rxchannelctrl = <0x1010000>; + xlnx,dma3-rxirqtimer = <0x3ff>; + xlnx,dma3-txchannelctrl = <0x1010000>; + xlnx,dma3-txirqtimer = <0x3ff>; xlnx,endian-reset = <0>; xlnx,generate-plb-timespecs = <1>; xlnx,icu-rd-fetch-plb-prio = <0>; xlnx,icu-rd-spec-plb-prio = <0>; xlnx,icu-rd-touch-plb-prio = <0>; - xlnx,interconnect-imask = ; + xlnx,interconnect-imask = <0xffffffff>; xlnx,mplb-allow-lock-xfer = <1>; xlnx,mplb-arb-mode = <0>; - xlnx,mplb-awidth = <20>; - xlnx,mplb-counter = <500>; - xlnx,mplb-dwidth = <80>; + xlnx,mplb-awidth = <0x20>; + xlnx,mplb-counter = <0x500>; + xlnx,mplb-dwidth = <0x80>; xlnx,mplb-max-burst = <8>; - xlnx,mplb-native-dwidth = <80>; + xlnx,mplb-native-dwidth = <0x80>; xlnx,mplb-p2p = <0>; xlnx,mplb-prio-dcur = <2>; xlnx,mplb-prio-dcuw = <3>; @@ -110,54 +116,41 @@ xlnx,mplb-write-pipe-enable = <1>; xlnx,mplb-write-post-enable = <1>; xlnx,num-dma = <1>; - xlnx,pir = ; + xlnx,pir = <0xf>; xlnx,ppc440mc-addr-base = <0>; - xlnx,ppc440mc-addr-high = <1fffffff>; + xlnx,ppc440mc-addr-high = <0xfffffff>; xlnx,ppc440mc-arb-mode = <0>; - xlnx,ppc440mc-bank-conflict-mask = ; - xlnx,ppc440mc-control = ; + xlnx,ppc440mc-bank-conflict-mask = <0xc00000>; + xlnx,ppc440mc-control = <0xf810008f>; xlnx,ppc440mc-max-burst = <8>; xlnx,ppc440mc-prio-dcur = <2>; xlnx,ppc440mc-prio-dcuw = <3>; xlnx,ppc440mc-prio-icu = <4>; xlnx,ppc440mc-prio-splb0 = <1>; xlnx,ppc440mc-prio-splb1 = <0>; - xlnx,ppc440mc-row-conflict-mask = <3ffe00>; + xlnx,ppc440mc-row-conflict-mask = <0x3ffe00>; xlnx,ppcdm-asyncmode = <0>; xlnx,ppcds-asyncmode = <0>; xlnx,user-reset = <0>; DMA0: sdma@80 { compatible = "xlnx,ll-dma-1.00.a"; - dcr-reg = < 80 11 >; - interrupt-parent = <&opb_intc_0>; - interrupts = < 5 2 6 2 >; + dcr-reg = < 0x80 0x11 >; + interrupt-parent = <&xps_intc_0>; + interrupts = < 9 2 0xa 2 >; } ; } ; } ; - plb_v46_cfb_0: plb@0 { + plb_v46_0: plb@0 { #address-cells = <1>; #size-cells = <1>; - compatible = "xlnx,plb-v46-1.02.a"; + compatible = "xlnx,plb-v46-1.02.a", "simple-bus"; ranges ; - iic_bus: i2c@d0020000 { - compatible = "xlnx,xps-iic-2.00.a"; - interrupt-parent = <&opb_intc_0>; - interrupts = < 7 2 >; - reg = < d0020000 200 >; - xlnx,clk-freq = <5f5e100>; - xlnx,family = "virtex5"; - xlnx,gpo-width = <1>; - xlnx,iic-freq = <186a0>; - xlnx,scl-inertial-delay = <0>; - xlnx,sda-inertial-delay = <0>; - xlnx,ten-bit-adr = <0>; - } ; - leds_8bit: gpio@d0010200 { + DIP_Switches_8Bit: gpio@81460000 { compatible = "xlnx,xps-gpio-1.00.a"; - interrupt-parent = <&opb_intc_0>; - interrupts = < 1 2 >; - reg = < d0010200 200 >; - xlnx,all-inputs = <0>; + interrupt-parent = <&xps_intc_0>; + interrupts = < 6 2 >; + reg = < 0x81460000 0x10000 >; + xlnx,all-inputs = <1>; xlnx,all-inputs-2 = <0>; xlnx,dout-default = <0>; xlnx,dout-default-2 = <0>; @@ -167,72 +160,137 @@ xlnx,is-bidir = <1>; xlnx,is-bidir-2 = <1>; xlnx,is-dual = <0>; - xlnx,tri-default = ; - xlnx,tri-default-2 = ; + xlnx,tri-default = <0xffffffff>; + xlnx,tri-default-2 = <0xffffffff>; } ; - ll_temac_0: xps-ll-temac@91200000 { + Hard_Ethernet_MAC: xps-ll-temac@81c00000 { #address-cells = <1>; #size-cells = <1>; compatible = "xlnx,compound"; - ethernet@91200000 { - compatible = "xlnx,xps-ll-temac-1.01.a"; + ethernet@81c00000 { + compatible = "xlnx,xps-ll-temac-1.01.b"; device_type = "network"; - interrupt-parent = <&opb_intc_0>; - interrupts = < 4 2 >; + interrupt-parent = <&xps_intc_0>; + interrupts = < 5 2 >; llink-connected = <&DMA0>; local-mac-address = [ 02 00 00 00 00 00 ]; - reg = < 91200000 40 >; + reg = < 0x81c00000 0x40 >; xlnx,bus2core-clk-ratio = <1>; xlnx,phy-type = <1>; xlnx,phyaddr = <1>; - xlnx,rxcsum = <0>; - xlnx,rxfifo = <4000>; + xlnx,rxcsum = <1>; + xlnx,rxfifo = <0x1000>; xlnx,temac-type = <0>; - xlnx,txcsum = <0>; - xlnx,txfifo = <4000>; + xlnx,txcsum = <1>; + xlnx,txfifo = <0x1000>; } ; } ; - opb_intc_0: interrupt-controller@d0020200 { - #interrupt-cells = <2>; - compatible = "xlnx,xps-intc-1.00.a"; - interrupt-controller ; - reg = < d0020200 20 >; - xlnx,num-intr-inputs = <8>; + LEDs_8Bit: gpio@81400000 { + compatible = "xlnx,xps-gpio-1.00.a"; + reg = < 0x81400000 0x10000 >; + xlnx,all-inputs = <0>; + xlnx,all-inputs-2 = <0>; + xlnx,dout-default = <0>; + xlnx,dout-default-2 = <0>; + xlnx,family = "virtex5"; + xlnx,gpio-width = <8>; + xlnx,interrupt-present = <0>; + xlnx,is-bidir = <1>; + xlnx,is-bidir-2 = <1>; + xlnx,is-dual = <0>; + xlnx,tri-default = <0xffffffff>; + xlnx,tri-default-2 = <0xffffffff>; } ; - plb_bram_if_cntlr_0: xps-bram-if-cntlr@ffff0000 { - compatible = "xlnx,xps-bram-if-cntlr-1.00.a"; - reg = < ffff0000 10000 >; + LEDs_Positions: gpio@81420000 { + compatible = "xlnx,xps-gpio-1.00.a"; + reg = < 0x81420000 0x10000 >; + xlnx,all-inputs = <0>; + xlnx,all-inputs-2 = <0>; + xlnx,dout-default = <0>; + xlnx,dout-default-2 = <0>; xlnx,family = "virtex5"; + xlnx,gpio-width = <5>; + xlnx,interrupt-present = <0>; + xlnx,is-bidir = <1>; + xlnx,is-bidir-2 = <1>; + xlnx,is-dual = <0>; + xlnx,tri-default = <0xffffffff>; + xlnx,tri-default-2 = <0xffffffff>; } ; - plb_bram_if_cntlr_1: xps-bram-if-cntlr@eee00000 { - compatible = "xlnx,xps-bram-if-cntlr-1.00.a"; - reg = < eee00000 2000 >; + Push_Buttons_5Bit: gpio@81440000 { + compatible = "xlnx,xps-gpio-1.00.a"; + interrupt-parent = <&xps_intc_0>; + interrupts = < 7 2 >; + reg = < 0x81440000 0x10000 >; + xlnx,all-inputs = <1>; + xlnx,all-inputs-2 = <0>; + xlnx,dout-default = <0>; + xlnx,dout-default-2 = <0>; xlnx,family = "virtex5"; + xlnx,gpio-width = <5>; + xlnx,interrupt-present = <1>; + xlnx,is-bidir = <1>; + xlnx,is-bidir-2 = <1>; + xlnx,is-dual = <0>; + xlnx,tri-default = <0xffffffff>; + xlnx,tri-default-2 = <0xffffffff>; } ; - rs232_uart_0: serial@d0000000 { - clock-frequency = <1312d00>; + RS232_Uart_1: serial@83e00000 { + clock-frequency = <100000000>; compatible = "xlnx,xps-uart16550-2.00.a", "ns16550"; - current-speed = <2580>; + current-speed = <0x2580>; device_type = "serial"; - interrupt-parent = <&opb_intc_0>; - interrupts = < 0 2 >; - reg = < d0000000 2000 >; - reg-offset = <1003>; + interrupt-parent = <&xps_intc_0>; + interrupts = < 8 2 >; + reg = < 0x83e00000 0x10000 >; + reg-offset = <3>; reg-shift = <2>; xlnx,family = "virtex5"; xlnx,has-external-rclk = <0>; - xlnx,has-external-xin = <1>; + xlnx,has-external-xin = <0>; xlnx,is-a-16550 = <1>; } ; - sysace_compactflash: sysace@d0030100 { + SysACE_CompactFlash: sysace@83600000 { compatible = "xlnx,xps-sysace-1.00.a"; - reg = < d0030100 80 >; + interrupt-parent = <&xps_intc_0>; + interrupts = < 4 2 >; + reg = < 0x83600000 0x10000 >; xlnx,family = "virtex5"; - xlnx,mem-width = <10>; + xlnx,mem-width = <0x10>; + } ; + xps_bram_if_cntlr_1: xps-bram-if-cntlr@ffff0000 { + compatible = "xlnx,xps-bram-if-cntlr-1.00.a"; + reg = < 0xffff0000 0x10000 >; + xlnx,family = "virtex5"; + } ; + xps_intc_0: interrupt-controller@81800000 { + #interrupt-cells = <2>; + compatible = "xlnx,xps-intc-1.00.a"; + interrupt-controller ; + reg = < 0x81800000 0x10000 >; + xlnx,num-intr-inputs = <0xb>; + } ; + xps_timebase_wdt_1: xps-timebase-wdt@83a00000 { + compatible = "xlnx,xps-timebase-wdt-1.00.b"; + interrupt-parent = <&xps_intc_0>; + interrupts = < 2 0 1 2 >; + reg = < 0x83a00000 0x10000 >; + xlnx,family = "virtex5"; + xlnx,wdt-enable-once = <0>; + xlnx,wdt-interval = <0x1e>; + } ; + xps_timer_1: timer@83c00000 { + compatible = "xlnx,xps-timer-1.00.a"; + interrupt-parent = <&xps_intc_0>; + interrupts = < 3 2 >; + reg = < 0x83c00000 0x10000 >; + xlnx,count-width = <0x20>; + xlnx,family = "virtex5"; + xlnx,gen0-assert = <1>; + xlnx,gen1-assert = <1>; + xlnx,one-timer-only = <1>; + xlnx,trig0-assert = <1>; + xlnx,trig1-assert = <1>; } ; - } ; - ppc440mc_ddr2_0: memory@0 { - device_type = "memory"; - reg = < 0 20000000 >; } ; } ; -- cgit v1.1 From b0852cb8841f35b124f4344d92abd8c0a6b54fcf Mon Sep 17 00:00:00 2001 From: Wolfgang Grandegger Date: Wed, 2 Jul 2008 11:56:40 +0200 Subject: powerpc/mpc5200: add missing MSCAN FDT nodes for TQM52xx This patch adds the still missing FDT nodes for the MSCAN devices for the TQM52xx modules. Signed-off-by: Wolfgang Grandegger Signed-off-by: Grant Likely --- arch/powerpc/boot/dts/tqm5200.dts | 14 ++++++++++++++ 1 file changed, 14 insertions(+) (limited to 'arch/powerpc/boot') diff --git a/arch/powerpc/boot/dts/tqm5200.dts b/arch/powerpc/boot/dts/tqm5200.dts index 773a68e..3008bf8 100644 --- a/arch/powerpc/boot/dts/tqm5200.dts +++ b/arch/powerpc/boot/dts/tqm5200.dts @@ -70,6 +70,20 @@ fsl,has-wdt; }; + can@900 { + compatible = "fsl,mpc5200-mscan"; + interrupts = <2 17 0>; + interrupt-parent = <&mpc5200_pic>; + reg = <0x900 0x80>; + }; + + can@980 { + compatible = "fsl,mpc5200-mscan"; + interrupts = <2 18 0>; + interrupt-parent = <&mpc5200_pic>; + reg = <0x980 0x80>; + }; + gpio@b00 { compatible = "fsl,mpc5200-gpio"; reg = <0xb00 0x40>; -- cgit v1.1 From 4df64c3e58d28ffc5c61bdbdd733c5d0303b9f3c Mon Sep 17 00:00:00 2001 From: John Rigby Date: Wed, 9 Jul 2008 14:54:01 -0600 Subject: powerpc/mpc5121: Update device tree for MPC5121ADS evaluation board Current device tree is only bare bones. This patch adds nodes to make it a complete tree for the MPC5121ads. Added nodes include: mbx - opengl coprocessor nfc - nand flash controller cpld-pic - on board cpld rtc clock - clock control pmc - power management control gpio mscan - can module i2c axe - audio coprocessor display - display interface unit mdio ethernet usb ioctl - pin config pata ac97 - PSC configured as AC97 pscfifo - psc fifo configuration dma pci Fix typo in header changing MDS to ADS. Add a compatible property of the form "fsl,mpc5121-..." to nodes missing one. Changed localbus compatible to fsl,mpc5121-localbus, this does not break anything because the only code that uses it finds it via the node name, not compatible. Signed-off-by: John Rigby Signed-off-by: Grant Likely --- arch/powerpc/boot/dts/mpc5121ads.dts | 310 +++++++++++++++++++++++++++++++++-- 1 file changed, 299 insertions(+), 11 deletions(-) (limited to 'arch/powerpc/boot') diff --git a/arch/powerpc/boot/dts/mpc5121ads.dts b/arch/powerpc/boot/dts/mpc5121ads.dts index 94ad7b2..1f9036c 100644 --- a/arch/powerpc/boot/dts/mpc5121ads.dts +++ b/arch/powerpc/boot/dts/mpc5121ads.dts @@ -1,7 +1,7 @@ /* - * MPC5121E MDS Device Tree Source + * MPC5121E ADS Device Tree Source * - * Copyright 2007 Freescale Semiconductor Inc. + * Copyright 2007,2008 Freescale Semiconductor Inc. * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License as published by the @@ -17,6 +17,10 @@ #address-cells = <1>; #size-cells = <1>; + aliases { + pci = &pci; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -39,8 +43,41 @@ reg = <0x00000000 0x10000000>; // 256MB at 0 }; + mbx@20000000 { + compatible = "fsl,mpc5121-mbx"; + reg = <0x20000000 0x4000>; + interrupts = <66 0x8>; + interrupt-parent = < &ipic >; + }; + + sram@30000000 { + compatible = "fsl,mpc5121-sram"; + reg = <0x30000000 0x20000>; // 128K at 0x30000000 + }; + + nfc@40000000 { + compatible = "fsl,mpc5121-nfc"; + reg = <0x40000000 0x100000>; // 1M at 0x40000000 + interrupts = <6 8>; + interrupt-parent = < &ipic >; + #address-cells = <1>; + #size-cells = <1>; + bank-width = <1>; + // ADS has two Hynix 512MB Nand flash chips in a single + // stacked package . + chips = <2>; + nand0@0 { + label = "nand0"; + reg = <0x00000000 0x02000000>; // first 32 MB of chip 0 + }; + nand1@20000000 { + label = "nand1"; + reg = <0x20000000 0x02000000>; // first 32 MB of chip 1 + }; + }; + localbus@80000020 { - compatible = "fsl,mpc5121ads-localbus"; + compatible = "fsl,mpc5121-localbus"; #address-cells = <2>; #size-cells = <1>; reg = <0x80000020 0x40>; @@ -51,14 +88,51 @@ flash@0,0 { compatible = "cfi-flash"; reg = <0 0x0 0x4000000>; + #address-cells = <1>; + #size-cells = <1>; bank-width = <4>; - device-width = <1>; + device-width = <2>; + protected@0 { + label = "protected"; + reg = <0x00000000 0x00040000>; // first sector is protected + read-only; + }; + filesystem@40000 { + label = "filesystem"; + reg = <0x00040000 0x03c00000>; // 60M for filesystem + }; + kernel@3c40000 { + label = "kernel"; + reg = <0x03c40000 0x00280000>; // 2.5M for kernel + }; + device-tree@3ec0000 { + label = "device-tree"; + reg = <0x03ec0000 0x00040000>; // one sector for device tree + }; + u-boot@3f00000 { + label = "u-boot"; + reg = <0x03f00000 0x00100000>; // 1M for u-boot + read-only; + }; }; board-control@2,0 { compatible = "fsl,mpc5121ads-cpld"; reg = <0x2 0x0 0x8000>; }; + + cpld_pic: pic@2,a { + compatible = "fsl,mpc5121ads-cpld-pic"; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x2 0xa 0x5>; + interrupt-parent = < &ipic >; + // irq routing + // all irqs but touch screen are routed to irq0 (ipic 48) + // touch screen is statically routed to irq1 (ipic 17) + // so don't use it here + interrupts = <48 0x8>; + }; }; soc@80000000 { @@ -85,38 +159,252 @@ reg = <0xc00 0x100>; }; - // 512x PSCs are not 52xx PSCs compatible + rtc@a00 { // Real time clock + compatible = "fsl,mpc5121-rtc"; + reg = <0xa00 0x100>; + interrupts = <79 0x8 80 0x8>; + interrupt-parent = < &ipic >; + }; + + clock@f00 { // Clock control + compatible = "fsl,mpc5121-clock"; + reg = <0xf00 0x100>; + }; + + pmc@1000{ //Power Management Controller + compatible = "fsl,mpc5121-pmc"; + reg = <0x1000 0x100>; + interrupts = <83 0x2>; + interrupt-parent = < &ipic >; + }; + + gpio@1100 { + compatible = "fsl,mpc5121-gpio"; + reg = <0x1100 0x100>; + interrupts = <78 0x8>; + interrupt-parent = < &ipic >; + }; + + mscan@1300 { + compatible = "fsl,mpc5121-mscan"; + cell-index = <0>; + interrupts = <12 0x8>; + interrupt-parent = < &ipic >; + reg = <0x1300 0x80>; + }; + + mscan@1380 { + compatible = "fsl,mpc5121-mscan"; + cell-index = <1>; + interrupts = <13 0x8>; + interrupt-parent = < &ipic >; + reg = <0x1380 0x80>; + }; + + i2c@1700 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,mpc5121-i2c", "fsl-i2c"; + cell-index = <0>; + reg = <0x1700 0x20>; + interrupts = <9 0x8>; + interrupt-parent = < &ipic >; + fsl5200-clocking; + }; + + i2c@1720 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,mpc5121-i2c", "fsl-i2c"; + cell-index = <1>; + reg = <0x1720 0x20>; + interrupts = <10 0x8>; + interrupt-parent = < &ipic >; + fsl5200-clocking; + }; + + i2c@1740 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,mpc5121-i2c", "fsl-i2c"; + cell-index = <2>; + reg = <0x1740 0x20>; + interrupts = <11 0x8>; + interrupt-parent = < &ipic >; + fsl5200-clocking; + }; + + i2ccontrol@1760 { + compatible = "fsl,mpc5121-i2c-ctrl"; + reg = <0x1760 0x8>; + }; + + axe@2000 { + compatible = "fsl,mpc5121-axe"; + reg = <0x2000 0x100>; + interrupts = <42 0x8>; + interrupt-parent = < &ipic >; + }; + + display@2100 { + compatible = "fsl,mpc5121-diu", "fsl-diu"; + reg = <0x2100 0x100>; + interrupts = <64 0x8>; + interrupt-parent = < &ipic >; + }; + + mdio@2800 { + compatible = "fsl,mpc5121-fec-mdio"; + reg = <0x2800 0x800>; + #address-cells = <1>; + #size-cells = <0>; + phy: ethernet-phy@0 { + reg = <1>; + device_type = "ethernet-phy"; + }; + }; + + ethernet@2800 { + device_type = "network"; + compatible = "fsl,mpc5121-fec"; + reg = <0x2800 0x800>; + local-mac-address = [ 00 00 00 00 00 00 ]; + interrupts = <4 0x8>; + interrupt-parent = < &ipic >; + phy-handle = < &phy >; + fsl,align-tx-packets = <4>; + }; + + // 5121e has two dr usb modules + // mpc5121_ads only uses USB0 + + // USB1 using external ULPI PHY + //usb@3000 { + // compatible = "fsl,mpc5121-usb2-dr", "fsl-usb2-dr"; + // reg = <0x3000 0x1000>; + // #address-cells = <1>; + // #size-cells = <0>; + // interrupt-parent = < &ipic >; + // interrupts = <43 0x8>; + // dr_mode = "otg"; + // phy_type = "ulpi"; + // port1; + //}; + + // USB0 using internal UTMI PHY + usb@4000 { + compatible = "fsl,mpc5121-usb2-dr", "fsl-usb2-dr"; + reg = <0x4000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupt-parent = < &ipic >; + interrupts = <44 0x8>; + dr_mode = "otg"; + phy_type = "utmi_wide"; + port0; + }; + + // IO control + ioctl@a000 { + compatible = "fsl,mpc5121-ioctl"; + reg = <0xA000 0x1000>; + }; + + pata@10200 { + compatible = "fsl,mpc5121-pata"; + reg = <0x10200 0x100>; + interrupts = <5 0x8>; + interrupt-parent = < &ipic >; + }; + + // 512x PSCs are not 52xx PSC compatible // PSC3 serial port A aka ttyPSC0 serial@11300 { device_type = "serial"; - compatible = "fsl,mpc5121-psc-uart"; + compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc"; // Logical port assignment needed until driver // learns to use aliases port-number = <0>; cell-index = <3>; reg = <0x11300 0x100>; - interrupts = <0x28 0x8>; // actually the fifo irq + interrupts = <40 0x8>; interrupt-parent = < &ipic >; + rx-fifo-size = <16>; + tx-fifo-size = <16>; }; // PSC4 serial port B aka ttyPSC1 serial@11400 { device_type = "serial"; - compatible = "fsl,mpc5121-psc-uart"; + compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc"; // Logical port assignment needed until driver // learns to use aliases port-number = <1>; cell-index = <4>; reg = <0x11400 0x100>; - interrupts = <0x28 0x8>; // actually the fifo irq + interrupts = <40 0x8>; interrupt-parent = < &ipic >; + rx-fifo-size = <16>; + tx-fifo-size = <16>; }; - pscsfifo@11f00 { + // PSC5 in ac97 mode + ac97@11500 { + compatible = "fsl,mpc5121-psc-ac97", "fsl,mpc5121-psc"; + cell-index = <5>; + reg = <0x11500 0x100>; + interrupts = <40 0x8>; + interrupt-parent = < &ipic >; + fsl,mode = "ac97-slave"; + rx-fifo-size = <384>; + tx-fifo-size = <384>; + }; + + pscfifo@11f00 { compatible = "fsl,mpc5121-psc-fifo"; reg = <0x11f00 0x100>; - interrupts = <0x28 0x8>; + interrupts = <40 0x8>; interrupt-parent = < &ipic >; }; + + dma@14000 { + compatible = "fsl,mpc5121-dma2"; + reg = <0x14000 0x1800>; + interrupts = <65 0x8>; + interrupt-parent = < &ipic >; + }; + + }; + + pci: pci@80008500 { + interrupt-map-mask = <0xf800 0x0 0x0 0x7>; + interrupt-map = < + // IDSEL 0x15 - Slot 1 PCI + 0xa800 0x0 0x0 0x1 &cpld_pic 0x0 0x8 + 0xa800 0x0 0x0 0x2 &cpld_pic 0x1 0x8 + 0xa800 0x0 0x0 0x3 &cpld_pic 0x2 0x8 + 0xa800 0x0 0x0 0x4 &cpld_pic 0x3 0x8 + + // IDSEL 0x16 - Slot 2 MiniPCI + 0xb000 0x0 0x0 0x1 &cpld_pic 0x4 0x8 + 0xb000 0x0 0x0 0x2 &cpld_pic 0x5 0x8 + + // IDSEL 0x17 - Slot 3 MiniPCI + 0xb800 0x0 0x0 0x1 &cpld_pic 0x6 0x8 + 0xb800 0x0 0x0 0x2 &cpld_pic 0x7 0x8 + >; + interrupt-parent = < &ipic >; + interrupts = <1 0x8>; + bus-range = <0 0>; + ranges = <0x42000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000 + 0x02000000 0x0 0xb0000000 0xb0000000 0x0 0x10000000 + 0x01000000 0x0 0x00000000 0x84000000 0x0 0x01000000>; + clock-frequency = <0>; + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + reg = <0x80008500 0x100>; + compatible = "fsl,mpc5121-pci"; + device_type = "pci"; }; }; -- cgit v1.1 From 0fe9b1ea60bc209c8c87afcbb1c2ec0b28835aa4 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Mon, 30 Jun 2008 23:24:14 -0500 Subject: powerpc/85xx: Fix KSI8560 .dts Rename MPIC label to mpic to match all other 85xx .dts and to fix compile issue introduced by addition of the DMA node. Signed-off-by: Kumar Gala --- arch/powerpc/boot/dts/ksi8560.dts | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) (limited to 'arch/powerpc/boot') diff --git a/arch/powerpc/boot/dts/ksi8560.dts b/arch/powerpc/boot/dts/ksi8560.dts index fd58043..4973758 100644 --- a/arch/powerpc/boot/dts/ksi8560.dts +++ b/arch/powerpc/boot/dts/ksi8560.dts @@ -59,7 +59,7 @@ memory-controller@2000 { compatible = "fsl,8540-memory-controller"; reg = <0x2000 0x1000>; - interrupt-parent = <&MPIC>; + interrupt-parent = <&mpic>; interrupts = <0x12 0x2>; }; @@ -68,7 +68,7 @@ reg = <0x20000 0x1000>; cache-line-size = <0x20>; /* 32 bytes */ cache-size = <0x40000>; /* L2, 256K */ - interrupt-parent = <&MPIC>; + interrupt-parent = <&mpic>; interrupts = <0x10 0x2>; }; @@ -79,7 +79,7 @@ compatible = "fsl-i2c"; reg = <0x3000 0x100>; interrupts = <0x2b 0x2>; - interrupt-parent = <&MPIC>; + interrupt-parent = <&mpic>; dfsrr; }; @@ -131,13 +131,13 @@ reg = <0x24520 0x20>; PHY1: ethernet-phy@1 { - interrupt-parent = <&MPIC>; + interrupt-parent = <&mpic>; reg = <0x1>; device_type = "ethernet-phy"; }; PHY2: ethernet-phy@2 { - interrupt-parent = <&MPIC>; + interrupt-parent = <&mpic>; reg = <0x2>; device_type = "ethernet-phy"; }; @@ -151,7 +151,7 @@ /* Mac address filled in by bootwrapper */ local-mac-address = [ 00 00 00 00 00 00 ]; interrupts = <0x1d 0x2 0x1e 0x2 0x22 0x2>; - interrupt-parent = <&MPIC>; + interrupt-parent = <&mpic>; phy-handle = <&PHY1>; }; @@ -163,11 +163,11 @@ /* Mac address filled in by bootwrapper */ local-mac-address = [ 00 00 00 00 00 00 ]; interrupts = <0x23 0x2 0x24 0x2 0x28 0x2>; - interrupt-parent = <&MPIC>; + interrupt-parent = <&mpic>; phy-handle = <&PHY2>; }; - MPIC: pic@40000 { + mpic: pic@40000 { #address-cells = <0>; #interrupt-cells = <2>; interrupt-controller; @@ -206,7 +206,7 @@ #interrupt-cells = <2>; interrupt-controller; interrupts = <0x2e 0x2>; - interrupt-parent = <&MPIC>; + interrupt-parent = <&mpic>; reg = <0x90c00 0x80>; compatible = "fsl,mpc8560-cpm-pic", "fsl,cpm2-pic"; }; @@ -244,7 +244,7 @@ fsl,mdc-pin = <25>; PHY0: ethernet-phy@0 { - interrupt-parent = <&MPIC>; + interrupt-parent = <&mpic>; reg = <0x0>; device_type = "ethernet-phy"; }; -- cgit v1.1 From deabeabf0bb8e6ad0b5917859893ac5af46d9b04 Mon Sep 17 00:00:00 2001 From: Anton Vorontsov Date: Tue, 1 Jul 2008 17:04:38 +0400 Subject: powerpc/86xx: mpc8610_hpcd: fix interrupt trigger type for ULi IDE i8259 PIC is disabled on MPC8610HPCD, and ULi IDE is configured to use PCI sideband interrupt that is specified in the device tree. Current HPCD's device tree specify that IDE interrupt is low to high sensitive, but in practice ULi IDE throws active-high interrupts (not active-low as all normal PCI devices). Signed-off-by: Anton Vorontsov Signed-off-by: Kumar Gala --- arch/powerpc/boot/dts/mpc8610_hpcd.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/powerpc/boot') diff --git a/arch/powerpc/boot/dts/mpc8610_hpcd.dts b/arch/powerpc/boot/dts/mpc8610_hpcd.dts index 65a5f64..981941e 100644 --- a/arch/powerpc/boot/dts/mpc8610_hpcd.dts +++ b/arch/powerpc/boot/dts/mpc8610_hpcd.dts @@ -363,7 +363,7 @@ 0xe000 0 0 4 &mpic 1 1 /* IDSEL 0x1f */ - 0xf800 0 0 1 &mpic 3 0 + 0xf800 0 0 1 &mpic 3 2 0xf800 0 0 2 &mpic 0 1 >; -- cgit v1.1 From a3083220c089c626a66b66af0eff4f9220d5b797 Mon Sep 17 00:00:00 2001 From: Wolfgang Grandegger Date: Thu, 26 Jun 2008 15:15:43 +0200 Subject: powerpc/85xx: TQM8548: add missing support for RTC and LM75 It adds the missing RTC node to tqm8548.dts and enables support for I2C, DS1307 and LM75 in the default configuration. Signed-off-by: Wolfgang Grandegger Signed-off-by: Kumar Gala --- arch/powerpc/boot/dts/tqm8548.dts | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch/powerpc/boot') diff --git a/arch/powerpc/boot/dts/tqm8548.dts b/arch/powerpc/boot/dts/tqm8548.dts index 13cd728..2563112 100644 --- a/arch/powerpc/boot/dts/tqm8548.dts +++ b/arch/powerpc/boot/dts/tqm8548.dts @@ -83,6 +83,11 @@ interrupts = <43 2>; interrupt-parent = <&mpic>; dfsrr; + + rtc@68 { + compatible = "dallas,ds1337"; + reg = <0x68>; + }; }; i2c@3100 { -- cgit v1.1 From 2f3804edf971d2080243d2b4552bfd61ddfbf969 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Wed, 2 Jul 2008 01:36:15 -0500 Subject: powerpc/85xx: Add support for MPC8536DS Add support for the MPC8536 process and MPC8536DS reference board. The MPC8536 is an e500v2 based SoC which eTSEC, USB, SATA, PCI, and PCIe. The USB and SATA IP blocks are similiar to those on the PQ2 Pro SoCs and thus use the same drivers. Signed-off-by: Kumar Gala --- arch/powerpc/boot/dts/mpc8536ds.dts | 420 ++++++++++++++++++++++++++++++++++++ 1 file changed, 420 insertions(+) create mode 100644 arch/powerpc/boot/dts/mpc8536ds.dts (limited to 'arch/powerpc/boot') diff --git a/arch/powerpc/boot/dts/mpc8536ds.dts b/arch/powerpc/boot/dts/mpc8536ds.dts new file mode 100644 index 0000000..98ad27a --- /dev/null +++ b/arch/powerpc/boot/dts/mpc8536ds.dts @@ -0,0 +1,420 @@ +/* + * MPC8536 DS Device Tree Source + * + * Copyright 2008 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +/dts-v1/; + +/ { + model = "fsl,mpc8536ds"; + compatible = "fsl,mpc8536ds"; + #address-cells = <1>; + #size-cells = <1>; + + aliases { + ethernet0 = &enet0; + ethernet1 = &enet1; + serial0 = &serial0; + serial1 = &serial1; + pci0 = &pci0; + pci1 = &pci1; + pci2 = &pci2; + pci3 = &pci3; + }; + + cpus { + #cpus = <1>; + #address-cells = <1>; + #size-cells = <0>; + + PowerPC,8536@0 { + device_type = "cpu"; + reg = <0>; + next-level-cache = <&L2>; + }; + }; + + memory { + device_type = "memory"; + reg = <00000000 00000000>; // Filled by U-Boot + }; + + soc@ffe00000 { + #address-cells = <1>; + #size-cells = <1>; + device_type = "soc"; + ranges = <0x0 0xffe00000 0x100000>; + reg = <0xffe00000 0x1000>; + bus-frequency = <0>; // Filled out by uboot. + + memory-controller@2000 { + compatible = "fsl,mpc8536-memory-controller"; + reg = <0x2000 0x1000>; + interrupt-parent = <&mpic>; + interrupts = <18 0x2>; + }; + + L2: l2-cache-controller@20000 { + compatible = "fsl,mpc8536-l2-cache-controller"; + reg = <0x20000 0x1000>; + interrupt-parent = <&mpic>; + interrupts = <16 0x2>; + }; + + i2c@3000 { + #address-cells = <1>; + #size-cells = <0>; + cell-index = <0>; + compatible = "fsl-i2c"; + reg = <0x3000 0x100>; + interrupts = <43 0x2>; + interrupt-parent = <&mpic>; + dfsrr; + }; + + i2c@3100 { + #address-cells = <1>; + #size-cells = <0>; + cell-index = <1>; + compatible = "fsl-i2c"; + reg = <0x3100 0x100>; + interrupts = <43 0x2>; + interrupt-parent = <&mpic>; + dfsrr; + rtc@68 { + compatible = "dallas,ds3232"; + reg = <0x68>; + }; + }; + + dma@21300 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,mpc8536-dma", "fsl,eloplus-dma"; + reg = <0x21300 4>; + ranges = <0 0x21100 0x200>; + cell-index = <0>; + dma-channel@0 { + compatible = "fsl,mpc8536-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x0 0x80>; + cell-index = <0>; + interrupt-parent = <&mpic>; + interrupts = <14 0x2>; + }; + dma-channel@80 { + compatible = "fsl,mpc8536-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x80 0x80>; + cell-index = <1>; + interrupt-parent = <&mpic>; + interrupts = <15 0x2>; + }; + dma-channel@100 { + compatible = "fsl,mpc8536-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x100 0x80>; + cell-index = <2>; + interrupt-parent = <&mpic>; + interrupts = <16 0x2>; + }; + dma-channel@180 { + compatible = "fsl,mpc8536-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x180 0x80>; + cell-index = <3>; + interrupt-parent = <&mpic>; + interrupts = <17 0x2>; + }; + }; + + mdio@24520 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,gianfar-mdio"; + reg = <0x24520 0x20>; + + phy0: ethernet-phy@0 { + interrupt-parent = <&mpic>; + interrupts = <10 0x1>; + reg = <0>; + device_type = "ethernet-phy"; + }; + phy1: ethernet-phy@1 { + interrupt-parent = <&mpic>; + interrupts = <10 0x1>; + reg = <1>; + device_type = "ethernet-phy"; + }; + }; + + usb@22000 { + compatible = "fsl,mpc8536-usb2-mph", "fsl-usb2-mph"; + reg = <0x22000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupt-parent = <&mpic>; + interrupts = <28 0x2>; + phy_type = "ulpi"; + }; + + usb@23000 { + compatible = "fsl,mpc8536-usb2-mph", "fsl-usb2-mph"; + reg = <0x23000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupt-parent = <&mpic>; + interrupts = <46 0x2>; + phy_type = "ulpi"; + }; + + enet0: ethernet@24000 { + cell-index = <0>; + device_type = "network"; + model = "TSEC"; + compatible = "gianfar"; + reg = <0x24000 0x1000>; + local-mac-address = [ 00 00 00 00 00 00 ]; + interrupts = <29 2 30 2 34 2>; + interrupt-parent = <&mpic>; + phy-handle = <&phy1>; + phy-connection-type = "rgmii-id"; + }; + + enet1: ethernet@26000 { + cell-index = <1>; + device_type = "network"; + model = "TSEC"; + compatible = "gianfar"; + reg = <0x26000 0x1000>; + local-mac-address = [ 00 00 00 00 00 00 ]; + interrupts = <31 2 32 2 33 2>; + interrupt-parent = <&mpic>; + phy-handle = <&phy0>; + phy-connection-type = "rgmii-id"; + }; + + usb@2b000 { + compatible = "fsl,mpc8536-usb2-dr", "fsl-usb2-dr"; + reg = <0x2b000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupt-parent = <&mpic>; + interrupts = <60 0x2>; + dr_mode = "peripheral"; + phy_type = "ulpi"; + }; + + serial0: serial@4500 { + cell-index = <0>; + device_type = "serial"; + compatible = "ns16550"; + reg = <0x4500 0x100>; + clock-frequency = <0>; + interrupts = <42 0x2>; + interrupt-parent = <&mpic>; + }; + + serial1: serial@4600 { + cell-index = <1>; + device_type = "serial"; + compatible = "ns16550"; + reg = <0x4600 0x100>; + clock-frequency = <0>; + interrupts = <42 0x2>; + interrupt-parent = <&mpic>; + }; + + sata@18000 { + compatible = "fsl,mpc8536-sata", "fsl,pq-sata"; + reg = <0x18000 0x1000>; + cell-index = <1>; + interrupts = <74 0x2>; + interrupt-parent = <&mpic>; + }; + + sata@19000 { + compatible = "fsl,mpc8536-sata", "fsl,pq-sata"; + reg = <0x19000 0x1000>; + cell-index = <2>; + interrupts = <41 0x2>; + interrupt-parent = <&mpic>; + }; + + global-utilities@e0000 { //global utilities block + compatible = "fsl,mpc8548-guts"; + reg = <0xe0000 0x1000>; + fsl,has-rstcr; + }; + + mpic: pic@40000 { + clock-frequency = <0>; + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <2>; + reg = <0x40000 0x40000>; + compatible = "chrp,open-pic"; + device_type = "open-pic"; + big-endian; + }; + + msi@41600 { + compatible = "fsl,mpc8536-msi", "fsl,mpic-msi"; + reg = <0x41600 0x80>; + msi-available-ranges = <0 0x100>; + interrupts = < + 0xe0 0 + 0xe1 0 + 0xe2 0 + 0xe3 0 + 0xe4 0 + 0xe5 0 + 0xe6 0 + 0xe7 0>; + interrupt-parent = <&mpic>; + }; + }; + + pci0: pci@ffe08000 { + cell-index = <0>; + compatible = "fsl,mpc8540-pci"; + device_type = "pci"; + interrupt-map-mask = <0xf800 0x0 0x0 0x7>; + interrupt-map = < + + /* IDSEL 0x11 J17 Slot 1 */ + 0x8800 0 0 1 &mpic 1 1 + 0x8800 0 0 2 &mpic 2 1 + 0x8800 0 0 3 &mpic 3 1 + 0x8800 0 0 4 &mpic 4 1>; + + interrupt-parent = <&mpic>; + interrupts = <24 0x2>; + bus-range = <0 0xff>; + ranges = <0x02000000 0 0x80000000 0x80000000 0 0x10000000 + 0x01000000 0 0x00000000 0xffc00000 0 0x00010000>; + clock-frequency = <66666666>; + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + reg = <0xffe08000 0x1000>; + }; + + pci1: pcie@ffe09000 { + cell-index = <1>; + compatible = "fsl,mpc8548-pcie"; + device_type = "pci"; + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + reg = <0xffe09000 0x1000>; + bus-range = <0 0xff>; + ranges = <0x02000000 0 0x98000000 0x98000000 0 0x08000000 + 0x01000000 0 0x00000000 0xffc20000 0 0x00010000>; + clock-frequency = <33333333>; + interrupt-parent = <&mpic>; + interrupts = <25 0x2>; + interrupt-map-mask = <0xf800 0 0 7>; + interrupt-map = < + /* IDSEL 0x0 */ + 0000 0 0 1 &mpic 4 1 + 0000 0 0 2 &mpic 5 1 + 0000 0 0 3 &mpic 6 1 + 0000 0 0 4 &mpic 7 1 + >; + pcie@0 { + reg = <0 0 0 0 0>; + #size-cells = <2>; + #address-cells = <3>; + device_type = "pci"; + ranges = <0x02000000 0 0x98000000 + 0x02000000 0 0x98000000 + 0 0x08000000 + + 0x01000000 0 0x00000000 + 0x01000000 0 0x00000000 + 0 0x00010000>; + }; + }; + + pci2: pcie@ffe0a000 { + cell-index = <2>; + compatible = "fsl,mpc8548-pcie"; + device_type = "pci"; + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + reg = <0xffe0a000 0x1000>; + bus-range = <0 0xff>; + ranges = <0x02000000 0 0x90000000 0x90000000 0 0x08000000 + 0x01000000 0 0x00000000 0xffc10000 0 0x00010000>; + clock-frequency = <33333333>; + interrupt-parent = <&mpic>; + interrupts = <26 0x2>; + interrupt-map-mask = <0xf800 0 0 7>; + interrupt-map = < + /* IDSEL 0x0 */ + 0000 0 0 1 &mpic 0 1 + 0000 0 0 2 &mpic 1 1 + 0000 0 0 3 &mpic 2 1 + 0000 0 0 4 &mpic 3 1 + >; + pcie@0 { + reg = <0 0 0 0 0>; + #size-cells = <2>; + #address-cells = <3>; + device_type = "pci"; + ranges = <0x02000000 0 0x90000000 + 0x02000000 0 0x90000000 + 0 0x08000000 + + 0x01000000 0 0x00000000 + 0x01000000 0 0x00000000 + 0 0x00010000>; + }; + }; + + pci3: pcie@ffe0b000 { + cell-index = <3>; + compatible = "fsl,mpc8548-pcie"; + device_type = "pci"; + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + reg = <0xffe0b000 0x1000>; + bus-range = <0 0xff>; + ranges = <0x02000000 0 0xa0000000 0xa0000000 0 0x20000000 + 0x01000000 0 0x00000000 0xffc30000 0 0x00010000>; + clock-frequency = <33333333>; + interrupt-parent = <&mpic>; + interrupts = <27 0x2>; + interrupt-map-mask = <0xf800 0 0 7>; + interrupt-map = < + /* IDSEL 0x0 */ + 0000 0 0 1 &mpic 8 1 + 0000 0 0 2 &mpic 9 1 + 0000 0 0 3 &mpic 10 1 + 0000 0 0 4 &mpic 11 1 + >; + + pcie@0 { + reg = <0 0 0 0 0>; + #size-cells = <2>; + #address-cells = <3>; + device_type = "pci"; + ranges = <0x02000000 0 0xa0000000 + 0x02000000 0 0xa0000000 + 0 0x20000000 + + 0x01000000 0 0x00000000 + 0x01000000 0 0x00000000 + 0 0x00100000>; + }; + }; +}; -- cgit v1.1 From a5d28c8e64ff0bc77d38d9c19c6d8163e4c0ffaa Mon Sep 17 00:00:00 2001 From: Jochen Friedrich Date: Wed, 2 Jul 2008 18:06:13 +0200 Subject: powerpc/CPM: Add i2c pins to dts and board setup Initialize I2C pins on boards with CPM1/CPM2 controllers and document the i2c bus in booting-without-of. The boards don't have any I2C chips connected to the I2C bus, so unless some external chips are connected to the boards, this code is just an example of setting everything else up. Signed-off-by: Jochen Friedrich Signed-off-by: Kumar Gala --- arch/powerpc/boot/dts/mpc8272ads.dts | 11 +++++++++++ arch/powerpc/boot/dts/mpc866ads.dts | 11 +++++++++++ arch/powerpc/boot/dts/mpc885ads.dts | 11 +++++++++++ 3 files changed, 33 insertions(+) (limited to 'arch/powerpc/boot') diff --git a/arch/powerpc/boot/dts/mpc8272ads.dts b/arch/powerpc/boot/dts/mpc8272ads.dts index 46e2da3..d27f8a7 100644 --- a/arch/powerpc/boot/dts/mpc8272ads.dts +++ b/arch/powerpc/boot/dts/mpc8272ads.dts @@ -217,6 +217,17 @@ linux,network-index = <1>; fsl,cpm-command = <0x16200300>; }; + + i2c@11860 { + compatible = "fsl,mpc8272-i2c", + "fsl,cpm2-i2c"; + reg = <0x11860 0x20 0x8afc 0x2>; + interrupts = <1 8>; + interrupt-parent = <&PIC>; + fsl,cpm-command = <0x29600000>; + #address-cells = <1>; + #size-cells = <0>; + }; }; PIC: interrupt-controller@10c00 { diff --git a/arch/powerpc/boot/dts/mpc866ads.dts b/arch/powerpc/boot/dts/mpc866ads.dts index 765e43c..bd70065 100644 --- a/arch/powerpc/boot/dts/mpc866ads.dts +++ b/arch/powerpc/boot/dts/mpc866ads.dts @@ -171,6 +171,17 @@ fsl,cpm-command = <0000>; linux,network-index = <1>; }; + + i2c@860 { + compatible = "fsl,mpc866-i2c", + "fsl,cpm1-i2c"; + reg = <0x860 0x20 0x3c80 0x30>; + interrupts = <16>; + interrupt-parent = <&CPM_PIC>; + fsl,cpm-command = <0x10>; + #address-cells = <1>; + #size-cells = <0>; + }; }; }; diff --git a/arch/powerpc/boot/dts/mpc885ads.dts b/arch/powerpc/boot/dts/mpc885ads.dts index 9895043..b123e9f 100644 --- a/arch/powerpc/boot/dts/mpc885ads.dts +++ b/arch/powerpc/boot/dts/mpc885ads.dts @@ -215,6 +215,17 @@ fsl,cpm-command = <0x80>; linux,network-index = <2>; }; + + i2c@860 { + compatible = "fsl,mpc885-i2c", + "fsl,cpm1-i2c"; + reg = <0x860 0x20 0x3c80 0x30>; + interrupts = <16>; + interrupt-parent = <&CPM_PIC>; + fsl,cpm-command = <0x10>; + #address-cells = <1>; + #size-cells = <0>; + }; }; }; -- cgit v1.1 From 3fd44736db9a5bf33e4a216b9cd43c9cfd57c459 Mon Sep 17 00:00:00 2001 From: Kim Phillips Date: Tue, 8 Jul 2008 19:13:33 -0500 Subject: powerpc/fsl: update crypto node definition and device tree instances delete obsolete device-type property, delete model property (use compatible property instead), prepend "fsl," to Freescale specific properties. Add nodes to device trees that are missing them, and fix broken property values in other trees. Signed-off-by: Kim Phillips Signed-off-by: Kumar Gala --- arch/powerpc/boot/dts/mpc8272ads.dts | 21 +++++++-------------- arch/powerpc/boot/dts/mpc8313erdb.dts | 15 ++++++--------- arch/powerpc/boot/dts/mpc8315erdb.dts | 15 +++++++-------- arch/powerpc/boot/dts/mpc832x_mds.dts | 15 ++++++--------- arch/powerpc/boot/dts/mpc832x_rdb.dts | 15 ++++++--------- arch/powerpc/boot/dts/mpc8349emitx.dts | 12 +++++------- arch/powerpc/boot/dts/mpc8349emitxgp.dts | 12 +++++------- arch/powerpc/boot/dts/mpc834x_mds.dts | 15 +++++---------- arch/powerpc/boot/dts/mpc836x_mds.dts | 13 +++++-------- arch/powerpc/boot/dts/mpc8377_mds.dts | 13 ++++++------- arch/powerpc/boot/dts/mpc8377_rdb.dts | 14 ++++++-------- arch/powerpc/boot/dts/mpc8378_mds.dts | 13 ++++++------- arch/powerpc/boot/dts/mpc8378_rdb.dts | 14 ++++++-------- arch/powerpc/boot/dts/mpc8379_mds.dts | 13 ++++++------- arch/powerpc/boot/dts/mpc8379_rdb.dts | 14 ++++++-------- arch/powerpc/boot/dts/mpc8536ds.dts | 12 ++++++++++++ arch/powerpc/boot/dts/mpc8541cds.dts | 11 +++++++++++ arch/powerpc/boot/dts/mpc8544ds.dts | 11 +++++++++++ arch/powerpc/boot/dts/mpc8548cds.dts | 11 +++++++++++ arch/powerpc/boot/dts/mpc8555cds.dts | 11 +++++++++++ arch/powerpc/boot/dts/mpc8568mds.dts | 14 ++++++-------- arch/powerpc/boot/dts/mpc8572ds.dts | 12 ++++++++++++ arch/powerpc/boot/dts/sbc8349.dts | 14 +++++--------- arch/powerpc/boot/dts/sbc8548.dts | 11 +++++++++++ arch/powerpc/boot/dts/tqm8541.dts | 11 +++++++++++ arch/powerpc/boot/dts/tqm8555.dts | 11 +++++++++++ 26 files changed, 200 insertions(+), 143 deletions(-) (limited to 'arch/powerpc/boot') diff --git a/arch/powerpc/boot/dts/mpc8272ads.dts b/arch/powerpc/boot/dts/mpc8272ads.dts index d27f8a7..2a1929a 100644 --- a/arch/powerpc/boot/dts/mpc8272ads.dts +++ b/arch/powerpc/boot/dts/mpc8272ads.dts @@ -237,22 +237,15 @@ compatible = "fsl,mpc8272-pic", "fsl,cpm2-pic"; }; -/* May need to remove if on a part without crypto engine */ crypto@30000 { - device_type = "crypto"; - model = "SEC2"; - compatible = "fsl,mpc8272-talitos-sec2", - "fsl,talitos-sec2", - "fsl,talitos", - "talitos"; - reg = <0x30000 0x10000>; - interrupts = <11 8>; + compatible = "fsl,sec1.0"; + reg = <0x40000 0x13000>; + interrupts = <47 0x8>; interrupt-parent = <&PIC>; - num-channels = <4>; - channel-fifo-len = <24>; - exec-units-mask = <0x7e>; -/* desc mask is for rev1.x, we need runtime fixup for >=2.x */ - descriptor-types-mask = <0x1010ebf>; + fsl,num-channels = <4>; + fsl,channel-fifo-len = <24>; + fsl,exec-units-mask = <0x7e>; + fsl,descriptor-types-mask = <0x1010415>; }; }; diff --git a/arch/powerpc/boot/dts/mpc8313erdb.dts b/arch/powerpc/boot/dts/mpc8313erdb.dts index b206843..3664fb5 100644 --- a/arch/powerpc/boot/dts/mpc8313erdb.dts +++ b/arch/powerpc/boot/dts/mpc8313erdb.dts @@ -254,17 +254,14 @@ }; crypto@30000 { - device_type = "crypto"; - model = "SEC2"; - compatible = "talitos"; - reg = <0x30000 0x7000>; + compatible = "fsl,sec2.2", "fsl,sec2.1", "fsl,sec2.0"; + reg = <0x30000 0x10000>; interrupts = <11 0x8>; interrupt-parent = <&ipic>; - /* Rev. 2.2 */ - num-channels = <1>; - channel-fifo-len = <24>; - exec-units-mask = <0x0000004c>; - descriptor-types-mask = <0x0122003f>; + fsl,num-channels = <1>; + fsl,channel-fifo-len = <24>; + fsl,exec-units-mask = <0x4c>; + fsl,descriptor-types-mask = <0x0122003f>; }; /* IPIC diff --git a/arch/powerpc/boot/dts/mpc8315erdb.dts b/arch/powerpc/boot/dts/mpc8315erdb.dts index a40e806..f704513 100644 --- a/arch/powerpc/boot/dts/mpc8315erdb.dts +++ b/arch/powerpc/boot/dts/mpc8315erdb.dts @@ -241,17 +241,16 @@ }; crypto@30000 { - model = "SEC3"; - device_type = "crypto"; - compatible = "talitos"; + compatible = "fsl,sec3.3", "fsl,sec3.1", "fsl,sec3.0", + "fsl,sec2.4", "fsl,sec2.2", "fsl,sec2.1", + "fsl,sec2.0"; reg = <0x30000 0x10000>; interrupts = <11 0x8>; interrupt-parent = <&ipic>; - /* Rev. 3.0 geometry */ - num-channels = <4>; - channel-fifo-len = <24>; - exec-units-mask = <0x000001fe>; - descriptor-types-mask = <0x03ab0ebf>; + fsl,num-channels = <4>; + fsl,channel-fifo-len = <24>; + fsl,exec-units-mask = <0x97c>; + fsl,descriptor-types-mask = <0x3ab0abf>; }; sata@18000 { diff --git a/arch/powerpc/boot/dts/mpc832x_mds.dts b/arch/powerpc/boot/dts/mpc832x_mds.dts index b5968b6..7345743 100644 --- a/arch/powerpc/boot/dts/mpc832x_mds.dts +++ b/arch/powerpc/boot/dts/mpc832x_mds.dts @@ -150,17 +150,14 @@ }; crypto@30000 { - device_type = "crypto"; - model = "SEC2"; - compatible = "talitos"; - reg = <0x30000 0x7000>; + compatible = "fsl,sec2.2", "fsl,sec2.1", "fsl,sec2.0"; + reg = <0x30000 0x10000>; interrupts = <11 0x8>; interrupt-parent = <&ipic>; - /* Rev. 2.2 */ - num-channels = <1>; - channel-fifo-len = <24>; - exec-units-mask = <0x0000004c>; - descriptor-types-mask = <0x0122003f>; + fsl,num-channels = <1>; + fsl,channel-fifo-len = <24>; + fsl,exec-units-mask = <0x4c>; + fsl,descriptor-types-mask = <0x0122003f>; }; ipic: pic@700 { diff --git a/arch/powerpc/boot/dts/mpc832x_rdb.dts b/arch/powerpc/boot/dts/mpc832x_rdb.dts index a798d86..e74c045 100644 --- a/arch/powerpc/boot/dts/mpc832x_rdb.dts +++ b/arch/powerpc/boot/dts/mpc832x_rdb.dts @@ -128,17 +128,14 @@ }; crypto@30000 { - device_type = "crypto"; - model = "SEC2"; - compatible = "talitos"; - reg = <0x30000 0x7000>; + compatible = "fsl,sec2.2", "fsl,sec2.1", "fsl,sec2.0"; + reg = <0x30000 0x10000>; interrupts = <11 0x8>; interrupt-parent = <&ipic>; - /* Rev. 2.2 */ - num-channels = <1>; - channel-fifo-len = <24>; - exec-units-mask = <0x0000004c>; - descriptor-types-mask = <0x0122003f>; + fsl,num-channels = <1>; + fsl,channel-fifo-len = <24>; + fsl,exec-units-mask = <0x4c>; + fsl,descriptor-types-mask = <0x0122003f>; }; ipic:pic@700 { diff --git a/arch/powerpc/boot/dts/mpc8349emitx.dts b/arch/powerpc/boot/dts/mpc8349emitx.dts index fc0f4c9..8dfab56 100644 --- a/arch/powerpc/boot/dts/mpc8349emitx.dts +++ b/arch/powerpc/boot/dts/mpc8349emitx.dts @@ -213,16 +213,14 @@ }; crypto@30000 { - device_type = "crypto"; - model = "SEC2"; - compatible = "talitos"; + compatible = "fsl,sec2.0"; reg = <0x30000 0x10000>; interrupts = <11 0x8>; interrupt-parent = <&ipic>; - num-channels = <4>; - channel-fifo-len = <24>; - exec-units-mask = <0x0000007e>; - descriptor-types-mask = <0x01010ebf>; + fsl,num-channels = <4>; + fsl,channel-fifo-len = <24>; + fsl,exec-units-mask = <0x7e>; + fsl,descriptor-types-mask = <0x01010ebf>; }; ipic: pic@700 { diff --git a/arch/powerpc/boot/dts/mpc8349emitxgp.dts b/arch/powerpc/boot/dts/mpc8349emitxgp.dts index e6afb1d..49ca349 100644 --- a/arch/powerpc/boot/dts/mpc8349emitxgp.dts +++ b/arch/powerpc/boot/dts/mpc8349emitxgp.dts @@ -186,16 +186,14 @@ }; crypto@30000 { - device_type = "crypto"; - model = "SEC2"; - compatible = "talitos"; + compatible = "fsl,sec2.0"; reg = <0x30000 0x10000>; interrupts = <11 0x8>; interrupt-parent = <&ipic>; - num-channels = <4>; - channel-fifo-len = <24>; - exec-units-mask = <0x0000007e>; - descriptor-types-mask = <0x01010ebf>; + fsl,num-channels = <4>; + fsl,channel-fifo-len = <24>; + fsl,exec-units-mask = <0x7e>; + fsl,descriptor-types-mask = <0x01010ebf>; }; ipic: pic@700 { diff --git a/arch/powerpc/boot/dts/mpc834x_mds.dts b/arch/powerpc/boot/dts/mpc834x_mds.dts index 9c75c7c..ba586cb 100644 --- a/arch/powerpc/boot/dts/mpc834x_mds.dts +++ b/arch/powerpc/boot/dts/mpc834x_mds.dts @@ -228,20 +228,15 @@ interrupt-parent = <&ipic>; }; - /* May need to remove if on a part without crypto engine */ crypto@30000 { - device_type = "crypto"; - model = "SEC2"; - compatible = "talitos"; + compatible = "fsl,sec2.0"; reg = <0x30000 0x10000>; interrupts = <11 0x8>; interrupt-parent = <&ipic>; - num-channels = <4>; - channel-fifo-len = <24>; - exec-units-mask = <0x0000007e>; - /* desc mask is for rev2.0, - * we need runtime fixup for >2.0 */ - descriptor-types-mask = <0x01010ebf>; + fsl,num-channels = <4>; + fsl,channel-fifo-len = <24>; + fsl,exec-units-mask = <0x7e>; + fsl,descriptor-types-mask = <0x01010ebf>; }; /* IPIC diff --git a/arch/powerpc/boot/dts/mpc836x_mds.dts b/arch/powerpc/boot/dts/mpc836x_mds.dts index 8e33b15..3701dae 100644 --- a/arch/powerpc/boot/dts/mpc836x_mds.dts +++ b/arch/powerpc/boot/dts/mpc836x_mds.dts @@ -154,17 +154,14 @@ }; crypto@30000 { - device_type = "crypto"; - model = "SEC2"; - compatible = "talitos"; + compatible = "fsl,sec2.0"; reg = <0x30000 0x10000>; interrupts = <11 0x8>; interrupt-parent = <&ipic>; - num-channels = <4>; - channel-fifo-len = <24>; - exec-units-mask = <0x0000007e>; - /* desc mask is for rev1.x, we need runtime fixup for >=2.x */ - descriptor-types-mask = <0x01010ebf>; + fsl,num-channels = <4>; + fsl,channel-fifo-len = <24>; + fsl,exec-units-mask = <0x7e>; + fsl,descriptor-types-mask = <0x01010ebf>; }; ipic: pic@700 { diff --git a/arch/powerpc/boot/dts/mpc8377_mds.dts b/arch/powerpc/boot/dts/mpc8377_mds.dts index 49a38cb..0a700cb 100644 --- a/arch/powerpc/boot/dts/mpc8377_mds.dts +++ b/arch/powerpc/boot/dts/mpc8377_mds.dts @@ -269,16 +269,15 @@ }; crypto@30000 { - model = "SEC3"; - compatible = "talitos"; + compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2", + "fsl,sec2.1", "fsl,sec2.0"; reg = <0x30000 0x10000>; interrupts = <11 0x8>; interrupt-parent = <&ipic>; - /* Rev. 3.0 geometry */ - num-channels = <4>; - channel-fifo-len = <24>; - exec-units-mask = <0x000001fe>; - descriptor-types-mask = <0x03ab0ebf>; + fsl,num-channels = <4>; + fsl,channel-fifo-len = <24>; + fsl,exec-units-mask = <0x9fe>; + fsl,descriptor-types-mask = <0x3ab0ebf>; }; sdhc@2e000 { diff --git a/arch/powerpc/boot/dts/mpc8377_rdb.dts b/arch/powerpc/boot/dts/mpc8377_rdb.dts index 1f45387..ed137aa 100644 --- a/arch/powerpc/boot/dts/mpc8377_rdb.dts +++ b/arch/powerpc/boot/dts/mpc8377_rdb.dts @@ -248,17 +248,15 @@ }; crypto@30000 { - model = "SEC3"; - device_type = "crypto"; - compatible = "talitos"; + compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2", + "fsl,sec2.1", "fsl,sec2.0"; reg = <0x30000 0x10000>; interrupts = <11 0x8>; interrupt-parent = <&ipic>; - /* Rev. 3.0 geometry */ - num-channels = <4>; - channel-fifo-len = <24>; - exec-units-mask = <0x000001fe>; - descriptor-types-mask = <0x03ab0ebf>; + fsl,num-channels = <4>; + fsl,channel-fifo-len = <24>; + fsl,exec-units-mask = <0x9fe>; + fsl,descriptor-types-mask = <0x3ab0ebf>; }; sata@18000 { diff --git a/arch/powerpc/boot/dts/mpc8378_mds.dts b/arch/powerpc/boot/dts/mpc8378_mds.dts index 99ad49d..29c8c76 100644 --- a/arch/powerpc/boot/dts/mpc8378_mds.dts +++ b/arch/powerpc/boot/dts/mpc8378_mds.dts @@ -269,16 +269,15 @@ }; crypto@30000 { - model = "SEC3"; - compatible = "talitos"; + compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2", + "fsl,sec2.1", "fsl,sec2.0"; reg = <0x30000 0x10000>; interrupts = <11 0x8>; interrupt-parent = <&ipic>; - /* Rev. 3.0 geometry */ - num-channels = <4>; - channel-fifo-len = <24>; - exec-units-mask = <0x000001fe>; - descriptor-types-mask = <0x03ab0ebf>; + fsl,num-channels = <4>; + fsl,channel-fifo-len = <24>; + fsl,exec-units-mask = <0x9fe>; + fsl,descriptor-types-mask = <0x3ab0ebf>; }; sdhc@2e000 { diff --git a/arch/powerpc/boot/dts/mpc8378_rdb.dts b/arch/powerpc/boot/dts/mpc8378_rdb.dts index 44e34d3..34a7f2f 100644 --- a/arch/powerpc/boot/dts/mpc8378_rdb.dts +++ b/arch/powerpc/boot/dts/mpc8378_rdb.dts @@ -248,17 +248,15 @@ }; crypto@30000 { - model = "SEC3"; - device_type = "crypto"; - compatible = "talitos"; + compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2", + "fsl,sec2.1", "fsl,sec2.0"; reg = <0x30000 0x10000>; interrupts = <11 0x8>; interrupt-parent = <&ipic>; - /* Rev. 3.0 geometry */ - num-channels = <4>; - channel-fifo-len = <24>; - exec-units-mask = <0x000001fe>; - descriptor-types-mask = <0x03ab0ebf>; + fsl,num-channels = <4>; + fsl,channel-fifo-len = <24>; + fsl,exec-units-mask = <0x9fe>; + fsl,descriptor-types-mask = <0x3ab0ebf>; }; /* IPIC diff --git a/arch/powerpc/boot/dts/mpc8379_mds.dts b/arch/powerpc/boot/dts/mpc8379_mds.dts index 980be81..d641a89 100644 --- a/arch/powerpc/boot/dts/mpc8379_mds.dts +++ b/arch/powerpc/boot/dts/mpc8379_mds.dts @@ -269,16 +269,15 @@ }; crypto@30000 { - model = "SEC3"; - compatible = "talitos"; + compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2", + "fsl,sec2.1", "fsl,sec2.0"; reg = <0x30000 0x10000>; interrupts = <11 0x8>; interrupt-parent = <&ipic>; - /* Rev. 3.0 geometry */ - num-channels = <4>; - channel-fifo-len = <24>; - exec-units-mask = <0x000001fe>; - descriptor-types-mask = <0x03ab0ebf>; + fsl,num-channels = <4>; + fsl,channel-fifo-len = <24>; + fsl,exec-units-mask = <0x9fe>; + fsl,descriptor-types-mask = <0x3ab0ebf>; }; sdhc@2e000 { diff --git a/arch/powerpc/boot/dts/mpc8379_rdb.dts b/arch/powerpc/boot/dts/mpc8379_rdb.dts index eeedf58..e4d7030 100644 --- a/arch/powerpc/boot/dts/mpc8379_rdb.dts +++ b/arch/powerpc/boot/dts/mpc8379_rdb.dts @@ -248,17 +248,15 @@ }; crypto@30000 { - model = "SEC3"; - device_type = "crypto"; - compatible = "talitos"; + compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2", + "fsl,sec2.1", "fsl,sec2.0"; reg = <0x30000 0x10000>; interrupts = <11 0x8>; interrupt-parent = <&ipic>; - /* Rev. 3.0 geometry */ - num-channels = <4>; - channel-fifo-len = <24>; - exec-units-mask = <0x000001fe>; - descriptor-types-mask = <0x03ab0ebf>; + fsl,num-channels = <4>; + fsl,channel-fifo-len = <24>; + fsl,exec-units-mask = <0x9fe>; + fsl,descriptor-types-mask = <0x3ab0ebf>; }; sata@18000 { diff --git a/arch/powerpc/boot/dts/mpc8536ds.dts b/arch/powerpc/boot/dts/mpc8536ds.dts index 98ad27a..02cfa24 100644 --- a/arch/powerpc/boot/dts/mpc8536ds.dts +++ b/arch/powerpc/boot/dts/mpc8536ds.dts @@ -231,6 +231,18 @@ interrupt-parent = <&mpic>; }; + crypto@30000 { + compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2", + "fsl,sec2.1", "fsl,sec2.0"; + reg = <0x30000 0x10000>; + interrupts = <45 2 58 2>; + interrupt-parent = <&mpic>; + fsl,num-channels = <4>; + fsl,channel-fifo-len = <24>; + fsl,exec-units-mask = <0x9fe>; + fsl,descriptor-types-mask = <0x3ab0ebf>; + }; + sata@18000 { compatible = "fsl,mpc8536-sata", "fsl,pq-sata"; reg = <0x18000 0x1000>; diff --git a/arch/powerpc/boot/dts/mpc8541cds.dts b/arch/powerpc/boot/dts/mpc8541cds.dts index 21ad71b..c4469f1 100644 --- a/arch/powerpc/boot/dts/mpc8541cds.dts +++ b/arch/powerpc/boot/dts/mpc8541cds.dts @@ -189,6 +189,17 @@ interrupt-parent = <&mpic>; }; + crypto@30000 { + compatible = "fsl,sec2.0"; + reg = <0x30000 0x10000>; + interrupts = <45 2>; + interrupt-parent = <&mpic>; + fsl,num-channels = <4>; + fsl,channel-fifo-len = <24>; + fsl,exec-units-mask = <0x7e>; + fsl,descriptor-types-mask = <0x01010ebf>; + }; + mpic: pic@40000 { interrupt-controller; #address-cells = <0>; diff --git a/arch/powerpc/boot/dts/mpc8544ds.dts b/arch/powerpc/boot/dts/mpc8544ds.dts index 6cf533f..7d3829d 100644 --- a/arch/powerpc/boot/dts/mpc8544ds.dts +++ b/arch/powerpc/boot/dts/mpc8544ds.dts @@ -210,6 +210,17 @@ fsl,has-rstcr; }; + crypto@30000 { + compatible = "fsl,sec2.1", "fsl,sec2.0"; + reg = <0x30000 0x10000>; + interrupts = <45 2>; + interrupt-parent = <&mpic>; + fsl,num-channels = <4>; + fsl,channel-fifo-len = <24>; + fsl,exec-units-mask = <0xfe>; + fsl,descriptor-types-mask = <0x12b0ebf>; + }; + mpic: pic@40000 { interrupt-controller; #address-cells = <0>; diff --git a/arch/powerpc/boot/dts/mpc8548cds.dts b/arch/powerpc/boot/dts/mpc8548cds.dts index d1fa6bb..d84466b 100644 --- a/arch/powerpc/boot/dts/mpc8548cds.dts +++ b/arch/powerpc/boot/dts/mpc8548cds.dts @@ -249,6 +249,17 @@ fsl,has-rstcr; }; + crypto@30000 { + compatible = "fsl,sec2.1", "fsl,sec2.0"; + reg = <0x30000 0x10000>; + interrupts = <45 2>; + interrupt-parent = <&mpic>; + fsl,num-channels = <4>; + fsl,channel-fifo-len = <24>; + fsl,exec-units-mask = <0xfe>; + fsl,descriptor-types-mask = <0x12b0ebf>; + }; + mpic: pic@40000 { interrupt-controller; #address-cells = <0>; diff --git a/arch/powerpc/boot/dts/mpc8555cds.dts b/arch/powerpc/boot/dts/mpc8555cds.dts index 6fc8059..e03a780 100644 --- a/arch/powerpc/boot/dts/mpc8555cds.dts +++ b/arch/powerpc/boot/dts/mpc8555cds.dts @@ -189,6 +189,17 @@ interrupt-parent = <&mpic>; }; + crypto@30000 { + compatible = "fsl,sec2.0"; + reg = <0x30000 0x10000>; + interrupts = <45 2>; + interrupt-parent = <&mpic>; + fsl,num-channels = <4>; + fsl,channel-fifo-len = <24>; + fsl,exec-units-mask = <0x7e>; + fsl,descriptor-types-mask = <0x01010ebf>; + }; + mpic: pic@40000 { interrupt-controller; #address-cells = <0>; diff --git a/arch/powerpc/boot/dts/mpc8568mds.dts b/arch/powerpc/boot/dts/mpc8568mds.dts index be9a289..9c30a34 100644 --- a/arch/powerpc/boot/dts/mpc8568mds.dts +++ b/arch/powerpc/boot/dts/mpc8568mds.dts @@ -231,16 +231,14 @@ }; crypto@30000 { - device_type = "crypto"; - model = "SEC2"; - compatible = "talitos"; - reg = <0x30000 0xf000>; + compatible = "fsl,sec2.1", "fsl,sec2.0"; + reg = <0x30000 0x10000>; interrupts = <45 2>; interrupt-parent = <&mpic>; - num-channels = <4>; - channel-fifo-len = <24>; - exec-units-mask = <0xfe>; - descriptor-types-mask = <0x12b0ebf>; + fsl,num-channels = <4>; + fsl,channel-fifo-len = <24>; + fsl,exec-units-mask = <0xfe>; + fsl,descriptor-types-mask = <0x12b0ebf>; }; mpic: pic@40000 { diff --git a/arch/powerpc/boot/dts/mpc8572ds.dts b/arch/powerpc/boot/dts/mpc8572ds.dts index cb06325..08c61e3 100644 --- a/arch/powerpc/boot/dts/mpc8572ds.dts +++ b/arch/powerpc/boot/dts/mpc8572ds.dts @@ -321,6 +321,18 @@ interrupt-parent = <&mpic>; }; + crypto@30000 { + compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2", + "fsl,sec2.1", "fsl,sec2.0"; + reg = <0x30000 0x10000>; + interrupts = <45 2 58 2>; + interrupt-parent = <&mpic>; + fsl,num-channels = <4>; + fsl,channel-fifo-len = <24>; + fsl,exec-units-mask = <0x9fe>; + fsl,descriptor-types-mask = <0x3ab0ebf>; + }; + mpic: pic@40000 { interrupt-controller; #address-cells = <0>; diff --git a/arch/powerpc/boot/dts/sbc8349.dts b/arch/powerpc/boot/dts/sbc8349.dts index 5b76bb2..45f789b 100644 --- a/arch/powerpc/boot/dts/sbc8349.dts +++ b/arch/powerpc/boot/dts/sbc8349.dts @@ -221,19 +221,15 @@ interrupt-parent = <&ipic>; }; - /* May need to remove if on a part without crypto engine */ crypto@30000 { - model = "SEC2"; - compatible = "talitos"; + compatible = "fsl,sec2.0"; reg = <0x30000 0x10000>; interrupts = <11 0x8>; interrupt-parent = <&ipic>; - num-channels = <4>; - channel-fifo-len = <24>; - exec-units-mask = <0x0000007e>; - /* desc mask is for rev2.0, - * we need runtime fixup for >2.0 */ - descriptor-types-mask = <0x01010ebf>; + fsl,num-channels = <4>; + fsl,channel-fifo-len = <24>; + fsl,exec-units-mask = <0x7e>; + fsl,descriptor-types-mask = <0x01010ebf>; }; /* IPIC diff --git a/arch/powerpc/boot/dts/sbc8548.dts b/arch/powerpc/boot/dts/sbc8548.dts index 21cbacb..333552b 100644 --- a/arch/powerpc/boot/dts/sbc8548.dts +++ b/arch/powerpc/boot/dts/sbc8548.dts @@ -304,6 +304,17 @@ fsl,has-rstcr; }; + crypto@30000 { + compatible = "fsl,sec2.1", "fsl,sec2.0"; + reg = <0x30000 0x10000>; + interrupts = <45 2>; + interrupt-parent = <&mpic>; + fsl,num-channels = <4>; + fsl,channel-fifo-len = <24>; + fsl,exec-units-mask = <0xfe>; + fsl,descriptor-types-mask = <0x12b0ebf>; + }; + mpic: pic@40000 { interrupt-controller; #address-cells = <0>; diff --git a/arch/powerpc/boot/dts/tqm8541.dts b/arch/powerpc/boot/dts/tqm8541.dts index d083a64..d76441e 100644 --- a/arch/powerpc/boot/dts/tqm8541.dts +++ b/arch/powerpc/boot/dts/tqm8541.dts @@ -200,6 +200,17 @@ interrupt-parent = <&mpic>; }; + crypto@30000 { + compatible = "fsl,sec2.0"; + reg = <0x30000 0x10000>; + interrupts = <45 2>; + interrupt-parent = <&mpic>; + fsl,num-channels = <4>; + fsl,channel-fifo-len = <24>; + fsl,exec-units-mask = <0x7e>; + fsl,descriptor-types-mask = <0x01010ebf>; + }; + mpic: pic@40000 { interrupt-controller; #address-cells = <0>; diff --git a/arch/powerpc/boot/dts/tqm8555.dts b/arch/powerpc/boot/dts/tqm8555.dts index 96b0b94..6f7ea59 100644 --- a/arch/powerpc/boot/dts/tqm8555.dts +++ b/arch/powerpc/boot/dts/tqm8555.dts @@ -200,6 +200,17 @@ interrupt-parent = <&mpic>; }; + crypto@30000 { + compatible = "fsl,sec2.0"; + reg = <0x30000 0x10000>; + interrupts = <45 2>; + interrupt-parent = <&mpic>; + fsl,num-channels = <4>; + fsl,channel-fifo-len = <24>; + fsl,exec-units-mask = <0x7e>; + fsl,descriptor-types-mask = <0x01010ebf>; + }; + mpic: pic@40000 { interrupt-controller; #address-cells = <0>; -- cgit v1.1