From a01fece2e4185ac173abd16d10304d73d47ebf00 Mon Sep 17 00:00:00 2001 From: John David Anglin Date: Wed, 14 Oct 2015 20:32:11 -0400 Subject: parisc: Change L1_CACHE_BYTES to 16 Change L1_CACHE_BYTES to 16 bytes. Tested for 16 days on rp3440. Additional remarks from Helge Deller: Saves ~17 kb of kernel code/data and gives a slight performance improvement in various test cases. Signed-off-by: John David Anglin Signed-off-by: Helge Deller --- arch/parisc/include/asm/cache.h | 18 +++++------------- 1 file changed, 5 insertions(+), 13 deletions(-) (limited to 'arch/parisc/include/asm') diff --git a/arch/parisc/include/asm/cache.h b/arch/parisc/include/asm/cache.h index 47f11c7..3d0e17b 100644 --- a/arch/parisc/include/asm/cache.h +++ b/arch/parisc/include/asm/cache.h @@ -7,20 +7,12 @@ /* - * PA 2.0 processors have 64-byte cachelines; PA 1.1 processors have - * 32-byte cachelines. The default configuration is not for SMP anyway, - * so if you're building for SMP, you should select the appropriate - * processor type. There is a potential livelock danger when running - * a machine with this value set too small, but it's more probable you'll - * just ruin performance. + * PA 2.0 processors have 64 and 128-byte L2 cachelines; PA 1.1 processors + * have 32-byte cachelines. The L1 length appears to be 16 bytes but this + * is not clearly documented. */ -#ifdef CONFIG_PA20 -#define L1_CACHE_BYTES 64 -#define L1_CACHE_SHIFT 6 -#else -#define L1_CACHE_BYTES 32 -#define L1_CACHE_SHIFT 5 -#endif +#define L1_CACHE_BYTES 16 +#define L1_CACHE_SHIFT 4 #ifndef __ASSEMBLY__ -- cgit v1.1