From 2c2277dc8e18eac8a59cdd0c62ca15106ab6f857 Mon Sep 17 00:00:00 2001 From: Helge Deller Date: Wed, 25 Nov 2015 22:43:45 +0100 Subject: parisc: Imporove debug info about space registers and TLB configuration Signed-off-by: Helge Deller --- arch/parisc/include/asm/pdc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/parisc/include/asm') diff --git a/arch/parisc/include/asm/pdc.h b/arch/parisc/include/asm/pdc.h index 7eb616e..451906d 100644 --- a/arch/parisc/include/asm/pdc.h +++ b/arch/parisc/include/asm/pdc.h @@ -63,7 +63,7 @@ struct pdc_tlb_cf { /* for PDC_CACHE (I/D-TLB's) */ tc_page : 1, /* 0 = 2K page-size-machine, 1 = 4k page size */ tc_cst : 3, /* 0 = incoherent operations, else coherent operations */ tc_aid : 5, /* ITLB: width of access ids of processor (encoded!) */ - tc_pad1 : 8; /* ITLB: width of space-registers (encoded) */ + tc_sr : 8; /* ITLB: width of space-registers (encoded) */ }; struct pdc_cache_info { /* main-PDC_CACHE-structure (caches & TLB's) */ -- cgit v1.1