From 99e3b942c62f42c8d5added63305e12372b06daf Mon Sep 17 00:00:00 2001 From: Franck Bui-Huu Date: Thu, 19 Oct 2006 13:19:59 +0200 Subject: [MIPS] page.h: remove __pa() usages. __pa() was used by virt_to_page() and virt_addr_valid(). These latter are used when kernel is initialised so __pa() is not appropriate, we use virt_to_phys() instead. Futhermore __pa() is going to take care of CKSEG0/XKPHYS address mix for 64 bit kernels. This makes __pa() more complex than virt_to_phys() and this extra work is not needed by virt_to_page() and virt_addr_valid(). Eventually it consolidates virt_to_phys() prototype by making its argument 'const'. this avoids some warnings that was due to some virt_to_page() usages which pass const pointer. Signed-off-by: Franck Bui-Huu Signed-off-by: Ralf Baechle --- arch/mips/mm/init.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'arch/mips') diff --git a/arch/mips/mm/init.c b/arch/mips/mm/init.c index 2de4d3c..3049912 100644 --- a/arch/mips/mm/init.c +++ b/arch/mips/mm/init.c @@ -90,9 +90,9 @@ unsigned long setup_zero_pages(void) if (!empty_zero_page) panic("Oh boy, that early out of memory?"); - page = virt_to_page(empty_zero_page); + page = virt_to_page((void *)empty_zero_page); split_page(page, order); - while (page < virt_to_page(empty_zero_page + (PAGE_SIZE << order))) { + while (page < virt_to_page((void *)(empty_zero_page + (PAGE_SIZE << order)))) { SetPageReserved(page); page++; } @@ -448,8 +448,8 @@ void free_init_pages(char *what, unsigned long begin, unsigned long end) unsigned long addr; for (addr = begin; addr < end; addr += PAGE_SIZE) { - ClearPageReserved(virt_to_page(addr)); - init_page_count(virt_to_page(addr)); + ClearPageReserved(virt_to_page((void *)addr)); + init_page_count(virt_to_page((void *)addr)); memset((void *)addr, 0xcc, PAGE_SIZE); free_page(addr); totalram_pages++; -- cgit v1.1 From d4df6d4e7a66b7a9bd57f5dc7d80d6b55dc12dbb Mon Sep 17 00:00:00 2001 From: Franck Bui-Huu Date: Thu, 19 Oct 2006 13:20:01 +0200 Subject: [MIPS] setup.c: get ride of CPHYSADDR() and use new __pa() implementation instead introduced by the previous patch. Indeed this macro can be used now even by the 64 bit kernels with CONFIG_BUILD_ELF64=n config. Signed-off-by: Franck Bui-Huu Signed-off-by: Ralf Baechle --- arch/mips/kernel/setup.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'arch/mips') diff --git a/arch/mips/kernel/setup.c b/arch/mips/kernel/setup.c index 8f6e896..715451a 100644 --- a/arch/mips/kernel/setup.c +++ b/arch/mips/kernel/setup.c @@ -204,12 +204,12 @@ static void __init finalize_initrd(void) printk(KERN_INFO "Initrd not found or empty"); goto disable; } - if (CPHYSADDR(initrd_end) > PFN_PHYS(max_low_pfn)) { + if (__pa(initrd_end) > PFN_PHYS(max_low_pfn)) { printk("Initrd extends beyond end of memory"); goto disable; } - reserve_bootmem(CPHYSADDR(initrd_start), size); + reserve_bootmem(__pa(initrd_start), size); initrd_below_start_ok = 1; printk(KERN_INFO "Initial ramdisk at: 0x%lx (%lu bytes)\n", @@ -260,7 +260,7 @@ static void __init bootmem_init(void) * of usable memory. */ reserved_end = init_initrd(); - reserved_end = PFN_UP(CPHYSADDR(max(reserved_end, (unsigned long)&_end))); + reserved_end = PFN_UP(__pa(max(reserved_end, (unsigned long)&_end))); /* * Find the highest page frame number we have available. -- cgit v1.1 From f5bffe3a9bcd6e5319b5fd3a8109625f8638425a Mon Sep 17 00:00:00 2001 From: Franck Bui-Huu Date: Thu, 19 Oct 2006 13:20:03 +0200 Subject: [MIPS] setup.c: use __pa_symbol() where needed It should fix the broken code in resource_init() too. Signed-off-by: Franck Bui-Huu Signed-off-by: Ralf Baechle --- arch/mips/kernel/setup.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) (limited to 'arch/mips') diff --git a/arch/mips/kernel/setup.c b/arch/mips/kernel/setup.c index 715451a..b52cc97 100644 --- a/arch/mips/kernel/setup.c +++ b/arch/mips/kernel/setup.c @@ -260,7 +260,7 @@ static void __init bootmem_init(void) * of usable memory. */ reserved_end = init_initrd(); - reserved_end = PFN_UP(__pa(max(reserved_end, (unsigned long)&_end))); + reserved_end = PFN_UP(max(__pa(reserved_end), __pa_symbol(&_end))); /* * Find the highest page frame number we have available. @@ -432,10 +432,10 @@ static void __init resource_init(void) if (UNCAC_BASE != IO_BASE) return; - code_resource.start = virt_to_phys(&_text); - code_resource.end = virt_to_phys(&_etext) - 1; - data_resource.start = virt_to_phys(&_etext); - data_resource.end = virt_to_phys(&_edata) - 1; + code_resource.start = __pa_symbol(&_text); + code_resource.end = __pa_symbol(&_etext) - 1; + data_resource.start = __pa_symbol(&_etext); + data_resource.end = __pa_symbol(&_edata) - 1; /* * Request address space for all standard RAM. -- cgit v1.1 From a7837b76b6de932c31d0b7c71176ca8d1213a3ce Mon Sep 17 00:00:00 2001 From: Franck Bui-Huu Date: Thu, 19 Oct 2006 13:20:04 +0200 Subject: [MIPS] setup.c: clean up initrd related code Signed-off-by: Franck Bui-Huu Signed-off-by: Ralf Baechle --- arch/mips/kernel/setup.c | 75 +++++++++++++++++++++++++++++++----------------- arch/mips/mm/init.c | 5 ---- 2 files changed, 48 insertions(+), 32 deletions(-) (limited to 'arch/mips') diff --git a/arch/mips/kernel/setup.c b/arch/mips/kernel/setup.c index b52cc97..89440a0 100644 --- a/arch/mips/kernel/setup.c +++ b/arch/mips/kernel/setup.c @@ -145,13 +145,12 @@ static int __init rd_start_early(char *p) unsigned long start = memparse(p, &p); #ifdef CONFIG_64BIT - /* HACK: Guess if the sign extension was forgotten */ - if (start > 0x0000000080000000 && start < 0x00000000ffffffff) - start |= 0xffffffff00000000UL; + /* Guess if the sign extension was forgotten by bootloader */ + if (start < XKPHYS) + start = (int)start; #endif initrd_start = start; initrd_end += start; - return 0; } early_param("rd_start", rd_start_early); @@ -159,41 +158,64 @@ early_param("rd_start", rd_start_early); static int __init rd_size_early(char *p) { initrd_end += memparse(p, &p); - return 0; } early_param("rd_size", rd_size_early); +/* it returns the next free pfn after initrd */ static unsigned long __init init_initrd(void) { - unsigned long tmp, end, size; + unsigned long end; u32 *initrd_header; - ROOT_DEV = Root_RAM0; - /* * Board specific code or command line parser should have * already set up initrd_start and initrd_end. In these cases * perfom sanity checks and use them if all looks good. */ - size = initrd_end - initrd_start; - if (initrd_end == 0 || size == 0) { - initrd_start = 0; - initrd_end = 0; - } else - return initrd_end; - - end = (unsigned long)&_end; - tmp = PAGE_ALIGN(end) - sizeof(u32) * 2; - if (tmp < end) - tmp += PAGE_SIZE; - - initrd_header = (u32 *)tmp; - if (initrd_header[0] == 0x494E5244) { - initrd_start = (unsigned long)&initrd_header[2]; - initrd_end = initrd_start + initrd_header[1]; + if (initrd_start && initrd_end > initrd_start) + goto sanitize; + + /* + * See if initrd has been added to the kernel image by + * arch/mips/boot/addinitrd.c. In that case a header is + * prepended to initrd and is made up by 8 bytes. The fisrt + * word is a magic number and the second one is the size of + * initrd. Initrd start must be page aligned in any cases. + */ + initrd_header = __va(PAGE_ALIGN(__pa_symbol(&_end) + 8)) - 8; + if (initrd_header[0] != 0x494E5244) + goto disable; + initrd_start = (unsigned long)(initrd_header + 2); + initrd_end = initrd_start + initrd_header[1]; + +sanitize: + if (initrd_start & ~PAGE_MASK) { + printk(KERN_ERR "initrd start must be page aligned\n"); + goto disable; } - return initrd_end; + if (initrd_start < PAGE_OFFSET) { + printk(KERN_ERR "initrd start < PAGE_OFFSET\n"); + goto disable; + } + + /* + * Sanitize initrd addresses. For example firmware + * can't guess if they need to pass them through + * 64-bits values if the kernel has been built in pure + * 32-bit. We need also to switch from KSEG0 to XKPHYS + * addresses now, so the code can now safely use __pa(). + */ + end = __pa(initrd_end); + initrd_end = (unsigned long)__va(end); + initrd_start = (unsigned long)__va(__pa(initrd_start)); + + ROOT_DEV = Root_RAM0; + return PFN_UP(end); +disable: + initrd_start = 0; + initrd_end = 0; + return 0; } static void __init finalize_initrd(void) @@ -259,8 +281,7 @@ static void __init bootmem_init(void) * not selected. Once that done we can determine the low bound * of usable memory. */ - reserved_end = init_initrd(); - reserved_end = PFN_UP(max(__pa(reserved_end), __pa_symbol(&_end))); + reserved_end = max(init_initrd(), PFN_UP(__pa_symbol(&_end))); /* * Find the highest page frame number we have available. diff --git a/arch/mips/mm/init.c b/arch/mips/mm/init.c index 3049912..4076963 100644 --- a/arch/mips/mm/init.c +++ b/arch/mips/mm/init.c @@ -460,11 +460,6 @@ void free_init_pages(char *what, unsigned long begin, unsigned long end) #ifdef CONFIG_BLK_DEV_INITRD void free_initrd_mem(unsigned long start, unsigned long end) { -#ifdef CONFIG_64BIT - /* Switch from KSEG0 to XKPHYS addresses */ - start = (unsigned long)phys_to_virt(CPHYSADDR(start)); - end = (unsigned long)phys_to_virt(CPHYSADDR(end)); -#endif free_init_pages("initrd memory", start, end); } #endif -- cgit v1.1 From acd86b8622099c3206e0a1665545ae2318089b9c Mon Sep 17 00:00:00 2001 From: Franck Bui-Huu Date: Thu, 19 Oct 2006 13:20:05 +0200 Subject: [MIPS] Make free_init_pages() arguments to be physical addresses It allows caller of this function to not care about CKSEG0/XKPHYS address mixes. It's now automatically done by free_init_pages(). We can now safely remove hack needed by 64 bit kernels with CONFIG_BUILD_ELF64=n in free_initmem(). Signed-off-by: Franck Bui-Huu Signed-off-by: Ralf Baechle --- arch/mips/mm/init.c | 33 +++++++++++++++++---------------- 1 file changed, 17 insertions(+), 16 deletions(-) (limited to 'arch/mips') diff --git a/arch/mips/mm/init.c b/arch/mips/mm/init.c index 4076963..9e29ba9 100644 --- a/arch/mips/mm/init.c +++ b/arch/mips/mm/init.c @@ -443,15 +443,18 @@ void __init mem_init(void) } #endif /* !CONFIG_NEED_MULTIPLE_NODES */ -void free_init_pages(char *what, unsigned long begin, unsigned long end) +static void free_init_pages(char *what, unsigned long begin, unsigned long end) { - unsigned long addr; + unsigned long pfn; - for (addr = begin; addr < end; addr += PAGE_SIZE) { - ClearPageReserved(virt_to_page((void *)addr)); - init_page_count(virt_to_page((void *)addr)); - memset((void *)addr, 0xcc, PAGE_SIZE); - free_page(addr); + for (pfn = PFN_UP(begin); pfn < PFN_DOWN(end); pfn++) { + struct page *page = pfn_to_page(pfn); + void *addr = phys_to_virt(PFN_PHYS(pfn)); + + ClearPageReserved(page); + init_page_count(page); + memset(addr, POISON_FREE_INITMEM, PAGE_SIZE); + __free_page(page); totalram_pages++; } printk(KERN_INFO "Freeing %s: %ldk freed\n", what, (end - begin) >> 10); @@ -460,7 +463,9 @@ void free_init_pages(char *what, unsigned long begin, unsigned long end) #ifdef CONFIG_BLK_DEV_INITRD void free_initrd_mem(unsigned long start, unsigned long end) { - free_init_pages("initrd memory", start, end); + free_init_pages("initrd memory", + virt_to_phys((void *)start), + virt_to_phys((void *)end)); } #endif @@ -468,17 +473,13 @@ extern unsigned long prom_free_prom_memory(void); void free_initmem(void) { - unsigned long start, end, freed; + unsigned long freed; freed = prom_free_prom_memory(); if (freed) printk(KERN_INFO "Freeing firmware memory: %ldk freed\n",freed); - start = (unsigned long)(&__init_begin); - end = (unsigned long)(&__init_end); -#ifdef CONFIG_64BIT - start = PAGE_OFFSET | CPHYSADDR(start); - end = PAGE_OFFSET | CPHYSADDR(end); -#endif - free_init_pages("unused kernel memory", start, end); + free_init_pages("unused kernel memory", + __pa_symbol(&__init_begin), + __pa_symbol(&__init_end)); } -- cgit v1.1 From 56ae58333031bb0564c141f955d1e42276cade55 Mon Sep 17 00:00:00 2001 From: Yoichi Yuasa Date: Sat, 14 Oct 2006 00:25:04 +0900 Subject: [MIPS] Rewrite GALILEO_INL/GALILEO_OUTL to GT_READ/GT_WRITE This patch has rewritten GALILEO_INL/GALILEO_OUTL using GT_READ/GT_WRITE. This patch tested on Cobalt Qube2. Signed-off-by: Yoichi Yuasa Signed-off-by: Ralf Baechle --- arch/mips/cobalt/irq.c | 31 ++++++++++++++----------------- arch/mips/cobalt/setup.c | 16 ++++++++-------- arch/mips/pci/fixup-cobalt.c | 11 +++++------ arch/mips/pci/ops-gt64111.c | 16 ++++++++-------- 4 files changed, 35 insertions(+), 39 deletions(-) (limited to 'arch/mips') diff --git a/arch/mips/cobalt/irq.c b/arch/mips/cobalt/irq.c index 82e569d..4c46f0e 100644 --- a/arch/mips/cobalt/irq.c +++ b/arch/mips/cobalt/irq.c @@ -45,25 +45,22 @@ static inline void galileo_irq(void) { unsigned int mask, pending, devfn; - mask = GALILEO_INL(GT_INTRMASK_OFS); - pending = GALILEO_INL(GT_INTRCAUSE_OFS) & mask; + mask = GT_READ(GT_INTRMASK_OFS); + pending = GT_READ(GT_INTRCAUSE_OFS) & mask; - if (pending & GALILEO_INTR_T0EXP) { - - GALILEO_OUTL(~GALILEO_INTR_T0EXP, GT_INTRCAUSE_OFS); + if (pending & GT_INTR_T0EXP_MSK) { + GT_WRITE(GT_INTRCAUSE_OFS, ~GT_INTR_T0EXP_MSK); do_IRQ(COBALT_GALILEO_IRQ); - - } else if (pending & GALILEO_INTR_RETRY_CTR) { - - devfn = GALILEO_INL(GT_PCI0_CFGADDR_OFS) >> 8; - GALILEO_OUTL(~GALILEO_INTR_RETRY_CTR, GT_INTRCAUSE_OFS); - printk(KERN_WARNING "Galileo: PCI retry count exceeded (%02x.%u)\n", - PCI_SLOT(devfn), PCI_FUNC(devfn)); - + } else if (pending & GT_INTR_RETRYCTR0_MSK) { + devfn = GT_READ(GT_PCI0_CFGADDR_OFS) >> 8; + GT_WRITE(GT_INTRCAUSE_OFS, ~GT_INTR_RETRYCTR0_MSK); + printk(KERN_WARNING + "Galileo: PCI retry count exceeded (%02x.%u)\n", + PCI_SLOT(devfn), PCI_FUNC(devfn)); } else { - - GALILEO_OUTL(mask & ~pending, GT_INTRMASK_OFS); - printk(KERN_WARNING "Galileo: masking unexpected interrupt %08x\n", pending); + GT_WRITE(GT_INTRMASK_OFS, mask & ~pending); + printk(KERN_WARNING + "Galileo: masking unexpected interrupt %08x\n", pending); } } @@ -104,7 +101,7 @@ void __init arch_init_irq(void) * Mask all Galileo interrupts. The Galileo * handler is set in cobalt_timer_setup() */ - GALILEO_OUTL(0, GT_INTRMASK_OFS); + GT_WRITE(GT_INTRMASK_OFS, 0); init_i8259_irqs(); /* 0 ... 15 */ mips_cpu_irq_init(COBALT_CPU_IRQ); /* 16 ... 23 */ diff --git a/arch/mips/cobalt/setup.c b/arch/mips/cobalt/setup.c index bf9dc72..e8f0f20 100644 --- a/arch/mips/cobalt/setup.c +++ b/arch/mips/cobalt/setup.c @@ -51,23 +51,23 @@ const char *get_system_type(void) void __init plat_timer_setup(struct irqaction *irq) { /* Load timer value for HZ (TCLK is 50MHz) */ - GALILEO_OUTL(50*1000*1000 / HZ, GT_TC0_OFS); + GT_WRITE(GT_TC0_OFS, 50*1000*1000 / HZ); /* Enable timer */ - GALILEO_OUTL(GALILEO_ENTC0 | GALILEO_SELTC0, GT_TC_CONTROL_OFS); + GT_WRITE(GT_TC_CONTROL_OFS, GT_TC_CONTROL_ENTC0_MSK | GT_TC_CONTROL_SELTC0_MSK); /* Register interrupt */ setup_irq(COBALT_GALILEO_IRQ, irq); /* Enable interrupt */ - GALILEO_OUTL(GALILEO_INTR_T0EXP | GALILEO_INL(GT_INTRMASK_OFS), GT_INTRMASK_OFS); + GT_WRITE(GT_INTRMASK_OFS, GT_INTR_T0EXP_MSK | GT_READ(GT_INTRMASK_OFS)); } extern struct pci_ops gt64111_pci_ops; static struct resource cobalt_mem_resource = { - .start = GT64111_MEM_BASE, - .end = GT64111_MEM_END, + .start = GT_DEF_PCI0_MEM0_BASE, + .end = GT_DEF_PCI0_MEM0_BASE + GT_DEF_PCI0_MEM0_SIZE - 1, .name = "PCI memory", .flags = IORESOURCE_MEM }; @@ -115,7 +115,7 @@ static struct pci_controller cobalt_pci_controller = { .mem_resource = &cobalt_mem_resource, .mem_offset = 0, .io_resource = &cobalt_io_resource, - .io_offset = 0 - GT64111_IO_BASE + .io_offset = 0 - GT_DEF_PCI0_IO_BASE, }; void __init plat_mem_setup(void) @@ -128,7 +128,7 @@ void __init plat_mem_setup(void) _machine_halt = cobalt_machine_halt; pm_power_off = cobalt_machine_power_off; - set_io_port_base(CKSEG1ADDR(GT64111_IO_BASE)); + set_io_port_base(CKSEG1ADDR(GT_DEF_PCI0_IO_BASE)); /* I/O port resource must include UART and LCD/buttons */ ioport_resource.end = 0x0fffffff; @@ -139,7 +139,7 @@ void __init plat_mem_setup(void) /* Read the cobalt id register out of the PCI config space */ PCI_CFG_SET(devfn, (VIA_COBALT_BRD_ID_REG & ~0x3)); - cobalt_board_id = GALILEO_INL(GT_PCI0_CFGDATA_OFS); + cobalt_board_id = GT_READ(GT_PCI0_CFGDATA_OFS); cobalt_board_id >>= ((VIA_COBALT_BRD_ID_REG & 3) * 8); cobalt_board_id = VIA_COBALT_BRD_REG_to_ID(cobalt_board_id); diff --git a/arch/mips/pci/fixup-cobalt.c b/arch/mips/pci/fixup-cobalt.c index 75a01e7..7d5f6bb 100644 --- a/arch/mips/pci/fixup-cobalt.c +++ b/arch/mips/pci/fixup-cobalt.c @@ -94,22 +94,21 @@ static void qube_raq_galileo_fixup(struct pci_dev *dev) #if 0 if (galileo_id >= 0x10) { /* New Galileo, assumes PCI stop line to VIA is connected. */ - GALILEO_OUTL(0x4020, GT_PCI0_TOR_OFS); + GT_WRITE(GT_PCI0_TOR_OFS, 0x4020); } else if (galileo_id == 0x1 || galileo_id == 0x2) #endif { signed int timeo; /* XXX WE MUST DO THIS ELSE GALILEO LOCKS UP! -DaveM */ - timeo = GALILEO_INL(GT_PCI0_TOR_OFS); + timeo = GT_READ(GT_PCI0_TOR_OFS); /* Old Galileo, assumes PCI STOP line to VIA is disconnected. */ - GALILEO_OUTL( + GT_WRITE(GT_PCI0_TOR_OFS, (0xff << 16) | /* retry count */ (0xff << 8) | /* timeout 1 */ - 0xff, /* timeout 0 */ - GT_PCI0_TOR_OFS); + 0xff); /* timeout 0 */ /* enable PCI retry exceeded interrupt */ - GALILEO_OUTL(GALILEO_INTR_RETRY_CTR | GALILEO_INL(GT_INTRMASK_OFS), GT_INTRMASK_OFS); + GT_WRITE(GT_INTRMASK_OFS, GT_INTR_RETRYCTR0_MSK | GT_READ(GT_INTRMASK_OFS)); } } diff --git a/arch/mips/pci/ops-gt64111.c b/arch/mips/pci/ops-gt64111.c index 13de459..ecd3991 100644 --- a/arch/mips/pci/ops-gt64111.c +++ b/arch/mips/pci/ops-gt64111.c @@ -38,18 +38,18 @@ static int gt64111_pci_read_config(struct pci_bus *bus, unsigned int devfn, switch (size) { case 4: PCI_CFG_SET(devfn, where); - *val = GALILEO_INL(GT_PCI0_CFGDATA_OFS); + *val = GT_READ(GT_PCI0_CFGDATA_OFS); return PCIBIOS_SUCCESSFUL; case 2: PCI_CFG_SET(devfn, (where & ~0x3)); - *val = GALILEO_INL(GT_PCI0_CFGDATA_OFS) + *val = GT_READ(GT_PCI0_CFGDATA_OFS) >> ((where & 3) * 8); return PCIBIOS_SUCCESSFUL; case 1: PCI_CFG_SET(devfn, (where & ~0x3)); - *val = GALILEO_INL(GT_PCI0_CFGDATA_OFS) + *val = GT_READ(GT_PCI0_CFGDATA_OFS) >> ((where & 3) * 8); return PCIBIOS_SUCCESSFUL; } @@ -68,25 +68,25 @@ static int gt64111_pci_write_config(struct pci_bus *bus, unsigned int devfn, switch (size) { case 4: PCI_CFG_SET(devfn, where); - GALILEO_OUTL(val, GT_PCI0_CFGDATA_OFS); + GT_WRITE(GT_PCI0_CFGDATA_OFS, val); return PCIBIOS_SUCCESSFUL; case 2: PCI_CFG_SET(devfn, (where & ~0x3)); - tmp = GALILEO_INL(GT_PCI0_CFGDATA_OFS); + tmp = GT_READ(GT_PCI0_CFGDATA_OFS); tmp &= ~(0xffff << ((where & 0x3) * 8)); tmp |= (val << ((where & 0x3) * 8)); - GALILEO_OUTL(tmp, GT_PCI0_CFGDATA_OFS); + GT_WRITE(GT_PCI0_CFGDATA_OFS, tmp); return PCIBIOS_SUCCESSFUL; case 1: PCI_CFG_SET(devfn, (where & ~0x3)); - tmp = GALILEO_INL(GT_PCI0_CFGDATA_OFS); + tmp = GT_READ(GT_PCI0_CFGDATA_OFS); tmp &= ~(0xff << ((where & 0x3) * 8)); tmp |= (val << ((where & 0x3) * 8)); - GALILEO_OUTL(tmp, GT_PCI0_CFGDATA_OFS); + GT_WRITE(GT_PCI0_CFGDATA_OFS, tmp); return PCIBIOS_SUCCESSFUL; } -- cgit v1.1 From 656be92f9ae194ed62bc81310a4589a7cd765f13 Mon Sep 17 00:00:00 2001 From: Atsushi Nemoto Date: Thu, 26 Oct 2006 00:08:31 +0900 Subject: [MIPS] Load modules to CKSEG0 if CONFIG_BUILD_ELF64=n This is a patch to load 64-bit modules to CKSEG0 so that can be compiled with -msym32 option. This makes each module ~10% smaller. * introduce MODULE_START and MODULE_END * custom module_alloc() * PGD for modules * change XTLB refill handler synthesizer * enable -msym32 for modules again (revert ca78b1a5c6a6e70e052d3ea253828e49b5d07c8a) New XTLB refill handler looks like this: 80000080 dmfc0 k0,C0_BADVADDR 80000084 bltz k0,800000e4 # goto l_module_alloc 80000088 lui k1,0x8046 # %high(pgd_current) 8000008c ld k1,24600(k1) # %low(pgd_current) 80000090 dsrl k0,k0,0x1b # l_vmalloc_done: 80000094 andi k0,k0,0x1ff8 80000098 daddu k1,k1,k0 8000009c dmfc0 k0,C0_BADVADDR 800000a0 ld k1,0(k1) 800000a4 dsrl k0,k0,0x12 800000a8 andi k0,k0,0xff8 800000ac daddu k1,k1,k0 800000b0 dmfc0 k0,C0_XCONTEXT 800000b4 ld k1,0(k1) 800000b8 andi k0,k0,0xff0 800000bc daddu k1,k1,k0 800000c0 ld k0,0(k1) 800000c4 ld k1,8(k1) 800000c8 dsrl k0,k0,0x6 800000cc mtc0 k0,C0_ENTRYLO0 800000d0 dsrl k1,k1,0x6 800000d4 mtc0 k1,C0_ENTRYL01 800000d8 nop 800000dc tlbwr 800000e0 eret 800000e4 dsll k1,k0,0x2 # l_module_alloc: 800000e8 bgez k1,80000008 # goto l_vmalloc 800000ec lui k1,0xc000 800000f0 dsubu k0,k0,k1 800000f4 lui k1,0x8046 # %high(module_pg_dir) 800000f8 beq zero,zero,80000000 800000fc nop 80000000 beq zero,zero,80000090 # goto l_vmalloc_done 80000004 daddiu k1,k1,0x4000 80000008 dsll32 k1,k1,0x0 # l_vmalloc: 8000000c dsubu k0,k0,k1 80000010 beq zero,zero,80000090 # goto l_vmalloc_done 80000014 lui k1,0x8046 # %high(swapper_pg_dir) Signed-off-by: Atsushi Nemoto Signed-off-by: Ralf Baechle --- arch/mips/Makefile | 4 +--- arch/mips/kernel/head.S | 3 +++ arch/mips/kernel/module.c | 15 +++++++++++++ arch/mips/mm/fault.c | 4 ++++ arch/mips/mm/pgtable-64.c | 3 +++ arch/mips/mm/tlbex.c | 55 +++++++++++++++++++++++++++++++++++++++++++++++ 6 files changed, 81 insertions(+), 3 deletions(-) (limited to 'arch/mips') diff --git a/arch/mips/Makefile b/arch/mips/Makefile index d580d46..641aa30 100644 --- a/arch/mips/Makefile +++ b/arch/mips/Makefile @@ -63,9 +63,7 @@ cflags-y += -mabi=64 ifdef CONFIG_BUILD_ELF64 cflags-y += $(call cc-option,-mno-explicit-relocs) else -# -msym32 can not be used for modules since they are loaded into XKSEG -CFLAGS_MODULE += $(call cc-option,-mno-explicit-relocs) -CFLAGS_KERNEL += $(call cc-option,-msym32) +cflags-y += $(call cc-option,-msym32) endif endif diff --git a/arch/mips/kernel/head.S b/arch/mips/kernel/head.S index ddc1b71..a2e095a 100644 --- a/arch/mips/kernel/head.S +++ b/arch/mips/kernel/head.S @@ -250,6 +250,9 @@ NESTED(smp_bootstrap, 16, sp) */ page swapper_pg_dir, _PGD_ORDER #ifdef CONFIG_64BIT +#if defined(CONFIG_MODULES) && !defined(CONFIG_BUILD_ELF64) + page module_pg_dir, _PGD_ORDER +#endif page invalid_pmd_table, _PMD_ORDER #endif page invalid_pte_table, _PTE_ORDER diff --git a/arch/mips/kernel/module.c b/arch/mips/kernel/module.c index d7bf021..cb08014 100644 --- a/arch/mips/kernel/module.c +++ b/arch/mips/kernel/module.c @@ -29,6 +29,7 @@ #include #include #include +#include /* MODULE_START */ struct mips_hi16 { struct mips_hi16 *next; @@ -43,9 +44,23 @@ static DEFINE_SPINLOCK(dbe_lock); void *module_alloc(unsigned long size) { +#ifdef MODULE_START + struct vm_struct *area; + + size = PAGE_ALIGN(size); + if (!size) + return NULL; + + area = __get_vm_area(size, VM_ALLOC, MODULE_START, MODULE_END); + if (!area) + return NULL; + + return __vmalloc_area(area, GFP_KERNEL, PAGE_KERNEL); +#else if (size == 0) return NULL; return vmalloc(size); +#endif } /* Free memory returned from module_alloc */ diff --git a/arch/mips/mm/fault.c b/arch/mips/mm/fault.c index 8423d85..6f90e7e 100644 --- a/arch/mips/mm/fault.c +++ b/arch/mips/mm/fault.c @@ -60,6 +60,10 @@ asmlinkage void do_page_fault(struct pt_regs *regs, unsigned long write, */ if (unlikely(address >= VMALLOC_START && address <= VMALLOC_END)) goto vmalloc_fault; +#ifdef MODULE_START + if (unlikely(address >= MODULE_START && address < MODULE_END)) + goto vmalloc_fault; +#endif /* * If we're in an interrupt or have no user diff --git a/arch/mips/mm/pgtable-64.c b/arch/mips/mm/pgtable-64.c index 8d600d3..c46eb65 100644 --- a/arch/mips/mm/pgtable-64.c +++ b/arch/mips/mm/pgtable-64.c @@ -58,6 +58,9 @@ void __init pagetable_init(void) /* Initialize the entire pgd. */ pgd_init((unsigned long)swapper_pg_dir); +#ifdef MODULE_START + pgd_init((unsigned long)module_pg_dir); +#endif pmd_init((unsigned long)invalid_pmd_table, (unsigned long)invalid_pte_table); pgd_base = swapper_pg_dir; diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c index fec318a..492c518 100644 --- a/arch/mips/mm/tlbex.c +++ b/arch/mips/mm/tlbex.c @@ -423,6 +423,9 @@ enum label_id { label_invalid, label_second_part, label_leave, +#ifdef MODULE_START + label_module_alloc, +#endif label_vmalloc, label_vmalloc_done, label_tlbw_hazard, @@ -455,6 +458,9 @@ static __init void build_label(struct label **lab, u32 *addr, L_LA(_second_part) L_LA(_leave) +#ifdef MODULE_START +L_LA(_module_alloc) +#endif L_LA(_vmalloc) L_LA(_vmalloc_done) L_LA(_tlbw_hazard) @@ -686,6 +692,13 @@ static void __init il_bgezl(u32 **p, struct reloc **r, unsigned int reg, i_bgezl(p, reg, 0); } +static void __init __attribute__((unused)) +il_bgez(u32 **p, struct reloc **r, unsigned int reg, enum label_id l) +{ + r_mips_pc16(r, *p, l); + i_bgez(p, reg, 0); +} + /* The only general purpose registers allowed in TLB handlers. */ #define K0 26 #define K1 27 @@ -970,7 +983,11 @@ build_get_pmde64(u32 **p, struct label **l, struct reloc **r, * The vmalloc handling is not in the hotpath. */ i_dmfc0(p, tmp, C0_BADVADDR); +#ifdef MODULE_START + il_bltz(p, r, tmp, label_module_alloc); +#else il_bltz(p, r, tmp, label_vmalloc); +#endif /* No i_nop needed here, since the next insn doesn't touch TMP. */ #ifdef CONFIG_SMP @@ -1023,8 +1040,46 @@ build_get_pgd_vmalloc64(u32 **p, struct label **l, struct reloc **r, { long swpd = (long)swapper_pg_dir; +#ifdef MODULE_START + long modd = (long)module_pg_dir; + + l_module_alloc(l, *p); + /* + * Assumption: + * VMALLOC_START >= 0xc000000000000000UL + * MODULE_START >= 0xe000000000000000UL + */ + i_SLL(p, ptr, bvaddr, 2); + il_bgez(p, r, ptr, label_vmalloc); + + if (in_compat_space_p(MODULE_START) && !rel_lo(MODULE_START)) { + i_lui(p, ptr, rel_hi(MODULE_START)); /* delay slot */ + } else { + /* unlikely configuration */ + i_nop(p); /* delay slot */ + i_LA(p, ptr, MODULE_START); + } + i_dsubu(p, bvaddr, bvaddr, ptr); + + if (in_compat_space_p(modd) && !rel_lo(modd)) { + il_b(p, r, label_vmalloc_done); + i_lui(p, ptr, rel_hi(modd)); + } else { + i_LA_mostly(p, ptr, modd); + il_b(p, r, label_vmalloc_done); + i_daddiu(p, ptr, ptr, rel_lo(modd)); + } + + l_vmalloc(l, *p); + if (in_compat_space_p(MODULE_START) && !rel_lo(MODULE_START) && + MODULE_START << 32 == VMALLOC_START) + i_dsll32(p, ptr, ptr, 0); /* typical case */ + else + i_LA(p, ptr, VMALLOC_START); +#else l_vmalloc(l, *p); i_LA(p, ptr, VMALLOC_START); +#endif i_dsubu(p, bvaddr, bvaddr, ptr); if (in_compat_space_p(swpd) && !rel_lo(swpd)) { -- cgit v1.1 From 5b10496b6e6577f65b032a5c4c97d0d3a841273c Mon Sep 17 00:00:00 2001 From: Atsushi Nemoto Date: Mon, 11 Sep 2006 17:50:29 +0900 Subject: [MIPS] Fast path for rdhwr emulation for TLS Add special short path for emulationg RDHWR which is used to support TLS. Add an extra prologue for cpu_has_vtag_icache case. Signed-off-by: Atsushi Nemoto Signed-off-by: Ralf Baechle --- arch/mips/kernel/genex.S | 63 ++++++++++++++++++++++++++++++++++++++++++++++++ arch/mips/kernel/traps.c | 15 +++++++++++- 2 files changed, 77 insertions(+), 1 deletion(-) (limited to 'arch/mips') diff --git a/arch/mips/kernel/genex.S b/arch/mips/kernel/genex.S index 5baca16..aacd4a0 100644 --- a/arch/mips/kernel/genex.S +++ b/arch/mips/kernel/genex.S @@ -19,6 +19,7 @@ #include #include #include +#include #define PANIC_PIC(msg) \ .set push; \ @@ -378,6 +379,68 @@ NESTED(nmi_handler, PT_SIZE, sp) BUILD_HANDLER dsp dsp sti silent /* #26 */ BUILD_HANDLER reserved reserved sti verbose /* others */ + .align 5 + LEAF(handle_ri_rdhwr_vivt) +#ifdef CONFIG_MIPS_MT_SMTC + PANIC_PIC("handle_ri_rdhwr_vivt called") +#else + .set push + .set noat + .set noreorder + /* check if TLB contains a entry for EPC */ + MFC0 k1, CP0_ENTRYHI + andi k1, 0xff /* ASID_MASK */ + MFC0 k0, CP0_EPC + PTR_SRL k0, PAGE_SHIFT + 1 + PTR_SLL k0, PAGE_SHIFT + 1 + or k1, k0 + MTC0 k1, CP0_ENTRYHI + mtc0_tlbw_hazard + tlbp + tlb_probe_hazard + mfc0 k1, CP0_INDEX + .set pop + bltz k1, handle_ri /* slow path */ + /* fall thru */ +#endif + END(handle_ri_rdhwr_vivt) + + LEAF(handle_ri_rdhwr) + .set push + .set noat + .set noreorder + /* 0x7c03e83b: rdhwr v1,$29 */ + MFC0 k1, CP0_EPC + lui k0, 0x7c03 + lw k1, (k1) + ori k0, 0xe83b + .set reorder + bne k0, k1, handle_ri /* if not ours */ + /* The insn is rdhwr. No need to check CAUSE.BD here. */ + get_saved_sp /* k1 := current_thread_info */ + .set noreorder + MFC0 k0, CP0_EPC +#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX) + ori k1, _THREAD_MASK + xori k1, _THREAD_MASK + LONG_L v1, TI_TP_VALUE(k1) + LONG_ADDIU k0, 4 + jr k0 + rfe +#else + LONG_ADDIU k0, 4 /* stall on $k0 */ + MTC0 k0, CP0_EPC + /* I hope three instructions between MTC0 and ERET are enough... */ + ori k1, _THREAD_MASK + xori k1, _THREAD_MASK + LONG_L v1, TI_TP_VALUE(k1) + .set mips3 + eret + .set mips0 +#endif + .set pop + END(handle_ri_rdhwr) + #ifdef CONFIG_64BIT /* A temporary overflow handler used by check_daddi(). */ diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c index 9fda1b8..6eccfb4 100644 --- a/arch/mips/kernel/traps.c +++ b/arch/mips/kernel/traps.c @@ -54,6 +54,8 @@ extern asmlinkage void handle_dbe(void); extern asmlinkage void handle_sys(void); extern asmlinkage void handle_bp(void); extern asmlinkage void handle_ri(void); +extern asmlinkage void handle_ri_rdhwr_vivt(void); +extern asmlinkage void handle_ri_rdhwr(void); extern asmlinkage void handle_cpu(void); extern asmlinkage void handle_ov(void); extern asmlinkage void handle_tr(void); @@ -1423,6 +1425,15 @@ void __init set_uncached_handler (unsigned long offset, void *addr, unsigned lon memcpy((void *)(uncached_ebase + offset), addr, size); } +static int __initdata rdhwr_noopt; +static int __init set_rdhwr_noopt(char *str) +{ + rdhwr_noopt = 1; + return 1; +} + +__setup("rdhwr_noopt", set_rdhwr_noopt); + void __init trap_init(void) { extern char except_vec3_generic, except_vec3_r4000; @@ -1502,7 +1513,9 @@ void __init trap_init(void) set_except_vector(8, handle_sys); set_except_vector(9, handle_bp); - set_except_vector(10, handle_ri); + set_except_vector(10, rdhwr_noopt ? handle_ri : + (cpu_has_vtag_icache ? + handle_ri_rdhwr_vivt : handle_ri_rdhwr)); set_except_vector(11, handle_cpu); set_except_vector(12, handle_ov); set_except_vector(13, handle_tr); -- cgit v1.1 From c237923009da464881d89f4bc27c3b5b1a93d61b Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Thu, 30 Nov 2006 01:14:44 +0000 Subject: [MIPS] Don't print presence of WAIT instruction on bootup. Not useful and quite a big of noise on bootup of large systems. Signed-off-by: Ralf Baechle --- arch/mips/kernel/cpu-probe.c | 19 +++---------------- 1 file changed, 3 insertions(+), 16 deletions(-) (limited to 'arch/mips') diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index 8485af3..442839e 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c @@ -110,9 +110,8 @@ static inline void check_wait(void) { struct cpuinfo_mips *c = ¤t_cpu_data; - printk("Checking for 'wait' instruction... "); if (nowait) { - printk (" disabled.\n"); + printk("Wait instruction disabled.\n"); return; } @@ -120,11 +119,9 @@ static inline void check_wait(void) case CPU_R3081: case CPU_R3081E: cpu_wait = r3081_wait; - printk(" available.\n"); break; case CPU_TX3927: cpu_wait = r39xx_wait; - printk(" available.\n"); break; case CPU_R4200: /* case CPU_R4300: */ @@ -146,33 +143,23 @@ static inline void check_wait(void) case CPU_74K: case CPU_PR4450: cpu_wait = r4k_wait; - printk(" available.\n"); break; case CPU_TX49XX: cpu_wait = r4k_wait_irqoff; - printk(" available.\n"); break; case CPU_AU1000: case CPU_AU1100: case CPU_AU1500: case CPU_AU1550: case CPU_AU1200: - if (allow_au1k_wait) { + if (allow_au1k_wait) cpu_wait = au1k_wait; - printk(" available.\n"); - } else - printk(" unavailable.\n"); break; case CPU_RM9000: - if ((c->processor_id & 0x00ff) >= 0x40) { + if ((c->processor_id & 0x00ff) >= 0x40) cpu_wait = r4k_wait; - printk(" available.\n"); - } else { - printk(" unavailable.\n"); - } break; default: - printk(" unavailable.\n"); break; } } -- cgit v1.1 From 583bb86fbb9e85287f020fe4eb5352a0ec3c66a3 Mon Sep 17 00:00:00 2001 From: Nicolas Schichan Date: Wed, 18 Oct 2006 15:14:55 +0200 Subject: [MIPS] Add support for kexec A tiny userland application loading the kernel and invoking kexec_load for mips is available here: http://chac.le-poulpe.net/~nico/kexec/kexec-2006-10-18.tar.gz Signed-off-by: Ralf Baechle --- arch/mips/Kconfig | 17 ++++++++ arch/mips/kernel/Makefile | 2 + arch/mips/kernel/machine_kexec.c | 85 ++++++++++++++++++++++++++++++++++++++ arch/mips/kernel/relocate_kernel.S | 80 +++++++++++++++++++++++++++++++++++ arch/mips/kernel/scall32-o32.S | 2 +- arch/mips/kernel/scall64-64.S | 2 +- arch/mips/kernel/scall64-n32.S | 2 +- arch/mips/kernel/scall64-o32.S | 2 +- 8 files changed, 188 insertions(+), 4 deletions(-) create mode 100644 arch/mips/kernel/machine_kexec.c create mode 100644 arch/mips/kernel/relocate_kernel.S (limited to 'arch/mips') diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 1443024..c0da0ff 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -766,6 +766,23 @@ config TOSHIBA_RBTX4938 endchoice +config KEXEC + bool "Kexec system call (EXPERIMENTAL)" + depends on EXPERIMENTAL + help + kexec is a system call that implements the ability to shutdown your + current kernel, and to start another kernel. It is like a reboot + but it is indepedent of the system firmware. And like a reboot + you can start any kernel with it, not just Linux. + + The name comes from the similiarity to the exec system call. + + It is an ongoing process to be certain the hardware in a machine + is properly shutdown, so do not be surprised if this code does not + initially work for you. It may help to enable device hotplugging + support. As of this writing the exact hardware interface is + strongly in flux, so no good recommendation can be made. + source "arch/mips/ddb5xxx/Kconfig" source "arch/mips/gt64120/ev64120/Kconfig" source "arch/mips/jazz/Kconfig" diff --git a/arch/mips/kernel/Makefile b/arch/mips/kernel/Makefile index 6bfbbed..f35b739 100644 --- a/arch/mips/kernel/Makefile +++ b/arch/mips/kernel/Makefile @@ -67,6 +67,8 @@ obj-$(CONFIG_64BIT) += cpu-bugs64.o obj-$(CONFIG_I8253) += i8253.o +obj-$(CONFIG_KEXEC) += machine_kexec.o relocate_kernel.o + CFLAGS_cpu-bugs64.o = $(shell if $(CC) $(CFLAGS) -Wa,-mdaddi -c -o /dev/null -xc /dev/null >/dev/null 2>&1; then echo "-DHAVE_AS_SET_DADDI"; fi) EXTRA_AFLAGS := $(CFLAGS) diff --git a/arch/mips/kernel/machine_kexec.c b/arch/mips/kernel/machine_kexec.c new file mode 100644 index 0000000..e0ad754 --- /dev/null +++ b/arch/mips/kernel/machine_kexec.c @@ -0,0 +1,85 @@ +/* + * machine_kexec.c for kexec + * Created by on Thu Oct 12 15:15:06 2006 + * + * This source code is licensed under the GNU General Public License, + * Version 2. See the file COPYING for more details. + */ + +#include +#include +#include + +#include +#include + +const extern unsigned char relocate_new_kernel[]; +const extern unsigned int relocate_new_kernel_size; + +extern unsigned long kexec_start_address; +extern unsigned long kexec_indirection_page; + +int +machine_kexec_prepare(struct kimage *kimage) +{ + return 0; +} + +void +machine_kexec_cleanup(struct kimage *kimage) +{ +} + +void +machine_shutdown(void) +{ +} + +void +machine_crash_shutdown(struct pt_regs *regs) +{ +} + +void +machine_kexec(struct kimage *image) +{ + unsigned long reboot_code_buffer; + unsigned long entry; + unsigned long *ptr; + + reboot_code_buffer = + (unsigned long)page_address(image->control_code_page); + + kexec_start_address = image->start; + kexec_indirection_page = phys_to_virt(image->head & PAGE_MASK); + + memcpy((void*)reboot_code_buffer, relocate_new_kernel, + relocate_new_kernel_size); + + /* + * The generic kexec code builds a page list with physical + * addresses. they are directly accessible through KSEG0 (or + * CKSEG0 or XPHYS if on 64bit system), hence the + * pys_to_virt() call. + */ + for (ptr = &image->head; (entry = *ptr) && !(entry &IND_DONE); + ptr = (entry & IND_INDIRECTION) ? + phys_to_virt(entry & PAGE_MASK) : ptr + 1) { + if (*ptr & IND_SOURCE || *ptr & IND_INDIRECTION || + *ptr & IND_DESTINATION) + *ptr = phys_to_virt(*ptr); + } + + /* + * we do not want to be bothered. + */ + local_irq_disable(); + + flush_icache_range(reboot_code_buffer, + reboot_code_buffer + KEXEC_CONTROL_CODE_SIZE); + + printk("Will call new kernel at %08x\n", image->start); + printk("Bye ...\n"); + flush_cache_all(); + ((void (*)(void))reboot_code_buffer)(); +} diff --git a/arch/mips/kernel/relocate_kernel.S b/arch/mips/kernel/relocate_kernel.S new file mode 100644 index 0000000..a3f0d00c --- /dev/null +++ b/arch/mips/kernel/relocate_kernel.S @@ -0,0 +1,80 @@ +/* + * relocate_kernel.S for kexec + * Created by on Thu Oct 12 17:49:57 2006 + * + * This source code is licensed under the GNU General Public License, + * Version 2. See the file COPYING for more details. + */ + +#include +#include +#include +#include +#include +#include +#include + + .globl relocate_new_kernel +relocate_new_kernel: + + PTR_L s0, kexec_indirection_page + PTR_L s1, kexec_start_address + +process_entry: + PTR_L s2, (s0) + PTR_ADD s0, s0, SZREG + + /* destination page */ + and s3, s2, 0x1 + beq s3, zero, 1f + and s4, s2, ~0x1 /* store destination addr in s4 */ + move a0, s4 + b process_entry + +1: + /* indirection page, update s0 */ + and s3, s2, 0x2 + beq s3, zero, 1f + and s0, s2, ~0x2 + b process_entry + +1: + /* done page */ + and s3, s2, 0x4 + beq s3, zero, 1f + b done +1: + /* source page */ + and s3, s2, 0x8 + beq s3, zero, process_entry + and s2, s2, ~0x8 + li s6, (1 << PAGE_SHIFT) / SZREG + +copy_word: + /* copy page word by word */ + REG_L s5, (s2) + REG_S s5, (s4) + INT_ADD s4, s4, SZREG + INT_ADD s2, s2, SZREG + INT_SUB s6, s6, 1 + beq s6, zero, process_entry + b copy_word + b process_entry + +done: + /* jump to kexec_start_address */ + j s1 + + .globl kexec_start_address +kexec_start_address: + .long 0x0 + + .globl kexec_indirection_page +kexec_indirection_page: + .long 0x0 + +relocate_new_kernel_end: + + .globl relocate_new_kernel_size +relocate_new_kernel_size: + .long relocate_new_kernel_end - relocate_new_kernel diff --git a/arch/mips/kernel/scall32-o32.S b/arch/mips/kernel/scall32-o32.S index a95f37d..7c0b393 100644 --- a/arch/mips/kernel/scall32-o32.S +++ b/arch/mips/kernel/scall32-o32.S @@ -653,7 +653,7 @@ einval: li v0, -EINVAL sys sys_move_pages 6 sys sys_set_robust_list 2 sys sys_get_robust_list 3 /* 4310 */ - sys sys_ni_syscall 0 + sys sys_kexec_load 4 sys sys_getcpu 3 sys sys_epoll_pwait 6 .endm diff --git a/arch/mips/kernel/scall64-64.S b/arch/mips/kernel/scall64-64.S index 8fb0f60..e569b84 100644 --- a/arch/mips/kernel/scall64-64.S +++ b/arch/mips/kernel/scall64-64.S @@ -468,6 +468,6 @@ sys_call_table: PTR sys_move_pages PTR sys_set_robust_list PTR sys_get_robust_list - PTR sys_ni_syscall /* 5270 */ + PTR sys_kexec_load /* 5270 */ PTR sys_getcpu PTR sys_epoll_pwait diff --git a/arch/mips/kernel/scall64-n32.S b/arch/mips/kernel/scall64-n32.S index 0da5ca2..5b18f26 100644 --- a/arch/mips/kernel/scall64-n32.S +++ b/arch/mips/kernel/scall64-n32.S @@ -394,6 +394,6 @@ EXPORT(sysn32_call_table) PTR sys_move_pages PTR compat_sys_set_robust_list PTR compat_sys_get_robust_list - PTR sys_ni_syscall + PTR compat_sys_kexec_load PTR sys_getcpu PTR sys_epoll_pwait diff --git a/arch/mips/kernel/scall64-o32.S b/arch/mips/kernel/scall64-o32.S index b9d00ca..e91379c 100644 --- a/arch/mips/kernel/scall64-o32.S +++ b/arch/mips/kernel/scall64-o32.S @@ -516,7 +516,7 @@ sys_call_table: PTR compat_sys_move_pages PTR compat_sys_set_robust_list PTR compat_sys_get_robust_list /* 4310 */ - PTR sys_ni_syscall + PTR compat_sys_kexec_load PTR sys_getcpu PTR sys_epoll_pwait .size sys_call_table,.-sys_call_table -- cgit v1.1 From 714cfe7865e5182a3b25be6a95c0b17aa8e64aa9 Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Mon, 23 Oct 2006 00:44:02 +0100 Subject: [MIPS] Oprofile: kernel support for the R10000. Signed-off-by: Ralf Baechle --- arch/mips/oprofile/Makefile | 1 + arch/mips/oprofile/common.c | 3 +++ arch/mips/oprofile/op_model_mipsxx.c | 32 +++++++++++++++++++++++++++----- 3 files changed, 31 insertions(+), 5 deletions(-) (limited to 'arch/mips') diff --git a/arch/mips/oprofile/Makefile b/arch/mips/oprofile/Makefile index 0a50aad..bf3be6f 100644 --- a/arch/mips/oprofile/Makefile +++ b/arch/mips/oprofile/Makefile @@ -12,5 +12,6 @@ oprofile-y := $(DRIVER_OBJS) common.o oprofile-$(CONFIG_CPU_MIPS32) += op_model_mipsxx.o oprofile-$(CONFIG_CPU_MIPS64) += op_model_mipsxx.o +oprofile-$(CONFIG_CPU_R10000) += op_model_mipsxx.o oprofile-$(CONFIG_CPU_SB1) += op_model_mipsxx.o oprofile-$(CONFIG_CPU_RM9000) += op_model_rm9000.o diff --git a/arch/mips/oprofile/common.c b/arch/mips/oprofile/common.c index 65eb554..4e0a90b39 100644 --- a/arch/mips/oprofile/common.c +++ b/arch/mips/oprofile/common.c @@ -83,6 +83,9 @@ int __init oprofile_arch_init(struct oprofile_operations *ops) case CPU_74K: case CPU_SB1: case CPU_SB1A: + case CPU_R10000: + case CPU_R12000: + case CPU_R14000: lmodel = &op_model_mipsxx_ops; break; diff --git a/arch/mips/oprofile/op_model_mipsxx.c b/arch/mips/oprofile/op_model_mipsxx.c index 1fb240c..455d76a 100644 --- a/arch/mips/oprofile/op_model_mipsxx.c +++ b/arch/mips/oprofile/op_model_mipsxx.c @@ -18,7 +18,7 @@ #define M_PERFCTL_SUPERVISOR (1UL << 2) #define M_PERFCTL_USER (1UL << 3) #define M_PERFCTL_INTERRUPT_ENABLE (1UL << 4) -#define M_PERFCTL_EVENT(event) ((event) << 5) +#define M_PERFCTL_EVENT(event) (((event) & 0x3f) << 5) #define M_PERFCTL_VPEID(vpe) ((vpe) << 16) #define M_PERFCTL_MT_EN(filter) ((filter) << 20) #define M_TC_EN_ALL M_PERFCTL_MT_EN(0) @@ -218,13 +218,23 @@ static inline int __n_counters(void) static inline int n_counters(void) { - int counters = __n_counters(); + int counters; + + switch (current_cpu_data.cputype) { + case CPU_R10000: + counters = 2; + + case CPU_R12000: + case CPU_R14000: + counters = 4; + + default: + counters = __n_counters(); + } #ifdef CONFIG_MIPS_MT_SMP - if (current_cpu_data.cputype == CPU_34K) - return counters >> 1; + counters >> 1; #endif - return counters; } @@ -284,6 +294,18 @@ static int __init mipsxx_init(void) op_model_mipsxx_ops.cpu_type = "mips/5K"; break; + case CPU_R10000: + if ((current_cpu_data.processor_id & 0xff) == 0x20) + op_model_mipsxx_ops.cpu_type = "mips/r10000-v2.x"; + else + op_model_mipsxx_ops.cpu_type = "mips/r10000"; + break; + + case CPU_R12000: + case CPU_R14000: + op_model_mipsxx_ops.cpu_type = "mips/r12000"; + break; + case CPU_SB1: case CPU_SB1A: op_model_mipsxx_ops.cpu_type = "mips/sb1"; -- cgit v1.1 From 0d02f0734f8d2310497fae4f960c978f679f66d9 Mon Sep 17 00:00:00 2001 From: Yoichi Yuasa Date: Wed, 1 Nov 2006 18:40:15 +0900 Subject: [MIPS] PB1200: Remove duplicate definitions Signed-off-by: Yoichi Yuasa Signed-off-by: Ralf Baechle --- arch/mips/au1000/pb1200/board_setup.c | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) (limited to 'arch/mips') diff --git a/arch/mips/au1000/pb1200/board_setup.c b/arch/mips/au1000/pb1200/board_setup.c index 8b953b9..043302b 100644 --- a/arch/mips/au1000/pb1200/board_setup.c +++ b/arch/mips/au1000/pb1200/board_setup.c @@ -55,7 +55,7 @@ #endif extern void _board_init_irq(void); -extern void (*board_init_irq)(void); +extern void (*board_init_irq)(void); void board_reset (void) { @@ -151,11 +151,7 @@ void __init board_setup(void) #endif /* Setup Pb1200 External Interrupt Controller */ - { - extern void (*board_init_irq)(void); - extern void _board_init_irq(void); - board_init_irq = _board_init_irq; - } + board_init_irq = _board_init_irq; } int -- cgit v1.1 From c87b6ebaea034c0e0ce86127870cf1511a307b64 Mon Sep 17 00:00:00 2001 From: Atsushi Nemoto Date: Sat, 28 Oct 2006 01:14:37 +0900 Subject: [MIPS] mips hpt cleanup: get rid of mips_hpt_init Currently nobody outside time.c require mips_hpt_init(). Remove it and call c0_hpt_timer_init() directly if R4k counter was used for timer interrupt. Signed-off-by: Atsushi Nemoto Signed-off-by: Ralf Baechle --- arch/mips/kernel/time.c | 22 ++++++++-------------- arch/mips/pmc-sierra/yosemite/smp.c | 2 -- 2 files changed, 8 insertions(+), 16 deletions(-) (limited to 'arch/mips') diff --git a/arch/mips/kernel/time.c b/arch/mips/kernel/time.c index e535f86..111d1ba 100644 --- a/arch/mips/kernel/time.c +++ b/arch/mips/kernel/time.c @@ -88,12 +88,6 @@ static unsigned int null_hpt_read(void) return 0; } -static void __init null_hpt_init(void) -{ - /* nothing */ -} - - /* * Timer ack for an R4k-compatible timer of a known frequency. */ @@ -133,7 +127,6 @@ static void __init c0_hpt_timer_init(void) int (*mips_timer_state)(void); void (*mips_timer_ack)(void); unsigned int (*mips_hpt_read)(void); -void (*mips_hpt_init)(void) __initdata = null_hpt_init; unsigned int mips_hpt_mask = 0xffffffff; /* last time when xtime and rtc are sync'ed up */ @@ -383,16 +376,20 @@ void __init time_init(void) if (!mips_timer_state) { /* No external timer interrupt -- use R4k. */ - mips_hpt_init = c0_hpt_timer_init; mips_timer_ack = c0_timer_ack; + /* Calculate cache parameters. */ + cycles_per_jiffy = + (mips_hpt_frequency + HZ / 2) / HZ; + /* + * This sets up the high precision + * timer for the first interrupt. + */ + c0_hpt_timer_init(); } } if (!mips_hpt_frequency) mips_hpt_frequency = calibrate_hpt(); - /* Calculate cache parameters. */ - cycles_per_jiffy = (mips_hpt_frequency + HZ / 2) / HZ; - /* Report the high precision timer rate for a reference. */ printk("Using %u.%03u MHz high precision timer.\n", ((mips_hpt_frequency + 500) / 1000) / 1000, @@ -403,9 +400,6 @@ void __init time_init(void) /* No timer interrupt ack (e.g. i8254). */ mips_timer_ack = null_timer_ack; - /* This sets up the high precision timer for the first interrupt. */ - mips_hpt_init(); - /* * Call board specific timer interrupt setup. * diff --git a/arch/mips/pmc-sierra/yosemite/smp.c b/arch/mips/pmc-sierra/yosemite/smp.c index 3cc0436..305491e 100644 --- a/arch/mips/pmc-sierra/yosemite/smp.c +++ b/arch/mips/pmc-sierra/yosemite/smp.c @@ -99,8 +99,6 @@ void prom_cpus_done(void) */ void prom_init_secondary(void) { - mips_hpt_init(); - set_c0_status(ST0_CO | ST0_IE | ST0_IM); } -- cgit v1.1 From 1603b5aca4f15b34848fb5594d0c7b6333b99144 Mon Sep 17 00:00:00 2001 From: Atsushi Nemoto Date: Thu, 2 Nov 2006 02:08:36 +0900 Subject: [MIPS] IRQ cleanups This is a big irq cleanup patch. * Use set_irq_chip() to register irq_chip. * Initialize .mask, .unmask, .mask_ack field. Functions for these method are already exist in most case. * Do not initialize .startup, .shutdown, .enable, .disable fields if default routines provided by irq_chip_set_defaults() were suitable. * Remove redundant irq_desc initializations. * Remove unnecessary local_irq_save/local_irq_restore, spin_lock. With this cleanup, it would be easy to switch to slightly lightwait irq flow handlers (handle_level_irq(), etc.) instead of __do_IRQ(). Though whole this patch is quite large, changes in each irq_chip are not quite simple. Please review and test on your platform. Thanks. Signed-off-by: Atsushi Nemoto Signed-off-by: Ralf Baechle --- arch/mips/au1000/common/irq.c | 63 +++---- arch/mips/ddb5xxx/ddb5477/irq_5477.c | 23 +-- arch/mips/dec/ecc-berr.c | 6 - arch/mips/dec/ioasic-irq.c | 72 ++------ arch/mips/dec/kn02-irq.c | 53 +----- arch/mips/emma2rh/common/irq_emma2rh.c | 34 +--- arch/mips/emma2rh/markeins/irq_markeins.c | 55 ++----- arch/mips/gt64120/ev64120/irq.c | 40 +---- arch/mips/jazz/irq.c | 27 +-- arch/mips/jmr3927/rbhma3100/irq.c | 32 +--- arch/mips/kernel/i8259.c | 21 +-- arch/mips/kernel/irq-msc01.c | 45 +---- arch/mips/kernel/irq-mv6434x.c | 53 +----- arch/mips/kernel/irq-rm7000.c | 53 +----- arch/mips/kernel/irq-rm9000.c | 45 ++--- arch/mips/kernel/irq.c | 13 -- arch/mips/kernel/irq_cpu.c | 77 ++------- arch/mips/lasat/interrupt.c | 36 +--- arch/mips/mips-boards/atlas/atlas_int.c | 28 +--- arch/mips/momentum/ocelot_c/cpci-irq.c | 53 +----- arch/mips/momentum/ocelot_c/uart-irq.c | 56 +------ arch/mips/philips/pnx8550/common/int.c | 66 ++------ arch/mips/sgi-ip22/ip22-eisa.c | 33 +--- arch/mips/sgi-ip22/ip22-int.c | 109 ++---------- arch/mips/sgi-ip27/ip27-irq.c | 17 +- arch/mips/sgi-ip27/ip27-timer.c | 27 +-- arch/mips/sgi-ip32/ip32-irq.c | 133 +++------------ arch/mips/sibyte/bcm1480/irq.c | 30 +--- arch/mips/sibyte/sb1250/irq.c | 30 +--- arch/mips/sni/irq.c | 40 +---- arch/mips/tx4927/common/tx4927_irq.c | 162 ++---------------- .../tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c | 183 ++------------------- arch/mips/tx4938/common/irq.c | 113 ++----------- arch/mips/tx4938/toshiba_rbtx4938/irq.c | 53 +----- arch/mips/vr41xx/common/icu.c | 46 ++---- arch/mips/vr41xx/nec-cmbvr4133/irq.c | 20 +-- 36 files changed, 292 insertions(+), 1655 deletions(-) (limited to 'arch/mips') diff --git a/arch/mips/au1000/common/irq.c b/arch/mips/au1000/common/irq.c index 2abe132..9cf7b671 100644 --- a/arch/mips/au1000/common/irq.c +++ b/arch/mips/au1000/common/irq.c @@ -70,7 +70,6 @@ extern irq_cpustat_t irq_stat [NR_CPUS]; extern void mips_timer_interrupt(void); static void setup_local_irq(unsigned int irq, int type, int int_req); -static unsigned int startup_irq(unsigned int irq); static void end_irq(unsigned int irq_nr); static inline void mask_and_ack_level_irq(unsigned int irq_nr); static inline void mask_and_ack_rise_edge_irq(unsigned int irq_nr); @@ -84,20 +83,6 @@ void (*board_init_irq)(void); static DEFINE_SPINLOCK(irq_lock); -static unsigned int startup_irq(unsigned int irq_nr) -{ - local_enable_irq(irq_nr); - return 0; -} - - -static void shutdown_irq(unsigned int irq_nr) -{ - local_disable_irq(irq_nr); - return; -} - - inline void local_enable_irq(unsigned int irq_nr) { if (irq_nr > AU1000_LAST_INTC0_INT) { @@ -249,41 +234,37 @@ void restore_local_and_enable(int controller, unsigned long mask) static struct irq_chip rise_edge_irq_type = { .typename = "Au1000 Rise Edge", - .startup = startup_irq, - .shutdown = shutdown_irq, - .enable = local_enable_irq, - .disable = local_disable_irq, .ack = mask_and_ack_rise_edge_irq, + .mask = local_disable_irq, + .mask_ack = mask_and_ack_rise_edge_irq, + .unmask = local_enable_irq, .end = end_irq, }; static struct irq_chip fall_edge_irq_type = { .typename = "Au1000 Fall Edge", - .startup = startup_irq, - .shutdown = shutdown_irq, - .enable = local_enable_irq, - .disable = local_disable_irq, .ack = mask_and_ack_fall_edge_irq, + .mask = local_disable_irq, + .mask_ack = mask_and_ack_fall_edge_irq, + .unmask = local_enable_irq, .end = end_irq, }; static struct irq_chip either_edge_irq_type = { .typename = "Au1000 Rise or Fall Edge", - .startup = startup_irq, - .shutdown = shutdown_irq, - .enable = local_enable_irq, - .disable = local_disable_irq, .ack = mask_and_ack_either_edge_irq, + .mask = local_disable_irq, + .mask_ack = mask_and_ack_either_edge_irq, + .unmask = local_enable_irq, .end = end_irq, }; static struct irq_chip level_irq_type = { .typename = "Au1000 Level", - .startup = startup_irq, - .shutdown = shutdown_irq, - .enable = local_enable_irq, - .disable = local_disable_irq, .ack = mask_and_ack_level_irq, + .mask = local_disable_irq, + .mask_ack = mask_and_ack_level_irq, + .unmask = local_enable_irq, .end = end_irq, }; @@ -328,31 +309,31 @@ static void setup_local_irq(unsigned int irq_nr, int type, int int_req) au_writel(1<<(irq_nr-32), IC1_CFG2CLR); au_writel(1<<(irq_nr-32), IC1_CFG1CLR); au_writel(1<<(irq_nr-32), IC1_CFG0SET); - irq_desc[irq_nr].chip = &rise_edge_irq_type; + set_irq_chip(irq_nr, &rise_edge_irq_type); break; case INTC_INT_FALL_EDGE: /* 0:1:0 */ au_writel(1<<(irq_nr-32), IC1_CFG2CLR); au_writel(1<<(irq_nr-32), IC1_CFG1SET); au_writel(1<<(irq_nr-32), IC1_CFG0CLR); - irq_desc[irq_nr].chip = &fall_edge_irq_type; + set_irq_chip(irq_nr, &fall_edge_irq_type); break; case INTC_INT_RISE_AND_FALL_EDGE: /* 0:1:1 */ au_writel(1<<(irq_nr-32), IC1_CFG2CLR); au_writel(1<<(irq_nr-32), IC1_CFG1SET); au_writel(1<<(irq_nr-32), IC1_CFG0SET); - irq_desc[irq_nr].chip = &either_edge_irq_type; + set_irq_chip(irq_nr, &either_edge_irq_type); break; case INTC_INT_HIGH_LEVEL: /* 1:0:1 */ au_writel(1<<(irq_nr-32), IC1_CFG2SET); au_writel(1<<(irq_nr-32), IC1_CFG1CLR); au_writel(1<<(irq_nr-32), IC1_CFG0SET); - irq_desc[irq_nr].chip = &level_irq_type; + set_irq_chip(irq_nr, &level_irq_type); break; case INTC_INT_LOW_LEVEL: /* 1:1:0 */ au_writel(1<<(irq_nr-32), IC1_CFG2SET); au_writel(1<<(irq_nr-32), IC1_CFG1SET); au_writel(1<<(irq_nr-32), IC1_CFG0CLR); - irq_desc[irq_nr].chip = &level_irq_type; + set_irq_chip(irq_nr, &level_irq_type); break; case INTC_INT_DISABLED: /* 0:0:0 */ au_writel(1<<(irq_nr-32), IC1_CFG0CLR); @@ -380,31 +361,31 @@ static void setup_local_irq(unsigned int irq_nr, int type, int int_req) au_writel(1< #include #include -#include #include #include @@ -231,13 +230,10 @@ irqreturn_t dec_ecc_be_interrupt(int irq, void *dev_id) static inline void dec_kn02_be_init(void) { volatile u32 *csr = (void *)CKSEG1ADDR(KN02_SLOT_BASE + KN02_CSR); - unsigned long flags; kn0x_erraddr = (void *)CKSEG1ADDR(KN02_SLOT_BASE + KN02_ERRADDR); kn0x_chksyn = (void *)CKSEG1ADDR(KN02_SLOT_BASE + KN02_CHKSYN); - spin_lock_irqsave(&kn02_lock, flags); - /* Preset write-only bits of the Control Register cache. */ cached_kn02_csr = *csr | KN02_CSR_LEDS; @@ -247,8 +243,6 @@ static inline void dec_kn02_be_init(void) cached_kn02_csr |= KN02_CSR_CORRECT; *csr = cached_kn02_csr; iob(); - - spin_unlock_irqrestore(&kn02_lock, flags); } static inline void dec_kn03_be_init(void) diff --git a/arch/mips/dec/ioasic-irq.c b/arch/mips/dec/ioasic-irq.c index 41cd2a9..d0af08b 100644 --- a/arch/mips/dec/ioasic-irq.c +++ b/arch/mips/dec/ioasic-irq.c @@ -13,7 +13,6 @@ #include #include -#include #include #include @@ -21,8 +20,6 @@ #include -static DEFINE_SPINLOCK(ioasic_lock); - static int ioasic_irq_base; @@ -52,65 +49,31 @@ static inline void clear_ioasic_irq(unsigned int irq) ioasic_write(IO_REG_SIR, sir); } -static inline void enable_ioasic_irq(unsigned int irq) -{ - unsigned long flags; - - spin_lock_irqsave(&ioasic_lock, flags); - unmask_ioasic_irq(irq); - spin_unlock_irqrestore(&ioasic_lock, flags); -} - -static inline void disable_ioasic_irq(unsigned int irq) -{ - unsigned long flags; - - spin_lock_irqsave(&ioasic_lock, flags); - mask_ioasic_irq(irq); - spin_unlock_irqrestore(&ioasic_lock, flags); -} - - -static inline unsigned int startup_ioasic_irq(unsigned int irq) -{ - enable_ioasic_irq(irq); - return 0; -} - -#define shutdown_ioasic_irq disable_ioasic_irq - static inline void ack_ioasic_irq(unsigned int irq) { - spin_lock(&ioasic_lock); mask_ioasic_irq(irq); - spin_unlock(&ioasic_lock); fast_iob(); } static inline void end_ioasic_irq(unsigned int irq) { if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) - enable_ioasic_irq(irq); + unmask_ioasic_irq(irq); } static struct irq_chip ioasic_irq_type = { .typename = "IO-ASIC", - .startup = startup_ioasic_irq, - .shutdown = shutdown_ioasic_irq, - .enable = enable_ioasic_irq, - .disable = disable_ioasic_irq, .ack = ack_ioasic_irq, + .mask = mask_ioasic_irq, + .mask_ack = ack_ioasic_irq, + .unmask = unmask_ioasic_irq, .end = end_ioasic_irq, }; -#define startup_ioasic_dma_irq startup_ioasic_irq - -#define shutdown_ioasic_dma_irq shutdown_ioasic_irq - -#define enable_ioasic_dma_irq enable_ioasic_irq +#define unmask_ioasic_dma_irq unmask_ioasic_irq -#define disable_ioasic_dma_irq disable_ioasic_irq +#define mask_ioasic_dma_irq mask_ioasic_irq #define ack_ioasic_dma_irq ack_ioasic_irq @@ -123,11 +86,10 @@ static inline void end_ioasic_dma_irq(unsigned int irq) static struct irq_chip ioasic_dma_irq_type = { .typename = "IO-ASIC-DMA", - .startup = startup_ioasic_dma_irq, - .shutdown = shutdown_ioasic_dma_irq, - .enable = enable_ioasic_dma_irq, - .disable = disable_ioasic_dma_irq, .ack = ack_ioasic_dma_irq, + .mask = mask_ioasic_dma_irq, + .mask_ack = ack_ioasic_dma_irq, + .unmask = unmask_ioasic_dma_irq, .end = end_ioasic_dma_irq, }; @@ -140,18 +102,10 @@ void __init init_ioasic_irqs(int base) ioasic_write(IO_REG_SIMR, 0); fast_iob(); - for (i = base; i < base + IO_INR_DMA; i++) { - irq_desc[i].status = IRQ_DISABLED; - irq_desc[i].action = 0; - irq_desc[i].depth = 1; - irq_desc[i].chip = &ioasic_irq_type; - } - for (; i < base + IO_IRQ_LINES; i++) { - irq_desc[i].status = IRQ_DISABLED; - irq_desc[i].action = 0; - irq_desc[i].depth = 1; - irq_desc[i].chip = &ioasic_dma_irq_type; - } + for (i = base; i < base + IO_INR_DMA; i++) + set_irq_chip(i, &ioasic_irq_type); + for (; i < base + IO_IRQ_LINES; i++) + set_irq_chip(i, &ioasic_dma_irq_type); ioasic_irq_base = base; } diff --git a/arch/mips/dec/kn02-irq.c b/arch/mips/dec/kn02-irq.c index 04a367a..c761d97 100644 --- a/arch/mips/dec/kn02-irq.c +++ b/arch/mips/dec/kn02-irq.c @@ -14,7 +14,6 @@ #include #include -#include #include #include @@ -29,7 +28,6 @@ * There is no default value -- it has to be initialized. */ u32 cached_kn02_csr; -DEFINE_SPINLOCK(kn02_lock); static int kn02_irq_base; @@ -53,54 +51,24 @@ static inline void mask_kn02_irq(unsigned int irq) *csr = cached_kn02_csr; } -static inline void enable_kn02_irq(unsigned int irq) -{ - unsigned long flags; - - spin_lock_irqsave(&kn02_lock, flags); - unmask_kn02_irq(irq); - spin_unlock_irqrestore(&kn02_lock, flags); -} - -static inline void disable_kn02_irq(unsigned int irq) -{ - unsigned long flags; - - spin_lock_irqsave(&kn02_lock, flags); - mask_kn02_irq(irq); - spin_unlock_irqrestore(&kn02_lock, flags); -} - - -static unsigned int startup_kn02_irq(unsigned int irq) -{ - enable_kn02_irq(irq); - return 0; -} - -#define shutdown_kn02_irq disable_kn02_irq - static void ack_kn02_irq(unsigned int irq) { - spin_lock(&kn02_lock); mask_kn02_irq(irq); - spin_unlock(&kn02_lock); iob(); } static void end_kn02_irq(unsigned int irq) { if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) - enable_kn02_irq(irq); + unmask_kn02_irq(irq); } static struct irq_chip kn02_irq_type = { .typename = "KN02-CSR", - .startup = startup_kn02_irq, - .shutdown = shutdown_kn02_irq, - .enable = enable_kn02_irq, - .disable = disable_kn02_irq, .ack = ack_kn02_irq, + .mask = mask_kn02_irq, + .mask_ack = ack_kn02_irq, + .unmask = unmask_kn02_irq, .end = end_kn02_irq, }; @@ -109,22 +77,15 @@ void __init init_kn02_irqs(int base) { volatile u32 *csr = (volatile u32 *)CKSEG1ADDR(KN02_SLOT_BASE + KN02_CSR); - unsigned long flags; int i; /* Mask interrupts. */ - spin_lock_irqsave(&kn02_lock, flags); cached_kn02_csr &= ~KN02_CSR_IOINTEN; *csr = cached_kn02_csr; iob(); - spin_unlock_irqrestore(&kn02_lock, flags); - - for (i = base; i < base + KN02_IRQ_LINES; i++) { - irq_desc[i].status = IRQ_DISABLED; - irq_desc[i].action = 0; - irq_desc[i].depth = 1; - irq_desc[i].chip = &kn02_irq_type; - } + + for (i = base; i < base + KN02_IRQ_LINES; i++) + set_irq_chip(i, &kn02_irq_type); kn02_irq_base = base; } diff --git a/arch/mips/emma2rh/common/irq_emma2rh.c b/arch/mips/emma2rh/common/irq_emma2rh.c index 197ed4c..bf1b83b 100644 --- a/arch/mips/emma2rh/common/irq_emma2rh.c +++ b/arch/mips/emma2rh/common/irq_emma2rh.c @@ -56,22 +56,6 @@ static void emma2rh_irq_disable(unsigned int irq) ll_emma2rh_irq_disable(irq - emma2rh_irq_base); } -static unsigned int emma2rh_irq_startup(unsigned int irq) -{ - emma2rh_irq_enable(irq); - return 0; -} - -#define emma2rh_irq_shutdown emma2rh_irq_disable - -static void emma2rh_irq_ack(unsigned int irq) -{ - /* disable interrupt - some handler will re-enable the irq - * and if the interrupt is leveled, we will have infinite loop - */ - ll_emma2rh_irq_disable(irq - emma2rh_irq_base); -} - static void emma2rh_irq_end(unsigned int irq) { if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) @@ -80,25 +64,19 @@ static void emma2rh_irq_end(unsigned int irq) struct irq_chip emma2rh_irq_controller = { .typename = "emma2rh_irq", - .startup = emma2rh_irq_startup, - .shutdown = emma2rh_irq_shutdown, - .enable = emma2rh_irq_enable, - .disable = emma2rh_irq_disable, - .ack = emma2rh_irq_ack, + .ack = emma2rh_irq_disable, + .mask = emma2rh_irq_disable, + .mask_ack = emma2rh_irq_disable, + .unmask = emma2rh_irq_enable, .end = emma2rh_irq_end, - .set_affinity = NULL /* no affinity stuff for UP */ }; void emma2rh_irq_init(u32 irq_base) { u32 i; - for (i = irq_base; i < irq_base + NUM_EMMA2RH_IRQ; i++) { - irq_desc[i].status = IRQ_DISABLED; - irq_desc[i].action = NULL; - irq_desc[i].depth = 1; - irq_desc[i].chip = &emma2rh_irq_controller; - } + for (i = irq_base; i < irq_base + NUM_EMMA2RH_IRQ; i++) + set_irq_chip(i, &emma2rh_irq_controller); emma2rh_irq_base = irq_base; } diff --git a/arch/mips/emma2rh/markeins/irq_markeins.c b/arch/mips/emma2rh/markeins/irq_markeins.c index 0b36eb0..8e5f08a 100644 --- a/arch/mips/emma2rh/markeins/irq_markeins.c +++ b/arch/mips/emma2rh/markeins/irq_markeins.c @@ -48,19 +48,6 @@ static void emma2rh_sw_irq_disable(unsigned int irq) ll_emma2rh_sw_irq_disable(irq - emma2rh_sw_irq_base); } -static unsigned int emma2rh_sw_irq_startup(unsigned int irq) -{ - emma2rh_sw_irq_enable(irq); - return 0; -} - -#define emma2rh_sw_irq_shutdown emma2rh_sw_irq_disable - -static void emma2rh_sw_irq_ack(unsigned int irq) -{ - ll_emma2rh_sw_irq_disable(irq - emma2rh_sw_irq_base); -} - static void emma2rh_sw_irq_end(unsigned int irq) { if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) @@ -69,25 +56,19 @@ static void emma2rh_sw_irq_end(unsigned int irq) struct irq_chip emma2rh_sw_irq_controller = { .typename = "emma2rh_sw_irq", - .startup = emma2rh_sw_irq_startup, - .shutdown = emma2rh_sw_irq_shutdown, - .enable = emma2rh_sw_irq_enable, - .disable = emma2rh_sw_irq_disable, - .ack = emma2rh_sw_irq_ack, + .ack = emma2rh_sw_irq_disable, + .mask = emma2rh_sw_irq_disable, + .mask_ack = emma2rh_sw_irq_disable, + .unmask = emma2rh_sw_irq_enable, .end = emma2rh_sw_irq_end, - .set_affinity = NULL, }; void emma2rh_sw_irq_init(u32 irq_base) { u32 i; - for (i = irq_base; i < irq_base + NUM_EMMA2RH_IRQ_SW; i++) { - irq_desc[i].status = IRQ_DISABLED; - irq_desc[i].action = NULL; - irq_desc[i].depth = 2; - irq_desc[i].chip = &emma2rh_sw_irq_controller; - } + for (i = irq_base; i < irq_base + NUM_EMMA2RH_IRQ_SW; i++) + set_irq_chip(i, &emma2rh_sw_irq_controller); emma2rh_sw_irq_base = irq_base; } @@ -126,14 +107,6 @@ static void emma2rh_gpio_irq_disable(unsigned int irq) ll_emma2rh_gpio_irq_disable(irq - emma2rh_gpio_irq_base); } -static unsigned int emma2rh_gpio_irq_startup(unsigned int irq) -{ - emma2rh_gpio_irq_enable(irq); - return 0; -} - -#define emma2rh_gpio_irq_shutdown emma2rh_gpio_irq_disable - static void emma2rh_gpio_irq_ack(unsigned int irq) { irq -= emma2rh_gpio_irq_base; @@ -149,25 +122,19 @@ static void emma2rh_gpio_irq_end(unsigned int irq) struct irq_chip emma2rh_gpio_irq_controller = { .typename = "emma2rh_gpio_irq", - .startup = emma2rh_gpio_irq_startup, - .shutdown = emma2rh_gpio_irq_shutdown, - .enable = emma2rh_gpio_irq_enable, - .disable = emma2rh_gpio_irq_disable, .ack = emma2rh_gpio_irq_ack, + .mask = emma2rh_gpio_irq_disable, + .mask_ack = emma2rh_gpio_irq_ack, + .unmask = emma2rh_gpio_irq_enable, .end = emma2rh_gpio_irq_end, - .set_affinity = NULL, }; void emma2rh_gpio_irq_init(u32 irq_base) { u32 i; - for (i = irq_base; i < irq_base + NUM_EMMA2RH_IRQ_GPIO; i++) { - irq_desc[i].status = IRQ_DISABLED; - irq_desc[i].action = NULL; - irq_desc[i].depth = 2; - irq_desc[i].chip = &emma2rh_gpio_irq_controller; - } + for (i = irq_base; i < irq_base + NUM_EMMA2RH_IRQ_GPIO; i++) + set_irq_chip(i, &emma2rh_gpio_irq_controller); emma2rh_gpio_irq_base = irq_base; } diff --git a/arch/mips/gt64120/ev64120/irq.c b/arch/mips/gt64120/ev64120/irq.c index ed4d82b..b3e5796 100644 --- a/arch/mips/gt64120/ev64120/irq.c +++ b/arch/mips/gt64120/ev64120/irq.c @@ -66,38 +66,21 @@ asmlinkage void plat_irq_dispatch(void) static void disable_ev64120_irq(unsigned int irq_nr) { - unsigned long flags; - - local_irq_save(flags); if (irq_nr >= 8) { // All PCI interrupts are on line 5 or 2 clear_c0_status(9 << 10); } else { clear_c0_status(1 << (irq_nr + 8)); } - local_irq_restore(flags); } static void enable_ev64120_irq(unsigned int irq_nr) { - unsigned long flags; - - local_irq_save(flags); if (irq_nr >= 8) // All PCI interrupts are on line 5 or 2 set_c0_status(9 << 10); else set_c0_status(1 << (irq_nr + 8)); - local_irq_restore(flags); -} - -static unsigned int startup_ev64120_irq(unsigned int irq) -{ - enable_ev64120_irq(irq); - return 0; /* Never anything pending */ } -#define shutdown_ev64120_irq disable_ev64120_irq -#define mask_and_ack_ev64120_irq disable_ev64120_irq - static void end_ev64120_irq(unsigned int irq) { if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) @@ -106,13 +89,11 @@ static void end_ev64120_irq(unsigned int irq) static struct irq_chip ev64120_irq_type = { .typename = "EV64120", - .startup = startup_ev64120_irq, - .shutdown = shutdown_ev64120_irq, - .enable = enable_ev64120_irq, - .disable = disable_ev64120_irq, - .ack = mask_and_ack_ev64120_irq, + .ack = disable_ev64120_irq, + .mask = disable_ev64120_irq, + .mask_ack = disable_ev64120_irq, + .unmask = enable_ev64120_irq, .end = end_ev64120_irq, - .set_affinity = NULL }; void gt64120_irq_setup(void) @@ -122,8 +103,6 @@ void gt64120_irq_setup(void) */ clear_c0_status(ST0_IM); - local_irq_disable(); - /* * Enable timer. Other interrupts will be enabled as they are * registered. @@ -133,16 +112,5 @@ void gt64120_irq_setup(void) void __init arch_init_irq(void) { - int i; - - /* Let's initialize our IRQ descriptors */ - for (i = 0; i < NR_IRQS; i++) { - irq_desc[i].status = 0; - irq_desc[i].chip = &no_irq_chip; - irq_desc[i].action = NULL; - irq_desc[i].depth = 0; - spin_lock_init(&irq_desc[i].lock); - } - gt64120_irq_setup(); } diff --git a/arch/mips/jazz/irq.c b/arch/mips/jazz/irq.c index d5bd6b3..4bbb6cb 100644 --- a/arch/mips/jazz/irq.c +++ b/arch/mips/jazz/irq.c @@ -28,14 +28,6 @@ static void enable_r4030_irq(unsigned int irq) spin_unlock_irqrestore(&r4030_lock, flags); } -static unsigned int startup_r4030_irq(unsigned int irq) -{ - enable_r4030_irq(irq); - return 0; /* never anything pending */ -} - -#define shutdown_r4030_irq disable_r4030_irq - void disable_r4030_irq(unsigned int irq) { unsigned int mask = ~(1 << (irq - JAZZ_PARALLEL_IRQ)); @@ -47,8 +39,6 @@ void disable_r4030_irq(unsigned int irq) spin_unlock_irqrestore(&r4030_lock, flags); } -#define mask_and_ack_r4030_irq disable_r4030_irq - static void end_r4030_irq(unsigned int irq) { if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) @@ -57,11 +47,10 @@ static void end_r4030_irq(unsigned int irq) static struct irq_chip r4030_irq_type = { .typename = "R4030", - .startup = startup_r4030_irq, - .shutdown = shutdown_r4030_irq, - .enable = enable_r4030_irq, - .disable = disable_r4030_irq, - .ack = mask_and_ack_r4030_irq, + .ack = disable_r4030_irq, + .mask = disable_r4030_irq, + .mask_ack = disable_r4030_irq, + .unmask = enable_r4030_irq, .end = end_r4030_irq, }; @@ -69,12 +58,8 @@ void __init init_r4030_ints(void) { int i; - for (i = JAZZ_PARALLEL_IRQ; i <= JAZZ_TIMER_IRQ; i++) { - irq_desc[i].status = IRQ_DISABLED; - irq_desc[i].action = 0; - irq_desc[i].depth = 1; - irq_desc[i].chip = &r4030_irq_type; - } + for (i = JAZZ_PARALLEL_IRQ; i <= JAZZ_TIMER_IRQ; i++) + set_irq_chip(i, &r4030_irq_type); r4030_write_reg16(JAZZ_IO_IRQ_ENABLE, 0); r4030_read_reg16(JAZZ_IO_IRQ_SOURCE); /* clear pending IRQs */ diff --git a/arch/mips/jmr3927/rbhma3100/irq.c b/arch/mips/jmr3927/rbhma3100/irq.c index de4a238..3da49c5 100644 --- a/arch/mips/jmr3927/rbhma3100/irq.c +++ b/arch/mips/jmr3927/rbhma3100/irq.c @@ -90,17 +90,6 @@ static unsigned char irc_level[TX3927_NUM_IR] = { static void jmr3927_irq_disable(unsigned int irq_nr); static void jmr3927_irq_enable(unsigned int irq_nr); -static DEFINE_SPINLOCK(jmr3927_irq_lock); - -static unsigned int jmr3927_irq_startup(unsigned int irq) -{ - jmr3927_irq_enable(irq); - - return 0; -} - -#define jmr3927_irq_shutdown jmr3927_irq_disable - static void jmr3927_irq_ack(unsigned int irq) { if (irq == JMR3927_IRQ_IRC_TMR0) @@ -118,9 +107,7 @@ static void jmr3927_irq_end(unsigned int irq) static void jmr3927_irq_disable(unsigned int irq_nr) { struct tb_irq_space* sp; - unsigned long flags; - spin_lock_irqsave(&jmr3927_irq_lock, flags); for (sp = tb_irq_spaces; sp; sp = sp->next) { if (sp->start_irqno <= irq_nr && irq_nr < sp->start_irqno + sp->nr_irqs) { @@ -130,15 +117,12 @@ static void jmr3927_irq_disable(unsigned int irq_nr) break; } } - spin_unlock_irqrestore(&jmr3927_irq_lock, flags); } static void jmr3927_irq_enable(unsigned int irq_nr) { struct tb_irq_space* sp; - unsigned long flags; - spin_lock_irqsave(&jmr3927_irq_lock, flags); for (sp = tb_irq_spaces; sp; sp = sp->next) { if (sp->start_irqno <= irq_nr && irq_nr < sp->start_irqno + sp->nr_irqs) { @@ -148,7 +132,6 @@ static void jmr3927_irq_enable(unsigned int irq_nr) break; } } - spin_unlock_irqrestore(&jmr3927_irq_lock, flags); } /* @@ -457,11 +440,10 @@ void __init arch_init_irq(void) static struct irq_chip jmr3927_irq_controller = { .typename = "jmr3927_irq", - .startup = jmr3927_irq_startup, - .shutdown = jmr3927_irq_shutdown, - .enable = jmr3927_irq_enable, - .disable = jmr3927_irq_disable, .ack = jmr3927_irq_ack, + .mask = jmr3927_irq_disable, + .mask_ack = jmr3927_irq_ack, + .unmask = jmr3927_irq_enable, .end = jmr3927_irq_end, }; @@ -469,12 +451,8 @@ void jmr3927_irq_init(u32 irq_base) { u32 i; - for (i= irq_base; i< irq_base + JMR3927_NR_IRQ_IRC + JMR3927_NR_IRQ_IOC; i++) { - irq_desc[i].status = IRQ_DISABLED; - irq_desc[i].action = NULL; - irq_desc[i].depth = 1; - irq_desc[i].chip = &jmr3927_irq_controller; - } + for (i= irq_base; i< irq_base + JMR3927_NR_IRQ_IRC + JMR3927_NR_IRQ_IOC; i++) + set_irq_chip(i, &jmr3927_irq_controller); jmr3927_irq_base = irq_base; } diff --git a/arch/mips/kernel/i8259.c b/arch/mips/kernel/i8259.c index 48e3418..2526c0c 100644 --- a/arch/mips/kernel/i8259.c +++ b/arch/mips/kernel/i8259.c @@ -40,21 +40,10 @@ static void end_8259A_irq (unsigned int irq) enable_8259A_irq(irq); } -#define shutdown_8259A_irq disable_8259A_irq - void mask_and_ack_8259A(unsigned int); -static unsigned int startup_8259A_irq(unsigned int irq) -{ - enable_8259A_irq(irq); - - return 0; /* never anything pending */ -} - static struct irq_chip i8259A_irq_type = { .typename = "XT-PIC", - .startup = startup_8259A_irq, - .shutdown = shutdown_8259A_irq, .enable = enable_8259A_irq, .disable = disable_8259A_irq, .ack = mask_and_ack_8259A, @@ -120,7 +109,7 @@ int i8259A_irq_pending(unsigned int irq) void make_8259A_irq(unsigned int irq) { disable_irq_nosync(irq); - irq_desc[irq].chip = &i8259A_irq_type; + set_irq_chip(irq, &i8259A_irq_type); enable_irq(irq); } @@ -323,12 +312,8 @@ void __init init_i8259_irqs (void) init_8259A(0); - for (i = 0; i < 16; i++) { - irq_desc[i].status = IRQ_DISABLED; - irq_desc[i].action = NULL; - irq_desc[i].depth = 1; - irq_desc[i].chip = &i8259A_irq_type; - } + for (i = 0; i < 16; i++) + set_irq_chip(i, &i8259A_irq_type); setup_irq(2, &irq2); } diff --git a/arch/mips/kernel/irq-msc01.c b/arch/mips/kernel/irq-msc01.c index 650a80c..e1880b2 100644 --- a/arch/mips/kernel/irq-msc01.c +++ b/arch/mips/kernel/irq-msc01.c @@ -45,31 +45,6 @@ static inline void unmask_msc_irq(unsigned int irq) } /* - * Enables the IRQ on SOC-it - */ -static void enable_msc_irq(unsigned int irq) -{ - unmask_msc_irq(irq); -} - -/* - * Initialize the IRQ on SOC-it - */ -static unsigned int startup_msc_irq(unsigned int irq) -{ - unmask_msc_irq(irq); - return 0; -} - -/* - * Disables the IRQ on SOC-it - */ -static void disable_msc_irq(unsigned int irq) -{ - mask_msc_irq(irq); -} - -/* * Masks and ACKs an IRQ */ static void level_mask_and_ack_msc_irq(unsigned int irq) @@ -136,25 +111,21 @@ msc_bind_eic_interrupt (unsigned int irq, unsigned int set) (irq<im_type) { case MSC01_IRQ_EDGE: - irq_desc[base+n].chip = &msc_edgeirq_type; + set_irq_chip(base+n, &msc_edgeirq_type); if (cpu_has_veic) MSCIC_WRITE(MSC01_IC_SUP+n*8, MSC01_IC_SUP_EDGE_BIT); else MSCIC_WRITE(MSC01_IC_SUP+n*8, MSC01_IC_SUP_EDGE_BIT | imp->im_lvl); break; case MSC01_IRQ_LEVEL: - irq_desc[base+n].chip = &msc_levelirq_type; + set_irq_chip(base+n, &msc_levelirq_type); if (cpu_has_veic) MSCIC_WRITE(MSC01_IC_SUP+n*8, 0); else diff --git a/arch/mips/kernel/irq-mv6434x.c b/arch/mips/kernel/irq-mv6434x.c index 37d1062..5012b9d 100644 --- a/arch/mips/kernel/irq-mv6434x.c +++ b/arch/mips/kernel/irq-mv6434x.c @@ -67,39 +67,6 @@ static inline void unmask_mv64340_irq(unsigned int irq) } /* - * Enables the IRQ on Marvell Chip - */ -static void enable_mv64340_irq(unsigned int irq) -{ - unmask_mv64340_irq(irq); -} - -/* - * Initialize the IRQ on Marvell Chip - */ -static unsigned int startup_mv64340_irq(unsigned int irq) -{ - unmask_mv64340_irq(irq); - return 0; -} - -/* - * Disables the IRQ on Marvell Chip - */ -static void disable_mv64340_irq(unsigned int irq) -{ - mask_mv64340_irq(irq); -} - -/* - * Masks and ACKs an IRQ - */ -static void mask_and_ack_mv64340_irq(unsigned int irq) -{ - mask_mv64340_irq(irq); -} - -/* * End IRQ processing */ static void end_mv64340_irq(unsigned int irq) @@ -133,15 +100,12 @@ void ll_mv64340_irq(void) do_IRQ(ls1bit32(irq_src_high) + irq_base + 32); } -#define shutdown_mv64340_irq disable_mv64340_irq - struct irq_chip mv64340_irq_type = { .typename = "MV-64340", - .startup = startup_mv64340_irq, - .shutdown = shutdown_mv64340_irq, - .enable = enable_mv64340_irq, - .disable = disable_mv64340_irq, - .ack = mask_and_ack_mv64340_irq, + .ack = mask_mv64340_irq, + .mask = mask_mv64340_irq, + .mask_ack = mask_mv64340_irq, + .unmask = unmask_mv64340_irq, .end = end_mv64340_irq, }; @@ -149,13 +113,8 @@ void __init mv64340_irq_init(unsigned int base) { int i; - /* Reset irq handlers pointers to NULL */ - for (i = base; i < base + 64; i++) { - irq_desc[i].status = IRQ_DISABLED; - irq_desc[i].action = 0; - irq_desc[i].depth = 2; - irq_desc[i].chip = &mv64340_irq_type; - } + for (i = base; i < base + 64; i++) + set_irq_chip(i, &mv64340_irq_type); irq_base = base; } diff --git a/arch/mips/kernel/irq-rm7000.c b/arch/mips/kernel/irq-rm7000.c index 6b54c71..6a297e3 100644 --- a/arch/mips/kernel/irq-rm7000.c +++ b/arch/mips/kernel/irq-rm7000.c @@ -29,42 +29,6 @@ static inline void mask_rm7k_irq(unsigned int irq) clear_c0_intcontrol(0x100 << (irq - irq_base)); } -static inline void rm7k_cpu_irq_enable(unsigned int irq) -{ - unsigned long flags; - - local_irq_save(flags); - unmask_rm7k_irq(irq); - local_irq_restore(flags); -} - -static void rm7k_cpu_irq_disable(unsigned int irq) -{ - unsigned long flags; - - local_irq_save(flags); - mask_rm7k_irq(irq); - local_irq_restore(flags); -} - -static unsigned int rm7k_cpu_irq_startup(unsigned int irq) -{ - rm7k_cpu_irq_enable(irq); - - return 0; -} - -#define rm7k_cpu_irq_shutdown rm7k_cpu_irq_disable - -/* - * While we ack the interrupt interrupts are disabled and thus we don't need - * to deal with concurrency issues. Same for rm7k_cpu_irq_end. - */ -static void rm7k_cpu_irq_ack(unsigned int irq) -{ - mask_rm7k_irq(irq); -} - static void rm7k_cpu_irq_end(unsigned int irq) { if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) @@ -73,11 +37,10 @@ static void rm7k_cpu_irq_end(unsigned int irq) static struct irq_chip rm7k_irq_controller = { .typename = "RM7000", - .startup = rm7k_cpu_irq_startup, - .shutdown = rm7k_cpu_irq_shutdown, - .enable = rm7k_cpu_irq_enable, - .disable = rm7k_cpu_irq_disable, - .ack = rm7k_cpu_irq_ack, + .ack = mask_rm7k_irq, + .mask = mask_rm7k_irq, + .mask_ack = mask_rm7k_irq, + .unmask = unmask_rm7k_irq, .end = rm7k_cpu_irq_end, }; @@ -87,12 +50,8 @@ void __init rm7k_cpu_irq_init(int base) clear_c0_intcontrol(0x00000f00); /* Mask all */ - for (i = base; i < base + 4; i++) { - irq_desc[i].status = IRQ_DISABLED; - irq_desc[i].action = NULL; - irq_desc[i].depth = 1; - irq_desc[i].chip = &rm7k_irq_controller; - } + for (i = base; i < base + 4; i++) + set_irq_chip(i, &rm7k_irq_controller); irq_base = base; } diff --git a/arch/mips/kernel/irq-rm9000.c b/arch/mips/kernel/irq-rm9000.c index 62f011b..9775384 100644 --- a/arch/mips/kernel/irq-rm9000.c +++ b/arch/mips/kernel/irq-rm9000.c @@ -48,15 +48,6 @@ static void rm9k_cpu_irq_disable(unsigned int irq) local_irq_restore(flags); } -static unsigned int rm9k_cpu_irq_startup(unsigned int irq) -{ - rm9k_cpu_irq_enable(irq); - - return 0; -} - -#define rm9k_cpu_irq_shutdown rm9k_cpu_irq_disable - /* * Performance counter interrupts are global on all processors. */ @@ -89,16 +80,6 @@ static void rm9k_perfcounter_irq_shutdown(unsigned int irq) on_each_cpu(local_rm9k_perfcounter_irq_shutdown, (void *) irq, 0, 1); } - -/* - * While we ack the interrupt interrupts are disabled and thus we don't need - * to deal with concurrency issues. Same for rm9k_cpu_irq_end. - */ -static void rm9k_cpu_irq_ack(unsigned int irq) -{ - mask_rm9k_irq(irq); -} - static void rm9k_cpu_irq_end(unsigned int irq) { if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) @@ -107,11 +88,10 @@ static void rm9k_cpu_irq_end(unsigned int irq) static struct irq_chip rm9k_irq_controller = { .typename = "RM9000", - .startup = rm9k_cpu_irq_startup, - .shutdown = rm9k_cpu_irq_shutdown, - .enable = rm9k_cpu_irq_enable, - .disable = rm9k_cpu_irq_disable, - .ack = rm9k_cpu_irq_ack, + .ack = mask_rm9k_irq, + .mask = mask_rm9k_irq, + .mask_ack = mask_rm9k_irq, + .unmask = unmask_rm9k_irq, .end = rm9k_cpu_irq_end, }; @@ -119,9 +99,10 @@ static struct irq_chip rm9k_perfcounter_irq = { .typename = "RM9000", .startup = rm9k_perfcounter_irq_startup, .shutdown = rm9k_perfcounter_irq_shutdown, - .enable = rm9k_cpu_irq_enable, - .disable = rm9k_cpu_irq_disable, - .ack = rm9k_cpu_irq_ack, + .ack = mask_rm9k_irq, + .mask = mask_rm9k_irq, + .mask_ack = mask_rm9k_irq, + .unmask = unmask_rm9k_irq, .end = rm9k_cpu_irq_end, }; @@ -135,15 +116,11 @@ void __init rm9k_cpu_irq_init(int base) clear_c0_intcontrol(0x0000f000); /* Mask all */ - for (i = base; i < base + 4; i++) { - irq_desc[i].status = IRQ_DISABLED; - irq_desc[i].action = NULL; - irq_desc[i].depth = 1; - irq_desc[i].chip = &rm9k_irq_controller; - } + for (i = base; i < base + 4; i++) + set_irq_chip(i, &rm9k_irq_controller); rm9000_perfcount_irq = base + 1; - irq_desc[rm9000_perfcount_irq].chip = &rm9k_perfcounter_irq; + set_irq_chip(rm9000_perfcount_irq, &rm9k_perfcounter_irq); irq_base = base; } diff --git a/arch/mips/kernel/irq.c b/arch/mips/kernel/irq.c index 9b0e49d..e997c94 100644 --- a/arch/mips/kernel/irq.c +++ b/arch/mips/kernel/irq.c @@ -172,19 +172,6 @@ __setup("nokgdb", nokgdb); void __init init_IRQ(void) { - int i; - - for (i = 0; i < NR_IRQS; i++) { - irq_desc[i].status = IRQ_DISABLED; - irq_desc[i].action = NULL; - irq_desc[i].depth = 1; - irq_desc[i].chip = &no_irq_chip; - spin_lock_init(&irq_desc[i].lock); -#ifdef CONFIG_MIPS_MT_SMTC - irq_hwmask[i] = 0; -#endif /* CONFIG_MIPS_MT_SMTC */ - } - arch_init_irq(); #ifdef CONFIG_KGDB diff --git a/arch/mips/kernel/irq_cpu.c b/arch/mips/kernel/irq_cpu.c index 9bb21c7..3b7cfa4 100644 --- a/arch/mips/kernel/irq_cpu.c +++ b/arch/mips/kernel/irq_cpu.c @@ -50,44 +50,6 @@ static inline void mask_mips_irq(unsigned int irq) irq_disable_hazard(); } -static inline void mips_cpu_irq_enable(unsigned int irq) -{ - unsigned long flags; - - local_irq_save(flags); - unmask_mips_irq(irq); - back_to_back_c0_hazard(); - local_irq_restore(flags); -} - -static void mips_cpu_irq_disable(unsigned int irq) -{ - unsigned long flags; - - local_irq_save(flags); - mask_mips_irq(irq); - back_to_back_c0_hazard(); - local_irq_restore(flags); -} - -static unsigned int mips_cpu_irq_startup(unsigned int irq) -{ - mips_cpu_irq_enable(irq); - - return 0; -} - -#define mips_cpu_irq_shutdown mips_cpu_irq_disable - -/* - * While we ack the interrupt interrupts are disabled and thus we don't need - * to deal with concurrency issues. Same for mips_cpu_irq_end. - */ -static void mips_cpu_irq_ack(unsigned int irq) -{ - mask_mips_irq(irq); -} - static void mips_cpu_irq_end(unsigned int irq) { if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) @@ -96,11 +58,10 @@ static void mips_cpu_irq_end(unsigned int irq) static struct irq_chip mips_cpu_irq_controller = { .typename = "MIPS", - .startup = mips_cpu_irq_startup, - .shutdown = mips_cpu_irq_shutdown, - .enable = mips_cpu_irq_enable, - .disable = mips_cpu_irq_disable, - .ack = mips_cpu_irq_ack, + .ack = mask_mips_irq, + .mask = mask_mips_irq, + .mask_ack = mask_mips_irq, + .unmask = unmask_mips_irq, .end = mips_cpu_irq_end, }; @@ -110,8 +71,6 @@ static struct irq_chip mips_cpu_irq_controller = { #define unmask_mips_mt_irq unmask_mips_irq #define mask_mips_mt_irq mask_mips_irq -#define mips_mt_cpu_irq_enable mips_cpu_irq_enable -#define mips_mt_cpu_irq_disable mips_cpu_irq_disable static unsigned int mips_mt_cpu_irq_startup(unsigned int irq) { @@ -119,13 +78,11 @@ static unsigned int mips_mt_cpu_irq_startup(unsigned int irq) clear_c0_cause(0x100 << (irq - mips_cpu_irq_base)); evpe(vpflags); - mips_mt_cpu_irq_enable(irq); + unmask_mips_mt_irq(irq); return 0; } -#define mips_mt_cpu_irq_shutdown mips_mt_cpu_irq_disable - /* * While we ack the interrupt interrupts are disabled and thus we don't need * to deal with concurrency issues. Same for mips_cpu_irq_end. @@ -143,10 +100,10 @@ static void mips_mt_cpu_irq_ack(unsigned int irq) static struct irq_chip mips_mt_cpu_irq_controller = { .typename = "MIPS", .startup = mips_mt_cpu_irq_startup, - .shutdown = mips_mt_cpu_irq_shutdown, - .enable = mips_mt_cpu_irq_enable, - .disable = mips_mt_cpu_irq_disable, .ack = mips_mt_cpu_irq_ack, + .mask = mask_mips_mt_irq, + .mask_ack = mips_mt_cpu_irq_ack, + .unmask = unmask_mips_mt_irq, .end = mips_mt_cpu_irq_end, }; @@ -163,19 +120,11 @@ void __init mips_cpu_irq_init(int irq_base) * leave them uninitialized for other processors. */ if (cpu_has_mipsmt) - for (i = irq_base; i < irq_base + 2; i++) { - irq_desc[i].status = IRQ_DISABLED; - irq_desc[i].action = NULL; - irq_desc[i].depth = 1; - irq_desc[i].chip = &mips_mt_cpu_irq_controller; - } - - for (i = irq_base + 2; i < irq_base + 8; i++) { - irq_desc[i].status = IRQ_DISABLED; - irq_desc[i].action = NULL; - irq_desc[i].depth = 1; - irq_desc[i].chip = &mips_cpu_irq_controller; - } + for (i = irq_base; i < irq_base + 2; i++) + set_irq_chip(i, &mips_mt_cpu_irq_controller); + + for (i = irq_base + 2; i < irq_base + 8; i++) + set_irq_chip(i, &mips_cpu_irq_controller); mips_cpu_irq_base = irq_base; } diff --git a/arch/mips/lasat/interrupt.c b/arch/mips/lasat/interrupt.c index a144a00..cac82af 100644 --- a/arch/mips/lasat/interrupt.c +++ b/arch/mips/lasat/interrupt.c @@ -36,33 +36,14 @@ static volatile int lasat_int_mask_shift; void disable_lasat_irq(unsigned int irq_nr) { - unsigned long flags; - - local_irq_save(flags); *lasat_int_mask &= ~(1 << irq_nr) << lasat_int_mask_shift; - local_irq_restore(flags); } void enable_lasat_irq(unsigned int irq_nr) { - unsigned long flags; - - local_irq_save(flags); *lasat_int_mask |= (1 << irq_nr) << lasat_int_mask_shift; - local_irq_restore(flags); } -static unsigned int startup_lasat_irq(unsigned int irq) -{ - enable_lasat_irq(irq); - - return 0; /* never anything pending */ -} - -#define shutdown_lasat_irq disable_lasat_irq - -#define mask_and_ack_lasat_irq disable_lasat_irq - static void end_lasat_irq(unsigned int irq) { if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) @@ -71,11 +52,10 @@ static void end_lasat_irq(unsigned int irq) static struct irq_chip lasat_irq_type = { .typename = "Lasat", - .startup = startup_lasat_irq, - .shutdown = shutdown_lasat_irq, - .enable = enable_lasat_irq, - .disable = disable_lasat_irq, - .ack = mask_and_ack_lasat_irq, + .ack = disable_lasat_irq, + .mask = disable_lasat_irq, + .mask_ack = disable_lasat_irq, + .unmask = enable_lasat_irq, .end = end_lasat_irq, }; @@ -152,10 +132,6 @@ void __init arch_init_irq(void) panic("arch_init_irq: mips_machtype incorrect"); } - for (i = 0; i <= LASATINT_END; i++) { - irq_desc[i].status = IRQ_DISABLED; - irq_desc[i].action = 0; - irq_desc[i].depth = 1; - irq_desc[i].chip = &lasat_irq_type; - } + for (i = 0; i <= LASATINT_END; i++) + set_irq_chip(i, &lasat_irq_type); } diff --git a/arch/mips/mips-boards/atlas/atlas_int.c b/arch/mips/mips-boards/atlas/atlas_int.c index be624b8..7c71004 100644 --- a/arch/mips/mips-boards/atlas/atlas_int.c +++ b/arch/mips/mips-boards/atlas/atlas_int.c @@ -62,16 +62,6 @@ void enable_atlas_irq(unsigned int irq_nr) iob(); } -static unsigned int startup_atlas_irq(unsigned int irq) -{ - enable_atlas_irq(irq); - return 0; /* never anything pending */ -} - -#define shutdown_atlas_irq disable_atlas_irq - -#define mask_and_ack_atlas_irq disable_atlas_irq - static void end_atlas_irq(unsigned int irq) { if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) @@ -80,11 +70,10 @@ static void end_atlas_irq(unsigned int irq) static struct irq_chip atlas_irq_type = { .typename = "Atlas", - .startup = startup_atlas_irq, - .shutdown = shutdown_atlas_irq, - .enable = enable_atlas_irq, - .disable = disable_atlas_irq, - .ack = mask_and_ack_atlas_irq, + .ack = disable_atlas_irq, + .mask = disable_atlas_irq, + .mask_ack = disable_atlas_irq, + .unmask = enable_atlas_irq, .end = end_atlas_irq, }; @@ -217,13 +206,8 @@ static inline void init_atlas_irqs (int base) */ atlas_hw0_icregs->intrsten = 0xffffffff; - for (i = ATLAS_INT_BASE; i <= ATLAS_INT_END; i++) { - irq_desc[i].status = IRQ_DISABLED; - irq_desc[i].action = 0; - irq_desc[i].depth = 1; - irq_desc[i].chip = &atlas_irq_type; - spin_lock_init(&irq_desc[i].lock); - } + for (i = ATLAS_INT_BASE; i <= ATLAS_INT_END; i++) + set_irq_chip(i, &atlas_irq_type); } static struct irqaction atlasirq = { diff --git a/arch/mips/momentum/ocelot_c/cpci-irq.c b/arch/mips/momentum/ocelot_c/cpci-irq.c index 47e3fa3..7723f09 100644 --- a/arch/mips/momentum/ocelot_c/cpci-irq.c +++ b/arch/mips/momentum/ocelot_c/cpci-irq.c @@ -66,39 +66,6 @@ static inline void unmask_cpci_irq(unsigned int irq) } /* - * Enables the IRQ in the FPGA - */ -static void enable_cpci_irq(unsigned int irq) -{ - unmask_cpci_irq(irq); -} - -/* - * Initialize the IRQ in the FPGA - */ -static unsigned int startup_cpci_irq(unsigned int irq) -{ - unmask_cpci_irq(irq); - return 0; -} - -/* - * Disables the IRQ in the FPGA - */ -static void disable_cpci_irq(unsigned int irq) -{ - mask_cpci_irq(irq); -} - -/* - * Masks and ACKs an IRQ - */ -static void mask_and_ack_cpci_irq(unsigned int irq) -{ - mask_cpci_irq(irq); -} - -/* * End IRQ processing */ static void end_cpci_irq(unsigned int irq) @@ -125,15 +92,12 @@ void ll_cpci_irq(void) do_IRQ(ls1bit8(irq_src) + CPCI_IRQ_BASE); } -#define shutdown_cpci_irq disable_cpci_irq - struct irq_chip cpci_irq_type = { .typename = "CPCI/FPGA", - .startup = startup_cpci_irq, - .shutdown = shutdown_cpci_irq, - .enable = enable_cpci_irq, - .disable = disable_cpci_irq, - .ack = mask_and_ack_cpci_irq, + .ack = mask_cpci_irq, + .mask = mask_cpci_irq, + .mask_ack = mask_cpci_irq, + .unmask = unmask_cpci_irq, .end = end_cpci_irq, }; @@ -141,11 +105,6 @@ void cpci_irq_init(void) { int i; - /* Reset irq handlers pointers to NULL */ - for (i = CPCI_IRQ_BASE; i < (CPCI_IRQ_BASE + 8); i++) { - irq_desc[i].status = IRQ_DISABLED; - irq_desc[i].action = 0; - irq_desc[i].depth = 2; - irq_desc[i].chip = &cpci_irq_type; - } + for (i = CPCI_IRQ_BASE; i < (CPCI_IRQ_BASE + 8); i++) + set_irq_chip(i, &cpci_irq_type); } diff --git a/arch/mips/momentum/ocelot_c/uart-irq.c b/arch/mips/momentum/ocelot_c/uart-irq.c index 510257d..72faf81 100644 --- a/arch/mips/momentum/ocelot_c/uart-irq.c +++ b/arch/mips/momentum/ocelot_c/uart-irq.c @@ -60,39 +60,6 @@ static inline void unmask_uart_irq(unsigned int irq) } /* - * Enables the IRQ in the FPGA - */ -static void enable_uart_irq(unsigned int irq) -{ - unmask_uart_irq(irq); -} - -/* - * Initialize the IRQ in the FPGA - */ -static unsigned int startup_uart_irq(unsigned int irq) -{ - unmask_uart_irq(irq); - return 0; -} - -/* - * Disables the IRQ in the FPGA - */ -static void disable_uart_irq(unsigned int irq) -{ - mask_uart_irq(irq); -} - -/* - * Masks and ACKs an IRQ - */ -static void mask_and_ack_uart_irq(unsigned int irq) -{ - mask_uart_irq(irq); -} - -/* * End IRQ processing */ static void end_uart_irq(unsigned int irq) @@ -118,28 +85,17 @@ void ll_uart_irq(void) do_IRQ(ls1bit8(irq_src) + 74); } -#define shutdown_uart_irq disable_uart_irq - struct irq_chip uart_irq_type = { .typename = "UART/FPGA", - .startup = startup_uart_irq, - .shutdown = shutdown_uart_irq, - .enable = enable_uart_irq, - .disable = disable_uart_irq, - .ack = mask_and_ack_uart_irq, + .ack = mask_uart_irq, + .mask = mask_uart_irq, + .mask_ack = mask_uart_irq, + .unmask = unmask_uart_irq, .end = end_uart_irq, }; void uart_irq_init(void) { - /* Reset irq handlers pointers to NULL */ - irq_desc[80].status = IRQ_DISABLED; - irq_desc[80].action = 0; - irq_desc[80].depth = 2; - irq_desc[80].chip = &uart_irq_type; - - irq_desc[81].status = IRQ_DISABLED; - irq_desc[81].action = 0; - irq_desc[81].depth = 2; - irq_desc[81].chip = &uart_irq_type; + set_irq_chip(80, &uart_irq_type); + set_irq_chip(81, &uart_irq_type); } diff --git a/arch/mips/philips/pnx8550/common/int.c b/arch/mips/philips/pnx8550/common/int.c index 7106116..e4bf494 100644 --- a/arch/mips/philips/pnx8550/common/int.c +++ b/arch/mips/philips/pnx8550/common/int.c @@ -38,8 +38,6 @@ #include #include -static DEFINE_SPINLOCK(irq_lock); - /* default prio for interrupts */ /* first one is a no-no so therefore always prio 0 (disabled) */ static char gic_prio[PNX8550_INT_GIC_TOTINT] = { @@ -149,38 +147,6 @@ static inline void unmask_irq(unsigned int irq_nr) } } -#define pnx8550_disable pnx8550_ack -static void pnx8550_ack(unsigned int irq) -{ - unsigned long flags; - - spin_lock_irqsave(&irq_lock, flags); - mask_irq(irq); - spin_unlock_irqrestore(&irq_lock, flags); -} - -#define pnx8550_enable pnx8550_unmask -static void pnx8550_unmask(unsigned int irq) -{ - unsigned long flags; - - spin_lock_irqsave(&irq_lock, flags); - unmask_irq(irq); - spin_unlock_irqrestore(&irq_lock, flags); -} - -static unsigned int startup_irq(unsigned int irq_nr) -{ - pnx8550_unmask(irq_nr); - return 0; -} - -static void shutdown_irq(unsigned int irq_nr) -{ - pnx8550_ack(irq_nr); - return; -} - int pnx8550_set_gic_priority(int irq, int priority) { int gic_irq = irq-PNX8550_INT_GIC_MIN; @@ -192,26 +158,19 @@ int pnx8550_set_gic_priority(int irq, int priority) return prev_priority; } -static inline void mask_and_ack_level_irq(unsigned int irq) -{ - pnx8550_disable(irq); - return; -} - static void end_irq(unsigned int irq) { if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) { - pnx8550_enable(irq); + unmask_irq(irq); } } static struct irq_chip level_irq_type = { .typename = "PNX Level IRQ", - .startup = startup_irq, - .shutdown = shutdown_irq, - .enable = pnx8550_enable, - .disable = pnx8550_disable, - .ack = mask_and_ack_level_irq, + .ack = mask_irq, + .mask = mask_irq, + .mask_ack = mask_irq, + .unmask = unmask_irq, .end = end_irq, }; @@ -233,8 +192,8 @@ void __init arch_init_irq(void) int configPR; for (i = 0; i < PNX8550_INT_CP0_TOTINT; i++) { - irq_desc[i].chip = &level_irq_type; - pnx8550_ack(i); /* mask the irq just in case */ + set_irq_chip(i, &level_irq_type); + mask_irq(i); /* mask the irq just in case */ } /* init of GIC/IPC interrupts */ @@ -270,7 +229,7 @@ void __init arch_init_irq(void) /* mask/priority is still 0 so we will not get any * interrupts until it is unmasked */ - irq_desc[i].chip = &level_irq_type; + set_irq_chip(i, &level_irq_type); } /* Priority level 0 */ @@ -279,20 +238,19 @@ void __init arch_init_irq(void) /* Set int vector table address */ PNX8550_GIC_VECTOR_0 = PNX8550_GIC_VECTOR_1 = 0; - irq_desc[MIPS_CPU_GIC_IRQ].chip = &level_irq_type; + set_irq_chip(MIPS_CPU_GIC_IRQ, &level_irq_type); setup_irq(MIPS_CPU_GIC_IRQ, &gic_action); /* init of Timer interrupts */ - for (i = PNX8550_INT_TIMER_MIN; i <= PNX8550_INT_TIMER_MAX; i++) { - irq_desc[i].chip = &level_irq_type; - } + for (i = PNX8550_INT_TIMER_MIN; i <= PNX8550_INT_TIMER_MAX; i++) + set_irq_chip(i, &level_irq_type); /* Stop Timer 1-3 */ configPR = read_c0_config7(); configPR |= 0x00000038; write_c0_config7(configPR); - irq_desc[MIPS_CPU_TIMER_IRQ].chip = &level_irq_type; + set_irq_chip(MIPS_CPU_TIMER_IRQ, &level_irq_type); setup_irq(MIPS_CPU_TIMER_IRQ, &timer_action); } diff --git a/arch/mips/sgi-ip22/ip22-eisa.c b/arch/mips/sgi-ip22/ip22-eisa.c index 0d18ed4..a1a9af6 100644 --- a/arch/mips/sgi-ip22/ip22-eisa.c +++ b/arch/mips/sgi-ip22/ip22-eisa.c @@ -95,16 +95,11 @@ static irqreturn_t ip22_eisa_intr(int irq, void *dev_id) static void enable_eisa1_irq(unsigned int irq) { - unsigned long flags; u8 mask; - local_irq_save(flags); - mask = inb(EISA_INT1_MASK); mask &= ~((u8) (1 << irq)); outb(mask, EISA_INT1_MASK); - - local_irq_restore(flags); } static unsigned int startup_eisa1_irq(unsigned int irq) @@ -130,8 +125,6 @@ static void disable_eisa1_irq(unsigned int irq) outb(mask, EISA_INT1_MASK); } -#define shutdown_eisa1_irq disable_eisa1_irq - static void mask_and_ack_eisa1_irq(unsigned int irq) { disable_eisa1_irq(irq); @@ -148,25 +141,20 @@ static void end_eisa1_irq(unsigned int irq) static struct irq_chip ip22_eisa1_irq_type = { .typename = "IP22 EISA", .startup = startup_eisa1_irq, - .shutdown = shutdown_eisa1_irq, - .enable = enable_eisa1_irq, - .disable = disable_eisa1_irq, .ack = mask_and_ack_eisa1_irq, + .mask = disable_eisa1_irq, + .mask_ack = mask_and_ack_eisa1_irq, + .unmask = enable_eisa1_irq, .end = end_eisa1_irq, }; static void enable_eisa2_irq(unsigned int irq) { - unsigned long flags; u8 mask; - local_irq_save(flags); - mask = inb(EISA_INT2_MASK); mask &= ~((u8) (1 << (irq - 8))); outb(mask, EISA_INT2_MASK); - - local_irq_restore(flags); } static unsigned int startup_eisa2_irq(unsigned int irq) @@ -192,8 +180,6 @@ static void disable_eisa2_irq(unsigned int irq) outb(mask, EISA_INT2_MASK); } -#define shutdown_eisa2_irq disable_eisa2_irq - static void mask_and_ack_eisa2_irq(unsigned int irq) { disable_eisa2_irq(irq); @@ -210,10 +196,10 @@ static void end_eisa2_irq(unsigned int irq) static struct irq_chip ip22_eisa2_irq_type = { .typename = "IP22 EISA", .startup = startup_eisa2_irq, - .shutdown = shutdown_eisa2_irq, - .enable = enable_eisa2_irq, - .disable = disable_eisa2_irq, .ack = mask_and_ack_eisa2_irq, + .mask = disable_eisa2_irq, + .mask_ack = mask_and_ack_eisa2_irq, + .unmask = enable_eisa2_irq, .end = end_eisa2_irq, }; @@ -275,13 +261,10 @@ int __init ip22_eisa_init(void) outb(0, EISA_DMA2_WRITE_SINGLE); for (i = SGINT_EISA; i < (SGINT_EISA + EISA_MAX_IRQ); i++) { - irq_desc[i].status = IRQ_DISABLED; - irq_desc[i].action = 0; - irq_desc[i].depth = 1; if (i < (SGINT_EISA + 8)) - irq_desc[i].chip = &ip22_eisa1_irq_type; + set_irq_chip(i, &ip22_eisa1_irq_type); else - irq_desc[i].chip = &ip22_eisa2_irq_type; + set_irq_chip(i, &ip22_eisa2_irq_type); } /* Cannot use request_irq because of kmalloc not being ready at such diff --git a/arch/mips/sgi-ip22/ip22-int.c b/arch/mips/sgi-ip22/ip22-int.c index af51889..8e2074b 100644 --- a/arch/mips/sgi-ip22/ip22-int.c +++ b/arch/mips/sgi-ip22/ip22-int.c @@ -40,34 +40,17 @@ extern int ip22_eisa_init(void); static void enable_local0_irq(unsigned int irq) { - unsigned long flags; - - local_irq_save(flags); /* don't allow mappable interrupt to be enabled from setup_irq, * we have our own way to do so */ if (irq != SGI_MAP_0_IRQ) sgint->imask0 |= (1 << (irq - SGINT_LOCAL0)); - local_irq_restore(flags); -} - -static unsigned int startup_local0_irq(unsigned int irq) -{ - enable_local0_irq(irq); - return 0; /* Never anything pending */ } static void disable_local0_irq(unsigned int irq) { - unsigned long flags; - - local_irq_save(flags); sgint->imask0 &= ~(1 << (irq - SGINT_LOCAL0)); - local_irq_restore(flags); } -#define shutdown_local0_irq disable_local0_irq -#define mask_and_ack_local0_irq disable_local0_irq - static void end_local0_irq (unsigned int irq) { if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) @@ -76,44 +59,26 @@ static void end_local0_irq (unsigned int irq) static struct irq_chip ip22_local0_irq_type = { .typename = "IP22 local 0", - .startup = startup_local0_irq, - .shutdown = shutdown_local0_irq, - .enable = enable_local0_irq, - .disable = disable_local0_irq, - .ack = mask_and_ack_local0_irq, + .ack = disable_local0_irq, + .mask = disable_local0_irq, + .mask_ack = disable_local0_irq, + .unmask = enable_local0_irq, .end = end_local0_irq, }; static void enable_local1_irq(unsigned int irq) { - unsigned long flags; - - local_irq_save(flags); /* don't allow mappable interrupt to be enabled from setup_irq, * we have our own way to do so */ if (irq != SGI_MAP_1_IRQ) sgint->imask1 |= (1 << (irq - SGINT_LOCAL1)); - local_irq_restore(flags); -} - -static unsigned int startup_local1_irq(unsigned int irq) -{ - enable_local1_irq(irq); - return 0; /* Never anything pending */ } void disable_local1_irq(unsigned int irq) { - unsigned long flags; - - local_irq_save(flags); sgint->imask1 &= ~(1 << (irq - SGINT_LOCAL1)); - local_irq_restore(flags); } -#define shutdown_local1_irq disable_local1_irq -#define mask_and_ack_local1_irq disable_local1_irq - static void end_local1_irq (unsigned int irq) { if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) @@ -122,44 +87,26 @@ static void end_local1_irq (unsigned int irq) static struct irq_chip ip22_local1_irq_type = { .typename = "IP22 local 1", - .startup = startup_local1_irq, - .shutdown = shutdown_local1_irq, - .enable = enable_local1_irq, - .disable = disable_local1_irq, - .ack = mask_and_ack_local1_irq, + .ack = disable_local1_irq, + .mask = disable_local1_irq, + .mask_ack = disable_local1_irq, + .unmask = enable_local1_irq, .end = end_local1_irq, }; static void enable_local2_irq(unsigned int irq) { - unsigned long flags; - - local_irq_save(flags); sgint->imask0 |= (1 << (SGI_MAP_0_IRQ - SGINT_LOCAL0)); sgint->cmeimask0 |= (1 << (irq - SGINT_LOCAL2)); - local_irq_restore(flags); -} - -static unsigned int startup_local2_irq(unsigned int irq) -{ - enable_local2_irq(irq); - return 0; /* Never anything pending */ } void disable_local2_irq(unsigned int irq) { - unsigned long flags; - - local_irq_save(flags); sgint->cmeimask0 &= ~(1 << (irq - SGINT_LOCAL2)); if (!sgint->cmeimask0) sgint->imask0 &= ~(1 << (SGI_MAP_0_IRQ - SGINT_LOCAL0)); - local_irq_restore(flags); } -#define shutdown_local2_irq disable_local2_irq -#define mask_and_ack_local2_irq disable_local2_irq - static void end_local2_irq (unsigned int irq) { if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) @@ -168,44 +115,26 @@ static void end_local2_irq (unsigned int irq) static struct irq_chip ip22_local2_irq_type = { .typename = "IP22 local 2", - .startup = startup_local2_irq, - .shutdown = shutdown_local2_irq, - .enable = enable_local2_irq, - .disable = disable_local2_irq, - .ack = mask_and_ack_local2_irq, + .ack = disable_local2_irq, + .mask = disable_local2_irq, + .mask_ack = disable_local2_irq, + .unmask = enable_local2_irq, .end = end_local2_irq, }; static void enable_local3_irq(unsigned int irq) { - unsigned long flags; - - local_irq_save(flags); sgint->imask1 |= (1 << (SGI_MAP_1_IRQ - SGINT_LOCAL1)); sgint->cmeimask1 |= (1 << (irq - SGINT_LOCAL3)); - local_irq_restore(flags); -} - -static unsigned int startup_local3_irq(unsigned int irq) -{ - enable_local3_irq(irq); - return 0; /* Never anything pending */ } void disable_local3_irq(unsigned int irq) { - unsigned long flags; - - local_irq_save(flags); sgint->cmeimask1 &= ~(1 << (irq - SGINT_LOCAL3)); if (!sgint->cmeimask1) sgint->imask1 &= ~(1 << (SGI_MAP_1_IRQ - SGINT_LOCAL1)); - local_irq_restore(flags); } -#define shutdown_local3_irq disable_local3_irq -#define mask_and_ack_local3_irq disable_local3_irq - static void end_local3_irq (unsigned int irq) { if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) @@ -214,11 +143,10 @@ static void end_local3_irq (unsigned int irq) static struct irq_chip ip22_local3_irq_type = { .typename = "IP22 local 3", - .startup = startup_local3_irq, - .shutdown = shutdown_local3_irq, - .enable = enable_local3_irq, - .disable = disable_local3_irq, - .ack = mask_and_ack_local3_irq, + .ack = disable_local3_irq, + .mask = disable_local3_irq, + .mask_ack = disable_local3_irq, + .unmask = enable_local3_irq, .end = end_local3_irq, }; @@ -430,10 +358,7 @@ void __init arch_init_irq(void) else handler = &ip22_local3_irq_type; - irq_desc[i].status = IRQ_DISABLED; - irq_desc[i].action = 0; - irq_desc[i].depth = 1; - irq_desc[i].chip = handler; + set_irq_chip(i, handler); } /* vector handler. this register the IRQ as non-sharable */ diff --git a/arch/mips/sgi-ip27/ip27-irq.c b/arch/mips/sgi-ip27/ip27-irq.c index 270ecd3..8243202 100644 --- a/arch/mips/sgi-ip27/ip27-irq.c +++ b/arch/mips/sgi-ip27/ip27-irq.c @@ -332,11 +332,6 @@ static inline void disable_bridge_irq(unsigned int irq) intr_disconnect_level(cpu, swlevel); } -static void mask_and_ack_bridge_irq(unsigned int irq) -{ - disable_bridge_irq(irq); -} - static void end_bridge_irq(unsigned int irq) { if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)) && @@ -348,18 +343,16 @@ static struct irq_chip bridge_irq_type = { .typename = "bridge", .startup = startup_bridge_irq, .shutdown = shutdown_bridge_irq, - .enable = enable_bridge_irq, - .disable = disable_bridge_irq, - .ack = mask_and_ack_bridge_irq, + .ack = disable_bridge_irq, + .mask = disable_bridge_irq, + .mask_ack = disable_bridge_irq, + .unmask = enable_bridge_irq, .end = end_bridge_irq, }; void __devinit register_bridge_irq(unsigned int irq) { - irq_desc[irq].status = IRQ_DISABLED; - irq_desc[irq].action = 0; - irq_desc[irq].depth = 1; - irq_desc[irq].chip = &bridge_irq_type; + set_irq_chip(irq, &bridge_irq_type); } int __devinit request_bridge_irq(struct bridge_controller *bc) diff --git a/arch/mips/sgi-ip27/ip27-timer.c b/arch/mips/sgi-ip27/ip27-timer.c index 5e82a26..86ba7fc 100644 --- a/arch/mips/sgi-ip27/ip27-timer.c +++ b/arch/mips/sgi-ip27/ip27-timer.c @@ -172,15 +172,6 @@ static __init unsigned long get_m48t35_time(void) return mktime(year, month, date, hour, min, sec); } -static unsigned int startup_rt_irq(unsigned int irq) -{ - return 0; -} - -static void shutdown_rt_irq(unsigned int irq) -{ -} - static void enable_rt_irq(unsigned int irq) { } @@ -189,21 +180,16 @@ static void disable_rt_irq(unsigned int irq) { } -static void mask_and_ack_rt(unsigned int irq) -{ -} - static void end_rt_irq(unsigned int irq) { } static struct irq_chip rt_irq_type = { .typename = "SN HUB RT timer", - .startup = startup_rt_irq, - .shutdown = shutdown_rt_irq, - .enable = enable_rt_irq, - .disable = disable_rt_irq, - .ack = mask_and_ack_rt, + .ack = disable_rt_irq, + .mask = disable_rt_irq, + .mask_ack = disable_rt_irq, + .unmask = enable_rt_irq, .end = end_rt_irq, }; @@ -221,10 +207,7 @@ void __init plat_timer_setup(struct irqaction *irq) if (irqno < 0) panic("Can't allocate interrupt number for timer interrupt"); - irq_desc[irqno].status = IRQ_DISABLED; - irq_desc[irqno].action = NULL; - irq_desc[irqno].depth = 1; - irq_desc[irqno].chip = &rt_irq_type; + set_irq_chip(irqno, &rt_irq_type); /* over-write the handler, we use our own way */ irq->handler = no_action; diff --git a/arch/mips/sgi-ip32/ip32-irq.c b/arch/mips/sgi-ip32/ip32-irq.c index c9acadd..ae06386 100644 --- a/arch/mips/sgi-ip32/ip32-irq.c +++ b/arch/mips/sgi-ip32/ip32-irq.c @@ -113,12 +113,6 @@ static void inline flush_mace_bus(void) * is quite different anyway. */ -/* - * IRQ spinlock - Ralf says not to disable CPU interrupts, - * and I think he knows better. - */ -static DEFINE_SPINLOCK(ip32_irq_lock); - /* Some initial interrupts to set up */ extern irqreturn_t crime_memerr_intr(int irq, void *dev_id); extern irqreturn_t crime_cpuerr_intr(int irq, void *dev_id); @@ -138,12 +132,6 @@ static void enable_cpu_irq(unsigned int irq) set_c0_status(STATUSF_IP7); } -static unsigned int startup_cpu_irq(unsigned int irq) -{ - enable_cpu_irq(irq); - return 0; -} - static void disable_cpu_irq(unsigned int irq) { clear_c0_status(STATUSF_IP7); @@ -155,16 +143,12 @@ static void end_cpu_irq(unsigned int irq) enable_cpu_irq (irq); } -#define shutdown_cpu_irq disable_cpu_irq -#define mask_and_ack_cpu_irq disable_cpu_irq - static struct irq_chip ip32_cpu_interrupt = { .typename = "IP32 CPU", - .startup = startup_cpu_irq, - .shutdown = shutdown_cpu_irq, - .enable = enable_cpu_irq, - .disable = disable_cpu_irq, - .ack = mask_and_ack_cpu_irq, + .ack = disable_cpu_irq, + .mask = disable_cpu_irq, + .mask_ack = disable_cpu_irq, + .unmask = enable_cpu_irq, .end = end_cpu_irq, }; @@ -177,45 +161,27 @@ static uint64_t crime_mask; static void enable_crime_irq(unsigned int irq) { - unsigned long flags; - - spin_lock_irqsave(&ip32_irq_lock, flags); crime_mask |= 1 << (irq - 1); crime->imask = crime_mask; - spin_unlock_irqrestore(&ip32_irq_lock, flags); -} - -static unsigned int startup_crime_irq(unsigned int irq) -{ - enable_crime_irq(irq); - return 0; /* This is probably not right; we could have pending irqs */ } static void disable_crime_irq(unsigned int irq) { - unsigned long flags; - - spin_lock_irqsave(&ip32_irq_lock, flags); crime_mask &= ~(1 << (irq - 1)); crime->imask = crime_mask; flush_crime_bus(); - spin_unlock_irqrestore(&ip32_irq_lock, flags); } static void mask_and_ack_crime_irq(unsigned int irq) { - unsigned long flags; - /* Edge triggered interrupts must be cleared. */ if ((irq >= CRIME_GBE0_IRQ && irq <= CRIME_GBE3_IRQ) || (irq >= CRIME_RE_EMPTY_E_IRQ && irq <= CRIME_RE_IDLE_E_IRQ) || (irq >= CRIME_SOFT0_IRQ && irq <= CRIME_SOFT2_IRQ)) { uint64_t crime_int; - spin_lock_irqsave(&ip32_irq_lock, flags); crime_int = crime->hard_int; crime_int &= ~(1 << (irq - 1)); crime->hard_int = crime_int; - spin_unlock_irqrestore(&ip32_irq_lock, flags); } disable_crime_irq(irq); } @@ -226,15 +192,12 @@ static void end_crime_irq(unsigned int irq) enable_crime_irq(irq); } -#define shutdown_crime_irq disable_crime_irq - static struct irq_chip ip32_crime_interrupt = { .typename = "IP32 CRIME", - .startup = startup_crime_irq, - .shutdown = shutdown_crime_irq, - .enable = enable_crime_irq, - .disable = disable_crime_irq, .ack = mask_and_ack_crime_irq, + .mask = disable_crime_irq, + .mask_ack = mask_and_ack_crime_irq, + .unmask = enable_crime_irq, .end = end_crime_irq, }; @@ -248,34 +211,20 @@ static unsigned long macepci_mask; static void enable_macepci_irq(unsigned int irq) { - unsigned long flags; - - spin_lock_irqsave(&ip32_irq_lock, flags); macepci_mask |= MACEPCI_CONTROL_INT(irq - 9); mace->pci.control = macepci_mask; crime_mask |= 1 << (irq - 1); crime->imask = crime_mask; - spin_unlock_irqrestore(&ip32_irq_lock, flags); -} - -static unsigned int startup_macepci_irq(unsigned int irq) -{ - enable_macepci_irq (irq); - return 0; } static void disable_macepci_irq(unsigned int irq) { - unsigned long flags; - - spin_lock_irqsave(&ip32_irq_lock, flags); crime_mask &= ~(1 << (irq - 1)); crime->imask = crime_mask; flush_crime_bus(); macepci_mask &= ~MACEPCI_CONTROL_INT(irq - 9); mace->pci.control = macepci_mask; flush_mace_bus(); - spin_unlock_irqrestore(&ip32_irq_lock, flags); } static void end_macepci_irq(unsigned int irq) @@ -284,16 +233,12 @@ static void end_macepci_irq(unsigned int irq) enable_macepci_irq(irq); } -#define shutdown_macepci_irq disable_macepci_irq -#define mask_and_ack_macepci_irq disable_macepci_irq - static struct irq_chip ip32_macepci_interrupt = { .typename = "IP32 MACE PCI", - .startup = startup_macepci_irq, - .shutdown = shutdown_macepci_irq, - .enable = enable_macepci_irq, - .disable = disable_macepci_irq, - .ack = mask_and_ack_macepci_irq, + .ack = disable_macepci_irq, + .mask = disable_macepci_irq, + .mask_ack = disable_macepci_irq, + .unmask = enable_macepci_irq, .end = end_macepci_irq, }; @@ -339,7 +284,6 @@ static unsigned long maceisa_mask; static void enable_maceisa_irq (unsigned int irq) { unsigned int crime_int = 0; - unsigned long flags; DBG ("maceisa enable: %u\n", irq); @@ -355,26 +299,16 @@ static void enable_maceisa_irq (unsigned int irq) break; } DBG ("crime_int %08x enabled\n", crime_int); - spin_lock_irqsave(&ip32_irq_lock, flags); crime_mask |= crime_int; crime->imask = crime_mask; maceisa_mask |= 1 << (irq - 33); mace->perif.ctrl.imask = maceisa_mask; - spin_unlock_irqrestore(&ip32_irq_lock, flags); -} - -static unsigned int startup_maceisa_irq(unsigned int irq) -{ - enable_maceisa_irq(irq); - return 0; } static void disable_maceisa_irq(unsigned int irq) { unsigned int crime_int = 0; - unsigned long flags; - spin_lock_irqsave(&ip32_irq_lock, flags); maceisa_mask &= ~(1 << (irq - 33)); if(!(maceisa_mask & MACEISA_AUDIO_INT)) crime_int |= MACE_AUDIO_INT; @@ -387,23 +321,20 @@ static void disable_maceisa_irq(unsigned int irq) flush_crime_bus(); mace->perif.ctrl.imask = maceisa_mask; flush_mace_bus(); - spin_unlock_irqrestore(&ip32_irq_lock, flags); } static void mask_and_ack_maceisa_irq(unsigned int irq) { - unsigned long mace_int, flags; + unsigned long mace_int; switch (irq) { case MACEISA_PARALLEL_IRQ: case MACEISA_SERIAL1_TDMAPR_IRQ: case MACEISA_SERIAL2_TDMAPR_IRQ: /* edge triggered */ - spin_lock_irqsave(&ip32_irq_lock, flags); mace_int = mace->perif.ctrl.istat; mace_int &= ~(1 << (irq - 33)); mace->perif.ctrl.istat = mace_int; - spin_unlock_irqrestore(&ip32_irq_lock, flags); break; } disable_maceisa_irq(irq); @@ -415,15 +346,12 @@ static void end_maceisa_irq(unsigned irq) enable_maceisa_irq(irq); } -#define shutdown_maceisa_irq disable_maceisa_irq - static struct irq_chip ip32_maceisa_interrupt = { .typename = "IP32 MACE ISA", - .startup = startup_maceisa_irq, - .shutdown = shutdown_maceisa_irq, - .enable = enable_maceisa_irq, - .disable = disable_maceisa_irq, .ack = mask_and_ack_maceisa_irq, + .mask = disable_maceisa_irq, + .mask_ack = mask_and_ack_maceisa_irq, + .unmask = enable_maceisa_irq, .end = end_maceisa_irq, }; @@ -433,29 +361,15 @@ static struct irq_chip ip32_maceisa_interrupt = { static void enable_mace_irq(unsigned int irq) { - unsigned long flags; - - spin_lock_irqsave(&ip32_irq_lock, flags); crime_mask |= 1 << (irq - 1); crime->imask = crime_mask; - spin_unlock_irqrestore(&ip32_irq_lock, flags); -} - -static unsigned int startup_mace_irq(unsigned int irq) -{ - enable_mace_irq(irq); - return 0; } static void disable_mace_irq(unsigned int irq) { - unsigned long flags; - - spin_lock_irqsave(&ip32_irq_lock, flags); crime_mask &= ~(1 << (irq - 1)); crime->imask = crime_mask; flush_crime_bus(); - spin_unlock_irqrestore(&ip32_irq_lock, flags); } static void end_mace_irq(unsigned int irq) @@ -464,16 +378,12 @@ static void end_mace_irq(unsigned int irq) enable_mace_irq(irq); } -#define shutdown_mace_irq disable_mace_irq -#define mask_and_ack_mace_irq disable_mace_irq - static struct irq_chip ip32_mace_interrupt = { .typename = "IP32 MACE", - .startup = startup_mace_irq, - .shutdown = shutdown_mace_irq, - .enable = enable_mace_irq, - .disable = disable_mace_irq, - .ack = mask_and_ack_mace_irq, + .ack = disable_mace_irq, + .mask = disable_mace_irq, + .mask_ack = disable_mace_irq, + .unmask = enable_mace_irq, .end = end_mace_irq, }; @@ -586,10 +496,7 @@ void __init arch_init_irq(void) else controller = &ip32_maceisa_interrupt; - irq_desc[irq].status = IRQ_DISABLED; - irq_desc[irq].action = 0; - irq_desc[irq].depth = 0; - irq_desc[irq].chip = controller; + set_irq_chip(irq, controller); } setup_irq(CRIME_MEMERR_IRQ, &memerr_irq); setup_irq(CRIME_CPUERR_IRQ, &cpuerr_irq); diff --git a/arch/mips/sibyte/bcm1480/irq.c b/arch/mips/sibyte/bcm1480/irq.c index 8b1f414..2e8f6b2 100644 --- a/arch/mips/sibyte/bcm1480/irq.c +++ b/arch/mips/sibyte/bcm1480/irq.c @@ -45,11 +45,9 @@ */ -#define shutdown_bcm1480_irq disable_bcm1480_irq static void end_bcm1480_irq(unsigned int irq); static void enable_bcm1480_irq(unsigned int irq); static void disable_bcm1480_irq(unsigned int irq); -static unsigned int startup_bcm1480_irq(unsigned int irq); static void ack_bcm1480_irq(unsigned int irq); #ifdef CONFIG_SMP static void bcm1480_set_affinity(unsigned int irq, cpumask_t mask); @@ -85,11 +83,10 @@ extern char sb1250_duart_present[]; static struct irq_chip bcm1480_irq_type = { .typename = "BCM1480-IMR", - .startup = startup_bcm1480_irq, - .shutdown = shutdown_bcm1480_irq, - .enable = enable_bcm1480_irq, - .disable = disable_bcm1480_irq, .ack = ack_bcm1480_irq, + .mask = disable_bcm1480_irq, + .mask_ack = ack_bcm1480_irq, + .unmask = enable_bcm1480_irq, .end = end_bcm1480_irq, #ifdef CONFIG_SMP .set_affinity = bcm1480_set_affinity @@ -188,14 +185,6 @@ static void bcm1480_set_affinity(unsigned int irq, cpumask_t mask) /*****************************************************************************/ -static unsigned int startup_bcm1480_irq(unsigned int irq) -{ - bcm1480_unmask_irq(bcm1480_irq_owner[irq], irq); - - return 0; /* never anything pending */ -} - - static void disable_bcm1480_irq(unsigned int irq) { bcm1480_mask_irq(bcm1480_irq_owner[irq], irq); @@ -270,16 +259,9 @@ void __init init_bcm1480_irqs(void) { int i; - for (i = 0; i < NR_IRQS; i++) { - irq_desc[i].status = IRQ_DISABLED; - irq_desc[i].action = 0; - irq_desc[i].depth = 1; - if (i < BCM1480_NR_IRQS) { - irq_desc[i].chip = &bcm1480_irq_type; - bcm1480_irq_owner[i] = 0; - } else { - irq_desc[i].chip = &no_irq_chip; - } + for (i = 0; i < BCM1480_NR_IRQS; i++) { + set_irq_chip(i, &bcm1480_irq_type); + bcm1480_irq_owner[i] = 0; } } diff --git a/arch/mips/sibyte/sb1250/irq.c b/arch/mips/sibyte/sb1250/irq.c index d5d2677..82ce753 100644 --- a/arch/mips/sibyte/sb1250/irq.c +++ b/arch/mips/sibyte/sb1250/irq.c @@ -44,11 +44,9 @@ */ -#define shutdown_sb1250_irq disable_sb1250_irq static void end_sb1250_irq(unsigned int irq); static void enable_sb1250_irq(unsigned int irq); static void disable_sb1250_irq(unsigned int irq); -static unsigned int startup_sb1250_irq(unsigned int irq); static void ack_sb1250_irq(unsigned int irq); #ifdef CONFIG_SMP static void sb1250_set_affinity(unsigned int irq, cpumask_t mask); @@ -70,11 +68,10 @@ extern char sb1250_duart_present[]; static struct irq_chip sb1250_irq_type = { .typename = "SB1250-IMR", - .startup = startup_sb1250_irq, - .shutdown = shutdown_sb1250_irq, - .enable = enable_sb1250_irq, - .disable = disable_sb1250_irq, .ack = ack_sb1250_irq, + .mask = disable_sb1250_irq, + .mask_ack = ack_sb1250_irq, + .unmask = enable_sb1250_irq, .end = end_sb1250_irq, #ifdef CONFIG_SMP .set_affinity = sb1250_set_affinity @@ -163,14 +160,6 @@ static void sb1250_set_affinity(unsigned int irq, cpumask_t mask) /*****************************************************************************/ -static unsigned int startup_sb1250_irq(unsigned int irq) -{ - sb1250_unmask_irq(sb1250_irq_owner[irq], irq); - - return 0; /* never anything pending */ -} - - static void disable_sb1250_irq(unsigned int irq) { sb1250_mask_irq(sb1250_irq_owner[irq], irq); @@ -239,16 +228,9 @@ void __init init_sb1250_irqs(void) { int i; - for (i = 0; i < NR_IRQS; i++) { - irq_desc[i].status = IRQ_DISABLED; - irq_desc[i].action = 0; - irq_desc[i].depth = 1; - if (i < SB1250_NR_IRQS) { - irq_desc[i].chip = &sb1250_irq_type; - sb1250_irq_owner[i] = 0; - } else { - irq_desc[i].chip = &no_irq_chip; - } + for (i = 0; i < SB1250_NR_IRQS; i++) { + set_irq_chip(i, &sb1250_irq_type); + sb1250_irq_owner[i] = 0; } } diff --git a/arch/mips/sni/irq.c b/arch/mips/sni/irq.c index 48fb74a..8511bcc 100644 --- a/arch/mips/sni/irq.c +++ b/arch/mips/sni/irq.c @@ -11,44 +11,25 @@ #include #include #include -#include #include #include #include -DEFINE_SPINLOCK(pciasic_lock); - static void enable_pciasic_irq(unsigned int irq) { unsigned int mask = 1 << (irq - PCIMT_IRQ_INT2); - unsigned long flags; - spin_lock_irqsave(&pciasic_lock, flags); *(volatile u8 *) PCIMT_IRQSEL |= mask; - spin_unlock_irqrestore(&pciasic_lock, flags); -} - -static unsigned int startup_pciasic_irq(unsigned int irq) -{ - enable_pciasic_irq(irq); - return 0; /* never anything pending */ } -#define shutdown_pciasic_irq disable_pciasic_irq - void disable_pciasic_irq(unsigned int irq) { unsigned int mask = ~(1 << (irq - PCIMT_IRQ_INT2)); - unsigned long flags; - spin_lock_irqsave(&pciasic_lock, flags); *(volatile u8 *) PCIMT_IRQSEL &= mask; - spin_unlock_irqrestore(&pciasic_lock, flags); } -#define mask_and_ack_pciasic_irq disable_pciasic_irq - static void end_pciasic_irq(unsigned int irq) { if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) @@ -57,11 +38,10 @@ static void end_pciasic_irq(unsigned int irq) static struct irq_chip pciasic_irq_type = { .typename = "ASIC-PCI", - .startup = startup_pciasic_irq, - .shutdown = shutdown_pciasic_irq, - .enable = enable_pciasic_irq, - .disable = disable_pciasic_irq, - .ack = mask_and_ack_pciasic_irq, + .ack = disable_pciasic_irq, + .mask = disable_pciasic_irq, + .mask_ack = disable_pciasic_irq, + .unmask = enable_pciasic_irq, .end = end_pciasic_irq, }; @@ -178,12 +158,8 @@ asmlinkage void plat_irq_dispatch(void) void __init init_pciasic(void) { - unsigned long flags; - - spin_lock_irqsave(&pciasic_lock, flags); * (volatile u8 *) PCIMT_IRQSEL = IT_EISA | IT_INTA | IT_INTB | IT_INTC | IT_INTD; - spin_unlock_irqrestore(&pciasic_lock, flags); } /* @@ -199,12 +175,8 @@ void __init arch_init_irq(void) init_pciasic(); /* Actually we've got more interrupts to handle ... */ - for (i = PCIMT_IRQ_INT2; i <= PCIMT_IRQ_ETHERNET; i++) { - irq_desc[i].status = IRQ_DISABLED; - irq_desc[i].action = 0; - irq_desc[i].depth = 1; - irq_desc[i].chip = &pciasic_irq_type; - } + for (i = PCIMT_IRQ_INT2; i <= PCIMT_IRQ_ETHERNET; i++) + set_irq_chip(i, &pciasic_irq_type); change_c0_status(ST0_IM, IE_IRQ1|IE_IRQ2|IE_IRQ3|IE_IRQ4); } diff --git a/arch/mips/tx4927/common/tx4927_irq.c b/arch/mips/tx4927/common/tx4927_irq.c index 8266a88..2c57ced 100644 --- a/arch/mips/tx4927/common/tx4927_irq.c +++ b/arch/mips/tx4927/common/tx4927_irq.c @@ -64,19 +64,13 @@ #define TX4927_IRQ_NEST4 ( 1 << 9 ) #define TX4927_IRQ_CP0_INIT ( 1 << 10 ) -#define TX4927_IRQ_CP0_STARTUP ( 1 << 11 ) -#define TX4927_IRQ_CP0_SHUTDOWN ( 1 << 12 ) #define TX4927_IRQ_CP0_ENABLE ( 1 << 13 ) #define TX4927_IRQ_CP0_DISABLE ( 1 << 14 ) -#define TX4927_IRQ_CP0_MASK ( 1 << 15 ) #define TX4927_IRQ_CP0_ENDIRQ ( 1 << 16 ) #define TX4927_IRQ_PIC_INIT ( 1 << 20 ) -#define TX4927_IRQ_PIC_STARTUP ( 1 << 21 ) -#define TX4927_IRQ_PIC_SHUTDOWN ( 1 << 22 ) #define TX4927_IRQ_PIC_ENABLE ( 1 << 23 ) #define TX4927_IRQ_PIC_DISABLE ( 1 << 24 ) -#define TX4927_IRQ_PIC_MASK ( 1 << 25 ) #define TX4927_IRQ_PIC_ENDIRQ ( 1 << 26 ) #define TX4927_IRQ_ALL 0xffffffff @@ -87,18 +81,12 @@ static const u32 tx4927_irq_debug_flag = (TX4927_IRQ_NONE | TX4927_IRQ_INFO | TX4927_IRQ_WARN | TX4927_IRQ_EROR // | TX4927_IRQ_CP0_INIT -// | TX4927_IRQ_CP0_STARTUP -// | TX4927_IRQ_CP0_SHUTDOWN // | TX4927_IRQ_CP0_ENABLE // | TX4927_IRQ_CP0_DISABLE -// | TX4927_IRQ_CP0_MASK // | TX4927_IRQ_CP0_ENDIRQ // | TX4927_IRQ_PIC_INIT -// | TX4927_IRQ_PIC_STARTUP -// | TX4927_IRQ_PIC_SHUTDOWN // | TX4927_IRQ_PIC_ENABLE // | TX4927_IRQ_PIC_DISABLE -// | TX4927_IRQ_PIC_MASK // | TX4927_IRQ_PIC_ENDIRQ // | TX4927_IRQ_INIT // | TX4927_IRQ_NEST1 @@ -124,49 +112,36 @@ static const u32 tx4927_irq_debug_flag = (TX4927_IRQ_NONE * Forwad definitions for all pic's */ -static unsigned int tx4927_irq_cp0_startup(unsigned int irq); -static void tx4927_irq_cp0_shutdown(unsigned int irq); static void tx4927_irq_cp0_enable(unsigned int irq); static void tx4927_irq_cp0_disable(unsigned int irq); -static void tx4927_irq_cp0_mask_and_ack(unsigned int irq); static void tx4927_irq_cp0_end(unsigned int irq); -static unsigned int tx4927_irq_pic_startup(unsigned int irq); -static void tx4927_irq_pic_shutdown(unsigned int irq); static void tx4927_irq_pic_enable(unsigned int irq); static void tx4927_irq_pic_disable(unsigned int irq); -static void tx4927_irq_pic_mask_and_ack(unsigned int irq); static void tx4927_irq_pic_end(unsigned int irq); /* * Kernel structs for all pic's */ -static DEFINE_SPINLOCK(tx4927_cp0_lock); -static DEFINE_SPINLOCK(tx4927_pic_lock); - #define TX4927_CP0_NAME "TX4927-CP0" static struct irq_chip tx4927_irq_cp0_type = { .typename = TX4927_CP0_NAME, - .startup = tx4927_irq_cp0_startup, - .shutdown = tx4927_irq_cp0_shutdown, - .enable = tx4927_irq_cp0_enable, - .disable = tx4927_irq_cp0_disable, - .ack = tx4927_irq_cp0_mask_and_ack, + .ack = tx4927_irq_cp0_disable, + .mask = tx4927_irq_cp0_disable, + .mask_ack = tx4927_irq_cp0_disable, + .unmask = tx4927_irq_cp0_enable, .end = tx4927_irq_cp0_end, - .set_affinity = NULL }; #define TX4927_PIC_NAME "TX4927-PIC" static struct irq_chip tx4927_irq_pic_type = { .typename = TX4927_PIC_NAME, - .startup = tx4927_irq_pic_startup, - .shutdown = tx4927_irq_pic_shutdown, - .enable = tx4927_irq_pic_enable, - .disable = tx4927_irq_pic_disable, - .ack = tx4927_irq_pic_mask_and_ack, + .ack = tx4927_irq_pic_disable, + .mask = tx4927_irq_pic_disable, + .mask_ack = tx4927_irq_pic_disable, + .unmask = tx4927_irq_pic_enable, .end = tx4927_irq_pic_end, - .set_affinity = NULL }; #define TX4927_PIC_ACTION(s) { no_action, 0, CPU_MASK_NONE, s, NULL, NULL } @@ -211,8 +186,6 @@ tx4927_irq_cp0_modify(unsigned cp0_reg, unsigned clr_bits, unsigned set_bits) break; } } - - return; } static void __init tx4927_irq_cp0_init(void) @@ -222,71 +195,22 @@ static void __init tx4927_irq_cp0_init(void) TX4927_IRQ_DPRINTK(TX4927_IRQ_CP0_INIT, "beg=%d end=%d\n", TX4927_IRQ_CP0_BEG, TX4927_IRQ_CP0_END); - for (i = TX4927_IRQ_CP0_BEG; i <= TX4927_IRQ_CP0_END; i++) { - irq_desc[i].status = IRQ_DISABLED; - irq_desc[i].action = 0; - irq_desc[i].depth = 1; - irq_desc[i].chip = &tx4927_irq_cp0_type; - } - - return; -} - -static unsigned int tx4927_irq_cp0_startup(unsigned int irq) -{ - TX4927_IRQ_DPRINTK(TX4927_IRQ_CP0_STARTUP, "irq=%d \n", irq); - - tx4927_irq_cp0_enable(irq); - - return (0); -} - -static void tx4927_irq_cp0_shutdown(unsigned int irq) -{ - TX4927_IRQ_DPRINTK(TX4927_IRQ_CP0_SHUTDOWN, "irq=%d \n", irq); - - tx4927_irq_cp0_disable(irq); - - return; + for (i = TX4927_IRQ_CP0_BEG; i <= TX4927_IRQ_CP0_END; i++) + set_irq_chip(i, &tx4927_irq_cp0_type); } static void tx4927_irq_cp0_enable(unsigned int irq) { - unsigned long flags; - TX4927_IRQ_DPRINTK(TX4927_IRQ_CP0_ENABLE, "irq=%d \n", irq); - spin_lock_irqsave(&tx4927_cp0_lock, flags); - tx4927_irq_cp0_modify(CCP0_STATUS, 0, tx4927_irq_cp0_mask(irq)); - - spin_unlock_irqrestore(&tx4927_cp0_lock, flags); - - return; } static void tx4927_irq_cp0_disable(unsigned int irq) { - unsigned long flags; - TX4927_IRQ_DPRINTK(TX4927_IRQ_CP0_DISABLE, "irq=%d \n", irq); - spin_lock_irqsave(&tx4927_cp0_lock, flags); - tx4927_irq_cp0_modify(CCP0_STATUS, tx4927_irq_cp0_mask(irq), 0); - - spin_unlock_irqrestore(&tx4927_cp0_lock, flags); - - return; -} - -static void tx4927_irq_cp0_mask_and_ack(unsigned int irq) -{ - TX4927_IRQ_DPRINTK(TX4927_IRQ_CP0_MASK, "irq=%d \n", irq); - - tx4927_irq_cp0_disable(irq); - - return; } static void tx4927_irq_cp0_end(unsigned int irq) @@ -296,8 +220,6 @@ static void tx4927_irq_cp0_end(unsigned int irq) if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) { tx4927_irq_cp0_enable(irq); } - - return; } /* @@ -418,94 +340,38 @@ static void tx4927_irq_pic_modify(unsigned pic_reg, unsigned clr_bits, val &= (~clr_bits); val |= (set_bits); TX4927_WR(pic_reg, val); - - return; } static void __init tx4927_irq_pic_init(void) { - unsigned long flags; int i; TX4927_IRQ_DPRINTK(TX4927_IRQ_PIC_INIT, "beg=%d end=%d\n", TX4927_IRQ_PIC_BEG, TX4927_IRQ_PIC_END); - for (i = TX4927_IRQ_PIC_BEG; i <= TX4927_IRQ_PIC_END; i++) { - irq_desc[i].status = IRQ_DISABLED; - irq_desc[i].action = 0; - irq_desc[i].depth = 2; - irq_desc[i].chip = &tx4927_irq_pic_type; - } + for (i = TX4927_IRQ_PIC_BEG; i <= TX4927_IRQ_PIC_END; i++) + set_irq_chip(i, &tx4927_irq_pic_type); setup_irq(TX4927_IRQ_NEST_PIC_ON_CP0, &tx4927_irq_pic_action); - spin_lock_irqsave(&tx4927_pic_lock, flags); - TX4927_WR(0xff1ff640, 0x6); /* irq level mask -- only accept hightest */ TX4927_WR(0xff1ff600, TX4927_RD(0xff1ff600) | 0x1); /* irq enable */ - - spin_unlock_irqrestore(&tx4927_pic_lock, flags); - - return; -} - -static unsigned int tx4927_irq_pic_startup(unsigned int irq) -{ - TX4927_IRQ_DPRINTK(TX4927_IRQ_PIC_STARTUP, "irq=%d\n", irq); - - tx4927_irq_pic_enable(irq); - - return (0); -} - -static void tx4927_irq_pic_shutdown(unsigned int irq) -{ - TX4927_IRQ_DPRINTK(TX4927_IRQ_PIC_SHUTDOWN, "irq=%d\n", irq); - - tx4927_irq_pic_disable(irq); - - return; } static void tx4927_irq_pic_enable(unsigned int irq) { - unsigned long flags; - TX4927_IRQ_DPRINTK(TX4927_IRQ_PIC_ENABLE, "irq=%d\n", irq); - spin_lock_irqsave(&tx4927_pic_lock, flags); - tx4927_irq_pic_modify(tx4927_irq_pic_addr(irq), 0, tx4927_irq_pic_mask(irq)); - - spin_unlock_irqrestore(&tx4927_pic_lock, flags); - - return; } static void tx4927_irq_pic_disable(unsigned int irq) { - unsigned long flags; - TX4927_IRQ_DPRINTK(TX4927_IRQ_PIC_DISABLE, "irq=%d\n", irq); - spin_lock_irqsave(&tx4927_pic_lock, flags); - tx4927_irq_pic_modify(tx4927_irq_pic_addr(irq), tx4927_irq_pic_mask(irq), 0); - - spin_unlock_irqrestore(&tx4927_pic_lock, flags); - - return; -} - -static void tx4927_irq_pic_mask_and_ack(unsigned int irq) -{ - TX4927_IRQ_DPRINTK(TX4927_IRQ_PIC_MASK, "irq=%d\n", irq); - - tx4927_irq_pic_disable(irq); - - return; } static void tx4927_irq_pic_end(unsigned int irq) @@ -515,8 +381,6 @@ static void tx4927_irq_pic_end(unsigned int irq) if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) { tx4927_irq_pic_enable(irq); } - - return; } /* @@ -533,8 +397,6 @@ void __init tx4927_irq_init(void) tx4927_irq_pic_init(); TX4927_IRQ_DPRINTK(TX4927_IRQ_INIT, "+\n"); - - return; } static int tx4927_irq_nested(void) diff --git a/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c b/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c index 0c3c3f6..1fdace8 100644 --- a/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c +++ b/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c @@ -151,16 +151,11 @@ JP7 is not bus master -- do NOT use -- only 4 pci bus master's allowed -- SouthB #define TOSHIBA_RBTX4927_IRQ_EROR ( 1 << 2 ) #define TOSHIBA_RBTX4927_IRQ_IOC_INIT ( 1 << 10 ) -#define TOSHIBA_RBTX4927_IRQ_IOC_STARTUP ( 1 << 11 ) -#define TOSHIBA_RBTX4927_IRQ_IOC_SHUTDOWN ( 1 << 12 ) #define TOSHIBA_RBTX4927_IRQ_IOC_ENABLE ( 1 << 13 ) #define TOSHIBA_RBTX4927_IRQ_IOC_DISABLE ( 1 << 14 ) -#define TOSHIBA_RBTX4927_IRQ_IOC_MASK ( 1 << 15 ) #define TOSHIBA_RBTX4927_IRQ_IOC_ENDIRQ ( 1 << 16 ) #define TOSHIBA_RBTX4927_IRQ_ISA_INIT ( 1 << 20 ) -#define TOSHIBA_RBTX4927_IRQ_ISA_STARTUP ( 1 << 21 ) -#define TOSHIBA_RBTX4927_IRQ_ISA_SHUTDOWN ( 1 << 22 ) #define TOSHIBA_RBTX4927_IRQ_ISA_ENABLE ( 1 << 23 ) #define TOSHIBA_RBTX4927_IRQ_ISA_DISABLE ( 1 << 24 ) #define TOSHIBA_RBTX4927_IRQ_ISA_MASK ( 1 << 25 ) @@ -175,15 +170,10 @@ static const u32 toshiba_rbtx4927_irq_debug_flag = (TOSHIBA_RBTX4927_IRQ_NONE | TOSHIBA_RBTX4927_IRQ_INFO | TOSHIBA_RBTX4927_IRQ_WARN | TOSHIBA_RBTX4927_IRQ_EROR // | TOSHIBA_RBTX4927_IRQ_IOC_INIT -// | TOSHIBA_RBTX4927_IRQ_IOC_STARTUP -// | TOSHIBA_RBTX4927_IRQ_IOC_SHUTDOWN // | TOSHIBA_RBTX4927_IRQ_IOC_ENABLE // | TOSHIBA_RBTX4927_IRQ_IOC_DISABLE -// | TOSHIBA_RBTX4927_IRQ_IOC_MASK // | TOSHIBA_RBTX4927_IRQ_IOC_ENDIRQ // | TOSHIBA_RBTX4927_IRQ_ISA_INIT -// | TOSHIBA_RBTX4927_IRQ_ISA_STARTUP -// | TOSHIBA_RBTX4927_IRQ_ISA_SHUTDOWN // | TOSHIBA_RBTX4927_IRQ_ISA_ENABLE // | TOSHIBA_RBTX4927_IRQ_ISA_DISABLE // | TOSHIBA_RBTX4927_IRQ_ISA_MASK @@ -231,35 +221,25 @@ extern void disable_8259A_irq(unsigned int irq); extern void mask_and_ack_8259A(unsigned int irq); #endif -static unsigned int toshiba_rbtx4927_irq_ioc_startup(unsigned int irq); -static void toshiba_rbtx4927_irq_ioc_shutdown(unsigned int irq); static void toshiba_rbtx4927_irq_ioc_enable(unsigned int irq); static void toshiba_rbtx4927_irq_ioc_disable(unsigned int irq); -static void toshiba_rbtx4927_irq_ioc_mask_and_ack(unsigned int irq); static void toshiba_rbtx4927_irq_ioc_end(unsigned int irq); #ifdef CONFIG_TOSHIBA_FPCIB0 -static unsigned int toshiba_rbtx4927_irq_isa_startup(unsigned int irq); -static void toshiba_rbtx4927_irq_isa_shutdown(unsigned int irq); static void toshiba_rbtx4927_irq_isa_enable(unsigned int irq); static void toshiba_rbtx4927_irq_isa_disable(unsigned int irq); static void toshiba_rbtx4927_irq_isa_mask_and_ack(unsigned int irq); static void toshiba_rbtx4927_irq_isa_end(unsigned int irq); #endif -static DEFINE_SPINLOCK(toshiba_rbtx4927_ioc_lock); - - #define TOSHIBA_RBTX4927_IOC_NAME "RBTX4927-IOC" static struct irq_chip toshiba_rbtx4927_irq_ioc_type = { .typename = TOSHIBA_RBTX4927_IOC_NAME, - .startup = toshiba_rbtx4927_irq_ioc_startup, - .shutdown = toshiba_rbtx4927_irq_ioc_shutdown, - .enable = toshiba_rbtx4927_irq_ioc_enable, - .disable = toshiba_rbtx4927_irq_ioc_disable, - .ack = toshiba_rbtx4927_irq_ioc_mask_and_ack, + .ack = toshiba_rbtx4927_irq_ioc_disable, + .mask = toshiba_rbtx4927_irq_ioc_disable, + .mask_ack = toshiba_rbtx4927_irq_ioc_disable, + .unmask = toshiba_rbtx4927_irq_ioc_enable, .end = toshiba_rbtx4927_irq_ioc_end, - .set_affinity = NULL }; #define TOSHIBA_RBTX4927_IOC_INTR_ENAB 0xbc002000 #define TOSHIBA_RBTX4927_IOC_INTR_STAT 0xbc002006 @@ -269,13 +249,11 @@ static struct irq_chip toshiba_rbtx4927_irq_ioc_type = { #define TOSHIBA_RBTX4927_ISA_NAME "RBTX4927-ISA" static struct irq_chip toshiba_rbtx4927_irq_isa_type = { .typename = TOSHIBA_RBTX4927_ISA_NAME, - .startup = toshiba_rbtx4927_irq_isa_startup, - .shutdown = toshiba_rbtx4927_irq_isa_shutdown, - .enable = toshiba_rbtx4927_irq_isa_enable, - .disable = toshiba_rbtx4927_irq_isa_disable, .ack = toshiba_rbtx4927_irq_isa_mask_and_ack, + .mask = toshiba_rbtx4927_irq_isa_disable, + .mask_ack = toshiba_rbtx4927_irq_isa_mask_and_ack, + .unmask = toshiba_rbtx4927_irq_isa_enable, .end = toshiba_rbtx4927_irq_isa_end, - .set_affinity = NULL }; #endif @@ -363,58 +341,15 @@ static void __init toshiba_rbtx4927_irq_ioc_init(void) TOSHIBA_RBTX4927_IRQ_IOC_END); for (i = TOSHIBA_RBTX4927_IRQ_IOC_BEG; - i <= TOSHIBA_RBTX4927_IRQ_IOC_END; i++) { - irq_desc[i].status = IRQ_DISABLED; - irq_desc[i].action = 0; - irq_desc[i].depth = 3; - irq_desc[i].chip = &toshiba_rbtx4927_irq_ioc_type; - } + i <= TOSHIBA_RBTX4927_IRQ_IOC_END; i++) + set_irq_chip(i, &toshiba_rbtx4927_irq_ioc_type); setup_irq(TOSHIBA_RBTX4927_IRQ_NEST_IOC_ON_PIC, &toshiba_rbtx4927_irq_ioc_action); - - return; } -static unsigned int toshiba_rbtx4927_irq_ioc_startup(unsigned int irq) -{ - TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_IOC_STARTUP, - "irq=%d\n", irq); - - if (irq < TOSHIBA_RBTX4927_IRQ_IOC_BEG - || irq > TOSHIBA_RBTX4927_IRQ_IOC_END) { - TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_EROR, - "bad irq=%d\n", irq); - panic("\n"); - } - - toshiba_rbtx4927_irq_ioc_enable(irq); - - return (0); -} - - -static void toshiba_rbtx4927_irq_ioc_shutdown(unsigned int irq) -{ - TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_IOC_SHUTDOWN, - "irq=%d\n", irq); - - if (irq < TOSHIBA_RBTX4927_IRQ_IOC_BEG - || irq > TOSHIBA_RBTX4927_IRQ_IOC_END) { - TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_EROR, - "bad irq=%d\n", irq); - panic("\n"); - } - - toshiba_rbtx4927_irq_ioc_disable(irq); - - return; -} - - static void toshiba_rbtx4927_irq_ioc_enable(unsigned int irq) { - unsigned long flags; volatile unsigned char v; TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_IOC_ENABLE, @@ -427,21 +362,14 @@ static void toshiba_rbtx4927_irq_ioc_enable(unsigned int irq) panic("\n"); } - spin_lock_irqsave(&toshiba_rbtx4927_ioc_lock, flags); - v = TX4927_RD08(TOSHIBA_RBTX4927_IOC_INTR_ENAB); v |= (1 << (irq - TOSHIBA_RBTX4927_IRQ_IOC_BEG)); TOSHIBA_RBTX4927_WR08(TOSHIBA_RBTX4927_IOC_INTR_ENAB, v); - - spin_unlock_irqrestore(&toshiba_rbtx4927_ioc_lock, flags); - - return; } static void toshiba_rbtx4927_irq_ioc_disable(unsigned int irq) { - unsigned long flags; volatile unsigned char v; TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_IOC_DISABLE, @@ -454,36 +382,11 @@ static void toshiba_rbtx4927_irq_ioc_disable(unsigned int irq) panic("\n"); } - spin_lock_irqsave(&toshiba_rbtx4927_ioc_lock, flags); - v = TX4927_RD08(TOSHIBA_RBTX4927_IOC_INTR_ENAB); v &= ~(1 << (irq - TOSHIBA_RBTX4927_IRQ_IOC_BEG)); TOSHIBA_RBTX4927_WR08(TOSHIBA_RBTX4927_IOC_INTR_ENAB, v); - - spin_unlock_irqrestore(&toshiba_rbtx4927_ioc_lock, flags); - - return; } - -static void toshiba_rbtx4927_irq_ioc_mask_and_ack(unsigned int irq) -{ - TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_IOC_MASK, - "irq=%d\n", irq); - - if (irq < TOSHIBA_RBTX4927_IRQ_IOC_BEG - || irq > TOSHIBA_RBTX4927_IRQ_IOC_END) { - TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_EROR, - "bad irq=%d\n", irq); - panic("\n"); - } - - toshiba_rbtx4927_irq_ioc_disable(irq); - - return; -} - - static void toshiba_rbtx4927_irq_ioc_end(unsigned int irq) { TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_IOC_ENDIRQ, @@ -499,8 +402,6 @@ static void toshiba_rbtx4927_irq_ioc_end(unsigned int irq) if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) { toshiba_rbtx4927_irq_ioc_enable(irq); } - - return; } @@ -520,13 +421,8 @@ static void __init toshiba_rbtx4927_irq_isa_init(void) TOSHIBA_RBTX4927_IRQ_ISA_END); for (i = TOSHIBA_RBTX4927_IRQ_ISA_BEG; - i <= TOSHIBA_RBTX4927_IRQ_ISA_END; i++) { - irq_desc[i].status = IRQ_DISABLED; - irq_desc[i].action = 0; - irq_desc[i].depth = - ((i < TOSHIBA_RBTX4927_IRQ_ISA_MID) ? (4) : (5)); - irq_desc[i].chip = &toshiba_rbtx4927_irq_isa_type; - } + i <= TOSHIBA_RBTX4927_IRQ_ISA_END; i++) + set_irq_chip(i, &toshiba_rbtx4927_irq_isa_type); setup_irq(TOSHIBA_RBTX4927_IRQ_NEST_ISA_ON_IOC, &toshiba_rbtx4927_irq_isa_master); @@ -536,48 +432,6 @@ static void __init toshiba_rbtx4927_irq_isa_init(void) /* make sure we are looking at IRR (not ISR) */ outb(0x0A, 0x20); outb(0x0A, 0xA0); - - return; -} -#endif - - -#ifdef CONFIG_TOSHIBA_FPCIB0 -static unsigned int toshiba_rbtx4927_irq_isa_startup(unsigned int irq) -{ - TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_ISA_STARTUP, - "irq=%d\n", irq); - - if (irq < TOSHIBA_RBTX4927_IRQ_ISA_BEG - || irq > TOSHIBA_RBTX4927_IRQ_ISA_END) { - TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_EROR, - "bad irq=%d\n", irq); - panic("\n"); - } - - toshiba_rbtx4927_irq_isa_enable(irq); - - return (0); -} -#endif - - -#ifdef CONFIG_TOSHIBA_FPCIB0 -static void toshiba_rbtx4927_irq_isa_shutdown(unsigned int irq) -{ - TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_ISA_SHUTDOWN, - "irq=%d\n", irq); - - if (irq < TOSHIBA_RBTX4927_IRQ_ISA_BEG - || irq > TOSHIBA_RBTX4927_IRQ_ISA_END) { - TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_EROR, - "bad irq=%d\n", irq); - panic("\n"); - } - - toshiba_rbtx4927_irq_isa_disable(irq); - - return; } #endif @@ -596,8 +450,6 @@ static void toshiba_rbtx4927_irq_isa_enable(unsigned int irq) } enable_8259A_irq(irq); - - return; } #endif @@ -616,8 +468,6 @@ static void toshiba_rbtx4927_irq_isa_disable(unsigned int irq) } disable_8259A_irq(irq); - - return; } #endif @@ -636,8 +486,6 @@ static void toshiba_rbtx4927_irq_isa_mask_and_ack(unsigned int irq) } mask_and_ack_8259A(irq); - - return; } #endif @@ -658,8 +506,6 @@ static void toshiba_rbtx4927_irq_isa_end(unsigned int irq) if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) { toshiba_rbtx4927_irq_isa_enable(irq); } - - return; } #endif @@ -668,8 +514,6 @@ void __init arch_init_irq(void) { extern void tx4927_irq_init(void); - local_irq_disable(); - tx4927_irq_init(); toshiba_rbtx4927_irq_ioc_init(); #ifdef CONFIG_TOSHIBA_FPCIB0 @@ -681,8 +525,6 @@ void __init arch_init_irq(void) #endif wbflush(); - - return; } void toshiba_rbtx4927_irq_dump(char *key) @@ -715,7 +557,6 @@ void toshiba_rbtx4927_irq_dump(char *key) } } #endif - return; } void toshiba_rbtx4927_irq_dump_pics(char *s) @@ -780,6 +621,4 @@ void toshiba_rbtx4927_irq_dump_pics(char *s) level5_s); TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_INFO, "[%s]\n", s); - - return; } diff --git a/arch/mips/tx4938/common/irq.c b/arch/mips/tx4938/common/irq.c index 77fe245..19c9ee9 100644 --- a/arch/mips/tx4938/common/irq.c +++ b/arch/mips/tx4938/common/irq.c @@ -37,48 +37,36 @@ /* Forwad definitions for all pic's */ /**********************************************************************************/ -static unsigned int tx4938_irq_cp0_startup(unsigned int irq); -static void tx4938_irq_cp0_shutdown(unsigned int irq); static void tx4938_irq_cp0_enable(unsigned int irq); static void tx4938_irq_cp0_disable(unsigned int irq); -static void tx4938_irq_cp0_mask_and_ack(unsigned int irq); static void tx4938_irq_cp0_end(unsigned int irq); -static unsigned int tx4938_irq_pic_startup(unsigned int irq); -static void tx4938_irq_pic_shutdown(unsigned int irq); static void tx4938_irq_pic_enable(unsigned int irq); static void tx4938_irq_pic_disable(unsigned int irq); -static void tx4938_irq_pic_mask_and_ack(unsigned int irq); static void tx4938_irq_pic_end(unsigned int irq); /**********************************************************************************/ /* Kernel structs for all pic's */ /**********************************************************************************/ -DEFINE_SPINLOCK(tx4938_cp0_lock); -DEFINE_SPINLOCK(tx4938_pic_lock); #define TX4938_CP0_NAME "TX4938-CP0" static struct irq_chip tx4938_irq_cp0_type = { .typename = TX4938_CP0_NAME, - .startup = tx4938_irq_cp0_startup, - .shutdown = tx4938_irq_cp0_shutdown, - .enable = tx4938_irq_cp0_enable, - .disable = tx4938_irq_cp0_disable, - .ack = tx4938_irq_cp0_mask_and_ack, + .ack = tx4938_irq_cp0_disable, + .mask = tx4938_irq_cp0_disable, + .mask_ack = tx4938_irq_cp0_disable, + .unmask = tx4938_irq_cp0_enable, .end = tx4938_irq_cp0_end, - .set_affinity = NULL }; #define TX4938_PIC_NAME "TX4938-PIC" static struct irq_chip tx4938_irq_pic_type = { .typename = TX4938_PIC_NAME, - .startup = tx4938_irq_pic_startup, - .shutdown = tx4938_irq_pic_shutdown, - .enable = tx4938_irq_pic_enable, - .disable = tx4938_irq_pic_disable, - .ack = tx4938_irq_pic_mask_and_ack, + .ack = tx4938_irq_pic_disable, + .mask = tx4938_irq_pic_disable, + .mask_ack = tx4938_irq_pic_disable, + .unmask = tx4938_irq_pic_enable, .end = tx4938_irq_pic_end, - .set_affinity = NULL }; static struct irqaction tx4938_irq_pic_action = { @@ -99,56 +87,20 @@ tx4938_irq_cp0_init(void) { int i; - for (i = TX4938_IRQ_CP0_BEG; i <= TX4938_IRQ_CP0_END; i++) { - irq_desc[i].status = IRQ_DISABLED; - irq_desc[i].action = 0; - irq_desc[i].depth = 1; - irq_desc[i].chip = &tx4938_irq_cp0_type; - } -} - -static unsigned int -tx4938_irq_cp0_startup(unsigned int irq) -{ - tx4938_irq_cp0_enable(irq); - - return 0; -} - -static void -tx4938_irq_cp0_shutdown(unsigned int irq) -{ - tx4938_irq_cp0_disable(irq); + for (i = TX4938_IRQ_CP0_BEG; i <= TX4938_IRQ_CP0_END; i++) + set_irq_chip(i, &tx4938_irq_cp0_type); } static void tx4938_irq_cp0_enable(unsigned int irq) { - unsigned long flags; - - spin_lock_irqsave(&tx4938_cp0_lock, flags); - set_c0_status(tx4938_irq_cp0_mask(irq)); - - spin_unlock_irqrestore(&tx4938_cp0_lock, flags); } static void tx4938_irq_cp0_disable(unsigned int irq) { - unsigned long flags; - - spin_lock_irqsave(&tx4938_cp0_lock, flags); - clear_c0_status(tx4938_irq_cp0_mask(irq)); - - spin_unlock_irqrestore(&tx4938_cp0_lock, flags); -} - -static void -tx4938_irq_cp0_mask_and_ack(unsigned int irq) -{ - tx4938_irq_cp0_disable(irq); } static void @@ -290,70 +242,29 @@ tx4938_irq_pic_modify(unsigned pic_reg, unsigned clr_bits, unsigned set_bits) static void __init tx4938_irq_pic_init(void) { - unsigned long flags; int i; - for (i = TX4938_IRQ_PIC_BEG; i <= TX4938_IRQ_PIC_END; i++) { - irq_desc[i].status = IRQ_DISABLED; - irq_desc[i].action = 0; - irq_desc[i].depth = 2; - irq_desc[i].chip = &tx4938_irq_pic_type; - } + for (i = TX4938_IRQ_PIC_BEG; i <= TX4938_IRQ_PIC_END; i++) + set_irq_chip(i, &tx4938_irq_pic_type); setup_irq(TX4938_IRQ_NEST_PIC_ON_CP0, &tx4938_irq_pic_action); - spin_lock_irqsave(&tx4938_pic_lock, flags); - TX4938_WR(0xff1ff640, 0x6); /* irq level mask -- only accept hightest */ TX4938_WR(0xff1ff600, TX4938_RD(0xff1ff600) | 0x1); /* irq enable */ - - spin_unlock_irqrestore(&tx4938_pic_lock, flags); -} - -static unsigned int -tx4938_irq_pic_startup(unsigned int irq) -{ - tx4938_irq_pic_enable(irq); - - return 0; -} - -static void -tx4938_irq_pic_shutdown(unsigned int irq) -{ - tx4938_irq_pic_disable(irq); } static void tx4938_irq_pic_enable(unsigned int irq) { - unsigned long flags; - - spin_lock_irqsave(&tx4938_pic_lock, flags); - tx4938_irq_pic_modify(tx4938_irq_pic_addr(irq), 0, tx4938_irq_pic_mask(irq)); - - spin_unlock_irqrestore(&tx4938_pic_lock, flags); } static void tx4938_irq_pic_disable(unsigned int irq) { - unsigned long flags; - - spin_lock_irqsave(&tx4938_pic_lock, flags); - tx4938_irq_pic_modify(tx4938_irq_pic_addr(irq), tx4938_irq_pic_mask(irq), 0); - - spin_unlock_irqrestore(&tx4938_pic_lock, flags); -} - -static void -tx4938_irq_pic_mask_and_ack(unsigned int irq) -{ - tx4938_irq_pic_disable(irq); } static void diff --git a/arch/mips/tx4938/toshiba_rbtx4938/irq.c b/arch/mips/tx4938/toshiba_rbtx4938/irq.c index 102e473..2735ffe 100644 --- a/arch/mips/tx4938/toshiba_rbtx4938/irq.c +++ b/arch/mips/tx4938/toshiba_rbtx4938/irq.c @@ -87,25 +87,18 @@ IRQ Device #include #include -static unsigned int toshiba_rbtx4938_irq_ioc_startup(unsigned int irq); -static void toshiba_rbtx4938_irq_ioc_shutdown(unsigned int irq); static void toshiba_rbtx4938_irq_ioc_enable(unsigned int irq); static void toshiba_rbtx4938_irq_ioc_disable(unsigned int irq); -static void toshiba_rbtx4938_irq_ioc_mask_and_ack(unsigned int irq); static void toshiba_rbtx4938_irq_ioc_end(unsigned int irq); -DEFINE_SPINLOCK(toshiba_rbtx4938_ioc_lock); - #define TOSHIBA_RBTX4938_IOC_NAME "RBTX4938-IOC" static struct irq_chip toshiba_rbtx4938_irq_ioc_type = { .typename = TOSHIBA_RBTX4938_IOC_NAME, - .startup = toshiba_rbtx4938_irq_ioc_startup, - .shutdown = toshiba_rbtx4938_irq_ioc_shutdown, - .enable = toshiba_rbtx4938_irq_ioc_enable, - .disable = toshiba_rbtx4938_irq_ioc_disable, - .ack = toshiba_rbtx4938_irq_ioc_mask_and_ack, + .ack = toshiba_rbtx4938_irq_ioc_disable, + .mask = toshiba_rbtx4938_irq_ioc_disable, + .mask_ack = toshiba_rbtx4938_irq_ioc_disable, + .unmask = toshiba_rbtx4938_irq_ioc_enable, .end = toshiba_rbtx4938_irq_ioc_end, - .set_affinity = NULL }; #define TOSHIBA_RBTX4938_IOC_INTR_ENAB 0xb7f02000 @@ -142,69 +135,35 @@ toshiba_rbtx4938_irq_ioc_init(void) int i; for (i = TOSHIBA_RBTX4938_IRQ_IOC_BEG; - i <= TOSHIBA_RBTX4938_IRQ_IOC_END; i++) { - irq_desc[i].status = IRQ_DISABLED; - irq_desc[i].action = 0; - irq_desc[i].depth = 3; - irq_desc[i].chip = &toshiba_rbtx4938_irq_ioc_type; - } + i <= TOSHIBA_RBTX4938_IRQ_IOC_END; i++) + set_irq_chip(i, &toshiba_rbtx4938_irq_ioc_type); setup_irq(RBTX4938_IRQ_IOCINT, &toshiba_rbtx4938_irq_ioc_action); } -static unsigned int -toshiba_rbtx4938_irq_ioc_startup(unsigned int irq) -{ - toshiba_rbtx4938_irq_ioc_enable(irq); - - return 0; -} - -static void -toshiba_rbtx4938_irq_ioc_shutdown(unsigned int irq) -{ - toshiba_rbtx4938_irq_ioc_disable(irq); -} - static void toshiba_rbtx4938_irq_ioc_enable(unsigned int irq) { - unsigned long flags; volatile unsigned char v; - spin_lock_irqsave(&toshiba_rbtx4938_ioc_lock, flags); - v = TX4938_RD08(TOSHIBA_RBTX4938_IOC_INTR_ENAB); v |= (1 << (irq - TOSHIBA_RBTX4938_IRQ_IOC_BEG)); TX4938_WR08(TOSHIBA_RBTX4938_IOC_INTR_ENAB, v); mmiowb(); TX4938_RD08(TOSHIBA_RBTX4938_IOC_INTR_ENAB); - - spin_unlock_irqrestore(&toshiba_rbtx4938_ioc_lock, flags); } static void toshiba_rbtx4938_irq_ioc_disable(unsigned int irq) { - unsigned long flags; volatile unsigned char v; - spin_lock_irqsave(&toshiba_rbtx4938_ioc_lock, flags); - v = TX4938_RD08(TOSHIBA_RBTX4938_IOC_INTR_ENAB); v &= ~(1 << (irq - TOSHIBA_RBTX4938_IRQ_IOC_BEG)); TX4938_WR08(TOSHIBA_RBTX4938_IOC_INTR_ENAB, v); mmiowb(); TX4938_RD08(TOSHIBA_RBTX4938_IOC_INTR_ENAB); - - spin_unlock_irqrestore(&toshiba_rbtx4938_ioc_lock, flags); -} - -static void -toshiba_rbtx4938_irq_ioc_mask_and_ack(unsigned int irq) -{ - toshiba_rbtx4938_irq_ioc_disable(irq); } static void diff --git a/arch/mips/vr41xx/common/icu.c b/arch/mips/vr41xx/common/icu.c index c215c0d..33d70a6 100644 --- a/arch/mips/vr41xx/common/icu.c +++ b/arch/mips/vr41xx/common/icu.c @@ -417,14 +417,7 @@ void vr41xx_disable_bcuint(void) EXPORT_SYMBOL(vr41xx_disable_bcuint); -static unsigned int startup_sysint1_irq(unsigned int irq) -{ - icu1_set(MSYSINT1REG, 1 << SYSINT1_IRQ_TO_PIN(irq)); - - return 0; /* never anything pending */ -} - -static void shutdown_sysint1_irq(unsigned int irq) +static void disable_sysint1_irq(unsigned int irq) { icu1_clear(MSYSINT1REG, 1 << SYSINT1_IRQ_TO_PIN(irq)); } @@ -434,9 +427,6 @@ static void enable_sysint1_irq(unsigned int irq) icu1_set(MSYSINT1REG, 1 << SYSINT1_IRQ_TO_PIN(irq)); } -#define disable_sysint1_irq shutdown_sysint1_irq -#define ack_sysint1_irq shutdown_sysint1_irq - static void end_sysint1_irq(unsigned int irq) { if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) @@ -445,22 +435,14 @@ static void end_sysint1_irq(unsigned int irq) static struct irq_chip sysint1_irq_type = { .typename = "SYSINT1", - .startup = startup_sysint1_irq, - .shutdown = shutdown_sysint1_irq, - .enable = enable_sysint1_irq, - .disable = disable_sysint1_irq, - .ack = ack_sysint1_irq, + .ack = disable_sysint1_irq, + .mask = disable_sysint1_irq, + .mask_ack = disable_sysint1_irq, + .unmask = enable_sysint1_irq, .end = end_sysint1_irq, }; -static unsigned int startup_sysint2_irq(unsigned int irq) -{ - icu2_set(MSYSINT2REG, 1 << SYSINT2_IRQ_TO_PIN(irq)); - - return 0; /* never anything pending */ -} - -static void shutdown_sysint2_irq(unsigned int irq) +static void disable_sysint2_irq(unsigned int irq) { icu2_clear(MSYSINT2REG, 1 << SYSINT2_IRQ_TO_PIN(irq)); } @@ -470,9 +452,6 @@ static void enable_sysint2_irq(unsigned int irq) icu2_set(MSYSINT2REG, 1 << SYSINT2_IRQ_TO_PIN(irq)); } -#define disable_sysint2_irq shutdown_sysint2_irq -#define ack_sysint2_irq shutdown_sysint2_irq - static void end_sysint2_irq(unsigned int irq) { if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) @@ -481,11 +460,10 @@ static void end_sysint2_irq(unsigned int irq) static struct irq_chip sysint2_irq_type = { .typename = "SYSINT2", - .startup = startup_sysint2_irq, - .shutdown = shutdown_sysint2_irq, - .enable = enable_sysint2_irq, - .disable = disable_sysint2_irq, - .ack = ack_sysint2_irq, + .ack = disable_sysint2_irq, + .mask = disable_sysint2_irq, + .mask_ack = disable_sysint2_irq, + .unmask = enable_sysint2_irq, .end = end_sysint2_irq, }; @@ -723,10 +701,10 @@ static int __init vr41xx_icu_init(void) icu2_write(MGIUINTHREG, 0xffff); for (i = SYSINT1_IRQ_BASE; i <= SYSINT1_IRQ_LAST; i++) - irq_desc[i].chip = &sysint1_irq_type; + set_irq_chip(i, &sysint1_irq_type); for (i = SYSINT2_IRQ_BASE; i <= SYSINT2_IRQ_LAST; i++) - irq_desc[i].chip = &sysint2_irq_type; + set_irq_chip(i, &sysint2_irq_type); cascade_irq(INT0_IRQ, icu_get_irq); cascade_irq(INT1_IRQ, icu_get_irq); diff --git a/arch/mips/vr41xx/nec-cmbvr4133/irq.c b/arch/mips/vr41xx/nec-cmbvr4133/irq.c index 2483487..a039bb7 100644 --- a/arch/mips/vr41xx/nec-cmbvr4133/irq.c +++ b/arch/mips/vr41xx/nec-cmbvr4133/irq.c @@ -30,17 +30,6 @@ extern void init_8259A(int hoge); extern int vr4133_rockhopper; -static unsigned int startup_i8259_irq(unsigned int irq) -{ - enable_8259A_irq(irq - I8259_IRQ_BASE); - return 0; -} - -static void shutdown_i8259_irq(unsigned int irq) -{ - disable_8259A_irq(irq - I8259_IRQ_BASE); -} - static void enable_i8259_irq(unsigned int irq) { enable_8259A_irq(irq - I8259_IRQ_BASE); @@ -64,11 +53,10 @@ static void end_i8259_irq(unsigned int irq) static struct irq_chip i8259_irq_type = { .typename = "XT-PIC", - .startup = startup_i8259_irq, - .shutdown = shutdown_i8259_irq, - .enable = enable_i8259_irq, - .disable = disable_i8259_irq, .ack = ack_i8259_irq, + .mask = disable_i8259_irq, + .mask_ack = ack_i8259_irq, + .unmask = enable_i8259_irq, .end = end_i8259_irq, }; @@ -104,7 +92,7 @@ void __init rockhopper_init_irq(void) } for (i = I8259_IRQ_BASE; i <= I8259_IRQ_LAST; i++) - irq_desc[i].chip = &i8259_irq_type; + set_irq_chip(i, &i8259_irq_type); setup_irq(I8259_SLAVE_IRQ, &i8259_slave_cascade); -- cgit v1.1 From 1417836e81c0ab8f5a0bfeafa90d3eaa41b2a067 Mon Sep 17 00:00:00 2001 From: Atsushi Nemoto Date: Tue, 14 Nov 2006 01:13:18 +0900 Subject: [MIPS] use generic_handle_irq, handle_level_irq, handle_percpu_irq Further incorporation of generic irq framework. Replacing __do_IRQ() by proper flow handler would make the irq handling path a bit simpler and faster. * use generic_handle_irq() instead of __do_IRQ(). * use handle_level_irq for obvious level-type irq chips. * use handle_percpu_irq for irqs marked as IRQ_PER_CPU. * setup .eoi routine for irq chips possibly used with handle_percpu_irq. Signed-off-by: Atsushi Nemoto Signed-off-by: Ralf Baechle --- arch/mips/dec/ioasic-irq.c | 6 ++++-- arch/mips/dec/kn02-irq.c | 2 +- arch/mips/emma2rh/common/irq_emma2rh.c | 3 ++- arch/mips/emma2rh/markeins/irq_markeins.c | 3 ++- arch/mips/jazz/irq.c | 2 +- arch/mips/kernel/irq-msc01.c | 2 ++ arch/mips/kernel/irq-mv6434x.c | 3 ++- arch/mips/kernel/irq-rm7000.c | 3 ++- arch/mips/kernel/irq-rm9000.c | 6 ++++-- arch/mips/kernel/irq_cpu.c | 5 ++++- arch/mips/kernel/smp-mt.c | 2 ++ arch/mips/kernel/smtc.c | 1 + arch/mips/lasat/interrupt.c | 2 +- arch/mips/mips-boards/atlas/atlas_int.c | 3 ++- arch/mips/mips-boards/generic/time.c | 1 + arch/mips/mips-boards/sim/sim_time.c | 3 ++- arch/mips/momentum/ocelot_c/cpci-irq.c | 2 +- arch/mips/momentum/ocelot_c/uart-irq.c | 4 ++-- arch/mips/philips/pnx8550/common/int.c | 12 +++++++----- arch/mips/sgi-ip22/ip22-int.c | 2 +- arch/mips/sgi-ip27/ip27-irq.c | 2 +- arch/mips/sgi-ip27/ip27-timer.c | 3 ++- arch/mips/tx4927/common/tx4927_irq.c | 6 ++++-- arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c | 3 ++- arch/mips/tx4938/common/irq.c | 6 ++++-- arch/mips/tx4938/toshiba_rbtx4938/irq.c | 3 ++- arch/mips/vr41xx/common/icu.c | 6 ++++-- 27 files changed, 63 insertions(+), 33 deletions(-) (limited to 'arch/mips') diff --git a/arch/mips/dec/ioasic-irq.c b/arch/mips/dec/ioasic-irq.c index d0af08b..269b22b 100644 --- a/arch/mips/dec/ioasic-irq.c +++ b/arch/mips/dec/ioasic-irq.c @@ -103,9 +103,11 @@ void __init init_ioasic_irqs(int base) fast_iob(); for (i = base; i < base + IO_INR_DMA; i++) - set_irq_chip(i, &ioasic_irq_type); + set_irq_chip_and_handler(i, &ioasic_irq_type, + handle_level_irq); for (; i < base + IO_IRQ_LINES; i++) - set_irq_chip(i, &ioasic_dma_irq_type); + set_irq_chip_and_handler(i, &ioasic_dma_irq_type, + handle_level_irq); ioasic_irq_base = base; } diff --git a/arch/mips/dec/kn02-irq.c b/arch/mips/dec/kn02-irq.c index c761d97..5a9be4c 100644 --- a/arch/mips/dec/kn02-irq.c +++ b/arch/mips/dec/kn02-irq.c @@ -85,7 +85,7 @@ void __init init_kn02_irqs(int base) iob(); for (i = base; i < base + KN02_IRQ_LINES; i++) - set_irq_chip(i, &kn02_irq_type); + set_irq_chip_and_handler(i, &kn02_irq_type, handle_level_irq); kn02_irq_base = base; } diff --git a/arch/mips/emma2rh/common/irq_emma2rh.c b/arch/mips/emma2rh/common/irq_emma2rh.c index bf1b83b..59b9829 100644 --- a/arch/mips/emma2rh/common/irq_emma2rh.c +++ b/arch/mips/emma2rh/common/irq_emma2rh.c @@ -76,7 +76,8 @@ void emma2rh_irq_init(u32 irq_base) u32 i; for (i = irq_base; i < irq_base + NUM_EMMA2RH_IRQ; i++) - set_irq_chip(i, &emma2rh_irq_controller); + set_irq_chip_and_handler(i, &emma2rh_irq_controller, + handle_level_irq); emma2rh_irq_base = irq_base; } diff --git a/arch/mips/emma2rh/markeins/irq_markeins.c b/arch/mips/emma2rh/markeins/irq_markeins.c index 8e5f08a..3ac4e40 100644 --- a/arch/mips/emma2rh/markeins/irq_markeins.c +++ b/arch/mips/emma2rh/markeins/irq_markeins.c @@ -68,7 +68,8 @@ void emma2rh_sw_irq_init(u32 irq_base) u32 i; for (i = irq_base; i < irq_base + NUM_EMMA2RH_IRQ_SW; i++) - set_irq_chip(i, &emma2rh_sw_irq_controller); + set_irq_chip_and_handler(i, &emma2rh_sw_irq_controller, + handle_level_irq); emma2rh_sw_irq_base = irq_base; } diff --git a/arch/mips/jazz/irq.c b/arch/mips/jazz/irq.c index 4bbb6cb..5c4f50c 100644 --- a/arch/mips/jazz/irq.c +++ b/arch/mips/jazz/irq.c @@ -59,7 +59,7 @@ void __init init_r4030_ints(void) int i; for (i = JAZZ_PARALLEL_IRQ; i <= JAZZ_TIMER_IRQ; i++) - set_irq_chip(i, &r4030_irq_type); + set_irq_chip_and_handler(i, &r4030_irq_type, handle_level_irq); r4030_write_reg16(JAZZ_IO_IRQ_ENABLE, 0); r4030_read_reg16(JAZZ_IO_IRQ_SOURCE); /* clear pending IRQs */ diff --git a/arch/mips/kernel/irq-msc01.c b/arch/mips/kernel/irq-msc01.c index e1880b2..bcaad66 100644 --- a/arch/mips/kernel/irq-msc01.c +++ b/arch/mips/kernel/irq-msc01.c @@ -117,6 +117,7 @@ struct irq_chip msc_levelirq_type = { .mask = mask_msc_irq, .mask_ack = level_mask_and_ack_msc_irq, .unmask = unmask_msc_irq, + .eoi = unmask_msc_irq, .end = end_msc_irq, }; @@ -126,6 +127,7 @@ struct irq_chip msc_edgeirq_type = { .mask = mask_msc_irq, .mask_ack = edge_mask_and_ack_msc_irq, .unmask = unmask_msc_irq, + .eoi = unmask_msc_irq, .end = end_msc_irq, }; diff --git a/arch/mips/kernel/irq-mv6434x.c b/arch/mips/kernel/irq-mv6434x.c index 5012b9d..6cfb31c 100644 --- a/arch/mips/kernel/irq-mv6434x.c +++ b/arch/mips/kernel/irq-mv6434x.c @@ -114,7 +114,8 @@ void __init mv64340_irq_init(unsigned int base) int i; for (i = base; i < base + 64; i++) - set_irq_chip(i, &mv64340_irq_type); + set_irq_chip_and_handler(i, &mv64340_irq_type, + handle_level_irq); irq_base = base; } diff --git a/arch/mips/kernel/irq-rm7000.c b/arch/mips/kernel/irq-rm7000.c index 6a297e3..ddcc2a5 100644 --- a/arch/mips/kernel/irq-rm7000.c +++ b/arch/mips/kernel/irq-rm7000.c @@ -51,7 +51,8 @@ void __init rm7k_cpu_irq_init(int base) clear_c0_intcontrol(0x00000f00); /* Mask all */ for (i = base; i < base + 4; i++) - set_irq_chip(i, &rm7k_irq_controller); + set_irq_chip_and_handler(i, &rm7k_irq_controller, + handle_level_irq); irq_base = base; } diff --git a/arch/mips/kernel/irq-rm9000.c b/arch/mips/kernel/irq-rm9000.c index 9775384..ba6440c 100644 --- a/arch/mips/kernel/irq-rm9000.c +++ b/arch/mips/kernel/irq-rm9000.c @@ -117,10 +117,12 @@ void __init rm9k_cpu_irq_init(int base) clear_c0_intcontrol(0x0000f000); /* Mask all */ for (i = base; i < base + 4; i++) - set_irq_chip(i, &rm9k_irq_controller); + set_irq_chip_and_handler(i, &rm9k_irq_controller, + handle_level_irq); rm9000_perfcount_irq = base + 1; - set_irq_chip(rm9000_perfcount_irq, &rm9k_perfcounter_irq); + set_irq_chip_and_handler(rm9000_perfcount_irq, &rm9k_perfcounter_irq, + handle_level_irq); irq_base = base; } diff --git a/arch/mips/kernel/irq_cpu.c b/arch/mips/kernel/irq_cpu.c index 3b7cfa4..be5ac23 100644 --- a/arch/mips/kernel/irq_cpu.c +++ b/arch/mips/kernel/irq_cpu.c @@ -62,6 +62,7 @@ static struct irq_chip mips_cpu_irq_controller = { .mask = mask_mips_irq, .mask_ack = mask_mips_irq, .unmask = unmask_mips_irq, + .eoi = unmask_mips_irq, .end = mips_cpu_irq_end, }; @@ -104,6 +105,7 @@ static struct irq_chip mips_mt_cpu_irq_controller = { .mask = mask_mips_mt_irq, .mask_ack = mips_mt_cpu_irq_ack, .unmask = unmask_mips_mt_irq, + .eoi = unmask_mips_mt_irq, .end = mips_mt_cpu_irq_end, }; @@ -124,7 +126,8 @@ void __init mips_cpu_irq_init(int irq_base) set_irq_chip(i, &mips_mt_cpu_irq_controller); for (i = irq_base + 2; i < irq_base + 8; i++) - set_irq_chip(i, &mips_cpu_irq_controller); + set_irq_chip_and_handler(i, &mips_cpu_irq_controller, + handle_level_irq); mips_cpu_irq_base = irq_base; } diff --git a/arch/mips/kernel/smp-mt.c b/arch/mips/kernel/smp-mt.c index 2ac19a6c..1ee689c 100644 --- a/arch/mips/kernel/smp-mt.c +++ b/arch/mips/kernel/smp-mt.c @@ -278,7 +278,9 @@ void __init plat_prepare_cpus(unsigned int max_cpus) /* need to mark IPI's as IRQ_PER_CPU */ irq_desc[cpu_ipi_resched_irq].status |= IRQ_PER_CPU; + set_irq_handler(cpu_ipi_resched_irq, handle_percpu_irq); irq_desc[cpu_ipi_call_irq].status |= IRQ_PER_CPU; + set_irq_handler(cpu_ipi_call_irq, handle_percpu_irq); } /* diff --git a/arch/mips/kernel/smtc.c b/arch/mips/kernel/smtc.c index 3b78caf..802febe 100644 --- a/arch/mips/kernel/smtc.c +++ b/arch/mips/kernel/smtc.c @@ -1009,6 +1009,7 @@ void setup_cross_vpe_interrupts(void) setup_irq_smtc(cpu_ipi_irq, &irq_ipi, (0x100 << MIPS_CPU_IPI_IRQ)); irq_desc[cpu_ipi_irq].status |= IRQ_PER_CPU; + set_irq_handler(cpu_ipi_irq, handle_percpu_irq); } /* diff --git a/arch/mips/lasat/interrupt.c b/arch/mips/lasat/interrupt.c index cac82af..4a84a7b 100644 --- a/arch/mips/lasat/interrupt.c +++ b/arch/mips/lasat/interrupt.c @@ -133,5 +133,5 @@ void __init arch_init_irq(void) } for (i = 0; i <= LASATINT_END; i++) - set_irq_chip(i, &lasat_irq_type); + set_irq_chip_and_handler(i, &lasat_irq_type, handle_level_irq); } diff --git a/arch/mips/mips-boards/atlas/atlas_int.c b/arch/mips/mips-boards/atlas/atlas_int.c index 7c71004..43dba6c 100644 --- a/arch/mips/mips-boards/atlas/atlas_int.c +++ b/arch/mips/mips-boards/atlas/atlas_int.c @@ -74,6 +74,7 @@ static struct irq_chip atlas_irq_type = { .mask = disable_atlas_irq, .mask_ack = disable_atlas_irq, .unmask = enable_atlas_irq, + .eoi = enable_atlas_irq, .end = end_atlas_irq, }; @@ -207,7 +208,7 @@ static inline void init_atlas_irqs (int base) atlas_hw0_icregs->intrsten = 0xffffffff; for (i = ATLAS_INT_BASE; i <= ATLAS_INT_END; i++) - set_irq_chip(i, &atlas_irq_type); + set_irq_chip_and_handler(i, &atlas_irq_type, handle_level_irq); } static struct irqaction atlasirq = { diff --git a/arch/mips/mips-boards/generic/time.c b/arch/mips/mips-boards/generic/time.c index d817c60..e4604c7 100644 --- a/arch/mips/mips-boards/generic/time.c +++ b/arch/mips/mips-boards/generic/time.c @@ -288,6 +288,7 @@ void __init plat_timer_setup(struct irqaction *irq) The effect is that the int remains disabled on the second cpu. Mark the interrupt with IRQ_PER_CPU to avoid any confusion */ irq_desc[mips_cpu_timer_irq].status |= IRQ_PER_CPU; + set_irq_handler(mips_cpu_timer_irq, handle_percpu_irq); #endif /* to generate the first timer interrupt */ diff --git a/arch/mips/mips-boards/sim/sim_time.c b/arch/mips/mips-boards/sim/sim_time.c index 24a4ed0..f2d998d 100644 --- a/arch/mips/mips-boards/sim/sim_time.c +++ b/arch/mips/mips-boards/sim/sim_time.c @@ -203,7 +203,8 @@ void __init plat_timer_setup(struct irqaction *irq) on seperate cpu's the first one tries to handle the second interrupt. The effect is that the int remains disabled on the second cpu. Mark the interrupt with IRQ_PER_CPU to avoid any confusion */ - irq_desc[mips_cpu_timer_irq].status |= IRQ_PER_CPU; + irq_desc[mips_cpu_timer_irq].flags |= IRQ_PER_CPU; + set_irq_handler(mips_cpu_timer_irq, handle_percpu_irq); #endif /* to generate the first timer interrupt */ diff --git a/arch/mips/momentum/ocelot_c/cpci-irq.c b/arch/mips/momentum/ocelot_c/cpci-irq.c index 7723f09..e5a4a0a 100644 --- a/arch/mips/momentum/ocelot_c/cpci-irq.c +++ b/arch/mips/momentum/ocelot_c/cpci-irq.c @@ -106,5 +106,5 @@ void cpci_irq_init(void) int i; for (i = CPCI_IRQ_BASE; i < (CPCI_IRQ_BASE + 8); i++) - set_irq_chip(i, &cpci_irq_type); + set_irq_chip_and_handler(i, &cpci_irq_type, handle_level_irq); } diff --git a/arch/mips/momentum/ocelot_c/uart-irq.c b/arch/mips/momentum/ocelot_c/uart-irq.c index 72faf81..0029f00 100644 --- a/arch/mips/momentum/ocelot_c/uart-irq.c +++ b/arch/mips/momentum/ocelot_c/uart-irq.c @@ -96,6 +96,6 @@ struct irq_chip uart_irq_type = { void uart_irq_init(void) { - set_irq_chip(80, &uart_irq_type); - set_irq_chip(81, &uart_irq_type); + set_irq_chip_and_handler(80, &uart_irq_type, handle_level_irq); + set_irq_chip_and_handler(81, &uart_irq_type, handle_level_irq); } diff --git a/arch/mips/philips/pnx8550/common/int.c b/arch/mips/philips/pnx8550/common/int.c index e4bf494..0dc2393 100644 --- a/arch/mips/philips/pnx8550/common/int.c +++ b/arch/mips/philips/pnx8550/common/int.c @@ -192,7 +192,7 @@ void __init arch_init_irq(void) int configPR; for (i = 0; i < PNX8550_INT_CP0_TOTINT; i++) { - set_irq_chip(i, &level_irq_type); + set_irq_chip_and_handler(i, &level_irq_type, handle_level_irq); mask_irq(i); /* mask the irq just in case */ } @@ -229,7 +229,7 @@ void __init arch_init_irq(void) /* mask/priority is still 0 so we will not get any * interrupts until it is unmasked */ - set_irq_chip(i, &level_irq_type); + set_irq_chip_and_handler(i, &level_irq_type, handle_level_irq); } /* Priority level 0 */ @@ -238,19 +238,21 @@ void __init arch_init_irq(void) /* Set int vector table address */ PNX8550_GIC_VECTOR_0 = PNX8550_GIC_VECTOR_1 = 0; - set_irq_chip(MIPS_CPU_GIC_IRQ, &level_irq_type); + set_irq_chip_and_handler(MIPS_CPU_GIC_IRQ, &level_irq_type, + handle_level_irq); setup_irq(MIPS_CPU_GIC_IRQ, &gic_action); /* init of Timer interrupts */ for (i = PNX8550_INT_TIMER_MIN; i <= PNX8550_INT_TIMER_MAX; i++) - set_irq_chip(i, &level_irq_type); + set_irq_chip_and_handler(i, &level_irq_type, handle_level_irq); /* Stop Timer 1-3 */ configPR = read_c0_config7(); configPR |= 0x00000038; write_c0_config7(configPR); - set_irq_chip(MIPS_CPU_TIMER_IRQ, &level_irq_type); + set_irq_chip_and_handler(MIPS_CPU_TIMER_IRQ, &level_irq_type, + handle_level_irq); setup_irq(MIPS_CPU_TIMER_IRQ, &timer_action); } diff --git a/arch/mips/sgi-ip22/ip22-int.c b/arch/mips/sgi-ip22/ip22-int.c index 8e2074b..c7b1380 100644 --- a/arch/mips/sgi-ip22/ip22-int.c +++ b/arch/mips/sgi-ip22/ip22-int.c @@ -358,7 +358,7 @@ void __init arch_init_irq(void) else handler = &ip22_local3_irq_type; - set_irq_chip(i, handler); + set_irq_chip_and_handler(i, handler, handle_level_irq); } /* vector handler. this register the IRQ as non-sharable */ diff --git a/arch/mips/sgi-ip27/ip27-irq.c b/arch/mips/sgi-ip27/ip27-irq.c index 8243202..5f8835b 100644 --- a/arch/mips/sgi-ip27/ip27-irq.c +++ b/arch/mips/sgi-ip27/ip27-irq.c @@ -352,7 +352,7 @@ static struct irq_chip bridge_irq_type = { void __devinit register_bridge_irq(unsigned int irq) { - set_irq_chip(irq, &bridge_irq_type); + set_irq_chip_and_handler(irq, &bridge_irq_type, handle_level_irq); } int __devinit request_bridge_irq(struct bridge_controller *bc) diff --git a/arch/mips/sgi-ip27/ip27-timer.c b/arch/mips/sgi-ip27/ip27-timer.c index 86ba7fc..e5441c3 100644 --- a/arch/mips/sgi-ip27/ip27-timer.c +++ b/arch/mips/sgi-ip27/ip27-timer.c @@ -190,6 +190,7 @@ static struct irq_chip rt_irq_type = { .mask = disable_rt_irq, .mask_ack = disable_rt_irq, .unmask = enable_rt_irq, + .eoi = enable_rt_irq, .end = end_rt_irq, }; @@ -207,7 +208,7 @@ void __init plat_timer_setup(struct irqaction *irq) if (irqno < 0) panic("Can't allocate interrupt number for timer interrupt"); - set_irq_chip(irqno, &rt_irq_type); + set_irq_chip_and_handler(irqno, &rt_irq_type, handle_percpu_irq); /* over-write the handler, we use our own way */ irq->handler = no_action; diff --git a/arch/mips/tx4927/common/tx4927_irq.c b/arch/mips/tx4927/common/tx4927_irq.c index 2c57ced..21873de 100644 --- a/arch/mips/tx4927/common/tx4927_irq.c +++ b/arch/mips/tx4927/common/tx4927_irq.c @@ -196,7 +196,8 @@ static void __init tx4927_irq_cp0_init(void) TX4927_IRQ_CP0_BEG, TX4927_IRQ_CP0_END); for (i = TX4927_IRQ_CP0_BEG; i <= TX4927_IRQ_CP0_END; i++) - set_irq_chip(i, &tx4927_irq_cp0_type); + set_irq_chip_and_handler(i, &tx4927_irq_cp0_type, + handle_level_irq); } static void tx4927_irq_cp0_enable(unsigned int irq) @@ -350,7 +351,8 @@ static void __init tx4927_irq_pic_init(void) TX4927_IRQ_PIC_BEG, TX4927_IRQ_PIC_END); for (i = TX4927_IRQ_PIC_BEG; i <= TX4927_IRQ_PIC_END; i++) - set_irq_chip(i, &tx4927_irq_pic_type); + set_irq_chip_and_handler(i, &tx4927_irq_pic_type, + handle_level_irq); setup_irq(TX4927_IRQ_NEST_PIC_ON_CP0, &tx4927_irq_pic_action); diff --git a/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c b/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c index 1fdace8..34cdb2a 100644 --- a/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c +++ b/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c @@ -342,7 +342,8 @@ static void __init toshiba_rbtx4927_irq_ioc_init(void) for (i = TOSHIBA_RBTX4927_IRQ_IOC_BEG; i <= TOSHIBA_RBTX4927_IRQ_IOC_END; i++) - set_irq_chip(i, &toshiba_rbtx4927_irq_ioc_type); + set_irq_chip_and_handler(i, &toshiba_rbtx4927_irq_ioc_type, + handle_level_irq); setup_irq(TOSHIBA_RBTX4927_IRQ_NEST_IOC_ON_PIC, &toshiba_rbtx4927_irq_ioc_action); diff --git a/arch/mips/tx4938/common/irq.c b/arch/mips/tx4938/common/irq.c index 19c9ee9..42e1276 100644 --- a/arch/mips/tx4938/common/irq.c +++ b/arch/mips/tx4938/common/irq.c @@ -88,7 +88,8 @@ tx4938_irq_cp0_init(void) int i; for (i = TX4938_IRQ_CP0_BEG; i <= TX4938_IRQ_CP0_END; i++) - set_irq_chip(i, &tx4938_irq_cp0_type); + set_irq_chip_and_handler(i, &tx4938_irq_cp0_type, + handle_level_irq); } static void @@ -245,7 +246,8 @@ tx4938_irq_pic_init(void) int i; for (i = TX4938_IRQ_PIC_BEG; i <= TX4938_IRQ_PIC_END; i++) - set_irq_chip(i, &tx4938_irq_pic_type); + set_irq_chip_and_handler(i, &tx4938_irq_pic_type, + handle_level_irq); setup_irq(TX4938_IRQ_NEST_PIC_ON_CP0, &tx4938_irq_pic_action); diff --git a/arch/mips/tx4938/toshiba_rbtx4938/irq.c b/arch/mips/tx4938/toshiba_rbtx4938/irq.c index 2735ffe..8c87a35 100644 --- a/arch/mips/tx4938/toshiba_rbtx4938/irq.c +++ b/arch/mips/tx4938/toshiba_rbtx4938/irq.c @@ -136,7 +136,8 @@ toshiba_rbtx4938_irq_ioc_init(void) for (i = TOSHIBA_RBTX4938_IRQ_IOC_BEG; i <= TOSHIBA_RBTX4938_IRQ_IOC_END; i++) - set_irq_chip(i, &toshiba_rbtx4938_irq_ioc_type); + set_irq_chip_and_handler(i, &toshiba_rbtx4938_irq_ioc_type, + handle_level_irq); setup_irq(RBTX4938_IRQ_IOCINT, &toshiba_rbtx4938_irq_ioc_action); diff --git a/arch/mips/vr41xx/common/icu.c b/arch/mips/vr41xx/common/icu.c index 33d70a6..54b92a7 100644 --- a/arch/mips/vr41xx/common/icu.c +++ b/arch/mips/vr41xx/common/icu.c @@ -701,10 +701,12 @@ static int __init vr41xx_icu_init(void) icu2_write(MGIUINTHREG, 0xffff); for (i = SYSINT1_IRQ_BASE; i <= SYSINT1_IRQ_LAST; i++) - set_irq_chip(i, &sysint1_irq_type); + set_irq_chip_and_handler(i, &sysint1_irq_type, + handle_level_irq); for (i = SYSINT2_IRQ_BASE; i <= SYSINT2_IRQ_LAST; i++) - set_irq_chip(i, &sysint2_irq_type); + set_irq_chip_and_handler(i, &sysint2_irq_type, + handle_level_irq); cascade_irq(INT0_IRQ, icu_get_irq); cascade_irq(INT1_IRQ, icu_get_irq); -- cgit v1.1 From dd6bfd627c4f4df771b9b73e4df75c6c0c177b09 Mon Sep 17 00:00:00 2001 From: Nicolas Kaiser Date: Tue, 7 Nov 2006 09:56:24 +0100 Subject: [MIPS] Fix double inclusions Signed-off-by: Nicolas Kaiser Signed-off-by: Ralf Baechle --- arch/mips/kernel/signal_n32.c | 1 - arch/mips/mips-boards/sim/sim_time.c | 15 ++++----------- arch/mips/sibyte/bcm1480/time.c | 2 -- arch/mips/tx4938/common/setup.c | 1 - 4 files changed, 4 insertions(+), 15 deletions(-) (limited to 'arch/mips') diff --git a/arch/mips/kernel/signal_n32.c b/arch/mips/kernel/signal_n32.c index 477c533..a67c185 100644 --- a/arch/mips/kernel/signal_n32.c +++ b/arch/mips/kernel/signal_n32.c @@ -17,7 +17,6 @@ */ #include #include -#include #include #include #include diff --git a/arch/mips/mips-boards/sim/sim_time.c b/arch/mips/mips-boards/sim/sim_time.c index f2d998d..30711d0 100644 --- a/arch/mips/mips-boards/sim/sim_time.c +++ b/arch/mips/mips-boards/sim/sim_time.c @@ -3,31 +3,24 @@ #include #include #include - -#include -#include -#include -#include -#include -#include - #include #include #include + #include +#include #include -#include #include #include #include +#include #include #include +#include #include #include #include -#include -#include unsigned long cpu_khz; diff --git a/arch/mips/sibyte/bcm1480/time.c b/arch/mips/sibyte/bcm1480/time.c index e136bde..03d5822 100644 --- a/arch/mips/sibyte/bcm1480/time.c +++ b/arch/mips/sibyte/bcm1480/time.c @@ -94,8 +94,6 @@ void bcm1480_time_init(void) */ } -#include - void bcm1480_timer_interrupt(void) { int cpu = smp_processor_id(); diff --git a/arch/mips/tx4938/common/setup.c b/arch/mips/tx4938/common/setup.c index f415a1f..dc87d92 100644 --- a/arch/mips/tx4938/common/setup.c +++ b/arch/mips/tx4938/common/setup.c @@ -31,7 +31,6 @@ #include #include #include -#include #include extern void toshiba_rbtx4938_setup(void); -- cgit v1.1 From e56798824456bd907cefe840ca127df0518942e3 Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Thu, 30 Nov 2006 01:14:47 +0000 Subject: [MIPS] Work around bogus gcc warnings. Signed-off-by: Ralf Baechle --- arch/mips/kernel/traps.c | 43 ++++++++++++++++++++++--------------------- 1 file changed, 22 insertions(+), 21 deletions(-) (limited to 'arch/mips') diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c index 6eccfb4..0ae19e1 100644 --- a/arch/mips/kernel/traps.c +++ b/arch/mips/kernel/traps.c @@ -399,19 +399,6 @@ asmlinkage void do_be(struct pt_regs *regs) force_sig(SIGBUS, current); } -static inline int get_insn_opcode(struct pt_regs *regs, unsigned int *opcode) -{ - unsigned int __user *epc; - - epc = (unsigned int __user *) regs->cp0_epc + - ((regs->cp0_cause & CAUSEF_BD) != 0); - if (!get_user(*opcode, epc)) - return 0; - - force_sig(SIGSEGV, current); - return 1; -} - /* * ll/sc emulation */ @@ -546,8 +533,8 @@ static inline int simulate_llsc(struct pt_regs *regs) { unsigned int opcode; - if (unlikely(get_insn_opcode(regs, &opcode))) - return -EFAULT; + if (get_user(opcode, (unsigned int __user *) exception_epc(regs))) + goto out_sigsegv; if ((opcode & OPCODE) == LL) { simulate_ll(regs, opcode); @@ -559,6 +546,10 @@ static inline int simulate_llsc(struct pt_regs *regs) } return -EFAULT; /* Strange things going on ... */ + +out_sigsegv: + force_sig(SIGSEGV, current); + return -EFAULT; } /* @@ -571,8 +562,8 @@ static inline int simulate_rdhwr(struct pt_regs *regs) struct thread_info *ti = task_thread_info(current); unsigned int opcode; - if (unlikely(get_insn_opcode(regs, &opcode))) - return -EFAULT; + if (get_user(opcode, (unsigned int __user *) exception_epc(regs))) + goto out_sigsegv; if (unlikely(compute_return_epc(regs))) return -EFAULT; @@ -591,6 +582,10 @@ static inline int simulate_rdhwr(struct pt_regs *regs) /* Not ours. */ return -EFAULT; + +out_sigsegv: + force_sig(SIGSEGV, current); + return -EFAULT; } asmlinkage void do_ov(struct pt_regs *regs) @@ -676,8 +671,8 @@ asmlinkage void do_bp(struct pt_regs *regs) die_if_kernel("Break instruction in kernel code", regs); - if (get_insn_opcode(regs, &opcode)) - return; + if (get_user(opcode, (unsigned int __user *) exception_epc(regs))) + goto out_sigsegv; /* * There is the ancient bug in the MIPS assemblers that the break @@ -710,6 +705,9 @@ asmlinkage void do_bp(struct pt_regs *regs) default: force_sig(SIGTRAP, current); } + +out_sigsegv: + force_sig(SIGSEGV, current); } asmlinkage void do_tr(struct pt_regs *regs) @@ -719,8 +717,8 @@ asmlinkage void do_tr(struct pt_regs *regs) die_if_kernel("Trap instruction in kernel code", regs); - if (get_insn_opcode(regs, &opcode)) - return; + if (get_user(opcode, (unsigned int __user *) exception_epc(regs))) + goto out_sigsegv; /* Immediate versions don't provide a code. */ if (!(opcode & OPCODE)) @@ -747,6 +745,9 @@ asmlinkage void do_tr(struct pt_regs *regs) default: force_sig(SIGTRAP, current); } + +out_sigsegv: + force_sig(SIGSEGV, current); } asmlinkage void do_ri(struct pt_regs *regs) -- cgit v1.1 From 0550d9d13e02b30efa117d47fcadea450bb23d23 Mon Sep 17 00:00:00 2001 From: Atsushi Nemoto Date: Tue, 22 Aug 2006 21:15:47 +0900 Subject: [MIPS] Remove redundant r4k_blast_icache() calls r4k_flush_cache_all() and r4k_flush_cache_mm() case: these are noop if the CPU did not have dc_aliases. It would mean we do not need to care about icache here. r4k_flush_cache_range case: if r4k_flush_cache_mm() did not need to care about icache, it would be same for this function. Signed-off-by: Atsushi Nemoto Signed-off-by: Ralf Baechle --- arch/mips/mm/c-r4k.c | 12 ++++-------- 1 file changed, 4 insertions(+), 8 deletions(-) (limited to 'arch/mips') diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c index cc895da..0138cb2 100644 --- a/arch/mips/mm/c-r4k.c +++ b/arch/mips/mm/c-r4k.c @@ -323,7 +323,6 @@ static void __init r4k_blast_scache_setup(void) static inline void local_r4k_flush_cache_all(void * args) { r4k_blast_dcache(); - r4k_blast_icache(); } static void r4k_flush_cache_all(void) @@ -359,21 +358,19 @@ static void r4k___flush_cache_all(void) static inline void local_r4k_flush_cache_range(void * args) { struct vm_area_struct *vma = args; - int exec; if (!(cpu_context(smp_processor_id(), vma->vm_mm))) return; - exec = vma->vm_flags & VM_EXEC; - if (cpu_has_dc_aliases || exec) - r4k_blast_dcache(); - if (exec) - r4k_blast_icache(); + r4k_blast_dcache(); } static void r4k_flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end) { + if (!cpu_has_dc_aliases) + return; + r4k_on_each_cpu(local_r4k_flush_cache_range, vma, 1, 1); } @@ -385,7 +382,6 @@ static inline void local_r4k_flush_cache_mm(void * args) return; r4k_blast_dcache(); - r4k_blast_icache(); /* * Kludge alert. For obscure reasons R4000SC and R4400SC go nuts if we -- cgit v1.1 From 617667ba724d46ffeccb88ee99e1379f29b0bfa7 Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Thu, 30 Nov 2006 01:14:48 +0000 Subject: [MIPS] Avoid dupliate D-cache flush on R400C / R4400 SC and MC variants. Signed-off-by: Ralf Baechle --- arch/mips/mm/c-r4k.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) (limited to 'arch/mips') diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c index 0138cb2..df04a31 100644 --- a/arch/mips/mm/c-r4k.c +++ b/arch/mips/mm/c-r4k.c @@ -381,17 +381,21 @@ static inline void local_r4k_flush_cache_mm(void * args) if (!cpu_context(smp_processor_id(), mm)) return; - r4k_blast_dcache(); - /* * Kludge alert. For obscure reasons R4000SC and R4400SC go nuts if we * only flush the primary caches but R10000 and R12000 behave sane ... + * R4000SC and R4400SC indexed S-cache ops also invalidate primary + * caches, so we can bail out early. */ if (current_cpu_data.cputype == CPU_R4000SC || current_cpu_data.cputype == CPU_R4000MC || current_cpu_data.cputype == CPU_R4400SC || - current_cpu_data.cputype == CPU_R4400MC) + current_cpu_data.cputype == CPU_R4400MC) { r4k_blast_scache(); + return; + } + + r4k_blast_dcache(); } static void r4k_flush_cache_mm(struct mm_struct *mm) -- cgit v1.1 From 187933f23679c413706030aefad9e85e79164c44 Mon Sep 17 00:00:00 2001 From: Atsushi Nemoto Date: Wed, 25 Oct 2006 23:57:04 +0900 Subject: [MIPS] do_IRQ cleanup Now we have both function and macro version of do_IRQ() and the former is used only by DEC and non-preemptive kernel. This patch makes everyone use the macro version and removes the function version. Signed-off-by: Atsushi Nemoto Signed-off-by: Ralf Baechle --- arch/mips/dec/int-handler.S | 2 +- arch/mips/dec/setup.c | 6 ++++++ arch/mips/kernel/irq.c | 19 ------------------- 3 files changed, 7 insertions(+), 20 deletions(-) (limited to 'arch/mips') diff --git a/arch/mips/dec/int-handler.S b/arch/mips/dec/int-handler.S index 31dd47d..b251ef8 100644 --- a/arch/mips/dec/int-handler.S +++ b/arch/mips/dec/int-handler.S @@ -267,7 +267,7 @@ handle_it: LONG_L s0, TI_REGS($28) LONG_S sp, TI_REGS($28) PTR_LA ra, ret_from_irq - j do_IRQ + j dec_irq_dispatch nop #ifdef CONFIG_32BIT diff --git a/arch/mips/dec/setup.c b/arch/mips/dec/setup.c index 6b7481e..d34032a 100644 --- a/arch/mips/dec/setup.c +++ b/arch/mips/dec/setup.c @@ -761,3 +761,9 @@ void __init arch_init_irq(void) if (dec_interrupt[DEC_IRQ_HALT] >= 0) setup_irq(dec_interrupt[DEC_IRQ_HALT], &haltirq); } + +asmlinkage unsigned int dec_irq_dispatch(unsigned int irq) +{ + do_IRQ(irq); + return 0; +} diff --git a/arch/mips/kernel/irq.c b/arch/mips/kernel/irq.c index e997c94..b339798 100644 --- a/arch/mips/kernel/irq.c +++ b/arch/mips/kernel/irq.c @@ -88,25 +88,6 @@ atomic_t irq_err_count; unsigned long irq_hwmask[NR_IRQS]; #endif /* CONFIG_MIPS_MT_SMTC */ -#undef do_IRQ - -/* - * do_IRQ handles all normal device IRQ's (the special - * SMP cross-CPU interrupts have their own specific - * handlers). - */ -asmlinkage unsigned int do_IRQ(unsigned int irq) -{ - irq_enter(); - - __DO_IRQ_SMTC_HOOK(); - __do_IRQ(irq); - - irq_exit(); - - return 1; -} - /* * Generic, controller-independent functions: */ -- cgit v1.1 From 005985609ff72df3257fde6b29aa9d71342c2a6b Mon Sep 17 00:00:00 2001 From: Atsushi Nemoto Date: Sun, 12 Nov 2006 00:10:28 +0900 Subject: [MIPS] mips HPT cleanup: make clocksource_mips public Make clocksource_mips public and get rid of mips_hpt_read, mips_hpt_mask. Signed-off-by: Atsushi Nemoto Signed-off-by: Ralf Baechle --- arch/mips/dec/time.c | 4 ++-- arch/mips/jmr3927/rbhma3100/setup.c | 4 ++-- arch/mips/kernel/time.c | 42 ++++++++++++++----------------------- arch/mips/sgi-ip27/ip27-timer.c | 4 ++-- arch/mips/sibyte/bcm1480/time.c | 4 ++-- arch/mips/sibyte/sb1250/time.c | 8 +++---- 6 files changed, 28 insertions(+), 38 deletions(-) (limited to 'arch/mips') diff --git a/arch/mips/dec/time.c b/arch/mips/dec/time.c index 69e424e..8b7e0c1 100644 --- a/arch/mips/dec/time.c +++ b/arch/mips/dec/time.c @@ -151,7 +151,7 @@ static void dec_timer_ack(void) CMOS_READ(RTC_REG_C); /* Ack the RTC interrupt. */ } -static unsigned int dec_ioasic_hpt_read(void) +static cycle_t dec_ioasic_hpt_read(void) { /* * The free-running counter is 32-bit which is good for about @@ -171,7 +171,7 @@ void __init dec_time_init(void) if (!cpu_has_counter && IOASIC) /* For pre-R4k systems we use the I/O ASIC's counter. */ - mips_hpt_read = dec_ioasic_hpt_read; + clocksource_mips.read = dec_ioasic_hpt_read; /* Set up the rate of periodic DS1287 interrupts. */ CMOS_WRITE(RTC_REF_CLCK_32KHZ | (16 - __ffs(HZ)), RTC_REG_A); diff --git a/arch/mips/jmr3927/rbhma3100/setup.c b/arch/mips/jmr3927/rbhma3100/setup.c index 16e5dfe..138f25e 100644 --- a/arch/mips/jmr3927/rbhma3100/setup.c +++ b/arch/mips/jmr3927/rbhma3100/setup.c @@ -170,7 +170,7 @@ static void jmr3927_machine_power_off(void) while (1); } -static unsigned int jmr3927_hpt_read(void) +static cycle_t jmr3927_hpt_read(void) { /* We assume this function is called xtime_lock held. */ return jiffies * (JMR3927_TIMER_CLK / HZ) + jmr3927_tmrptr->trr; @@ -182,7 +182,7 @@ extern void rtc_ds1742_init(unsigned long base); #endif static void __init jmr3927_time_init(void) { - mips_hpt_read = jmr3927_hpt_read; + clocksource_mips.read = jmr3927_hpt_read; mips_hpt_frequency = JMR3927_TIMER_CLK; #ifdef USE_RTC_DS1742 if (jmr3927_have_nvram()) { diff --git a/arch/mips/kernel/time.c b/arch/mips/kernel/time.c index 111d1ba..11aab6d 100644 --- a/arch/mips/kernel/time.c +++ b/arch/mips/kernel/time.c @@ -11,7 +11,6 @@ * Free Software Foundation; either version 2 of the License, or (at your * option) any later version. */ -#include #include #include #include @@ -83,7 +82,7 @@ static void null_timer_ack(void) { /* nothing */ } /* * Null high precision timer functions for systems lacking one. */ -static unsigned int null_hpt_read(void) +static cycle_t null_hpt_read(void) { return 0; } @@ -112,7 +111,7 @@ static void c0_timer_ack(void) /* * High precision timer functions for a R4k-compatible timer. */ -static unsigned int c0_hpt_read(void) +static cycle_t c0_hpt_read(void) { return read_c0_count(); } @@ -126,8 +125,6 @@ static void __init c0_hpt_timer_init(void) int (*mips_timer_state)(void); void (*mips_timer_ack)(void); -unsigned int (*mips_hpt_read)(void); -unsigned int mips_hpt_mask = 0xffffffff; /* last time when xtime and rtc are sync'ed up */ static long last_rtc_update; @@ -269,8 +266,7 @@ static struct irqaction timer_irqaction = { static unsigned int __init calibrate_hpt(void) { - u64 frequency; - u32 hpt_start, hpt_end, hpt_count, hz; + cycle_t frequency, hpt_start, hpt_end, hpt_count, hz; const int loops = HZ / 10; int log_2_loops = 0; @@ -296,28 +292,23 @@ static unsigned int __init calibrate_hpt(void) * during the calculated number of periods between timer * interrupts. */ - hpt_start = mips_hpt_read(); + hpt_start = clocksource_mips.read(); do { while (mips_timer_state()); while (!mips_timer_state()); } while (--i); - hpt_end = mips_hpt_read(); + hpt_end = clocksource_mips.read(); - hpt_count = (hpt_end - hpt_start) & mips_hpt_mask; + hpt_count = (hpt_end - hpt_start) & clocksource_mips.mask; hz = HZ; - frequency = (u64)hpt_count * (u64)hz; + frequency = hpt_count * hz; return frequency >> log_2_loops; } -static cycle_t read_mips_hpt(void) -{ - return (cycle_t)mips_hpt_read(); -} - -static struct clocksource clocksource_mips = { +struct clocksource clocksource_mips = { .name = "MIPS", - .read = read_mips_hpt, + .mask = 0xffffffff, .is_continuous = 1, }; @@ -326,7 +317,7 @@ static void __init init_mips_clocksource(void) u64 temp; u32 shift; - if (!mips_hpt_frequency || mips_hpt_read == null_hpt_read) + if (!mips_hpt_frequency || clocksource_mips.read == null_hpt_read) return; /* Calclate a somewhat reasonable rating value */ @@ -340,7 +331,6 @@ static void __init init_mips_clocksource(void) } clocksource_mips.shift = shift; clocksource_mips.mult = (u32)temp; - clocksource_mips.mask = mips_hpt_mask; clocksource_register(&clocksource_mips); } @@ -360,19 +350,19 @@ void __init time_init(void) -xtime.tv_sec, -xtime.tv_nsec); /* Choose appropriate high precision timer routines. */ - if (!cpu_has_counter && !mips_hpt_read) + if (!cpu_has_counter && !clocksource_mips.read) /* No high precision timer -- sorry. */ - mips_hpt_read = null_hpt_read; + clocksource_mips.read = null_hpt_read; else if (!mips_hpt_frequency && !mips_timer_state) { /* A high precision timer of unknown frequency. */ - if (!mips_hpt_read) + if (!clocksource_mips.read) /* No external high precision timer -- use R4k. */ - mips_hpt_read = c0_hpt_read; + clocksource_mips.read = c0_hpt_read; } else { /* We know counter frequency. Or we can get it. */ - if (!mips_hpt_read) { + if (!clocksource_mips.read) { /* No external high precision timer -- use R4k. */ - mips_hpt_read = c0_hpt_read; + clocksource_mips.read = c0_hpt_read; if (!mips_timer_state) { /* No external timer interrupt -- use R4k. */ diff --git a/arch/mips/sgi-ip27/ip27-timer.c b/arch/mips/sgi-ip27/ip27-timer.c index e5441c3..7d36172 100644 --- a/arch/mips/sgi-ip27/ip27-timer.c +++ b/arch/mips/sgi-ip27/ip27-timer.c @@ -223,14 +223,14 @@ void __init plat_timer_setup(struct irqaction *irq) setup_irq(irqno, &rt_irqaction); } -static unsigned int ip27_hpt_read(void) +static cycle_t ip27_hpt_read(void) { return REMOTE_HUB_L(cputonasid(0), PI_RT_COUNT); } void __init ip27_time_init(void) { - mips_hpt_read = ip27_hpt_read; + clocksource_mips.read = ip27_hpt_read; mips_hpt_frequency = CYCLES_PER_SEC; xtime.tv_sec = get_m48t35_time(); xtime.tv_nsec = 0; diff --git a/arch/mips/sibyte/bcm1480/time.c b/arch/mips/sibyte/bcm1480/time.c index 03d5822..6f3f71b 100644 --- a/arch/mips/sibyte/bcm1480/time.c +++ b/arch/mips/sibyte/bcm1480/time.c @@ -117,7 +117,7 @@ void bcm1480_timer_interrupt(void) } } -static unsigned int bcm1480_hpt_read(void) +static cycle_t bcm1480_hpt_read(void) { /* We assume this function is called xtime_lock held. */ unsigned long count = @@ -127,6 +127,6 @@ static unsigned int bcm1480_hpt_read(void) void __init bcm1480_hpt_setup(void) { - mips_hpt_read = bcm1480_hpt_read; + clocksource_mips.read = bcm1480_hpt_read; mips_hpt_frequency = BCM1480_HPT_VALUE; } diff --git a/arch/mips/sibyte/sb1250/time.c b/arch/mips/sibyte/sb1250/time.c index bcb74f2..2efffe1 100644 --- a/arch/mips/sibyte/sb1250/time.c +++ b/arch/mips/sibyte/sb1250/time.c @@ -51,7 +51,7 @@ extern int sb1250_steal_irq(int irq); -static unsigned int sb1250_hpt_read(void); +static cycle_t sb1250_hpt_read(void); void __init sb1250_hpt_setup(void) { @@ -66,8 +66,8 @@ void __init sb1250_hpt_setup(void) IOADDR(A_SCD_TIMER_REGISTER(SB1250_HPT_NUM, R_SCD_TIMER_CFG))); mips_hpt_frequency = V_SCD_TIMER_FREQ; - mips_hpt_read = sb1250_hpt_read; - mips_hpt_mask = M_SCD_TIMER_INIT; + clocksource_mips.read = sb1250_hpt_read; + clocksource_mips.mask = M_SCD_TIMER_INIT; } } @@ -143,7 +143,7 @@ void sb1250_timer_interrupt(void) * The HPT is free running from SB1250_HPT_VALUE down to 0 then starts over * again. */ -static unsigned int sb1250_hpt_read(void) +static cycle_t sb1250_hpt_read(void) { unsigned int count; -- cgit v1.1 From 63dc68a8cf60cb110b147dab1704d990808b39e2 Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Mon, 16 Oct 2006 01:38:50 +0100 Subject: [MIPS] Use conditional traps for BUG_ON on MIPS II and better. This shaves of around 4kB and a few cycles for the average kernel that has CONFIG_BUG enabled. Signed-off-by: Ralf Baechle --- arch/mips/kernel/traps.c | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) (limited to 'arch/mips') diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c index 0ae19e1..2a932cad 100644 --- a/arch/mips/kernel/traps.c +++ b/arch/mips/kernel/traps.c @@ -669,8 +669,6 @@ asmlinkage void do_bp(struct pt_regs *regs) unsigned int opcode, bcode; siginfo_t info; - die_if_kernel("Break instruction in kernel code", regs); - if (get_user(opcode, (unsigned int __user *) exception_epc(regs))) goto out_sigsegv; @@ -693,6 +691,7 @@ asmlinkage void do_bp(struct pt_regs *regs) switch (bcode) { case BRK_OVERFLOW << 10: case BRK_DIVZERO << 10: + die_if_kernel("Break instruction in kernel code", regs); if (bcode == (BRK_DIVZERO << 10)) info.si_code = FPE_INTDIV; else @@ -702,7 +701,11 @@ asmlinkage void do_bp(struct pt_regs *regs) info.si_addr = (void __user *) regs->cp0_epc; force_sig_info(SIGFPE, &info, current); break; + case BRK_BUG: + die("Kernel bug detected", regs); + break; default: + die_if_kernel("Break instruction in kernel code", regs); force_sig(SIGTRAP, current); } @@ -715,8 +718,6 @@ asmlinkage void do_tr(struct pt_regs *regs) unsigned int opcode, tcode = 0; siginfo_t info; - die_if_kernel("Trap instruction in kernel code", regs); - if (get_user(opcode, (unsigned int __user *) exception_epc(regs))) goto out_sigsegv; @@ -733,6 +734,7 @@ asmlinkage void do_tr(struct pt_regs *regs) switch (tcode) { case BRK_OVERFLOW: case BRK_DIVZERO: + die_if_kernel("Trap instruction in kernel code", regs); if (tcode == BRK_DIVZERO) info.si_code = FPE_INTDIV; else @@ -742,7 +744,11 @@ asmlinkage void do_tr(struct pt_regs *regs) info.si_addr = (void __user *) regs->cp0_epc; force_sig_info(SIGFPE, &info, current); break; + case BRK_BUG: + die("Kernel bug detected", regs); + break; default: + die_if_kernel("Trap instruction in kernel code", regs); force_sig(SIGTRAP, current); } -- cgit v1.1 From aa414dff4f7bef29457592414551becdca72dd6b Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Thu, 30 Nov 2006 01:14:51 +0000 Subject: [MIPS] Remove duplicate ISA DMA code for 0 DMA channel case. Signed-off-by: Ralf Baechle --- arch/mips/Kconfig | 11 ++++++----- arch/mips/kernel/Makefile | 1 - arch/mips/kernel/dma-no-isa.c | 28 ---------------------------- 3 files changed, 6 insertions(+), 34 deletions(-) delete mode 100644 arch/mips/kernel/dma-no-isa.c (limited to 'arch/mips') diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index c0da0ff..9614367 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -266,8 +266,8 @@ config MIPS_MALTA select BOOT_ELF32 select HAVE_STD_PC_SERIAL_PORT select DMA_NONCOHERENT - select IRQ_CPU select GENERIC_ISA_DMA + select IRQ_CPU select HW_HAS_PCI select I8259 select MIPS_BOARDS_GEN @@ -534,7 +534,7 @@ config SGI_IP22 select HW_HAS_EISA select IP22_CPU_SCACHE select IRQ_CPU - select NO_ISA if ISA + select GENERIC_ISA_DMA_SUPPORT_BROKEN select SWAP_IO_SPACE select SYS_HAS_CPU_R4X00 select SYS_HAS_CPU_R5000 @@ -881,6 +881,9 @@ config MIPS_NILE4 config MIPS_DISABLE_OBSOLETE_IDE bool +config GENERIC_ISA_DMA_SUPPORT_BROKEN + bool + # # Endianess selection. Suffiently obscure so many users don't know what to # answer,so we try hard to limit the available choices. Also the use of a @@ -1852,13 +1855,11 @@ source "drivers/pci/Kconfig" config ISA bool -config NO_ISA - bool - config EISA bool "EISA support" depends on HW_HAS_EISA select ISA + select GENERIC_ISA_DMA ---help--- The Extended Industry Standard Architecture (EISA) bus was developed as an open alternative to the IBM MicroChannel bus. diff --git a/arch/mips/kernel/Makefile b/arch/mips/kernel/Makefile index f35b739..bbbb8d7 100644 --- a/arch/mips/kernel/Makefile +++ b/arch/mips/kernel/Makefile @@ -45,7 +45,6 @@ obj-$(CONFIG_MIPS_APSP_KSPD) += kspd.o obj-$(CONFIG_MIPS_VPE_LOADER) += vpe.o obj-$(CONFIG_MIPS_VPE_APSP_API) += rtlx.o -obj-$(CONFIG_NO_ISA) += dma-no-isa.o obj-$(CONFIG_I8259) += i8259.o obj-$(CONFIG_IRQ_CPU) += irq_cpu.o obj-$(CONFIG_IRQ_CPU_RM7K) += irq-rm7000.o diff --git a/arch/mips/kernel/dma-no-isa.c b/arch/mips/kernel/dma-no-isa.c deleted file mode 100644 index 6df8b07..0000000 --- a/arch/mips/kernel/dma-no-isa.c +++ /dev/null @@ -1,28 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2004 by Ralf Baechle - * - * Dummy ISA DMA functions for systems that don't have ISA but share drivers - * with ISA such as legacy free PCI. - */ -#include -#include -#include - -DEFINE_SPINLOCK(dma_spin_lock); - -int request_dma(unsigned int dmanr, const char * device_id) -{ - return -EINVAL; -} - -void free_dma(unsigned int dmanr) -{ -} - -EXPORT_SYMBOL(dma_spin_lock); -EXPORT_SYMBOL(request_dma); -EXPORT_SYMBOL(free_dma); -- cgit v1.1 From 3cb2fccc5f48a4d6269dfd00b4db570fca2a04d5 Mon Sep 17 00:00:00 2001 From: Matt LaPlante Date: Thu, 30 Nov 2006 05:22:59 +0100 Subject: Fix misc Kconfig typos Fix various Kconfig typos. Signed-off-by: Matt LaPlante Acked-by: Randy Dunlap Signed-off-by: Adrian Bunk --- arch/mips/Kconfig | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/mips') diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 1443024..22bb540 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -865,7 +865,7 @@ config MIPS_DISABLE_OBSOLETE_IDE bool # -# Endianess selection. Suffiently obscure so many users don't know what to +# Endianess selection. Sufficiently obscure so many users don't know what to # answer,so we try hard to limit the available choices. Also the use of a # choice statement should be more obvious to the user. # @@ -874,7 +874,7 @@ choice help Some MIPS machines can be configured for either little or big endian byte order. These modes require different kernels and a different - Linux distribution. In general there is one prefered byteorder for a + Linux distribution. In general there is one preferred byteorder for a particular system but some systems are just as commonly used in the one or the other endianess. -- cgit v1.1 From 8e3d8433d8c22ca6c42cba4a67d300c39aae7822 Mon Sep 17 00:00:00 2001 From: Al Viro Date: Tue, 14 Nov 2006 21:18:18 -0800 Subject: [NET]: MIPS checksum annotations and cleanups. * sanitize prototypes, annotate * kill shift-by-16 in checksum calculations * htons->shift in l-e checksum calculations Signed-off-by: Al Viro Signed-off-by: David S. Miller --- arch/mips/lib/csum_partial_copy.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'arch/mips') diff --git a/arch/mips/lib/csum_partial_copy.c b/arch/mips/lib/csum_partial_copy.c index 6e9f366..1720f2c 100644 --- a/arch/mips/lib/csum_partial_copy.c +++ b/arch/mips/lib/csum_partial_copy.c @@ -16,8 +16,8 @@ /* * copy while checksumming, otherwise like csum_partial */ -unsigned int csum_partial_copy_nocheck(const unsigned char *src, - unsigned char *dst, int len, unsigned int sum) +__wsum csum_partial_copy_nocheck(const void *src, + void *dst, int len, __wsum sum) { /* * It's 2:30 am and I don't feel like doing it real ... @@ -33,8 +33,8 @@ unsigned int csum_partial_copy_nocheck(const unsigned char *src, * Copy from userspace and compute checksum. If we catch an exception * then zero the rest of the buffer. */ -unsigned int csum_partial_copy_from_user (const unsigned char __user *src, - unsigned char *dst, int len, unsigned int sum, int *err_ptr) +__wsum csum_partial_copy_from_user (const void __user *src, + void *dst, int len, __wsum sum, int *err_ptr) { int missing; -- cgit v1.1 From 05e4396651ca1cac51d8da9ff4992741c9dc1e39 Mon Sep 17 00:00:00 2001 From: Atsushi Nemoto Date: Tue, 7 Nov 2006 18:02:44 +0900 Subject: [MIPS] Use SYSVIPC_COMPAT to fix various problems on N32 N32 SysV IPC system calls should use 32-bit compatible code. arch/mips/kernel/linux32.c have similar compatible code for O32, but ipc/compat.c seems more complete. We can use it for both N32 and O32. This patch should fix these problems (and other possible problems): http://www.linux-mips.org/cgi-bin/mesg.cgi?a=linux-mips&i=1149188824.6986.6.camel%40diimka-laptop http://www.linux-mips.org/cgi-bin/mesg.cgi?a=linux-mips&i=44C6B829.8050508%40caviumnetworks.com Signed-off-by: Atsushi Nemoto Signed-off-by: Ralf Baechle --- arch/mips/Kconfig | 5 + arch/mips/kernel/linux32.c | 578 ++--------------------------------------- arch/mips/kernel/scall64-n32.S | 14 +- 3 files changed, 35 insertions(+), 562 deletions(-) (limited to 'arch/mips') diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 27f83e6..2308c8e 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -1940,6 +1940,11 @@ config COMPAT depends on MIPS32_COMPAT default y +config SYSVIPC_COMPAT + bool + depends on COMPAT && SYSVIPC + default y + config MIPS32_O32 bool "Kernel support for o32 binaries" depends on MIPS32_COMPAT diff --git a/arch/mips/kernel/linux32.c b/arch/mips/kernel/linux32.c index 7a3ebbe..b061c9a 100644 --- a/arch/mips/kernel/linux32.c +++ b/arch/mips/kernel/linux32.c @@ -382,531 +382,6 @@ asmlinkage int sys32_sched_rr_get_interval(compat_pid_t pid, return ret; } -struct msgbuf32 { s32 mtype; char mtext[1]; }; - -struct ipc_perm32 -{ - key_t key; - __compat_uid_t uid; - __compat_gid_t gid; - __compat_uid_t cuid; - __compat_gid_t cgid; - compat_mode_t mode; - unsigned short seq; -}; - -struct ipc64_perm32 { - key_t key; - __compat_uid_t uid; - __compat_gid_t gid; - __compat_uid_t cuid; - __compat_gid_t cgid; - compat_mode_t mode; - unsigned short seq; - unsigned short __pad1; - unsigned int __unused1; - unsigned int __unused2; -}; - -struct semid_ds32 { - struct ipc_perm32 sem_perm; /* permissions .. see ipc.h */ - compat_time_t sem_otime; /* last semop time */ - compat_time_t sem_ctime; /* last change time */ - u32 sem_base; /* ptr to first semaphore in array */ - u32 sem_pending; /* pending operations to be processed */ - u32 sem_pending_last; /* last pending operation */ - u32 undo; /* undo requests on this array */ - unsigned short sem_nsems; /* no. of semaphores in array */ -}; - -struct semid64_ds32 { - struct ipc64_perm32 sem_perm; - compat_time_t sem_otime; - compat_time_t sem_ctime; - unsigned int sem_nsems; - unsigned int __unused1; - unsigned int __unused2; -}; - -struct msqid_ds32 -{ - struct ipc_perm32 msg_perm; - u32 msg_first; - u32 msg_last; - compat_time_t msg_stime; - compat_time_t msg_rtime; - compat_time_t msg_ctime; - u32 wwait; - u32 rwait; - unsigned short msg_cbytes; - unsigned short msg_qnum; - unsigned short msg_qbytes; - compat_ipc_pid_t msg_lspid; - compat_ipc_pid_t msg_lrpid; -}; - -struct msqid64_ds32 { - struct ipc64_perm32 msg_perm; - compat_time_t msg_stime; - unsigned int __unused1; - compat_time_t msg_rtime; - unsigned int __unused2; - compat_time_t msg_ctime; - unsigned int __unused3; - unsigned int msg_cbytes; - unsigned int msg_qnum; - unsigned int msg_qbytes; - compat_pid_t msg_lspid; - compat_pid_t msg_lrpid; - unsigned int __unused4; - unsigned int __unused5; -}; - -struct shmid_ds32 { - struct ipc_perm32 shm_perm; - int shm_segsz; - compat_time_t shm_atime; - compat_time_t shm_dtime; - compat_time_t shm_ctime; - compat_ipc_pid_t shm_cpid; - compat_ipc_pid_t shm_lpid; - unsigned short shm_nattch; -}; - -struct shmid64_ds32 { - struct ipc64_perm32 shm_perm; - compat_size_t shm_segsz; - compat_time_t shm_atime; - compat_time_t shm_dtime; - compat_time_t shm_ctime; - compat_pid_t shm_cpid; - compat_pid_t shm_lpid; - unsigned int shm_nattch; - unsigned int __unused1; - unsigned int __unused2; -}; - -struct ipc_kludge32 { - u32 msgp; - s32 msgtyp; -}; - -static int -do_sys32_semctl(int first, int second, int third, void __user *uptr) -{ - union semun fourth; - u32 pad; - int err, err2; - struct semid64_ds s; - mm_segment_t old_fs; - - if (!uptr) - return -EINVAL; - err = -EFAULT; - if (get_user (pad, (u32 __user *)uptr)) - return err; - if ((third & ~IPC_64) == SETVAL) - fourth.val = (int)pad; - else - fourth.__pad = (void __user *)A(pad); - switch (third & ~IPC_64) { - case IPC_INFO: - case IPC_RMID: - case IPC_SET: - case SEM_INFO: - case GETVAL: - case GETPID: - case GETNCNT: - case GETZCNT: - case GETALL: - case SETVAL: - case SETALL: - err = sys_semctl (first, second, third, fourth); - break; - - case IPC_STAT: - case SEM_STAT: - fourth.__pad = (struct semid64_ds __user *)&s; - old_fs = get_fs(); - set_fs(KERNEL_DS); - err = sys_semctl(first, second, third | IPC_64, fourth); - set_fs(old_fs); - - if (third & IPC_64) { - struct semid64_ds32 __user *usp64 = (struct semid64_ds32 __user *) A(pad); - - if (!access_ok(VERIFY_WRITE, usp64, sizeof(*usp64))) { - err = -EFAULT; - break; - } - err2 = __put_user(s.sem_perm.key, &usp64->sem_perm.key); - err2 |= __put_user(s.sem_perm.uid, &usp64->sem_perm.uid); - err2 |= __put_user(s.sem_perm.gid, &usp64->sem_perm.gid); - err2 |= __put_user(s.sem_perm.cuid, &usp64->sem_perm.cuid); - err2 |= __put_user(s.sem_perm.cgid, &usp64->sem_perm.cgid); - err2 |= __put_user(s.sem_perm.mode, &usp64->sem_perm.mode); - err2 |= __put_user(s.sem_perm.seq, &usp64->sem_perm.seq); - err2 |= __put_user(s.sem_otime, &usp64->sem_otime); - err2 |= __put_user(s.sem_ctime, &usp64->sem_ctime); - err2 |= __put_user(s.sem_nsems, &usp64->sem_nsems); - } else { - struct semid_ds32 __user *usp32 = (struct semid_ds32 __user *) A(pad); - - if (!access_ok(VERIFY_WRITE, usp32, sizeof(*usp32))) { - err = -EFAULT; - break; - } - err2 = __put_user(s.sem_perm.key, &usp32->sem_perm.key); - err2 |= __put_user(s.sem_perm.uid, &usp32->sem_perm.uid); - err2 |= __put_user(s.sem_perm.gid, &usp32->sem_perm.gid); - err2 |= __put_user(s.sem_perm.cuid, &usp32->sem_perm.cuid); - err2 |= __put_user(s.sem_perm.cgid, &usp32->sem_perm.cgid); - err2 |= __put_user(s.sem_perm.mode, &usp32->sem_perm.mode); - err2 |= __put_user(s.sem_perm.seq, &usp32->sem_perm.seq); - err2 |= __put_user(s.sem_otime, &usp32->sem_otime); - err2 |= __put_user(s.sem_ctime, &usp32->sem_ctime); - err2 |= __put_user(s.sem_nsems, &usp32->sem_nsems); - } - if (err2) - err = -EFAULT; - break; - - default: - err = - EINVAL; - break; - } - - return err; -} - -static int -do_sys32_msgsnd (int first, int second, int third, void __user *uptr) -{ - struct msgbuf32 __user *up = (struct msgbuf32 __user *)uptr; - struct msgbuf *p; - mm_segment_t old_fs; - int err; - - if (second < 0) - return -EINVAL; - p = kmalloc (second + sizeof (struct msgbuf) - + 4, GFP_USER); - if (!p) - return -ENOMEM; - err = get_user (p->mtype, &up->mtype); - if (err) - goto out; - err |= __copy_from_user (p->mtext, &up->mtext, second); - if (err) - goto out; - old_fs = get_fs (); - set_fs (KERNEL_DS); - err = sys_msgsnd (first, (struct msgbuf __user *)p, second, third); - set_fs (old_fs); -out: - kfree (p); - - return err; -} - -static int -do_sys32_msgrcv (int first, int second, int msgtyp, int third, - int version, void __user *uptr) -{ - struct msgbuf32 __user *up; - struct msgbuf *p; - mm_segment_t old_fs; - int err; - - if (!version) { - struct ipc_kludge32 __user *uipck = (struct ipc_kludge32 __user *)uptr; - struct ipc_kludge32 ipck; - - err = -EINVAL; - if (!uptr) - goto out; - err = -EFAULT; - if (copy_from_user (&ipck, uipck, sizeof (struct ipc_kludge32))) - goto out; - uptr = (void __user *)AA(ipck.msgp); - msgtyp = ipck.msgtyp; - } - - if (second < 0) - return -EINVAL; - err = -ENOMEM; - p = kmalloc (second + sizeof (struct msgbuf) + 4, GFP_USER); - if (!p) - goto out; - old_fs = get_fs (); - set_fs (KERNEL_DS); - err = sys_msgrcv (first, (struct msgbuf __user *)p, second + 4, msgtyp, third); - set_fs (old_fs); - if (err < 0) - goto free_then_out; - up = (struct msgbuf32 __user *)uptr; - if (put_user (p->mtype, &up->mtype) || - __copy_to_user (&up->mtext, p->mtext, err)) - err = -EFAULT; -free_then_out: - kfree (p); -out: - return err; -} - -static int -do_sys32_msgctl (int first, int second, void __user *uptr) -{ - int err = -EINVAL, err2; - struct msqid64_ds m; - struct msqid_ds32 __user *up32 = (struct msqid_ds32 __user *)uptr; - struct msqid64_ds32 __user *up64 = (struct msqid64_ds32 __user *)uptr; - mm_segment_t old_fs; - - switch (second & ~IPC_64) { - case IPC_INFO: - case IPC_RMID: - case MSG_INFO: - err = sys_msgctl (first, second, (struct msqid_ds __user *)uptr); - break; - - case IPC_SET: - if (second & IPC_64) { - if (!access_ok(VERIFY_READ, up64, sizeof(*up64))) { - err = -EFAULT; - break; - } - err = __get_user(m.msg_perm.uid, &up64->msg_perm.uid); - err |= __get_user(m.msg_perm.gid, &up64->msg_perm.gid); - err |= __get_user(m.msg_perm.mode, &up64->msg_perm.mode); - err |= __get_user(m.msg_qbytes, &up64->msg_qbytes); - } else { - if (!access_ok(VERIFY_READ, up32, sizeof(*up32))) { - err = -EFAULT; - break; - } - err = __get_user(m.msg_perm.uid, &up32->msg_perm.uid); - err |= __get_user(m.msg_perm.gid, &up32->msg_perm.gid); - err |= __get_user(m.msg_perm.mode, &up32->msg_perm.mode); - err |= __get_user(m.msg_qbytes, &up32->msg_qbytes); - } - if (err) - break; - old_fs = get_fs(); - set_fs(KERNEL_DS); - err = sys_msgctl(first, second | IPC_64, (struct msqid_ds __user *)&m); - set_fs(old_fs); - break; - - case IPC_STAT: - case MSG_STAT: - old_fs = get_fs(); - set_fs(KERNEL_DS); - err = sys_msgctl(first, second | IPC_64, (struct msqid_ds __user *)&m); - set_fs(old_fs); - if (second & IPC_64) { - if (!access_ok(VERIFY_WRITE, up64, sizeof(*up64))) { - err = -EFAULT; - break; - } - err2 = __put_user(m.msg_perm.key, &up64->msg_perm.key); - err2 |= __put_user(m.msg_perm.uid, &up64->msg_perm.uid); - err2 |= __put_user(m.msg_perm.gid, &up64->msg_perm.gid); - err2 |= __put_user(m.msg_perm.cuid, &up64->msg_perm.cuid); - err2 |= __put_user(m.msg_perm.cgid, &up64->msg_perm.cgid); - err2 |= __put_user(m.msg_perm.mode, &up64->msg_perm.mode); - err2 |= __put_user(m.msg_perm.seq, &up64->msg_perm.seq); - err2 |= __put_user(m.msg_stime, &up64->msg_stime); - err2 |= __put_user(m.msg_rtime, &up64->msg_rtime); - err2 |= __put_user(m.msg_ctime, &up64->msg_ctime); - err2 |= __put_user(m.msg_cbytes, &up64->msg_cbytes); - err2 |= __put_user(m.msg_qnum, &up64->msg_qnum); - err2 |= __put_user(m.msg_qbytes, &up64->msg_qbytes); - err2 |= __put_user(m.msg_lspid, &up64->msg_lspid); - err2 |= __put_user(m.msg_lrpid, &up64->msg_lrpid); - if (err2) - err = -EFAULT; - } else { - if (!access_ok(VERIFY_WRITE, up32, sizeof(*up32))) { - err = -EFAULT; - break; - } - err2 = __put_user(m.msg_perm.key, &up32->msg_perm.key); - err2 |= __put_user(m.msg_perm.uid, &up32->msg_perm.uid); - err2 |= __put_user(m.msg_perm.gid, &up32->msg_perm.gid); - err2 |= __put_user(m.msg_perm.cuid, &up32->msg_perm.cuid); - err2 |= __put_user(m.msg_perm.cgid, &up32->msg_perm.cgid); - err2 |= __put_user(m.msg_perm.mode, &up32->msg_perm.mode); - err2 |= __put_user(m.msg_perm.seq, &up32->msg_perm.seq); - err2 |= __put_user(m.msg_stime, &up32->msg_stime); - err2 |= __put_user(m.msg_rtime, &up32->msg_rtime); - err2 |= __put_user(m.msg_ctime, &up32->msg_ctime); - err2 |= __put_user(m.msg_cbytes, &up32->msg_cbytes); - err2 |= __put_user(m.msg_qnum, &up32->msg_qnum); - err2 |= __put_user(m.msg_qbytes, &up32->msg_qbytes); - err2 |= __put_user(m.msg_lspid, &up32->msg_lspid); - err2 |= __put_user(m.msg_lrpid, &up32->msg_lrpid); - if (err2) - err = -EFAULT; - } - break; - } - - return err; -} - -static int -do_sys32_shmat (int first, int second, int third, int version, void __user *uptr) -{ - unsigned long raddr; - u32 __user *uaddr = (u32 __user *)A((u32)third); - int err = -EINVAL; - - if (version == 1) - return err; - err = do_shmat (first, uptr, second, &raddr); - if (err) - return err; - err = put_user (raddr, uaddr); - return err; -} - -struct shm_info32 { - int used_ids; - u32 shm_tot, shm_rss, shm_swp; - u32 swap_attempts, swap_successes; -}; - -static int -do_sys32_shmctl (int first, int second, void __user *uptr) -{ - struct shmid64_ds32 __user *up64 = (struct shmid64_ds32 __user *)uptr; - struct shmid_ds32 __user *up32 = (struct shmid_ds32 __user *)uptr; - struct shm_info32 __user *uip = (struct shm_info32 __user *)uptr; - int err = -EFAULT, err2; - struct shmid64_ds s64; - mm_segment_t old_fs; - struct shm_info si; - struct shmid_ds s; - - switch (second & ~IPC_64) { - case IPC_INFO: - second = IPC_INFO; /* So that we don't have to translate it */ - case IPC_RMID: - case SHM_LOCK: - case SHM_UNLOCK: - err = sys_shmctl(first, second, (struct shmid_ds __user *)uptr); - break; - case IPC_SET: - if (second & IPC_64) { - err = get_user(s.shm_perm.uid, &up64->shm_perm.uid); - err |= get_user(s.shm_perm.gid, &up64->shm_perm.gid); - err |= get_user(s.shm_perm.mode, &up64->shm_perm.mode); - } else { - err = get_user(s.shm_perm.uid, &up32->shm_perm.uid); - err |= get_user(s.shm_perm.gid, &up32->shm_perm.gid); - err |= get_user(s.shm_perm.mode, &up32->shm_perm.mode); - } - if (err) - break; - old_fs = get_fs(); - set_fs(KERNEL_DS); - err = sys_shmctl(first, second & ~IPC_64, (struct shmid_ds __user *)&s); - set_fs(old_fs); - break; - - case IPC_STAT: - case SHM_STAT: - old_fs = get_fs(); - set_fs(KERNEL_DS); - err = sys_shmctl(first, second | IPC_64, (void __user *) &s64); - set_fs(old_fs); - if (err < 0) - break; - if (second & IPC_64) { - if (!access_ok(VERIFY_WRITE, up64, sizeof(*up64))) { - err = -EFAULT; - break; - } - err2 = __put_user(s64.shm_perm.key, &up64->shm_perm.key); - err2 |= __put_user(s64.shm_perm.uid, &up64->shm_perm.uid); - err2 |= __put_user(s64.shm_perm.gid, &up64->shm_perm.gid); - err2 |= __put_user(s64.shm_perm.cuid, &up64->shm_perm.cuid); - err2 |= __put_user(s64.shm_perm.cgid, &up64->shm_perm.cgid); - err2 |= __put_user(s64.shm_perm.mode, &up64->shm_perm.mode); - err2 |= __put_user(s64.shm_perm.seq, &up64->shm_perm.seq); - err2 |= __put_user(s64.shm_atime, &up64->shm_atime); - err2 |= __put_user(s64.shm_dtime, &up64->shm_dtime); - err2 |= __put_user(s64.shm_ctime, &up64->shm_ctime); - err2 |= __put_user(s64.shm_segsz, &up64->shm_segsz); - err2 |= __put_user(s64.shm_nattch, &up64->shm_nattch); - err2 |= __put_user(s64.shm_cpid, &up64->shm_cpid); - err2 |= __put_user(s64.shm_lpid, &up64->shm_lpid); - } else { - if (!access_ok(VERIFY_WRITE, up32, sizeof(*up32))) { - err = -EFAULT; - break; - } - err2 = __put_user(s64.shm_perm.key, &up32->shm_perm.key); - err2 |= __put_user(s64.shm_perm.uid, &up32->shm_perm.uid); - err2 |= __put_user(s64.shm_perm.gid, &up32->shm_perm.gid); - err2 |= __put_user(s64.shm_perm.cuid, &up32->shm_perm.cuid); - err2 |= __put_user(s64.shm_perm.cgid, &up32->shm_perm.cgid); - err2 |= __put_user(s64.shm_perm.mode, &up32->shm_perm.mode); - err2 |= __put_user(s64.shm_perm.seq, &up32->shm_perm.seq); - err2 |= __put_user(s64.shm_atime, &up32->shm_atime); - err2 |= __put_user(s64.shm_dtime, &up32->shm_dtime); - err2 |= __put_user(s64.shm_ctime, &up32->shm_ctime); - err2 |= __put_user(s64.shm_segsz, &up32->shm_segsz); - err2 |= __put_user(s64.shm_nattch, &up32->shm_nattch); - err2 |= __put_user(s64.shm_cpid, &up32->shm_cpid); - err2 |= __put_user(s64.shm_lpid, &up32->shm_lpid); - } - if (err2) - err = -EFAULT; - break; - - case SHM_INFO: - old_fs = get_fs(); - set_fs(KERNEL_DS); - err = sys_shmctl(first, second, (void __user *)&si); - set_fs(old_fs); - if (err < 0) - break; - err2 = put_user(si.used_ids, &uip->used_ids); - err2 |= __put_user(si.shm_tot, &uip->shm_tot); - err2 |= __put_user(si.shm_rss, &uip->shm_rss); - err2 |= __put_user(si.shm_swp, &uip->shm_swp); - err2 |= __put_user(si.swap_attempts, &uip->swap_attempts); - err2 |= __put_user (si.swap_successes, &uip->swap_successes); - if (err2) - err = -EFAULT; - break; - - default: - err = -EINVAL; - break; - } - - return err; -} - -static int sys32_semtimedop(int semid, struct sembuf __user *tsems, int nsems, - const struct compat_timespec __user *timeout32) -{ - struct compat_timespec t32; - struct timespec __user *t64 = compat_alloc_user_space(sizeof(*t64)); - - if (copy_from_user(&t32, timeout32, sizeof(t32))) - return -EFAULT; - - if (put_user(t32.tv_sec, &t64->tv_sec) || - put_user(t32.tv_nsec, &t64->tv_nsec)) - return -EFAULT; - - return sys_semtimedop(semid, tsems, nsems, t64); -} - asmlinkage long sys32_ipc (u32 call, int first, int second, int third, u32 ptr, u32 fifth) { @@ -918,48 +393,43 @@ sys32_ipc (u32 call, int first, int second, int third, u32 ptr, u32 fifth) switch (call) { case SEMOP: /* struct sembuf is the same on 32 and 64bit :)) */ - err = sys_semtimedop (first, (struct sembuf __user *)AA(ptr), second, - NULL); + err = sys_semtimedop(first, compat_ptr(ptr), second, NULL); break; case SEMTIMEDOP: - err = sys32_semtimedop (first, (struct sembuf __user *)AA(ptr), second, - (const struct compat_timespec __user *)AA(fifth)); + err = compat_sys_semtimedop(first, compat_ptr(ptr), second, + compat_ptr(fifth)); break; case SEMGET: - err = sys_semget (first, second, third); + err = sys_semget(first, second, third); break; case SEMCTL: - err = do_sys32_semctl (first, second, third, - (void __user *)AA(ptr)); + err = compat_sys_semctl(first, second, third, compat_ptr(ptr)); break; - case MSGSND: - err = do_sys32_msgsnd (first, second, third, - (void __user *)AA(ptr)); + err = compat_sys_msgsnd(first, second, third, compat_ptr(ptr)); break; case MSGRCV: - err = do_sys32_msgrcv (first, second, fifth, third, - version, (void __user *)AA(ptr)); + err = compat_sys_msgrcv(first, second, fifth, third, + version, compat_ptr(ptr)); break; case MSGGET: - err = sys_msgget ((key_t) first, second); + err = sys_msgget((key_t) first, second); break; case MSGCTL: - err = do_sys32_msgctl (first, second, (void __user *)AA(ptr)); + err = compat_sys_msgctl(first, second, compat_ptr(ptr)); break; - case SHMAT: - err = do_sys32_shmat (first, second, third, - version, (void __user *)AA(ptr)); + err = compat_sys_shmat(first, second, third, version, + compat_ptr(ptr)); break; case SHMDT: - err = sys_shmdt ((char __user *)A(ptr)); + err = sys_shmdt(compat_ptr(ptr)); break; case SHMGET: - err = sys_shmget (first, (unsigned)second, third); + err = sys_shmget(first, (unsigned)second, third); break; case SHMCTL: - err = do_sys32_shmctl (first, second, (void __user *)AA(ptr)); + err = compat_sys_shmctl(first, second, compat_ptr(ptr)); break; default: err = -EINVAL; @@ -969,18 +439,16 @@ sys32_ipc (u32 call, int first, int second, int third, u32 ptr, u32 fifth) return err; } -asmlinkage long sys32_shmat(int shmid, char __user *shmaddr, - int shmflg, int32_t __user *addr) +#ifdef CONFIG_MIPS32_N32 +asmlinkage long sysn32_semctl(int semid, int semnum, int cmd, union semun arg) { - unsigned long raddr; - int err; - - err = do_shmat(shmid, shmaddr, shmflg, &raddr); - if (err) - return err; - - return put_user(raddr, addr); + /* compat_sys_semctl expects a pointer to union semun */ + u32 __user *uptr = compat_alloc_user_space(sizeof(u32)); + if (put_user(ptr_to_compat(arg.__pad), uptr)) + return -EFAULT; + return compat_sys_semctl(semid, semnum, cmd, uptr); } +#endif struct sysctl_args32 { diff --git a/arch/mips/kernel/scall64-n32.S b/arch/mips/kernel/scall64-n32.S index 5b18f26..34567d8 100644 --- a/arch/mips/kernel/scall64-n32.S +++ b/arch/mips/kernel/scall64-n32.S @@ -149,8 +149,8 @@ EXPORT(sysn32_call_table) PTR sys_mincore PTR sys_madvise PTR sys_shmget - PTR sys32_shmat - PTR sys_shmctl /* 6030 */ + PTR sys_shmat + PTR compat_sys_shmctl /* 6030 */ PTR sys_dup PTR sys_dup2 PTR sys_pause @@ -184,12 +184,12 @@ EXPORT(sysn32_call_table) PTR sys32_newuname PTR sys_semget PTR sys_semop - PTR sys_semctl + PTR sysn32_semctl PTR sys_shmdt /* 6065 */ PTR sys_msgget - PTR sys_msgsnd - PTR sys_msgrcv - PTR sys_msgctl + PTR compat_sys_msgsnd + PTR compat_sys_msgrcv + PTR compat_sys_msgctl PTR compat_sys_fcntl /* 6070 */ PTR sys_flock PTR sys_fsync @@ -335,7 +335,7 @@ EXPORT(sysn32_call_table) PTR compat_sys_fcntl64 PTR sys_set_tid_address PTR sys_restart_syscall - PTR sys_semtimedop /* 6215 */ + PTR compat_sys_semtimedop /* 6215 */ PTR sys_fadvise64_64 PTR compat_sys_statfs64 PTR compat_sys_fstatfs64 -- cgit v1.1 From 03dbd2e0b1dcb24d63f64aa234cce3a7fabed328 Mon Sep 17 00:00:00 2001 From: "Maciej W. Rozycki" Date: Thu, 30 Nov 2006 13:45:32 +0000 Subject: [MIPS] SWARM: Fix a typo in #error directives This is a fix for a typo repeated several times in #error directives for invalid SiByte configurations. Signed-off-by: Maciej W. Rozycki Signed-off-by: Ralf Baechle --- arch/mips/sibyte/swarm/setup.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'arch/mips') diff --git a/arch/mips/sibyte/swarm/setup.c b/arch/mips/sibyte/swarm/setup.c index ac342f5..defa1f1 100644 --- a/arch/mips/sibyte/swarm/setup.c +++ b/arch/mips/sibyte/swarm/setup.c @@ -43,7 +43,7 @@ #elif defined(CONFIG_SIBYTE_SB1250) || defined(CONFIG_SIBYTE_BCM112X) #include #else -#error invalid SiByte board configuation +#error invalid SiByte board configuration #endif #include #include @@ -53,7 +53,7 @@ extern void bcm1480_setup(void); #elif defined(CONFIG_SIBYTE_SB1250) || defined(CONFIG_SIBYTE_BCM112X) extern void sb1250_setup(void); #else -#error invalid SiByte board configuation +#error invalid SiByte board configuration #endif extern int xicor_probe(void); @@ -90,7 +90,7 @@ void __init plat_timer_setup(struct irqaction *irq) #elif defined(CONFIG_SIBYTE_SB1250) || defined(CONFIG_SIBYTE_BCM112X) sb1250_time_init(); #else -#error invalid SiByte board configuation +#error invalid SiByte board configuration #endif } @@ -111,7 +111,7 @@ void __init plat_mem_setup(void) #elif defined(CONFIG_SIBYTE_SB1250) || defined(CONFIG_SIBYTE_BCM112X) sb1250_setup(); #else -#error invalid SiByte board configuation +#error invalid SiByte board configuration #endif panic_timeout = 5; /* For debug. */ -- cgit v1.1 From 0bcdda0f3a87ed684d46841b6069409e39c4af65 Mon Sep 17 00:00:00 2001 From: Atsushi Nemoto Date: Mon, 4 Dec 2006 00:42:59 +0900 Subject: [MIPS] Unify csum_partial.S The 32-bit version and 64-bit version are almost equal. Unify them. This makes further improvements (for example, copying with parallel, supporting PREFETCH, etc.) easier. Signed-off-by: Atsushi Nemoto Signed-off-by: Ralf Baechle --- arch/mips/lib-32/Makefile | 2 +- arch/mips/lib-32/csum_partial.S | 240 ------------------------------------- arch/mips/lib-64/Makefile | 2 +- arch/mips/lib-64/csum_partial.S | 242 ------------------------------------- arch/mips/lib/Makefile | 4 +- arch/mips/lib/csum_partial.S | 258 ++++++++++++++++++++++++++++++++++++++++ 6 files changed, 262 insertions(+), 486 deletions(-) delete mode 100644 arch/mips/lib-32/csum_partial.S delete mode 100644 arch/mips/lib-64/csum_partial.S create mode 100644 arch/mips/lib/csum_partial.S (limited to 'arch/mips') diff --git a/arch/mips/lib-32/Makefile b/arch/mips/lib-32/Makefile index ad28578..dcd4d2e 100644 --- a/arch/mips/lib-32/Makefile +++ b/arch/mips/lib-32/Makefile @@ -2,7 +2,7 @@ # Makefile for MIPS-specific library files.. # -lib-y += csum_partial.o memset.o watch.o +lib-y += memset.o watch.o obj-$(CONFIG_CPU_MIPS32) += dump_tlb.o obj-$(CONFIG_CPU_MIPS64) += dump_tlb.o diff --git a/arch/mips/lib-32/csum_partial.S b/arch/mips/lib-32/csum_partial.S deleted file mode 100644 index ea257db..0000000 --- a/arch/mips/lib-32/csum_partial.S +++ /dev/null @@ -1,240 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1998 Ralf Baechle - */ -#include -#include - -#define ADDC(sum,reg) \ - addu sum, reg; \ - sltu v1, sum, reg; \ - addu sum, v1 - -#define CSUM_BIGCHUNK(src, offset, sum, t0, t1, t2, t3) \ - lw t0, (offset + 0x00)(src); \ - lw t1, (offset + 0x04)(src); \ - lw t2, (offset + 0x08)(src); \ - lw t3, (offset + 0x0c)(src); \ - ADDC(sum, t0); \ - ADDC(sum, t1); \ - ADDC(sum, t2); \ - ADDC(sum, t3); \ - lw t0, (offset + 0x10)(src); \ - lw t1, (offset + 0x14)(src); \ - lw t2, (offset + 0x18)(src); \ - lw t3, (offset + 0x1c)(src); \ - ADDC(sum, t0); \ - ADDC(sum, t1); \ - ADDC(sum, t2); \ - ADDC(sum, t3); \ - -/* - * a0: source address - * a1: length of the area to checksum - * a2: partial checksum - */ - -#define src a0 -#define dest a1 -#define sum v0 - - .text - .set noreorder - -/* unknown src alignment and < 8 bytes to go */ -small_csumcpy: - move a1, t2 - - andi t0, a1, 4 - beqz t0, 1f - andi t0, a1, 2 - - /* Still a full word to go */ - ulw t1, (src) - addiu src, 4 - ADDC(sum, t1) - -1: move t1, zero - beqz t0, 1f - andi t0, a1, 1 - - /* Still a halfword to go */ - ulhu t1, (src) - addiu src, 2 - -1: beqz t0, 1f - sll t1, t1, 16 - - lbu t2, (src) - nop - -#ifdef __MIPSEB__ - sll t2, t2, 8 -#endif - or t1, t2 - -1: ADDC(sum, t1) - - /* fold checksum */ - sll v1, sum, 16 - addu sum, v1 - sltu v1, sum, v1 - srl sum, sum, 16 - addu sum, v1 - - /* odd buffer alignment? */ - beqz t7, 1f - nop - sll v1, sum, 8 - srl sum, sum, 8 - or sum, v1 - andi sum, 0xffff -1: - .set reorder - /* Add the passed partial csum. */ - ADDC(sum, a2) - jr ra - .set noreorder - -/* ------------------------------------------------------------------------- */ - - .align 5 -LEAF(csum_partial) - move sum, zero - move t7, zero - - sltiu t8, a1, 0x8 - bnez t8, small_csumcpy /* < 8 bytes to copy */ - move t2, a1 - - beqz a1, out - andi t7, src, 0x1 /* odd buffer? */ - -hword_align: - beqz t7, word_align - andi t8, src, 0x2 - - lbu t0, (src) - subu a1, a1, 0x1 -#ifdef __MIPSEL__ - sll t0, t0, 8 -#endif - ADDC(sum, t0) - addu src, src, 0x1 - andi t8, src, 0x2 - -word_align: - beqz t8, dword_align - sltiu t8, a1, 56 - - lhu t0, (src) - subu a1, a1, 0x2 - ADDC(sum, t0) - sltiu t8, a1, 56 - addu src, src, 0x2 - -dword_align: - bnez t8, do_end_words - move t8, a1 - - andi t8, src, 0x4 - beqz t8, qword_align - andi t8, src, 0x8 - - lw t0, 0x00(src) - subu a1, a1, 0x4 - ADDC(sum, t0) - addu src, src, 0x4 - andi t8, src, 0x8 - -qword_align: - beqz t8, oword_align - andi t8, src, 0x10 - - lw t0, 0x00(src) - lw t1, 0x04(src) - subu a1, a1, 0x8 - ADDC(sum, t0) - ADDC(sum, t1) - addu src, src, 0x8 - andi t8, src, 0x10 - -oword_align: - beqz t8, begin_movement - srl t8, a1, 0x7 - - lw t3, 0x08(src) - lw t4, 0x0c(src) - lw t0, 0x00(src) - lw t1, 0x04(src) - ADDC(sum, t3) - ADDC(sum, t4) - ADDC(sum, t0) - ADDC(sum, t1) - subu a1, a1, 0x10 - addu src, src, 0x10 - srl t8, a1, 0x7 - -begin_movement: - beqz t8, 1f - andi t2, a1, 0x40 - -move_128bytes: - CSUM_BIGCHUNK(src, 0x00, sum, t0, t1, t3, t4) - CSUM_BIGCHUNK(src, 0x20, sum, t0, t1, t3, t4) - CSUM_BIGCHUNK(src, 0x40, sum, t0, t1, t3, t4) - CSUM_BIGCHUNK(src, 0x60, sum, t0, t1, t3, t4) - subu t8, t8, 0x01 - bnez t8, move_128bytes - addu src, src, 0x80 - -1: - beqz t2, 1f - andi t2, a1, 0x20 - -move_64bytes: - CSUM_BIGCHUNK(src, 0x00, sum, t0, t1, t3, t4) - CSUM_BIGCHUNK(src, 0x20, sum, t0, t1, t3, t4) - addu src, src, 0x40 - -1: - beqz t2, do_end_words - andi t8, a1, 0x1c - -move_32bytes: - CSUM_BIGCHUNK(src, 0x00, sum, t0, t1, t3, t4) - andi t8, a1, 0x1c - addu src, src, 0x20 - -do_end_words: - beqz t8, maybe_end_cruft - srl t8, t8, 0x2 - -end_words: - lw t0, (src) - subu t8, t8, 0x1 - ADDC(sum, t0) - bnez t8, end_words - addu src, src, 0x4 - -maybe_end_cruft: - andi t2, a1, 0x3 - -small_memcpy: - j small_csumcpy; move a1, t2 - beqz t2, out - move a1, t2 - -end_bytes: - lb t0, (src) - subu a1, a1, 0x1 - bnez a2, end_bytes - addu src, src, 0x1 - -out: - jr ra - move v0, sum - END(csum_partial) diff --git a/arch/mips/lib-64/Makefile b/arch/mips/lib-64/Makefile index ad28578..dcd4d2e 100644 --- a/arch/mips/lib-64/Makefile +++ b/arch/mips/lib-64/Makefile @@ -2,7 +2,7 @@ # Makefile for MIPS-specific library files.. # -lib-y += csum_partial.o memset.o watch.o +lib-y += memset.o watch.o obj-$(CONFIG_CPU_MIPS32) += dump_tlb.o obj-$(CONFIG_CPU_MIPS64) += dump_tlb.o diff --git a/arch/mips/lib-64/csum_partial.S b/arch/mips/lib-64/csum_partial.S deleted file mode 100644 index 25aba66..0000000 --- a/arch/mips/lib-64/csum_partial.S +++ /dev/null @@ -1,242 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Quick'n'dirty IP checksum ... - * - * Copyright (C) 1998, 1999 Ralf Baechle - * Copyright (C) 1999 Silicon Graphics, Inc. - */ -#include -#include - -#define ADDC(sum,reg) \ - addu sum, reg; \ - sltu v1, sum, reg; \ - addu sum, v1 - -#define CSUM_BIGCHUNK(src, offset, sum, t0, t1, t2, t3) \ - lw t0, (offset + 0x00)(src); \ - lw t1, (offset + 0x04)(src); \ - lw t2, (offset + 0x08)(src); \ - lw t3, (offset + 0x0c)(src); \ - ADDC(sum, t0); \ - ADDC(sum, t1); \ - ADDC(sum, t2); \ - ADDC(sum, t3); \ - lw t0, (offset + 0x10)(src); \ - lw t1, (offset + 0x14)(src); \ - lw t2, (offset + 0x18)(src); \ - lw t3, (offset + 0x1c)(src); \ - ADDC(sum, t0); \ - ADDC(sum, t1); \ - ADDC(sum, t2); \ - ADDC(sum, t3); \ - -/* - * a0: source address - * a1: length of the area to checksum - * a2: partial checksum - */ - -#define src a0 -#define sum v0 - - .text - .set noreorder - -/* unknown src alignment and < 8 bytes to go */ -small_csumcpy: - move a1, ta2 - - andi ta0, a1, 4 - beqz ta0, 1f - andi ta0, a1, 2 - - /* Still a full word to go */ - ulw ta1, (src) - daddiu src, 4 - ADDC(sum, ta1) - -1: move ta1, zero - beqz ta0, 1f - andi ta0, a1, 1 - - /* Still a halfword to go */ - ulhu ta1, (src) - daddiu src, 2 - -1: beqz ta0, 1f - sll ta1, ta1, 16 - - lbu ta2, (src) - nop - -#ifdef __MIPSEB__ - sll ta2, ta2, 8 -#endif - or ta1, ta2 - -1: ADDC(sum, ta1) - - /* fold checksum */ - sll v1, sum, 16 - addu sum, v1 - sltu v1, sum, v1 - srl sum, sum, 16 - addu sum, v1 - - /* odd buffer alignment? */ - beqz t3, 1f - nop - sll v1, sum, 8 - srl sum, sum, 8 - or sum, v1 - andi sum, 0xffff -1: - .set reorder - /* Add the passed partial csum. */ - ADDC(sum, a2) - jr ra - .set noreorder - -/* ------------------------------------------------------------------------- */ - - .align 5 -LEAF(csum_partial) - move sum, zero - move t3, zero - - sltiu t8, a1, 0x8 - bnez t8, small_csumcpy /* < 8 bytes to copy */ - move ta2, a1 - - beqz a1, out - andi t3, src, 0x1 /* odd buffer? */ - -hword_align: - beqz t3, word_align - andi t8, src, 0x2 - - lbu ta0, (src) - dsubu a1, a1, 0x1 -#ifdef __MIPSEL__ - sll ta0, ta0, 8 -#endif - ADDC(sum, ta0) - daddu src, src, 0x1 - andi t8, src, 0x2 - -word_align: - beqz t8, dword_align - sltiu t8, a1, 56 - - lhu ta0, (src) - dsubu a1, a1, 0x2 - ADDC(sum, ta0) - sltiu t8, a1, 56 - daddu src, src, 0x2 - -dword_align: - bnez t8, do_end_words - move t8, a1 - - andi t8, src, 0x4 - beqz t8, qword_align - andi t8, src, 0x8 - - lw ta0, 0x00(src) - dsubu a1, a1, 0x4 - ADDC(sum, ta0) - daddu src, src, 0x4 - andi t8, src, 0x8 - -qword_align: - beqz t8, oword_align - andi t8, src, 0x10 - - lw ta0, 0x00(src) - lw ta1, 0x04(src) - dsubu a1, a1, 0x8 - ADDC(sum, ta0) - ADDC(sum, ta1) - daddu src, src, 0x8 - andi t8, src, 0x10 - -oword_align: - beqz t8, begin_movement - dsrl t8, a1, 0x7 - - lw ta3, 0x08(src) - lw t0, 0x0c(src) - lw ta0, 0x00(src) - lw ta1, 0x04(src) - ADDC(sum, ta3) - ADDC(sum, t0) - ADDC(sum, ta0) - ADDC(sum, ta1) - dsubu a1, a1, 0x10 - daddu src, src, 0x10 - dsrl t8, a1, 0x7 - -begin_movement: - beqz t8, 1f - andi ta2, a1, 0x40 - -move_128bytes: - CSUM_BIGCHUNK(src, 0x00, sum, ta0, ta1, ta3, t0) - CSUM_BIGCHUNK(src, 0x20, sum, ta0, ta1, ta3, t0) - CSUM_BIGCHUNK(src, 0x40, sum, ta0, ta1, ta3, t0) - CSUM_BIGCHUNK(src, 0x60, sum, ta0, ta1, ta3, t0) - dsubu t8, t8, 0x01 - bnez t8, move_128bytes - daddu src, src, 0x80 - -1: - beqz ta2, 1f - andi ta2, a1, 0x20 - -move_64bytes: - CSUM_BIGCHUNK(src, 0x00, sum, ta0, ta1, ta3, t0) - CSUM_BIGCHUNK(src, 0x20, sum, ta0, ta1, ta3, t0) - daddu src, src, 0x40 - -1: - beqz ta2, do_end_words - andi t8, a1, 0x1c - -move_32bytes: - CSUM_BIGCHUNK(src, 0x00, sum, ta0, ta1, ta3, t0) - andi t8, a1, 0x1c - daddu src, src, 0x20 - -do_end_words: - beqz t8, maybe_end_cruft - dsrl t8, t8, 0x2 - -end_words: - lw ta0, (src) - dsubu t8, t8, 0x1 - ADDC(sum, ta0) - bnez t8, end_words - daddu src, src, 0x4 - -maybe_end_cruft: - andi ta2, a1, 0x3 - -small_memcpy: - j small_csumcpy; move a1, ta2 /* XXX ??? */ - beqz t2, out - move a1, ta2 - -end_bytes: - lb ta0, (src) - dsubu a1, a1, 0x1 - bnez a2, end_bytes - daddu src, src, 0x1 - -out: - jr ra - move v0, sum - END(csum_partial) diff --git a/arch/mips/lib/Makefile b/arch/mips/lib/Makefile index b225543..888b61e 100644 --- a/arch/mips/lib/Makefile +++ b/arch/mips/lib/Makefile @@ -2,8 +2,8 @@ # Makefile for MIPS-specific library files.. # -lib-y += csum_partial_copy.o memcpy.o promlib.o strlen_user.o strncpy_user.o \ - strnlen_user.o uncached.o +lib-y += csum_partial.o csum_partial_copy.o memcpy.o promlib.o \ + strlen_user.o strncpy_user.o strnlen_user.o uncached.o obj-y += iomap.o diff --git a/arch/mips/lib/csum_partial.S b/arch/mips/lib/csum_partial.S new file mode 100644 index 0000000..15611d9 --- /dev/null +++ b/arch/mips/lib/csum_partial.S @@ -0,0 +1,258 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Quick'n'dirty IP checksum ... + * + * Copyright (C) 1998, 1999 Ralf Baechle + * Copyright (C) 1999 Silicon Graphics, Inc. + */ +#include +#include + +#ifdef CONFIG_64BIT +#define T0 ta0 +#define T1 ta1 +#define T2 ta2 +#define T3 ta3 +#define T4 t0 +#define T7 t3 +#else +#define T0 t0 +#define T1 t1 +#define T2 t2 +#define T3 t3 +#define T4 t4 +#define T7 t7 +#endif + +#define ADDC(sum,reg) \ + addu sum, reg; \ + sltu v1, sum, reg; \ + addu sum, v1 + +#define CSUM_BIGCHUNK(src, offset, sum, _t0, _t1, _t2, _t3) \ + lw _t0, (offset + 0x00)(src); \ + lw _t1, (offset + 0x04)(src); \ + lw _t2, (offset + 0x08)(src); \ + lw _t3, (offset + 0x0c)(src); \ + ADDC(sum, _t0); \ + ADDC(sum, _t1); \ + ADDC(sum, _t2); \ + ADDC(sum, _t3); \ + lw _t0, (offset + 0x10)(src); \ + lw _t1, (offset + 0x14)(src); \ + lw _t2, (offset + 0x18)(src); \ + lw _t3, (offset + 0x1c)(src); \ + ADDC(sum, _t0); \ + ADDC(sum, _t1); \ + ADDC(sum, _t2); \ + ADDC(sum, _t3); \ + +/* + * a0: source address + * a1: length of the area to checksum + * a2: partial checksum + */ + +#define src a0 +#define sum v0 + + .text + .set noreorder + +/* unknown src alignment and < 8 bytes to go */ +small_csumcpy: + move a1, T2 + + andi T0, a1, 4 + beqz T0, 1f + andi T0, a1, 2 + + /* Still a full word to go */ + ulw T1, (src) + PTR_ADDIU src, 4 + ADDC(sum, T1) + +1: move T1, zero + beqz T0, 1f + andi T0, a1, 1 + + /* Still a halfword to go */ + ulhu T1, (src) + PTR_ADDIU src, 2 + +1: beqz T0, 1f + sll T1, T1, 16 + + lbu T2, (src) + nop + +#ifdef __MIPSEB__ + sll T2, T2, 8 +#endif + or T1, T2 + +1: ADDC(sum, T1) + + /* fold checksum */ + sll v1, sum, 16 + addu sum, v1 + sltu v1, sum, v1 + srl sum, sum, 16 + addu sum, v1 + + /* odd buffer alignment? */ + beqz T7, 1f + nop + sll v1, sum, 8 + srl sum, sum, 8 + or sum, v1 + andi sum, 0xffff +1: + .set reorder + /* Add the passed partial csum. */ + ADDC(sum, a2) + jr ra + .set noreorder + +/* ------------------------------------------------------------------------- */ + + .align 5 +LEAF(csum_partial) + move sum, zero + move T7, zero + + sltiu t8, a1, 0x8 + bnez t8, small_csumcpy /* < 8 bytes to copy */ + move T2, a1 + + beqz a1, out + andi T7, src, 0x1 /* odd buffer? */ + +hword_align: + beqz T7, word_align + andi t8, src, 0x2 + + lbu T0, (src) + LONG_SUBU a1, a1, 0x1 +#ifdef __MIPSEL__ + sll T0, T0, 8 +#endif + ADDC(sum, T0) + PTR_ADDU src, src, 0x1 + andi t8, src, 0x2 + +word_align: + beqz t8, dword_align + sltiu t8, a1, 56 + + lhu T0, (src) + LONG_SUBU a1, a1, 0x2 + ADDC(sum, T0) + sltiu t8, a1, 56 + PTR_ADDU src, src, 0x2 + +dword_align: + bnez t8, do_end_words + move t8, a1 + + andi t8, src, 0x4 + beqz t8, qword_align + andi t8, src, 0x8 + + lw T0, 0x00(src) + LONG_SUBU a1, a1, 0x4 + ADDC(sum, T0) + PTR_ADDU src, src, 0x4 + andi t8, src, 0x8 + +qword_align: + beqz t8, oword_align + andi t8, src, 0x10 + + lw T0, 0x00(src) + lw T1, 0x04(src) + LONG_SUBU a1, a1, 0x8 + ADDC(sum, T0) + ADDC(sum, T1) + PTR_ADDU src, src, 0x8 + andi t8, src, 0x10 + +oword_align: + beqz t8, begin_movement + LONG_SRL t8, a1, 0x7 + + lw T3, 0x08(src) + lw T4, 0x0c(src) + lw T0, 0x00(src) + lw T1, 0x04(src) + ADDC(sum, T3) + ADDC(sum, T4) + ADDC(sum, T0) + ADDC(sum, T1) + LONG_SUBU a1, a1, 0x10 + PTR_ADDU src, src, 0x10 + LONG_SRL t8, a1, 0x7 + +begin_movement: + beqz t8, 1f + andi T2, a1, 0x40 + +move_128bytes: + CSUM_BIGCHUNK(src, 0x00, sum, T0, T1, T3, T4) + CSUM_BIGCHUNK(src, 0x20, sum, T0, T1, T3, T4) + CSUM_BIGCHUNK(src, 0x40, sum, T0, T1, T3, T4) + CSUM_BIGCHUNK(src, 0x60, sum, T0, T1, T3, T4) + LONG_SUBU t8, t8, 0x01 + bnez t8, move_128bytes + PTR_ADDU src, src, 0x80 + +1: + beqz T2, 1f + andi T2, a1, 0x20 + +move_64bytes: + CSUM_BIGCHUNK(src, 0x00, sum, T0, T1, T3, T4) + CSUM_BIGCHUNK(src, 0x20, sum, T0, T1, T3, T4) + PTR_ADDU src, src, 0x40 + +1: + beqz T2, do_end_words + andi t8, a1, 0x1c + +move_32bytes: + CSUM_BIGCHUNK(src, 0x00, sum, T0, T1, T3, T4) + andi t8, a1, 0x1c + PTR_ADDU src, src, 0x20 + +do_end_words: + beqz t8, maybe_end_cruft + LONG_SRL t8, t8, 0x2 + +end_words: + lw T0, (src) + LONG_SUBU t8, t8, 0x1 + ADDC(sum, T0) + bnez t8, end_words + PTR_ADDU src, src, 0x4 + +maybe_end_cruft: + andi T2, a1, 0x3 + +small_memcpy: + j small_csumcpy; move a1, T2 /* XXX ??? */ + beqz t2, out + move a1, T2 + +end_bytes: + lb T0, (src) + LONG_SUBU a1, a1, 0x1 + bnez a2, end_bytes + PTR_ADDU src, src, 0x1 + +out: + jr ra + move v0, sum + END(csum_partial) -- cgit v1.1 From 08f57f7ffe5819e537301b1f1109fa4fc670bfff Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Sun, 3 Dec 2006 19:55:45 +0000 Subject: [MIPS] Alchemy: Automatically enable CONFIG_RESOURCES_64BIT for PCI configs. Signed-off-by: Ralf Baechle --- arch/mips/Kconfig | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'arch/mips') diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 2308c8e..3947e5d 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -16,6 +16,7 @@ config MIPS_MTX1 bool "4G Systems MTX-1 board" select DMA_NONCOHERENT select HW_HAS_PCI + select RESOURCES_64BIT if PCI select SOC_AU1500 select SYS_HAS_CPU_MIPS32_R1 select SYS_SUPPORTS_LITTLE_ENDIAN @@ -32,6 +33,7 @@ config MIPS_PB1000 select SOC_AU1000 select DMA_NONCOHERENT select HW_HAS_PCI + select RESOURCES_64BIT if PCI select SWAP_IO_SPACE select SYS_HAS_CPU_MIPS32_R1 select SYS_SUPPORTS_LITTLE_ENDIAN @@ -41,6 +43,7 @@ config MIPS_PB1100 select SOC_AU1100 select DMA_NONCOHERENT select HW_HAS_PCI + select RESOURCES_64BIT if PCI select SWAP_IO_SPACE select SYS_HAS_CPU_MIPS32_R1 select SYS_SUPPORTS_LITTLE_ENDIAN @@ -50,6 +53,7 @@ config MIPS_PB1500 select SOC_AU1500 select DMA_NONCOHERENT select HW_HAS_PCI + select RESOURCES_64BIT if PCI select SYS_HAS_CPU_MIPS32_R1 select SYS_SUPPORTS_LITTLE_ENDIAN @@ -59,6 +63,7 @@ config MIPS_PB1550 select DMA_NONCOHERENT select HW_HAS_PCI select MIPS_DISABLE_OBSOLETE_IDE + select RESOURCES_64BIT if PCI select SYS_HAS_CPU_MIPS32_R1 select SYS_SUPPORTS_LITTLE_ENDIAN @@ -67,6 +72,7 @@ config MIPS_PB1200 select SOC_AU1200 select DMA_NONCOHERENT select MIPS_DISABLE_OBSOLETE_IDE + select RESOURCES_64BIT if PCI select SYS_HAS_CPU_MIPS32_R1 select SYS_SUPPORTS_LITTLE_ENDIAN @@ -75,6 +81,7 @@ config MIPS_DB1000 select SOC_AU1000 select DMA_NONCOHERENT select HW_HAS_PCI + select RESOURCES_64BIT if PCI select SYS_HAS_CPU_MIPS32_R1 select SYS_SUPPORTS_LITTLE_ENDIAN @@ -91,6 +98,7 @@ config MIPS_DB1500 select DMA_NONCOHERENT select HW_HAS_PCI select MIPS_DISABLE_OBSOLETE_IDE + select RESOURCES_64BIT if PCI select SYS_HAS_CPU_MIPS32_R1 select SYS_SUPPORTS_BIG_ENDIAN select SYS_SUPPORTS_LITTLE_ENDIAN @@ -101,6 +109,7 @@ config MIPS_DB1550 select HW_HAS_PCI select DMA_NONCOHERENT select MIPS_DISABLE_OBSOLETE_IDE + select RESOURCES_64BIT if PCI select SYS_HAS_CPU_MIPS32_R1 select SYS_SUPPORTS_LITTLE_ENDIAN -- cgit v1.1 From 0004a9dfeaa709a7f853487aba19932c9b1a87c8 Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Tue, 31 Oct 2006 03:45:07 +0000 Subject: [MIPS] Cleanup memory barriers for weakly ordered systems. Also the R4000 / R4600 LL/SC instructions imply a sync so no explicit sync needed. Signed-off-by: Ralf Baechle --- arch/mips/Kconfig | 4 ++++ arch/mips/kernel/smp.c | 6 +++--- 2 files changed, 7 insertions(+), 3 deletions(-) (limited to 'arch/mips') diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 3947e5d..4d64960 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -1277,6 +1277,7 @@ config CPU_RM9000 select CPU_SUPPORTS_32BIT_KERNEL select CPU_SUPPORTS_64BIT_KERNEL select CPU_SUPPORTS_HIGHMEM + select WEAK_ORDERING config CPU_SB1 bool "SB1" @@ -1285,6 +1286,7 @@ config CPU_SB1 select CPU_SUPPORTS_32BIT_KERNEL select CPU_SUPPORTS_64BIT_KERNEL select CPU_SUPPORTS_HIGHMEM + select WEAK_ORDERING endchoice @@ -1345,6 +1347,8 @@ config SYS_HAS_CPU_RM9000 config SYS_HAS_CPU_SB1 bool +config WEAK_ORDERING + bool endmenu # diff --git a/arch/mips/kernel/smp.c b/arch/mips/kernel/smp.c index 49db516..f2a8701 100644 --- a/arch/mips/kernel/smp.c +++ b/arch/mips/kernel/smp.c @@ -172,7 +172,7 @@ int smp_call_function (void (*func) (void *info), void *info, int retry, spin_lock(&smp_call_lock); call_data = &data; - mb(); + smp_mb(); /* Send a message to all other CPUs and wait for them to respond */ for_each_online_cpu(i) @@ -204,7 +204,7 @@ void smp_call_function_interrupt(void) * Notify initiating CPU that I've grabbed the data and am * about to execute the function. */ - mb(); + smp_mb(); atomic_inc(&call_data->started); /* @@ -215,7 +215,7 @@ void smp_call_function_interrupt(void) irq_exit(); if (wait) { - mb(); + smp_mb(); atomic_inc(&call_data->finished); } } -- cgit v1.1 From 6d5aefb8eaa38e44b5b8cf60c812aceafc02d924 Mon Sep 17 00:00:00 2001 From: David Howells Date: Tue, 5 Dec 2006 19:36:26 +0000 Subject: WorkQueue: Fix up arch-specific work items where possible Fix up arch-specific work items where possible to use the new work_struct and delayed_work structs. Three places that enqueue bits of their stack and then return have been marked with #error as this is not permitted. Signed-Off-By: David Howells --- arch/mips/kernel/kspd.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/mips') diff --git a/arch/mips/kernel/kspd.c b/arch/mips/kernel/kspd.c index f06a144..2c82412 100644 --- a/arch/mips/kernel/kspd.c +++ b/arch/mips/kernel/kspd.c @@ -319,7 +319,7 @@ static void sp_cleanup(void) static int channel_open = 0; /* the work handler */ -static void sp_work(void *data) +static void sp_work(struct work_struct *unused) { if (!channel_open) { if( rtlx_open(RTLX_CHANNEL_SYSIO, 1) != 0) { @@ -354,7 +354,7 @@ static void startwork(int vpe) return; } - INIT_WORK(&work, sp_work, NULL); + INIT_WORK(&work, sp_work); queue_work(workqueue, &work); } else queue_work(workqueue, &work); -- cgit v1.1 From 25ba2f506c69bd54a7342210422176baf10018c5 Mon Sep 17 00:00:00 2001 From: Atsushi Nemoto Date: Sat, 2 Dec 2006 00:08:03 +0900 Subject: [MIPS] Do not use handle_level_irq for ioasic_dma_irq_type. Signed-off-by: Atsushi Nemoto Signed-off-by: Ralf Baechle --- arch/mips/dec/ioasic-irq.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'arch/mips') diff --git a/arch/mips/dec/ioasic-irq.c b/arch/mips/dec/ioasic-irq.c index 269b22b..e21476d 100644 --- a/arch/mips/dec/ioasic-irq.c +++ b/arch/mips/dec/ioasic-irq.c @@ -106,8 +106,7 @@ void __init init_ioasic_irqs(int base) set_irq_chip_and_handler(i, &ioasic_irq_type, handle_level_irq); for (; i < base + IO_IRQ_LINES; i++) - set_irq_chip_and_handler(i, &ioasic_dma_irq_type, - handle_level_irq); + set_irq_chip(i, &ioasic_dma_irq_type); ioasic_irq_base = base; } -- cgit v1.1 From 1ccd1c1c35a6cb21da32479931d4fa6d47320095 Mon Sep 17 00:00:00 2001 From: Atsushi Nemoto Date: Wed, 6 Dec 2006 01:20:57 +0900 Subject: [MIPS] genirq: use name instead of typename The "typename" field was obsoleted by the "name" field. Signed-off-by: Atsushi Nemoto Signed-off-by: Ralf Baechle --- arch/mips/kernel/irq.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/mips') diff --git a/arch/mips/kernel/irq.c b/arch/mips/kernel/irq.c index b339798..2fe4c86 100644 --- a/arch/mips/kernel/irq.c +++ b/arch/mips/kernel/irq.c @@ -117,7 +117,7 @@ int show_interrupts(struct seq_file *p, void *v) for_each_online_cpu(j) seq_printf(p, "%10u ", kstat_cpu(j).irqs[i]); #endif - seq_printf(p, " %14s", irq_desc[i].chip->typename); + seq_printf(p, " %14s", irq_desc[i].chip->name); seq_printf(p, " %s", action->name); for (action=action->next; action; action = action->next) -- cgit v1.1 From e77c232cfc6e1250b2916a7c69225d6634d05a49 Mon Sep 17 00:00:00 2001 From: Franck Bui-Huu Date: Fri, 1 Dec 2006 18:22:27 +0100 Subject: [MIPS] Compile __do_IRQ() when really needed __do_IRQ() is needed only by irq handlers that can't use default handlers defined in kernel/irq/chip.c. For others platforms there's no need to compile this function since it won't be used. For those platforms this patch defines GENERIC_HARDIRQS_NO__DO_IRQ symbol which is used exactly for this purpose. Futhermore for platforms which do not use __do_IRQ(), end() method which is part of the 'irq_chip' structure is not used. This patch simply removes this method in this case. Signed-off-by: Franck Bui-Huu Signed-off-by: Ralf Baechle --- arch/mips/Kconfig | 9 +++++++ arch/mips/dec/ioasic-irq.c | 1 - arch/mips/dec/kn02-irq.c | 7 ------ arch/mips/emma2rh/common/irq_emma2rh.c | 7 ------ arch/mips/emma2rh/markeins/irq_markeins.c | 7 ------ arch/mips/jazz/irq.c | 7 ------ arch/mips/kernel/irq-mv6434x.c | 10 -------- arch/mips/kernel/irq-rm7000.c | 7 ------ arch/mips/kernel/irq-rm9000.c | 8 ------- arch/mips/kernel/irq_cpu.c | 10 -------- arch/mips/lasat/interrupt.c | 7 ------ arch/mips/momentum/ocelot_c/cpci-irq.c | 10 -------- arch/mips/momentum/ocelot_c/uart-irq.c | 10 -------- arch/mips/philips/pnx8550/common/int.c | 8 ------- arch/mips/sgi-ip22/ip22-int.c | 28 ---------------------- arch/mips/sgi-ip27/ip27-irq.c | 8 ------- arch/mips/sgi-ip27/ip27-timer.c | 5 ---- arch/mips/tx4927/common/tx4927_irq.c | 26 -------------------- .../tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c | 21 ---------------- arch/mips/tx4938/common/irq.c | 20 ---------------- arch/mips/tx4938/toshiba_rbtx4938/irq.c | 10 -------- arch/mips/vr41xx/Kconfig | 5 ++++ arch/mips/vr41xx/common/icu.c | 14 ----------- 23 files changed, 14 insertions(+), 231 deletions(-) (limited to 'arch/mips') diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 4d64960..d8af858f 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -242,6 +242,7 @@ config LASAT select SYS_SUPPORTS_32BIT_KERNEL select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL select SYS_SUPPORTS_LITTLE_ENDIAN + select GENERIC_HARDIRQS_NO__DO_IRQ config MIPS_ATLAS bool "MIPS Atlas board" @@ -265,6 +266,7 @@ config MIPS_ATLAS select SYS_SUPPORTS_BIG_ENDIAN select SYS_SUPPORTS_LITTLE_ENDIAN select SYS_SUPPORTS_MULTITHREADING if EXPERIMENTAL + select GENERIC_HARDIRQS_NO__DO_IRQ help This enables support for the MIPS Technologies Atlas evaluation board. @@ -419,6 +421,7 @@ config MOMENCO_OCELOT_C select SYS_SUPPORTS_32BIT_KERNEL select SYS_SUPPORTS_64BIT_KERNEL select SYS_SUPPORTS_BIG_ENDIAN + select GENERIC_HARDIRQS_NO__DO_IRQ help The Ocelot is a MIPS-based Single Board Computer (SBC) made by Momentum Computer . @@ -569,6 +572,7 @@ config SGI_IP27 select SYS_SUPPORTS_BIG_ENDIAN select SYS_SUPPORTS_NUMA select SYS_SUPPORTS_SMP + select GENERIC_HARDIRQS_NO__DO_IRQ help This are the SGI Origin 200, Origin 2000 and Onyx 2 Graphics workstations. To compile a Linux kernel that runs on these, say Y @@ -835,6 +839,10 @@ config SCHED_NO_NO_OMIT_FRAME_POINTER bool default y +config GENERIC_HARDIRQS_NO__DO_IRQ + bool + default n + # # Select some configuration options automatically based on user selections. # @@ -996,6 +1004,7 @@ config SOC_PNX8550 select HW_HAS_PCI select SYS_HAS_CPU_MIPS32_R1 select SYS_SUPPORTS_32BIT_KERNEL + select GENERIC_HARDIRQS_NO__DO_IRQ config SWAP_IO_SPACE bool diff --git a/arch/mips/dec/ioasic-irq.c b/arch/mips/dec/ioasic-irq.c index e21476d..4c7cb404 100644 --- a/arch/mips/dec/ioasic-irq.c +++ b/arch/mips/dec/ioasic-irq.c @@ -67,7 +67,6 @@ static struct irq_chip ioasic_irq_type = { .mask = mask_ioasic_irq, .mask_ack = ack_ioasic_irq, .unmask = unmask_ioasic_irq, - .end = end_ioasic_irq, }; diff --git a/arch/mips/dec/kn02-irq.c b/arch/mips/dec/kn02-irq.c index 5a9be4c..916e46b 100644 --- a/arch/mips/dec/kn02-irq.c +++ b/arch/mips/dec/kn02-irq.c @@ -57,19 +57,12 @@ static void ack_kn02_irq(unsigned int irq) iob(); } -static void end_kn02_irq(unsigned int irq) -{ - if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) - unmask_kn02_irq(irq); -} - static struct irq_chip kn02_irq_type = { .typename = "KN02-CSR", .ack = ack_kn02_irq, .mask = mask_kn02_irq, .mask_ack = ack_kn02_irq, .unmask = unmask_kn02_irq, - .end = end_kn02_irq, }; diff --git a/arch/mips/emma2rh/common/irq_emma2rh.c b/arch/mips/emma2rh/common/irq_emma2rh.c index 59b9829..8d880f0 100644 --- a/arch/mips/emma2rh/common/irq_emma2rh.c +++ b/arch/mips/emma2rh/common/irq_emma2rh.c @@ -56,19 +56,12 @@ static void emma2rh_irq_disable(unsigned int irq) ll_emma2rh_irq_disable(irq - emma2rh_irq_base); } -static void emma2rh_irq_end(unsigned int irq) -{ - if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) - ll_emma2rh_irq_enable(irq - emma2rh_irq_base); -} - struct irq_chip emma2rh_irq_controller = { .typename = "emma2rh_irq", .ack = emma2rh_irq_disable, .mask = emma2rh_irq_disable, .mask_ack = emma2rh_irq_disable, .unmask = emma2rh_irq_enable, - .end = emma2rh_irq_end, }; void emma2rh_irq_init(u32 irq_base) diff --git a/arch/mips/emma2rh/markeins/irq_markeins.c b/arch/mips/emma2rh/markeins/irq_markeins.c index 3ac4e40..2116d9b 100644 --- a/arch/mips/emma2rh/markeins/irq_markeins.c +++ b/arch/mips/emma2rh/markeins/irq_markeins.c @@ -48,19 +48,12 @@ static void emma2rh_sw_irq_disable(unsigned int irq) ll_emma2rh_sw_irq_disable(irq - emma2rh_sw_irq_base); } -static void emma2rh_sw_irq_end(unsigned int irq) -{ - if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) - ll_emma2rh_sw_irq_enable(irq - emma2rh_sw_irq_base); -} - struct irq_chip emma2rh_sw_irq_controller = { .typename = "emma2rh_sw_irq", .ack = emma2rh_sw_irq_disable, .mask = emma2rh_sw_irq_disable, .mask_ack = emma2rh_sw_irq_disable, .unmask = emma2rh_sw_irq_enable, - .end = emma2rh_sw_irq_end, }; void emma2rh_sw_irq_init(u32 irq_base) diff --git a/arch/mips/jazz/irq.c b/arch/mips/jazz/irq.c index 5c4f50c..f8d417b 100644 --- a/arch/mips/jazz/irq.c +++ b/arch/mips/jazz/irq.c @@ -39,19 +39,12 @@ void disable_r4030_irq(unsigned int irq) spin_unlock_irqrestore(&r4030_lock, flags); } -static void end_r4030_irq(unsigned int irq) -{ - if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) - enable_r4030_irq(irq); -} - static struct irq_chip r4030_irq_type = { .typename = "R4030", .ack = disable_r4030_irq, .mask = disable_r4030_irq, .mask_ack = disable_r4030_irq, .unmask = enable_r4030_irq, - .end = end_r4030_irq, }; void __init init_r4030_ints(void) diff --git a/arch/mips/kernel/irq-mv6434x.c b/arch/mips/kernel/irq-mv6434x.c index 6cfb31c..efbd219 100644 --- a/arch/mips/kernel/irq-mv6434x.c +++ b/arch/mips/kernel/irq-mv6434x.c @@ -67,15 +67,6 @@ static inline void unmask_mv64340_irq(unsigned int irq) } /* - * End IRQ processing - */ -static void end_mv64340_irq(unsigned int irq) -{ - if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) - unmask_mv64340_irq(irq); -} - -/* * Interrupt handler for interrupts coming from the Marvell chip. * It could be built in ethernet ports etc... */ @@ -106,7 +97,6 @@ struct irq_chip mv64340_irq_type = { .mask = mask_mv64340_irq, .mask_ack = mask_mv64340_irq, .unmask = unmask_mv64340_irq, - .end = end_mv64340_irq, }; void __init mv64340_irq_init(unsigned int base) diff --git a/arch/mips/kernel/irq-rm7000.c b/arch/mips/kernel/irq-rm7000.c index ddcc2a5..123324b 100644 --- a/arch/mips/kernel/irq-rm7000.c +++ b/arch/mips/kernel/irq-rm7000.c @@ -29,19 +29,12 @@ static inline void mask_rm7k_irq(unsigned int irq) clear_c0_intcontrol(0x100 << (irq - irq_base)); } -static void rm7k_cpu_irq_end(unsigned int irq) -{ - if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) - unmask_rm7k_irq(irq); -} - static struct irq_chip rm7k_irq_controller = { .typename = "RM7000", .ack = mask_rm7k_irq, .mask = mask_rm7k_irq, .mask_ack = mask_rm7k_irq, .unmask = unmask_rm7k_irq, - .end = rm7k_cpu_irq_end, }; void __init rm7k_cpu_irq_init(int base) diff --git a/arch/mips/kernel/irq-rm9000.c b/arch/mips/kernel/irq-rm9000.c index ba6440c..0e6f4c5 100644 --- a/arch/mips/kernel/irq-rm9000.c +++ b/arch/mips/kernel/irq-rm9000.c @@ -80,19 +80,12 @@ static void rm9k_perfcounter_irq_shutdown(unsigned int irq) on_each_cpu(local_rm9k_perfcounter_irq_shutdown, (void *) irq, 0, 1); } -static void rm9k_cpu_irq_end(unsigned int irq) -{ - if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) - unmask_rm9k_irq(irq); -} - static struct irq_chip rm9k_irq_controller = { .typename = "RM9000", .ack = mask_rm9k_irq, .mask = mask_rm9k_irq, .mask_ack = mask_rm9k_irq, .unmask = unmask_rm9k_irq, - .end = rm9k_cpu_irq_end, }; static struct irq_chip rm9k_perfcounter_irq = { @@ -103,7 +96,6 @@ static struct irq_chip rm9k_perfcounter_irq = { .mask = mask_rm9k_irq, .mask_ack = mask_rm9k_irq, .unmask = unmask_rm9k_irq, - .end = rm9k_cpu_irq_end, }; unsigned int rm9000_perfcount_irq; diff --git a/arch/mips/kernel/irq_cpu.c b/arch/mips/kernel/irq_cpu.c index be5ac23..fcc86b9 100644 --- a/arch/mips/kernel/irq_cpu.c +++ b/arch/mips/kernel/irq_cpu.c @@ -50,12 +50,6 @@ static inline void mask_mips_irq(unsigned int irq) irq_disable_hazard(); } -static void mips_cpu_irq_end(unsigned int irq) -{ - if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) - unmask_mips_irq(irq); -} - static struct irq_chip mips_cpu_irq_controller = { .typename = "MIPS", .ack = mask_mips_irq, @@ -63,7 +57,6 @@ static struct irq_chip mips_cpu_irq_controller = { .mask_ack = mask_mips_irq, .unmask = unmask_mips_irq, .eoi = unmask_mips_irq, - .end = mips_cpu_irq_end, }; /* @@ -96,8 +89,6 @@ static void mips_mt_cpu_irq_ack(unsigned int irq) mask_mips_mt_irq(irq); } -#define mips_mt_cpu_irq_end mips_cpu_irq_end - static struct irq_chip mips_mt_cpu_irq_controller = { .typename = "MIPS", .startup = mips_mt_cpu_irq_startup, @@ -106,7 +97,6 @@ static struct irq_chip mips_mt_cpu_irq_controller = { .mask_ack = mips_mt_cpu_irq_ack, .unmask = unmask_mips_mt_irq, .eoi = unmask_mips_mt_irq, - .end = mips_mt_cpu_irq_end, }; void __init mips_cpu_irq_init(int irq_base) diff --git a/arch/mips/lasat/interrupt.c b/arch/mips/lasat/interrupt.c index 4a84a7b..2affa5f 100644 --- a/arch/mips/lasat/interrupt.c +++ b/arch/mips/lasat/interrupt.c @@ -44,19 +44,12 @@ void enable_lasat_irq(unsigned int irq_nr) *lasat_int_mask |= (1 << irq_nr) << lasat_int_mask_shift; } -static void end_lasat_irq(unsigned int irq) -{ - if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) - enable_lasat_irq(irq); -} - static struct irq_chip lasat_irq_type = { .typename = "Lasat", .ack = disable_lasat_irq, .mask = disable_lasat_irq, .mask_ack = disable_lasat_irq, .unmask = enable_lasat_irq, - .end = end_lasat_irq, }; static inline int ls1bit32(unsigned int x) diff --git a/arch/mips/momentum/ocelot_c/cpci-irq.c b/arch/mips/momentum/ocelot_c/cpci-irq.c index e5a4a0a..bb11fef 100644 --- a/arch/mips/momentum/ocelot_c/cpci-irq.c +++ b/arch/mips/momentum/ocelot_c/cpci-irq.c @@ -66,15 +66,6 @@ static inline void unmask_cpci_irq(unsigned int irq) } /* - * End IRQ processing - */ -static void end_cpci_irq(unsigned int irq) -{ - if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) - unmask_cpci_irq(irq); -} - -/* * Interrupt handler for interrupts coming from the FPGA chip. * It could be built in ethernet ports etc... */ @@ -98,7 +89,6 @@ struct irq_chip cpci_irq_type = { .mask = mask_cpci_irq, .mask_ack = mask_cpci_irq, .unmask = unmask_cpci_irq, - .end = end_cpci_irq, }; void cpci_irq_init(void) diff --git a/arch/mips/momentum/ocelot_c/uart-irq.c b/arch/mips/momentum/ocelot_c/uart-irq.c index 0029f00..a7a80c0d 100644 --- a/arch/mips/momentum/ocelot_c/uart-irq.c +++ b/arch/mips/momentum/ocelot_c/uart-irq.c @@ -60,15 +60,6 @@ static inline void unmask_uart_irq(unsigned int irq) } /* - * End IRQ processing - */ -static void end_uart_irq(unsigned int irq) -{ - if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) - unmask_uart_irq(irq); -} - -/* * Interrupt handler for interrupts coming from the FPGA chip. */ void ll_uart_irq(void) @@ -91,7 +82,6 @@ struct irq_chip uart_irq_type = { .mask = mask_uart_irq, .mask_ack = mask_uart_irq, .unmask = unmask_uart_irq, - .end = end_uart_irq, }; void uart_irq_init(void) diff --git a/arch/mips/philips/pnx8550/common/int.c b/arch/mips/philips/pnx8550/common/int.c index 0dc2393..2c36c10 100644 --- a/arch/mips/philips/pnx8550/common/int.c +++ b/arch/mips/philips/pnx8550/common/int.c @@ -158,20 +158,12 @@ int pnx8550_set_gic_priority(int irq, int priority) return prev_priority; } -static void end_irq(unsigned int irq) -{ - if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) { - unmask_irq(irq); - } -} - static struct irq_chip level_irq_type = { .typename = "PNX Level IRQ", .ack = mask_irq, .mask = mask_irq, .mask_ack = mask_irq, .unmask = unmask_irq, - .end = end_irq, }; static struct irqaction gic_action = { diff --git a/arch/mips/sgi-ip22/ip22-int.c b/arch/mips/sgi-ip22/ip22-int.c index c7b1380..c44f8be 100644 --- a/arch/mips/sgi-ip22/ip22-int.c +++ b/arch/mips/sgi-ip22/ip22-int.c @@ -51,19 +51,12 @@ static void disable_local0_irq(unsigned int irq) sgint->imask0 &= ~(1 << (irq - SGINT_LOCAL0)); } -static void end_local0_irq (unsigned int irq) -{ - if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) - enable_local0_irq(irq); -} - static struct irq_chip ip22_local0_irq_type = { .typename = "IP22 local 0", .ack = disable_local0_irq, .mask = disable_local0_irq, .mask_ack = disable_local0_irq, .unmask = enable_local0_irq, - .end = end_local0_irq, }; static void enable_local1_irq(unsigned int irq) @@ -79,19 +72,12 @@ void disable_local1_irq(unsigned int irq) sgint->imask1 &= ~(1 << (irq - SGINT_LOCAL1)); } -static void end_local1_irq (unsigned int irq) -{ - if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) - enable_local1_irq(irq); -} - static struct irq_chip ip22_local1_irq_type = { .typename = "IP22 local 1", .ack = disable_local1_irq, .mask = disable_local1_irq, .mask_ack = disable_local1_irq, .unmask = enable_local1_irq, - .end = end_local1_irq, }; static void enable_local2_irq(unsigned int irq) @@ -107,19 +93,12 @@ void disable_local2_irq(unsigned int irq) sgint->imask0 &= ~(1 << (SGI_MAP_0_IRQ - SGINT_LOCAL0)); } -static void end_local2_irq (unsigned int irq) -{ - if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) - enable_local2_irq(irq); -} - static struct irq_chip ip22_local2_irq_type = { .typename = "IP22 local 2", .ack = disable_local2_irq, .mask = disable_local2_irq, .mask_ack = disable_local2_irq, .unmask = enable_local2_irq, - .end = end_local2_irq, }; static void enable_local3_irq(unsigned int irq) @@ -135,19 +114,12 @@ void disable_local3_irq(unsigned int irq) sgint->imask1 &= ~(1 << (SGI_MAP_1_IRQ - SGINT_LOCAL1)); } -static void end_local3_irq (unsigned int irq) -{ - if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) - enable_local3_irq(irq); -} - static struct irq_chip ip22_local3_irq_type = { .typename = "IP22 local 3", .ack = disable_local3_irq, .mask = disable_local3_irq, .mask_ack = disable_local3_irq, .unmask = enable_local3_irq, - .end = end_local3_irq, }; static void indy_local0_irqdispatch(void) diff --git a/arch/mips/sgi-ip27/ip27-irq.c b/arch/mips/sgi-ip27/ip27-irq.c index 5f8835b..319f880 100644 --- a/arch/mips/sgi-ip27/ip27-irq.c +++ b/arch/mips/sgi-ip27/ip27-irq.c @@ -332,13 +332,6 @@ static inline void disable_bridge_irq(unsigned int irq) intr_disconnect_level(cpu, swlevel); } -static void end_bridge_irq(unsigned int irq) -{ - if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)) && - irq_desc[irq].action) - enable_bridge_irq(irq); -} - static struct irq_chip bridge_irq_type = { .typename = "bridge", .startup = startup_bridge_irq, @@ -347,7 +340,6 @@ static struct irq_chip bridge_irq_type = { .mask = disable_bridge_irq, .mask_ack = disable_bridge_irq, .unmask = enable_bridge_irq, - .end = end_bridge_irq, }; void __devinit register_bridge_irq(unsigned int irq) diff --git a/arch/mips/sgi-ip27/ip27-timer.c b/arch/mips/sgi-ip27/ip27-timer.c index 7d36172..c20e989 100644 --- a/arch/mips/sgi-ip27/ip27-timer.c +++ b/arch/mips/sgi-ip27/ip27-timer.c @@ -180,10 +180,6 @@ static void disable_rt_irq(unsigned int irq) { } -static void end_rt_irq(unsigned int irq) -{ -} - static struct irq_chip rt_irq_type = { .typename = "SN HUB RT timer", .ack = disable_rt_irq, @@ -191,7 +187,6 @@ static struct irq_chip rt_irq_type = { .mask_ack = disable_rt_irq, .unmask = enable_rt_irq, .eoi = enable_rt_irq, - .end = end_rt_irq, }; static struct irqaction rt_irqaction = { diff --git a/arch/mips/tx4927/common/tx4927_irq.c b/arch/mips/tx4927/common/tx4927_irq.c index 21873de..ed4a19a 100644 --- a/arch/mips/tx4927/common/tx4927_irq.c +++ b/arch/mips/tx4927/common/tx4927_irq.c @@ -66,12 +66,10 @@ #define TX4927_IRQ_CP0_INIT ( 1 << 10 ) #define TX4927_IRQ_CP0_ENABLE ( 1 << 13 ) #define TX4927_IRQ_CP0_DISABLE ( 1 << 14 ) -#define TX4927_IRQ_CP0_ENDIRQ ( 1 << 16 ) #define TX4927_IRQ_PIC_INIT ( 1 << 20 ) #define TX4927_IRQ_PIC_ENABLE ( 1 << 23 ) #define TX4927_IRQ_PIC_DISABLE ( 1 << 24 ) -#define TX4927_IRQ_PIC_ENDIRQ ( 1 << 26 ) #define TX4927_IRQ_ALL 0xffffffff #endif @@ -82,12 +80,10 @@ static const u32 tx4927_irq_debug_flag = (TX4927_IRQ_NONE | TX4927_IRQ_WARN | TX4927_IRQ_EROR // | TX4927_IRQ_CP0_INIT // | TX4927_IRQ_CP0_ENABLE -// | TX4927_IRQ_CP0_DISABLE // | TX4927_IRQ_CP0_ENDIRQ // | TX4927_IRQ_PIC_INIT // | TX4927_IRQ_PIC_ENABLE // | TX4927_IRQ_PIC_DISABLE -// | TX4927_IRQ_PIC_ENDIRQ // | TX4927_IRQ_INIT // | TX4927_IRQ_NEST1 // | TX4927_IRQ_NEST2 @@ -114,11 +110,9 @@ static const u32 tx4927_irq_debug_flag = (TX4927_IRQ_NONE static void tx4927_irq_cp0_enable(unsigned int irq); static void tx4927_irq_cp0_disable(unsigned int irq); -static void tx4927_irq_cp0_end(unsigned int irq); static void tx4927_irq_pic_enable(unsigned int irq); static void tx4927_irq_pic_disable(unsigned int irq); -static void tx4927_irq_pic_end(unsigned int irq); /* * Kernel structs for all pic's @@ -131,7 +125,6 @@ static struct irq_chip tx4927_irq_cp0_type = { .mask = tx4927_irq_cp0_disable, .mask_ack = tx4927_irq_cp0_disable, .unmask = tx4927_irq_cp0_enable, - .end = tx4927_irq_cp0_end, }; #define TX4927_PIC_NAME "TX4927-PIC" @@ -141,7 +134,6 @@ static struct irq_chip tx4927_irq_pic_type = { .mask = tx4927_irq_pic_disable, .mask_ack = tx4927_irq_pic_disable, .unmask = tx4927_irq_pic_enable, - .end = tx4927_irq_pic_end, }; #define TX4927_PIC_ACTION(s) { no_action, 0, CPU_MASK_NONE, s, NULL, NULL } @@ -214,15 +206,6 @@ static void tx4927_irq_cp0_disable(unsigned int irq) tx4927_irq_cp0_modify(CCP0_STATUS, tx4927_irq_cp0_mask(irq), 0); } -static void tx4927_irq_cp0_end(unsigned int irq) -{ - TX4927_IRQ_DPRINTK(TX4927_IRQ_CP0_ENDIRQ, "irq=%d \n", irq); - - if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) { - tx4927_irq_cp0_enable(irq); - } -} - /* * Functions for pic */ @@ -376,15 +359,6 @@ static void tx4927_irq_pic_disable(unsigned int irq) tx4927_irq_pic_mask(irq), 0); } -static void tx4927_irq_pic_end(unsigned int irq) -{ - TX4927_IRQ_DPRINTK(TX4927_IRQ_PIC_ENDIRQ, "irq=%d\n", irq); - - if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) { - tx4927_irq_pic_enable(irq); - } -} - /* * Main init functions */ diff --git a/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c b/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c index 34cdb2a..5a5ea6c 100644 --- a/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c +++ b/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c @@ -153,7 +153,6 @@ JP7 is not bus master -- do NOT use -- only 4 pci bus master's allowed -- SouthB #define TOSHIBA_RBTX4927_IRQ_IOC_INIT ( 1 << 10 ) #define TOSHIBA_RBTX4927_IRQ_IOC_ENABLE ( 1 << 13 ) #define TOSHIBA_RBTX4927_IRQ_IOC_DISABLE ( 1 << 14 ) -#define TOSHIBA_RBTX4927_IRQ_IOC_ENDIRQ ( 1 << 16 ) #define TOSHIBA_RBTX4927_IRQ_ISA_INIT ( 1 << 20 ) #define TOSHIBA_RBTX4927_IRQ_ISA_ENABLE ( 1 << 23 ) @@ -172,7 +171,6 @@ static const u32 toshiba_rbtx4927_irq_debug_flag = // | TOSHIBA_RBTX4927_IRQ_IOC_INIT // | TOSHIBA_RBTX4927_IRQ_IOC_ENABLE // | TOSHIBA_RBTX4927_IRQ_IOC_DISABLE -// | TOSHIBA_RBTX4927_IRQ_IOC_ENDIRQ // | TOSHIBA_RBTX4927_IRQ_ISA_INIT // | TOSHIBA_RBTX4927_IRQ_ISA_ENABLE // | TOSHIBA_RBTX4927_IRQ_ISA_DISABLE @@ -223,7 +221,6 @@ extern void mask_and_ack_8259A(unsigned int irq); static void toshiba_rbtx4927_irq_ioc_enable(unsigned int irq); static void toshiba_rbtx4927_irq_ioc_disable(unsigned int irq); -static void toshiba_rbtx4927_irq_ioc_end(unsigned int irq); #ifdef CONFIG_TOSHIBA_FPCIB0 static void toshiba_rbtx4927_irq_isa_enable(unsigned int irq); @@ -239,7 +236,6 @@ static struct irq_chip toshiba_rbtx4927_irq_ioc_type = { .mask = toshiba_rbtx4927_irq_ioc_disable, .mask_ack = toshiba_rbtx4927_irq_ioc_disable, .unmask = toshiba_rbtx4927_irq_ioc_enable, - .end = toshiba_rbtx4927_irq_ioc_end, }; #define TOSHIBA_RBTX4927_IOC_INTR_ENAB 0xbc002000 #define TOSHIBA_RBTX4927_IOC_INTR_STAT 0xbc002006 @@ -388,23 +384,6 @@ static void toshiba_rbtx4927_irq_ioc_disable(unsigned int irq) TOSHIBA_RBTX4927_WR08(TOSHIBA_RBTX4927_IOC_INTR_ENAB, v); } -static void toshiba_rbtx4927_irq_ioc_end(unsigned int irq) -{ - TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_IOC_ENDIRQ, - "irq=%d\n", irq); - - if (irq < TOSHIBA_RBTX4927_IRQ_IOC_BEG - || irq > TOSHIBA_RBTX4927_IRQ_IOC_END) { - TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_EROR, - "bad irq=%d\n", irq); - panic("\n"); - } - - if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) { - toshiba_rbtx4927_irq_ioc_enable(irq); - } -} - /**********************************************************************************/ /* Functions for isa */ diff --git a/arch/mips/tx4938/common/irq.c b/arch/mips/tx4938/common/irq.c index 42e1276..a347b42 100644 --- a/arch/mips/tx4938/common/irq.c +++ b/arch/mips/tx4938/common/irq.c @@ -39,11 +39,9 @@ static void tx4938_irq_cp0_enable(unsigned int irq); static void tx4938_irq_cp0_disable(unsigned int irq); -static void tx4938_irq_cp0_end(unsigned int irq); static void tx4938_irq_pic_enable(unsigned int irq); static void tx4938_irq_pic_disable(unsigned int irq); -static void tx4938_irq_pic_end(unsigned int irq); /**********************************************************************************/ /* Kernel structs for all pic's */ @@ -56,7 +54,6 @@ static struct irq_chip tx4938_irq_cp0_type = { .mask = tx4938_irq_cp0_disable, .mask_ack = tx4938_irq_cp0_disable, .unmask = tx4938_irq_cp0_enable, - .end = tx4938_irq_cp0_end, }; #define TX4938_PIC_NAME "TX4938-PIC" @@ -66,7 +63,6 @@ static struct irq_chip tx4938_irq_pic_type = { .mask = tx4938_irq_pic_disable, .mask_ack = tx4938_irq_pic_disable, .unmask = tx4938_irq_pic_enable, - .end = tx4938_irq_pic_end, }; static struct irqaction tx4938_irq_pic_action = { @@ -104,14 +100,6 @@ tx4938_irq_cp0_disable(unsigned int irq) clear_c0_status(tx4938_irq_cp0_mask(irq)); } -static void -tx4938_irq_cp0_end(unsigned int irq) -{ - if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) { - tx4938_irq_cp0_enable(irq); - } -} - /**********************************************************************************/ /* Functions for pic */ /**********************************************************************************/ @@ -269,14 +257,6 @@ tx4938_irq_pic_disable(unsigned int irq) tx4938_irq_pic_mask(irq), 0); } -static void -tx4938_irq_pic_end(unsigned int irq) -{ - if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) { - tx4938_irq_pic_enable(irq); - } -} - /**********************************************************************************/ /* Main init functions */ /**********************************************************************************/ diff --git a/arch/mips/tx4938/toshiba_rbtx4938/irq.c b/arch/mips/tx4938/toshiba_rbtx4938/irq.c index 8c87a35..b6f363d 100644 --- a/arch/mips/tx4938/toshiba_rbtx4938/irq.c +++ b/arch/mips/tx4938/toshiba_rbtx4938/irq.c @@ -89,7 +89,6 @@ IRQ Device static void toshiba_rbtx4938_irq_ioc_enable(unsigned int irq); static void toshiba_rbtx4938_irq_ioc_disable(unsigned int irq); -static void toshiba_rbtx4938_irq_ioc_end(unsigned int irq); #define TOSHIBA_RBTX4938_IOC_NAME "RBTX4938-IOC" static struct irq_chip toshiba_rbtx4938_irq_ioc_type = { @@ -98,7 +97,6 @@ static struct irq_chip toshiba_rbtx4938_irq_ioc_type = { .mask = toshiba_rbtx4938_irq_ioc_disable, .mask_ack = toshiba_rbtx4938_irq_ioc_disable, .unmask = toshiba_rbtx4938_irq_ioc_enable, - .end = toshiba_rbtx4938_irq_ioc_end, }; #define TOSHIBA_RBTX4938_IOC_INTR_ENAB 0xb7f02000 @@ -167,14 +165,6 @@ toshiba_rbtx4938_irq_ioc_disable(unsigned int irq) TX4938_RD08(TOSHIBA_RBTX4938_IOC_INTR_ENAB); } -static void -toshiba_rbtx4938_irq_ioc_end(unsigned int irq) -{ - if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) { - toshiba_rbtx4938_irq_ioc_enable(irq); - } -} - extern void __init txx9_spi_irqinit(int irc_irq); void __init arch_init_irq(void) diff --git a/arch/mips/vr41xx/Kconfig b/arch/mips/vr41xx/Kconfig index 92f41f6..c8dfd80 100644 --- a/arch/mips/vr41xx/Kconfig +++ b/arch/mips/vr41xx/Kconfig @@ -6,6 +6,7 @@ config CASIO_E55 select ISA select SYS_SUPPORTS_32BIT_KERNEL select SYS_SUPPORTS_LITTLE_ENDIAN + select GENERIC_HARDIRQS_NO__DO_IRQ config IBM_WORKPAD bool "Support for IBM WorkPad z50" @@ -15,6 +16,7 @@ config IBM_WORKPAD select ISA select SYS_SUPPORTS_32BIT_KERNEL select SYS_SUPPORTS_LITTLE_ENDIAN + select GENERIC_HARDIRQS_NO__DO_IRQ config NEC_CMBVR4133 bool "Support for NEC CMB-VR4133" @@ -39,6 +41,7 @@ config TANBAC_TB022X select IRQ_CPU select SYS_SUPPORTS_32BIT_KERNEL select SYS_SUPPORTS_LITTLE_ENDIAN + select GENERIC_HARDIRQS_NO__DO_IRQ help The TANBAC VR4131 multichip module(TB0225) and the TANBAC VR4131DIMM(TB0229) are MIPS-based platforms @@ -71,6 +74,7 @@ config VICTOR_MPC30X select IRQ_CPU select SYS_SUPPORTS_32BIT_KERNEL select SYS_SUPPORTS_LITTLE_ENDIAN + select GENERIC_HARDIRQS_NO__DO_IRQ config ZAO_CAPCELLA bool "Support for ZAO Networks Capcella" @@ -80,6 +84,7 @@ config ZAO_CAPCELLA select IRQ_CPU select SYS_SUPPORTS_32BIT_KERNEL select SYS_SUPPORTS_LITTLE_ENDIAN + select GENERIC_HARDIRQS_NO__DO_IRQ config PCI_VR41XX bool "Add PCI control unit support of NEC VR4100 series" diff --git a/arch/mips/vr41xx/common/icu.c b/arch/mips/vr41xx/common/icu.c index 54b92a7..c075261 100644 --- a/arch/mips/vr41xx/common/icu.c +++ b/arch/mips/vr41xx/common/icu.c @@ -427,19 +427,12 @@ static void enable_sysint1_irq(unsigned int irq) icu1_set(MSYSINT1REG, 1 << SYSINT1_IRQ_TO_PIN(irq)); } -static void end_sysint1_irq(unsigned int irq) -{ - if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) - icu1_set(MSYSINT1REG, 1 << SYSINT1_IRQ_TO_PIN(irq)); -} - static struct irq_chip sysint1_irq_type = { .typename = "SYSINT1", .ack = disable_sysint1_irq, .mask = disable_sysint1_irq, .mask_ack = disable_sysint1_irq, .unmask = enable_sysint1_irq, - .end = end_sysint1_irq, }; static void disable_sysint2_irq(unsigned int irq) @@ -452,19 +445,12 @@ static void enable_sysint2_irq(unsigned int irq) icu2_set(MSYSINT2REG, 1 << SYSINT2_IRQ_TO_PIN(irq)); } -static void end_sysint2_irq(unsigned int irq) -{ - if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) - icu2_set(MSYSINT2REG, 1 << SYSINT2_IRQ_TO_PIN(irq)); -} - static struct irq_chip sysint2_irq_type = { .typename = "SYSINT2", .ack = disable_sysint2_irq, .mask = disable_sysint2_irq, .mask_ack = disable_sysint2_irq, .unmask = enable_sysint2_irq, - .end = end_sysint2_irq, }; static inline int set_sysint1_assign(unsigned int irq, unsigned char assign) -- cgit v1.1 From 49afb1f67b42c4240fef9d2d8b76c317c56a189d Mon Sep 17 00:00:00 2001 From: "Maciej W. Rozycki" Date: Wed, 6 Dec 2006 11:50:23 +0000 Subject: [MIPS] *-berr: Header inclusions for DEC bus error handlers A fixup to add missing header inclusions for bus error handlers for DECstation system after the recent switch to get_irq_regs(). Signed-off-by: Maciej W. Rozycki Signed-off-by: Ralf Baechle --- arch/mips/dec/ecc-berr.c | 1 + arch/mips/dec/kn01-berr.c | 2 ++ 2 files changed, 3 insertions(+) (limited to 'arch/mips') diff --git a/arch/mips/dec/ecc-berr.c b/arch/mips/dec/ecc-berr.c index c8430c0..6d55e8a 100644 --- a/arch/mips/dec/ecc-berr.c +++ b/arch/mips/dec/ecc-berr.c @@ -25,6 +25,7 @@ #include #include #include +#include #include #include diff --git a/arch/mips/dec/kn01-berr.c b/arch/mips/dec/kn01-berr.c index f19b461..d3b8002 100644 --- a/arch/mips/dec/kn01-berr.c +++ b/arch/mips/dec/kn01-berr.c @@ -20,8 +20,10 @@ #include #include +#include #include #include +#include #include #include #include -- cgit v1.1 From 2cafe978462bc4016392aa330bf501a674679a86 Mon Sep 17 00:00:00 2001 From: Atsushi Nemoto Date: Thu, 7 Dec 2006 02:04:17 +0900 Subject: [MIPS] Import updates from i386's i8259.c Import many updates from i386's i8259.c, especially genirq transitions. Signed-off-by: Atsushi Nemoto Signed-off-by: Ralf Baechle --- arch/mips/kernel/i8259.c | 162 +++++++++++++++++++++++++---------------------- 1 file changed, 86 insertions(+), 76 deletions(-) (limited to 'arch/mips') diff --git a/arch/mips/kernel/i8259.c b/arch/mips/kernel/i8259.c index 2526c0c..b59a676 100644 --- a/arch/mips/kernel/i8259.c +++ b/arch/mips/kernel/i8259.c @@ -19,9 +19,6 @@ #include #include -void enable_8259A_irq(unsigned int irq); -void disable_8259A_irq(unsigned int irq); - /* * This is the 'legacy' 8259A Programmable Interrupt Controller, * present in the majority of PC/AT boxes. @@ -31,23 +28,16 @@ void disable_8259A_irq(unsigned int irq); * moves to arch independent land */ +static int i8259A_auto_eoi; DEFINE_SPINLOCK(i8259A_lock); - -static void end_8259A_irq (unsigned int irq) -{ - if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)) && - irq_desc[irq].action) - enable_8259A_irq(irq); -} - +/* some platforms call this... */ void mask_and_ack_8259A(unsigned int); -static struct irq_chip i8259A_irq_type = { - .typename = "XT-PIC", - .enable = enable_8259A_irq, - .disable = disable_8259A_irq, - .ack = mask_and_ack_8259A, - .end = end_8259A_irq, +static struct irq_chip i8259A_chip = { + .name = "XT-PIC", + .mask = disable_8259A_irq, + .unmask = enable_8259A_irq, + .mask_ack = mask_and_ack_8259A, }; /* @@ -59,8 +49,8 @@ static struct irq_chip i8259A_irq_type = { */ static unsigned int cached_irq_mask = 0xffff; -#define cached_21 (cached_irq_mask) -#define cached_A1 (cached_irq_mask >> 8) +#define cached_master_mask (cached_irq_mask) +#define cached_slave_mask (cached_irq_mask >> 8) void disable_8259A_irq(unsigned int irq) { @@ -70,9 +60,9 @@ void disable_8259A_irq(unsigned int irq) spin_lock_irqsave(&i8259A_lock, flags); cached_irq_mask |= mask; if (irq & 8) - outb(cached_A1,0xA1); + outb(cached_slave_mask, PIC_SLAVE_IMR); else - outb(cached_21,0x21); + outb(cached_master_mask, PIC_MASTER_IMR); spin_unlock_irqrestore(&i8259A_lock, flags); } @@ -84,9 +74,9 @@ void enable_8259A_irq(unsigned int irq) spin_lock_irqsave(&i8259A_lock, flags); cached_irq_mask &= mask; if (irq & 8) - outb(cached_A1,0xA1); + outb(cached_slave_mask, PIC_SLAVE_IMR); else - outb(cached_21,0x21); + outb(cached_master_mask, PIC_MASTER_IMR); spin_unlock_irqrestore(&i8259A_lock, flags); } @@ -98,9 +88,9 @@ int i8259A_irq_pending(unsigned int irq) spin_lock_irqsave(&i8259A_lock, flags); if (irq < 8) - ret = inb(0x20) & mask; + ret = inb(PIC_MASTER_CMD) & mask; else - ret = inb(0xA0) & (mask >> 8); + ret = inb(PIC_SLAVE_CMD) & (mask >> 8); spin_unlock_irqrestore(&i8259A_lock, flags); return ret; @@ -109,7 +99,7 @@ int i8259A_irq_pending(unsigned int irq) void make_8259A_irq(unsigned int irq) { disable_irq_nosync(irq); - set_irq_chip(irq, &i8259A_irq_type); + set_irq_chip_and_handler(irq, &i8259A_chip, handle_level_irq); enable_irq(irq); } @@ -125,14 +115,14 @@ static inline int i8259A_irq_real(unsigned int irq) int irqmask = 1 << irq; if (irq < 8) { - outb(0x0B,0x20); /* ISR register */ - value = inb(0x20) & irqmask; - outb(0x0A,0x20); /* back to the IRR register */ + outb(0x0B,PIC_MASTER_CMD); /* ISR register */ + value = inb(PIC_MASTER_CMD) & irqmask; + outb(0x0A,PIC_MASTER_CMD); /* back to the IRR register */ return value; } - outb(0x0B,0xA0); /* ISR register */ - value = inb(0xA0) & (irqmask >> 8); - outb(0x0A,0xA0); /* back to the IRR register */ + outb(0x0B,PIC_SLAVE_CMD); /* ISR register */ + value = inb(PIC_SLAVE_CMD) & (irqmask >> 8); + outb(0x0A,PIC_SLAVE_CMD); /* back to the IRR register */ return value; } @@ -149,17 +139,19 @@ void mask_and_ack_8259A(unsigned int irq) spin_lock_irqsave(&i8259A_lock, flags); /* - * Lightweight spurious IRQ detection. We do not want to overdo - * spurious IRQ handling - it's usually a sign of hardware problems, so - * we only do the checks we can do without slowing down good hardware - * nnecesserily. + * Lightweight spurious IRQ detection. We do not want + * to overdo spurious IRQ handling - it's usually a sign + * of hardware problems, so we only do the checks we can + * do without slowing down good hardware unnecessarily. * - * Note that IRQ7 and IRQ15 (the two spurious IRQs usually resulting - * rom the 8259A-1|2 PICs) occur even if the IRQ is masked in the 8259A. - * Thus we can check spurious 8259A IRQs without doing the quite slow - * i8259A_irq_real() call for every IRQ. This does not cover 100% of - * spurious interrupts, but should be enough to warn the user that - * there is something bad going on ... + * Note that IRQ7 and IRQ15 (the two spurious IRQs + * usually resulting from the 8259A-1|2 PICs) occur + * even if the IRQ is masked in the 8259A. Thus we + * can check spurious 8259A IRQs without doing the + * quite slow i8259A_irq_real() call for every IRQ. + * This does not cover 100% of spurious interrupts, + * but should be enough to warn the user that there + * is something bad going on ... */ if (cached_irq_mask & irqmask) goto spurious_8259A_irq; @@ -167,14 +159,14 @@ void mask_and_ack_8259A(unsigned int irq) handle_real_irq: if (irq & 8) { - inb(0xA1); /* DUMMY - (do we need this?) */ - outb(cached_A1,0xA1); - outb(0x60+(irq&7),0xA0);/* 'Specific EOI' to slave */ - outb(0x62,0x20); /* 'Specific EOI' to master-IRQ2 */ + inb(PIC_SLAVE_IMR); /* DUMMY - (do we need this?) */ + outb(cached_slave_mask, PIC_SLAVE_IMR); + outb(0x60+(irq&7),PIC_SLAVE_CMD);/* 'Specific EOI' to slave */ + outb(0x60+PIC_CASCADE_IR,PIC_MASTER_CMD); /* 'Specific EOI' to master-IRQ2 */ } else { - inb(0x21); /* DUMMY - (do we need this?) */ - outb(cached_21,0x21); - outb(0x60+irq,0x20); /* 'Specific EOI' to master */ + inb(PIC_MASTER_IMR); /* DUMMY - (do we need this?) */ + outb(cached_master_mask, PIC_MASTER_IMR); + outb(0x60+irq,PIC_MASTER_CMD); /* 'Specific EOI to master */ } #ifdef CONFIG_MIPS_MT_SMTC if (irq_hwmask[irq] & ST0_IM) @@ -195,7 +187,7 @@ spurious_8259A_irq: goto handle_real_irq; { - static int spurious_irq_mask = 0; + static int spurious_irq_mask; /* * At this point we can be sure the IRQ is spurious, * lets ACK and report it. [once per IRQ] @@ -216,13 +208,25 @@ spurious_8259A_irq: static int i8259A_resume(struct sys_device *dev) { - init_8259A(0); + init_8259A(i8259A_auto_eoi); + return 0; +} + +static int i8259A_shutdown(struct sys_device *dev) +{ + /* Put the i8259A into a quiescent state that + * the kernel initialization code can get it + * out of. + */ + outb(0xff, PIC_MASTER_IMR); /* mask all of 8259A-1 */ + outb(0xff, PIC_SLAVE_IMR); /* mask all of 8259A-1 */ return 0; } static struct sysdev_class i8259_sysdev_class = { set_kset_name("i8259"), .resume = i8259A_resume, + .shutdown = i8259A_shutdown, }; static struct sys_device device_i8259A = { @@ -244,41 +248,41 @@ void __init init_8259A(int auto_eoi) { unsigned long flags; + i8259A_auto_eoi = auto_eoi; + spin_lock_irqsave(&i8259A_lock, flags); - outb(0xff, 0x21); /* mask all of 8259A-1 */ - outb(0xff, 0xA1); /* mask all of 8259A-2 */ + outb(0xff, PIC_MASTER_IMR); /* mask all of 8259A-1 */ + outb(0xff, PIC_SLAVE_IMR); /* mask all of 8259A-2 */ /* * outb_p - this has to work on a wide range of PC hardware. */ - outb_p(0x11, 0x20); /* ICW1: select 8259A-1 init */ - outb_p(0x00, 0x21); /* ICW2: 8259A-1 IR0-7 mapped to 0x00-0x07 */ - outb_p(0x04, 0x21); /* 8259A-1 (the master) has a slave on IR2 */ - if (auto_eoi) - outb_p(0x03, 0x21); /* master does Auto EOI */ - else - outb_p(0x01, 0x21); /* master expects normal EOI */ - - outb_p(0x11, 0xA0); /* ICW1: select 8259A-2 init */ - outb_p(0x08, 0xA1); /* ICW2: 8259A-2 IR0-7 mapped to 0x08-0x0f */ - outb_p(0x02, 0xA1); /* 8259A-2 is a slave on master's IR2 */ - outb_p(0x01, 0xA1); /* (slave's support for AEOI in flat mode - is to be investigated) */ - + outb_p(0x11, PIC_MASTER_CMD); /* ICW1: select 8259A-1 init */ + outb_p(I8259A_IRQ_BASE + 0, PIC_MASTER_IMR); /* ICW2: 8259A-1 IR0 mapped to I8259A_IRQ_BASE + 0x00 */ + outb_p(1U << PIC_CASCADE_IR, PIC_MASTER_IMR); /* 8259A-1 (the master) has a slave on IR2 */ + if (auto_eoi) /* master does Auto EOI */ + outb_p(MASTER_ICW4_DEFAULT | PIC_ICW4_AEOI, PIC_MASTER_IMR); + else /* master expects normal EOI */ + outb_p(MASTER_ICW4_DEFAULT, PIC_MASTER_IMR); + + outb_p(0x11, PIC_SLAVE_CMD); /* ICW1: select 8259A-2 init */ + outb_p(I8259A_IRQ_BASE + 8, PIC_SLAVE_IMR); /* ICW2: 8259A-2 IR0 mapped to I8259A_IRQ_BASE + 0x08 */ + outb_p(PIC_CASCADE_IR, PIC_SLAVE_IMR); /* 8259A-2 is a slave on master's IR2 */ + outb_p(SLAVE_ICW4_DEFAULT, PIC_SLAVE_IMR); /* (slave's support for AEOI in flat mode is to be investigated) */ if (auto_eoi) /* - * in AEOI mode we just have to mask the interrupt + * In AEOI mode we just have to mask the interrupt * when acking. */ - i8259A_irq_type.ack = disable_8259A_irq; + i8259A_chip.mask_ack = disable_8259A_irq; else - i8259A_irq_type.ack = mask_and_ack_8259A; + i8259A_chip.mask_ack = mask_and_ack_8259A; udelay(100); /* wait for 8259A to initialize */ - outb(cached_21, 0x21); /* restore master IRQ mask */ - outb(cached_A1, 0xA1); /* restore slave IRQ mask */ + outb(cached_master_mask, PIC_MASTER_IMR); /* restore master IRQ mask */ + outb(cached_slave_mask, PIC_SLAVE_IMR); /* restore slave IRQ mask */ spin_unlock_irqrestore(&i8259A_lock, flags); } @@ -291,11 +295,17 @@ static struct irqaction irq2 = { }; static struct resource pic1_io_resource = { - .name = "pic1", .start = 0x20, .end = 0x21, .flags = IORESOURCE_BUSY + .name = "pic1", + .start = PIC_MASTER_CMD, + .end = PIC_MASTER_IMR, + .flags = IORESOURCE_BUSY }; static struct resource pic2_io_resource = { - .name = "pic2", .start = 0xa0, .end = 0xa1, .flags = IORESOURCE_BUSY + .name = "pic2", + .start = PIC_SLAVE_CMD, + .end = PIC_SLAVE_IMR, + .flags = IORESOURCE_BUSY }; /* @@ -313,7 +323,7 @@ void __init init_i8259_irqs (void) init_8259A(0); for (i = 0; i < 16; i++) - set_irq_chip(i, &i8259A_irq_type); + set_irq_chip_and_handler(i, &i8259A_chip, handle_level_irq); - setup_irq(2, &irq2); + setup_irq(PIC_CASCADE_IR, &irq2); } -- cgit v1.1 From a866374aecc90c7d90619727ccd851ac096b2fc7 Mon Sep 17 00:00:00 2001 From: Peter Zijlstra Date: Wed, 6 Dec 2006 20:32:20 -0800 Subject: [PATCH] mm: pagefault_{disable,enable}() Introduce pagefault_{disable,enable}() and use these where previously we did manual preempt increments/decrements to make the pagefault handler do the atomic thing. Currently they still rely on the increased preempt count, but do not rely on the disabled preemption, this might go away in the future. (NOTE: the extra barrier() in pagefault_disable might fix some holes on machines which have too many registers for their own good) [heiko.carstens@de.ibm.com: s390 fix] Signed-off-by: Peter Zijlstra Acked-by: Nick Piggin Cc: Martin Schwidefsky Signed-off-by: Heiko Carstens Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- arch/mips/mm/highmem.c | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) (limited to 'arch/mips') diff --git a/arch/mips/mm/highmem.c b/arch/mips/mm/highmem.c index 99ebf3c..675502a 100644 --- a/arch/mips/mm/highmem.c +++ b/arch/mips/mm/highmem.c @@ -39,7 +39,7 @@ void *__kmap_atomic(struct page *page, enum km_type type) unsigned long vaddr; /* even !CONFIG_PREEMPT needs this, for in_atomic in do_page_fault */ - inc_preempt_count(); + pagefault_disable(); if (!PageHighMem(page)) return page_address(page); @@ -62,8 +62,7 @@ void __kunmap_atomic(void *kvaddr, enum km_type type) enum fixed_addresses idx = type + KM_TYPE_NR*smp_processor_id(); if (vaddr < FIXADDR_START) { // FIXME - dec_preempt_count(); - preempt_check_resched(); + pagefault_enable(); return; } @@ -78,8 +77,7 @@ void __kunmap_atomic(void *kvaddr, enum km_type type) local_flush_tlb_one(vaddr); #endif - dec_preempt_count(); - preempt_check_resched(); + pagefault_enable(); } #ifndef CONFIG_LIMITED_DMA @@ -92,7 +90,7 @@ void *kmap_atomic_pfn(unsigned long pfn, enum km_type type) enum fixed_addresses idx; unsigned long vaddr; - inc_preempt_count(); + pagefault_disable(); idx = type + KM_TYPE_NR*smp_processor_id(); vaddr = __fix_to_virt(FIX_KMAP_BEGIN + idx); -- cgit v1.1 From 386d9a7edd9f3492c99124b0a659e9ed7abb30f9 Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Wed, 6 Dec 2006 20:37:53 -0800 Subject: [PATCH] elf: Always define elf_addr_t in linux/elf.h Define elf_addr_t in linux/elf.h. The size of the type is determined using ELF_CLASS. This allows us to remove the defines that today are spread all over .c and .h files. Signed-off-by: Magnus Damm Cc: Daniel Jacobowitz Cc: Roland McGrath Cc: Jakub Jelinek Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- arch/mips/kernel/binfmt_elfn32.c | 1 - arch/mips/kernel/binfmt_elfo32.c | 1 - arch/mips/kernel/irixelf.c | 4 ---- 3 files changed, 6 deletions(-) (limited to 'arch/mips') diff --git a/arch/mips/kernel/binfmt_elfn32.c b/arch/mips/kernel/binfmt_elfn32.c index 4a9f1ec..9b34238 100644 --- a/arch/mips/kernel/binfmt_elfn32.c +++ b/arch/mips/kernel/binfmt_elfn32.c @@ -90,7 +90,6 @@ struct elf_prpsinfo32 char pr_psargs[ELF_PRARGSZ]; /* initial part of arg list */ }; -#define elf_addr_t u32 #define elf_caddr_t u32 #define init_elf_binfmt init_elfn32_binfmt diff --git a/arch/mips/kernel/binfmt_elfo32.c b/arch/mips/kernel/binfmt_elfo32.c index e318137..993f7ec 100644 --- a/arch/mips/kernel/binfmt_elfo32.c +++ b/arch/mips/kernel/binfmt_elfo32.c @@ -92,7 +92,6 @@ struct elf_prpsinfo32 char pr_psargs[ELF_PRARGSZ]; /* initial part of arg list */ }; -#define elf_addr_t u32 #define elf_caddr_t u32 #define init_elf_binfmt init_elf32_binfmt diff --git a/arch/mips/kernel/irixelf.c b/arch/mips/kernel/irixelf.c index ab12c8f..a82fae2 100644 --- a/arch/mips/kernel/irixelf.c +++ b/arch/mips/kernel/irixelf.c @@ -52,10 +52,6 @@ static struct linux_binfmt irix_format = { irix_core_dump, PAGE_SIZE }; -#ifndef elf_addr_t -#define elf_addr_t unsigned long -#endif - #ifdef DEBUG /* Debugging routines. */ static char *get_elf_p_type(Elf32_Word p_type) -- cgit v1.1 From 584236ac7cdddeec0fdff25d2e475471ef91d028 Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Wed, 6 Dec 2006 20:37:56 -0800 Subject: [PATCH] elf: include terminating zero in n_namesz The ELF32 spec says we should plus we include the zero on other platforms. Signed-off-by: Magnus Damm Cc: Daniel Jacobowitz Cc: Roland McGrath Cc: Jakub Jelinek Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- arch/mips/kernel/irixelf.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/mips') diff --git a/arch/mips/kernel/irixelf.c b/arch/mips/kernel/irixelf.c index a82fae2..1bbefbf 100644 --- a/arch/mips/kernel/irixelf.c +++ b/arch/mips/kernel/irixelf.c @@ -1009,7 +1009,7 @@ static int notesize(struct memelfnote *en) int sz; sz = sizeof(struct elf_note); - sz += roundup(strlen(en->name), 4); + sz += roundup(strlen(en->name) + 1, 4); sz += roundup(en->datasz, 4); return sz; @@ -1028,7 +1028,7 @@ static int writenote(struct memelfnote *men, struct file *file) { struct elf_note en; - en.n_namesz = strlen(men->name); + en.n_namesz = strlen(men->name) + 1; en.n_descsz = men->datasz; en.n_type = men->type; -- cgit v1.1 From f67637ee4b5d90d41160d755b9a8cca18c394586 Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Wed, 6 Dec 2006 20:38:54 -0800 Subject: [PATCH] Add struct dev pointer to dma_is_consistent() dma_is_consistent() is ill-designed in that it does not have a struct device pointer argument which makes proper support for systems that consist of a mix of coherent and non-coherent DMA devices hard. Change dma_is_consistent to take a struct device pointer as first argument and fix the sole caller to pass it. Signed-off-by: Ralf Baechle Cc: James Bottomley Cc: "David S. Miller" Cc: Greg KH Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- arch/mips/mm/dma-coherent.c | 2 +- arch/mips/mm/dma-ip27.c | 2 +- arch/mips/mm/dma-ip32.c | 2 +- arch/mips/mm/dma-noncoherent.c | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) (limited to 'arch/mips') diff --git a/arch/mips/mm/dma-coherent.c b/arch/mips/mm/dma-coherent.c index 7fa5fd1..18bc83e 100644 --- a/arch/mips/mm/dma-coherent.c +++ b/arch/mips/mm/dma-coherent.c @@ -190,7 +190,7 @@ int dma_supported(struct device *dev, u64 mask) EXPORT_SYMBOL(dma_supported); -int dma_is_consistent(dma_addr_t dma_addr) +int dma_is_consistent(struct device *dev, dma_addr_t dma_addr) { return 1; } diff --git a/arch/mips/mm/dma-ip27.c b/arch/mips/mm/dma-ip27.c index 8da19fd..8e9a5a8 100644 --- a/arch/mips/mm/dma-ip27.c +++ b/arch/mips/mm/dma-ip27.c @@ -197,7 +197,7 @@ int dma_supported(struct device *dev, u64 mask) EXPORT_SYMBOL(dma_supported); -int dma_is_consistent(dma_addr_t dma_addr) +int dma_is_consistent(struct device *dev, dma_addr_t dma_addr) { return 1; } diff --git a/arch/mips/mm/dma-ip32.c b/arch/mips/mm/dma-ip32.c index ec54ed0..08720a4 100644 --- a/arch/mips/mm/dma-ip32.c +++ b/arch/mips/mm/dma-ip32.c @@ -363,7 +363,7 @@ int dma_supported(struct device *dev, u64 mask) EXPORT_SYMBOL(dma_supported); -int dma_is_consistent(dma_addr_t dma_addr) +int dma_is_consistent(struct device *dev, dma_addr_t dma_addr) { return 1; } diff --git a/arch/mips/mm/dma-noncoherent.c b/arch/mips/mm/dma-noncoherent.c index 2eeffe5..4a3efc6 100644 --- a/arch/mips/mm/dma-noncoherent.c +++ b/arch/mips/mm/dma-noncoherent.c @@ -299,7 +299,7 @@ int dma_supported(struct device *dev, u64 mask) EXPORT_SYMBOL(dma_supported); -int dma_is_consistent(dma_addr_t dma_addr) +int dma_is_consistent(struct device *dev, dma_addr_t dma_addr) { return 1; } -- cgit v1.1 From d3fa72e4556ec1f04e46a0d561d9e785ecaa173d Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Wed, 6 Dec 2006 20:38:56 -0800 Subject: [PATCH] Pass struct dev pointer to dma_cache_sync() Pass struct dev pointer to dma_cache_sync() dma_cache_sync() is ill-designed in that it does not have a struct device pointer argument which makes proper support for systems that consist of a mix of coherent and non-coherent DMA devices hard. Change dma_cache_sync to take a struct device pointer as first argument and fix all its callers to pass it. Signed-off-by: Ralf Baechle Cc: James Bottomley Cc: "David S. Miller" Cc: Greg KH Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- arch/mips/mm/dma-coherent.c | 2 +- arch/mips/mm/dma-ip27.c | 2 +- arch/mips/mm/dma-ip32.c | 3 ++- arch/mips/mm/dma-noncoherent.c | 3 ++- 4 files changed, 6 insertions(+), 4 deletions(-) (limited to 'arch/mips') diff --git a/arch/mips/mm/dma-coherent.c b/arch/mips/mm/dma-coherent.c index 18bc83e..5697c6e 100644 --- a/arch/mips/mm/dma-coherent.c +++ b/arch/mips/mm/dma-coherent.c @@ -197,7 +197,7 @@ int dma_is_consistent(struct device *dev, dma_addr_t dma_addr) EXPORT_SYMBOL(dma_is_consistent); -void dma_cache_sync(void *vaddr, size_t size, +void dma_cache_sync(struct device *dev, void *vaddr, size_t size, enum dma_data_direction direction) { BUG_ON(direction == DMA_NONE); diff --git a/arch/mips/mm/dma-ip27.c b/arch/mips/mm/dma-ip27.c index 8e9a5a8..f088344 100644 --- a/arch/mips/mm/dma-ip27.c +++ b/arch/mips/mm/dma-ip27.c @@ -204,7 +204,7 @@ int dma_is_consistent(struct device *dev, dma_addr_t dma_addr) EXPORT_SYMBOL(dma_is_consistent); -void dma_cache_sync(void *vaddr, size_t size, +void dma_cache_sync(struct device *dev, void *vaddr, size_t size, enum dma_data_direction direction) { BUG_ON(direction == DMA_NONE); diff --git a/arch/mips/mm/dma-ip32.c b/arch/mips/mm/dma-ip32.c index 08720a4..b42b6f7 100644 --- a/arch/mips/mm/dma-ip32.c +++ b/arch/mips/mm/dma-ip32.c @@ -370,7 +370,8 @@ int dma_is_consistent(struct device *dev, dma_addr_t dma_addr) EXPORT_SYMBOL(dma_is_consistent); -void dma_cache_sync(void *vaddr, size_t size, enum dma_data_direction direction) +void dma_cache_sync(struct device *dev, void *vaddr, size_t size, + enum dma_data_direction direction) { if (direction == DMA_NONE) return; diff --git a/arch/mips/mm/dma-noncoherent.c b/arch/mips/mm/dma-noncoherent.c index 4a3efc6..8cecef0 100644 --- a/arch/mips/mm/dma-noncoherent.c +++ b/arch/mips/mm/dma-noncoherent.c @@ -306,7 +306,8 @@ int dma_is_consistent(struct device *dev, dma_addr_t dma_addr) EXPORT_SYMBOL(dma_is_consistent); -void dma_cache_sync(void *vaddr, size_t size, enum dma_data_direction direction) +void dma_cache_sync(struct device *dev, void *vaddr, size_t size, + enum dma_data_direction direction) { if (direction == DMA_NONE) return; -- cgit v1.1 From 1b04fe9a8ef10774174897b15d753b9de85fe9e9 Mon Sep 17 00:00:00 2001 From: Josef Sipek Date: Fri, 8 Dec 2006 02:37:20 -0800 Subject: [PATCH] struct path: convert mips Signed-off-by: Josef Sipek Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- arch/mips/kernel/rtlx.c | 6 +++--- arch/mips/kernel/sysirix.c | 10 +++++----- arch/mips/kernel/vpe.c | 2 +- arch/mips/lasat/sysctl.c | 6 +++--- 4 files changed, 12 insertions(+), 12 deletions(-) (limited to 'arch/mips') diff --git a/arch/mips/kernel/rtlx.c b/arch/mips/kernel/rtlx.c index 8c8c832..5a99e3e 100644 --- a/arch/mips/kernel/rtlx.c +++ b/arch/mips/kernel/rtlx.c @@ -415,7 +415,7 @@ static unsigned int file_poll(struct file *file, poll_table * wait) int minor; unsigned int mask = 0; - minor = iminor(file->f_dentry->d_inode); + minor = iminor(file->f_path.dentry->d_inode); poll_wait(file, &channel_wqs[minor].rt_queue, wait); poll_wait(file, &channel_wqs[minor].lx_queue, wait); @@ -437,7 +437,7 @@ static unsigned int file_poll(struct file *file, poll_table * wait) static ssize_t file_read(struct file *file, char __user * buffer, size_t count, loff_t * ppos) { - int minor = iminor(file->f_dentry->d_inode); + int minor = iminor(file->f_path.dentry->d_inode); /* data available? */ if (!rtlx_read_poll(minor, (file->f_flags & O_NONBLOCK) ? 0 : 1)) { @@ -454,7 +454,7 @@ static ssize_t file_write(struct file *file, const char __user * buffer, struct rtlx_channel *rt; DECLARE_WAITQUEUE(wait, current); - minor = iminor(file->f_dentry->d_inode); + minor = iminor(file->f_path.dentry->d_inode); rt = &rtlx->channel[minor]; /* any space left... */ diff --git a/arch/mips/kernel/sysirix.c b/arch/mips/kernel/sysirix.c index 93c74fe..6c2406a 100644 --- a/arch/mips/kernel/sysirix.c +++ b/arch/mips/kernel/sysirix.c @@ -732,7 +732,7 @@ asmlinkage int irix_fstatfs(unsigned int fd, struct irix_statfs __user *buf) goto out; } - error = vfs_statfs(file->f_dentry, &kbuf); + error = vfs_statfs(file->f_path.dentry, &kbuf); if (error) goto out_f; @@ -1041,7 +1041,7 @@ asmlinkage unsigned long irix_mmap32(unsigned long addr, size_t len, int prot, unsigned long old_pos; long max_size = offset + len; - if (max_size > file->f_dentry->d_inode->i_size) { + if (max_size > file->f_path.dentry->d_inode->i_size) { old_pos = sys_lseek (fd, max_size - 1, 0); sys_write (fd, (void __user *) "", 1); sys_lseek (fd, old_pos, 0); @@ -1406,7 +1406,7 @@ asmlinkage int irix_fstatvfs(int fd, struct irix_statvfs __user *buf) error = -EBADF; goto out; } - error = vfs_statfs(file->f_dentry, &kbuf); + error = vfs_statfs(file->f_path.dentry, &kbuf); if (error) goto out_f; @@ -1526,7 +1526,7 @@ asmlinkage int irix_mmap64(struct pt_regs *regs) unsigned long old_pos; long max_size = off2 + len; - if (max_size > file->f_dentry->d_inode->i_size) { + if (max_size > file->f_path.dentry->d_inode->i_size) { old_pos = sys_lseek (fd, max_size - 1, 0); sys_write (fd, (void __user *) "", 1); sys_lseek (fd, old_pos, 0); @@ -1658,7 +1658,7 @@ asmlinkage int irix_fstatvfs64(int fd, struct irix_statvfs __user *buf) error = -EBADF; goto out; } - error = vfs_statfs(file->f_dentry, &kbuf); + error = vfs_statfs(file->f_path.dentry, &kbuf); if (error) goto out_f; diff --git a/arch/mips/kernel/vpe.c b/arch/mips/kernel/vpe.c index 51ddd21..666bef48 100644 --- a/arch/mips/kernel/vpe.c +++ b/arch/mips/kernel/vpe.c @@ -1179,7 +1179,7 @@ static ssize_t vpe_write(struct file *file, const char __user * buffer, size_t ret = count; struct vpe *v; - minor = iminor(file->f_dentry->d_inode); + minor = iminor(file->f_path.dentry->d_inode); if ((v = get_vpe(minor)) == NULL) return -ENODEV; diff --git a/arch/mips/lasat/sysctl.c b/arch/mips/lasat/sysctl.c index 6dd7ae1..da35d45 100644 --- a/arch/mips/lasat/sysctl.c +++ b/arch/mips/lasat/sysctl.c @@ -286,11 +286,11 @@ int proc_lasat_eeprom_value(ctl_table *table, int write, struct file *filp, mutex_unlock(&lasat_info_mutex); return r; } - if (filp && filp->f_dentry) + if (filp && filp->f_path.dentry) { - if (!strcmp(filp->f_dentry->d_name.name, "prid")) + if (!strcmp(filp->f_path.dentry->d_name.name, "prid")) lasat_board_info.li_eeprom_info.prid = lasat_board_info.li_prid; - if (!strcmp(filp->f_dentry->d_name.name, "debugaccess")) + if (!strcmp(filp->f_path.dentry->d_name.name, "debugaccess")) lasat_board_info.li_eeprom_info.debugaccess = lasat_board_info.li_debugaccess; } lasat_write_eeprom_info(); -- cgit v1.1 From f0d1b0b30d250a07627ad8b9fbbb5c7cc08422e8 Mon Sep 17 00:00:00 2001 From: David Howells Date: Fri, 8 Dec 2006 02:37:49 -0800 Subject: [PATCH] LOG2: Implement a general integer log2 facility in the kernel This facility provides three entry points: ilog2() Log base 2 of unsigned long ilog2_u32() Log base 2 of u32 ilog2_u64() Log base 2 of u64 These facilities can either be used inside functions on dynamic data: int do_something(long q) { ...; y = ilog2(x) ...; } Or can be used to statically initialise global variables with constant values: unsigned n = ilog2(27); When performing static initialisation, the compiler will report "error: initializer element is not constant" if asked to take a log of zero or of something not reducible to a constant. They treat negative numbers as unsigned. When not dealing with a constant, they fall back to using fls() which permits them to use arch-specific log calculation instructions - such as BSR on x86/x86_64 or SCAN on FRV - if available. [akpm@osdl.org: MMC fix] Signed-off-by: David Howells Cc: Benjamin Herrenschmidt Cc: Paul Mackerras Cc: Herbert Xu Cc: David Howells Cc: Wojtek Kaniewski Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- arch/mips/Kconfig | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'arch/mips') diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index d8af858f..57af8d8 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -819,6 +819,14 @@ config RWSEM_GENERIC_SPINLOCK config RWSEM_XCHGADD_ALGORITHM bool +config ARCH_HAS_ILOG2_U32 + bool + default n + +config ARCH_HAS_ILOG2_U64 + bool + default n + config GENERIC_FIND_NEXT_BIT bool default y -- cgit v1.1 From 937949d9edbf4049bd41af6c9f92c26280584564 Mon Sep 17 00:00:00 2001 From: Cedric Le Goater Date: Fri, 8 Dec 2006 02:37:54 -0800 Subject: [PATCH] add process_session() helper routine Replace occurences of task->signal->session by a new process_session() helper routine. It will be useful for pid namespaces to abstract the session pid number. Signed-off-by: Cedric Le Goater Cc: Kirill Korotaev Cc: Eric W. Biederman Cc: Herbert Poetzl Cc: Sukadev Bhattiprolu Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- arch/mips/kernel/irixelf.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/mips') diff --git a/arch/mips/kernel/irixelf.c b/arch/mips/kernel/irixelf.c index 1bbefbf..37cad5d 100644 --- a/arch/mips/kernel/irixelf.c +++ b/arch/mips/kernel/irixelf.c @@ -1145,7 +1145,7 @@ static int irix_core_dump(long signr, struct pt_regs * regs, struct file *file) psinfo.pr_pid = prstatus.pr_pid = current->pid; psinfo.pr_ppid = prstatus.pr_ppid = current->parent->pid; psinfo.pr_pgrp = prstatus.pr_pgrp = process_group(current); - psinfo.pr_sid = prstatus.pr_sid = current->signal->session; + psinfo.pr_sid = prstatus.pr_sid = process_session(current); if (current->pid == current->tgid) { /* * This is the record for the group leader. Add in the -- cgit v1.1 From 8e087929df884dbb13e383d49d192bdd6928ecbf Mon Sep 17 00:00:00 2001 From: Haavard Skinnemoen Date: Fri, 8 Dec 2006 02:38:04 -0800 Subject: [PATCH] Generic ioremap_page_range: mips conversion Convert MIPS to use generic ioremap_page_range() [yoichi_yuasa@tripeaks.co.jp: build fix] Signed-off-by: Haavard Skinnemoen Cc: Ralf Baechle Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- arch/mips/mm/ioremap.c | 96 +++++--------------------------------------------- 1 file changed, 8 insertions(+), 88 deletions(-) (limited to 'arch/mips') diff --git a/arch/mips/mm/ioremap.c b/arch/mips/mm/ioremap.c index cea7d0e..fc2c96f 100644 --- a/arch/mips/mm/ioremap.c +++ b/arch/mips/mm/ioremap.c @@ -6,98 +6,13 @@ * (C) Copyright 1995 1996 Linus Torvalds * (C) Copyright 2001, 2002 Ralf Baechle */ +#include #include #include #include #include -#include -#include -#include - -static inline void remap_area_pte(pte_t * pte, unsigned long address, - phys_t size, phys_t phys_addr, unsigned long flags) -{ - phys_t end; - unsigned long pfn; - pgprot_t pgprot = __pgprot(_PAGE_GLOBAL | _PAGE_PRESENT | __READABLE - | __WRITEABLE | flags); - - address &= ~PMD_MASK; - end = address + size; - if (end > PMD_SIZE) - end = PMD_SIZE; - if (address >= end) - BUG(); - pfn = phys_addr >> PAGE_SHIFT; - do { - if (!pte_none(*pte)) { - printk("remap_area_pte: page already exists\n"); - BUG(); - } - set_pte(pte, pfn_pte(pfn, pgprot)); - address += PAGE_SIZE; - pfn++; - pte++; - } while (address && (address < end)); -} - -static inline int remap_area_pmd(pmd_t * pmd, unsigned long address, - phys_t size, phys_t phys_addr, unsigned long flags) -{ - phys_t end; - - address &= ~PGDIR_MASK; - end = address + size; - if (end > PGDIR_SIZE) - end = PGDIR_SIZE; - phys_addr -= address; - if (address >= end) - BUG(); - do { - pte_t * pte = pte_alloc_kernel(pmd, address); - if (!pte) - return -ENOMEM; - remap_area_pte(pte, address, end - address, address + phys_addr, flags); - address = (address + PMD_SIZE) & PMD_MASK; - pmd++; - } while (address && (address < end)); - return 0; -} - -static int remap_area_pages(unsigned long address, phys_t phys_addr, - phys_t size, unsigned long flags) -{ - int error; - pgd_t * dir; - unsigned long end = address + size; - - phys_addr -= address; - dir = pgd_offset(&init_mm, address); - flush_cache_all(); - if (address >= end) - BUG(); - do { - pud_t *pud; - pmd_t *pmd; - - error = -ENOMEM; - pud = pud_alloc(&init_mm, dir, address); - if (!pud) - break; - pmd = pmd_alloc(&init_mm, pud, address); - if (!pmd) - break; - if (remap_area_pmd(pmd, address, end - address, - phys_addr + address, flags)) - break; - error = 0; - address = (address + PGDIR_SIZE) & PGDIR_MASK; - dir++; - } while (address && (address < end)); - flush_tlb_all(); - return error; -} +#include /* * Generic mapping function (not visible outside): @@ -121,6 +36,7 @@ void __iomem * __ioremap(phys_t phys_addr, phys_t size, unsigned long flags) unsigned long offset; phys_t last_addr; void * addr; + pgprot_t pgprot; phys_addr = fixup_bigphys_addr(phys_addr, size); @@ -152,6 +68,9 @@ void __iomem * __ioremap(phys_t phys_addr, phys_t size, unsigned long flags) return NULL; } + pgprot = __pgprot(_PAGE_GLOBAL | _PAGE_PRESENT | __READABLE + | __WRITEABLE | flags); + /* * Mappings have to be page-aligned */ @@ -166,7 +85,8 @@ void __iomem * __ioremap(phys_t phys_addr, phys_t size, unsigned long flags) if (!area) return NULL; addr = area->addr; - if (remap_area_pages((unsigned long) addr, phys_addr, size, flags)) { + if (ioremap_page_range((unsigned long)addr, (unsigned long)addr + size, + phys_addr, pgprot)) { vunmap(addr); return NULL; } -- cgit v1.1 From 14b36af46a1d3652aff6734ea24816995dff8123 Mon Sep 17 00:00:00 2001 From: Thomas Bogendoerfer Date: Tue, 5 Dec 2006 17:05:44 +0100 Subject: [MIPS] Rename SNI_RM200_PCI to just SNI_RM preparing for more RM machines Signed-off-by: Thomas Bogendoerfer Signed-off-by: Ralf Baechle --- arch/mips/Kconfig | 14 +++++++------- arch/mips/Makefile | 10 +++++----- arch/mips/configs/atlas_defconfig | 2 +- arch/mips/configs/bigsur_defconfig | 2 +- arch/mips/configs/capcella_defconfig | 2 +- arch/mips/configs/cobalt_defconfig | 2 +- arch/mips/configs/db1000_defconfig | 2 +- arch/mips/configs/db1100_defconfig | 2 +- arch/mips/configs/db1200_defconfig | 2 +- arch/mips/configs/db1500_defconfig | 2 +- arch/mips/configs/db1550_defconfig | 2 +- arch/mips/configs/ddb5477_defconfig | 2 +- arch/mips/configs/decstation_defconfig | 2 +- arch/mips/configs/e55_defconfig | 2 +- arch/mips/configs/emma2rh_defconfig | 2 +- arch/mips/configs/ev64120_defconfig | 2 +- arch/mips/configs/excite_defconfig | 2 +- arch/mips/configs/ip22_defconfig | 2 +- arch/mips/configs/ip27_defconfig | 2 +- arch/mips/configs/ip32_defconfig | 2 +- arch/mips/configs/jaguar-atx_defconfig | 2 +- arch/mips/configs/jazz_defconfig | 2 +- arch/mips/configs/jmr3927_defconfig | 2 +- arch/mips/configs/lasat200_defconfig | 2 +- arch/mips/configs/malta_defconfig | 2 +- arch/mips/configs/mipssim_defconfig | 2 +- arch/mips/configs/mpc30x_defconfig | 2 +- arch/mips/configs/ocelot_3_defconfig | 2 +- arch/mips/configs/ocelot_c_defconfig | 2 +- arch/mips/configs/ocelot_defconfig | 2 +- arch/mips/configs/ocelot_g_defconfig | 2 +- arch/mips/configs/pb1100_defconfig | 2 +- arch/mips/configs/pb1500_defconfig | 2 +- arch/mips/configs/pb1550_defconfig | 2 +- arch/mips/configs/pnx8550-jbs_defconfig | 2 +- arch/mips/configs/pnx8550-v2pci_defconfig | 2 +- arch/mips/configs/qemu_defconfig | 2 +- arch/mips/configs/rbhma4500_defconfig | 2 +- arch/mips/configs/rm200_defconfig | 2 +- arch/mips/configs/sb1250-swarm_defconfig | 2 +- arch/mips/configs/sead_defconfig | 2 +- arch/mips/configs/tb0226_defconfig | 2 +- arch/mips/configs/tb0229_defconfig | 2 +- arch/mips/configs/tb0287_defconfig | 2 +- arch/mips/configs/workpad_defconfig | 2 +- arch/mips/configs/wrppmc_defconfig | 2 +- arch/mips/configs/yosemite_defconfig | 2 +- arch/mips/defconfig | 2 +- arch/mips/pci/Makefile | 2 +- 49 files changed, 59 insertions(+), 59 deletions(-) (limited to 'arch/mips') diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 57af8d8..7078bf4 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -701,8 +701,8 @@ config SIBYTE_CRHONE select SYS_SUPPORTS_HIGHMEM select SYS_SUPPORTS_LITTLE_ENDIAN -config SNI_RM200_PCI - bool "SNI RM200 PCI" +config SNI_RM + bool "SNI RM200/300/400" select ARC if CPU_LITTLE_ENDIAN select ARC32 if CPU_LITTLE_ENDIAN select ARCH_MAY_HAVE_PC_FDC @@ -725,8 +725,8 @@ config SNI_RM200_PCI select SYS_SUPPORTS_HIGHMEM select SYS_SUPPORTS_LITTLE_ENDIAN help - The SNI RM200 PCI was a MIPS-based platform manufactured by Siemens - Nixdorf Informationssysteme (SNI), parent company of Pyramid + The SNI RM200/300/400 are MIPS-based machines manufactured by + Siemens Nixdorf Informationssysteme (SNI), parent company of Pyramid Technology and now in turn merged with Fujitsu. Say Y here to support this machine type. @@ -1070,16 +1070,16 @@ config HAVE_STD_PC_SERIAL_PORT config ARC_CONSOLE bool "ARC console support" - depends on SGI_IP22 || SNI_RM200_PCI + depends on SGI_IP22 || SNI_RM config ARC_MEMORY bool - depends on MACH_JAZZ || SNI_RM200_PCI || SGI_IP32 + depends on MACH_JAZZ || SNI_RM || SGI_IP32 default y config ARC_PROMLIB bool - depends on MACH_JAZZ || SNI_RM200_PCI || SGI_IP22 || SGI_IP32 + depends on MACH_JAZZ || SNI_RM || SGI_IP22 || SGI_IP32 default y config ARC64 diff --git a/arch/mips/Makefile b/arch/mips/Makefile index 641aa30..8eb6fc1 100644 --- a/arch/mips/Makefile +++ b/arch/mips/Makefile @@ -569,11 +569,11 @@ libs-$(CONFIG_SIBYTE_BIGSUR) += arch/mips/sibyte/swarm/ load-$(CONFIG_SIBYTE_BIGSUR) := 0xffffffff80100000 # -# SNI RM200 PCI +# SNI RM # -core-$(CONFIG_SNI_RM200_PCI) += arch/mips/sni/ -cflags-$(CONFIG_SNI_RM200_PCI) += -Iinclude/asm-mips/mach-rm200 -load-$(CONFIG_SNI_RM200_PCI) += 0xffffffff80600000 +core-$(CONFIG_SNI_RM) += arch/mips/sni/ +cflags-$(CONFIG_SNI_RM) += -Iinclude/asm-mips/mach-rm +load-$(CONFIG_SNI_RM) += 0xffffffff80600000 # # Toshiba JMR-TX3927 board @@ -695,7 +695,7 @@ ifdef CONFIG_QEMU all: vmlinux.bin endif -ifdef CONFIG_SNI_RM200_PCI +ifdef CONFIG_SNI_RM all: vmlinux.ecoff endif diff --git a/arch/mips/configs/atlas_defconfig b/arch/mips/configs/atlas_defconfig index 35931be..ac18916 100644 --- a/arch/mips/configs/atlas_defconfig +++ b/arch/mips/configs/atlas_defconfig @@ -59,7 +59,7 @@ CONFIG_MIPS_ATLAS=y # CONFIG_SIBYTE_LITTLESUR is not set # CONFIG_SIBYTE_CRHINE is not set # CONFIG_SIBYTE_CRHONE is not set -# CONFIG_SNI_RM200_PCI is not set +# CONFIG_SNI_RM is not set # CONFIG_TOSHIBA_JMR3927 is not set # CONFIG_TOSHIBA_RBTX4927 is not set # CONFIG_TOSHIBA_RBTX4938 is not set diff --git a/arch/mips/configs/bigsur_defconfig b/arch/mips/configs/bigsur_defconfig index ba3bf73..9554257 100644 --- a/arch/mips/configs/bigsur_defconfig +++ b/arch/mips/configs/bigsur_defconfig @@ -57,7 +57,7 @@ CONFIG_SIBYTE_BIGSUR=y # CONFIG_SIBYTE_LITTLESUR is not set # CONFIG_SIBYTE_CRHINE is not set # CONFIG_SIBYTE_CRHONE is not set -# CONFIG_SNI_RM200_PCI is not set +# CONFIG_SNI_RM is not set # CONFIG_TOSHIBA_JMR3927 is not set # CONFIG_TOSHIBA_RBTX4927 is not set # CONFIG_TOSHIBA_RBTX4938 is not set diff --git a/arch/mips/configs/capcella_defconfig b/arch/mips/configs/capcella_defconfig index e535812..49590d4 100644 --- a/arch/mips/configs/capcella_defconfig +++ b/arch/mips/configs/capcella_defconfig @@ -59,7 +59,7 @@ CONFIG_MACH_VR41XX=y # CONFIG_SIBYTE_LITTLESUR is not set # CONFIG_SIBYTE_CRHINE is not set # CONFIG_SIBYTE_CRHONE is not set -# CONFIG_SNI_RM200_PCI is not set +# CONFIG_SNI_RM is not set # CONFIG_TOSHIBA_JMR3927 is not set # CONFIG_TOSHIBA_RBTX4927 is not set # CONFIG_TOSHIBA_RBTX4938 is not set diff --git a/arch/mips/configs/cobalt_defconfig b/arch/mips/configs/cobalt_defconfig index adf1e8c..0607fc2 100644 --- a/arch/mips/configs/cobalt_defconfig +++ b/arch/mips/configs/cobalt_defconfig @@ -59,7 +59,7 @@ CONFIG_MIPS_COBALT=y # CONFIG_SIBYTE_LITTLESUR is not set # CONFIG_SIBYTE_CRHINE is not set # CONFIG_SIBYTE_CRHONE is not set -# CONFIG_SNI_RM200_PCI is not set +# CONFIG_SNI_RM is not set # CONFIG_TOSHIBA_JMR3927 is not set # CONFIG_TOSHIBA_RBTX4927 is not set # CONFIG_TOSHIBA_RBTX4938 is not set diff --git a/arch/mips/configs/db1000_defconfig b/arch/mips/configs/db1000_defconfig index 4fd29ff..1a57b33 100644 --- a/arch/mips/configs/db1000_defconfig +++ b/arch/mips/configs/db1000_defconfig @@ -59,7 +59,7 @@ CONFIG_MIPS_DB1000=y # CONFIG_SIBYTE_LITTLESUR is not set # CONFIG_SIBYTE_CRHINE is not set # CONFIG_SIBYTE_CRHONE is not set -# CONFIG_SNI_RM200_PCI is not set +# CONFIG_SNI_RM is not set # CONFIG_TOSHIBA_JMR3927 is not set # CONFIG_TOSHIBA_RBTX4927 is not set # CONFIG_TOSHIBA_RBTX4938 is not set diff --git a/arch/mips/configs/db1100_defconfig b/arch/mips/configs/db1100_defconfig index 025b960..0055ec4 100644 --- a/arch/mips/configs/db1100_defconfig +++ b/arch/mips/configs/db1100_defconfig @@ -59,7 +59,7 @@ CONFIG_MIPS_DB1100=y # CONFIG_SIBYTE_LITTLESUR is not set # CONFIG_SIBYTE_CRHINE is not set # CONFIG_SIBYTE_CRHONE is not set -# CONFIG_SNI_RM200_PCI is not set +# CONFIG_SNI_RM is not set # CONFIG_TOSHIBA_JMR3927 is not set # CONFIG_TOSHIBA_RBTX4927 is not set # CONFIG_TOSHIBA_RBTX4938 is not set diff --git a/arch/mips/configs/db1200_defconfig b/arch/mips/configs/db1200_defconfig index 80c9dd9..c41823b 100644 --- a/arch/mips/configs/db1200_defconfig +++ b/arch/mips/configs/db1200_defconfig @@ -59,7 +59,7 @@ CONFIG_MIPS_DB1200=y # CONFIG_SIBYTE_LITTLESUR is not set # CONFIG_SIBYTE_CRHINE is not set # CONFIG_SIBYTE_CRHONE is not set -# CONFIG_SNI_RM200_PCI is not set +# CONFIG_SNI_RM is not set # CONFIG_TOSHIBA_JMR3927 is not set # CONFIG_TOSHIBA_RBTX4927 is not set # CONFIG_TOSHIBA_RBTX4938 is not set diff --git a/arch/mips/configs/db1500_defconfig b/arch/mips/configs/db1500_defconfig index 6caa90b..7d6d921 100644 --- a/arch/mips/configs/db1500_defconfig +++ b/arch/mips/configs/db1500_defconfig @@ -59,7 +59,7 @@ CONFIG_MIPS_DB1500=y # CONFIG_SIBYTE_LITTLESUR is not set # CONFIG_SIBYTE_CRHINE is not set # CONFIG_SIBYTE_CRHONE is not set -# CONFIG_SNI_RM200_PCI is not set +# CONFIG_SNI_RM is not set # CONFIG_TOSHIBA_JMR3927 is not set # CONFIG_TOSHIBA_RBTX4927 is not set # CONFIG_TOSHIBA_RBTX4938 is not set diff --git a/arch/mips/configs/db1550_defconfig b/arch/mips/configs/db1550_defconfig index c6cae86..c681c91 100644 --- a/arch/mips/configs/db1550_defconfig +++ b/arch/mips/configs/db1550_defconfig @@ -59,7 +59,7 @@ CONFIG_MIPS_DB1550=y # CONFIG_SIBYTE_LITTLESUR is not set # CONFIG_SIBYTE_CRHINE is not set # CONFIG_SIBYTE_CRHONE is not set -# CONFIG_SNI_RM200_PCI is not set +# CONFIG_SNI_RM is not set # CONFIG_TOSHIBA_JMR3927 is not set # CONFIG_TOSHIBA_RBTX4927 is not set # CONFIG_TOSHIBA_RBTX4938 is not set diff --git a/arch/mips/configs/ddb5477_defconfig b/arch/mips/configs/ddb5477_defconfig index 72f2400..dd4bb00 100644 --- a/arch/mips/configs/ddb5477_defconfig +++ b/arch/mips/configs/ddb5477_defconfig @@ -59,7 +59,7 @@ CONFIG_DDB5477=y # CONFIG_SIBYTE_LITTLESUR is not set # CONFIG_SIBYTE_CRHINE is not set # CONFIG_SIBYTE_CRHONE is not set -# CONFIG_SNI_RM200_PCI is not set +# CONFIG_SNI_RM is not set # CONFIG_TOSHIBA_JMR3927 is not set # CONFIG_TOSHIBA_RBTX4927 is not set # CONFIG_TOSHIBA_RBTX4938 is not set diff --git a/arch/mips/configs/decstation_defconfig b/arch/mips/configs/decstation_defconfig index fe1387e..8a31ce4 100644 --- a/arch/mips/configs/decstation_defconfig +++ b/arch/mips/configs/decstation_defconfig @@ -59,7 +59,7 @@ CONFIG_MACH_DECSTATION=y # CONFIG_SIBYTE_LITTLESUR is not set # CONFIG_SIBYTE_CRHINE is not set # CONFIG_SIBYTE_CRHONE is not set -# CONFIG_SNI_RM200_PCI is not set +# CONFIG_SNI_RM is not set # CONFIG_TOSHIBA_JMR3927 is not set # CONFIG_TOSHIBA_RBTX4927 is not set # CONFIG_TOSHIBA_RBTX4938 is not set diff --git a/arch/mips/configs/e55_defconfig b/arch/mips/configs/e55_defconfig index 6133c28..6fa4f91 100644 --- a/arch/mips/configs/e55_defconfig +++ b/arch/mips/configs/e55_defconfig @@ -59,7 +59,7 @@ CONFIG_MACH_VR41XX=y # CONFIG_SIBYTE_LITTLESUR is not set # CONFIG_SIBYTE_CRHINE is not set # CONFIG_SIBYTE_CRHONE is not set -# CONFIG_SNI_RM200_PCI is not set +# CONFIG_SNI_RM is not set # CONFIG_TOSHIBA_JMR3927 is not set # CONFIG_TOSHIBA_RBTX4927 is not set # CONFIG_TOSHIBA_RBTX4938 is not set diff --git a/arch/mips/configs/emma2rh_defconfig b/arch/mips/configs/emma2rh_defconfig index a484b7d..4c9d040 100644 --- a/arch/mips/configs/emma2rh_defconfig +++ b/arch/mips/configs/emma2rh_defconfig @@ -59,7 +59,7 @@ CONFIG_MARKEINS=y # CONFIG_SIBYTE_LITTLESUR is not set # CONFIG_SIBYTE_CRHINE is not set # CONFIG_SIBYTE_CRHONE is not set -# CONFIG_SNI_RM200_PCI is not set +# CONFIG_SNI_RM is not set # CONFIG_TOSHIBA_JMR3927 is not set # CONFIG_TOSHIBA_RBTX4927 is not set # CONFIG_TOSHIBA_RBTX4938 is not set diff --git a/arch/mips/configs/ev64120_defconfig b/arch/mips/configs/ev64120_defconfig index 21bfcde..d5b4973 100644 --- a/arch/mips/configs/ev64120_defconfig +++ b/arch/mips/configs/ev64120_defconfig @@ -59,7 +59,7 @@ CONFIG_MIPS_EV64120=y # CONFIG_SIBYTE_LITTLESUR is not set # CONFIG_SIBYTE_CRHINE is not set # CONFIG_SIBYTE_CRHONE is not set -# CONFIG_SNI_RM200_PCI is not set +# CONFIG_SNI_RM is not set # CONFIG_TOSHIBA_JMR3927 is not set # CONFIG_TOSHIBA_RBTX4927 is not set # CONFIG_TOSHIBA_RBTX4938 is not set diff --git a/arch/mips/configs/excite_defconfig b/arch/mips/configs/excite_defconfig index 1a5b06c..697140c 100644 --- a/arch/mips/configs/excite_defconfig +++ b/arch/mips/configs/excite_defconfig @@ -60,7 +60,7 @@ CONFIG_BASLER_EXCITE=y # CONFIG_SIBYTE_LITTLESUR is not set # CONFIG_SIBYTE_CRHINE is not set # CONFIG_SIBYTE_CRHONE is not set -# CONFIG_SNI_RM200_PCI is not set +# CONFIG_SNI_RM is not set # CONFIG_TOSHIBA_JMR3927 is not set # CONFIG_TOSHIBA_RBTX4927 is not set # CONFIG_TOSHIBA_RBTX4938 is not set diff --git a/arch/mips/configs/ip22_defconfig b/arch/mips/configs/ip22_defconfig index 21d53e0..f9812d1 100644 --- a/arch/mips/configs/ip22_defconfig +++ b/arch/mips/configs/ip22_defconfig @@ -59,7 +59,7 @@ CONFIG_SGI_IP22=y # CONFIG_SIBYTE_LITTLESUR is not set # CONFIG_SIBYTE_CRHINE is not set # CONFIG_SIBYTE_CRHONE is not set -# CONFIG_SNI_RM200_PCI is not set +# CONFIG_SNI_RM is not set # CONFIG_TOSHIBA_JMR3927 is not set # CONFIG_TOSHIBA_RBTX4927 is not set # CONFIG_TOSHIBA_RBTX4938 is not set diff --git a/arch/mips/configs/ip27_defconfig b/arch/mips/configs/ip27_defconfig index e3e94c7..96090f2 100644 --- a/arch/mips/configs/ip27_defconfig +++ b/arch/mips/configs/ip27_defconfig @@ -59,7 +59,7 @@ CONFIG_SGI_IP27=y # CONFIG_SIBYTE_LITTLESUR is not set # CONFIG_SIBYTE_CRHINE is not set # CONFIG_SIBYTE_CRHONE is not set -# CONFIG_SNI_RM200_PCI is not set +# CONFIG_SNI_RM is not set # CONFIG_TOSHIBA_JMR3927 is not set # CONFIG_TOSHIBA_RBTX4927 is not set # CONFIG_TOSHIBA_RBTX4938 is not set diff --git a/arch/mips/configs/ip32_defconfig b/arch/mips/configs/ip32_defconfig index b4ab2be..61e069a 100644 --- a/arch/mips/configs/ip32_defconfig +++ b/arch/mips/configs/ip32_defconfig @@ -59,7 +59,7 @@ CONFIG_SGI_IP32=y # CONFIG_SIBYTE_LITTLESUR is not set # CONFIG_SIBYTE_CRHINE is not set # CONFIG_SIBYTE_CRHONE is not set -# CONFIG_SNI_RM200_PCI is not set +# CONFIG_SNI_RM is not set # CONFIG_TOSHIBA_JMR3927 is not set # CONFIG_TOSHIBA_RBTX4927 is not set # CONFIG_TOSHIBA_RBTX4938 is not set diff --git a/arch/mips/configs/jaguar-atx_defconfig b/arch/mips/configs/jaguar-atx_defconfig index 9d4d17a..8896666 100644 --- a/arch/mips/configs/jaguar-atx_defconfig +++ b/arch/mips/configs/jaguar-atx_defconfig @@ -59,7 +59,7 @@ CONFIG_MOMENCO_JAGUAR_ATX=y # CONFIG_SIBYTE_LITTLESUR is not set # CONFIG_SIBYTE_CRHINE is not set # CONFIG_SIBYTE_CRHONE is not set -# CONFIG_SNI_RM200_PCI is not set +# CONFIG_SNI_RM is not set # CONFIG_TOSHIBA_JMR3927 is not set # CONFIG_TOSHIBA_RBTX4927 is not set # CONFIG_TOSHIBA_RBTX4938 is not set diff --git a/arch/mips/configs/jazz_defconfig b/arch/mips/configs/jazz_defconfig index 382083e..835764d8 100644 --- a/arch/mips/configs/jazz_defconfig +++ b/arch/mips/configs/jazz_defconfig @@ -57,7 +57,7 @@ CONFIG_MACH_JAZZ=y # CONFIG_SIBYTE_LITTLESUR is not set # CONFIG_SIBYTE_CRHINE is not set # CONFIG_SIBYTE_CRHONE is not set -# CONFIG_SNI_RM200_PCI is not set +# CONFIG_SNI_RM is not set # CONFIG_TOSHIBA_JMR3927 is not set # CONFIG_TOSHIBA_RBTX4927 is not set # CONFIG_TOSHIBA_RBTX4938 is not set diff --git a/arch/mips/configs/jmr3927_defconfig b/arch/mips/configs/jmr3927_defconfig index d037466..50fd955 100644 --- a/arch/mips/configs/jmr3927_defconfig +++ b/arch/mips/configs/jmr3927_defconfig @@ -59,7 +59,7 @@ CONFIG_MIPS=y # CONFIG_SIBYTE_LITTLESUR is not set # CONFIG_SIBYTE_CRHINE is not set # CONFIG_SIBYTE_CRHONE is not set -# CONFIG_SNI_RM200_PCI is not set +# CONFIG_SNI_RM is not set CONFIG_TOSHIBA_JMR3927=y # CONFIG_TOSHIBA_RBTX4927 is not set # CONFIG_TOSHIBA_RBTX4938 is not set diff --git a/arch/mips/configs/lasat200_defconfig b/arch/mips/configs/lasat200_defconfig index 1db8249..05f539f 100644 --- a/arch/mips/configs/lasat200_defconfig +++ b/arch/mips/configs/lasat200_defconfig @@ -59,7 +59,7 @@ CONFIG_LASAT=y # CONFIG_SIBYTE_LITTLESUR is not set # CONFIG_SIBYTE_CRHINE is not set # CONFIG_SIBYTE_CRHONE is not set -# CONFIG_SNI_RM200_PCI is not set +# CONFIG_SNI_RM is not set # CONFIG_TOSHIBA_JMR3927 is not set # CONFIG_TOSHIBA_RBTX4927 is not set # CONFIG_TOSHIBA_RBTX4938 is not set diff --git a/arch/mips/configs/malta_defconfig b/arch/mips/configs/malta_defconfig index 101e803..1f9300f 100644 --- a/arch/mips/configs/malta_defconfig +++ b/arch/mips/configs/malta_defconfig @@ -57,7 +57,7 @@ CONFIG_MIPS_MALTA=y # CONFIG_SIBYTE_LITTLESUR is not set # CONFIG_SIBYTE_CRHINE is not set # CONFIG_SIBYTE_CRHONE is not set -# CONFIG_SNI_RM200_PCI is not set +# CONFIG_SNI_RM is not set # CONFIG_TOSHIBA_JMR3927 is not set # CONFIG_TOSHIBA_RBTX4927 is not set # CONFIG_TOSHIBA_RBTX4938 is not set diff --git a/arch/mips/configs/mipssim_defconfig b/arch/mips/configs/mipssim_defconfig index a3cbd23b..03efcfd 100644 --- a/arch/mips/configs/mipssim_defconfig +++ b/arch/mips/configs/mipssim_defconfig @@ -59,7 +59,7 @@ CONFIG_MIPS_SIM=y # CONFIG_SIBYTE_LITTLESUR is not set # CONFIG_SIBYTE_CRHINE is not set # CONFIG_SIBYTE_CRHONE is not set -# CONFIG_SNI_RM200_PCI is not set +# CONFIG_SNI_RM is not set # CONFIG_TOSHIBA_JMR3927 is not set # CONFIG_TOSHIBA_RBTX4927 is not set # CONFIG_TOSHIBA_RBTX4938 is not set diff --git a/arch/mips/configs/mpc30x_defconfig b/arch/mips/configs/mpc30x_defconfig index 6570b47..e4221aa 100644 --- a/arch/mips/configs/mpc30x_defconfig +++ b/arch/mips/configs/mpc30x_defconfig @@ -59,7 +59,7 @@ CONFIG_MACH_VR41XX=y # CONFIG_SIBYTE_LITTLESUR is not set # CONFIG_SIBYTE_CRHINE is not set # CONFIG_SIBYTE_CRHONE is not set -# CONFIG_SNI_RM200_PCI is not set +# CONFIG_SNI_RM is not set # CONFIG_TOSHIBA_JMR3927 is not set # CONFIG_TOSHIBA_RBTX4927 is not set # CONFIG_TOSHIBA_RBTX4938 is not set diff --git a/arch/mips/configs/ocelot_3_defconfig b/arch/mips/configs/ocelot_3_defconfig index 440d65f..32b1afd 100644 --- a/arch/mips/configs/ocelot_3_defconfig +++ b/arch/mips/configs/ocelot_3_defconfig @@ -59,7 +59,7 @@ CONFIG_MOMENCO_OCELOT_3=y # CONFIG_SIBYTE_LITTLESUR is not set # CONFIG_SIBYTE_CRHINE is not set # CONFIG_SIBYTE_CRHONE is not set -# CONFIG_SNI_RM200_PCI is not set +# CONFIG_SNI_RM is not set # CONFIG_TOSHIBA_JMR3927 is not set # CONFIG_TOSHIBA_RBTX4927 is not set # CONFIG_TOSHIBA_RBTX4938 is not set diff --git a/arch/mips/configs/ocelot_c_defconfig b/arch/mips/configs/ocelot_c_defconfig index c2c7ae7..ebe75c1 100644 --- a/arch/mips/configs/ocelot_c_defconfig +++ b/arch/mips/configs/ocelot_c_defconfig @@ -59,7 +59,7 @@ CONFIG_MOMENCO_OCELOT_C=y # CONFIG_SIBYTE_LITTLESUR is not set # CONFIG_SIBYTE_CRHINE is not set # CONFIG_SIBYTE_CRHONE is not set -# CONFIG_SNI_RM200_PCI is not set +# CONFIG_SNI_RM is not set # CONFIG_TOSHIBA_JMR3927 is not set # CONFIG_TOSHIBA_RBTX4927 is not set # CONFIG_TOSHIBA_RBTX4938 is not set diff --git a/arch/mips/configs/ocelot_defconfig b/arch/mips/configs/ocelot_defconfig index 67efe27..5a9603c 100644 --- a/arch/mips/configs/ocelot_defconfig +++ b/arch/mips/configs/ocelot_defconfig @@ -59,7 +59,7 @@ CONFIG_MOMENCO_OCELOT=y # CONFIG_SIBYTE_LITTLESUR is not set # CONFIG_SIBYTE_CRHINE is not set # CONFIG_SIBYTE_CRHONE is not set -# CONFIG_SNI_RM200_PCI is not set +# CONFIG_SNI_RM is not set # CONFIG_TOSHIBA_JMR3927 is not set # CONFIG_TOSHIBA_RBTX4927 is not set # CONFIG_TOSHIBA_RBTX4938 is not set diff --git a/arch/mips/configs/ocelot_g_defconfig b/arch/mips/configs/ocelot_g_defconfig index a10f34d..46a942c 100644 --- a/arch/mips/configs/ocelot_g_defconfig +++ b/arch/mips/configs/ocelot_g_defconfig @@ -59,7 +59,7 @@ CONFIG_MOMENCO_OCELOT_G=y # CONFIG_SIBYTE_LITTLESUR is not set # CONFIG_SIBYTE_CRHINE is not set # CONFIG_SIBYTE_CRHONE is not set -# CONFIG_SNI_RM200_PCI is not set +# CONFIG_SNI_RM is not set # CONFIG_TOSHIBA_JMR3927 is not set # CONFIG_TOSHIBA_RBTX4927 is not set # CONFIG_TOSHIBA_RBTX4938 is not set diff --git a/arch/mips/configs/pb1100_defconfig b/arch/mips/configs/pb1100_defconfig index 9e672f6..7d3c688 100644 --- a/arch/mips/configs/pb1100_defconfig +++ b/arch/mips/configs/pb1100_defconfig @@ -59,7 +59,7 @@ CONFIG_MIPS_PB1100=y # CONFIG_SIBYTE_LITTLESUR is not set # CONFIG_SIBYTE_CRHINE is not set # CONFIG_SIBYTE_CRHONE is not set -# CONFIG_SNI_RM200_PCI is not set +# CONFIG_SNI_RM is not set # CONFIG_TOSHIBA_JMR3927 is not set # CONFIG_TOSHIBA_RBTX4927 is not set # CONFIG_TOSHIBA_RBTX4938 is not set diff --git a/arch/mips/configs/pb1500_defconfig b/arch/mips/configs/pb1500_defconfig index d0c0f4a..a77805a 100644 --- a/arch/mips/configs/pb1500_defconfig +++ b/arch/mips/configs/pb1500_defconfig @@ -59,7 +59,7 @@ CONFIG_MIPS_PB1500=y # CONFIG_SIBYTE_LITTLESUR is not set # CONFIG_SIBYTE_CRHINE is not set # CONFIG_SIBYTE_CRHONE is not set -# CONFIG_SNI_RM200_PCI is not set +# CONFIG_SNI_RM is not set # CONFIG_TOSHIBA_JMR3927 is not set # CONFIG_TOSHIBA_RBTX4927 is not set # CONFIG_TOSHIBA_RBTX4938 is not set diff --git a/arch/mips/configs/pb1550_defconfig b/arch/mips/configs/pb1550_defconfig index 3db7427..8318d74 100644 --- a/arch/mips/configs/pb1550_defconfig +++ b/arch/mips/configs/pb1550_defconfig @@ -59,7 +59,7 @@ CONFIG_MIPS_PB1550=y # CONFIG_SIBYTE_LITTLESUR is not set # CONFIG_SIBYTE_CRHINE is not set # CONFIG_SIBYTE_CRHONE is not set -# CONFIG_SNI_RM200_PCI is not set +# CONFIG_SNI_RM is not set # CONFIG_TOSHIBA_JMR3927 is not set # CONFIG_TOSHIBA_RBTX4927 is not set # CONFIG_TOSHIBA_RBTX4938 is not set diff --git a/arch/mips/configs/pnx8550-jbs_defconfig b/arch/mips/configs/pnx8550-jbs_defconfig index 280a800..fcb8fea 100644 --- a/arch/mips/configs/pnx8550-jbs_defconfig +++ b/arch/mips/configs/pnx8550-jbs_defconfig @@ -57,7 +57,7 @@ CONFIG_PNX8550_JBS=y # CONFIG_SIBYTE_LITTLESUR is not set # CONFIG_SIBYTE_CRHINE is not set # CONFIG_SIBYTE_CRHONE is not set -# CONFIG_SNI_RM200_PCI is not set +# CONFIG_SNI_RM is not set # CONFIG_TOSHIBA_JMR3927 is not set # CONFIG_TOSHIBA_RBTX4927 is not set # CONFIG_TOSHIBA_RBTX4938 is not set diff --git a/arch/mips/configs/pnx8550-v2pci_defconfig b/arch/mips/configs/pnx8550-v2pci_defconfig index 64b9fbf..5bc3248 100644 --- a/arch/mips/configs/pnx8550-v2pci_defconfig +++ b/arch/mips/configs/pnx8550-v2pci_defconfig @@ -57,7 +57,7 @@ CONFIG_PNX8550_V2PCI=y # CONFIG_SIBYTE_LITTLESUR is not set # CONFIG_SIBYTE_CRHINE is not set # CONFIG_SIBYTE_CRHONE is not set -# CONFIG_SNI_RM200_PCI is not set +# CONFIG_SNI_RM is not set # CONFIG_TOSHIBA_JMR3927 is not set # CONFIG_TOSHIBA_RBTX4927 is not set # CONFIG_TOSHIBA_RBTX4938 is not set diff --git a/arch/mips/configs/qemu_defconfig b/arch/mips/configs/qemu_defconfig index 9b0dab8..aa61f0f 100644 --- a/arch/mips/configs/qemu_defconfig +++ b/arch/mips/configs/qemu_defconfig @@ -59,7 +59,7 @@ CONFIG_QEMU=y # CONFIG_SIBYTE_LITTLESUR is not set # CONFIG_SIBYTE_CRHINE is not set # CONFIG_SIBYTE_CRHONE is not set -# CONFIG_SNI_RM200_PCI is not set +# CONFIG_SNI_RM is not set # CONFIG_TOSHIBA_JMR3927 is not set # CONFIG_TOSHIBA_RBTX4927 is not set # CONFIG_TOSHIBA_RBTX4938 is not set diff --git a/arch/mips/configs/rbhma4500_defconfig b/arch/mips/configs/rbhma4500_defconfig index dd02960..f9e8f41 100644 --- a/arch/mips/configs/rbhma4500_defconfig +++ b/arch/mips/configs/rbhma4500_defconfig @@ -59,7 +59,7 @@ CONFIG_MIPS=y # CONFIG_SIBYTE_LITTLESUR is not set # CONFIG_SIBYTE_CRHINE is not set # CONFIG_SIBYTE_CRHONE is not set -# CONFIG_SNI_RM200_PCI is not set +# CONFIG_SNI_RM is not set # CONFIG_TOSHIBA_JMR3927 is not set # CONFIG_TOSHIBA_RBTX4927 is not set CONFIG_TOSHIBA_RBTX4938=y diff --git a/arch/mips/configs/rm200_defconfig b/arch/mips/configs/rm200_defconfig index d8a498d..496aa67 100644 --- a/arch/mips/configs/rm200_defconfig +++ b/arch/mips/configs/rm200_defconfig @@ -59,7 +59,7 @@ CONFIG_MIPS=y # CONFIG_SIBYTE_LITTLESUR is not set # CONFIG_SIBYTE_CRHINE is not set # CONFIG_SIBYTE_CRHONE is not set -CONFIG_SNI_RM200_PCI=y +CONFIG_SNI_RM=y # CONFIG_TOSHIBA_JMR3927 is not set # CONFIG_TOSHIBA_RBTX4927 is not set # CONFIG_TOSHIBA_RBTX4938 is not set diff --git a/arch/mips/configs/sb1250-swarm_defconfig b/arch/mips/configs/sb1250-swarm_defconfig index 805a4fe..e33c172 100644 --- a/arch/mips/configs/sb1250-swarm_defconfig +++ b/arch/mips/configs/sb1250-swarm_defconfig @@ -59,7 +59,7 @@ CONFIG_SIBYTE_SWARM=y # CONFIG_SIBYTE_LITTLESUR is not set # CONFIG_SIBYTE_CRHINE is not set # CONFIG_SIBYTE_CRHONE is not set -# CONFIG_SNI_RM200_PCI is not set +# CONFIG_SNI_RM is not set # CONFIG_TOSHIBA_JMR3927 is not set # CONFIG_TOSHIBA_RBTX4927 is not set # CONFIG_TOSHIBA_RBTX4938 is not set diff --git a/arch/mips/configs/sead_defconfig b/arch/mips/configs/sead_defconfig index 6fcb656..83fb932 100644 --- a/arch/mips/configs/sead_defconfig +++ b/arch/mips/configs/sead_defconfig @@ -59,7 +59,7 @@ CONFIG_MIPS_SEAD=y # CONFIG_SIBYTE_LITTLESUR is not set # CONFIG_SIBYTE_CRHINE is not set # CONFIG_SIBYTE_CRHONE is not set -# CONFIG_SNI_RM200_PCI is not set +# CONFIG_SNI_RM is not set # CONFIG_TOSHIBA_JMR3927 is not set # CONFIG_TOSHIBA_RBTX4927 is not set # CONFIG_TOSHIBA_RBTX4938 is not set diff --git a/arch/mips/configs/tb0226_defconfig b/arch/mips/configs/tb0226_defconfig index dc312f1..e9d4eae 100644 --- a/arch/mips/configs/tb0226_defconfig +++ b/arch/mips/configs/tb0226_defconfig @@ -59,7 +59,7 @@ CONFIG_MACH_VR41XX=y # CONFIG_SIBYTE_LITTLESUR is not set # CONFIG_SIBYTE_CRHINE is not set # CONFIG_SIBYTE_CRHONE is not set -# CONFIG_SNI_RM200_PCI is not set +# CONFIG_SNI_RM is not set # CONFIG_TOSHIBA_JMR3927 is not set # CONFIG_TOSHIBA_RBTX4927 is not set # CONFIG_TOSHIBA_RBTX4938 is not set diff --git a/arch/mips/configs/tb0229_defconfig b/arch/mips/configs/tb0229_defconfig index 85615d9..c19597f 100644 --- a/arch/mips/configs/tb0229_defconfig +++ b/arch/mips/configs/tb0229_defconfig @@ -59,7 +59,7 @@ CONFIG_MACH_VR41XX=y # CONFIG_SIBYTE_LITTLESUR is not set # CONFIG_SIBYTE_CRHINE is not set # CONFIG_SIBYTE_CRHONE is not set -# CONFIG_SNI_RM200_PCI is not set +# CONFIG_SNI_RM is not set # CONFIG_TOSHIBA_JMR3927 is not set # CONFIG_TOSHIBA_RBTX4927 is not set # CONFIG_TOSHIBA_RBTX4938 is not set diff --git a/arch/mips/configs/tb0287_defconfig b/arch/mips/configs/tb0287_defconfig index f7e8194..97d94f9 100644 --- a/arch/mips/configs/tb0287_defconfig +++ b/arch/mips/configs/tb0287_defconfig @@ -57,7 +57,7 @@ CONFIG_MACH_VR41XX=y # CONFIG_SIBYTE_LITTLESUR is not set # CONFIG_SIBYTE_CRHINE is not set # CONFIG_SIBYTE_CRHONE is not set -# CONFIG_SNI_RM200_PCI is not set +# CONFIG_SNI_RM is not set # CONFIG_TOSHIBA_JMR3927 is not set # CONFIG_TOSHIBA_RBTX4927 is not set # CONFIG_TOSHIBA_RBTX4938 is not set diff --git a/arch/mips/configs/workpad_defconfig b/arch/mips/configs/workpad_defconfig index 863f6a7..553734a 100644 --- a/arch/mips/configs/workpad_defconfig +++ b/arch/mips/configs/workpad_defconfig @@ -59,7 +59,7 @@ CONFIG_MACH_VR41XX=y # CONFIG_SIBYTE_LITTLESUR is not set # CONFIG_SIBYTE_CRHINE is not set # CONFIG_SIBYTE_CRHONE is not set -# CONFIG_SNI_RM200_PCI is not set +# CONFIG_SNI_RM is not set # CONFIG_TOSHIBA_JMR3927 is not set # CONFIG_TOSHIBA_RBTX4927 is not set # CONFIG_TOSHIBA_RBTX4938 is not set diff --git a/arch/mips/configs/wrppmc_defconfig b/arch/mips/configs/wrppmc_defconfig index c10267d..d3dfb70 100644 --- a/arch/mips/configs/wrppmc_defconfig +++ b/arch/mips/configs/wrppmc_defconfig @@ -59,7 +59,7 @@ CONFIG_WR_PPMC=y # CONFIG_SIBYTE_LITTLESUR is not set # CONFIG_SIBYTE_CRHINE is not set # CONFIG_SIBYTE_CRHONE is not set -# CONFIG_SNI_RM200_PCI is not set +# CONFIG_SNI_RM is not set # CONFIG_TOSHIBA_JMR3927 is not set # CONFIG_TOSHIBA_RBTX4927 is not set # CONFIG_TOSHIBA_RBTX4938 is not set diff --git a/arch/mips/configs/yosemite_defconfig b/arch/mips/configs/yosemite_defconfig index 4d3c132..b9f74d6 100644 --- a/arch/mips/configs/yosemite_defconfig +++ b/arch/mips/configs/yosemite_defconfig @@ -59,7 +59,7 @@ CONFIG_PMC_YOSEMITE=y # CONFIG_SIBYTE_LITTLESUR is not set # CONFIG_SIBYTE_CRHINE is not set # CONFIG_SIBYTE_CRHONE is not set -# CONFIG_SNI_RM200_PCI is not set +# CONFIG_SNI_RM is not set # CONFIG_TOSHIBA_JMR3927 is not set # CONFIG_TOSHIBA_RBTX4927 is not set # CONFIG_TOSHIBA_RBTX4938 is not set diff --git a/arch/mips/defconfig b/arch/mips/defconfig index 21d53e0..f9812d1 100644 --- a/arch/mips/defconfig +++ b/arch/mips/defconfig @@ -59,7 +59,7 @@ CONFIG_SGI_IP22=y # CONFIG_SIBYTE_LITTLESUR is not set # CONFIG_SIBYTE_CRHINE is not set # CONFIG_SIBYTE_CRHONE is not set -# CONFIG_SNI_RM200_PCI is not set +# CONFIG_SNI_RM is not set # CONFIG_TOSHIBA_JMR3927 is not set # CONFIG_TOSHIBA_RBTX4927 is not set # CONFIG_TOSHIBA_RBTX4938 is not set diff --git a/arch/mips/pci/Makefile b/arch/mips/pci/Makefile index 70cb55b..82b20c2 100644 --- a/arch/mips/pci/Makefile +++ b/arch/mips/pci/Makefile @@ -43,7 +43,7 @@ obj-$(CONFIG_SGI_IP32) += fixup-ip32.o ops-mace.o pci-ip32.o obj-$(CONFIG_SIBYTE_SB1250) += fixup-sb1250.o pci-sb1250.o obj-$(CONFIG_SIBYTE_BCM112X) += fixup-sb1250.o pci-sb1250.o obj-$(CONFIG_SIBYTE_BCM1x80) += pci-bcm1480.o pci-bcm1480ht.o -obj-$(CONFIG_SNI_RM200_PCI) += fixup-sni.o ops-sni.o +obj-$(CONFIG_SNI_RM) += fixup-sni.o ops-sni.o obj-$(CONFIG_TANBAC_TB0219) += fixup-tb0219.o obj-$(CONFIG_TANBAC_TB0226) += fixup-tb0226.o obj-$(CONFIG_TANBAC_TB0287) += fixup-tb0287.o -- cgit v1.1 From 52ffe760ea9ec407292d093c3f06c1cda5187228 Mon Sep 17 00:00:00 2001 From: Atsushi Nemoto Date: Fri, 8 Dec 2006 01:04:31 +0900 Subject: [MIPS] Make csum_partial more readable Use standard o32 register name instead of T0, T1, etc, like memcpy.S. Signed-off-by: Atsushi Nemoto Signed-off-by: Ralf Baechle --- arch/mips/lib/csum_partial.S | 144 ++++++++++++++++++++++--------------------- 1 file changed, 74 insertions(+), 70 deletions(-) (limited to 'arch/mips') diff --git a/arch/mips/lib/csum_partial.S b/arch/mips/lib/csum_partial.S index 15611d9..3bffdbb 100644 --- a/arch/mips/lib/csum_partial.S +++ b/arch/mips/lib/csum_partial.S @@ -12,19 +12,23 @@ #include #ifdef CONFIG_64BIT -#define T0 ta0 -#define T1 ta1 -#define T2 ta2 -#define T3 ta3 -#define T4 t0 -#define T7 t3 -#else -#define T0 t0 -#define T1 t1 -#define T2 t2 -#define T3 t3 -#define T4 t4 -#define T7 t7 +/* + * As we are sharing code base with the mips32 tree (which use the o32 ABI + * register definitions). We need to redefine the register definitions from + * the n64 ABI register naming to the o32 ABI register naming. + */ +#undef t0 +#undef t1 +#undef t2 +#undef t3 +#define t0 $8 +#define t1 $9 +#define t2 $10 +#define t3 $11 +#define t4 $12 +#define t5 $13 +#define t6 $14 +#define t7 $15 #endif #define ADDC(sum,reg) \ @@ -64,37 +68,37 @@ /* unknown src alignment and < 8 bytes to go */ small_csumcpy: - move a1, T2 + move a1, t2 - andi T0, a1, 4 - beqz T0, 1f - andi T0, a1, 2 + andi t0, a1, 4 + beqz t0, 1f + andi t0, a1, 2 /* Still a full word to go */ - ulw T1, (src) + ulw t1, (src) PTR_ADDIU src, 4 - ADDC(sum, T1) + ADDC(sum, t1) -1: move T1, zero - beqz T0, 1f - andi T0, a1, 1 +1: move t1, zero + beqz t0, 1f + andi t0, a1, 1 /* Still a halfword to go */ - ulhu T1, (src) + ulhu t1, (src) PTR_ADDIU src, 2 -1: beqz T0, 1f - sll T1, T1, 16 +1: beqz t0, 1f + sll t1, t1, 16 - lbu T2, (src) + lbu t2, (src) nop #ifdef __MIPSEB__ - sll T2, T2, 8 + sll t2, t2, 8 #endif - or T1, T2 + or t1, t2 -1: ADDC(sum, T1) +1: ADDC(sum, t1) /* fold checksum */ sll v1, sum, 16 @@ -104,7 +108,7 @@ small_csumcpy: addu sum, v1 /* odd buffer alignment? */ - beqz T7, 1f + beqz t7, 1f nop sll v1, sum, 8 srl sum, sum, 8 @@ -122,25 +126,25 @@ small_csumcpy: .align 5 LEAF(csum_partial) move sum, zero - move T7, zero + move t7, zero sltiu t8, a1, 0x8 bnez t8, small_csumcpy /* < 8 bytes to copy */ - move T2, a1 + move t2, a1 beqz a1, out - andi T7, src, 0x1 /* odd buffer? */ + andi t7, src, 0x1 /* odd buffer? */ hword_align: - beqz T7, word_align + beqz t7, word_align andi t8, src, 0x2 - lbu T0, (src) + lbu t0, (src) LONG_SUBU a1, a1, 0x1 #ifdef __MIPSEL__ - sll T0, T0, 8 + sll t0, t0, 8 #endif - ADDC(sum, T0) + ADDC(sum, t0) PTR_ADDU src, src, 0x1 andi t8, src, 0x2 @@ -148,9 +152,9 @@ word_align: beqz t8, dword_align sltiu t8, a1, 56 - lhu T0, (src) + lhu t0, (src) LONG_SUBU a1, a1, 0x2 - ADDC(sum, T0) + ADDC(sum, t0) sltiu t8, a1, 56 PTR_ADDU src, src, 0x2 @@ -162,9 +166,9 @@ dword_align: beqz t8, qword_align andi t8, src, 0x8 - lw T0, 0x00(src) + lw t0, 0x00(src) LONG_SUBU a1, a1, 0x4 - ADDC(sum, T0) + ADDC(sum, t0) PTR_ADDU src, src, 0x4 andi t8, src, 0x8 @@ -172,11 +176,11 @@ qword_align: beqz t8, oword_align andi t8, src, 0x10 - lw T0, 0x00(src) - lw T1, 0x04(src) + lw t0, 0x00(src) + lw t1, 0x04(src) LONG_SUBU a1, a1, 0x8 - ADDC(sum, T0) - ADDC(sum, T1) + ADDC(sum, t0) + ADDC(sum, t1) PTR_ADDU src, src, 0x8 andi t8, src, 0x10 @@ -184,46 +188,46 @@ oword_align: beqz t8, begin_movement LONG_SRL t8, a1, 0x7 - lw T3, 0x08(src) - lw T4, 0x0c(src) - lw T0, 0x00(src) - lw T1, 0x04(src) - ADDC(sum, T3) - ADDC(sum, T4) - ADDC(sum, T0) - ADDC(sum, T1) + lw t3, 0x08(src) + lw t4, 0x0c(src) + lw t0, 0x00(src) + lw t1, 0x04(src) + ADDC(sum, t3) + ADDC(sum, t4) + ADDC(sum, t0) + ADDC(sum, t1) LONG_SUBU a1, a1, 0x10 PTR_ADDU src, src, 0x10 LONG_SRL t8, a1, 0x7 begin_movement: beqz t8, 1f - andi T2, a1, 0x40 + andi t2, a1, 0x40 move_128bytes: - CSUM_BIGCHUNK(src, 0x00, sum, T0, T1, T3, T4) - CSUM_BIGCHUNK(src, 0x20, sum, T0, T1, T3, T4) - CSUM_BIGCHUNK(src, 0x40, sum, T0, T1, T3, T4) - CSUM_BIGCHUNK(src, 0x60, sum, T0, T1, T3, T4) + CSUM_BIGCHUNK(src, 0x00, sum, t0, t1, t3, t4) + CSUM_BIGCHUNK(src, 0x20, sum, t0, t1, t3, t4) + CSUM_BIGCHUNK(src, 0x40, sum, t0, t1, t3, t4) + CSUM_BIGCHUNK(src, 0x60, sum, t0, t1, t3, t4) LONG_SUBU t8, t8, 0x01 bnez t8, move_128bytes PTR_ADDU src, src, 0x80 1: - beqz T2, 1f - andi T2, a1, 0x20 + beqz t2, 1f + andi t2, a1, 0x20 move_64bytes: - CSUM_BIGCHUNK(src, 0x00, sum, T0, T1, T3, T4) - CSUM_BIGCHUNK(src, 0x20, sum, T0, T1, T3, T4) + CSUM_BIGCHUNK(src, 0x00, sum, t0, t1, t3, t4) + CSUM_BIGCHUNK(src, 0x20, sum, t0, t1, t3, t4) PTR_ADDU src, src, 0x40 1: - beqz T2, do_end_words + beqz t2, do_end_words andi t8, a1, 0x1c move_32bytes: - CSUM_BIGCHUNK(src, 0x00, sum, T0, T1, T3, T4) + CSUM_BIGCHUNK(src, 0x00, sum, t0, t1, t3, t4) andi t8, a1, 0x1c PTR_ADDU src, src, 0x20 @@ -232,22 +236,22 @@ do_end_words: LONG_SRL t8, t8, 0x2 end_words: - lw T0, (src) + lw t0, (src) LONG_SUBU t8, t8, 0x1 - ADDC(sum, T0) + ADDC(sum, t0) bnez t8, end_words PTR_ADDU src, src, 0x4 maybe_end_cruft: - andi T2, a1, 0x3 + andi t2, a1, 0x3 small_memcpy: - j small_csumcpy; move a1, T2 /* XXX ??? */ + j small_csumcpy; move a1, t2 /* XXX ??? */ beqz t2, out - move a1, T2 + move a1, t2 end_bytes: - lb T0, (src) + lb t0, (src) LONG_SUBU a1, a1, 0x1 bnez a2, end_bytes PTR_ADDU src, src, 0x1 -- cgit v1.1 From 773ff78838ca3c07245e45c06235e0baaa5f710a Mon Sep 17 00:00:00 2001 From: Atsushi Nemoto Date: Fri, 8 Dec 2006 01:04:45 +0900 Subject: [MIPS] Optimize flow of csum_partial Delete dead codes at end of the function and move small_csumcopy there. This makes some labels (maybe_end_cruft, small_memcpy, end_bytes, out) needless and eliminates some branches. Signed-off-by: Atsushi Nemoto Signed-off-by: Ralf Baechle --- arch/mips/lib/csum_partial.S | 129 ++++++++++++++++++------------------------- 1 file changed, 54 insertions(+), 75 deletions(-) (limited to 'arch/mips') diff --git a/arch/mips/lib/csum_partial.S b/arch/mips/lib/csum_partial.S index 3bffdbb..b04475d 100644 --- a/arch/mips/lib/csum_partial.S +++ b/arch/mips/lib/csum_partial.S @@ -65,64 +65,6 @@ .text .set noreorder - -/* unknown src alignment and < 8 bytes to go */ -small_csumcpy: - move a1, t2 - - andi t0, a1, 4 - beqz t0, 1f - andi t0, a1, 2 - - /* Still a full word to go */ - ulw t1, (src) - PTR_ADDIU src, 4 - ADDC(sum, t1) - -1: move t1, zero - beqz t0, 1f - andi t0, a1, 1 - - /* Still a halfword to go */ - ulhu t1, (src) - PTR_ADDIU src, 2 - -1: beqz t0, 1f - sll t1, t1, 16 - - lbu t2, (src) - nop - -#ifdef __MIPSEB__ - sll t2, t2, 8 -#endif - or t1, t2 - -1: ADDC(sum, t1) - - /* fold checksum */ - sll v1, sum, 16 - addu sum, v1 - sltu v1, sum, v1 - srl sum, sum, 16 - addu sum, v1 - - /* odd buffer alignment? */ - beqz t7, 1f - nop - sll v1, sum, 8 - srl sum, sum, 8 - or sum, v1 - andi sum, 0xffff -1: - .set reorder - /* Add the passed partial csum. */ - ADDC(sum, a2) - jr ra - .set noreorder - -/* ------------------------------------------------------------------------- */ - .align 5 LEAF(csum_partial) move sum, zero @@ -132,8 +74,7 @@ LEAF(csum_partial) bnez t8, small_csumcpy /* < 8 bytes to copy */ move t2, a1 - beqz a1, out - andi t7, src, 0x1 /* odd buffer? */ + andi t7, src, 0x1 /* odd buffer? */ hword_align: beqz t7, word_align @@ -232,8 +173,9 @@ move_32bytes: PTR_ADDU src, src, 0x20 do_end_words: - beqz t8, maybe_end_cruft - LONG_SRL t8, t8, 0x2 + beqz t8, small_csumcpy + andi t2, a1, 0x3 + LONG_SRL t8, t8, 0x2 end_words: lw t0, (src) @@ -242,21 +184,58 @@ end_words: bnez t8, end_words PTR_ADDU src, src, 0x4 -maybe_end_cruft: - andi t2, a1, 0x3 +/* unknown src alignment and < 8 bytes to go */ +small_csumcpy: + move a1, t2 -small_memcpy: - j small_csumcpy; move a1, t2 /* XXX ??? */ - beqz t2, out - move a1, t2 + andi t0, a1, 4 + beqz t0, 1f + andi t0, a1, 2 -end_bytes: - lb t0, (src) - LONG_SUBU a1, a1, 0x1 - bnez a2, end_bytes - PTR_ADDU src, src, 0x1 + /* Still a full word to go */ + ulw t1, (src) + PTR_ADDIU src, 4 + ADDC(sum, t1) + +1: move t1, zero + beqz t0, 1f + andi t0, a1, 1 + + /* Still a halfword to go */ + ulhu t1, (src) + PTR_ADDIU src, 2 + +1: beqz t0, 1f + sll t1, t1, 16 + + lbu t2, (src) + nop + +#ifdef __MIPSEB__ + sll t2, t2, 8 +#endif + or t1, t2 + +1: ADDC(sum, t1) -out: + /* fold checksum */ + sll v1, sum, 16 + addu sum, v1 + sltu v1, sum, v1 + srl sum, sum, 16 + addu sum, v1 + + /* odd buffer alignment? */ + beqz t7, 1f + nop + sll v1, sum, 8 + srl sum, sum, 8 + or sum, v1 + andi sum, 0xffff +1: + .set reorder + /* Add the passed partial csum. */ + ADDC(sum, a2) jr ra - move v0, sum + .set noreorder END(csum_partial) -- cgit v1.1 From ed99e2bc1dc5dc54eb5a019f4975562dbef20103 Mon Sep 17 00:00:00 2001 From: Atsushi Nemoto Date: Fri, 8 Dec 2006 01:04:51 +0900 Subject: [MIPS] Optimize csum_partial for 64bit kernel Make csum_partial 64-bit powered. Signed-off-by: Atsushi Nemoto Signed-off-by: Ralf Baechle --- arch/mips/lib/csum_partial.S | 76 +++++++++++++++++++++++++++++++------------- 1 file changed, 54 insertions(+), 22 deletions(-) (limited to 'arch/mips') diff --git a/arch/mips/lib/csum_partial.S b/arch/mips/lib/csum_partial.S index b04475d..9db3572 100644 --- a/arch/mips/lib/csum_partial.S +++ b/arch/mips/lib/csum_partial.S @@ -29,30 +29,49 @@ #define t5 $13 #define t6 $14 #define t7 $15 + +#define USE_DOUBLE #endif +#ifdef USE_DOUBLE + +#define LOAD ld +#define ADD daddu +#define NBYTES 8 + +#else + +#define LOAD lw +#define ADD addu +#define NBYTES 4 + +#endif /* USE_DOUBLE */ + +#define UNIT(unit) ((unit)*NBYTES) + #define ADDC(sum,reg) \ - addu sum, reg; \ + ADD sum, reg; \ sltu v1, sum, reg; \ - addu sum, v1 + ADD sum, v1 -#define CSUM_BIGCHUNK(src, offset, sum, _t0, _t1, _t2, _t3) \ - lw _t0, (offset + 0x00)(src); \ - lw _t1, (offset + 0x04)(src); \ - lw _t2, (offset + 0x08)(src); \ - lw _t3, (offset + 0x0c)(src); \ - ADDC(sum, _t0); \ - ADDC(sum, _t1); \ - ADDC(sum, _t2); \ - ADDC(sum, _t3); \ - lw _t0, (offset + 0x10)(src); \ - lw _t1, (offset + 0x14)(src); \ - lw _t2, (offset + 0x18)(src); \ - lw _t3, (offset + 0x1c)(src); \ +#define CSUM_BIGCHUNK1(src, offset, sum, _t0, _t1, _t2, _t3) \ + LOAD _t0, (offset + UNIT(0))(src); \ + LOAD _t1, (offset + UNIT(1))(src); \ + LOAD _t2, (offset + UNIT(2))(src); \ + LOAD _t3, (offset + UNIT(3))(src); \ ADDC(sum, _t0); \ ADDC(sum, _t1); \ ADDC(sum, _t2); \ - ADDC(sum, _t3); \ + ADDC(sum, _t3) + +#ifdef USE_DOUBLE +#define CSUM_BIGCHUNK(src, offset, sum, _t0, _t1, _t2, _t3) \ + CSUM_BIGCHUNK1(src, offset, sum, _t0, _t1, _t2, _t3) +#else +#define CSUM_BIGCHUNK(src, offset, sum, _t0, _t1, _t2, _t3) \ + CSUM_BIGCHUNK1(src, offset, sum, _t0, _t1, _t2, _t3); \ + CSUM_BIGCHUNK1(src, offset + 0x10, sum, _t0, _t1, _t2, _t3) +#endif /* * a0: source address @@ -117,11 +136,17 @@ qword_align: beqz t8, oword_align andi t8, src, 0x10 +#ifdef USE_DOUBLE + ld t0, 0x00(src) + LONG_SUBU a1, a1, 0x8 + ADDC(sum, t0) +#else lw t0, 0x00(src) lw t1, 0x04(src) LONG_SUBU a1, a1, 0x8 ADDC(sum, t0) ADDC(sum, t1) +#endif PTR_ADDU src, src, 0x8 andi t8, src, 0x10 @@ -129,14 +154,14 @@ oword_align: beqz t8, begin_movement LONG_SRL t8, a1, 0x7 - lw t3, 0x08(src) - lw t4, 0x0c(src) - lw t0, 0x00(src) - lw t1, 0x04(src) - ADDC(sum, t3) - ADDC(sum, t4) +#ifdef USE_DOUBLE + ld t0, 0x00(src) + ld t1, 0x08(src) ADDC(sum, t0) ADDC(sum, t1) +#else + CSUM_BIGCHUNK1(src, 0x00, sum, t0, t1, t3, t4) +#endif LONG_SUBU a1, a1, 0x10 PTR_ADDU src, src, 0x10 LONG_SRL t8, a1, 0x7 @@ -219,6 +244,13 @@ small_csumcpy: 1: ADDC(sum, t1) /* fold checksum */ +#ifdef USE_DOUBLE + dsll32 v1, sum, 0 + daddu sum, v1 + sltu v1, sum, v1 + dsra32 sum, sum, 0 + addu sum, v1 +#endif sll v1, sum, 16 addu sum, v1 sltu v1, sum, v1 -- cgit v1.1 From 9fd32cfbb602f3e5e898faa61d83c4a7897bd48a Mon Sep 17 00:00:00 2001 From: Atsushi Nemoto Date: Fri, 8 Dec 2006 01:55:07 +0900 Subject: [MIPS] Add GENERIC_HARDIRQS_NO__DO_IRQ for i8259 users Now that i8259A_chip uses new irq flow handler select GENERIC_HARDIRQS_NO__DO_IRQ on some more platforms. Signed-off-by: Atsushi Nemoto Signed-off-by: Ralf Baechle --- arch/mips/Kconfig | 6 +++++ .../tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c | 27 ++-------------------- arch/mips/vr41xx/Kconfig | 5 ---- arch/mips/vr41xx/nec-cmbvr4133/irq.c | 9 +------- 4 files changed, 9 insertions(+), 38 deletions(-) (limited to 'arch/mips') diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 7078bf4..e58928a 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -165,6 +165,7 @@ config MIPS_COBALT select SYS_SUPPORTS_32BIT_KERNEL select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL select SYS_SUPPORTS_LITTLE_ENDIAN + select GENERIC_HARDIRQS_NO__DO_IRQ config MACH_DECSTATION bool "DECstations" @@ -225,6 +226,7 @@ config MACH_JAZZ select SYS_SUPPORTS_32BIT_KERNEL select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL select SYS_SUPPORTS_100HZ + select GENERIC_HARDIRQS_NO__DO_IRQ help This a family of machines based on the MIPS R4030 chipset which was used by several vendors to build RISC/os and Windows NT workstations. @@ -482,6 +484,7 @@ config MACH_VR41XX select SYS_HAS_CPU_VR41XX select SYS_SUPPORTS_32BIT_KERNEL select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL + select GENERIC_HARDIRQS_NO__DO_IRQ config PMC_YOSEMITE bool "PMC-Sierra Yosemite eval board" @@ -515,6 +518,7 @@ config QEMU select SYS_SUPPORTS_BIG_ENDIAN select SYS_SUPPORTS_LITTLE_ENDIAN select ARCH_SPARSEMEM_ENABLE + select GENERIC_HARDIRQS_NO__DO_IRQ help Qemu is a software emulator which among other architectures also can simulate a MIPS32 4Kc system. This patch adds support for the @@ -754,6 +758,7 @@ config TOSHIBA_RBTX4927 select SYS_SUPPORTS_64BIT_KERNEL select SYS_SUPPORTS_BIG_ENDIAN select TOSHIBA_BOARDS + select GENERIC_HARDIRQS_NO__DO_IRQ help This Toshiba board is based on the TX4927 processor. Say Y here to support this machine type @@ -773,6 +778,7 @@ config TOSHIBA_RBTX4938 select SYS_SUPPORTS_LITTLE_ENDIAN select SYS_SUPPORTS_BIG_ENDIAN select TOSHIBA_BOARDS + select GENERIC_HARDIRQS_NO__DO_IRQ help This Toshiba board is based on the TX4938 processor. Say Y here to support this machine type diff --git a/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c b/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c index 5a5ea6c..b54b529 100644 --- a/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c +++ b/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c @@ -158,7 +158,6 @@ JP7 is not bus master -- do NOT use -- only 4 pci bus master's allowed -- SouthB #define TOSHIBA_RBTX4927_IRQ_ISA_ENABLE ( 1 << 23 ) #define TOSHIBA_RBTX4927_IRQ_ISA_DISABLE ( 1 << 24 ) #define TOSHIBA_RBTX4927_IRQ_ISA_MASK ( 1 << 25 ) -#define TOSHIBA_RBTX4927_IRQ_ISA_ENDIRQ ( 1 << 26 ) #define TOSHIBA_RBTX4927_SETUP_ALL 0xffffffff #endif @@ -175,7 +174,6 @@ static const u32 toshiba_rbtx4927_irq_debug_flag = // | TOSHIBA_RBTX4927_IRQ_ISA_ENABLE // | TOSHIBA_RBTX4927_IRQ_ISA_DISABLE // | TOSHIBA_RBTX4927_IRQ_ISA_MASK -// | TOSHIBA_RBTX4927_IRQ_ISA_ENDIRQ ); #endif @@ -226,7 +224,6 @@ static void toshiba_rbtx4927_irq_ioc_disable(unsigned int irq); static void toshiba_rbtx4927_irq_isa_enable(unsigned int irq); static void toshiba_rbtx4927_irq_isa_disable(unsigned int irq); static void toshiba_rbtx4927_irq_isa_mask_and_ack(unsigned int irq); -static void toshiba_rbtx4927_irq_isa_end(unsigned int irq); #endif #define TOSHIBA_RBTX4927_IOC_NAME "RBTX4927-IOC" @@ -249,7 +246,6 @@ static struct irq_chip toshiba_rbtx4927_irq_isa_type = { .mask = toshiba_rbtx4927_irq_isa_disable, .mask_ack = toshiba_rbtx4927_irq_isa_mask_and_ack, .unmask = toshiba_rbtx4927_irq_isa_enable, - .end = toshiba_rbtx4927_irq_isa_end, }; #endif @@ -402,7 +398,8 @@ static void __init toshiba_rbtx4927_irq_isa_init(void) for (i = TOSHIBA_RBTX4927_IRQ_ISA_BEG; i <= TOSHIBA_RBTX4927_IRQ_ISA_END; i++) - set_irq_chip(i, &toshiba_rbtx4927_irq_isa_type); + set_irq_chip_and_handler(i, &toshiba_rbtx4927_irq_isa_type, + handle_level_irq); setup_irq(TOSHIBA_RBTX4927_IRQ_NEST_ISA_ON_IOC, &toshiba_rbtx4927_irq_isa_master); @@ -470,26 +467,6 @@ static void toshiba_rbtx4927_irq_isa_mask_and_ack(unsigned int irq) #endif -#ifdef CONFIG_TOSHIBA_FPCIB0 -static void toshiba_rbtx4927_irq_isa_end(unsigned int irq) -{ - TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_ISA_ENDIRQ, - "irq=%d\n", irq); - - if (irq < TOSHIBA_RBTX4927_IRQ_ISA_BEG - || irq > TOSHIBA_RBTX4927_IRQ_ISA_END) { - TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_EROR, - "bad irq=%d\n", irq); - panic("\n"); - } - - if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) { - toshiba_rbtx4927_irq_isa_enable(irq); - } -} -#endif - - void __init arch_init_irq(void) { extern void tx4927_irq_init(void); diff --git a/arch/mips/vr41xx/Kconfig b/arch/mips/vr41xx/Kconfig index c8dfd80..92f41f6 100644 --- a/arch/mips/vr41xx/Kconfig +++ b/arch/mips/vr41xx/Kconfig @@ -6,7 +6,6 @@ config CASIO_E55 select ISA select SYS_SUPPORTS_32BIT_KERNEL select SYS_SUPPORTS_LITTLE_ENDIAN - select GENERIC_HARDIRQS_NO__DO_IRQ config IBM_WORKPAD bool "Support for IBM WorkPad z50" @@ -16,7 +15,6 @@ config IBM_WORKPAD select ISA select SYS_SUPPORTS_32BIT_KERNEL select SYS_SUPPORTS_LITTLE_ENDIAN - select GENERIC_HARDIRQS_NO__DO_IRQ config NEC_CMBVR4133 bool "Support for NEC CMB-VR4133" @@ -41,7 +39,6 @@ config TANBAC_TB022X select IRQ_CPU select SYS_SUPPORTS_32BIT_KERNEL select SYS_SUPPORTS_LITTLE_ENDIAN - select GENERIC_HARDIRQS_NO__DO_IRQ help The TANBAC VR4131 multichip module(TB0225) and the TANBAC VR4131DIMM(TB0229) are MIPS-based platforms @@ -74,7 +71,6 @@ config VICTOR_MPC30X select IRQ_CPU select SYS_SUPPORTS_32BIT_KERNEL select SYS_SUPPORTS_LITTLE_ENDIAN - select GENERIC_HARDIRQS_NO__DO_IRQ config ZAO_CAPCELLA bool "Support for ZAO Networks Capcella" @@ -84,7 +80,6 @@ config ZAO_CAPCELLA select IRQ_CPU select SYS_SUPPORTS_32BIT_KERNEL select SYS_SUPPORTS_LITTLE_ENDIAN - select GENERIC_HARDIRQS_NO__DO_IRQ config PCI_VR41XX bool "Add PCI control unit support of NEC VR4100 series" diff --git a/arch/mips/vr41xx/nec-cmbvr4133/irq.c b/arch/mips/vr41xx/nec-cmbvr4133/irq.c index a039bb7..128ed8d 100644 --- a/arch/mips/vr41xx/nec-cmbvr4133/irq.c +++ b/arch/mips/vr41xx/nec-cmbvr4133/irq.c @@ -45,19 +45,12 @@ static void ack_i8259_irq(unsigned int irq) mask_and_ack_8259A(irq - I8259_IRQ_BASE); } -static void end_i8259_irq(unsigned int irq) -{ - if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) - enable_8259A_irq(irq - I8259_IRQ_BASE); -} - static struct irq_chip i8259_irq_type = { .typename = "XT-PIC", .ack = ack_i8259_irq, .mask = disable_i8259_irq, .mask_ack = ack_i8259_irq, .unmask = enable_i8259_irq, - .end = end_i8259_irq, }; static int i8259_get_irq_number(int irq) @@ -92,7 +85,7 @@ void __init rockhopper_init_irq(void) } for (i = I8259_IRQ_BASE; i <= I8259_IRQ_LAST; i++) - set_irq_chip(i, &i8259_irq_type); + set_irq_chip_and_handler(i, &i8259_irq_type, handle_level_irq); setup_irq(I8259_SLAVE_IRQ, &i8259_slave_cascade); -- cgit v1.1 From c25c79d80e02db1bd993426f979c5f1b42a0f132 Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Fri, 8 Dec 2006 12:55:42 +0000 Subject: [MIPS] Qemu now has an ELF loader. So nuke kludge for flat binaries. Signed-off-by: Ralf Baechle --- arch/mips/kernel/head.S | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/mips') diff --git a/arch/mips/kernel/head.S b/arch/mips/kernel/head.S index a2e095a..9a7811d 100644 --- a/arch/mips/kernel/head.S +++ b/arch/mips/kernel/head.S @@ -138,7 +138,7 @@ EXPORT(stext) # used for profiling EXPORT(_stext) -#if defined(CONFIG_QEMU) || defined(CONFIG_MIPS_SIM) +#ifdef CONFIG_MIPS_SIM /* * Give us a fighting chance of running if execution beings at the * kernel load address. This is needed because this platform does -- cgit v1.1 From f0647a52974daccbe20990fb6341f07792445fe0 Mon Sep 17 00:00:00 2001 From: Vitaly Wool Date: Fri, 8 Dec 2006 11:40:35 +0300 Subject: [PATCH] add STB810 support (Philips PNX8550-based) Signed-off-by: Vitaly Wool Signed-off-by: Ralf Baechle --- arch/mips/Kconfig | 5 + arch/mips/Makefile | 5 + arch/mips/configs/pnx8550-stb810_defconfig | 1229 ++++++++++++++++++++++++ arch/mips/pci/fixup-pnx8550.c | 4 +- arch/mips/philips/pnx8550/common/prom.c | 20 +- arch/mips/philips/pnx8550/jbs/irqmap.c | 8 +- arch/mips/philips/pnx8550/stb810/Makefile | 4 + arch/mips/philips/pnx8550/stb810/board_setup.c | 49 + arch/mips/philips/pnx8550/stb810/irqmap.c | 23 + arch/mips/philips/pnx8550/stb810/prom_init.c | 49 + 10 files changed, 1376 insertions(+), 20 deletions(-) create mode 100644 arch/mips/configs/pnx8550-stb810_defconfig create mode 100644 arch/mips/philips/pnx8550/stb810/Makefile create mode 100644 arch/mips/philips/pnx8550/stb810/board_setup.c create mode 100644 arch/mips/philips/pnx8550/stb810/irqmap.c create mode 100644 arch/mips/philips/pnx8550/stb810/prom_init.c (limited to 'arch/mips') diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index e58928a..fd2ff06 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -461,6 +461,11 @@ config PNX8550_JBS select PNX8550 select SYS_SUPPORTS_LITTLE_ENDIAN +config PNX8550_STB810 + bool "Support for Philips PNX8550 based STB810 board" + select PNX8550 + select SYS_SUPPORTS_LITTLE_ENDIAN + config DDB5477 bool "NEC DDB Vrc-5477" select DDB5XXX_COMMON diff --git a/arch/mips/Makefile b/arch/mips/Makefile index 8eb6fc1..d1b026a 100644 --- a/arch/mips/Makefile +++ b/arch/mips/Makefile @@ -463,6 +463,11 @@ libs-$(CONFIG_PNX8550_JBS) += arch/mips/philips/pnx8550/jbs/ #cflags-$(CONFIG_PNX8550_JBS) += -Iinclude/asm-mips/mach-pnx8550 load-$(CONFIG_PNX8550_JBS) += 0xffffffff80060000 +# Philips PNX8550 STB810 board +# +libs-$(CONFIG_PNX8550_STB810) += arch/mips/philips/pnx8550/stb810/ +load-$(CONFIG_PNX8550_STB810) += 0xffffffff80060000 + # NEC EMMA2RH boards # core-$(CONFIG_EMMA2RH) += arch/mips/emma2rh/common/ diff --git a/arch/mips/configs/pnx8550-stb810_defconfig b/arch/mips/configs/pnx8550-stb810_defconfig new file mode 100644 index 0000000..f38a2c1 --- /dev/null +++ b/arch/mips/configs/pnx8550-stb810_defconfig @@ -0,0 +1,1229 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.19 +# Thu Dec 7 16:35:12 2006 +# +CONFIG_MIPS=y + +# +# Machine selection +# +# CONFIG_MIPS_MTX1 is not set +# CONFIG_MIPS_BOSPORUS is not set +# CONFIG_MIPS_PB1000 is not set +# CONFIG_MIPS_PB1100 is not set +# CONFIG_MIPS_PB1500 is not set +# CONFIG_MIPS_PB1550 is not set +# CONFIG_MIPS_PB1200 is not set +# CONFIG_MIPS_DB1000 is not set +# CONFIG_MIPS_DB1100 is not set +# CONFIG_MIPS_DB1500 is not set +# CONFIG_MIPS_DB1550 is not set +# CONFIG_MIPS_DB1200 is not set +# CONFIG_MIPS_MIRAGE is not set +# CONFIG_BASLER_EXCITE is not set +# CONFIG_MIPS_COBALT is not set +# CONFIG_MACH_DECSTATION is not set +# CONFIG_MIPS_EV64120 is not set +# CONFIG_MACH_JAZZ is not set +# CONFIG_LASAT is not set +# CONFIG_MIPS_ATLAS is not set +# CONFIG_MIPS_MALTA is not set +# CONFIG_MIPS_SEAD is not set +# CONFIG_WR_PPMC is not set +# CONFIG_MIPS_SIM is not set +# CONFIG_MOMENCO_JAGUAR_ATX is not set +# CONFIG_MOMENCO_OCELOT is not set +# CONFIG_MOMENCO_OCELOT_3 is not set +# CONFIG_MOMENCO_OCELOT_C is not set +# CONFIG_MOMENCO_OCELOT_G is not set +# CONFIG_MIPS_XXS1500 is not set +# CONFIG_PNX8550_V2PCI is not set +# CONFIG_PNX8550_JBS is not set +CONFIG_PNX8550_STB810=y +# CONFIG_DDB5477 is not set +# CONFIG_MACH_VR41XX is not set +# CONFIG_PMC_YOSEMITE is not set +# CONFIG_QEMU is not set +# CONFIG_MARKEINS is not set +# CONFIG_SGI_IP22 is not set +# CONFIG_SGI_IP27 is not set +# CONFIG_SGI_IP32 is not set +# CONFIG_SIBYTE_BIGSUR is not set +# CONFIG_SIBYTE_SWARM is not set +# CONFIG_SIBYTE_SENTOSA is not set +# CONFIG_SIBYTE_RHONE is not set +# CONFIG_SIBYTE_CARMEL is not set +# CONFIG_SIBYTE_PTSWARM is not set +# CONFIG_SIBYTE_LITTLESUR is not set +# CONFIG_SIBYTE_CRHINE is not set +# CONFIG_SIBYTE_CRHONE is not set +# CONFIG_SNI_RM200_PCI is not set +# CONFIG_TOSHIBA_JMR3927 is not set +# CONFIG_TOSHIBA_RBTX4927 is not set +# CONFIG_TOSHIBA_RBTX4938 is not set +# CONFIG_KEXEC is not set +CONFIG_RWSEM_GENERIC_SPINLOCK=y +CONFIG_GENERIC_FIND_NEXT_BIT=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_GENERIC_TIME=y +CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y +CONFIG_DMA_NONCOHERENT=y +CONFIG_DMA_NEED_PCI_MAP_STATE=y +# CONFIG_CPU_BIG_ENDIAN is not set +CONFIG_CPU_LITTLE_ENDIAN=y +CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y +CONFIG_PNX8550=y +CONFIG_SOC_PNX8550=y +CONFIG_MIPS_L1_CACHE_SHIFT=5 + +# +# CPU selection +# +CONFIG_CPU_MIPS32_R1=y +# CONFIG_CPU_MIPS32_R2 is not set +# CONFIG_CPU_MIPS64_R1 is not set +# CONFIG_CPU_MIPS64_R2 is not set +# CONFIG_CPU_R3000 is not set +# CONFIG_CPU_TX39XX is not set +# CONFIG_CPU_VR41XX is not set +# CONFIG_CPU_R4300 is not set +# CONFIG_CPU_R4X00 is not set +# CONFIG_CPU_TX49XX is not set +# CONFIG_CPU_R5000 is not set +# CONFIG_CPU_R5432 is not set +# CONFIG_CPU_R6000 is not set +# CONFIG_CPU_NEVADA is not set +# CONFIG_CPU_R8000 is not set +# CONFIG_CPU_R10000 is not set +# CONFIG_CPU_RM7000 is not set +# CONFIG_CPU_RM9000 is not set +# CONFIG_CPU_SB1 is not set +CONFIG_SYS_HAS_CPU_MIPS32_R1=y +CONFIG_CPU_MIPS32=y +CONFIG_CPU_MIPSR1=y +CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y + +# +# Kernel type +# +CONFIG_32BIT=y +# CONFIG_64BIT is not set +CONFIG_PAGE_SIZE_4KB=y +# CONFIG_PAGE_SIZE_8KB is not set +# CONFIG_PAGE_SIZE_16KB is not set +# CONFIG_PAGE_SIZE_64KB is not set +CONFIG_CPU_HAS_PREFETCH=y +CONFIG_MIPS_MT_DISABLED=y +# CONFIG_MIPS_MT_SMP is not set +# CONFIG_MIPS_MT_SMTC is not set +# CONFIG_MIPS_VPE_LOADER is not set +# CONFIG_64BIT_PHYS_ADDR is not set +CONFIG_CPU_HAS_LLSC=y +CONFIG_CPU_HAS_SYNC=y +CONFIG_GENERIC_HARDIRQS=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_CPU_SUPPORTS_HIGHMEM=y +CONFIG_ARCH_FLATMEM_ENABLE=y +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +# CONFIG_SPARSEMEM_STATIC is not set +CONFIG_SPLIT_PTLOCK_CPUS=4 +# CONFIG_RESOURCES_64BIT is not set +# CONFIG_HZ_48 is not set +# CONFIG_HZ_100 is not set +# CONFIG_HZ_128 is not set +CONFIG_HZ_250=y +# CONFIG_HZ_256 is not set +# CONFIG_HZ_1000 is not set +# CONFIG_HZ_1024 is not set +CONFIG_SYS_SUPPORTS_ARBIT_HZ=y +CONFIG_HZ=250 +CONFIG_PREEMPT_NONE=y +# CONFIG_PREEMPT_VOLUNTARY is not set +# CONFIG_PREEMPT is not set +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" + +# +# Code maturity level options +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 + +# +# General setup +# +CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +# CONFIG_IPC_NS is not set +# CONFIG_POSIX_MQUEUE is not set +# CONFIG_BSD_PROCESS_ACCT is not set +# CONFIG_TASKSTATS is not set +# CONFIG_UTS_NS is not set +# CONFIG_AUDIT is not set +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_SYSFS_DEPRECATED=y +# CONFIG_RELAY is not set +CONFIG_INITRAMFS_SOURCE="" +# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set +CONFIG_SYSCTL=y +CONFIG_EMBEDDED=y +# CONFIG_SYSCTL_SYSCALL is not set +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_ALL is not set +# CONFIG_KALLSYMS_EXTRA_PASS is not set +# CONFIG_HOTPLUG is not set +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_EPOLL=y +CONFIG_SHMEM=y +CONFIG_SLAB=y +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_RT_MUTEXES=y +# CONFIG_TINY_SHMEM is not set +CONFIG_BASE_SMALL=0 +# CONFIG_SLOB is not set + +# +# Loadable module support +# +CONFIG_MODULES=y +# CONFIG_MODULE_UNLOAD is not set +# CONFIG_MODVERSIONS is not set +# CONFIG_MODULE_SRCVERSION_ALL is not set +CONFIG_KMOD=y + +# +# Block layer +# +CONFIG_BLOCK=y +# CONFIG_LBD is not set +# CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_LSF is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_AS=y +CONFIG_IOSCHED_DEADLINE=y +CONFIG_IOSCHED_CFQ=y +CONFIG_DEFAULT_AS=y +# CONFIG_DEFAULT_DEADLINE is not set +# CONFIG_DEFAULT_CFQ is not set +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="anticipatory" + +# +# Bus options (PCI, PCMCIA, EISA, ISA, TC) +# +CONFIG_HW_HAS_PCI=y +CONFIG_PCI=y +# CONFIG_PCI_MULTITHREAD_PROBE is not set +# CONFIG_PCI_DEBUG is not set +CONFIG_MMU=y + +# +# PCCARD (PCMCIA/CardBus) support +# + +# +# PCI Hotplug Support +# + +# +# Executable file formats +# +CONFIG_BINFMT_ELF=y +# CONFIG_BINFMT_MISC is not set +CONFIG_TRAD_SIGNALS=y + +# +# Networking +# +CONFIG_NET=y + +# +# Networking options +# +# CONFIG_NETDEBUG is not set +CONFIG_PACKET=y +# CONFIG_PACKET_MMAP is not set +CONFIG_UNIX=y +CONFIG_XFRM=y +# CONFIG_XFRM_USER is not set +# CONFIG_XFRM_SUB_POLICY is not set +# CONFIG_NET_KEY is not set +CONFIG_INET=y +# CONFIG_IP_MULTICAST is not set +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_FIB_HASH=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_ARPD is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_XFRM_TUNNEL is not set +# CONFIG_INET_TUNNEL is not set +CONFIG_INET_XFRM_MODE_TRANSPORT=y +CONFIG_INET_XFRM_MODE_TUNNEL=y +CONFIG_INET_XFRM_MODE_BEET=y +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +# CONFIG_IPV6 is not set +# CONFIG_INET6_XFRM_TUNNEL is not set +# CONFIG_INET6_TUNNEL is not set +# CONFIG_NETWORK_SECMARK is not set +# CONFIG_NETFILTER is not set + +# +# DCCP Configuration (EXPERIMENTAL) +# +# CONFIG_IP_DCCP is not set + +# +# SCTP Configuration (EXPERIMENTAL) +# +# CONFIG_IP_SCTP is not set + +# +# TIPC Configuration (EXPERIMENTAL) +# +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +# CONFIG_BRIDGE is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set + +# +# QoS and/or fair queueing +# +# CONFIG_NET_SCHED is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +# CONFIG_IEEE80211 is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +# CONFIG_DEBUG_DRIVER is not set +# CONFIG_SYS_HYPERVISOR is not set + +# +# Connector - unified userspace <-> kernelspace linker +# +# CONFIG_CONNECTOR is not set + +# +# Memory Technology Devices (MTD) +# +# CONFIG_MTD is not set + +# +# Parallel port support +# +# CONFIG_PARPORT is not set + +# +# Plug and Play support +# + +# +# Block devices +# +# CONFIG_BLK_CPQ_DA is not set +# CONFIG_BLK_CPQ_CISS_DA is not set +# CONFIG_BLK_DEV_DAC960 is not set +# CONFIG_BLK_DEV_UMEM is not set +# CONFIG_BLK_DEV_COW_COMMON is not set +CONFIG_BLK_DEV_LOOP=y +# CONFIG_BLK_DEV_CRYPTOLOOP is not set +# CONFIG_BLK_DEV_NBD is not set +# CONFIG_BLK_DEV_SX8 is not set +# CONFIG_BLK_DEV_UB is not set +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=16 +CONFIG_BLK_DEV_RAM_SIZE=8192 +CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024 +CONFIG_BLK_DEV_INITRD=y +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set + +# +# Misc devices +# +# CONFIG_SGI_IOC4 is not set +# CONFIG_TIFM_CORE is not set + +# +# ATA/ATAPI/MFM/RLL support +# +CONFIG_IDE=y +CONFIG_IDE_MAX_HWIFS=4 +CONFIG_BLK_DEV_IDE=y + +# +# Please see Documentation/ide.txt for help/info on IDE drives +# +# CONFIG_BLK_DEV_IDE_SATA is not set +CONFIG_BLK_DEV_IDEDISK=y +# CONFIG_IDEDISK_MULTI_MODE is not set +CONFIG_BLK_DEV_IDECD=m +# CONFIG_BLK_DEV_IDETAPE is not set +# CONFIG_BLK_DEV_IDEFLOPPY is not set +CONFIG_BLK_DEV_IDESCSI=y +# CONFIG_IDE_TASK_IOCTL is not set + +# +# IDE chipset support/bugfixes +# +CONFIG_IDE_GENERIC=y +CONFIG_BLK_DEV_IDEPCI=y +CONFIG_IDEPCI_SHARE_IRQ=y +CONFIG_BLK_DEV_OFFBOARD=y +CONFIG_BLK_DEV_GENERIC=y +# CONFIG_BLK_DEV_OPTI621 is not set +CONFIG_BLK_DEV_IDEDMA_PCI=y +# CONFIG_BLK_DEV_IDEDMA_FORCED is not set +# CONFIG_IDEDMA_PCI_AUTO is not set +# CONFIG_BLK_DEV_AEC62XX is not set +# CONFIG_BLK_DEV_ALI15X3 is not set +# CONFIG_BLK_DEV_AMD74XX is not set +# CONFIG_BLK_DEV_CMD64X is not set +# CONFIG_BLK_DEV_TRIFLEX is not set +# CONFIG_BLK_DEV_CY82C693 is not set +# CONFIG_BLK_DEV_CS5520 is not set +# CONFIG_BLK_DEV_CS5530 is not set +# CONFIG_BLK_DEV_HPT34X is not set +CONFIG_BLK_DEV_HPT366=y +# CONFIG_BLK_DEV_JMICRON is not set +# CONFIG_BLK_DEV_SC1200 is not set +# CONFIG_BLK_DEV_PIIX is not set +# CONFIG_BLK_DEV_IT821X is not set +# CONFIG_BLK_DEV_NS87415 is not set +# CONFIG_BLK_DEV_PDC202XX_OLD is not set +# CONFIG_BLK_DEV_PDC202XX_NEW is not set +# CONFIG_BLK_DEV_SVWKS is not set +# CONFIG_BLK_DEV_SIIMAGE is not set +# CONFIG_BLK_DEV_SLC90E66 is not set +# CONFIG_BLK_DEV_TRM290 is not set +# CONFIG_BLK_DEV_VIA82CXXX is not set +# CONFIG_IDE_ARM is not set +CONFIG_BLK_DEV_IDEDMA=y +# CONFIG_IDEDMA_IVB is not set +# CONFIG_IDEDMA_AUTO is not set +# CONFIG_BLK_DEV_HD is not set + +# +# SCSI device support +# +# CONFIG_RAID_ATTRS is not set +CONFIG_SCSI=y +# CONFIG_SCSI_NETLINK is not set +CONFIG_SCSI_PROC_FS=y + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=y +# CONFIG_CHR_DEV_ST is not set +# CONFIG_CHR_DEV_OSST is not set +# CONFIG_BLK_DEV_SR is not set +# CONFIG_CHR_DEV_SG is not set +# CONFIG_CHR_DEV_SCH is not set + +# +# Some SCSI devices (e.g. CD jukebox) support multiple LUNs +# +# CONFIG_SCSI_MULTI_LUN is not set +CONFIG_SCSI_CONSTANTS=y +# CONFIG_SCSI_LOGGING is not set + +# +# SCSI Transports +# +# CONFIG_SCSI_SPI_ATTRS is not set +# CONFIG_SCSI_FC_ATTRS is not set +CONFIG_SCSI_ISCSI_ATTRS=m +# CONFIG_SCSI_SAS_ATTRS is not set +# CONFIG_SCSI_SAS_LIBSAS is not set + +# +# SCSI low-level drivers +# +CONFIG_ISCSI_TCP=m +# CONFIG_BLK_DEV_3W_XXXX_RAID is not set +# CONFIG_SCSI_3W_9XXX is not set +# CONFIG_SCSI_ACARD is not set +# CONFIG_SCSI_AACRAID is not set +# CONFIG_SCSI_AIC7XXX is not set +# CONFIG_SCSI_AIC7XXX_OLD is not set +# CONFIG_SCSI_AIC79XX is not set +# CONFIG_SCSI_AIC94XX is not set +# CONFIG_SCSI_DPT_I2O is not set +# CONFIG_SCSI_ARCMSR is not set +# CONFIG_MEGARAID_NEWGEN is not set +# CONFIG_MEGARAID_LEGACY is not set +# CONFIG_MEGARAID_SAS is not set +# CONFIG_SCSI_HPTIOP is not set +# CONFIG_SCSI_DMX3191D is not set +# CONFIG_SCSI_FUTURE_DOMAIN is not set +# CONFIG_SCSI_IPS is not set +# CONFIG_SCSI_INITIO is not set +# CONFIG_SCSI_INIA100 is not set +# CONFIG_SCSI_STEX is not set +# CONFIG_SCSI_SYM53C8XX_2 is not set +# CONFIG_SCSI_QLOGIC_1280 is not set +# CONFIG_SCSI_QLA_FC is not set +# CONFIG_SCSI_QLA_ISCSI is not set +# CONFIG_SCSI_LPFC is not set +# CONFIG_SCSI_DC395x is not set +# CONFIG_SCSI_DC390T is not set +# CONFIG_SCSI_NSP32 is not set +# CONFIG_SCSI_DEBUG is not set + +# +# Serial ATA (prod) and Parallel ATA (experimental) drivers +# +# CONFIG_ATA is not set + +# +# Multi-device support (RAID and LVM) +# +# CONFIG_MD is not set + +# +# Fusion MPT device support +# +# CONFIG_FUSION is not set +# CONFIG_FUSION_SPI is not set +# CONFIG_FUSION_FC is not set +# CONFIG_FUSION_SAS is not set + +# +# IEEE 1394 (FireWire) support +# +# CONFIG_IEEE1394 is not set + +# +# I2O device support +# +# CONFIG_I2O is not set + +# +# Network device support +# +CONFIG_NETDEVICES=y +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_EQUALIZER is not set +# CONFIG_TUN is not set + +# +# ARCnet devices +# +# CONFIG_ARCNET is not set + +# +# PHY device support +# +# CONFIG_PHYLIB is not set + +# +# Ethernet (10 or 100Mbit) +# +CONFIG_NET_ETHERNET=y +CONFIG_MII=y +# CONFIG_HAPPYMEAL is not set +# CONFIG_SUNGEM is not set +# CONFIG_CASSINI is not set +# CONFIG_NET_VENDOR_3COM is not set +# CONFIG_DM9000 is not set + +# +# Tulip family network device support +# +# CONFIG_NET_TULIP is not set +# CONFIG_HP100 is not set +CONFIG_NET_PCI=y +# CONFIG_PCNET32 is not set +# CONFIG_AMD8111_ETH is not set +# CONFIG_ADAPTEC_STARFIRE is not set +# CONFIG_B44 is not set +# CONFIG_FORCEDETH is not set +# CONFIG_DGRS is not set +# CONFIG_EEPRO100 is not set +# CONFIG_E100 is not set +# CONFIG_FEALNX is not set +CONFIG_NATSEMI=y +# CONFIG_NE2K_PCI is not set +# CONFIG_8139CP is not set +# CONFIG_8139TOO is not set +# CONFIG_SIS900 is not set +# CONFIG_EPIC100 is not set +# CONFIG_SUNDANCE is not set +# CONFIG_TLAN is not set +# CONFIG_VIA_RHINE is not set + +# +# Ethernet (1000 Mbit) +# +# CONFIG_ACENIC is not set +# CONFIG_DL2K is not set +# CONFIG_E1000 is not set +# CONFIG_NS83820 is not set +# CONFIG_HAMACHI is not set +# CONFIG_YELLOWFIN is not set +# CONFIG_R8169 is not set +# CONFIG_SIS190 is not set +# CONFIG_SKGE is not set +# CONFIG_SKY2 is not set +# CONFIG_SK98LIN is not set +# CONFIG_VIA_VELOCITY is not set +# CONFIG_TIGON3 is not set +# CONFIG_BNX2 is not set +# CONFIG_QLA3XXX is not set + +# +# Ethernet (10000 Mbit) +# +# CONFIG_CHELSIO_T1 is not set +# CONFIG_IXGB is not set +# CONFIG_S2IO is not set +# CONFIG_MYRI10GE is not set +# CONFIG_NETXEN_NIC is not set + +# +# Token Ring devices +# +# CONFIG_TR is not set + +# +# Wireless LAN (non-hamradio) +# +# CONFIG_NET_RADIO is not set + +# +# Wan interfaces +# +# CONFIG_WAN is not set +# CONFIG_FDDI is not set +# CONFIG_HIPPI is not set +# CONFIG_PPP is not set +# CONFIG_SLIP is not set +# CONFIG_NET_FC is not set +# CONFIG_SHAPER is not set +# CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set + +# +# ISDN subsystem +# +# CONFIG_ISDN is not set + +# +# Telephony Support +# +# CONFIG_PHONE is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set + +# +# Userland interfaces +# +# CONFIG_INPUT_MOUSEDEV is not set +# CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_TSDEV is not set +# CONFIG_INPUT_EVDEV is not set +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set + +# +# Hardware I/O ports +# +CONFIG_SERIO=y +# CONFIG_SERIO_I8042 is not set +# CONFIG_SERIO_SERPORT is not set +# CONFIG_SERIO_PCIPS2 is not set +CONFIG_SERIO_LIBPS2=y +# CONFIG_SERIO_RAW is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_VT=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +# CONFIG_VT_HW_CONSOLE_BINDING is not set +# CONFIG_SERIAL_NONSTANDARD is not set + +# +# Serial drivers +# +# CONFIG_SERIAL_8250 is not set + +# +# Non-8250 serial port support +# +# CONFIG_SERIAL_PNX8XXX is not set +# CONFIG_SERIAL_JSM is not set +CONFIG_UNIX98_PTYS=y +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=256 + +# +# IPMI +# +# CONFIG_IPMI_HANDLER is not set + +# +# Watchdog Cards +# +# CONFIG_WATCHDOG is not set +CONFIG_HW_RANDOM=y +# CONFIG_RTC is not set +# CONFIG_GEN_RTC is not set +# CONFIG_DTLK is not set +# CONFIG_R3964 is not set +# CONFIG_APPLICOM is not set +# CONFIG_DRM is not set +# CONFIG_RAW_DRIVER is not set + +# +# TPM devices +# +# CONFIG_TCG_TPM is not set + +# +# I2C support +# +# CONFIG_I2C is not set + +# +# SPI support +# +# CONFIG_SPI is not set +# CONFIG_SPI_MASTER is not set + +# +# Dallas's 1-wire bus +# +# CONFIG_W1 is not set + +# +# Hardware Monitoring support +# +CONFIG_HWMON=y +# CONFIG_HWMON_VID is not set +# CONFIG_SENSORS_ABITUGURU is not set +# CONFIG_SENSORS_F71805F is not set +# CONFIG_SENSORS_VT1211 is not set +# CONFIG_HWMON_DEBUG_CHIP is not set + +# +# Multimedia devices +# +# CONFIG_VIDEO_DEV is not set + +# +# Digital Video Broadcasting Devices +# +# CONFIG_DVB is not set +# CONFIG_USB_DABUSB is not set + +# +# Graphics support +# +CONFIG_FIRMWARE_EDID=y +# CONFIG_FB is not set + +# +# Console display driver support +# +# CONFIG_VGA_CONSOLE is not set +CONFIG_DUMMY_CONSOLE=y +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set + +# +# Sound +# +# CONFIG_SOUND is not set + +# +# USB support +# +CONFIG_USB_ARCH_HAS_HCD=y +CONFIG_USB_ARCH_HAS_OHCI=y +CONFIG_USB_ARCH_HAS_EHCI=y +CONFIG_USB=y +# CONFIG_USB_DEBUG is not set + +# +# Miscellaneous USB options +# +# CONFIG_USB_DEVICEFS is not set +# CONFIG_USB_BANDWIDTH is not set +# CONFIG_USB_DYNAMIC_MINORS is not set +# CONFIG_USB_MULTITHREAD_PROBE is not set +# CONFIG_USB_OTG is not set + +# +# USB Host Controller Drivers +# +# CONFIG_USB_EHCI_HCD is not set +# CONFIG_USB_ISP116X_HCD is not set +CONFIG_USB_OHCI_HCD=y +# CONFIG_USB_OHCI_BIG_ENDIAN is not set +CONFIG_USB_OHCI_LITTLE_ENDIAN=y +# CONFIG_USB_UHCI_HCD is not set +# CONFIG_USB_SL811_HCD is not set + +# +# USB Device Class drivers +# +# CONFIG_USB_ACM is not set +# CONFIG_USB_PRINTER is not set + +# +# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' +# + +# +# may also be needed; see USB_STORAGE Help for more information +# +CONFIG_USB_STORAGE=y +# CONFIG_USB_STORAGE_DEBUG is not set +CONFIG_USB_STORAGE_DATAFAB=y +CONFIG_USB_STORAGE_FREECOM=y +CONFIG_USB_STORAGE_ISD200=y +CONFIG_USB_STORAGE_DPCM=y +CONFIG_USB_STORAGE_USBAT=y +CONFIG_USB_STORAGE_SDDR09=y +CONFIG_USB_STORAGE_SDDR55=y +CONFIG_USB_STORAGE_JUMPSHOT=y +# CONFIG_USB_STORAGE_ALAUDA is not set +# CONFIG_USB_STORAGE_KARMA is not set +# CONFIG_USB_LIBUSUAL is not set + +# +# USB Input Devices +# +# CONFIG_USB_HID is not set + +# +# USB HID Boot Protocol drivers +# +# CONFIG_USB_KBD is not set +# CONFIG_USB_MOUSE is not set +# CONFIG_USB_AIPTEK is not set +# CONFIG_USB_WACOM is not set +# CONFIG_USB_ACECAD is not set +# CONFIG_USB_KBTAB is not set +# CONFIG_USB_POWERMATE is not set +# CONFIG_USB_TOUCHSCREEN is not set +# CONFIG_USB_YEALINK is not set +# CONFIG_USB_XPAD is not set +# CONFIG_USB_ATI_REMOTE is not set +# CONFIG_USB_ATI_REMOTE2 is not set +# CONFIG_USB_KEYSPAN_REMOTE is not set +# CONFIG_USB_APPLETOUCH is not set + +# +# USB Imaging devices +# +# CONFIG_USB_MDC800 is not set +# CONFIG_USB_MICROTEK is not set + +# +# USB Network Adapters +# +# CONFIG_USB_CATC is not set +# CONFIG_USB_KAWETH is not set +# CONFIG_USB_PEGASUS is not set +# CONFIG_USB_RTL8150 is not set +# CONFIG_USB_USBNET_MII is not set +# CONFIG_USB_USBNET is not set +CONFIG_USB_MON=y + +# +# USB port drivers +# + +# +# USB Serial Converter support +# +# CONFIG_USB_SERIAL is not set + +# +# USB Miscellaneous drivers +# +# CONFIG_USB_EMI62 is not set +# CONFIG_USB_EMI26 is not set +# CONFIG_USB_ADUTUX is not set +# CONFIG_USB_AUERSWALD is not set +# CONFIG_USB_RIO500 is not set +# CONFIG_USB_LEGOTOWER is not set +# CONFIG_USB_LCD is not set +# CONFIG_USB_LED is not set +# CONFIG_USB_CYPRESS_CY7C63 is not set +# CONFIG_USB_CYTHERM is not set +# CONFIG_USB_PHIDGET is not set +# CONFIG_USB_IDMOUSE is not set +# CONFIG_USB_FTDI_ELAN is not set +# CONFIG_USB_APPLEDISPLAY is not set +# CONFIG_USB_LD is not set +# CONFIG_USB_TRANCEVIBRATOR is not set + +# +# USB DSL modem support +# + +# +# USB Gadget Support +# +# CONFIG_USB_GADGET is not set + +# +# MMC/SD Card support +# +# CONFIG_MMC is not set + +# +# LED devices +# +# CONFIG_NEW_LEDS is not set + +# +# LED drivers +# + +# +# LED Triggers +# + +# +# InfiniBand support +# +# CONFIG_INFINIBAND is not set + +# +# EDAC - error detection and reporting (RAS) (EXPERIMENTAL) +# + +# +# Real Time Clock +# +# CONFIG_RTC_CLASS is not set + +# +# DMA Engine support +# +# CONFIG_DMA_ENGINE is not set + +# +# DMA Clients +# + +# +# DMA Devices +# + +# +# File systems +# +CONFIG_EXT2_FS=y +# CONFIG_EXT2_FS_XATTR is not set +# CONFIG_EXT2_FS_XIP is not set +# CONFIG_EXT3_FS is not set +# CONFIG_EXT4DEV_FS is not set +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +# CONFIG_FS_POSIX_ACL is not set +# CONFIG_XFS_FS is not set +# CONFIG_GFS2_FS is not set +# CONFIG_OCFS2_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_ROMFS_FS is not set +CONFIG_INOTIFY=y +CONFIG_INOTIFY_USER=y +# CONFIG_QUOTA is not set +# CONFIG_DNOTIFY is not set +# CONFIG_AUTOFS_FS is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_FUSE_FS is not set + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=y +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +# CONFIG_PROC_KCORE is not set +CONFIG_PROC_SYSCTL=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +# CONFIG_TMPFS_POSIX_ACL is not set +# CONFIG_HUGETLB_PAGE is not set +CONFIG_RAMFS=y +# CONFIG_CONFIGFS_FS is not set + +# +# Miscellaneous filesystems +# +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +# CONFIG_CRAMFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set + +# +# Network File Systems +# +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +# CONFIG_NFS_V3_ACL is not set +# CONFIG_NFS_V4 is not set +# CONFIG_NFS_DIRECTIO is not set +CONFIG_NFSD=m +# CONFIG_NFSD_V3 is not set +# CONFIG_NFSD_TCP is not set +CONFIG_ROOT_NFS=y +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +CONFIG_EXPORTFS=m +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +# CONFIG_RPCSEC_GSS_KRB5 is not set +# CONFIG_RPCSEC_GSS_SPKM3 is not set +# CONFIG_SMB_FS is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set +# CONFIG_9P_FS is not set + +# +# Partition Types +# +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_MSDOS_PARTITION=y + +# +# Native Language Support +# +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="iso8859-1" +# CONFIG_NLS_CODEPAGE_437 is not set +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +# CONFIG_NLS_CODEPAGE_850 is not set +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +# CONFIG_NLS_ASCII is not set +# CONFIG_NLS_ISO8859_1 is not set +# CONFIG_NLS_ISO8859_2 is not set +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +# CONFIG_NLS_UTF8 is not set + +# +# Profiling support +# +# CONFIG_PROFILING is not set + +# +# Kernel hacking +# +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +# CONFIG_PRINTK_TIME is not set +CONFIG_ENABLE_MUST_CHECK=y +CONFIG_MAGIC_SYSRQ=y +# CONFIG_UNUSED_SYMBOLS is not set +CONFIG_DEBUG_KERNEL=y +CONFIG_LOG_BUF_SHIFT=14 +CONFIG_DETECT_SOFTLOCKUP=y +# CONFIG_SCHEDSTATS is not set +CONFIG_DEBUG_SLAB=y +# CONFIG_DEBUG_SLAB_LEAK is not set +# CONFIG_DEBUG_RT_MUTEXES is not set +# CONFIG_RT_MUTEX_TESTER is not set +# CONFIG_DEBUG_SPINLOCK is not set +# CONFIG_DEBUG_MUTEXES is not set +# CONFIG_DEBUG_RWSEMS is not set +# CONFIG_DEBUG_LOCK_ALLOC is not set +# CONFIG_PROVE_LOCKING is not set +# CONFIG_DEBUG_SPINLOCK_SLEEP is not set +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set +# CONFIG_DEBUG_KOBJECT is not set +# CONFIG_DEBUG_INFO is not set +# CONFIG_DEBUG_FS is not set +# CONFIG_DEBUG_VM is not set +# CONFIG_DEBUG_LIST is not set +CONFIG_FORCED_INLINING=y +CONFIG_HEADERS_CHECK=y +# CONFIG_RCU_TORTURE_TEST is not set +CONFIG_CROSSCOMPILE=y +CONFIG_CMDLINE="console=ttyS1,38400n8 kgdb=ttyS0 root=/dev/nfs ip=bootp" +# CONFIG_DEBUG_STACK_USAGE is not set +# CONFIG_KGDB is not set +# CONFIG_RUNTIME_DEBUG is not set +# CONFIG_MIPS_UNCACHED is not set + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITY is not set + +# +# Cryptographic options +# +CONFIG_CRYPTO=y +CONFIG_CRYPTO_ALGAPI=m +CONFIG_CRYPTO_BLKCIPHER=m +CONFIG_CRYPTO_MANAGER=m +# CONFIG_CRYPTO_HMAC is not set +# CONFIG_CRYPTO_NULL is not set +# CONFIG_CRYPTO_MD4 is not set +CONFIG_CRYPTO_MD5=m +# CONFIG_CRYPTO_SHA1 is not set +# CONFIG_CRYPTO_SHA256 is not set +# CONFIG_CRYPTO_SHA512 is not set +# CONFIG_CRYPTO_WP512 is not set +# CONFIG_CRYPTO_TGR192 is not set +CONFIG_CRYPTO_ECB=m +CONFIG_CRYPTO_CBC=m +# CONFIG_CRYPTO_DES is not set +# CONFIG_CRYPTO_BLOWFISH is not set +# CONFIG_CRYPTO_TWOFISH is not set +# CONFIG_CRYPTO_SERPENT is not set +# CONFIG_CRYPTO_AES is not set +# CONFIG_CRYPTO_CAST5 is not set +# CONFIG_CRYPTO_CAST6 is not set +# CONFIG_CRYPTO_TEA is not set +# CONFIG_CRYPTO_ARC4 is not set +# CONFIG_CRYPTO_KHAZAD is not set +# CONFIG_CRYPTO_ANUBIS is not set +# CONFIG_CRYPTO_DEFLATE is not set +# CONFIG_CRYPTO_MICHAEL_MIC is not set +CONFIG_CRYPTO_CRC32C=m +# CONFIG_CRYPTO_TEST is not set + +# +# Hardware crypto devices +# + +# +# Library routines +# +CONFIG_CRC_CCITT=m +# CONFIG_CRC16 is not set +CONFIG_CRC32=y +CONFIG_LIBCRC32C=m +CONFIG_PLIST=y diff --git a/arch/mips/pci/fixup-pnx8550.c b/arch/mips/pci/fixup-pnx8550.c index 4256b3b..50546da 100644 --- a/arch/mips/pci/fixup-pnx8550.c +++ b/arch/mips/pci/fixup-pnx8550.c @@ -33,7 +33,7 @@ #define DBG(x...) #endif -extern char irq_tab_jbs[][5]; +extern char pnx8550_irq_tab[][5]; void __init pcibios_fixup_resources(struct pci_dev *dev) { @@ -47,7 +47,7 @@ void __init pcibios_fixup(void) int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin) { - return irq_tab_jbs[slot][pin]; + return pnx8550_irq_tab[slot][pin]; } /* Do platform specific device initialization at pci_enable_device() time */ diff --git a/arch/mips/philips/pnx8550/common/prom.c b/arch/mips/philips/pnx8550/common/prom.c index f8952c1..eb6ec11 100644 --- a/arch/mips/philips/pnx8550/common/prom.c +++ b/arch/mips/philips/pnx8550/common/prom.c @@ -35,23 +35,15 @@ char * prom_getcmdline(void) return &(arcs_cmdline[0]); } -void prom_init_cmdline(void) +void __init prom_init_cmdline(void) { - char *cp; - int actr; - - actr = 1; /* Always ignore argv[0] */ + int i; - cp = &(arcs_cmdline[0]); - while(actr < prom_argc) { - strcpy(cp, prom_argv[actr]); - cp += strlen(prom_argv[actr]); - *cp++ = ' '; - actr++; + arcs_cmdline[0] = '\0'; + for (i = 0; i < prom_argc; i++) { + strcat(arcs_cmdline, prom_argv[i]); + strcat(arcs_cmdline, " "); } - if (cp != &(arcs_cmdline[0])) /* get rid of trailing space */ - --cp; - *cp = '\0'; } char *prom_getenv(char *envname) diff --git a/arch/mips/philips/pnx8550/jbs/irqmap.c b/arch/mips/philips/pnx8550/jbs/irqmap.c index f78e042..98c3429 100644 --- a/arch/mips/philips/pnx8550/jbs/irqmap.c +++ b/arch/mips/philips/pnx8550/jbs/irqmap.c @@ -28,9 +28,9 @@ #include #include -char irq_tab_jbs[][5] __initdata = { - [8] = { -1, PNX8550_INT_PCI_INTA, 0xff, 0xff, 0xff}, - [9] = { -1, PNX8550_INT_PCI_INTA, 0xff, 0xff, 0xff}, - [17] = { -1, PNX8550_INT_PCI_INTA, 0xff, 0xff, 0xff}, +char pnx8550_irq_tab[][5] __initdata = { + [8] = { -1, PNX8550_INT_PCI_INTA, 0xff, 0xff, 0xff}, + [9] = { -1, PNX8550_INT_PCI_INTA, 0xff, 0xff, 0xff}, + [17] = { -1, PNX8550_INT_PCI_INTA, 0xff, 0xff, 0xff}, }; diff --git a/arch/mips/philips/pnx8550/stb810/Makefile b/arch/mips/philips/pnx8550/stb810/Makefile new file mode 100644 index 0000000..f14b592 --- /dev/null +++ b/arch/mips/philips/pnx8550/stb810/Makefile @@ -0,0 +1,4 @@ + +# Makefile for the Philips STB810 Board. + +lib-y := prom_init.o board_setup.o irqmap.o diff --git a/arch/mips/philips/pnx8550/stb810/board_setup.c b/arch/mips/philips/pnx8550/stb810/board_setup.c new file mode 100644 index 0000000..345d71e --- /dev/null +++ b/arch/mips/philips/pnx8550/stb810/board_setup.c @@ -0,0 +1,49 @@ +/* + * STB810 specific board startup routines. + * + * Based on the arch/mips/philips/pnx8550/jbs/board_setup.c + * + * Author: MontaVista Software, Inc. + * source@mvista.com + * + * Copyright 2005 MontaVista Software Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +#include + +void __init board_setup(void) +{ + unsigned long config0, configpr; + + config0 = read_c0_config(); + + /* clear all three cache coherency fields */ + config0 &= ~(0x7 | (7<<25) | (7<<28)); + config0 |= (CONF_CM_DEFAULT | (CONF_CM_DEFAULT<<25) | + (CONF_CM_DEFAULT<<28)); + write_c0_config(config0); + + configpr = read_c0_config7(); + configpr |= (1<<19); /* enable tlb */ + write_c0_config7(configpr); +} diff --git a/arch/mips/philips/pnx8550/stb810/irqmap.c b/arch/mips/philips/pnx8550/stb810/irqmap.c new file mode 100644 index 0000000..5ee11e1 --- /dev/null +++ b/arch/mips/philips/pnx8550/stb810/irqmap.c @@ -0,0 +1,23 @@ +/* + * Philips STB810 board irqmap. + * + * Author: MontaVista Software, Inc. + * source@mvista.com + * + * Copyright 2005 MontaVista Software Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#include +#include + +char pnx8550_irq_tab[][5] __initdata = { + [8] = { -1, PNX8550_INT_PCI_INTA, 0xff, 0xff, 0xff}, + [9] = { -1, PNX8550_INT_PCI_INTA, 0xff, 0xff, 0xff}, + [10] = { -1, PNX8550_INT_PCI_INTA, 0xff, 0xff, 0xff}, +}; + diff --git a/arch/mips/philips/pnx8550/stb810/prom_init.c b/arch/mips/philips/pnx8550/stb810/prom_init.c new file mode 100644 index 0000000..ea5b4e0 --- /dev/null +++ b/arch/mips/philips/pnx8550/stb810/prom_init.c @@ -0,0 +1,49 @@ +/* + * STB810 specific prom routines + * + * Author: MontaVista Software, Inc. + * source@mvista.com + * + * Copyright 2005 MontaVista Software Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +int prom_argc; +char **prom_argv, **prom_envp; +extern void __init prom_init_cmdline(void); +extern char *prom_getenv(char *envname); + +const char *get_system_type(void) +{ + return "Philips PNX8550/STB810"; +} + +void __init prom_init(void) +{ + unsigned long memsize; + + prom_argc = (int) fw_arg0; + prom_argv = (char **) fw_arg1; + prom_envp = (char **) fw_arg2; + + prom_init_cmdline(); + + mips_machgroup = MACH_GROUP_PHILIPS; + mips_machtype = MACH_PHILIPS_STB810; + + memsize = 0x08000000; /* Trimedia uses memory above */ + add_memory_region(0, memsize, BOOT_MEM_RAM); +} -- cgit v1.1 From 1f29bcd739972f71f2fd5d5d265daf3e1208fa5e Mon Sep 17 00:00:00 2001 From: Alexey Dobriyan Date: Sun, 10 Dec 2006 02:19:10 -0800 Subject: [PATCH] sysctl: remove unused "context" param Signed-off-by: Alexey Dobriyan Cc: Andi Kleen Cc: "David S. Miller" Cc: David Howells Cc: Ralf Baechle Cc: "Eric W. Biederman" Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- arch/mips/lasat/sysctl.c | 17 ++++++++--------- 1 file changed, 8 insertions(+), 9 deletions(-) (limited to 'arch/mips') diff --git a/arch/mips/lasat/sysctl.c b/arch/mips/lasat/sysctl.c index da35d45..1287835 100644 --- a/arch/mips/lasat/sysctl.c +++ b/arch/mips/lasat/sysctl.c @@ -40,12 +40,12 @@ static DEFINE_MUTEX(lasat_info_mutex); /* Strategy function to write EEPROM after changing string entry */ int sysctl_lasatstring(ctl_table *table, int *name, int nlen, void *oldval, size_t *oldlenp, - void *newval, size_t newlen, void **context) + void *newval, size_t newlen) { int r; mutex_lock(&lasat_info_mutex); r = sysctl_string(table, name, - nlen, oldval, oldlenp, newval, newlen, context); + nlen, oldval, oldlenp, newval, newlen); if (r < 0) { mutex_unlock(&lasat_info_mutex); return r; @@ -119,11 +119,11 @@ int proc_dolasatrtc(ctl_table *table, int write, struct file *filp, /* Sysctl for setting the IP addresses */ int sysctl_lasat_intvec(ctl_table *table, int *name, int nlen, void *oldval, size_t *oldlenp, - void *newval, size_t newlen, void **context) + void *newval, size_t newlen) { int r; mutex_lock(&lasat_info_mutex); - r = sysctl_intvec(table, name, nlen, oldval, oldlenp, newval, newlen, context); + r = sysctl_intvec(table, name, nlen, oldval, oldlenp, newval, newlen); if (r < 0) { mutex_unlock(&lasat_info_mutex); return r; @@ -139,14 +139,14 @@ int sysctl_lasat_intvec(ctl_table *table, int *name, int nlen, /* Same for RTC */ int sysctl_lasat_rtc(ctl_table *table, int *name, int nlen, void *oldval, size_t *oldlenp, - void *newval, size_t newlen, void **context) + void *newval, size_t newlen) { int r; mutex_lock(&lasat_info_mutex); rtctmp = ds1603_read(); if (rtctmp < 0) rtctmp = 0; - r = sysctl_intvec(table, name, nlen, oldval, oldlenp, newval, newlen, context); + r = sysctl_intvec(table, name, nlen, oldval, oldlenp, newval, newlen); if (r < 0) { mutex_unlock(&lasat_info_mutex); return r; @@ -251,13 +251,12 @@ int proc_lasat_ip(ctl_table *table, int write, struct file *filp, static int sysctl_lasat_eeprom_value(ctl_table *table, int *name, int nlen, void *oldval, size_t *oldlenp, - void *newval, size_t newlen, - void **context) + void *newval, size_t newlen) { int r; mutex_lock(&lasat_info_mutex); - r = sysctl_intvec(table, name, nlen, oldval, oldlenp, newval, newlen, context); + r = sysctl_intvec(table, name, nlen, oldval, oldlenp, newval, newlen); if (r < 0) { mutex_unlock(&lasat_info_mutex); return r; -- cgit v1.1 From bbea9f69668a3d0cf9feba15a724cd02896f8675 Mon Sep 17 00:00:00 2001 From: Vadim Lobanov Date: Sun, 10 Dec 2006 02:21:12 -0800 Subject: [PATCH] fdtable: Make fdarray and fdsets equal in size Currently, each fdtable supports three dynamically-sized arrays of data: the fdarray and two fdsets. The code allows the number of fds supported by the fdarray (fdtable->max_fds) to differ from the number of fds supported by each of the fdsets (fdtable->max_fdset). In practice, it is wasteful for these two sizes to differ: whenever we hit a limit on the smaller-capacity structure, we will reallocate the entire fdtable and all the dynamic arrays within it, so any delta in the memory used by the larger-capacity structure will never be touched at all. Rather than hogging this excess, we shouldn't even allocate it in the first place, and keep the capacities of the fdarray and the fdsets equal. This patch removes fdtable->max_fdset. As an added bonus, most of the supporting code becomes simpler. Signed-off-by: Vadim Lobanov Cc: Christoph Hellwig Cc: Al Viro Cc: Dipankar Sarma Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- arch/mips/kernel/kspd.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/mips') diff --git a/arch/mips/kernel/kspd.c b/arch/mips/kernel/kspd.c index 2c82412..5929f883 100644 --- a/arch/mips/kernel/kspd.c +++ b/arch/mips/kernel/kspd.c @@ -301,7 +301,7 @@ static void sp_cleanup(void) for (;;) { unsigned long set; i = j * __NFDBITS; - if (i >= fdt->max_fdset || i >= fdt->max_fds) + if (i >= fdt->max_fds) break; set = fdt->open_fds->fds_bits[j++]; while (set) { -- cgit v1.1 From 86384d544157db23879064cde36061cdcafc6794 Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Sun, 10 Dec 2006 14:57:28 +0000 Subject: [MIPS] Discard .exit.text at linktime. This fixes fairly unobvious breakage of various drivers. Signed-off-by: Ralf Baechle --- arch/mips/kernel/vmlinux.lds.S | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) (limited to 'arch/mips') diff --git a/arch/mips/kernel/vmlinux.lds.S b/arch/mips/kernel/vmlinux.lds.S index 79f0317..2f4508f 100644 --- a/arch/mips/kernel/vmlinux.lds.S +++ b/arch/mips/kernel/vmlinux.lds.S @@ -109,9 +109,6 @@ SECTIONS .con_initcall.init : { *(.con_initcall.init) } __con_initcall_end = .; SECURITY_INIT - /* .exit.text is discarded at runtime, not link time, to deal with - references from .rodata */ - .exit.text : { *(.exit.text) } . = ALIGN(_PAGE_SIZE); __initramfs_start = .; .init.ramfs : { *(.init.ramfs) } @@ -139,6 +136,7 @@ SECTIONS /* Sections to be discarded */ /DISCARD/ : { + *(.exit.text) *(.exit.data) *(.exitcall.exit) -- cgit v1.1 From ae32ffd65bbcc32795bb9b58ed12941efeb03dff Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Sun, 10 Dec 2006 15:05:11 +0000 Subject: [MIPS] Export csum_partial_copy_nocheck. ibmtr.c and typhoon.c use it. Signed-off-by: Ralf Baechle --- arch/mips/lib/csum_partial_copy.c | 3 +++ 1 file changed, 3 insertions(+) (limited to 'arch/mips') diff --git a/arch/mips/lib/csum_partial_copy.c b/arch/mips/lib/csum_partial_copy.c index 1720f2c..0677104 100644 --- a/arch/mips/lib/csum_partial_copy.c +++ b/arch/mips/lib/csum_partial_copy.c @@ -7,6 +7,7 @@ * Copyright (C) 1998, 1999 Ralf Baechle */ #include +#include #include #include #include @@ -29,6 +30,8 @@ __wsum csum_partial_copy_nocheck(const void *src, return sum; } +EXPORT_SYMBOL(csum_partial_copy_nocheck); + /* * Copy from userspace and compute checksum. If we catch an exception * then zero the rest of the buffer. -- cgit v1.1 From f8bf35a9145b0831d7d110402662d9cff2d90bd9 Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Sun, 10 Dec 2006 15:09:38 +0000 Subject: [MIPS] Export pm_power_off This is required for ipmi_poweroff.c to work as a module. Signed-off-by: Ralf Baechle --- arch/mips/kernel/reset.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/mips') diff --git a/arch/mips/kernel/reset.c b/arch/mips/kernel/reset.c index 621037d..060563a 100644 --- a/arch/mips/kernel/reset.c +++ b/arch/mips/kernel/reset.c @@ -23,6 +23,8 @@ void (*_machine_restart)(char *command); void (*_machine_halt)(void); void (*pm_power_off)(void); +EXPORT_SYMBOL(pm_power_off); + void machine_restart(char *command) { if (_machine_restart) -- cgit v1.1 From 9202f32558601c2c99ddc438eb3218131d00d413 Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Sun, 10 Dec 2006 18:43:59 +0000 Subject: [MIPS] Export local_flush_data_cache_page for sake of IDE. On a CPU with aliases the IDE core needs to flush caches in the special IDE variants of insw, insl etc. If IDE support is built as a module this will only work if local_flush_data_cache_page happens is exported as a module. As per policy export local_flush_data_cache_page as GPL symbol only. Signed-off-by: Ralf Baechle --- arch/mips/mm/cache.c | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/mips') diff --git a/arch/mips/mm/cache.c b/arch/mips/mm/cache.c index caf807d..1f954a2 100644 --- a/arch/mips/mm/cache.c +++ b/arch/mips/mm/cache.c @@ -32,6 +32,7 @@ void (*local_flush_data_cache_page)(void * addr); void (*flush_data_cache_page)(unsigned long addr); void (*flush_icache_all)(void); +EXPORT_SYMBOL_GPL(local_flush_data_cache_page); EXPORT_SYMBOL(flush_data_cache_page); #ifdef CONFIG_DMA_NONCOHERENT -- cgit v1.1 From 2efac77e82a36bf616d474f2eb721d95543cfae9 Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Mon, 11 Dec 2006 11:54:52 +0000 Subject: [MIPS] Discard .exit.text and .exit.data at runtime. While the recent cset 86384d544157db23879064cde36061cdcafc6794 did improve things it didn't resolve all the problems. So bite the bullet and discard .exit.text and .exit.data at runtime. Which of course sucks because it bloats binaries with code that will never ever be used but it's the only thing that will work reliable as demonstrated by the function sd_major() in drivers/scsi/sd.c. Gcc may compile sd_major() using a jump table which it will put into .rodata. If it also inlines sd_major's function body into exit_sd() which gcc > 3.4.x does. If CONFIG_BLK_DEV_SD has been set to y we would like ld to discard exit_sd's code at link time. However sd_major happens to contain a switch statement which gcc will compile using a jump table in .rodata on the architectures I checked. So, when ld later discards .exit.text only the jump table in .rodata with its stale references to the discard .exit.text will be left which any no antique ld will honor with a link error. Signed-off-by: Ralf Baechle --- arch/mips/kernel/vmlinux.lds.S | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'arch/mips') diff --git a/arch/mips/kernel/vmlinux.lds.S b/arch/mips/kernel/vmlinux.lds.S index 2f4508f..cecff24 100644 --- a/arch/mips/kernel/vmlinux.lds.S +++ b/arch/mips/kernel/vmlinux.lds.S @@ -109,6 +109,10 @@ SECTIONS .con_initcall.init : { *(.con_initcall.init) } __con_initcall_end = .; SECURITY_INIT + /* .exit.text is discarded at runtime, not link time, to deal with + references from .rodata */ + .exit.text : { *(.exit.text) } + .exit.data : { *(.exit.data) } . = ALIGN(_PAGE_SIZE); __initramfs_start = .; .init.ramfs : { *(.init.ramfs) } @@ -136,8 +140,6 @@ SECTIONS /* Sections to be discarded */ /DISCARD/ : { - *(.exit.text) - *(.exit.data) *(.exitcall.exit) /* ABI crap starts here */ -- cgit v1.1 From b228f4c54df37b53c6f364aa7f3efa4280bcc4f0 Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Mon, 11 Dec 2006 15:33:30 +0000 Subject: [MIPS] Malta: Resurrect MTD support for onboard flash. Signed-off-by: Ralf Baechle --- arch/mips/configs/malta_defconfig | 80 ++++++++++++++++++++++++++++++- arch/mips/mips-boards/malta/Makefile | 2 +- arch/mips/mips-boards/malta/malta_setup.c | 39 --------------- 3 files changed, 80 insertions(+), 41 deletions(-) (limited to 'arch/mips') diff --git a/arch/mips/configs/malta_defconfig b/arch/mips/configs/malta_defconfig index 1f9300f..96e9410 100644 --- a/arch/mips/configs/malta_defconfig +++ b/arch/mips/configs/malta_defconfig @@ -644,7 +644,85 @@ CONFIG_CONNECTOR=m # # Memory Technology Devices (MTD) # -# CONFIG_MTD is not set +CONFIG_MTD=y +# CONFIG_MTD_DEBUG is not set +# CONFIG_MTD_CONCAT is not set +CONFIG_MTD_PARTITIONS=y +# CONFIG_MTD_REDBOOT_PARTS is not set +# CONFIG_MTD_CMDLINE_PARTS is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLOCK=y +# CONFIG_FTL is not set +# CONFIG_NFTL is not set +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set + +# +# RAM/ROM/Flash chip drivers +# +CONFIG_MTD_CFI=y +# CONFIG_MTD_JEDECPROBE is not set +CONFIG_MTD_GEN_PROBE=y +# CONFIG_MTD_CFI_ADV_OPTIONS is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +CONFIG_MTD_CFI_INTELEXT=y +CONFIG_MTD_CFI_AMDSTD=y +CONFIG_MTD_CFI_STAA=y +CONFIG_MTD_CFI_UTIL=y +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set +# CONFIG_MTD_OBSOLETE_CHIPS is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +CONFIG_MTD_PHYSMAP=y +CONFIG_MTD_PHYSMAP_START=0x0 +CONFIG_MTD_PHYSMAP_LEN=0x0 +CONFIG_MTD_PHYSMAP_BANKWIDTH=0 +# CONFIG_MTD_PLATRAM is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_PMC551 is not set +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOC2001PLUS is not set + +# +# NAND Flash Device Drivers +# +# CONFIG_MTD_NAND is not set + +# +# OneNAND Flash Device Drivers +# +# CONFIG_MTD_ONENAND is not set # # Parallel port support diff --git a/arch/mips/mips-boards/malta/Makefile b/arch/mips/mips-boards/malta/Makefile index 77ee5c6..b662c75 100644 --- a/arch/mips/mips-boards/malta/Makefile +++ b/arch/mips/mips-boards/malta/Makefile @@ -19,5 +19,5 @@ # under Linux. # -obj-y := malta_int.o malta_setup.o +obj-y := malta_int.o malta_mtd.o malta_setup.o obj-$(CONFIG_SMP) += malta_smp.o diff --git a/arch/mips/mips-boards/malta/malta_setup.c b/arch/mips/mips-boards/malta/malta_setup.c index 282f3e5..56ea766 100644 --- a/arch/mips/mips-boards/malta/malta_setup.c +++ b/arch/mips/mips-boards/malta/malta_setup.c @@ -21,13 +21,6 @@ #include #include -#ifdef CONFIG_MTD -#include -#include -#include -#include -#endif - #include #include #include @@ -58,30 +51,6 @@ struct resource standard_io_resources[] = { { .name = "dma2", .start = 0xc0, .end = 0xdf, .flags = IORESOURCE_BUSY }, }; -#ifdef CONFIG_MTD -static struct mtd_partition malta_mtd_partitions[] = { - { - .name = "YAMON", - .offset = 0x0, - .size = 0x100000, - .mask_flags = MTD_WRITEABLE - }, - { - .name = "User FS", - .offset = 0x100000, - .size = 0x2e0000 - }, - { - .name = "Board Config", - .offset = 0x3e0000, - .size = 0x020000, - .mask_flags = MTD_WRITEABLE - } -}; - -#define number_partitions (sizeof(malta_mtd_partitions)/sizeof(struct mtd_partition)) -#endif - const char *get_system_type(void) { return "MIPS Malta"; @@ -211,14 +180,6 @@ void __init plat_mem_setup(void) #endif #endif -#ifdef CONFIG_MTD - /* - * Support for MTD on Malta. Use the generic physmap driver - */ - physmap_configure(0x1e000000, 0x400000, 4, NULL); - physmap_set_partitions(malta_mtd_partitions, number_partitions); -#endif - mips_reboot_setup(); board_time_init = mips_time_init; -- cgit v1.1 From cbb8fc07974073543fdc61da23713ab49ddd3ced Mon Sep 17 00:00:00 2001 From: Franck Bui-Huu Date: Wed, 6 Dec 2006 16:48:28 +0100 Subject: [MIPS] paging_init(): use highend_pfn/highstart_pfn This patch makes paging_init() use highend_pfn/highstart_pfn globals. It removes the need of 'high' local which was needed only by HIGHMEM config. More important perhaps, it fixes a bug when HIGHMEM is set but there's actually no physical highmem (highend_pfn = 0) Signed-off-by: Franck Bui-Huu Signed-off-by: Ralf Baechle --- arch/mips/mm/init.c | 17 ++++++++--------- 1 file changed, 8 insertions(+), 9 deletions(-) (limited to 'arch/mips') diff --git a/arch/mips/mm/init.c b/arch/mips/mm/init.c index 9e29ba9..ea2d153 100644 --- a/arch/mips/mm/init.c +++ b/arch/mips/mm/init.c @@ -316,7 +316,7 @@ static int __init page_is_ram(unsigned long pagenr) void __init paging_init(void) { unsigned long zones_size[MAX_NR_ZONES] = { 0, }; - unsigned long max_dma, high, low; + unsigned long max_dma, low; #ifndef CONFIG_FLATMEM unsigned long zholes_size[MAX_NR_ZONES] = { 0, }; unsigned long i, j, pfn; @@ -331,7 +331,6 @@ void __init paging_init(void) max_dma = virt_to_phys((char *)MAX_DMA_ADDRESS) >> PAGE_SHIFT; low = max_low_pfn; - high = highend_pfn; #ifdef CONFIG_ISA if (low < max_dma) @@ -344,13 +343,13 @@ void __init paging_init(void) zones_size[ZONE_DMA] = low; #endif #ifdef CONFIG_HIGHMEM - if (cpu_has_dc_aliases) { - printk(KERN_WARNING "This processor doesn't support highmem."); - if (high - low) - printk(" %ldk highmem ignored", high - low); - printk("\n"); - } else - zones_size[ZONE_HIGHMEM] = high - low; + zones_size[ZONE_HIGHMEM] = highend_pfn - highstart_pfn; + + if (cpu_has_dc_aliases && zones_size[ZONE_HIGHMEM]) { + printk(KERN_WARNING "This processor doesn't support highmem." + " %ldk highmem ignored\n", zones_size[ZONE_HIGHMEM]); + zones_size[ZONE_HIGHMEM] = 0; + } #endif #ifdef CONFIG_FLATMEM -- cgit v1.1 From 5cbded585d129d0226cb48ac4202b253c781be26 Mon Sep 17 00:00:00 2001 From: "Robert P. J. Day" Date: Wed, 13 Dec 2006 00:35:56 -0800 Subject: [PATCH] getting rid of all casts of k[cmz]alloc() calls Run this: #!/bin/sh for f in $(grep -Erl "\([^\)]*\) *k[cmz]alloc" *) ; do echo "De-casting $f..." perl -pi -e "s/ ?= ?\([^\)]*\) *(k[cmz]alloc) *\(/ = \1\(/" $f done And then go through and reinstate those cases where code is casting pointers to non-pointers. And then drop a few hunks which conflicted with outstanding work. Cc: Russell King , Ian Molton Cc: Mikael Starvik Cc: Yoshinori Sato Cc: Roman Zippel Cc: Geert Uytterhoeven Cc: Ralf Baechle Cc: Paul Mackerras Cc: Kyle McMartin Cc: Benjamin Herrenschmidt Cc: Martin Schwidefsky Cc: "David S. Miller" Cc: Jeff Dike Cc: Greg KH Cc: Jens Axboe Cc: Paul Fulghum Cc: Alan Cox Cc: Karsten Keil Cc: Mauro Carvalho Chehab Cc: Jeff Garzik Cc: James Bottomley Cc: Ian Kent Cc: Steven French Cc: David Woodhouse Cc: Neil Brown Cc: Jaroslav Kysela Cc: Takashi Iwai Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- arch/mips/kernel/apm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/mips') diff --git a/arch/mips/kernel/apm.c b/arch/mips/kernel/apm.c index 528e731..ba16d07 100644 --- a/arch/mips/kernel/apm.c +++ b/arch/mips/kernel/apm.c @@ -356,7 +356,7 @@ static int apm_open(struct inode * inode, struct file * filp) { struct apm_user *as; - as = (struct apm_user *)kzalloc(sizeof(*as), GFP_KERNEL); + as = kzalloc(sizeof(*as), GFP_KERNEL); if (as) { /* * XXX - this is a tiny bit broken, when we consider BSD -- cgit v1.1 From bcd022801ee514e28c32837f0b3ce18c775f1a7b Mon Sep 17 00:00:00 2001 From: Atsushi Nemoto Date: Tue, 12 Dec 2006 17:14:56 +0000 Subject: [PATCH] MIPS: Fix COW D-cache aliasing on fork Provide a custom copy_user_highpage() to deal with aliasing issues on MIPS. It uses kmap_coherent() to map an user page for kernel with same color. Rewrite copy_to_user_page() and copy_from_user_page() with the new interfaces to avoid extra cache flushing. The main part of this patch was originally written by Ralf Baechle; Atushi Nemoto did the the debugging. Signed-off-by: Atsushi Nemoto Signed-off-by: Ralf Baechle Signed-off-by: Linus Torvalds --- arch/mips/mm/init.c | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) (limited to 'arch/mips') diff --git a/arch/mips/mm/init.c b/arch/mips/mm/init.c index ea2d153..30245c0 100644 --- a/arch/mips/mm/init.c +++ b/arch/mips/mm/init.c @@ -203,6 +203,31 @@ static inline void kunmap_coherent(struct page *page) preempt_check_resched(); } +void copy_user_highpage(struct page *to, struct page *from, + unsigned long vaddr, struct vm_area_struct *vma) +{ + void *vfrom, *vto; + + vto = kmap_atomic(to, KM_USER1); + if (cpu_has_dc_aliases) { + vfrom = kmap_coherent(from, vaddr); + copy_page(vto, vfrom); + kunmap_coherent(from); + } else { + vfrom = kmap_atomic(from, KM_USER0); + copy_page(vto, vfrom); + kunmap_atomic(vfrom, KM_USER0); + } + if (((vma->vm_flags & VM_EXEC) && !cpu_has_ic_fills_f_dc) || + pages_do_alias((unsigned long)vto, vaddr & PAGE_MASK)) + flush_data_cache_page((unsigned long)vto); + kunmap_atomic(vto, KM_USER1); + /* Make sure this page is cleared on other CPU's too before using it */ + smp_wmb(); +} + +EXPORT_SYMBOL(copy_user_highpage); + void copy_to_user_page(struct vm_area_struct *vma, struct page *page, unsigned long vaddr, void *dst, const void *src, unsigned long len) -- cgit v1.1 From 61e84f99877fa8caaf1be86d51d825406e8d8bc1 Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Tue, 12 Dec 2006 11:52:34 +0000 Subject: [MIPS] Malta: Add missing MTD file. Signed-off-by: Ralf Baechle --- arch/mips/mips-boards/malta/malta_mtd.c | 63 +++++++++++++++++++++++++++++++++ 1 file changed, 63 insertions(+) create mode 100644 arch/mips/mips-boards/malta/malta_mtd.c (limited to 'arch/mips') diff --git a/arch/mips/mips-boards/malta/malta_mtd.c b/arch/mips/mips-boards/malta/malta_mtd.c new file mode 100644 index 0000000..8ad9bdf --- /dev/null +++ b/arch/mips/mips-boards/malta/malta_mtd.c @@ -0,0 +1,63 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2006 MIPS Technologies, Inc. + * written by Ralf Baechle + */ + +#include +#include +#include +#include +#include + +static struct mtd_partition malta_mtd_partitions[] = { + { + .name = "YAMON", + .offset = 0x0, + .size = 0x100000, + .mask_flags = MTD_WRITEABLE + }, { + .name = "User FS", + .offset = 0x100000, + .size = 0x2e0000 + }, { + .name = "Board Config", + .offset = 0x3e0000, + .size = 0x020000, + .mask_flags = MTD_WRITEABLE + } +}; + +static struct physmap_flash_data malta_flash_data = { + .width = 4, + .nr_parts = ARRAY_SIZE(malta_mtd_partitions), + .parts = malta_mtd_partitions +}; + +static struct resource malta_flash_resource = { + .start = 0x1e000000, + .end = 0x1e3fffff, + .flags = IORESOURCE_MEM +}; + +static struct platform_device malta_flash = { + .name = "physmap-flash", + .id = 0, + .dev = { + .platform_data = &malta_flash_data, + }, + .num_resources = 1, + .resource = &malta_flash_resource, +}; + +static int __init malta_mtd_init(void) +{ + platform_device_register(&malta_flash); + + return 0; +} + +module_init(malta_mtd_init) -- cgit v1.1 From f860c90bd6ce22c6a0a352cc16acc74fba3d628e Mon Sep 17 00:00:00 2001 From: Atsushi Nemoto Date: Wed, 13 Dec 2006 01:22:06 +0900 Subject: [MIPS] csum_partial and copy in parallel Implement optimized asm version of csum_partial_copy_nocheck, csum_partial_copy_from_user and csum_and_copy_to_user which can do calculate and copy in parallel, based on memcpy.S. Signed-off-by: Atsushi Nemoto Signed-off-by: Ralf Baechle --- arch/mips/kernel/mips_ksyms.c | 2 + arch/mips/lib/Makefile | 2 +- arch/mips/lib/csum_partial.S | 442 ++++++++++++++++++++++++++++++++++++++ arch/mips/lib/csum_partial_copy.c | 52 ----- 4 files changed, 445 insertions(+), 53 deletions(-) delete mode 100644 arch/mips/lib/csum_partial_copy.c (limited to 'arch/mips') diff --git a/arch/mips/kernel/mips_ksyms.c b/arch/mips/kernel/mips_ksyms.c index f44a013..2ef857c 100644 --- a/arch/mips/kernel/mips_ksyms.c +++ b/arch/mips/kernel/mips_ksyms.c @@ -46,5 +46,7 @@ EXPORT_SYMBOL(__strnlen_user_nocheck_asm); EXPORT_SYMBOL(__strnlen_user_asm); EXPORT_SYMBOL(csum_partial); +EXPORT_SYMBOL(csum_partial_copy_nocheck); +EXPORT_SYMBOL(__csum_partial_copy_user); EXPORT_SYMBOL(invalid_pte_table); diff --git a/arch/mips/lib/Makefile b/arch/mips/lib/Makefile index 888b61e..989c900 100644 --- a/arch/mips/lib/Makefile +++ b/arch/mips/lib/Makefile @@ -2,7 +2,7 @@ # Makefile for MIPS-specific library files.. # -lib-y += csum_partial.o csum_partial_copy.o memcpy.o promlib.o \ +lib-y += csum_partial.o memcpy.o promlib.o \ strlen_user.o strncpy_user.o strnlen_user.o uncached.o obj-y += iomap.o diff --git a/arch/mips/lib/csum_partial.S b/arch/mips/lib/csum_partial.S index 9db3572..c0a77fe 100644 --- a/arch/mips/lib/csum_partial.S +++ b/arch/mips/lib/csum_partial.S @@ -8,7 +8,9 @@ * Copyright (C) 1998, 1999 Ralf Baechle * Copyright (C) 1999 Silicon Graphics, Inc. */ +#include #include +#include #include #ifdef CONFIG_64BIT @@ -271,3 +273,443 @@ small_csumcpy: jr ra .set noreorder END(csum_partial) + + +/* + * checksum and copy routines based on memcpy.S + * + * csum_partial_copy_nocheck(src, dst, len, sum) + * __csum_partial_copy_user(src, dst, len, sum, errp) + * + * See "Spec" in memcpy.S for details. Unlike __copy_user, all + * function in this file use the standard calling convention. + */ + +#define src a0 +#define dst a1 +#define len a2 +#define psum a3 +#define sum v0 +#define odd t8 +#define errptr t9 + +/* + * The exception handler for loads requires that: + * 1- AT contain the address of the byte just past the end of the source + * of the copy, + * 2- src_entry <= src < AT, and + * 3- (dst - src) == (dst_entry - src_entry), + * The _entry suffix denotes values when __copy_user was called. + * + * (1) is set up up by __csum_partial_copy_from_user and maintained by + * not writing AT in __csum_partial_copy + * (2) is met by incrementing src by the number of bytes copied + * (3) is met by not doing loads between a pair of increments of dst and src + * + * The exception handlers for stores stores -EFAULT to errptr and return. + * These handlers do not need to overwrite any data. + */ + +#define EXC(inst_reg,addr,handler) \ +9: inst_reg, addr; \ + .section __ex_table,"a"; \ + PTR 9b, handler; \ + .previous + +#ifdef USE_DOUBLE + +#define LOAD ld +#define LOADL ldl +#define LOADR ldr +#define STOREL sdl +#define STORER sdr +#define STORE sd +#define ADD daddu +#define SUB dsubu +#define SRL dsrl +#define SLL dsll +#define SLLV dsllv +#define SRLV dsrlv +#define NBYTES 8 +#define LOG_NBYTES 3 + +#else + +#define LOAD lw +#define LOADL lwl +#define LOADR lwr +#define STOREL swl +#define STORER swr +#define STORE sw +#define ADD addu +#define SUB subu +#define SRL srl +#define SLL sll +#define SLLV sllv +#define SRLV srlv +#define NBYTES 4 +#define LOG_NBYTES 2 + +#endif /* USE_DOUBLE */ + +#ifdef CONFIG_CPU_LITTLE_ENDIAN +#define LDFIRST LOADR +#define LDREST LOADL +#define STFIRST STORER +#define STREST STOREL +#define SHIFT_DISCARD SLLV +#define SHIFT_DISCARD_REVERT SRLV +#else +#define LDFIRST LOADL +#define LDREST LOADR +#define STFIRST STOREL +#define STREST STORER +#define SHIFT_DISCARD SRLV +#define SHIFT_DISCARD_REVERT SLLV +#endif + +#define FIRST(unit) ((unit)*NBYTES) +#define REST(unit) (FIRST(unit)+NBYTES-1) + +#define ADDRMASK (NBYTES-1) + + .set noat + +LEAF(__csum_partial_copy_user) + PTR_ADDU AT, src, len /* See (1) above. */ +#ifdef CONFIG_64BIT + move errptr, a4 +#else + lw errptr, 16(sp) +#endif +FEXPORT(csum_partial_copy_nocheck) + move sum, zero + move odd, zero + /* + * Note: dst & src may be unaligned, len may be 0 + * Temps + */ + /* + * The "issue break"s below are very approximate. + * Issue delays for dcache fills will perturb the schedule, as will + * load queue full replay traps, etc. + * + * If len < NBYTES use byte operations. + */ + sltu t2, len, NBYTES + and t1, dst, ADDRMASK + bnez t2, copy_bytes_checklen + and t0, src, ADDRMASK + andi odd, dst, 0x1 /* odd buffer? */ + bnez t1, dst_unaligned + nop + bnez t0, src_unaligned_dst_aligned + /* + * use delay slot for fall-through + * src and dst are aligned; need to compute rem + */ +both_aligned: + SRL t0, len, LOG_NBYTES+3 # +3 for 8 units/iter + beqz t0, cleanup_both_aligned # len < 8*NBYTES + nop + SUB len, 8*NBYTES # subtract here for bgez loop + .align 4 +1: +EXC( LOAD t0, UNIT(0)(src), l_exc) +EXC( LOAD t1, UNIT(1)(src), l_exc_copy) +EXC( LOAD t2, UNIT(2)(src), l_exc_copy) +EXC( LOAD t3, UNIT(3)(src), l_exc_copy) +EXC( LOAD t4, UNIT(4)(src), l_exc_copy) +EXC( LOAD t5, UNIT(5)(src), l_exc_copy) +EXC( LOAD t6, UNIT(6)(src), l_exc_copy) +EXC( LOAD t7, UNIT(7)(src), l_exc_copy) + SUB len, len, 8*NBYTES + ADD src, src, 8*NBYTES +EXC( STORE t0, UNIT(0)(dst), s_exc) + ADDC(sum, t0) +EXC( STORE t1, UNIT(1)(dst), s_exc) + ADDC(sum, t1) +EXC( STORE t2, UNIT(2)(dst), s_exc) + ADDC(sum, t2) +EXC( STORE t3, UNIT(3)(dst), s_exc) + ADDC(sum, t3) +EXC( STORE t4, UNIT(4)(dst), s_exc) + ADDC(sum, t4) +EXC( STORE t5, UNIT(5)(dst), s_exc) + ADDC(sum, t5) +EXC( STORE t6, UNIT(6)(dst), s_exc) + ADDC(sum, t6) +EXC( STORE t7, UNIT(7)(dst), s_exc) + ADDC(sum, t7) + bgez len, 1b + ADD dst, dst, 8*NBYTES + ADD len, 8*NBYTES # revert len (see above) + + /* + * len == the number of bytes left to copy < 8*NBYTES + */ +cleanup_both_aligned: +#define rem t7 + beqz len, done + sltu t0, len, 4*NBYTES + bnez t0, less_than_4units + and rem, len, (NBYTES-1) # rem = len % NBYTES + /* + * len >= 4*NBYTES + */ +EXC( LOAD t0, UNIT(0)(src), l_exc) +EXC( LOAD t1, UNIT(1)(src), l_exc_copy) +EXC( LOAD t2, UNIT(2)(src), l_exc_copy) +EXC( LOAD t3, UNIT(3)(src), l_exc_copy) + SUB len, len, 4*NBYTES + ADD src, src, 4*NBYTES +EXC( STORE t0, UNIT(0)(dst), s_exc) + ADDC(sum, t0) +EXC( STORE t1, UNIT(1)(dst), s_exc) + ADDC(sum, t1) +EXC( STORE t2, UNIT(2)(dst), s_exc) + ADDC(sum, t2) +EXC( STORE t3, UNIT(3)(dst), s_exc) + ADDC(sum, t3) + beqz len, done + ADD dst, dst, 4*NBYTES +less_than_4units: + /* + * rem = len % NBYTES + */ + beq rem, len, copy_bytes + nop +1: +EXC( LOAD t0, 0(src), l_exc) + ADD src, src, NBYTES + SUB len, len, NBYTES +EXC( STORE t0, 0(dst), s_exc) + ADDC(sum, t0) + bne rem, len, 1b + ADD dst, dst, NBYTES + + /* + * src and dst are aligned, need to copy rem bytes (rem < NBYTES) + * A loop would do only a byte at a time with possible branch + * mispredicts. Can't do an explicit LOAD dst,mask,or,STORE + * because can't assume read-access to dst. Instead, use + * STREST dst, which doesn't require read access to dst. + * + * This code should perform better than a simple loop on modern, + * wide-issue mips processors because the code has fewer branches and + * more instruction-level parallelism. + */ +#define bits t2 + beqz len, done + ADD t1, dst, len # t1 is just past last byte of dst + li bits, 8*NBYTES + SLL rem, len, 3 # rem = number of bits to keep +EXC( LOAD t0, 0(src), l_exc) + SUB bits, bits, rem # bits = number of bits to discard + SHIFT_DISCARD t0, t0, bits +EXC( STREST t0, -1(t1), s_exc) + SHIFT_DISCARD_REVERT t0, t0, bits + .set reorder + ADDC(sum, t0) + b done + .set noreorder +dst_unaligned: + /* + * dst is unaligned + * t0 = src & ADDRMASK + * t1 = dst & ADDRMASK; T1 > 0 + * len >= NBYTES + * + * Copy enough bytes to align dst + * Set match = (src and dst have same alignment) + */ +#define match rem +EXC( LDFIRST t3, FIRST(0)(src), l_exc) + ADD t2, zero, NBYTES +EXC( LDREST t3, REST(0)(src), l_exc_copy) + SUB t2, t2, t1 # t2 = number of bytes copied + xor match, t0, t1 +EXC( STFIRST t3, FIRST(0)(dst), s_exc) + SLL t4, t1, 3 # t4 = number of bits to discard + SHIFT_DISCARD t3, t3, t4 + /* no SHIFT_DISCARD_REVERT to handle odd buffer properly */ + ADDC(sum, t3) + beq len, t2, done + SUB len, len, t2 + ADD dst, dst, t2 + beqz match, both_aligned + ADD src, src, t2 + +src_unaligned_dst_aligned: + SRL t0, len, LOG_NBYTES+2 # +2 for 4 units/iter + beqz t0, cleanup_src_unaligned + and rem, len, (4*NBYTES-1) # rem = len % 4*NBYTES +1: +/* + * Avoid consecutive LD*'s to the same register since some mips + * implementations can't issue them in the same cycle. + * It's OK to load FIRST(N+1) before REST(N) because the two addresses + * are to the same unit (unless src is aligned, but it's not). + */ +EXC( LDFIRST t0, FIRST(0)(src), l_exc) +EXC( LDFIRST t1, FIRST(1)(src), l_exc_copy) + SUB len, len, 4*NBYTES +EXC( LDREST t0, REST(0)(src), l_exc_copy) +EXC( LDREST t1, REST(1)(src), l_exc_copy) +EXC( LDFIRST t2, FIRST(2)(src), l_exc_copy) +EXC( LDFIRST t3, FIRST(3)(src), l_exc_copy) +EXC( LDREST t2, REST(2)(src), l_exc_copy) +EXC( LDREST t3, REST(3)(src), l_exc_copy) + ADD src, src, 4*NBYTES +#ifdef CONFIG_CPU_SB1 + nop # improves slotting +#endif +EXC( STORE t0, UNIT(0)(dst), s_exc) + ADDC(sum, t0) +EXC( STORE t1, UNIT(1)(dst), s_exc) + ADDC(sum, t1) +EXC( STORE t2, UNIT(2)(dst), s_exc) + ADDC(sum, t2) +EXC( STORE t3, UNIT(3)(dst), s_exc) + ADDC(sum, t3) + bne len, rem, 1b + ADD dst, dst, 4*NBYTES + +cleanup_src_unaligned: + beqz len, done + and rem, len, NBYTES-1 # rem = len % NBYTES + beq rem, len, copy_bytes + nop +1: +EXC( LDFIRST t0, FIRST(0)(src), l_exc) +EXC( LDREST t0, REST(0)(src), l_exc_copy) + ADD src, src, NBYTES + SUB len, len, NBYTES +EXC( STORE t0, 0(dst), s_exc) + ADDC(sum, t0) + bne len, rem, 1b + ADD dst, dst, NBYTES + +copy_bytes_checklen: + beqz len, done + nop +copy_bytes: + /* 0 < len < NBYTES */ +#ifdef CONFIG_CPU_LITTLE_ENDIAN +#define SHIFT_START 0 +#define SHIFT_INC 8 +#else +#define SHIFT_START 8*(NBYTES-1) +#define SHIFT_INC -8 +#endif + move t2, zero # partial word + li t3, SHIFT_START # shift +/* use l_exc_copy here to return correct sum on fault */ +#define COPY_BYTE(N) \ +EXC( lbu t0, N(src), l_exc_copy); \ + SUB len, len, 1; \ +EXC( sb t0, N(dst), s_exc); \ + SLLV t0, t0, t3; \ + addu t3, SHIFT_INC; \ + beqz len, copy_bytes_done; \ + or t2, t0 + + COPY_BYTE(0) + COPY_BYTE(1) +#ifdef USE_DOUBLE + COPY_BYTE(2) + COPY_BYTE(3) + COPY_BYTE(4) + COPY_BYTE(5) +#endif +EXC( lbu t0, NBYTES-2(src), l_exc_copy) + SUB len, len, 1 +EXC( sb t0, NBYTES-2(dst), s_exc) + SLLV t0, t0, t3 + or t2, t0 +copy_bytes_done: + ADDC(sum, t2) +done: + /* fold checksum */ +#ifdef USE_DOUBLE + dsll32 v1, sum, 0 + daddu sum, v1 + sltu v1, sum, v1 + dsra32 sum, sum, 0 + addu sum, v1 +#endif + sll v1, sum, 16 + addu sum, v1 + sltu v1, sum, v1 + srl sum, sum, 16 + addu sum, v1 + + /* odd buffer alignment? */ + beqz odd, 1f + nop + sll v1, sum, 8 + srl sum, sum, 8 + or sum, v1 + andi sum, 0xffff +1: + .set reorder + ADDC(sum, psum) + jr ra + .set noreorder + +l_exc_copy: + /* + * Copy bytes from src until faulting load address (or until a + * lb faults) + * + * When reached by a faulting LDFIRST/LDREST, THREAD_BUADDR($28) + * may be more than a byte beyond the last address. + * Hence, the lb below may get an exception. + * + * Assumes src < THREAD_BUADDR($28) + */ + LOAD t0, TI_TASK($28) + li t2, SHIFT_START + LOAD t0, THREAD_BUADDR(t0) +1: +EXC( lbu t1, 0(src), l_exc) + ADD src, src, 1 + sb t1, 0(dst) # can't fault -- we're copy_from_user + SLLV t1, t1, t2 + addu t2, SHIFT_INC + ADDC(sum, t1) + bne src, t0, 1b + ADD dst, dst, 1 +l_exc: + LOAD t0, TI_TASK($28) + nop + LOAD t0, THREAD_BUADDR(t0) # t0 is just past last good address + nop + SUB len, AT, t0 # len number of uncopied bytes + /* + * Here's where we rely on src and dst being incremented in tandem, + * See (3) above. + * dst += (fault addr - src) to put dst at first byte to clear + */ + ADD dst, t0 # compute start address in a1 + SUB dst, src + /* + * Clear len bytes starting at dst. Can't call __bzero because it + * might modify len. An inefficient loop for these rare times... + */ + beqz len, done + SUB src, len, 1 +1: sb zero, 0(dst) + ADD dst, dst, 1 + bnez src, 1b + SUB src, src, 1 + li v1, -EFAULT + b done + sw v1, (errptr) + +s_exc: + li v0, -1 /* invalid checksum */ + li v1, -EFAULT + jr ra + sw v1, (errptr) + END(__csum_partial_copy_user) diff --git a/arch/mips/lib/csum_partial_copy.c b/arch/mips/lib/csum_partial_copy.c deleted file mode 100644 index 0677104..0000000 --- a/arch/mips/lib/csum_partial_copy.c +++ /dev/null @@ -1,52 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1994, 1995 Waldorf Electronics GmbH - * Copyright (C) 1998, 1999 Ralf Baechle - */ -#include -#include -#include -#include -#include -#include -#include - -/* - * copy while checksumming, otherwise like csum_partial - */ -__wsum csum_partial_copy_nocheck(const void *src, - void *dst, int len, __wsum sum) -{ - /* - * It's 2:30 am and I don't feel like doing it real ... - * This is lots slower than the real thing (tm) - */ - sum = csum_partial(src, len, sum); - memcpy(dst, src, len); - - return sum; -} - -EXPORT_SYMBOL(csum_partial_copy_nocheck); - -/* - * Copy from userspace and compute checksum. If we catch an exception - * then zero the rest of the buffer. - */ -__wsum csum_partial_copy_from_user (const void __user *src, - void *dst, int len, __wsum sum, int *err_ptr) -{ - int missing; - - might_sleep(); - missing = copy_from_user(dst, src, len); - if (missing) { - memset(dst + len - missing, 0, missing); - *err_ptr = -EFAULT; - } - - return csum_partial(dst, len, sum); -} -- cgit v1.1 From f75f369fd783d194cb45632617561ca4d7045849 Mon Sep 17 00:00:00 2001 From: Atsushi Nemoto Date: Mon, 8 Jan 2007 01:27:40 +0900 Subject: [MIPS] Fix build errors on SEAD Quick and dirty fix for build errors on SEAD. Signed-off-by: Atsushi Nemoto Signed-off-by: Ralf Baechle --- arch/mips/mips-boards/generic/time.c | 9 +++++++-- arch/mips/mips-boards/sead/sead_int.c | 4 ++-- 2 files changed, 9 insertions(+), 4 deletions(-) (limited to 'arch/mips') diff --git a/arch/mips/mips-boards/generic/time.c b/arch/mips/mips-boards/generic/time.c index e4604c7..a3c3a1d 100644 --- a/arch/mips/mips-boards/generic/time.c +++ b/arch/mips/mips-boards/generic/time.c @@ -47,6 +47,9 @@ #ifdef CONFIG_MIPS_MALTA #include #endif +#ifdef CONFIG_MIPS_SEAD +#include +#endif unsigned long cpu_khz; @@ -263,11 +266,13 @@ void __init mips_time_init(void) void __init plat_timer_setup(struct irqaction *irq) { +#ifdef MSC01E_INT_BASE if (cpu_has_veic) { set_vi_handler (MSC01E_INT_CPUCTR, mips_timer_dispatch); mips_cpu_timer_irq = MSC01E_INT_BASE + MSC01E_INT_CPUCTR; - } - else { + } else +#endif + { if (cpu_has_vint) set_vi_handler (MIPSCPU_INT_CPUCTR, mips_timer_dispatch); mips_cpu_timer_irq = MIPSCPU_INT_BASE + MIPSCPU_INT_CPUCTR; diff --git a/arch/mips/mips-boards/sead/sead_int.c b/arch/mips/mips-boards/sead/sead_int.c index f445fcd..874ccb0 100644 --- a/arch/mips/mips-boards/sead/sead_int.c +++ b/arch/mips/mips-boards/sead/sead_int.c @@ -21,7 +21,7 @@ * Sead board. */ #include -#include +#include #include #include @@ -108,7 +108,7 @@ asmlinkage void plat_irq_dispatch(void) if (irq >= 0) do_IRQ(MIPSCPU_INT_BASE + irq); else - spurious_interrupt(regs); + spurious_interrupt(); } void __init arch_init_irq(void) -- cgit v1.1 From d98f92371461c5c8cc24e12a212c59b3f437b581 Mon Sep 17 00:00:00 2001 From: Davy Chan Date: Fri, 5 Jan 2007 13:56:46 +0800 Subject: [MIPS] pnx8550: Fix write_config_byte() PCI config space accessor There's a serious typo in the function: arch/mips/pci/ops-pnx8550.c:write_config_byte() The parameter passed to the function config_access() is PCI_CMD_CONFIG_READ instead of PCI_CMD_CONFIG_WRITE. This renders any attempts to write a single byte to the PCI configuration registers useless. This problem does not exist for write_config_word() nor write_config_dword(). This problem has been there since kernel v2.6.17 and is still there as of kernel v2.6.19.1. Signed-off-by: Ralf Baechle --- arch/mips/pci/ops-pnx8550.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/mips') diff --git a/arch/mips/pci/ops-pnx8550.c b/arch/mips/pci/ops-pnx8550.c index 454b65c..f556b7a 100644 --- a/arch/mips/pci/ops-pnx8550.c +++ b/arch/mips/pci/ops-pnx8550.c @@ -202,7 +202,7 @@ write_config_byte(struct pci_bus *bus, unsigned int devfn, int where, u8 val) break; } - err = config_access(PCI_CMD_CONFIG_READ, bus, devfn, where, ~(1 << (where & 3)), &data); + err = config_access(PCI_CMD_CONFIG_WRITE, bus, devfn, where, ~(1 << (where & 3)), &data); return err; } -- cgit v1.1 From 33b06b513e804ae64ebd5105fb703ec90bd7e173 Mon Sep 17 00:00:00 2001 From: Atsushi Nemoto Date: Mon, 18 Dec 2006 00:38:21 +0900 Subject: [MIPS] TX49: Fix use of CDEX build_store_reg() The commit a923660d786a53e78834b19062f7af2535f7f8ad accidently prevents TX49 from using CDEX. Use build_dst_pref() only if prefetch for store was really available. Signed-off-by: Atsushi Nemoto Signed-off-by: Ralf Baechle --- arch/mips/mm/pg-r4k.c | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) (limited to 'arch/mips') diff --git a/arch/mips/mm/pg-r4k.c b/arch/mips/mm/pg-r4k.c index d41fc58..dc795be 100644 --- a/arch/mips/mm/pg-r4k.c +++ b/arch/mips/mm/pg-r4k.c @@ -243,11 +243,10 @@ static void __init __build_store_reg(int reg) static inline void build_store_reg(int reg) { - if (cpu_has_prefetch) - if (reg) - build_dst_pref(pref_offset_copy); - else - build_dst_pref(pref_offset_clear); + int pref_off = cpu_has_prefetch ? + (reg ? pref_offset_copy : pref_offset_clear) : 0; + if (pref_off) + build_dst_pref(pref_off); else if (cpu_has_cache_cdex_s) build_cdex_s(); else if (cpu_has_cache_cdex_p) -- cgit v1.1 From 2dbda7dceca81adfe57c8884be5c66e70822d89a Mon Sep 17 00:00:00 2001 From: Vitaly Wool Date: Thu, 28 Dec 2006 17:14:05 +0300 Subject: [MIPS] PNX8550: Fix system timer support the patch inlined below restores proper time accounting for PNX8550-based boards. It also gets rid of #ifdef in the generic code which becomes unnecessary then. It's functionally identical to the previous patch with the same name but it has minor comments from Atsushi and Sergei taken into account. Signed-off-by: Vitaly Wool Signed-off-by: Ralf Baechle --- arch/mips/kernel/time.c | 2 -- arch/mips/philips/pnx8550/common/time.c | 44 +++++++++++++++++++++++++++------ 2 files changed, 37 insertions(+), 9 deletions(-) (limited to 'arch/mips') diff --git a/arch/mips/kernel/time.c b/arch/mips/kernel/time.c index 11aab6d..8aa544f7 100644 --- a/arch/mips/kernel/time.c +++ b/arch/mips/kernel/time.c @@ -94,10 +94,8 @@ static void c0_timer_ack(void) { unsigned int count; -#ifndef CONFIG_SOC_PNX8550 /* pnx8550 resets to zero */ /* Ack this timer interrupt and set the next one. */ expirelo += cycles_per_jiffy; -#endif write_c0_compare(expirelo); /* Check to see if we have missed any timer interrupts. */ diff --git a/arch/mips/philips/pnx8550/common/time.c b/arch/mips/philips/pnx8550/common/time.c index 65c440e..f80acae 100644 --- a/arch/mips/philips/pnx8550/common/time.c +++ b/arch/mips/philips/pnx8550/common/time.c @@ -33,7 +33,17 @@ #include #include -extern unsigned int mips_hpt_frequency; +static unsigned long cpj; + +static cycle_t hpt_read(void) +{ + return read_c0_count2(); +} + +static void timer_ack(void) +{ + write_c0_compare(cpj); +} /* * pnx8550_time_init() - it does the following things: @@ -68,27 +78,47 @@ void pnx8550_time_init(void) * HZ timer interrupts per second. */ mips_hpt_frequency = 27UL * ((1000000UL * n)/(m * pow2p)); + cpj = (mips_hpt_frequency + HZ / 2) / HZ; + timer_ack(); + + /* Setup Timer 2 */ + write_c0_count2(0); + write_c0_compare2(0xffffffff); + + clocksource_mips.read = hpt_read; + mips_timer_ack = timer_ack; +} + +static irqreturn_t monotonic_interrupt(int irq, void *dev_id) +{ + /* Timer 2 clear interrupt */ + write_c0_compare2(-1); + return IRQ_HANDLED; } +static struct irqaction monotonic_irqaction = { + .handler = monotonic_interrupt, + .flags = IRQF_DISABLED, + .name = "Monotonic timer", +}; + void __init plat_timer_setup(struct irqaction *irq) { int configPR; setup_irq(PNX8550_INT_TIMER1, irq); + setup_irq(PNX8550_INT_TIMER2, &monotonic_irqaction); - /* Start timer1 */ + /* Timer 1 start */ configPR = read_c0_config7(); configPR &= ~0x00000008; write_c0_config7(configPR); - /* Timer 2 stop */ + /* Timer 2 start */ configPR = read_c0_config7(); - configPR |= 0x00000010; + configPR &= ~0x00000010; write_c0_config7(configPR); - write_c0_count2(0); - write_c0_compare2(0xffffffff); - /* Timer 3 stop */ configPR = read_c0_config7(); configPR |= 0x00000020; -- cgit v1.1 From 6b4cd2755039a0be642699e3fc2e3386daa88151 Mon Sep 17 00:00:00 2001 From: Atsushi Nemoto Date: Tue, 9 Jan 2007 10:23:00 +0900 Subject: [MIPS] PNX8550: Fix system timer initialization Signed-off-by: Atsushi Nemoto Signed-off-by: Ralf Baechle --- arch/mips/philips/pnx8550/common/time.c | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/mips') diff --git a/arch/mips/philips/pnx8550/common/time.c b/arch/mips/philips/pnx8550/common/time.c index f80acae..68def38 100644 --- a/arch/mips/philips/pnx8550/common/time.c +++ b/arch/mips/philips/pnx8550/common/time.c @@ -79,6 +79,7 @@ void pnx8550_time_init(void) */ mips_hpt_frequency = 27UL * ((1000000UL * n)/(m * pow2p)); cpj = (mips_hpt_frequency + HZ / 2) / HZ; + write_c0_count(0); timer_ack(); /* Setup Timer 2 */ -- cgit v1.1 From e16d8df0be26c8e82c4a1188af8143f2d466b12a Mon Sep 17 00:00:00 2001 From: Atsushi Nemoto Date: Wed, 10 Jan 2007 18:53:33 +0900 Subject: [MIPS] Fix N32 SysV IPC routines Add wrappers for N32 msg{snd,rcv}. compat_sys_msg{snd,rcv} can not not be used as system call entries as is. This fix is based on Kaz Kylheku's patch. Also change a type of last argument of sysn32_semctl to match its true size. Signed-off-by: Atsushi Nemoto Signed-off-by: Ralf Baechle --- arch/mips/kernel/linux32.c | 16 ++++++++++++++-- arch/mips/kernel/scall64-n32.S | 4 ++-- 2 files changed, 16 insertions(+), 4 deletions(-) (limited to 'arch/mips') diff --git a/arch/mips/kernel/linux32.c b/arch/mips/kernel/linux32.c index b061c9a..de3fae2 100644 --- a/arch/mips/kernel/linux32.c +++ b/arch/mips/kernel/linux32.c @@ -440,14 +440,26 @@ sys32_ipc (u32 call, int first, int second, int third, u32 ptr, u32 fifth) } #ifdef CONFIG_MIPS32_N32 -asmlinkage long sysn32_semctl(int semid, int semnum, int cmd, union semun arg) +asmlinkage long sysn32_semctl(int semid, int semnum, int cmd, u32 arg) { /* compat_sys_semctl expects a pointer to union semun */ u32 __user *uptr = compat_alloc_user_space(sizeof(u32)); - if (put_user(ptr_to_compat(arg.__pad), uptr)) + if (put_user(arg, uptr)) return -EFAULT; return compat_sys_semctl(semid, semnum, cmd, uptr); } + +asmlinkage long sysn32_msgsnd(int msqid, u32 msgp, unsigned msgsz, int msgflg) +{ + return compat_sys_msgsnd(msqid, msgsz, msgflg, compat_ptr(msgp)); +} + +asmlinkage long sysn32_msgrcv(int msqid, u32 msgp, size_t msgsz, int msgtyp, + int msgflg) +{ + return compat_sys_msgrcv(msqid, msgsz, msgtyp, msgflg, IPC_64, + compat_ptr(msgp)); +} #endif struct sysctl_args32 diff --git a/arch/mips/kernel/scall64-n32.S b/arch/mips/kernel/scall64-n32.S index 34567d8..a7bff2a 100644 --- a/arch/mips/kernel/scall64-n32.S +++ b/arch/mips/kernel/scall64-n32.S @@ -187,8 +187,8 @@ EXPORT(sysn32_call_table) PTR sysn32_semctl PTR sys_shmdt /* 6065 */ PTR sys_msgget - PTR compat_sys_msgsnd - PTR compat_sys_msgrcv + PTR sysn32_msgsnd + PTR sysn32_msgrcv PTR compat_sys_msgctl PTR compat_sys_fcntl /* 6070 */ PTR sys_flock -- cgit v1.1 From 8a93c4968fc177844680987b31d00d1fc3bc02aa Mon Sep 17 00:00:00 2001 From: Alexander Bigga Date: Thu, 21 Dec 2006 11:25:19 +0100 Subject: [MIPS] Alchemy: Fix PCI-memory access The problem was introduced in 2.6.18.3 with the casting of some 36bit-defines (PCI memory) in au1000.h to resource_size_t which may be u32 or u64 depending on the experimental CONFIG_RESOURCES_64BIT. With unset CONFIG_RESOURCES_64BIT, the pci-memory cannot be accessed because the ioremap in arch/mips/au1000/common/pci.c already used the truncated addresses. With set CONFIG_RESOURCES_64BIT, things get even worse, because PCI-scan aborts, due to resource conflict: request_resource() in arch/mips/pci/pci.c fails because the maximum iomem-address is 0xffffffff (32bit) but the pci-memory-start-address is 0x440000000 (36bit). To get pci working again, I propose the following patch: 1. remove the resource_size_t-casting from au1000.h again 2. make the casting in arch/mips/au1000/common/pci.c (it's allowed and necessary here. The 36bit-handling will be done in __fixup_bigphys_addr). With this patch pci works again like in 2.6.18.2, the gcc-compile warnings in pci.c are gone and it doesn't depend on CONFIG_EXPERIMENTAL. Signed-off-by: Alexander Bigga Signed-off-by: Ralf Baechle --- --- arch/mips/au1000/common/pci.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'arch/mips') diff --git a/arch/mips/au1000/common/pci.c b/arch/mips/au1000/common/pci.c index da591f6..9f8ce08 100644 --- a/arch/mips/au1000/common/pci.c +++ b/arch/mips/au1000/common/pci.c @@ -39,15 +39,15 @@ /* TBD */ static struct resource pci_io_resource = { - .start = PCI_IO_START, - .end = PCI_IO_END, + .start = (resource_size_t)PCI_IO_START, + .end = (resource_size_t)PCI_IO_END, .name = "PCI IO space", .flags = IORESOURCE_IO }; static struct resource pci_mem_resource = { - .start = PCI_MEM_START, - .end = PCI_MEM_END, + .start = (resource_size_t)PCI_MEM_START, + .end = (resource_size_t)PCI_MEM_END, .name = "PCI memory space", .flags = IORESOURCE_MEM }; -- cgit v1.1 From b282b6f8a8d1cf3e132ce3769d7d1cac81d9dd2d Mon Sep 17 00:00:00 2001 From: Gautham R Shenoy Date: Wed, 10 Jan 2007 23:15:34 -0800 Subject: [PATCH] Change cpu_up and co from __devinit to __cpuinit Compiling the kernel with CONFIG_HOTPLUG = y and CONFIG_HOTPLUG_CPU = n with CONFIG_RELOCATABLE = y generates the following modpost warnings WARNING: vmlinux - Section mismatch: reference to .init.data: from .text between '_cpu_up' (at offset 0xc0141b7d) and 'cpu_up' WARNING: vmlinux - Section mismatch: reference to .init.data: from .text between '_cpu_up' (at offset 0xc0141b9c) and 'cpu_up' WARNING: vmlinux - Section mismatch: reference to .init.text:__cpu_up from .text between '_cpu_up' (at offset 0xc0141bd8) and 'cpu_up' WARNING: vmlinux - Section mismatch: reference to .init.data: from .text between '_cpu_up' (at offset 0xc0141c05) and 'cpu_up' WARNING: vmlinux - Section mismatch: reference to .init.data: from .text between '_cpu_up' (at offset 0xc0141c26) and 'cpu_up' WARNING: vmlinux - Section mismatch: reference to .init.data: from .text between '_cpu_up' (at offset 0xc0141c37) and 'cpu_up' This is because cpu_up, _cpu_up and __cpu_up (in some architectures) are defined as __devinit AND __cpu_up calls some __cpuinit functions. Since __cpuinit would map to __init with this kind of a configuration, we get a .text refering .init.data warning. This patch solves the problem by converting all of __cpu_up, _cpu_up and cpu_up from __devinit to __cpuinit. The approach is justified since the callers of cpu_up are either dependent on CONFIG_HOTPLUG_CPU or are of __init type. Thus when CONFIG_HOTPLUG_CPU=y, all these cpu up functions would land up in .text section, and when CONFIG_HOTPLUG_CPU=n, all these functions would land up in .init section. Tested on a i386 SMP machine running linux-2.6.20-rc3-mm1. Signed-off-by: Gautham R Shenoy Cc: Vivek Goyal Cc: Mikael Starvik Cc: Ralf Baechle Cc: Kyle McMartin Cc: Paul Mackerras Cc: Benjamin Herrenschmidt Cc: "David S. Miller" Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- arch/mips/kernel/smp.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/mips') diff --git a/arch/mips/kernel/smp.c b/arch/mips/kernel/smp.c index f2a8701..0555fc5 100644 --- a/arch/mips/kernel/smp.c +++ b/arch/mips/kernel/smp.c @@ -271,7 +271,7 @@ void __devinit smp_prepare_boot_cpu(void) * and keep control until "cpu_online(cpu)" is set. Note: cpu is * physical, not logical. */ -int __devinit __cpu_up(unsigned int cpu) +int __cpuinit __cpu_up(unsigned int cpu) { struct task_struct *idle; -- cgit v1.1