From 11ed4add992062de988773287c32e43f294968ac Mon Sep 17 00:00:00 2001 From: Andrea Gelmini Date: Sun, 23 May 2010 21:52:11 +0200 Subject: MIPS: PCI: RM9000 checkpatch cleanup arch/mips/pci/ops-titan-ht.c:36: ERROR: "foo * bar" should be "foo *bar" arch/mips/pci/ops-titan-ht.c:68: ERROR: "foo * bar" should be "foo *bar" Signed-off-by: Andrea Gelmini Cc: Tejun Heo Cc: Christoph Lameter Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/1277/ Signed-off-by: Ralf Baechle --- arch/mips/pci/ops-titan-ht.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/mips/pci') diff --git a/arch/mips/pci/ops-titan-ht.c b/arch/mips/pci/ops-titan-ht.c index 749c192..57d54ad 100644 --- a/arch/mips/pci/ops-titan-ht.c +++ b/arch/mips/pci/ops-titan-ht.c @@ -32,7 +32,7 @@ #include static int titan_ht_config_read_dword(struct pci_bus *bus, unsigned int devfn, - int offset, u32 * val) + int offset, u32 *val) { volatile uint32_t address; int busno; @@ -64,7 +64,7 @@ static int titan_ht_config_read_dword(struct pci_bus *bus, unsigned int devfn, } static int titan_ht_config_read(struct pci_bus *bus, unsigned int devfn, - int offset, int size, u32 * val) + int offset, int size, u32 *val) { uint32_t dword; -- cgit v1.1 From a894f14d7ebe9e278b496b1e653ae57f2eff514e Mon Sep 17 00:00:00 2001 From: David Daney Date: Fri, 23 Jul 2010 10:43:45 -0700 Subject: MIPS: Octeon: Move MSI code out of octeon-irq.c. Put all the MSI code in one place (msi-octeon.c). This simplifies octeon-irq.c and gets rid of some ugly #ifdefs Signed-off-by: David Daney To: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/1484/ Signed-off-by: Ralf Baechle --- arch/mips/pci/msi-octeon.c | 90 ++++++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 88 insertions(+), 2 deletions(-) (limited to 'arch/mips/pci') diff --git a/arch/mips/pci/msi-octeon.c b/arch/mips/pci/msi-octeon.c index 03742e6..1e31526 100644 --- a/arch/mips/pci/msi-octeon.c +++ b/arch/mips/pci/msi-octeon.c @@ -249,12 +249,99 @@ static irqreturn_t octeon_msi_interrupt(int cpl, void *dev_id) return IRQ_NONE; } +static DEFINE_RAW_SPINLOCK(octeon_irq_msi_lock); + +static void octeon_irq_msi_ack(unsigned int irq) +{ + if (!octeon_has_feature(OCTEON_FEATURE_PCIE)) { + /* These chips have PCI */ + cvmx_write_csr(CVMX_NPI_NPI_MSI_RCV, + 1ull << (irq - OCTEON_IRQ_MSI_BIT0)); + } else { + /* + * These chips have PCIe. Thankfully the ACK doesn't + * need any locking. + */ + cvmx_write_csr(CVMX_PEXP_NPEI_MSI_RCV0, + 1ull << (irq - OCTEON_IRQ_MSI_BIT0)); + } +} + +static void octeon_irq_msi_eoi(unsigned int irq) +{ + /* Nothing needed */ +} + +static void octeon_irq_msi_enable(unsigned int irq) +{ + if (!octeon_has_feature(OCTEON_FEATURE_PCIE)) { + /* + * Octeon PCI doesn't have the ability to mask/unmask + * MSI interrupts individually. Instead of + * masking/unmasking them in groups of 16, we simple + * assume MSI devices are well behaved. MSI + * interrupts are always enable and the ACK is assumed + * to be enough. + */ + } else { + /* These chips have PCIe. Note that we only support + * the first 64 MSI interrupts. Unfortunately all the + * MSI enables are in the same register. We use + * MSI0's lock to control access to them all. + */ + uint64_t en; + unsigned long flags; + raw_spin_lock_irqsave(&octeon_irq_msi_lock, flags); + en = cvmx_read_csr(CVMX_PEXP_NPEI_MSI_ENB0); + en |= 1ull << (irq - OCTEON_IRQ_MSI_BIT0); + cvmx_write_csr(CVMX_PEXP_NPEI_MSI_ENB0, en); + cvmx_read_csr(CVMX_PEXP_NPEI_MSI_ENB0); + raw_spin_unlock_irqrestore(&octeon_irq_msi_lock, flags); + } +} + +static void octeon_irq_msi_disable(unsigned int irq) +{ + if (!octeon_has_feature(OCTEON_FEATURE_PCIE)) { + /* See comment in enable */ + } else { + /* + * These chips have PCIe. Note that we only support + * the first 64 MSI interrupts. Unfortunately all the + * MSI enables are in the same register. We use + * MSI0's lock to control access to them all. + */ + uint64_t en; + unsigned long flags; + raw_spin_lock_irqsave(&octeon_irq_msi_lock, flags); + en = cvmx_read_csr(CVMX_PEXP_NPEI_MSI_ENB0); + en &= ~(1ull << (irq - OCTEON_IRQ_MSI_BIT0)); + cvmx_write_csr(CVMX_PEXP_NPEI_MSI_ENB0, en); + cvmx_read_csr(CVMX_PEXP_NPEI_MSI_ENB0); + raw_spin_unlock_irqrestore(&octeon_irq_msi_lock, flags); + } +} + +static struct irq_chip octeon_irq_chip_msi = { + .name = "MSI", + .enable = octeon_irq_msi_enable, + .disable = octeon_irq_msi_disable, + .ack = octeon_irq_msi_ack, + .eoi = octeon_irq_msi_eoi, +}; /* * Initializes the MSI interrupt handling code */ -int octeon_msi_initialize(void) +static int __init octeon_msi_initialize(void) { + int irq; + + for (irq = OCTEON_IRQ_MSI_BIT0; irq <= OCTEON_IRQ_MSI_BIT63; irq++) { + set_irq_chip_and_handler(irq, &octeon_irq_chip_msi, + handle_percpu_irq); + } + if (octeon_has_feature(OCTEON_FEATURE_PCIE)) { if (request_irq(OCTEON_IRQ_PCI_MSI0, octeon_msi_interrupt, IRQF_SHARED, @@ -284,5 +371,4 @@ int octeon_msi_initialize(void) } return 0; } - subsys_initcall(octeon_msi_initialize); -- cgit v1.1 From a5decf700be1123c2da6bdab5099bce072c55cc2 Mon Sep 17 00:00:00 2001 From: David Daney Date: Fri, 23 Jul 2010 10:43:48 -0700 Subject: MIPS: Octeon: Get rid of a bunch of MSI IRQ number definitions. MSI IRQ numbers are allocated dynamically, so there is no reason to have all these static definitions. Signed-off-by: David Daney To: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/1487/ Signed-off-by: Ralf Baechle --- arch/mips/pci/msi-octeon.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/mips/pci') diff --git a/arch/mips/pci/msi-octeon.c b/arch/mips/pci/msi-octeon.c index 1e31526..5ce1a6a 100644 --- a/arch/mips/pci/msi-octeon.c +++ b/arch/mips/pci/msi-octeon.c @@ -181,7 +181,7 @@ void arch_teardown_msi_irq(unsigned int irq) int number_irqs; uint64_t bitmask; - if ((irq < OCTEON_IRQ_MSI_BIT0) || (irq > OCTEON_IRQ_MSI_BIT63)) + if ((irq < OCTEON_IRQ_MSI_BIT0) || (irq > OCTEON_IRQ_MSI_LAST)) panic("arch_teardown_msi_irq: Attempted to teardown illegal " "MSI interrupt (%d)", irq); irq -= OCTEON_IRQ_MSI_BIT0; @@ -337,7 +337,7 @@ static int __init octeon_msi_initialize(void) { int irq; - for (irq = OCTEON_IRQ_MSI_BIT0; irq <= OCTEON_IRQ_MSI_BIT63; irq++) { + for (irq = OCTEON_IRQ_MSI_BIT0; irq <= OCTEON_IRQ_MSI_LAST; irq++) { set_irq_chip_and_handler(irq, &octeon_irq_chip_msi, handle_percpu_irq); } -- cgit v1.1 From 7d9eee6e52e817c006666b0efc5068aa219dbecb Mon Sep 17 00:00:00 2001 From: David Daney Date: Fri, 23 Jul 2010 10:43:49 -0700 Subject: MIPS: Octeon: Make MSI use handle_simple_irq(). The use of handle_percpu_irq() is not really what we want for MSI, use handle_simple_irq() instead. This is probably the prototypical case for using handle_simple_irq(), because all the MSIs are dispatched from the root interrupt service routine. Also since the base IRQ is not shared, don't pass IRQF_SHARED. Signed-off-by: David Daney To: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/1488/ Signed-off-by: Ralf Baechle --- arch/mips/pci/msi-octeon.c | 61 ++++++++++++---------------------------------- 1 file changed, 15 insertions(+), 46 deletions(-) (limited to 'arch/mips/pci') diff --git a/arch/mips/pci/msi-octeon.c b/arch/mips/pci/msi-octeon.c index 5ce1a6a..83ceb52 100644 --- a/arch/mips/pci/msi-octeon.c +++ b/arch/mips/pci/msi-octeon.c @@ -228,22 +228,20 @@ static irqreturn_t octeon_msi_interrupt(int cpl, void *dev_id) irq = fls64(msi_bits); if (irq) { irq += OCTEON_IRQ_MSI_BIT0 - 1; + if (octeon_has_feature(OCTEON_FEATURE_PCIE)) { + /* These chips have PCIe */ + cvmx_write_csr(CVMX_PEXP_NPEI_MSI_RCV0, + 1ull << (irq - OCTEON_IRQ_MSI_BIT0)); + } else { + /* These chips have PCI */ + cvmx_write_csr(CVMX_NPI_NPI_MSI_RCV, + 1ull << (irq - OCTEON_IRQ_MSI_BIT0)); + } if (irq_desc[irq].action) { do_IRQ(irq); return IRQ_HANDLED; } else { pr_err("Spurious MSI interrupt %d\n", irq); - if (octeon_has_feature(OCTEON_FEATURE_PCIE)) { - /* These chips have PCIe */ - cvmx_write_csr(CVMX_PEXP_NPEI_MSI_RCV0, - 1ull << (irq - - OCTEON_IRQ_MSI_BIT0)); - } else { - /* These chips have PCI */ - cvmx_write_csr(CVMX_NPI_NPI_MSI_RCV, - 1ull << (irq - - OCTEON_IRQ_MSI_BIT0)); - } } } return IRQ_NONE; @@ -251,27 +249,6 @@ static irqreturn_t octeon_msi_interrupt(int cpl, void *dev_id) static DEFINE_RAW_SPINLOCK(octeon_irq_msi_lock); -static void octeon_irq_msi_ack(unsigned int irq) -{ - if (!octeon_has_feature(OCTEON_FEATURE_PCIE)) { - /* These chips have PCI */ - cvmx_write_csr(CVMX_NPI_NPI_MSI_RCV, - 1ull << (irq - OCTEON_IRQ_MSI_BIT0)); - } else { - /* - * These chips have PCIe. Thankfully the ACK doesn't - * need any locking. - */ - cvmx_write_csr(CVMX_PEXP_NPEI_MSI_RCV0, - 1ull << (irq - OCTEON_IRQ_MSI_BIT0)); - } -} - -static void octeon_irq_msi_eoi(unsigned int irq) -{ - /* Nothing needed */ -} - static void octeon_irq_msi_enable(unsigned int irq) { if (!octeon_has_feature(OCTEON_FEATURE_PCIE)) { @@ -326,8 +303,6 @@ static struct irq_chip octeon_irq_chip_msi = { .name = "MSI", .enable = octeon_irq_msi_enable, .disable = octeon_irq_msi_disable, - .ack = octeon_irq_msi_ack, - .eoi = octeon_irq_msi_eoi, }; /* @@ -338,34 +313,28 @@ static int __init octeon_msi_initialize(void) int irq; for (irq = OCTEON_IRQ_MSI_BIT0; irq <= OCTEON_IRQ_MSI_LAST; irq++) { - set_irq_chip_and_handler(irq, &octeon_irq_chip_msi, - handle_percpu_irq); + set_irq_chip_and_handler(irq, &octeon_irq_chip_msi, handle_simple_irq); } if (octeon_has_feature(OCTEON_FEATURE_PCIE)) { if (request_irq(OCTEON_IRQ_PCI_MSI0, octeon_msi_interrupt, - IRQF_SHARED, - "MSI[0:63]", octeon_msi_interrupt)) + 0, "MSI[0:63]", octeon_msi_interrupt)) panic("request_irq(OCTEON_IRQ_PCI_MSI0) failed"); } else if (octeon_is_pci_host()) { if (request_irq(OCTEON_IRQ_PCI_MSI0, octeon_msi_interrupt, - IRQF_SHARED, - "MSI[0:15]", octeon_msi_interrupt)) + 0, "MSI[0:15]", octeon_msi_interrupt)) panic("request_irq(OCTEON_IRQ_PCI_MSI0) failed"); if (request_irq(OCTEON_IRQ_PCI_MSI1, octeon_msi_interrupt, - IRQF_SHARED, - "MSI[16:31]", octeon_msi_interrupt)) + 0, "MSI[16:31]", octeon_msi_interrupt)) panic("request_irq(OCTEON_IRQ_PCI_MSI1) failed"); if (request_irq(OCTEON_IRQ_PCI_MSI2, octeon_msi_interrupt, - IRQF_SHARED, - "MSI[32:47]", octeon_msi_interrupt)) + 0, "MSI[32:47]", octeon_msi_interrupt)) panic("request_irq(OCTEON_IRQ_PCI_MSI2) failed"); if (request_irq(OCTEON_IRQ_PCI_MSI3, octeon_msi_interrupt, - IRQF_SHARED, - "MSI[48:63]", octeon_msi_interrupt)) + 0, "MSI[48:63]", octeon_msi_interrupt)) panic("request_irq(OCTEON_IRQ_PCI_MSI3) failed"); } -- cgit v1.1 From 1aa2b2782a056b9bb0a19fae5a04624d8dcd8379 Mon Sep 17 00:00:00 2001 From: David Daney Date: Mon, 26 Jul 2010 18:14:15 -0700 Subject: MIPS: Octeon: Support 256 MSI on PCIe Signed-off-by: David Daney To: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/1507/ Signed-off-by: Ralf Baechle --- arch/mips/pci/msi-octeon.c | 294 +++++++++++++++++++++++++++------------------ 1 file changed, 177 insertions(+), 117 deletions(-) (limited to 'arch/mips/pci') diff --git a/arch/mips/pci/msi-octeon.c b/arch/mips/pci/msi-octeon.c index 83ceb52..7c75640 100644 --- a/arch/mips/pci/msi-octeon.c +++ b/arch/mips/pci/msi-octeon.c @@ -3,7 +3,7 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 2005-2009 Cavium Networks + * Copyright (C) 2005-2009, 2010 Cavium Networks */ #include #include @@ -22,7 +22,7 @@ * Each bit in msi_free_irq_bitmask represents a MSI interrupt that is * in use. */ -static uint64_t msi_free_irq_bitmask; +static u64 msi_free_irq_bitmask[4]; /* * Each bit in msi_multiple_irq_bitmask tells that the device using @@ -30,7 +30,7 @@ static uint64_t msi_free_irq_bitmask; * is used so we can disable all of the MSI interrupts when a device * uses multiple. */ -static uint64_t msi_multiple_irq_bitmask; +static u64 msi_multiple_irq_bitmask[4]; /* * This lock controls updates to msi_free_irq_bitmask and @@ -38,6 +38,11 @@ static uint64_t msi_multiple_irq_bitmask; */ static DEFINE_SPINLOCK(msi_free_irq_bitmask_lock); +/* + * Number of MSI IRQs used. This variable is set up in + * the module init time. + */ +static int msi_irq_size; /** * Called when a driver request MSI interrupts instead of the @@ -54,12 +59,13 @@ static DEFINE_SPINLOCK(msi_free_irq_bitmask_lock); int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc) { struct msi_msg msg; - uint16_t control; + u16 control; int configured_private_bits; int request_private_bits; - int irq; + int irq = 0; int irq_step; - uint64_t search_mask; + u64 search_mask; + int index; /* * Read the MSI config to figure out how many IRQs this device @@ -111,29 +117,31 @@ try_only_one: * use. */ spin_lock(&msi_free_irq_bitmask_lock); - for (irq = 0; irq < 64; irq += irq_step) { - if ((msi_free_irq_bitmask & (search_mask << irq)) == 0) { - msi_free_irq_bitmask |= search_mask << irq; - msi_multiple_irq_bitmask |= (search_mask >> 1) << irq; - break; + for (index = 0; index < msi_irq_size/64; index++) { + for (irq = 0; irq < 64; irq += irq_step) { + if ((msi_free_irq_bitmask[index] & (search_mask << irq)) == 0) { + msi_free_irq_bitmask[index] |= search_mask << irq; + msi_multiple_irq_bitmask[index] |= (search_mask >> 1) << irq; + goto msi_irq_allocated; + } } } +msi_irq_allocated: spin_unlock(&msi_free_irq_bitmask_lock); /* Make sure the search for available interrupts didn't fail */ if (irq >= 64) { if (request_private_bits) { - pr_err("arch_setup_msi_irq: Unable to find %d free " - "interrupts, trying just one", + pr_err("arch_setup_msi_irq: Unable to find %d free interrupts, trying just one", 1 << request_private_bits); request_private_bits = 0; goto try_only_one; } else - panic("arch_setup_msi_irq: Unable to find a free MSI " - "interrupt"); + panic("arch_setup_msi_irq: Unable to find a free MSI interrupt"); } /* MSI interrupts start at logical IRQ OCTEON_IRQ_MSI_BIT0 */ + irq += index*64; irq += OCTEON_IRQ_MSI_BIT0; switch (octeon_dma_bar_type) { @@ -179,12 +187,18 @@ try_only_one: void arch_teardown_msi_irq(unsigned int irq) { int number_irqs; - uint64_t bitmask; + u64 bitmask; + int index = 0; + int irq0; - if ((irq < OCTEON_IRQ_MSI_BIT0) || (irq > OCTEON_IRQ_MSI_LAST)) + if ((irq < OCTEON_IRQ_MSI_BIT0) + || (irq > msi_irq_size + OCTEON_IRQ_MSI_BIT0)) panic("arch_teardown_msi_irq: Attempted to teardown illegal " "MSI interrupt (%d)", irq); + irq -= OCTEON_IRQ_MSI_BIT0; + index = irq / 64; + irq0 = irq % 64; /* * Count the number of IRQs we need to free by looking at the @@ -192,151 +206,197 @@ void arch_teardown_msi_irq(unsigned int irq) * IRQ is also owned by this device. */ number_irqs = 0; - while ((irq+number_irqs < 64) && - (msi_multiple_irq_bitmask & (1ull << (irq + number_irqs)))) + while ((irq0 + number_irqs < 64) && + (msi_multiple_irq_bitmask[index] + & (1ull << (irq0 + number_irqs)))) number_irqs++; number_irqs++; /* Mask with one bit for each IRQ */ bitmask = (1 << number_irqs) - 1; /* Shift the mask to the correct bit location */ - bitmask <<= irq; - if ((msi_free_irq_bitmask & bitmask) != bitmask) + bitmask <<= irq0; + if ((msi_free_irq_bitmask[index] & bitmask) != bitmask) panic("arch_teardown_msi_irq: Attempted to teardown MSI " "interrupt (%d) not in use", irq); /* Checks are done, update the in use bitmask */ spin_lock(&msi_free_irq_bitmask_lock); - msi_free_irq_bitmask &= ~bitmask; - msi_multiple_irq_bitmask &= ~bitmask; + msi_free_irq_bitmask[index] &= ~bitmask; + msi_multiple_irq_bitmask[index] &= ~bitmask; spin_unlock(&msi_free_irq_bitmask_lock); } +static DEFINE_RAW_SPINLOCK(octeon_irq_msi_lock); -/* - * Called by the interrupt handling code when an MSI interrupt - * occurs. - */ -static irqreturn_t octeon_msi_interrupt(int cpl, void *dev_id) +static u64 msi_rcv_reg[4]; +static u64 mis_ena_reg[4]; + +static void octeon_irq_msi_enable_pcie(unsigned int irq) { - uint64_t msi_bits; - int irq; + u64 en; + unsigned long flags; + int msi_number = irq - OCTEON_IRQ_MSI_BIT0; + int irq_index = msi_number >> 6; + int irq_bit = msi_number & 0x3f; + + raw_spin_lock_irqsave(&octeon_irq_msi_lock, flags); + en = cvmx_read_csr(mis_ena_reg[irq_index]); + en |= 1ull << irq_bit; + cvmx_write_csr(mis_ena_reg[irq_index], en); + cvmx_read_csr(mis_ena_reg[irq_index]); + raw_spin_unlock_irqrestore(&octeon_irq_msi_lock, flags); +} - if (octeon_dma_bar_type == OCTEON_DMA_BAR_TYPE_PCIE) - msi_bits = cvmx_read_csr(CVMX_PEXP_NPEI_MSI_RCV0); - else - msi_bits = cvmx_read_csr(CVMX_NPI_NPI_MSI_RCV); - irq = fls64(msi_bits); - if (irq) { - irq += OCTEON_IRQ_MSI_BIT0 - 1; - if (octeon_has_feature(OCTEON_FEATURE_PCIE)) { - /* These chips have PCIe */ - cvmx_write_csr(CVMX_PEXP_NPEI_MSI_RCV0, - 1ull << (irq - OCTEON_IRQ_MSI_BIT0)); - } else { - /* These chips have PCI */ - cvmx_write_csr(CVMX_NPI_NPI_MSI_RCV, - 1ull << (irq - OCTEON_IRQ_MSI_BIT0)); - } - if (irq_desc[irq].action) { - do_IRQ(irq); - return IRQ_HANDLED; - } else { - pr_err("Spurious MSI interrupt %d\n", irq); - } - } - return IRQ_NONE; +static void octeon_irq_msi_disable_pcie(unsigned int irq) +{ + u64 en; + unsigned long flags; + int msi_number = irq - OCTEON_IRQ_MSI_BIT0; + int irq_index = msi_number >> 6; + int irq_bit = msi_number & 0x3f; + + raw_spin_lock_irqsave(&octeon_irq_msi_lock, flags); + en = cvmx_read_csr(mis_ena_reg[irq_index]); + en &= ~(1ull << irq_bit); + cvmx_write_csr(mis_ena_reg[irq_index], en); + cvmx_read_csr(mis_ena_reg[irq_index]); + raw_spin_unlock_irqrestore(&octeon_irq_msi_lock, flags); } -static DEFINE_RAW_SPINLOCK(octeon_irq_msi_lock); +static struct irq_chip octeon_irq_chip_msi_pcie = { + .name = "MSI", + .enable = octeon_irq_msi_enable_pcie, + .disable = octeon_irq_msi_disable_pcie, +}; -static void octeon_irq_msi_enable(unsigned int irq) +static void octeon_irq_msi_enable_pci(unsigned int irq) { - if (!octeon_has_feature(OCTEON_FEATURE_PCIE)) { - /* - * Octeon PCI doesn't have the ability to mask/unmask - * MSI interrupts individually. Instead of - * masking/unmasking them in groups of 16, we simple - * assume MSI devices are well behaved. MSI - * interrupts are always enable and the ACK is assumed - * to be enough. - */ - } else { - /* These chips have PCIe. Note that we only support - * the first 64 MSI interrupts. Unfortunately all the - * MSI enables are in the same register. We use - * MSI0's lock to control access to them all. - */ - uint64_t en; - unsigned long flags; - raw_spin_lock_irqsave(&octeon_irq_msi_lock, flags); - en = cvmx_read_csr(CVMX_PEXP_NPEI_MSI_ENB0); - en |= 1ull << (irq - OCTEON_IRQ_MSI_BIT0); - cvmx_write_csr(CVMX_PEXP_NPEI_MSI_ENB0, en); - cvmx_read_csr(CVMX_PEXP_NPEI_MSI_ENB0); - raw_spin_unlock_irqrestore(&octeon_irq_msi_lock, flags); - } + /* + * Octeon PCI doesn't have the ability to mask/unmask MSI + * interrupts individually. Instead of masking/unmasking them + * in groups of 16, we simple assume MSI devices are well + * behaved. MSI interrupts are always enable and the ACK is + * assumed to be enough + */ } -static void octeon_irq_msi_disable(unsigned int irq) +static void octeon_irq_msi_disable_pci(unsigned int irq) { - if (!octeon_has_feature(OCTEON_FEATURE_PCIE)) { - /* See comment in enable */ - } else { - /* - * These chips have PCIe. Note that we only support - * the first 64 MSI interrupts. Unfortunately all the - * MSI enables are in the same register. We use - * MSI0's lock to control access to them all. - */ - uint64_t en; - unsigned long flags; - raw_spin_lock_irqsave(&octeon_irq_msi_lock, flags); - en = cvmx_read_csr(CVMX_PEXP_NPEI_MSI_ENB0); - en &= ~(1ull << (irq - OCTEON_IRQ_MSI_BIT0)); - cvmx_write_csr(CVMX_PEXP_NPEI_MSI_ENB0, en); - cvmx_read_csr(CVMX_PEXP_NPEI_MSI_ENB0); - raw_spin_unlock_irqrestore(&octeon_irq_msi_lock, flags); - } + /* See comment in enable */ } -static struct irq_chip octeon_irq_chip_msi = { +static struct irq_chip octeon_irq_chip_msi_pci = { .name = "MSI", - .enable = octeon_irq_msi_enable, - .disable = octeon_irq_msi_disable, + .enable = octeon_irq_msi_enable_pci, + .disable = octeon_irq_msi_disable_pci, }; /* - * Initializes the MSI interrupt handling code + * Called by the interrupt handling code when an MSI interrupt + * occurs. */ -static int __init octeon_msi_initialize(void) +static irqreturn_t __octeon_msi_do_interrupt(int index, u64 msi_bits) { int irq; + int bit; - for (irq = OCTEON_IRQ_MSI_BIT0; irq <= OCTEON_IRQ_MSI_LAST; irq++) { - set_irq_chip_and_handler(irq, &octeon_irq_chip_msi, handle_simple_irq); + bit = fls64(msi_bits); + if (bit) { + bit--; + /* Acknowledge it first. */ + cvmx_write_csr(msi_rcv_reg[index], 1ull << bit); + + irq = bit + OCTEON_IRQ_MSI_BIT0 + 64 * index; + do_IRQ(irq); + return IRQ_HANDLED; } + return IRQ_NONE; +} + +#define OCTEON_MSI_INT_HANDLER_X(x) \ +static irqreturn_t octeon_msi_interrupt##x(int cpl, void *dev_id) \ +{ \ + u64 msi_bits = cvmx_read_csr(msi_rcv_reg[(x)]); \ + return __octeon_msi_do_interrupt((x), msi_bits); \ +} + +/* + * Create octeon_msi_interrupt{0-3} function body + */ +OCTEON_MSI_INT_HANDLER_X(0); +OCTEON_MSI_INT_HANDLER_X(1); +OCTEON_MSI_INT_HANDLER_X(2); +OCTEON_MSI_INT_HANDLER_X(3); + +/* + * Initializes the MSI interrupt handling code + */ +int __init octeon_msi_initialize(void) +{ + int irq; + struct irq_chip *msi; + + if (octeon_dma_bar_type == OCTEON_DMA_BAR_TYPE_PCIE) { + msi_rcv_reg[0] = CVMX_PEXP_NPEI_MSI_RCV0; + msi_rcv_reg[1] = CVMX_PEXP_NPEI_MSI_RCV1; + msi_rcv_reg[2] = CVMX_PEXP_NPEI_MSI_RCV2; + msi_rcv_reg[3] = CVMX_PEXP_NPEI_MSI_RCV3; + mis_ena_reg[0] = CVMX_PEXP_NPEI_MSI_ENB0; + mis_ena_reg[1] = CVMX_PEXP_NPEI_MSI_ENB1; + mis_ena_reg[2] = CVMX_PEXP_NPEI_MSI_ENB2; + mis_ena_reg[3] = CVMX_PEXP_NPEI_MSI_ENB3; + msi = &octeon_irq_chip_msi_pcie; + } else { + msi_rcv_reg[0] = CVMX_NPI_NPI_MSI_RCV; +#define INVALID_GENERATE_ADE 0x8700000000000000ULL; + msi_rcv_reg[1] = INVALID_GENERATE_ADE; + msi_rcv_reg[2] = INVALID_GENERATE_ADE; + msi_rcv_reg[3] = INVALID_GENERATE_ADE; + mis_ena_reg[0] = INVALID_GENERATE_ADE; + mis_ena_reg[1] = INVALID_GENERATE_ADE; + mis_ena_reg[2] = INVALID_GENERATE_ADE; + mis_ena_reg[3] = INVALID_GENERATE_ADE; + msi = &octeon_irq_chip_msi_pci; + } + + for (irq = OCTEON_IRQ_MSI_BIT0; irq <= OCTEON_IRQ_MSI_LAST; irq++) + set_irq_chip_and_handler(irq, msi, handle_simple_irq); if (octeon_has_feature(OCTEON_FEATURE_PCIE)) { - if (request_irq(OCTEON_IRQ_PCI_MSI0, octeon_msi_interrupt, - 0, "MSI[0:63]", octeon_msi_interrupt)) + if (request_irq(OCTEON_IRQ_PCI_MSI0, octeon_msi_interrupt0, + 0, "MSI[0:63]", octeon_msi_interrupt0)) panic("request_irq(OCTEON_IRQ_PCI_MSI0) failed"); + + if (request_irq(OCTEON_IRQ_PCI_MSI1, octeon_msi_interrupt1, + 0, "MSI[64:127]", octeon_msi_interrupt1)) + panic("request_irq(OCTEON_IRQ_PCI_MSI1) failed"); + + if (request_irq(OCTEON_IRQ_PCI_MSI2, octeon_msi_interrupt2, + 0, "MSI[127:191]", octeon_msi_interrupt2)) + panic("request_irq(OCTEON_IRQ_PCI_MSI2) failed"); + + if (request_irq(OCTEON_IRQ_PCI_MSI3, octeon_msi_interrupt3, + 0, "MSI[192:255]", octeon_msi_interrupt3)) + panic("request_irq(OCTEON_IRQ_PCI_MSI3) failed"); + + msi_irq_size = 256; } else if (octeon_is_pci_host()) { - if (request_irq(OCTEON_IRQ_PCI_MSI0, octeon_msi_interrupt, - 0, "MSI[0:15]", octeon_msi_interrupt)) + if (request_irq(OCTEON_IRQ_PCI_MSI0, octeon_msi_interrupt0, + 0, "MSI[0:15]", octeon_msi_interrupt0)) panic("request_irq(OCTEON_IRQ_PCI_MSI0) failed"); - if (request_irq(OCTEON_IRQ_PCI_MSI1, octeon_msi_interrupt, - 0, "MSI[16:31]", octeon_msi_interrupt)) + if (request_irq(OCTEON_IRQ_PCI_MSI1, octeon_msi_interrupt0, + 0, "MSI[16:31]", octeon_msi_interrupt0)) panic("request_irq(OCTEON_IRQ_PCI_MSI1) failed"); - if (request_irq(OCTEON_IRQ_PCI_MSI2, octeon_msi_interrupt, - 0, "MSI[32:47]", octeon_msi_interrupt)) + if (request_irq(OCTEON_IRQ_PCI_MSI2, octeon_msi_interrupt0, + 0, "MSI[32:47]", octeon_msi_interrupt0)) panic("request_irq(OCTEON_IRQ_PCI_MSI2) failed"); - if (request_irq(OCTEON_IRQ_PCI_MSI3, octeon_msi_interrupt, - 0, "MSI[48:63]", octeon_msi_interrupt)) + if (request_irq(OCTEON_IRQ_PCI_MSI3, octeon_msi_interrupt0, + 0, "MSI[48:63]", octeon_msi_interrupt0)) panic("request_irq(OCTEON_IRQ_PCI_MSI3) failed"); - + msi_irq_size = 64; } return 0; } -- cgit v1.1 From 52a0f00b50ea360e3cf7e3281523c6a8aafc5761 Mon Sep 17 00:00:00 2001 From: Chandrakala Chavva Date: Mon, 26 Jul 2010 18:14:16 -0700 Subject: MIPS: Octeon: Disallow MSI-X interrupt and fall back to MSI interrupts. MSI-X interrupts are not supported yet for Octeon, return error if MSI-X interrupts are requested by driver so that the driver will fall back to use MSI interrupts. Signed-off-by: Chandrakala Chavva To: linux-mips@linux-mips.org Cc: David Daney Patchwork: https://patchwork.linux-mips.org/patch/1506/ Signed-off-by: Ralf Baechle Signed-off-by: David Daney --- arch/mips/pci/msi-octeon.c | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) (limited to 'arch/mips/pci') diff --git a/arch/mips/pci/msi-octeon.c b/arch/mips/pci/msi-octeon.c index 7c75640..d808049 100644 --- a/arch/mips/pci/msi-octeon.c +++ b/arch/mips/pci/msi-octeon.c @@ -177,6 +177,34 @@ msi_irq_allocated: return 0; } +int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type) +{ + struct msi_desc *entry; + int ret; + + /* + * MSI-X is not supported. + */ + if (type == PCI_CAP_ID_MSIX) + return -EINVAL; + + /* + * If an architecture wants to support multiple MSI, it needs to + * override arch_setup_msi_irqs() + */ + if (type == PCI_CAP_ID_MSI && nvec > 1) + return 1; + + list_for_each_entry(entry, &dev->msi_list, list) { + ret = arch_setup_msi_irq(dev, entry); + if (ret < 0) + return ret; + if (ret > 0) + return -ENOSPC; + } + + return 0; +} /** * Called when a device no longer needs its MSI interrupts. All -- cgit v1.1 From 2b5987abaf2dd6c3934e0376b7d9f64411cdcf03 Mon Sep 17 00:00:00 2001 From: David Daney Date: Wed, 4 Aug 2010 14:53:57 -0700 Subject: MIPS: Octeon: Allow more than 3.75GB of memory with PCIe We reserve the 3.75GB - 4GB region of PCIe address space for device to device transfers, making the corresponding physical memory under direct mapping unavailable for DMA. To allow for PCIe DMA to all physical memory we map this chunk of physical memory with BAR1. Because of the resulting discontinuity in the mapping function, we remove a page of memory at each end of the range so multi-page DMA buffers can never be allocated that span the range. Signed-off-by: David Daney To: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/1535/ Signed-off-by: Ralf Baechle --- arch/mips/pci/pcie-octeon.c | 37 +++++++++++++++++++++++++++++++------ 1 file changed, 31 insertions(+), 6 deletions(-) (limited to 'arch/mips/pci') diff --git a/arch/mips/pci/pcie-octeon.c b/arch/mips/pci/pcie-octeon.c index 6aa5c54..861361e 100644 --- a/arch/mips/pci/pcie-octeon.c +++ b/arch/mips/pci/pcie-octeon.c @@ -402,6 +402,10 @@ static void __cvmx_pcie_rc_initialize_config_space(int pcie_port) npei_ctl_status2.s.mps = 0; /* Max read request size = 128 bytes for best Octeon DMA performance */ npei_ctl_status2.s.mrrs = 0; + if (pcie_port) + npei_ctl_status2.s.c1_b1_s = 3; /* Port1 BAR1 Size 256MB */ + else + npei_ctl_status2.s.c0_b1_s = 3; /* Port0 BAR1 Size 256MB */ cvmx_write_csr(CVMX_PEXP_NPEI_CTL_STATUS2, npei_ctl_status2.u64); /* ECRC Generation (PCIE*_CFG070[GE,CE]) */ @@ -666,6 +670,8 @@ static int __cvmx_pcie_rc_initialize_link(int pcie_port) static int cvmx_pcie_rc_initialize(int pcie_port) { int i; + int base; + u64 addr_swizzle; union cvmx_ciu_soft_prst ciu_soft_prst; union cvmx_pescx_bist_status pescx_bist_status; union cvmx_pescx_bist_status2 pescx_bist_status2; @@ -674,6 +680,7 @@ static int cvmx_pcie_rc_initialize(int pcie_port) union cvmx_npei_mem_access_subidx mem_access_subid; union cvmx_npei_dbg_data npei_dbg_data; union cvmx_pescx_ctl_status2 pescx_ctl_status2; + union cvmx_npei_bar1_indexx bar1_index; /* * Make sure we aren't trying to setup a target mode interface @@ -918,12 +925,30 @@ static int cvmx_pcie_rc_initialize(int pcie_port) /* Set Octeon's BAR0 to decode 0-16KB. It overlaps with Bar2 */ cvmx_write_csr(CVMX_PESCX_P2N_BAR0_START(pcie_port), 0); - /* - * Disable Octeon's BAR1. It isn't needed in RC mode since - * BAR2 maps all of memory. BAR2 also maps 256MB-512MB into - * the 2nd 256MB of memory. - */ - cvmx_write_csr(CVMX_PESCX_P2N_BAR1_START(pcie_port), -1); + /* BAR1 follows BAR2 with a gap. */ + cvmx_write_csr(CVMX_PESCX_P2N_BAR1_START(pcie_port), CVMX_PCIE_BAR1_RC_BASE); + + bar1_index.u32 = 0; + bar1_index.s.addr_idx = (CVMX_PCIE_BAR1_PHYS_BASE >> 22); + bar1_index.s.ca = 1; /* Not Cached */ + bar1_index.s.end_swp = 1; /* Endian Swap mode */ + bar1_index.s.addr_v = 1; /* Valid entry */ + + base = pcie_port ? 16 : 0; + + /* Big endian swizzle for 32-bit PEXP_NCB register. */ +#ifdef __MIPSEB__ + addr_swizzle = 4; +#else + addr_swizzle = 0; +#endif + for (i = 0; i < 16; i++) { + cvmx_write64_uint32((CVMX_PEXP_NPEI_BAR1_INDEXX(base) ^ addr_swizzle), + bar1_index.u32); + base++; + /* 256MB / 16 >> 22 == 4 */ + bar1_index.s.addr_idx += (((1ull << 28) / 16ull) >> 22); + } /* * Set Octeon's BAR2 to decode 0-2^39. Bar0 and Bar1 take -- cgit v1.1