From 8393c524a25609a30129e4a8975cf3b91f6c16a5 Mon Sep 17 00:00:00 2001 From: Huacai Chen Date: Tue, 29 Jul 2014 14:54:40 +0800 Subject: MIPS: tlbex: Fix a missing statement for HUGETLB In commit 2c8c53e28f1 (MIPS: Optimize TLB handlers for Octeon CPUs) build_r4000_tlb_refill_handler() is modified. But it doesn't compatible with the original code in HUGETLB case. Because there is a copy & paste error and one line of code is missing. It is very easy to produce a bug with LTP's hugemmap05 test. Signed-off-by: Huacai Chen Signed-off-by: Binbin Zhou Cc: Cc: John Crispin Cc: Steven J. Hill Cc: linux-mips@linux-mips.org Cc: Fuxin Zhang Cc: Zhangjin Wu Patchwork: https://patchwork.linux-mips.org/patch/7496/ Signed-off-by: Ralf Baechle --- arch/mips/mm/tlbex.c | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/mips/mm') diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c index e80e10b..343fe0f 100644 --- a/arch/mips/mm/tlbex.c +++ b/arch/mips/mm/tlbex.c @@ -1299,6 +1299,7 @@ static void build_r4000_tlb_refill_handler(void) } #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT uasm_l_tlb_huge_update(&l, p); + UASM_i_LW(&p, K0, 0, K1); build_huge_update_entries(&p, htlb_info.huge_pte, K1); build_huge_tlb_write_entry(&p, &l, &r, K0, tlb_random, htlb_info.restore_scratch); -- cgit v1.1 From 1062080a7d8dbe08cefce728341285e77930ef49 Mon Sep 17 00:00:00 2001 From: Leonid Yegoshin Date: Fri, 11 Jul 2014 15:18:05 -0700 Subject: MIPS: bugfix: missed cache flush of TLB refill handler Commit Commit 1d40cfcd3442a53e98468cdb3e6d4d9a568d76cf Author: Ralf Baechle Date: Fri Jul 15 15:23:23 2005 +0000 Avoid SMP cacheflushes. This is a minor optimization of startup but will also avoid smp_call_function from doing stupid things when called from a CPU that is not yet marked online. missed an appropriate cache flush of TLB refill handler because that time it was at fixed location CAC_BASE. After years the refill handler in EBASE vector is not at that location and can be allocated in some another memory and needs I-cache sync as other TLB exception vectors. Besides that, the new function - local_flash_icache_range() was introduced to avoid SMP cacheflushes. Signed-off-by: Leonid Yegoshin Cc: linux-mips@linux-mips.org Cc: paul.gortmaker@windriver.com Cc: jchandra@broadcom.com Cc: linux-kernel@vger.kernel.org Cc: david.daney@cavium.com Patchwork: https://patchwork.linux-mips.org/patch/7312/ Signed-off-by: Ralf Baechle --- arch/mips/mm/tlbex.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/mips/mm') diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c index 343fe0f..cf8a952 100644 --- a/arch/mips/mm/tlbex.c +++ b/arch/mips/mm/tlbex.c @@ -429,6 +429,7 @@ static void build_r3000_tlb_refill_handler(void) (unsigned int)(p - tlb_handler)); memcpy((void *)ebase, tlb_handler, 0x80); + local_flush_icache_range(ebase, ebase + 0x80); dump_handler("r3000_tlb_refill", (u32 *)ebase, 32); } @@ -1416,6 +1417,7 @@ static void build_r4000_tlb_refill_handler(void) final_len); memcpy((void *)ebase, final_handler, 0x100); + local_flush_icache_range(ebase, ebase + 0x100); dump_handler("r4000_tlb_refill", (u32 *)ebase, 64); } -- cgit v1.1