From 48ed33c1b3737eb1324c1ae023a8eeccad60cef9 Mon Sep 17 00:00:00 2001 From: Paul Burton Date: Fri, 19 Aug 2016 18:13:36 +0100 Subject: MIPS: sc-mips: L2 cache is inclusive of L1 dcache for CM3 In systems with CM3 & higher, the L2 cache is inclusive of the L1 dcache. Indicate this such that cpu_has_inclusive_pcaches evaluates true and we avoid some unnecessary cache ops during DMA cache maintenance. Signed-off-by: Paul Burton Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/14018/ Signed-off-by: Ralf Baechle --- arch/mips/mm/sc-mips.c | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/mips/mm/sc-mips.c') diff --git a/arch/mips/mm/sc-mips.c b/arch/mips/mm/sc-mips.c index 286a4d5..c909c334 100644 --- a/arch/mips/mm/sc-mips.c +++ b/arch/mips/mm/sc-mips.c @@ -181,6 +181,7 @@ static int __init mips_sc_probe_cm3(void) if (c->scache.linesz) { c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT; + c->options |= MIPS_CPU_INCLUSIVE_CACHES; return 1; } -- cgit v1.1