From 3b1d4ed5353af04d6aa20be2701727b9cdb2ac61 Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Wed, 20 Jun 2007 22:27:10 +0100 Subject: [MIPS] Don't drag a platform specific header into generic arch code. For some platforms it's definitions may conflict. So that's the one-liner. The rest is 10 square kilometers of collateral damage fixup this include used to paper over. Signed-off-by: Ralf Baechle --- arch/mips/mips-boards/atlas/atlas_int.c | 8 +++--- arch/mips/mips-boards/generic/time.c | 50 +++++++++++---------------------- arch/mips/mips-boards/malta/malta_int.c | 14 ++++----- arch/mips/mips-boards/sead/sead_int.c | 2 +- arch/mips/mips-boards/sead/sead_setup.c | 2 +- arch/mips/mips-boards/sim/sim_int.c | 2 +- arch/mips/mips-boards/sim/sim_time.c | 8 +++--- 7 files changed, 34 insertions(+), 52 deletions(-) (limited to 'arch/mips/mips-boards') diff --git a/arch/mips/mips-boards/atlas/atlas_int.c b/arch/mips/mips-boards/atlas/atlas_int.c index 9f49da9..6c8f025 100644 --- a/arch/mips/mips-boards/atlas/atlas_int.c +++ b/arch/mips/mips-boards/atlas/atlas_int.c @@ -189,7 +189,7 @@ asmlinkage void plat_irq_dispatch(void) if (irq == MIPSCPU_INT_ATLAS) atlas_hw0_irqdispatch(); else if (irq >= 0) - do_IRQ(MIPSCPU_INT_BASE + irq); + do_IRQ(MIPS_CPU_IRQ_BASE + irq); else spurious_interrupt(); } @@ -261,11 +261,11 @@ void __init arch_init_irq(void) } else if (cpu_has_vint) { set_vi_handler (MIPSCPU_INT_ATLAS, atlas_hw0_irqdispatch); #ifdef CONFIG_MIPS_MT_SMTC - setup_irq_smtc (MIPSCPU_INT_BASE + MIPSCPU_INT_ATLAS, + setup_irq_smtc (MIPS_CPU_IRQ_BASE + MIPSCPU_INT_ATLAS, &atlasirq, (0x100 << MIPSCPU_INT_ATLAS)); #else /* Not SMTC */ - setup_irq(MIPSCPU_INT_BASE + MIPSCPU_INT_ATLAS, &atlasirq); + setup_irq(MIPS_CPU_IRQ_BASE + MIPSCPU_INT_ATLAS, &atlasirq); #endif /* CONFIG_MIPS_MT_SMTC */ } else - setup_irq(MIPSCPU_INT_BASE + MIPSCPU_INT_ATLAS, &atlasirq); + setup_irq(MIPS_CPU_IRQ_BASE + MIPSCPU_INT_ATLAS, &atlasirq); } diff --git a/arch/mips/mips-boards/generic/time.c b/arch/mips/mips-boards/generic/time.c index 8f1000f..c45d556 100644 --- a/arch/mips/mips-boards/generic/time.c +++ b/arch/mips/mips-boards/generic/time.c @@ -54,7 +54,7 @@ unsigned long cpu_khz; static int mips_cpu_timer_irq; -extern int mipsxx_perfcount_irq; +extern int cp0_perfcount_irq; extern void smtc_timer_broadcast(int); static void mips_timer_dispatch(void) @@ -64,7 +64,7 @@ static void mips_timer_dispatch(void) static void mips_perf_dispatch(void) { - do_IRQ(mipsxx_perfcount_irq); + do_IRQ(cp0_perfcount_irq); } /* @@ -82,12 +82,12 @@ static inline int handle_perf_irq (int r2) { /* * The performance counter overflow interrupt may be shared with the - * timer interrupt (mipsxx_perfcount_irq < 0). If it is and a + * timer interrupt (cp0_perfcount_irq < 0). If it is and a * performance counter has overflowed (perf_irq() == IRQ_HANDLED) * and we can't reliably determine if a counter interrupt has also * happened (!r2) then don't check for a timer interrupt. */ - return (mipsxx_perfcount_irq < 0) && + return (cp0_perfcount_irq < 0) && perf_irq() == IRQ_HANDLED && !r2; } @@ -259,42 +259,31 @@ static struct irqaction perf_irqaction = { void __init plat_perf_setup(struct irqaction *irq) { - int hwint = 0; - mipsxx_perfcount_irq = -1; + cp0_perfcount_irq = -1; #ifdef MSC01E_INT_BASE if (cpu_has_veic) { set_vi_handler (MSC01E_INT_PERFCTR, mips_perf_dispatch); - mipsxx_perfcount_irq = MSC01E_INT_BASE + MSC01E_INT_PERFCTR; + cp0_perfcount_irq = MSC01E_INT_BASE + MSC01E_INT_PERFCTR; } else #endif - if (cpu_has_mips_r2) { - /* - * Read IntCtl.IPPCI to determine the performance - * counter interrupt - */ - hwint = (read_c0_intctl () >> 26) & 7; - if (hwint != MIPSCPU_INT_CPUCTR) { - if (cpu_has_vint) - set_vi_handler (hwint, mips_perf_dispatch); - mipsxx_perfcount_irq = MIPSCPU_INT_BASE + hwint; - } - } - if (mipsxx_perfcount_irq >= 0) { + if (cp0_perfcount_irq >= 0) { + if (cpu_has_vint) + set_vi_handler(cp0_perfcount_irq, mips_perf_dispatch); #ifdef CONFIG_MIPS_MT_SMTC - setup_irq_smtc(mipsxx_perfcount_irq, irq, 0x100 << hwint); + setup_irq_smtc(cp0_perfcount_irq, irq, + 0x100 << cp0_perfcount_irq); #else - setup_irq(mipsxx_perfcount_irq, irq); + setup_irq(cp0_perfcount_irq, irq); #endif /* CONFIG_MIPS_MT_SMTC */ #ifdef CONFIG_SMP - set_irq_handler(mipsxx_perfcount_irq, handle_percpu_irq); + set_irq_handler(cp0_perfcount_irq, handle_percpu_irq); #endif } } void __init plat_timer_setup(struct irqaction *irq) { - int hwint = 0; #ifdef MSC01E_INT_BASE if (cpu_has_veic) { set_vi_handler (MSC01E_INT_CPUCTR, mips_timer_dispatch); @@ -303,22 +292,15 @@ void __init plat_timer_setup(struct irqaction *irq) else #endif { - if (cpu_has_mips_r2) - /* - * Read IntCtl.IPTI to determine the timer interrupt - */ - hwint = (read_c0_intctl () >> 29) & 7; - else - hwint = MIPSCPU_INT_CPUCTR; if (cpu_has_vint) - set_vi_handler (hwint, mips_timer_dispatch); - mips_cpu_timer_irq = MIPSCPU_INT_BASE + hwint; + set_vi_handler(cp0_compare_irq, mips_timer_dispatch); + mips_cpu_timer_irq = MIPS_CPU_IRQ_BASE + cp0_compare_irq; } /* we are using the cpu counter for timer interrupts */ irq->handler = mips_timer_interrupt; /* we use our own handler */ #ifdef CONFIG_MIPS_MT_SMTC - setup_irq_smtc(mips_cpu_timer_irq, irq, 0x100 << hwint); + setup_irq_smtc(mips_cpu_timer_irq, irq, 0x100 << cp0_compare_irq); #else setup_irq(mips_cpu_timer_irq, irq); #endif /* CONFIG_MIPS_MT_SMTC */ diff --git a/arch/mips/mips-boards/malta/malta_int.c b/arch/mips/mips-boards/malta/malta_int.c index 1668cc2..c78d4834 100644 --- a/arch/mips/mips-boards/malta/malta_int.c +++ b/arch/mips/mips-boards/malta/malta_int.c @@ -257,7 +257,7 @@ asmlinkage void plat_irq_dispatch(void) if (irq == MIPSCPU_INT_I8259A) malta_hw0_irqdispatch(); else if (irq > 0) - do_IRQ(MIPSCPU_INT_BASE + irq); + do_IRQ(MIPS_CPU_IRQ_BASE + irq); else spurious_interrupt(); } @@ -326,17 +326,17 @@ void __init arch_init_irq(void) set_vi_handler (MIPSCPU_INT_I8259A, malta_hw0_irqdispatch); set_vi_handler (MIPSCPU_INT_COREHI, corehi_irqdispatch); #ifdef CONFIG_MIPS_MT_SMTC - setup_irq_smtc (MIPSCPU_INT_BASE+MIPSCPU_INT_I8259A, &i8259irq, + setup_irq_smtc (MIPS_CPU_IRQ_BASE+MIPSCPU_INT_I8259A, &i8259irq, (0x100 << MIPSCPU_INT_I8259A)); - setup_irq_smtc (MIPSCPU_INT_BASE+MIPSCPU_INT_COREHI, + setup_irq_smtc (MIPS_CPU_IRQ_BASE+MIPSCPU_INT_COREHI, &corehi_irqaction, (0x100 << MIPSCPU_INT_COREHI)); #else /* Not SMTC */ - setup_irq (MIPSCPU_INT_BASE+MIPSCPU_INT_I8259A, &i8259irq); - setup_irq (MIPSCPU_INT_BASE+MIPSCPU_INT_COREHI, &corehi_irqaction); + setup_irq (MIPS_CPU_IRQ_BASE+MIPSCPU_INT_I8259A, &i8259irq); + setup_irq (MIPS_CPU_IRQ_BASE+MIPSCPU_INT_COREHI, &corehi_irqaction); #endif /* CONFIG_MIPS_MT_SMTC */ } else { - setup_irq (MIPSCPU_INT_BASE+MIPSCPU_INT_I8259A, &i8259irq); - setup_irq (MIPSCPU_INT_BASE+MIPSCPU_INT_COREHI, &corehi_irqaction); + setup_irq (MIPS_CPU_IRQ_BASE+MIPSCPU_INT_I8259A, &i8259irq); + setup_irq (MIPS_CPU_IRQ_BASE+MIPSCPU_INT_COREHI, &corehi_irqaction); } } diff --git a/arch/mips/mips-boards/sead/sead_int.c b/arch/mips/mips-boards/sead/sead_int.c index c4b9de3..9ca0f82 100644 --- a/arch/mips/mips-boards/sead/sead_int.c +++ b/arch/mips/mips-boards/sead/sead_int.c @@ -106,7 +106,7 @@ asmlinkage void plat_irq_dispatch(void) irq = irq_ffs(pending); if (irq >= 0) - do_IRQ(MIPSCPU_INT_BASE + irq); + do_IRQ(MIPS_CPU_IRQ_BASE + irq); else spurious_interrupt(); } diff --git a/arch/mips/mips-boards/sead/sead_setup.c b/arch/mips/mips-boards/sead/sead_setup.c index 811aba1..bb80140 100644 --- a/arch/mips/mips-boards/sead/sead_setup.c +++ b/arch/mips/mips-boards/sead/sead_setup.c @@ -68,7 +68,7 @@ static void __init serial_init(void) #else s.iobase = SEAD_UART0_REGS_BASE+3; #endif - s.irq = MIPSCPU_INT_BASE + MIPSCPU_INT_UART0; + s.irq = MIPS_CPU_IRQ_BASE + MIPSCPU_INT_UART0; s.uartclk = SEAD_BASE_BAUD * 16; s.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_AUTO_IRQ; s.iotype = UPIO_PORT; diff --git a/arch/mips/mips-boards/sim/sim_int.c b/arch/mips/mips-boards/sim/sim_int.c index 15ac065..766e015 100644 --- a/arch/mips/mips-boards/sim/sim_int.c +++ b/arch/mips/mips-boards/sim/sim_int.c @@ -77,7 +77,7 @@ asmlinkage void plat_irq_dispatch(void) irq = irq_ffs(pending); if (irq > 0) - do_IRQ(MIPSCPU_INT_BASE + irq); + do_IRQ(MIPS_CPU_IRQ_BASE + irq); else spurious_interrupt(); } diff --git a/arch/mips/mips-boards/sim/sim_time.c b/arch/mips/mips-boards/sim/sim_time.c index d3a21c7..7224ffe 100644 --- a/arch/mips/mips-boards/sim/sim_time.c +++ b/arch/mips/mips-boards/sim/sim_time.c @@ -71,8 +71,8 @@ irqreturn_t sim_timer_interrupt(int irq, void *dev_id) int vpflags = dvpe(); write_c0_compare (read_c0_count() - 1); - clear_c0_cause(0x100 << MIPSCPU_INT_CPUCTR); - set_c0_status(0x100 << MIPSCPU_INT_CPUCTR); + clear_c0_cause(0x100 << cp0_compare_irq); + set_c0_status(0x100 << cp0_compare_irq); irq_enable_hazard(); evpe(vpflags); @@ -183,8 +183,8 @@ void __init plat_timer_setup(struct irqaction *irq) } else { if (cpu_has_vint) - set_vi_handler(MIPSCPU_INT_CPUCTR, mips_timer_dispatch); - mips_cpu_timer_irq = MIPSCPU_INT_BASE + MIPSCPU_INT_CPUCTR; + set_vi_handler(cp0_compare_irq, mips_timer_dispatch); + mips_cpu_timer_irq = MIPS_CPU_IRQ_BASE + cp0_compare_irq; } /* we are using the cpu counter for timer interrupts */ -- cgit v1.1