From 946db17349f6922a9c8a959c34ad9fb3aa238952 Mon Sep 17 00:00:00 2001 From: Paul Burton Date: Tue, 22 Sep 2015 11:12:12 -0700 Subject: MIPS: CPS: Read CM GCR base from cop0 Rather than patching the start of mips_cps_core_entry to provide the base address of the CM GCRs, simply read that base address from the cop0 CMGCRBase register, converting from the physical address to an uncached virtual address. Signed-off-by: Paul Burton Cc: linux-mips@linux-mips.org Cc: Rusty Russell Cc: Andrew Bresticker Cc: linux-kernel@vger.kernel.org Cc: Niklas Cassel Cc: Ezequiel Garcia Cc: Markos Chandras Patchwork: https://patchwork.linux-mips.org/patch/11203/ Signed-off-by: Ralf Baechle --- arch/mips/kernel/smp-cps.c | 2 -- 1 file changed, 2 deletions(-) (limited to 'arch/mips/kernel/smp-cps.c') diff --git a/arch/mips/kernel/smp-cps.c b/arch/mips/kernel/smp-cps.c index c889377..8b96750 100644 --- a/arch/mips/kernel/smp-cps.c +++ b/arch/mips/kernel/smp-cps.c @@ -133,11 +133,9 @@ static void __init cps_prepare_cpus(unsigned int max_cpus) /* * Patch the start of mips_cps_core_entry to provide: * - * v1 = CM base address * s0 = kseg0 CCA */ entry_code = (u32 *)&mips_cps_core_entry; - UASM_i_LA(&entry_code, 3, (long)mips_cm_base); uasm_i_addiu(&entry_code, 16, 0, cca); blast_dcache_range((unsigned long)&mips_cps_core_entry, (unsigned long)entry_code); -- cgit v1.1 From a8c20614b0163a71f2df3f9788bfe8b9ff07d742 Mon Sep 17 00:00:00 2001 From: Paul Burton Date: Tue, 22 Sep 2015 11:12:14 -0700 Subject: MIPS: CPS: Warn if a core doesn't start When debugging core bringup it is useful to see the state of the CPC sequencer, so output that value if the core hasn't started within a reasonable amount of time (1 second). This avoids simply appearing to the user to hang if a secondary core fails to start. Signed-off-by: Paul Burton Cc: linux-mips@linux-mips.org Cc: Rusty Russell Cc: Andrew Bresticker Cc: linux-kernel@vger.kernel.org Cc: Niklas Cassel Cc: Ezequiel Garcia Cc: Markos Chandras Patchwork: https://patchwork.linux-mips.org/patch/11205/ Signed-off-by: Ralf Baechle --- arch/mips/kernel/smp-cps.c | 26 +++++++++++++++++++++++++- 1 file changed, 25 insertions(+), 1 deletion(-) (limited to 'arch/mips/kernel/smp-cps.c') diff --git a/arch/mips/kernel/smp-cps.c b/arch/mips/kernel/smp-cps.c index 8b96750..48b1b75 100644 --- a/arch/mips/kernel/smp-cps.c +++ b/arch/mips/kernel/smp-cps.c @@ -8,6 +8,7 @@ * option) any later version. */ +#include #include #include #include @@ -188,7 +189,8 @@ err_out: static void boot_core(unsigned core) { - u32 access; + u32 access, stat, seq_state; + unsigned timeout; /* Select the appropriate core */ write_gcr_cl_other(core << CM_GCR_Cx_OTHER_CORENUM_SHF); @@ -208,6 +210,28 @@ static void boot_core(unsigned core) /* Reset the core */ mips_cpc_lock_other(core); write_cpc_co_cmd(CPC_Cx_CMD_RESET); + + timeout = 100; + while (true) { + stat = read_cpc_co_stat_conf(); + seq_state = stat & CPC_Cx_STAT_CONF_SEQSTATE_MSK; + + /* U6 == coherent execution, ie. the core is up */ + if (seq_state == CPC_Cx_STAT_CONF_SEQSTATE_U6) + break; + + /* Delay a little while before we start warning */ + if (timeout) { + timeout--; + mdelay(10); + continue; + } + + pr_warn("Waiting for core %u to start... STAT_CONF=0x%x\n", + core, stat); + mdelay(1000); + } + mips_cpc_unlock_other(); } else { /* Take the core out of reset */ -- cgit v1.1 From 4ede31617056b7424eef28dce59dd6dbe81729c3 Mon Sep 17 00:00:00 2001 From: Paul Burton Date: Tue, 22 Sep 2015 11:12:17 -0700 Subject: MIPS: CM: make use of mips_cm_{lock,unlock}_other Document that CPC core-other accesses must take place within the bounds of the CM lock, and begin using the CM lock functions where we access the GCRs of other cores. This is required because with CM3 the CPC began using GCR_CL_OTHER instead of CPC_CL_OTHER. Signed-off-by: Paul Burton Cc: linux-mips@linux-mips.org Cc: Rusty Russell Cc: Andrew Bresticker Cc: Bjorn Helgaas Cc: linux-kernel@vger.kernel.org Cc: Niklas Cassel Cc: Ezequiel Garcia Cc: Markos Chandras Patchwork: https://patchwork.linux-mips.org/patch/11208/ Signed-off-by: Ralf Baechle --- arch/mips/kernel/smp-cps.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) (limited to 'arch/mips/kernel/smp-cps.c') diff --git a/arch/mips/kernel/smp-cps.c b/arch/mips/kernel/smp-cps.c index 48b1b75..e04c805 100644 --- a/arch/mips/kernel/smp-cps.c +++ b/arch/mips/kernel/smp-cps.c @@ -38,8 +38,9 @@ static unsigned core_vpe_count(unsigned core) if (!config_enabled(CONFIG_MIPS_MT_SMP) || !cpu_has_mipsmt) return 1; - write_gcr_cl_other(core << CM_GCR_Cx_OTHER_CORENUM_SHF); + mips_cm_lock_other(core, 0); cfg = read_gcr_co_config() & CM_GCR_Cx_CONFIG_PVPE_MSK; + mips_cm_unlock_other(); return (cfg >> CM_GCR_Cx_CONFIG_PVPE_SHF) + 1; } @@ -193,7 +194,7 @@ static void boot_core(unsigned core) unsigned timeout; /* Select the appropriate core */ - write_gcr_cl_other(core << CM_GCR_Cx_OTHER_CORENUM_SHF); + mips_cm_lock_other(core, 0); /* Set its reset vector */ write_gcr_co_reset_base(CKSEG1ADDR((unsigned long)mips_cps_core_entry)); @@ -238,6 +239,8 @@ static void boot_core(unsigned core) write_gcr_co_reset_release(0); } + mips_cm_unlock_other(); + /* The core is now powered up */ bitmap_set(core_power, core, 1); } -- cgit v1.1