From 1820ec1d2b993f3ec00169e881504aa4541a9bf7 Mon Sep 17 00:00:00 2001 From: Manuel Lauss Date: Sun, 21 Dec 2008 09:26:20 +0100 Subject: MIPS: Alchemy: remove get/set_au1x00_lcd_clock(). There are no in-tree users, so remove them. Signed-off-by: Manuel Lauss Signed-off-by: Ralf Baechle --- arch/mips/alchemy/common/time.c | 1 - 1 file changed, 1 deletion(-) (limited to 'arch/mips/alchemy/common/time.c') diff --git a/arch/mips/alchemy/common/time.c b/arch/mips/alchemy/common/time.c index 563d939..68d7142 100644 --- a/arch/mips/alchemy/common/time.c +++ b/arch/mips/alchemy/common/time.c @@ -224,7 +224,6 @@ void __init plat_time_init(void) printk(KERN_INFO "CPU frequency %u.%02u MHz\n", est_freq / 1000000, ((est_freq % 1000000) * 100) / 1000000); set_au1x00_speed(est_freq); - set_au1x00_lcd_clock(); /* program the LCD clock */ #ifdef CONFIG_PM /* -- cgit v1.1 From 074cf656700ddd1d2bd7f815f78e785418beb898 Mon Sep 17 00:00:00 2001 From: Manuel Lauss Date: Sun, 21 Dec 2008 09:26:21 +0100 Subject: MIPS: Alchemy: remove cpu_table. Remove the cpu_table: - move detection of whether c0_config[OD] is read-only and should be set to fix various chip errata to au1000 headers. - move detection of write-only sys_cpupll to au1000 headers. - remove the BCLK switching code: Activation of this features should be left to the boards using the chips since it also affects external devices tied to BCLK, and only the board designers know whether it is safe to enable. Signed-off-by: Manuel Lauss Signed-off-by: Ralf Baechle delete mode 100644 arch/mips/alchemy/common/cputable.c --- arch/mips/alchemy/common/time.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/mips/alchemy/common/time.c') diff --git a/arch/mips/alchemy/common/time.c b/arch/mips/alchemy/common/time.c index 68d7142..1518570 100644 --- a/arch/mips/alchemy/common/time.c +++ b/arch/mips/alchemy/common/time.c @@ -198,7 +198,7 @@ unsigned long calc_clock(void) * silicon versions of Au1000 are not sold by AMD, we don't bend * over backwards trying to determine the frequency. */ - if (cur_cpu_spec[0]->cpu_pll_wo) + if (au1xxx_cpu_has_pll_wo()) #ifdef CONFIG_SOC_AU1000_FREQUENCY cpu_speed = CONFIG_SOC_AU1000_FREQUENCY; #else @@ -221,7 +221,7 @@ void __init plat_time_init(void) est_freq += 5000; /* round */ est_freq -= est_freq%10000; - printk(KERN_INFO "CPU frequency %u.%02u MHz\n", + printk(KERN_INFO "(PRId %08x) @ %u.%02u MHz\n", read_c0_prid(), est_freq / 1000000, ((est_freq % 1000000) * 100) / 1000000); set_au1x00_speed(est_freq); -- cgit v1.1 From 0c694de12b54fa96b9555e07603f567906ce21c8 Mon Sep 17 00:00:00 2001 From: Manuel Lauss Date: Sun, 21 Dec 2008 09:26:23 +0100 Subject: MIPS: Alchemy: RTC counter clocksource / clockevent support. Add support for the 32 kHz counter1 (RTC) as clocksource / clockevent device. As a nice side effect, this also enables use of the 'wait' instruction for runtime idle power savings. If the counters aren't enabled/working properly, fall back on the cp0 counter clock code. Signed-off-by: Manuel Lauss Signed-off-by: Ralf Baechle --- arch/mips/alchemy/common/time.c | 292 +++++++++++++++++----------------------- 1 file changed, 123 insertions(+), 169 deletions(-) (limited to 'arch/mips/alchemy/common/time.c') diff --git a/arch/mips/alchemy/common/time.c b/arch/mips/alchemy/common/time.c index 1518570..57f0aec 100644 --- a/arch/mips/alchemy/common/time.c +++ b/arch/mips/alchemy/common/time.c @@ -1,5 +1,7 @@ /* + * Copyright (C) 2008 Manuel Lauss * + * Previous incarnations were: * Copyright (C) 2001, 2006, 2008 MontaVista Software, * Copied and modified Carsten Langgaard's time.c * @@ -23,131 +25,27 @@ * * ######################################################################## * - * Setting up the clock on the MIPS boards. - * - * We provide the clock interrupt processing and the timer offset compute - * functions. If CONFIG_PM is selected, we also ensure the 32KHz timer is - * available. -- Dan + * Clocksource/event using the 32.768kHz-clocked Counter1 ('RTC' in the + * databooks). Firmware/Board init code must enable the counters in the + * counter control register, otherwise the CP0 counter clocksource/event + * will be installed instead (and use of 'wait' instruction is prohibited). */ -#include -#include +#include +#include +#include #include -#include #include #include -static int no_au1xxx_32khz; -extern int allow_au1k_wait; /* default off for CP0 Counter */ +/* 32kHz clock enabled and detected */ +#define CNTR_OK (SYS_CNTRL_E0 | SYS_CNTRL_32S) -#ifdef CONFIG_PM -#if HZ < 100 || HZ > 1000 -#error "unsupported HZ value! Must be in [100,1000]" -#endif -#define MATCH20_INC (328 * 100 / HZ) /* magic number 328 is for HZ=100... */ -static unsigned long last_pc0, last_match20; -#endif +extern int allow_au1k_wait; /* default off for CP0 Counter */ static DEFINE_SPINLOCK(time_lock); -unsigned long wtimer; - -#ifdef CONFIG_PM -static irqreturn_t counter0_irq(int irq, void *dev_id) -{ - unsigned long pc0; - int time_elapsed; - static int jiffie_drift; - - if (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_M20) { - /* should never happen! */ - printk(KERN_WARNING "counter 0 w status error\n"); - return IRQ_NONE; - } - - pc0 = au_readl(SYS_TOYREAD); - if (pc0 < last_match20) - /* counter overflowed */ - time_elapsed = (0xffffffff - last_match20) + pc0; - else - time_elapsed = pc0 - last_match20; - - while (time_elapsed > 0) { - do_timer(1); -#ifndef CONFIG_SMP - update_process_times(user_mode(get_irq_regs())); -#endif - time_elapsed -= MATCH20_INC; - last_match20 += MATCH20_INC; - jiffie_drift++; - } - - last_pc0 = pc0; - au_writel(last_match20 + MATCH20_INC, SYS_TOYMATCH2); - au_sync(); - - /* - * Our counter ticks at 10.009765625 ms/tick, we we're running - * almost 10 uS too slow per tick. - */ - - if (jiffie_drift >= 999) { - jiffie_drift -= 999; - do_timer(1); /* increment jiffies by one */ -#ifndef CONFIG_SMP - update_process_times(user_mode(get_irq_regs())); -#endif - } - - return IRQ_HANDLED; -} - -struct irqaction counter0_action = { - .handler = counter0_irq, - .flags = IRQF_DISABLED, - .name = "alchemy-toy", - .dev_id = NULL, -}; - -/* When we wakeup from sleep, we have to "catch up" on all of the - * timer ticks we have missed. - */ -void wakeup_counter0_adjust(void) -{ - unsigned long pc0; - int time_elapsed; - - pc0 = au_readl(SYS_TOYREAD); - if (pc0 < last_match20) - /* counter overflowed */ - time_elapsed = (0xffffffff - last_match20) + pc0; - else - time_elapsed = pc0 - last_match20; - - while (time_elapsed > 0) { - time_elapsed -= MATCH20_INC; - last_match20 += MATCH20_INC; - } - - last_pc0 = pc0; - au_writel(last_match20 + MATCH20_INC, SYS_TOYMATCH2); - au_sync(); - -} - -/* This is just for debugging to set the timer for a sleep delay. */ -void wakeup_counter0_set(int ticks) -{ - unsigned long pc0; - - pc0 = au_readl(SYS_TOYREAD); - last_pc0 = pc0; - au_writel(last_match20 + (MATCH20_INC * ticks), SYS_TOYMATCH2); - au_sync(); -} -#endif - /* * I haven't found anyone that doesn't use a 12 MHz source clock, * but just in case..... @@ -162,37 +60,15 @@ void wakeup_counter0_set(int ticks) * this advertised speed will introduce error and sometimes not work * properly. This function is futher convoluted to still allow configurations * to do that in case they have really, really old silicon with a - * write-only PLL register, that we need the 32 KHz when power management - * "wait" is enabled, and we need to detect if the 32 KHz isn't present - * but requested......got it? :-) -- Dan + * write-only PLL register. -- Dan */ unsigned long calc_clock(void) { unsigned long cpu_speed; unsigned long flags; - unsigned long counter; spin_lock_irqsave(&time_lock, flags); - /* Power management cares if we don't have a 32 KHz counter. */ - no_au1xxx_32khz = 0; - counter = au_readl(SYS_COUNTER_CNTRL); - if (counter & SYS_CNTRL_E0) { - int trim_divide = 16; - - au_writel(counter | SYS_CNTRL_EN1, SYS_COUNTER_CNTRL); - - while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_T1S); - /* RTC now ticks at 32.768/16 kHz */ - au_writel(trim_divide - 1, SYS_RTCTRIM); - while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_T1S); - - while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C1S); - au_writel(0, SYS_TOYWRITE); - while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C1S); - } else - no_au1xxx_32khz = 1; - /* * On early Au1000, sys_cpupll was write-only. Since these * silicon versions of Au1000 are not sold by AMD, we don't bend @@ -215,8 +91,65 @@ unsigned long calc_clock(void) return cpu_speed; } +static cycle_t au1x_counter1_read(void) +{ + return au_readl(SYS_RTCREAD); +} + +static struct clocksource au1x_counter1_clocksource = { + .name = "alchemy-counter1", + .read = au1x_counter1_read, + .mask = CLOCKSOURCE_MASK(32), + .flags = CLOCK_SOURCE_IS_CONTINUOUS, + .rating = 100, +}; + +static int au1x_rtcmatch2_set_next_event(unsigned long delta, + struct clock_event_device *cd) +{ + delta += au_readl(SYS_RTCREAD); + /* wait for register access */ + while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_M21) + ; + au_writel(delta, SYS_RTCMATCH2); + au_sync(); + + return 0; +} + +static void au1x_rtcmatch2_set_mode(enum clock_event_mode mode, + struct clock_event_device *cd) +{ +} + +static irqreturn_t au1x_rtcmatch2_irq(int irq, void *dev_id) +{ + struct clock_event_device *cd = dev_id; + cd->event_handler(cd); + return IRQ_HANDLED; +} + +static struct clock_event_device au1x_rtcmatch2_clockdev = { + .name = "rtcmatch2", + .features = CLOCK_EVT_FEAT_ONESHOT, + .rating = 100, + .irq = AU1000_RTC_MATCH2_INT, + .set_next_event = au1x_rtcmatch2_set_next_event, + .set_mode = au1x_rtcmatch2_set_mode, + .cpumask = CPU_MASK_ALL, +}; + +static struct irqaction au1x_rtcmatch2_irqaction = { + .handler = au1x_rtcmatch2_irq, + .flags = IRQF_DISABLED | IRQF_TIMER, + .name = "timer", + .dev_id = &au1x_rtcmatch2_clockdev, +}; + void __init plat_time_init(void) { + struct clock_event_device *cd = &au1x_rtcmatch2_clockdev; + unsigned long t; unsigned int est_freq = calc_clock(); est_freq += 5000; /* round */ @@ -225,41 +158,62 @@ void __init plat_time_init(void) est_freq / 1000000, ((est_freq % 1000000) * 100) / 1000000); set_au1x00_speed(est_freq); -#ifdef CONFIG_PM - /* - * setup counter 0, since it keeps ticking after a - * 'wait' instruction has been executed. The CP0 timer and - * counter 1 do NOT continue running after 'wait' - * - * It's too early to call request_irq() here, so we handle - * counter 0 interrupt as a special irq and it doesn't show - * up under /proc/interrupts. - * - * Check to ensure we really have a 32 KHz oscillator before - * we do this. + /* Check if firmware (YAMON, ...) has enabled 32kHz and clock + * has been detected. If so install the rtcmatch2 clocksource, + * otherwise don't bother. Note that both bits being set is by + * no means a definite guarantee that the counters actually work + * (the 32S bit seems to be stuck set to 1 once a single clock- + * edge is detected, hence the timeouts). */ - if (no_au1xxx_32khz) - printk(KERN_WARNING "WARNING: no 32KHz clock found.\n"); - else { - while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C0S); - au_writel(0, SYS_TOYWRITE); - while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C0S); + if (CNTR_OK != (au_readl(SYS_COUNTER_CNTRL) & CNTR_OK)) + goto cntr_err; - au_writel(au_readl(SYS_WAKEMSK) | (1 << 8), SYS_WAKEMSK); - au_writel(~0, SYS_WAKESRC); - au_sync(); - while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_M20); + /* + * setup counter 1 (RTC) to tick at full speed + */ + t = 0xffffff; + while ((au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_T1S) && t--) + asm volatile ("nop"); + if (!t) + goto cntr_err; - /* Setup match20 to interrupt once every HZ */ - last_pc0 = last_match20 = au_readl(SYS_TOYREAD); - au_writel(last_match20 + MATCH20_INC, SYS_TOYMATCH2); - au_sync(); - while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_M20); - setup_irq(AU1000_TOY_MATCH2_INT, &counter0_action); + au_writel(0, SYS_RTCTRIM); /* 32.768 kHz */ + au_sync(); - /* We can use the real 'wait' instruction. */ - allow_au1k_wait = 1; - } + t = 0xffffff; + while ((au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C1S) && t--) + asm volatile ("nop"); + if (!t) + goto cntr_err; + au_writel(0, SYS_RTCWRITE); + au_sync(); -#endif + t = 0xffffff; + while ((au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C1S) && t--) + asm volatile ("nop"); + if (!t) + goto cntr_err; + + /* register counter1 clocksource and event device */ + clocksource_set_clock(&au1x_counter1_clocksource, 32768); + clocksource_register(&au1x_counter1_clocksource); + + cd->shift = 32; + cd->mult = div_sc(32768, NSEC_PER_SEC, cd->shift); + cd->max_delta_ns = clockevent_delta2ns(0xffffffff, cd); + cd->min_delta_ns = clockevent_delta2ns(8, cd); /* ~0.25ms */ + clockevents_register_device(cd); + setup_irq(AU1000_RTC_MATCH2_INT, &au1x_rtcmatch2_irqaction); + + printk(KERN_INFO "Alchemy clocksource installed\n"); + + /* can now use 'wait' */ + allow_au1k_wait = 1; + return; + +cntr_err: + /* counters unusable, use C0 counter */ + r4k_clockevent_init(); + init_r4k_clocksource(); + allow_au1k_wait = 0; } -- cgit v1.1 From 2699cdfb765c3b7d77d28ea3bc7d84e486697177 Mon Sep 17 00:00:00 2001 From: Manuel Lauss Date: Sun, 21 Dec 2008 09:26:24 +0100 Subject: MIPS: Alchemy: move calc_clock function. Now that nothing in time.c depends on calc_clock, it can be moved to clocks.c where it belongs. While at it, give it a better non-generic name and call it as soon as possible in plat_mem_init. Signed-off-by: Manuel Lauss Signed-off-by: Ralf Baechle --- arch/mips/alchemy/common/time.c | 54 ----------------------------------------- 1 file changed, 54 deletions(-) (limited to 'arch/mips/alchemy/common/time.c') diff --git a/arch/mips/alchemy/common/time.c b/arch/mips/alchemy/common/time.c index 57f0aec..3288014 100644 --- a/arch/mips/alchemy/common/time.c +++ b/arch/mips/alchemy/common/time.c @@ -44,53 +44,6 @@ extern int allow_au1k_wait; /* default off for CP0 Counter */ -static DEFINE_SPINLOCK(time_lock); - -/* - * I haven't found anyone that doesn't use a 12 MHz source clock, - * but just in case..... - */ -#define AU1000_SRC_CLK 12000000 - -/* - * We read the real processor speed from the PLL. This is important - * because it is more accurate than computing it from the 32 KHz - * counter, if it exists. If we don't have an accurate processor - * speed, all of the peripherals that derive their clocks based on - * this advertised speed will introduce error and sometimes not work - * properly. This function is futher convoluted to still allow configurations - * to do that in case they have really, really old silicon with a - * write-only PLL register. -- Dan - */ -unsigned long calc_clock(void) -{ - unsigned long cpu_speed; - unsigned long flags; - - spin_lock_irqsave(&time_lock, flags); - - /* - * On early Au1000, sys_cpupll was write-only. Since these - * silicon versions of Au1000 are not sold by AMD, we don't bend - * over backwards trying to determine the frequency. - */ - if (au1xxx_cpu_has_pll_wo()) -#ifdef CONFIG_SOC_AU1000_FREQUENCY - cpu_speed = CONFIG_SOC_AU1000_FREQUENCY; -#else - cpu_speed = 396000000; -#endif - else - cpu_speed = (au_readl(SYS_CPUPLL) & 0x0000003f) * AU1000_SRC_CLK; - /* On Alchemy CPU:counter ratio is 1:1 */ - mips_hpt_frequency = cpu_speed; - /* Equation: Baudrate = CPU / (SD * 2 * CLKDIV * 16) */ - set_au1x00_uart_baud_base(cpu_speed / (2 * ((int)(au_readl(SYS_POWERCTRL) - & 0x03) + 2) * 16)); - spin_unlock_irqrestore(&time_lock, flags); - return cpu_speed; -} - static cycle_t au1x_counter1_read(void) { return au_readl(SYS_RTCREAD); @@ -150,13 +103,6 @@ void __init plat_time_init(void) { struct clock_event_device *cd = &au1x_rtcmatch2_clockdev; unsigned long t; - unsigned int est_freq = calc_clock(); - - est_freq += 5000; /* round */ - est_freq -= est_freq%10000; - printk(KERN_INFO "(PRId %08x) @ %u.%02u MHz\n", read_c0_prid(), - est_freq / 1000000, ((est_freq % 1000000) * 100) / 1000000); - set_au1x00_speed(est_freq); /* Check if firmware (YAMON, ...) has enabled 32kHz and clock * has been detected. If so install the rtcmatch2 clocksource, -- cgit v1.1 From 2d2eca4d11933bd37a4944aae06e6122efffaea8 Mon Sep 17 00:00:00 2001 From: Manuel Lauss Date: Tue, 6 Jan 2009 10:34:52 +0100 Subject: MIPS: Alchemy: time.c build fix In Linus' current -git the cpumask member is now a pointer. Signed-off-by: Manuel Lauss Signed-off-by: Ralf Baechle --- arch/mips/alchemy/common/time.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/mips/alchemy/common/time.c') diff --git a/arch/mips/alchemy/common/time.c b/arch/mips/alchemy/common/time.c index 3288014..6fd441d 100644 --- a/arch/mips/alchemy/common/time.c +++ b/arch/mips/alchemy/common/time.c @@ -89,7 +89,7 @@ static struct clock_event_device au1x_rtcmatch2_clockdev = { .irq = AU1000_RTC_MATCH2_INT, .set_next_event = au1x_rtcmatch2_set_next_event, .set_mode = au1x_rtcmatch2_set_mode, - .cpumask = CPU_MASK_ALL, + .cpumask = CPU_MASK_ALL_PTR, }; static struct irqaction au1x_rtcmatch2_irqaction = { -- cgit v1.1 From 4b0d3f5c28c631c1aeb1860993572ad8468a4c11 Mon Sep 17 00:00:00 2001 From: Roel Kluin Date: Sat, 31 Jan 2009 12:23:34 +0100 Subject: MIPS: Alchemy: In plat_time_init() t reaches -1, tested: 0 With a postfix decrement t reaches -1 rather than 0, so the fall-back will not occur. Signed-off-by: Roel Kluin Cc: mano@roarinelk.homelinux.net Signed-off-by: Ralf Baechle --- arch/mips/alchemy/common/time.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'arch/mips/alchemy/common/time.c') diff --git a/arch/mips/alchemy/common/time.c b/arch/mips/alchemy/common/time.c index 6fd441d..f58d4ff 100644 --- a/arch/mips/alchemy/common/time.c +++ b/arch/mips/alchemy/common/time.c @@ -118,7 +118,7 @@ void __init plat_time_init(void) * setup counter 1 (RTC) to tick at full speed */ t = 0xffffff; - while ((au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_T1S) && t--) + while ((au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_T1S) && --t) asm volatile ("nop"); if (!t) goto cntr_err; @@ -127,7 +127,7 @@ void __init plat_time_init(void) au_sync(); t = 0xffffff; - while ((au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C1S) && t--) + while ((au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C1S) && --t) asm volatile ("nop"); if (!t) goto cntr_err; @@ -135,7 +135,7 @@ void __init plat_time_init(void) au_sync(); t = 0xffffff; - while ((au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C1S) && t--) + while ((au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C1S) && --t) asm volatile ("nop"); if (!t) goto cntr_err; -- cgit v1.1