From 672c54466d24994eb9633f993862c89539504a42 Mon Sep 17 00:00:00 2001 From: Grant Likely Date: Thu, 13 Jan 2011 15:36:09 -0700 Subject: dt/flattree: Return virtual address from early_init_dt_alloc_memory_arch() The physical address is never used by the device tree code when allocating memory for unflattening. Change the architecture's alloc hook to return the virutal address instead. Signed-off-by: Grant Likely --- arch/microblaze/kernel/prom.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/microblaze') diff --git a/arch/microblaze/kernel/prom.c b/arch/microblaze/kernel/prom.c index c881393..bceaa55 100644 --- a/arch/microblaze/kernel/prom.c +++ b/arch/microblaze/kernel/prom.c @@ -47,9 +47,9 @@ void __init early_init_dt_add_memory_arch(u64 base, u64 size) memblock_add(base, size); } -u64 __init early_init_dt_alloc_memory_arch(u64 size, u64 align) +void * __init early_init_dt_alloc_memory_arch(u64 size, u64 align) { - return memblock_alloc(size, align); + return __va(memblock_alloc(size, align)); } #ifdef CONFIG_EARLY_PRINTK -- cgit v1.1 From 1947fc1d51fa7c21e9c253d37d076ef6f4d73130 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Sun, 16 Jan 2011 13:50:17 +0100 Subject: microblaze: Fix missing pagemap.h Add missing linux/pagemap.h to solve compilation error. Error log: In file included from linux/arch/microblaze/include/asm/tlb.h:17, from mm/pgtable-generic.c:9: include/asm-generic/tlb.h: In function 'tlb_flush_mmu': include/asm-generic/tlb.h:76: error: implicit declaration of function 'release_pages' include/asm-generic/tlb.h: In function 'tlb_remove_page': include/asm-generic/tlb.h:105: error: implicit declaration of function 'page_cache_release' Signed-off-by: Michal Simek --- arch/microblaze/include/asm/tlb.h | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/microblaze') diff --git a/arch/microblaze/include/asm/tlb.h b/arch/microblaze/include/asm/tlb.h index e8abd4a..8aa9781 100644 --- a/arch/microblaze/include/asm/tlb.h +++ b/arch/microblaze/include/asm/tlb.h @@ -13,6 +13,7 @@ #define tlb_flush(tlb) flush_tlb_mm((tlb)->mm) +#include #include #ifdef CONFIG_MMU -- cgit v1.1 From 658b368da198a1436c7d6a0f1f4029d3c6e30b20 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Sun, 16 Jan 2011 13:56:53 +0100 Subject: microblaze: Fix asm/pgtable.h Function ptep_test_and_clear_young have had wrong the first argument. It is also necessary to add __HAVE macros for ptep_test_and_clear_young and ptep_get_and_clear functions. Error log: In file included from linux/arch/microblaze/include/asm/pgtable.h:570, from arch/microblaze/mm/pgtable.c:35: include/asm-generic/pgtable.h:23: error: conflicting types for 'ptep_test_and_clear_young' linux/arch/microblaze/include/asm/pgtable.h:449: error: previous definition of 'ptep_test_and_clear_young' was here include/asm-generic/pgtable.h:73: error: redefinition of 'ptep_get_and_clear' linux/arch/microblaze/include/asm/pgtable.h:462: error: previous definition of 'ptep_get_and_clear' was here Signed-off-by: Michal Simek --- arch/microblaze/include/asm/pgtable.h | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'arch/microblaze') diff --git a/arch/microblaze/include/asm/pgtable.h b/arch/microblaze/include/asm/pgtable.h index cae268c2..b23f680 100644 --- a/arch/microblaze/include/asm/pgtable.h +++ b/arch/microblaze/include/asm/pgtable.h @@ -444,8 +444,9 @@ static inline void set_pte_at(struct mm_struct *mm, unsigned long addr, *ptep = pte; } -static inline int ptep_test_and_clear_young(struct mm_struct *mm, - unsigned long addr, pte_t *ptep) +#define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG +static inline int ptep_test_and_clear_young(struct vm_area_struct *vma, + unsigned long address, pte_t *ptep) { return (pte_update(ptep, _PAGE_ACCESSED, 0) & _PAGE_ACCESSED) != 0; } @@ -457,6 +458,7 @@ static inline int ptep_test_and_clear_dirty(struct mm_struct *mm, (_PAGE_DIRTY | _PAGE_HWWRITE), 0) & _PAGE_DIRTY) != 0; } +#define __HAVE_ARCH_PTEP_GET_AND_CLEAR static inline pte_t ptep_get_and_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep) { -- cgit v1.1 From 6a108a14fa356ef607be308b68337939e56ea94e Mon Sep 17 00:00:00 2001 From: David Rientjes Date: Thu, 20 Jan 2011 14:44:16 -0800 Subject: kconfig: rename CONFIG_EMBEDDED to CONFIG_EXPERT The meaning of CONFIG_EMBEDDED has long since been obsoleted; the option is used to configure any non-standard kernel with a much larger scope than only small devices. This patch renames the option to CONFIG_EXPERT in init/Kconfig and fixes references to the option throughout the kernel. A new CONFIG_EMBEDDED option is added that automatically selects CONFIG_EXPERT when enabled and can be used in the future to isolate options that should only be considered for embedded systems (RISC architectures, SLOB, etc). Calling the option "EXPERT" more accurately represents its intention: only expert users who understand the impact of the configuration changes they are making should enable it. Reviewed-by: Ingo Molnar Acked-by: David Woodhouse Signed-off-by: David Rientjes Cc: Greg KH Cc: "David S. Miller" Cc: Jens Axboe Cc: Arnd Bergmann Cc: Robin Holt Cc: Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- arch/microblaze/configs/mmu_defconfig | 2 +- arch/microblaze/configs/nommu_defconfig | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/microblaze') diff --git a/arch/microblaze/configs/mmu_defconfig b/arch/microblaze/configs/mmu_defconfig index ab8fbe7..b3f5eec 100644 --- a/arch/microblaze/configs/mmu_defconfig +++ b/arch/microblaze/configs/mmu_defconfig @@ -7,7 +7,7 @@ CONFIG_BLK_DEV_INITRD=y CONFIG_INITRAMFS_SOURCE="rootfs.cpio" CONFIG_INITRAMFS_COMPRESSION_GZIP=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y CONFIG_KALLSYMS_ALL=y CONFIG_KALLSYMS_EXTRA_PASS=y # CONFIG_HOTPLUG is not set diff --git a/arch/microblaze/configs/nommu_defconfig b/arch/microblaze/configs/nommu_defconfig index ebc143c..0249e4b 100644 --- a/arch/microblaze/configs/nommu_defconfig +++ b/arch/microblaze/configs/nommu_defconfig @@ -6,7 +6,7 @@ CONFIG_BSD_PROCESS_ACCT_V3=y CONFIG_IKCONFIG=y CONFIG_IKCONFIG_PROC=y CONFIG_SYSFS_DEPRECATED_V2=y -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y CONFIG_KALLSYMS_ALL=y CONFIG_KALLSYMS_EXTRA_PASS=y # CONFIG_HOTPLUG is not set -- cgit v1.1 From 1c77ff22f539ceaa64ea43d6a26d867e84602cb7 Mon Sep 17 00:00:00 2001 From: Thomas Gleixner Date: Wed, 19 Jan 2011 19:41:35 +0100 Subject: genirq: Remove __do_IRQ All architectures are finally converted. Remove the cruft. Signed-off-by: Thomas Gleixner Cc: Richard Henderson Cc: Mike Frysinger Cc: David Howells Cc: Tony Luck Cc: Greg Ungerer Cc: Michal Simek Acked-by: David Howells Cc: Kyle McMartin Acked-by: Benjamin Herrenschmidt Cc: Chen Liqin Cc: "David S. Miller" Cc: Chris Metcalf Cc: Jeff Dike --- arch/microblaze/Kconfig | 3 --- 1 file changed, 3 deletions(-) (limited to 'arch/microblaze') diff --git a/arch/microblaze/Kconfig b/arch/microblaze/Kconfig index 5f5018a..5a63784 100644 --- a/arch/microblaze/Kconfig +++ b/arch/microblaze/Kconfig @@ -52,9 +52,6 @@ config GENERIC_TIME_VSYSCALL config GENERIC_CLOCKEVENTS def_bool y -config GENERIC_HARDIRQS_NO__DO_IRQ - def_bool y - config GENERIC_GPIO def_bool y -- cgit v1.1 From b6e31629e335e8664a11be05992d39b2ee030960 Mon Sep 17 00:00:00 2001 From: Thomas Gleixner Date: Wed, 19 Jan 2011 20:35:05 +0100 Subject: microblaze: Use generic irq Kconfig No functional change. Signed-off-by: Thomas Gleixner Acked-by: Michal Simek --- arch/microblaze/Kconfig | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) (limited to 'arch/microblaze') diff --git a/arch/microblaze/Kconfig b/arch/microblaze/Kconfig index 5a63784..3168003 100644 --- a/arch/microblaze/Kconfig +++ b/arch/microblaze/Kconfig @@ -15,6 +15,8 @@ config MICROBLAZE select TRACING_SUPPORT select OF select OF_EARLY_FLATTREE + select HAVE_GENERIC_HARDIRQS + select GENERIC_IRQ_PROBE config SWAP def_bool n @@ -37,12 +39,6 @@ config GENERIC_FIND_NEXT_BIT config GENERIC_HWEIGHT def_bool y -config GENERIC_HARDIRQS - def_bool y - -config GENERIC_IRQ_PROBE - def_bool y - config GENERIC_CALIBRATE_DELAY def_bool y -- cgit v1.1 From 026a2078791b64aede220b1b1a3e4dfe4ab175e7 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 26 Jan 2011 13:41:05 +0100 Subject: microblaze: Fix DTB passing from bootloader Little endian system needs to check OF_DT_HEADER but it is swapped because it is in big-endian. Microblaze LE provides lwr instruction which loads magic number in BIG endian format which can be compared. There is used the fact that if you write 0x1 as word and load it as byte then you get for big-endian zero and 1 for little-endian. Signed-off-by: Michal Simek --- arch/microblaze/kernel/head.S | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) (limited to 'arch/microblaze') diff --git a/arch/microblaze/kernel/head.S b/arch/microblaze/kernel/head.S index 4243400..0db20b5 100644 --- a/arch/microblaze/kernel/head.S +++ b/arch/microblaze/kernel/head.S @@ -77,8 +77,18 @@ real_start: We ensure r7 points to a valid FDT, just in case the bootloader is broken or non-existent */ beqi r7, no_fdt_arg /* NULL pointer? don't copy */ - lw r11, r0, r7 /* Does r7 point to a */ - rsubi r11, r11, OF_DT_HEADER /* valid FDT? */ +/* Does r7 point to a valid FDT? Load HEADER magic number */ + /* Run time Big/Little endian platform */ + /* Save 1 as word and load byte - 0 - BIG, 1 - LITTLE */ + addik r11, r0, 0x1 /* BIG/LITTLE checking value */ + /* __bss_start will be zeroed later - it is just temp location */ + swi r11, r0, TOPHYS(__bss_start) + lbui r11, r0, TOPHYS(__bss_start) + beqid r11, big_endian /* DO NOT break delay stop dependency */ + lw r11, r0, r7 /* Big endian load in delay slot */ + lwr r11, r0, r7 /* Little endian load */ +big_endian: + rsubi r11, r11, OF_DT_HEADER /* Check FDT header */ beqi r11, _prepare_copy_fdt or r7, r0, r0 /* clear R7 when not valid DTB */ bnei r11, no_fdt_arg /* No - get out of here */ -- cgit v1.1 From 9c749e177ccc0b3ee9589425c7255079e7a726fc Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Fri, 28 Jan 2011 13:14:58 +0100 Subject: microblaze: Fix unaligned issue on MMU system with BS=0 DIV=1 Unaligned code use shift for finding register operand. There is used BSRLI(r8,r8,2) macro which is expand for BS=0, DIV=1 by ori rD, r0, (1 << imm); \ idivu rD, rD, rA but if rD is equal rA then ori instruction rewrite value which should be devide. The patch remove this macro which use idivu instruction because idivu takes 32/34 cycles. The highest shifting is 20 which takes 20 cycles. Signed-off-by: Michal Simek --- arch/microblaze/kernel/hw_exception_handler.S | 4 ---- 1 file changed, 4 deletions(-) (limited to 'arch/microblaze') diff --git a/arch/microblaze/kernel/hw_exception_handler.S b/arch/microblaze/kernel/hw_exception_handler.S index 25f6e07..782680d 100644 --- a/arch/microblaze/kernel/hw_exception_handler.S +++ b/arch/microblaze/kernel/hw_exception_handler.S @@ -147,10 +147,6 @@ #if CONFIG_XILINX_MICROBLAZE0_USE_BARREL > 0 #define BSRLI(rD, rA, imm) \ bsrli rD, rA, imm - #elif CONFIG_XILINX_MICROBLAZE0_USE_DIV > 0 - #define BSRLI(rD, rA, imm) \ - ori rD, r0, (1 << imm); \ - idivu rD, rD, rA #else #define BSRLI(rD, rA, imm) BSRLI ## imm (rD, rA) /* Only the used shift constants defined here - add more if needed */ -- cgit v1.1 From de93c3c119382cb888ca8a94b642dbcf8035525e Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Fri, 28 Jan 2011 13:26:54 +0100 Subject: microblaze: Fix ASM optimized code for LE Microblaze little-endian doesn't support ASM optimized library functions(memcpy/memmove). Kconfig doens't contain any information about endian that's why it is necessary to check it in the source code. The code is used with barrel shifter is used. Signed-off-by: Michal Simek --- arch/microblaze/lib/fastcopy.S | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/microblaze') diff --git a/arch/microblaze/lib/fastcopy.S b/arch/microblaze/lib/fastcopy.S index fdc48bb..62021d7 100644 --- a/arch/microblaze/lib/fastcopy.S +++ b/arch/microblaze/lib/fastcopy.S @@ -29,6 +29,10 @@ * between mem locations with size of xfer spec'd in bytes */ +#ifdef __MICROBLAZEEL__ +#error Microblaze LE not support ASM optimized lib func. Disable OPT_LIB_ASM. +#endif + #include .text .globl memcpy -- cgit v1.1 From 12dfc73e1ddb44b2d23e0ca614b6ec50596adae0 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Mon, 7 Feb 2011 13:32:55 +0100 Subject: microblaze: Fix IRQ flag handling for MSR=0 Patch: Fix IRQ flag handling naming (sha1: f9ee29270c11dba7d0fe0b83ce47a4d8e8d2101) introduced problem on system with MSR=0. Signed-off-by: Michal Simek --- arch/microblaze/include/asm/irqflags.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/microblaze') diff --git a/arch/microblaze/include/asm/irqflags.h b/arch/microblaze/include/asm/irqflags.h index 5fd3190..c4532f0 100644 --- a/arch/microblaze/include/asm/irqflags.h +++ b/arch/microblaze/include/asm/irqflags.h @@ -12,7 +12,7 @@ #include #include -#ifdef CONFIG_XILINX_MICROBLAZE0_USE_MSR_INSTR +#if CONFIG_XILINX_MICROBLAZE0_USE_MSR_INSTR static inline unsigned long arch_local_irq_save(void) { -- cgit v1.1 From 1649700408531ec64ae33af55a1091db50d1f7da Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Mon, 7 Feb 2011 11:29:43 +0100 Subject: microblaze: Fix asm compilation warning Microblaze ASM doesn't support hex values for mfs instructions. /tmp/ccwiXVmt.s: Assembler messages: /tmp/ccwiXVmt.s:19: Warning: ignoring operands: x00 Signed-off-by: Michal Simek --- arch/microblaze/kernel/cpu/pvr.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/microblaze') diff --git a/arch/microblaze/kernel/cpu/pvr.c b/arch/microblaze/kernel/cpu/pvr.c index e01afa6..488c1ed 100644 --- a/arch/microblaze/kernel/cpu/pvr.c +++ b/arch/microblaze/kernel/cpu/pvr.c @@ -27,7 +27,7 @@ register unsigned tmp __asm__("r3"); \ tmp = 0x0; /* Prevent warning about unused */ \ __asm__ __volatile__ ( \ - "mfs %0, rpvr" #pvrid ";" \ + "mfs %0, rpvr" #pvrid ";" \ : "=r" (tmp) : : "memory"); \ val = tmp; \ } @@ -54,7 +54,7 @@ int cpu_has_pvr(void) if (!(flags & PVR_MSR_BIT)) return 0; - get_single_pvr(0x00, pvr0); + get_single_pvr(0, pvr0); pr_debug("%s: pvr0 is 0x%08x\n", __func__, pvr0); if (pvr0 & PVR0_PVR_FULL_MASK) -- cgit v1.1 From 1f80a67da2da4180355bc36b2691f16684b194fd Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Mon, 7 Feb 2011 18:51:54 +0100 Subject: microblaze: Fix pte_update function Do not disable irq in asm but use irq macros. Systems with MSR=0 couldn't use pte_update function because msrclr was hardcoded. Signed-off-by: Michal Simek --- arch/microblaze/include/asm/pgtable.h | 27 +++++++++++++-------------- 1 file changed, 13 insertions(+), 14 deletions(-) (limited to 'arch/microblaze') diff --git a/arch/microblaze/include/asm/pgtable.h b/arch/microblaze/include/asm/pgtable.h index b23f680..885574a 100644 --- a/arch/microblaze/include/asm/pgtable.h +++ b/arch/microblaze/include/asm/pgtable.h @@ -411,20 +411,19 @@ static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) static inline unsigned long pte_update(pte_t *p, unsigned long clr, unsigned long set) { - unsigned long old, tmp, msr; - - __asm__ __volatile__("\ - msrclr %2, 0x2\n\ - nop\n\ - lw %0, %4, r0\n\ - andn %1, %0, %5\n\ - or %1, %1, %6\n\ - sw %1, %4, r0\n\ - mts rmsr, %2\n\ - nop" - : "=&r" (old), "=&r" (tmp), "=&r" (msr), "=m" (*p) - : "r" ((unsigned long)(p + 1) - 4), "r" (clr), "r" (set), "m" (*p) - : "cc"); + unsigned long flags, old, tmp; + + raw_local_irq_save(flags); + + __asm__ __volatile__( "lw %0, %2, r0 \n" + "andn %1, %0, %3 \n" + "or %1, %1, %4 \n" + "sw %1, %2, r0 \n" + : "=&r" (old), "=&r" (tmp) + : "r" ((unsigned long)(p + 1) - 4), "r" (clr), "r" (set) + : "cc"); + + raw_local_irq_restore(flags); return old; } -- cgit v1.1 From 0eb6aaf52965c14ba3ea245448c4806cfcd1d18c Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Fri, 4 Feb 2011 15:24:11 +0100 Subject: microblaze: Fix msr instruction detection Fix msr instructions detection. The current code just use msrclr for loading msr content and compare it with proper MSR content. If msrclr is not implemented r8 contains pc address. Previous code wanted to use MSR carry bit but if msrclr wasn't implemented carry wasn't cleared. Signed-off-by: Michal Simek --- arch/microblaze/kernel/head.S | 15 +++++++-------- arch/microblaze/kernel/setup.c | 4 ++-- 2 files changed, 9 insertions(+), 10 deletions(-) (limited to 'arch/microblaze') diff --git a/arch/microblaze/kernel/head.S b/arch/microblaze/kernel/head.S index 0db20b5..778a5ce 100644 --- a/arch/microblaze/kernel/head.S +++ b/arch/microblaze/kernel/head.S @@ -62,15 +62,14 @@ real_start: andi r1, r1, ~2 mts rmsr, r1 /* - * Here is checking mechanism which check if Microblaze has msr instructions - * We load msr and compare it with previous r1 value - if is the same, - * msr instructions works if not - cpu don't have them. + * According to Xilinx, msrclr instruction behaves like 'mfs rX,rpc' + * if the msrclr instruction is not enabled. We use this to detect + * if the opcode is available, by issuing msrclr and then testing the result. + * r8 == 0 - msr instructions are implemented + * r8 != 0 - msr instructions are not implemented */ - /* r8=0 - I have msr instr, 1 - I don't have them */ - rsubi r0, r0, 1 /* set the carry bit */ - msrclr r0, 0x4 /* try to clear it */ - /* read the carry bit, r8 will be '0' if msrclr exists */ - addik r8, r0, 0 + msrclr r8, 0 /* clear nothing - just read msr for test */ + cmpu r8, r8, r1 /* r1 must contain msr reg content */ /* r7 may point to an FDT, or there may be one linked in. if it's in r7, we've got to save it away ASAP. diff --git a/arch/microblaze/kernel/setup.c b/arch/microblaze/kernel/setup.c index bb1558e..9312fbb 100644 --- a/arch/microblaze/kernel/setup.c +++ b/arch/microblaze/kernel/setup.c @@ -161,11 +161,11 @@ void __init machine_early_init(const char *cmdline, unsigned int ram, #if CONFIG_XILINX_MICROBLAZE0_USE_MSR_INSTR if (msr) eprintk("!!!Your kernel has setup MSR instruction but " - "CPU don't have it %d\n", msr); + "CPU don't have it %x\n", msr); #else if (!msr) eprintk("!!!Your kernel not setup MSR instruction but " - "CPU have it %d\n", msr); + "CPU have it %x\n", msr); #endif for (src = __ivt_start; src < __ivt_end; src++, dst++) -- cgit v1.1