From 863018a7a24a29c0862c62e70c89244fdd5a08bf Mon Sep 17 00:00:00 2001 From: Thomas Gleixner Date: Wed, 22 Sep 2010 19:13:16 +0200 Subject: m32r: Cleanup direct irq_desc access The irq descriptors are already initialized by the generic code. Remove the redundant init code and set the irq chip with the proper accessor function. Signed-off-by: Thomas Gleixner Cc: Hirokazu Takata Cc: Paul Mundt --- arch/m32r/platforms/opsput/setup.c | 70 ++++++++------------------------------ 1 file changed, 14 insertions(+), 56 deletions(-) (limited to 'arch/m32r/platforms/opsput/setup.c') diff --git a/arch/m32r/platforms/opsput/setup.c b/arch/m32r/platforms/opsput/setup.c index 5f3402a..a16a7fe 100644 --- a/arch/m32r/platforms/opsput/setup.c +++ b/arch/m32r/platforms/opsput/setup.c @@ -300,101 +300,65 @@ void __init init_IRQ(void) { #if defined(CONFIG_SMC91X) /* INT#0: LAN controller on OPSPUT-LAN (SMC91C111)*/ - irq_desc[OPSPUT_LAN_IRQ_LAN].status = IRQ_DISABLED; - irq_desc[OPSPUT_LAN_IRQ_LAN].chip = &opsput_lanpld_irq_type; - irq_desc[OPSPUT_LAN_IRQ_LAN].action = 0; - irq_desc[OPSPUT_LAN_IRQ_LAN].depth = 1; /* disable nested irq */ + set_irq_chip(OPSPUT_LAN_IRQ_LAN, &opsput_lanpld_irq_type); lanpld_icu_data[irq2lanpldirq(OPSPUT_LAN_IRQ_LAN)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD02; /* "H" edge sense */ disable_opsput_lanpld_irq(OPSPUT_LAN_IRQ_LAN); #endif /* CONFIG_SMC91X */ /* MFT2 : system timer */ - irq_desc[M32R_IRQ_MFT2].status = IRQ_DISABLED; - irq_desc[M32R_IRQ_MFT2].chip = &opsput_irq_type; - irq_desc[M32R_IRQ_MFT2].action = 0; - irq_desc[M32R_IRQ_MFT2].depth = 1; + set_irq_chip(M32R_IRQ_MFT2, &opsput_irq_type); icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN; disable_opsput_irq(M32R_IRQ_MFT2); /* SIO0 : receive */ - irq_desc[M32R_IRQ_SIO0_R].status = IRQ_DISABLED; - irq_desc[M32R_IRQ_SIO0_R].chip = &opsput_irq_type; - irq_desc[M32R_IRQ_SIO0_R].action = 0; - irq_desc[M32R_IRQ_SIO0_R].depth = 1; + set_irq_chip(M32R_IRQ_SIO0_R, &opsput_irq_type); icu_data[M32R_IRQ_SIO0_R].icucr = 0; disable_opsput_irq(M32R_IRQ_SIO0_R); /* SIO0 : send */ - irq_desc[M32R_IRQ_SIO0_S].status = IRQ_DISABLED; - irq_desc[M32R_IRQ_SIO0_S].chip = &opsput_irq_type; - irq_desc[M32R_IRQ_SIO0_S].action = 0; - irq_desc[M32R_IRQ_SIO0_S].depth = 1; + set_irq_chip(M32R_IRQ_SIO0_S, &opsput_irq_type); icu_data[M32R_IRQ_SIO0_S].icucr = 0; disable_opsput_irq(M32R_IRQ_SIO0_S); /* SIO1 : receive */ - irq_desc[M32R_IRQ_SIO1_R].status = IRQ_DISABLED; - irq_desc[M32R_IRQ_SIO1_R].chip = &opsput_irq_type; - irq_desc[M32R_IRQ_SIO1_R].action = 0; - irq_desc[M32R_IRQ_SIO1_R].depth = 1; + set_irq_chip(M32R_IRQ_SIO1_R, &opsput_irq_type); icu_data[M32R_IRQ_SIO1_R].icucr = 0; disable_opsput_irq(M32R_IRQ_SIO1_R); /* SIO1 : send */ - irq_desc[M32R_IRQ_SIO1_S].status = IRQ_DISABLED; - irq_desc[M32R_IRQ_SIO1_S].chip = &opsput_irq_type; - irq_desc[M32R_IRQ_SIO1_S].action = 0; - irq_desc[M32R_IRQ_SIO1_S].depth = 1; + set_irq_chip(M32R_IRQ_SIO1_S, &opsput_irq_type); icu_data[M32R_IRQ_SIO1_S].icucr = 0; disable_opsput_irq(M32R_IRQ_SIO1_S); /* DMA1 : */ - irq_desc[M32R_IRQ_DMA1].status = IRQ_DISABLED; - irq_desc[M32R_IRQ_DMA1].chip = &opsput_irq_type; - irq_desc[M32R_IRQ_DMA1].action = 0; - irq_desc[M32R_IRQ_DMA1].depth = 1; + set_irq_chip(M32R_IRQ_DMA1, &opsput_irq_type); icu_data[M32R_IRQ_DMA1].icucr = 0; disable_opsput_irq(M32R_IRQ_DMA1); #ifdef CONFIG_SERIAL_M32R_PLDSIO /* INT#1: SIO0 Receive on PLD */ - irq_desc[PLD_IRQ_SIO0_RCV].status = IRQ_DISABLED; - irq_desc[PLD_IRQ_SIO0_RCV].chip = &opsput_pld_irq_type; - irq_desc[PLD_IRQ_SIO0_RCV].action = 0; - irq_desc[PLD_IRQ_SIO0_RCV].depth = 1; /* disable nested irq */ + set_irq_chip(PLD_IRQ_SIO0_RCV, &opsput_pld_irq_type); pld_icu_data[irq2pldirq(PLD_IRQ_SIO0_RCV)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD03; disable_opsput_pld_irq(PLD_IRQ_SIO0_RCV); /* INT#1: SIO0 Send on PLD */ - irq_desc[PLD_IRQ_SIO0_SND].status = IRQ_DISABLED; - irq_desc[PLD_IRQ_SIO0_SND].chip = &opsput_pld_irq_type; - irq_desc[PLD_IRQ_SIO0_SND].action = 0; - irq_desc[PLD_IRQ_SIO0_SND].depth = 1; /* disable nested irq */ + set_irq_chip(PLD_IRQ_SIO0_SND, &opsput_pld_irq_type); pld_icu_data[irq2pldirq(PLD_IRQ_SIO0_SND)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD03; disable_opsput_pld_irq(PLD_IRQ_SIO0_SND); #endif /* CONFIG_SERIAL_M32R_PLDSIO */ /* INT#1: CFC IREQ on PLD */ - irq_desc[PLD_IRQ_CFIREQ].status = IRQ_DISABLED; - irq_desc[PLD_IRQ_CFIREQ].chip = &opsput_pld_irq_type; - irq_desc[PLD_IRQ_CFIREQ].action = 0; - irq_desc[PLD_IRQ_CFIREQ].depth = 1; /* disable nested irq */ + set_irq_chip(PLD_IRQ_CFIREQ, &opsput_pld_irq_type); pld_icu_data[irq2pldirq(PLD_IRQ_CFIREQ)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD01; /* 'L' level sense */ disable_opsput_pld_irq(PLD_IRQ_CFIREQ); /* INT#1: CFC Insert on PLD */ - irq_desc[PLD_IRQ_CFC_INSERT].status = IRQ_DISABLED; - irq_desc[PLD_IRQ_CFC_INSERT].chip = &opsput_pld_irq_type; - irq_desc[PLD_IRQ_CFC_INSERT].action = 0; - irq_desc[PLD_IRQ_CFC_INSERT].depth = 1; /* disable nested irq */ + set_irq_chip(PLD_IRQ_CFC_INSERT, &opsput_pld_irq_type); pld_icu_data[irq2pldirq(PLD_IRQ_CFC_INSERT)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD00; /* 'L' edge sense */ disable_opsput_pld_irq(PLD_IRQ_CFC_INSERT); /* INT#1: CFC Eject on PLD */ - irq_desc[PLD_IRQ_CFC_EJECT].status = IRQ_DISABLED; - irq_desc[PLD_IRQ_CFC_EJECT].chip = &opsput_pld_irq_type; - irq_desc[PLD_IRQ_CFC_EJECT].action = 0; - irq_desc[PLD_IRQ_CFC_EJECT].depth = 1; /* disable nested irq */ + set_irq_chip(PLD_IRQ_CFC_EJECT, &opsput_pld_irq_type); pld_icu_data[irq2pldirq(PLD_IRQ_CFC_EJECT)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD02; /* 'H' edge sense */ disable_opsput_pld_irq(PLD_IRQ_CFC_EJECT); @@ -415,10 +379,7 @@ void __init init_IRQ(void) #if defined(CONFIG_USB) outw(USBCR_OTGS, USBCR); /* USBCR: non-OTG */ - irq_desc[OPSPUT_LCD_IRQ_USB_INT1].status = IRQ_DISABLED; - irq_desc[OPSPUT_LCD_IRQ_USB_INT1].chip = &opsput_lcdpld_irq_type; - irq_desc[OPSPUT_LCD_IRQ_USB_INT1].action = 0; - irq_desc[OPSPUT_LCD_IRQ_USB_INT1].depth = 1; + set_irq_chip(OPSPUT_LCD_IRQ_USB_INT1, &opsput_lcdpld_irq_type); lcdpld_icu_data[irq2lcdpldirq(OPSPUT_LCD_IRQ_USB_INT1)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD01; /* "L" level sense */ disable_opsput_lcdpld_irq(OPSPUT_LCD_IRQ_USB_INT1); #endif @@ -433,10 +394,7 @@ void __init init_IRQ(void) /* * INT3# is used for AR */ - irq_desc[M32R_IRQ_INT3].status = IRQ_DISABLED; - irq_desc[M32R_IRQ_INT3].chip = &opsput_irq_type; - irq_desc[M32R_IRQ_INT3].action = 0; - irq_desc[M32R_IRQ_INT3].depth = 1; + set_irq_chip(M32R_IRQ_INT3, &opsput_irq_type); icu_data[M32R_IRQ_INT3].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10; disable_opsput_irq(M32R_IRQ_INT3); #endif /* CONFIG_VIDEO_M32R_AR */ -- cgit v1.1 From 883c0ccde1e12e7721966626983d61ccdbd0ae99 Mon Sep 17 00:00:00 2001 From: Thomas Gleixner Date: Wed, 19 Jan 2011 18:48:15 +0100 Subject: m32r: Convert opsput irq chip Convert the irq chips to the new functions and use proper flow handlers. handle_level_irq is appropriate. Signed-off-by: Thomas Gleixner Cc: Hirokazu Takata Cc: Paul Mundt --- arch/m32r/platforms/opsput/setup.c | 58 ++++++++++++++++++-------------------- 1 file changed, 27 insertions(+), 31 deletions(-) (limited to 'arch/m32r/platforms/opsput/setup.c') diff --git a/arch/m32r/platforms/opsput/setup.c b/arch/m32r/platforms/opsput/setup.c index a16a7fe..8c0907d 100644 --- a/arch/m32r/platforms/opsput/setup.c +++ b/arch/m32r/platforms/opsput/setup.c @@ -46,39 +46,30 @@ static void enable_opsput_irq(unsigned int irq) outl(data, port); } -static void mask_and_ack_opsput(unsigned int irq) +static void mask_opsput(struct irq_data *data) { - disable_opsput_irq(irq); + disable_opsput_irq(data->irq); } -static void end_opsput_irq(unsigned int irq) +static void unmask_opsput(struct irq_data *data) { - enable_opsput_irq(irq); + enable_opsput_irq(data->irq); } -static unsigned int startup_opsput_irq(unsigned int irq) -{ - enable_opsput_irq(irq); - return (0); -} - -static void shutdown_opsput_irq(unsigned int irq) +static void shutdown_opsput(struct irq_data *data) { unsigned long port; - port = irq2port(irq); + port = irq2port(data->irq); outl(M32R_ICUCR_ILEVEL7, port); } static struct irq_chip opsput_irq_type = { - .name = "OPSPUT-IRQ", - .startup = startup_opsput_irq, - .shutdown = shutdown_opsput_irq, - .enable = enable_opsput_irq, - .disable = disable_opsput_irq, - .ack = mask_and_ack_opsput, - .end = end_opsput_irq + .name = "OPSPUT-IRQ", + .irq_shutdown = shutdown_opsput, + .irq_mask = mask_opsput, + .irq_unmask = unmask_opsput, }; /* @@ -100,7 +91,6 @@ static void disable_opsput_pld_irq(unsigned int irq) unsigned int pldirq; pldirq = irq2pldirq(irq); -// disable_opsput_irq(M32R_IRQ_INT1); port = pldirq2port(pldirq); data = pld_icu_data[pldirq].icucr|PLD_ICUCR_ILEVEL7; outw(data, port); @@ -112,7 +102,6 @@ static void enable_opsput_pld_irq(unsigned int irq) unsigned int pldirq; pldirq = irq2pldirq(irq); -// enable_opsput_irq(M32R_IRQ_INT1); port = pldirq2port(pldirq); data = pld_icu_data[pldirq].icucr|PLD_ICUCR_IEN|PLD_ICUCR_ILEVEL6; outw(data, port); @@ -127,7 +116,7 @@ static void mask_and_ack_opsput_pld(unsigned int irq) static void end_opsput_pld_irq(unsigned int irq) { enable_opsput_pld_irq(irq); - end_opsput_irq(M32R_IRQ_INT1); + enable_opsput_irq(M32R_IRQ_INT1); } static unsigned int startup_opsput_pld_irq(unsigned int irq) @@ -197,7 +186,7 @@ static void mask_and_ack_opsput_lanpld(unsigned int irq) static void end_opsput_lanpld_irq(unsigned int irq) { enable_opsput_lanpld_irq(irq); - end_opsput_irq(M32R_IRQ_INT0); + enable_opsput_irq(M32R_IRQ_INT0); } static unsigned int startup_opsput_lanpld_irq(unsigned int irq) @@ -266,7 +255,7 @@ static void mask_and_ack_opsput_lcdpld(unsigned int irq) static void end_opsput_lcdpld_irq(unsigned int irq) { enable_opsput_lcdpld_irq(irq); - end_opsput_irq(M32R_IRQ_INT2); + enable_opsput_irq(M32R_IRQ_INT2); } static unsigned int startup_opsput_lcdpld_irq(unsigned int irq) @@ -306,32 +295,38 @@ void __init init_IRQ(void) #endif /* CONFIG_SMC91X */ /* MFT2 : system timer */ - set_irq_chip(M32R_IRQ_MFT2, &opsput_irq_type); + set_irq_chip_and_handler(M32R_IRQ_MFT2, &opsput_irq_type, + handle_level_irq); icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN; disable_opsput_irq(M32R_IRQ_MFT2); /* SIO0 : receive */ - set_irq_chip(M32R_IRQ_SIO0_R, &opsput_irq_type); + set_irq_chip_and_handler(M32R_IRQ_SIO0_R, &opsput_irq_type, + handle_level_irq); icu_data[M32R_IRQ_SIO0_R].icucr = 0; disable_opsput_irq(M32R_IRQ_SIO0_R); /* SIO0 : send */ - set_irq_chip(M32R_IRQ_SIO0_S, &opsput_irq_type); + set_irq_chip_and_handler(M32R_IRQ_SIO0_S, &opsput_irq_type, + handle_level_irq); icu_data[M32R_IRQ_SIO0_S].icucr = 0; disable_opsput_irq(M32R_IRQ_SIO0_S); /* SIO1 : receive */ - set_irq_chip(M32R_IRQ_SIO1_R, &opsput_irq_type); + set_irq_chip_and_handler(M32R_IRQ_SIO1_R, &opsput_irq_type, + handle_level_irq); icu_data[M32R_IRQ_SIO1_R].icucr = 0; disable_opsput_irq(M32R_IRQ_SIO1_R); /* SIO1 : send */ - set_irq_chip(M32R_IRQ_SIO1_S, &opsput_irq_type); + set_irq_chip_and_handler(M32R_IRQ_SIO1_S, &opsput_irq_type, + handle_level_irq); icu_data[M32R_IRQ_SIO1_S].icucr = 0; disable_opsput_irq(M32R_IRQ_SIO1_S); /* DMA1 : */ - set_irq_chip(M32R_IRQ_DMA1, &opsput_irq_type); + set_irq_chip_and_handler(M32R_IRQ_DMA1, &opsput_irq_type, + handle_level_irq); icu_data[M32R_IRQ_DMA1].icucr = 0; disable_opsput_irq(M32R_IRQ_DMA1); @@ -394,7 +389,8 @@ void __init init_IRQ(void) /* * INT3# is used for AR */ - set_irq_chip(M32R_IRQ_INT3, &opsput_irq_type); + set_irq_chip_and_handler(M32R_IRQ_INT3, &opsput_irq_type, + handle_level_irq); icu_data[M32R_IRQ_INT3].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10; disable_opsput_irq(M32R_IRQ_INT3); #endif /* CONFIG_VIDEO_M32R_AR */ -- cgit v1.1 From 22cbc9384a495f2e6eb0d0fda91692431a28468e Mon Sep 17 00:00:00 2001 From: Thomas Gleixner Date: Wed, 19 Jan 2011 18:55:09 +0100 Subject: m32r: Convert opsput pld irq chip Convert the irq chips to the new functions and use proper flow handlers. handle_level_irq is appropriate. Signed-off-by: Thomas Gleixner Cc: Hirokazu Takata Cc: Paul Mundt --- arch/m32r/platforms/opsput/setup.c | 46 +++++++++++++++++--------------------- 1 file changed, 20 insertions(+), 26 deletions(-) (limited to 'arch/m32r/platforms/opsput/setup.c') diff --git a/arch/m32r/platforms/opsput/setup.c b/arch/m32r/platforms/opsput/setup.c index 8c0907d..00eb3b8 100644 --- a/arch/m32r/platforms/opsput/setup.c +++ b/arch/m32r/platforms/opsput/setup.c @@ -107,44 +107,33 @@ static void enable_opsput_pld_irq(unsigned int irq) outw(data, port); } -static void mask_and_ack_opsput_pld(unsigned int irq) +static void mask_opsput_pld(struct irq_data *data) { - disable_opsput_pld_irq(irq); -// mask_and_ack_opsput(M32R_IRQ_INT1); + disable_opsput_pld_irq(data->irq); } -static void end_opsput_pld_irq(unsigned int irq) +static void unmask_opsput_pld(struct irq_data *data) { - enable_opsput_pld_irq(irq); + enable_opsput_pld_irq(data->irq); enable_opsput_irq(M32R_IRQ_INT1); } -static unsigned int startup_opsput_pld_irq(unsigned int irq) -{ - enable_opsput_pld_irq(irq); - return (0); -} - -static void shutdown_opsput_pld_irq(unsigned int irq) +static void shutdown_opsput_pld(struct irq_data *data) { unsigned long port; unsigned int pldirq; - pldirq = irq2pldirq(irq); -// shutdown_opsput_irq(M32R_IRQ_INT1); + pldirq = irq2pldirq(data->irq); port = pldirq2port(pldirq); outw(PLD_ICUCR_ILEVEL7, port); } static struct irq_chip opsput_pld_irq_type = { - .name = "OPSPUT-PLD-IRQ", - .startup = startup_opsput_pld_irq, - .shutdown = shutdown_opsput_pld_irq, - .enable = enable_opsput_pld_irq, - .disable = disable_opsput_pld_irq, - .ack = mask_and_ack_opsput_pld, - .end = end_opsput_pld_irq + .name = "OPSPUT-PLD-IRQ", + .irq_shutdown = shutdown_opsput_pld, + .irq_mask = mask_opsput_pld, + .irq_unmask = unmask_opsput_pld, }; /* @@ -332,28 +321,33 @@ void __init init_IRQ(void) #ifdef CONFIG_SERIAL_M32R_PLDSIO /* INT#1: SIO0 Receive on PLD */ - set_irq_chip(PLD_IRQ_SIO0_RCV, &opsput_pld_irq_type); + set_irq_chip_and_handler(PLD_IRQ_SIO0_RCV, &opsput_pld_irq_type, + handle_level_irq); pld_icu_data[irq2pldirq(PLD_IRQ_SIO0_RCV)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD03; disable_opsput_pld_irq(PLD_IRQ_SIO0_RCV); /* INT#1: SIO0 Send on PLD */ - set_irq_chip(PLD_IRQ_SIO0_SND, &opsput_pld_irq_type); + set_irq_chip_and_handler(PLD_IRQ_SIO0_SND, &opsput_pld_irq_type, + handle_level_irq); pld_icu_data[irq2pldirq(PLD_IRQ_SIO0_SND)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD03; disable_opsput_pld_irq(PLD_IRQ_SIO0_SND); #endif /* CONFIG_SERIAL_M32R_PLDSIO */ /* INT#1: CFC IREQ on PLD */ - set_irq_chip(PLD_IRQ_CFIREQ, &opsput_pld_irq_type); + set_irq_chip_and_handler(PLD_IRQ_CFIREQ, &opsput_pld_irq_type, + handle_level_irq); pld_icu_data[irq2pldirq(PLD_IRQ_CFIREQ)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD01; /* 'L' level sense */ disable_opsput_pld_irq(PLD_IRQ_CFIREQ); /* INT#1: CFC Insert on PLD */ - set_irq_chip(PLD_IRQ_CFC_INSERT, &opsput_pld_irq_type); + set_irq_chip_and_handler(PLD_IRQ_CFC_INSERT, &opsput_pld_irq_type, + handle_level_irq); pld_icu_data[irq2pldirq(PLD_IRQ_CFC_INSERT)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD00; /* 'L' edge sense */ disable_opsput_pld_irq(PLD_IRQ_CFC_INSERT); /* INT#1: CFC Eject on PLD */ - set_irq_chip(PLD_IRQ_CFC_EJECT, &opsput_pld_irq_type); + set_irq_chip_and_handler(PLD_IRQ_CFC_EJECT, &opsput_pld_irq_type, + handle_level_irq); pld_icu_data[irq2pldirq(PLD_IRQ_CFC_EJECT)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD02; /* 'H' edge sense */ disable_opsput_pld_irq(PLD_IRQ_CFC_EJECT); -- cgit v1.1 From 1899a493b991cf9ea7a57d15b64588632fe32cf0 Mon Sep 17 00:00:00 2001 From: Thomas Gleixner Date: Wed, 19 Jan 2011 18:58:45 +0100 Subject: m32r: Convert opsput lanpld irq chip Convert the irq chips to the new functions and use proper flow handlers. handle_level_irq is appropriate. Signed-off-by: Thomas Gleixner Cc: Hirokazu Takata Cc: Paul Mundt --- arch/m32r/platforms/opsput/setup.c | 32 ++++++++++++-------------------- 1 file changed, 12 insertions(+), 20 deletions(-) (limited to 'arch/m32r/platforms/opsput/setup.c') diff --git a/arch/m32r/platforms/opsput/setup.c b/arch/m32r/platforms/opsput/setup.c index 00eb3b8..7648c1d 100644 --- a/arch/m32r/platforms/opsput/setup.c +++ b/arch/m32r/platforms/opsput/setup.c @@ -167,42 +167,33 @@ static void enable_opsput_lanpld_irq(unsigned int irq) outw(data, port); } -static void mask_and_ack_opsput_lanpld(unsigned int irq) +static void mask_opsput_lanpld(struct irq_data *data) { - disable_opsput_lanpld_irq(irq); + disable_opsput_lanpld_irq(data->irq); } -static void end_opsput_lanpld_irq(unsigned int irq) +static void unmask_opsput_lanpld(struct irq_data *data) { - enable_opsput_lanpld_irq(irq); + enable_opsput_lanpld_irq(data->irq); enable_opsput_irq(M32R_IRQ_INT0); } -static unsigned int startup_opsput_lanpld_irq(unsigned int irq) -{ - enable_opsput_lanpld_irq(irq); - return (0); -} - -static void shutdown_opsput_lanpld_irq(unsigned int irq) +static void shutdown_opsput_lanpld(struct irq_data *data) { unsigned long port; unsigned int pldirq; - pldirq = irq2lanpldirq(irq); + pldirq = irq2lanpldirq(data->irq); port = lanpldirq2port(pldirq); outw(PLD_ICUCR_ILEVEL7, port); } static struct irq_chip opsput_lanpld_irq_type = { - .name = "OPSPUT-PLD-LAN-IRQ", - .startup = startup_opsput_lanpld_irq, - .shutdown = shutdown_opsput_lanpld_irq, - .enable = enable_opsput_lanpld_irq, - .disable = disable_opsput_lanpld_irq, - .ack = mask_and_ack_opsput_lanpld, - .end = end_opsput_lanpld_irq + .name = "OPSPUT-PLD-LAN-IRQ", + .irq_shutdown = shutdown_opsput_lanpld, + .irq_mask = mask_opsput_lanpld, + .irq_unmask = unmask_opsput_lanpld, }; /* @@ -278,7 +269,8 @@ void __init init_IRQ(void) { #if defined(CONFIG_SMC91X) /* INT#0: LAN controller on OPSPUT-LAN (SMC91C111)*/ - set_irq_chip(OPSPUT_LAN_IRQ_LAN, &opsput_lanpld_irq_type); + set_irq_chip_and_handler(OPSPUT_LAN_IRQ_LAN, &opsput_lanpld_irq_type, + handle_level_irq); lanpld_icu_data[irq2lanpldirq(OPSPUT_LAN_IRQ_LAN)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD02; /* "H" edge sense */ disable_opsput_lanpld_irq(OPSPUT_LAN_IRQ_LAN); #endif /* CONFIG_SMC91X */ -- cgit v1.1 From 9b141fa649b160c6a0854a79fe2cd741c5c99e80 Mon Sep 17 00:00:00 2001 From: Thomas Gleixner Date: Wed, 19 Jan 2011 19:01:23 +0100 Subject: m32r: Convert opsput_lcdpld irq chip Convert the irq chips to the new functions and use proper flow handlers. handle_level_irq is appropriate. Signed-off-by: Thomas Gleixner Cc: Hirokazu Takata Cc: Paul Mundt --- arch/m32r/platforms/opsput/setup.c | 42 +++++++++++++++----------------------- 1 file changed, 16 insertions(+), 26 deletions(-) (limited to 'arch/m32r/platforms/opsput/setup.c') diff --git a/arch/m32r/platforms/opsput/setup.c b/arch/m32r/platforms/opsput/setup.c index 7648c1d..1273154 100644 --- a/arch/m32r/platforms/opsput/setup.c +++ b/arch/m32r/platforms/opsput/setup.c @@ -227,42 +227,32 @@ static void enable_opsput_lcdpld_irq(unsigned int irq) outw(data, port); } -static void mask_and_ack_opsput_lcdpld(unsigned int irq) +static void mask_opsput_lcdpld(struct irq_data *data) { - disable_opsput_lcdpld_irq(irq); + disable_opsput_lcdpld_irq(data->irq); } -static void end_opsput_lcdpld_irq(unsigned int irq) +static void unmask_opsput_lcdpld(struct irq_data *data) { - enable_opsput_lcdpld_irq(irq); + enable_opsput_lcdpld_irq(data->irq); enable_opsput_irq(M32R_IRQ_INT2); } -static unsigned int startup_opsput_lcdpld_irq(unsigned int irq) -{ - enable_opsput_lcdpld_irq(irq); - return (0); -} - -static void shutdown_opsput_lcdpld_irq(unsigned int irq) +static void shutdown_opsput_lcdpld(struct irq_data *data) { unsigned long port; unsigned int pldirq; - pldirq = irq2lcdpldirq(irq); + pldirq = irq2lcdpldirq(data->irq); port = lcdpldirq2port(pldirq); outw(PLD_ICUCR_ILEVEL7, port); } -static struct irq_chip opsput_lcdpld_irq_type = -{ - "OPSPUT-PLD-LCD-IRQ", - startup_opsput_lcdpld_irq, - shutdown_opsput_lcdpld_irq, - enable_opsput_lcdpld_irq, - disable_opsput_lcdpld_irq, - mask_and_ack_opsput_lcdpld, - end_opsput_lcdpld_irq +static struct irq_chip opsput_lcdpld_irq_type = { + .name = "OPSPUT-PLD-LCD-IRQ", + .irq_shutdown = shutdown_opsput_lcdpld, + .irq_mask = mask_opsput_lcdpld, + .irq_unmask = unmask_opsput_lcdpld, }; void __init init_IRQ(void) @@ -358,11 +348,11 @@ void __init init_IRQ(void) enable_opsput_irq(M32R_IRQ_INT1); #if defined(CONFIG_USB) - outw(USBCR_OTGS, USBCR); /* USBCR: non-OTG */ - - set_irq_chip(OPSPUT_LCD_IRQ_USB_INT1, &opsput_lcdpld_irq_type); - lcdpld_icu_data[irq2lcdpldirq(OPSPUT_LCD_IRQ_USB_INT1)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD01; /* "L" level sense */ - disable_opsput_lcdpld_irq(OPSPUT_LCD_IRQ_USB_INT1); + outw(USBCR_OTGS, USBCR); /* USBCR: non-OTG */ + set_irq_chip_and_handler(OPSPUT_LCD_IRQ_USB_INT1, + &opsput_lcdpld_irq_type, handle_level_irq); + lcdpld_icu_data[irq2lcdpldirq(OPSPUT_LCD_IRQ_USB_INT1)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD01; /* "L" level sense */ + disable_opsput_lcdpld_irq(OPSPUT_LCD_IRQ_USB_INT1); #endif /* * INT2# is used for BAT, USB, AUDIO -- cgit v1.1