From 3c835670ab5f72a4ea2d0db232b1acc07924f186 Mon Sep 17 00:00:00 2001 From: David Howells Date: Wed, 28 Nov 2007 16:22:05 -0800 Subject: FRV: arrange things such that BRA can reach from the trap table Arrange the sections in the FRV arch so that a BRA instruction with a 16-bit displacement can always reach from the trap table to entry.S, tlb-miss.S and break.S. The problem otherwise is that the linker can insert sufficient code between the slots in the trap table and the targets of the branch instructions in those slots that the displacement field in the instruction isn't sufficiently large. This is because the branch targets were in the .text section along with most of the other code in the kernel. Signed-off-by: David Howells Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- arch/frv/kernel/vmlinux.lds.S | 27 +++++++++++++++------------ 1 file changed, 15 insertions(+), 12 deletions(-) (limited to 'arch/frv/kernel/vmlinux.lds.S') diff --git a/arch/frv/kernel/vmlinux.lds.S b/arch/frv/kernel/vmlinux.lds.S index 3b71e0c..a17a81d 100644 --- a/arch/frv/kernel/vmlinux.lds.S +++ b/arch/frv/kernel/vmlinux.lds.S @@ -76,6 +76,12 @@ SECTIONS *(.data.init_task) } + . = ALIGN(4096); + .data.page_aligned : { *(.data.idt) } + + . = ALIGN(L1_CACHE_BYTES); + .data.cacheline_aligned : { *(.data.cacheline_aligned) } + .trap : { /* trap table management - read entry-table.S before modifying */ . = ALIGN(8192); @@ -86,28 +92,25 @@ SECTIONS *(.trap.break) } - . = ALIGN(4096); - .data.page_aligned : { *(.data.idt) } - - . = ALIGN(L1_CACHE_BYTES); - .data.cacheline_aligned : { *(.data.cacheline_aligned) } - /* Text and read-only data */ . = ALIGN(4); _text = .; _stext = .; .text : { - *( - .text.start .text.* + *(.text.start) + *(.text.entry) + *(.text.break) + *(.text.tlbmiss) + TEXT_TEXT + SCHED_TEXT + LOCK_TEXT #ifdef CONFIG_DEBUG_INFO + *( .init.text .exit.text .exitcall.exit -#endif ) - TEXT_TEXT - SCHED_TEXT - LOCK_TEXT +#endif *(.fixup) *(.gnu.warning) *(.exitcall.exit) -- cgit v1.1