From e269a869417cd4053b37da1b19186902d3cbf63b Mon Sep 17 00:00:00 2001 From: Jesper Nilsson Date: Wed, 15 Jan 2014 14:42:37 +0100 Subject: Drop code for CRISv10 CPU simulator That simulator is dead and redundant. Signed-off-by: Jesper Nilsson --- arch/cris/arch-v10/kernel/Makefile | 1 - arch/cris/arch-v10/kernel/debugport.c | 7 --- arch/cris/arch-v10/kernel/entry.S | 4 +- arch/cris/arch-v10/kernel/head.S | 5 -- arch/cris/arch-v10/kernel/irq.c | 18 ++----- arch/cris/arch-v10/kernel/process.c | 5 +- arch/cris/arch-v10/kernel/time.c | 92 +++++++++++++++-------------------- arch/cris/arch-v10/lib/dram_init.S | 40 +++++++-------- 8 files changed, 65 insertions(+), 107 deletions(-) (limited to 'arch/cris/arch-v10') diff --git a/arch/cris/arch-v10/kernel/Makefile b/arch/cris/arch-v10/kernel/Makefile index dcfec41..4841e82 100644 --- a/arch/cris/arch-v10/kernel/Makefile +++ b/arch/cris/arch-v10/kernel/Makefile @@ -1,4 +1,3 @@ -# $Id: Makefile,v 1.6 2004/12/13 12:21:51 starvik Exp $ # # Makefile for the linux kernel. # diff --git a/arch/cris/arch-v10/kernel/debugport.c b/arch/cris/arch-v10/kernel/debugport.c index f932c85..7d307cc 100644 --- a/arch/cris/arch-v10/kernel/debugport.c +++ b/arch/cris/arch-v10/kernel/debugport.c @@ -19,7 +19,6 @@ #include #include #include -#include /* Get SIMCOUT. */ extern void reset_watchdog(void); @@ -318,12 +317,6 @@ console_write(struct console *co, const char *buf, unsigned int len) if (!port) return; -#ifdef CONFIG_SVINTO_SIM - /* no use to simulate the serial debug output */ - SIMCOUT(buf, len); - return; -#endif - console_write_direct(co, buf, len); } diff --git a/arch/cris/arch-v10/kernel/entry.S b/arch/cris/arch-v10/kernel/entry.S index def0a53..81570fc 100644 --- a/arch/cris/arch-v10/kernel/entry.S +++ b/arch/cris/arch-v10/kernel/entry.S @@ -457,7 +457,7 @@ IRQ1_interrupt: ba _Rexit ; Return the standard way nop wdog: -#if defined(CONFIG_ETRAX_WATCHDOG) && !defined(CONFIG_SVINTO_SIM) +#if defined(CONFIG_ETRAX_WATCHDOG) ;; Check if we're waiting for reset to happen, as signalled by ;; hard_reset_now setting cause_of_death to a magic value. If so, just ;; get stuck until reset happens. @@ -523,7 +523,7 @@ _watchdogmsg: .ascii "Oops: bitten by watchdog\n\0" .previous -#endif /* CONFIG_ETRAX_WATCHDOG and not CONFIG_SVINTO_SIM */ +#endif /* CONFIG_ETRAX_WATCHDOG */ spurious_interrupt: di diff --git a/arch/cris/arch-v10/kernel/head.S b/arch/cris/arch-v10/kernel/head.S index 137bf52..4a146e1 100644 --- a/arch/cris/arch-v10/kernel/head.S +++ b/arch/cris/arch-v10/kernel/head.S @@ -168,13 +168,11 @@ _inflash: #endif ;; Set up waitstates etc according to kernel configuration. -#ifndef CONFIG_SVINTO_SIM move.d CONFIG_ETRAX_DEF_R_WAITSTATES, $r0 move.d $r0, [R_WAITSTATES] move.d CONFIG_ETRAX_DEF_R_BUS_CONFIG, $r0 move.d $r0, [R_BUS_CONFIG] -#endif ;; We need to initialze DRAM registers before we start using the DRAM @@ -466,7 +464,6 @@ no_command_line: move.d $r0,[genconfig_shadow] ; init a shadow register of R_GEN_CONFIG -#ifndef CONFIG_SVINTO_SIM move.d $r0,[R_GEN_CONFIG] #if 0 @@ -701,8 +698,6 @@ no_command_line: move.b $r0,[R_SERIAL3_TR_CTRL] #endif -#endif /* CONFIG_SVINTO_SIM */ - jump start_kernel ; jump into the C-function start_kernel in init/main.c .data diff --git a/arch/cris/arch-v10/kernel/irq.c b/arch/cris/arch-v10/kernel/irq.c index ba0e596..09cae80 100644 --- a/arch/cris/arch-v10/kernel/irq.c +++ b/arch/cris/arch-v10/kernel/irq.c @@ -5,7 +5,7 @@ * * Authors: Bjorn Wesen (bjornw@axis.com) * - * This file contains the interrupt vectors and some + * This file contains the interrupt vectors and some * helper functions * */ @@ -182,19 +182,14 @@ void do_multiple_IRQ(struct pt_regs* regs) setting the irq vector table. */ -void __init -init_IRQ(void) +void __init init_IRQ(void) { int i; /* clear all interrupt masks */ - -#ifndef CONFIG_SVINTO_SIM *R_IRQ_MASK0_CLR = 0xffffffff; *R_IRQ_MASK1_CLR = 0xffffffff; *R_IRQ_MASK2_CLR = 0xffffffff; -#endif - *R_VECT_MASK_CLR = 0xffffffff; for (i = 0; i < 256; i++) @@ -211,25 +206,20 @@ init_IRQ(void) executed by the associated break handler, rather than just a jump address. therefore we need to setup a default breakpoint handler for all breakpoints */ - for (i = 0; i < 16; i++) set_break_vector(i, do_sigtrap); - - /* except IRQ 15 which is the multiple-IRQ handler on Etrax100 */ + /* except IRQ 15 which is the multiple-IRQ handler on Etrax100 */ set_int_vector(15, multiple_interrupt); - - /* 0 and 1 which are special breakpoint/NMI traps */ + /* 0 and 1 which are special breakpoint/NMI traps */ set_int_vector(0, hwbreakpoint); set_int_vector(1, IRQ1_interrupt); /* and irq 14 which is the mmu bus fault handler */ - set_int_vector(14, mmu_bus_fault); /* setup the system-call trap, which is reached by BREAK 13 */ - set_break_vector(13, system_call); /* setup a breakpoint handler for debugging used for both user and diff --git a/arch/cris/arch-v10/kernel/process.c b/arch/cris/arch-v10/kernel/process.c index 753e9a0..c20e4e8 100644 --- a/arch/cris/arch-v10/kernel/process.c +++ b/arch/cris/arch-v10/kernel/process.c @@ -14,7 +14,6 @@ #include #include #include -#include #include #include #include @@ -56,14 +55,14 @@ void hard_reset_now (void) * code to know about it than the watchdog handler in entry.S and * this code, implementing hard reset through the watchdog. */ -#if defined(CONFIG_ETRAX_WATCHDOG) && !defined(CONFIG_SVINTO_SIM) +#if defined(CONFIG_ETRAX_WATCHDOG) extern int cause_of_death; #endif printk("*** HARD RESET ***\n"); local_irq_disable(); -#if defined(CONFIG_ETRAX_WATCHDOG) && !defined(CONFIG_SVINTO_SIM) +#if defined(CONFIG_ETRAX_WATCHDOG) cause_of_death = 0xbedead; #else /* Since we dont plan to keep on resetting the watchdog, diff --git a/arch/cris/arch-v10/kernel/time.c b/arch/cris/arch-v10/kernel/time.c index e6a7227..b5eb5cd 100644 --- a/arch/cris/arch-v10/kernel/time.c +++ b/arch/cris/arch-v10/kernel/time.c @@ -14,7 +14,6 @@ #include #include #include -#include #include #include #include @@ -34,7 +33,7 @@ unsigned long get_ns_in_jiffie(void) local_irq_save(flags); timer_count = *R_TIMER0_DATA; - presc_count = *R_TIM_PRESC_STATUS; + presc_count = *R_TIM_PRESC_STATUS; /* presc_count might be wrapped */ t1 = *R_TIMER0_DATA; @@ -50,7 +49,7 @@ unsigned long get_ns_in_jiffie(void) presc_count = PRESCALE_VALUE - presc_count - PRESCALE_VALUE/2; } - ns = ( (TIMER0_DIV - timer_count) * ((1000000000/HZ)/TIMER0_DIV )) + + ns = ( (TIMER0_DIV - timer_count) * ((1000000000/HZ)/TIMER0_DIV )) + ( (presc_count) * (1000000000/PRESCALE_FREQ)); return ns; } @@ -80,7 +79,7 @@ static u32 cris_v10_gettimeoffset(void) * by the R_WATCHDOG register. The R_WATCHDOG register contains an enable bit * and a 3-bit key value. The effect of writing to the R_WATCHDOG register is * described in the table below: - * + * * Watchdog Value written: * state: To enable: To key: Operation: * -------- ---------- ------- ---------- @@ -89,15 +88,15 @@ static u32 cris_v10_gettimeoffset(void) * started 0 ~key Stop watchdog * started 1 ~key Restart watchdog with key = ~key. * started X new_key_val Change key to new_key_val. - * + * * Note: '~' is the bitwise NOT operator. - * + * */ /* right now, starting the watchdog is the same as resetting it */ #define start_watchdog reset_watchdog -#if defined(CONFIG_ETRAX_WATCHDOG) && !defined(CONFIG_SVINTO_SIM) +#ifdef CONFIG_ETRAX_WATCHDOG static int watchdog_key = 0; /* arbitrary number */ #endif @@ -107,10 +106,9 @@ static int watchdog_key = 0; /* arbitrary number */ #define WATCHDOG_MIN_FREE_PAGES 8 -void -reset_watchdog(void) +void reset_watchdog(void) { -#if defined(CONFIG_ETRAX_WATCHDOG) && !defined(CONFIG_SVINTO_SIM) +#if defined(CONFIG_ETRAX_WATCHDOG) /* only keep watchdog happy as long as we have memory left! */ if(nr_free_pages() > WATCHDOG_MIN_FREE_PAGES) { /* reset the watchdog with the inverse of the old key */ @@ -123,28 +121,23 @@ reset_watchdog(void) /* stop the watchdog - we still need the correct key */ -void -stop_watchdog(void) +void stop_watchdog(void) { -#if defined(CONFIG_ETRAX_WATCHDOG) && !defined(CONFIG_SVINTO_SIM) +#ifdef CONFIG_ETRAX_WATCHDOG watchdog_key ^= 0x7; /* invert key, which is 3 bits */ *R_WATCHDOG = IO_FIELD(R_WATCHDOG, key, watchdog_key) | IO_STATE(R_WATCHDOG, enable, stop); -#endif +#endif } +extern void cris_do_profile(struct pt_regs *regs); + /* * timer_interrupt() needs to keep up the real-time clock, * as well as call the "xtime_update()" routine every clocktick */ - -//static unsigned short myjiff; /* used by our debug routine print_timestamp */ - -extern void cris_do_profile(struct pt_regs *regs); - -static inline irqreturn_t -timer_interrupt(int irq, void *dev_id) +static inline irqreturn_t timer_interrupt(int irq, void *dev_id) { struct pt_regs *regs = get_irq_regs(); /* acknowledge the timer irq */ @@ -160,20 +153,18 @@ timer_interrupt(int irq, void *dev_id) IO_STATE( R_TIMER_CTRL, tm0, run) | IO_STATE( R_TIMER_CTRL, clksel0, c6250kHz); #else - *R_TIMER_CTRL = r_timer_ctrl_shadow | - IO_STATE(R_TIMER_CTRL, i0, clr); + *R_TIMER_CTRL = r_timer_ctrl_shadow | IO_STATE(R_TIMER_CTRL, i0, clr); #endif /* reset watchdog otherwise it resets us! */ reset_watchdog(); - + /* Update statistics. */ update_process_times(user_mode(regs)); /* call the real timer interrupt handler */ - xtime_update(1); - + cris_do_profile(regs); /* Save profiling information */ return IRQ_HANDLED; } @@ -186,16 +177,15 @@ static struct irqaction irq2 = { .name = "timer", }; -void __init -time_init(void) -{ +void __init time_init(void) +{ arch_gettimeoffset = cris_v10_gettimeoffset; - /* probe for the RTC and read it if it exists - * Before the RTC can be probed the loops_per_usec variable needs - * to be initialized to make usleep work. A better value for - * loops_per_usec is calculated by the kernel later once the - * clock has started. + /* probe for the RTC and read it if it exists + * Before the RTC can be probed the loops_per_usec variable needs + * to be initialized to make usleep work. A better value for + * loops_per_usec is calculated by the kernel later once the + * clock has started. */ loops_per_usec = 50; @@ -206,7 +196,7 @@ time_init(void) * Remember that linux/timex.h contains #defines that rely on the * timer settings below (hz and divide factor) !!! */ - + #ifdef USE_CASCADE_TIMERS *R_TIMER_CTRL = IO_FIELD( R_TIMER_CTRL, timerdiv1, 0) | @@ -217,8 +207,8 @@ time_init(void) IO_STATE( R_TIMER_CTRL, i0, nop) | IO_STATE( R_TIMER_CTRL, tm0, stop_ld) | IO_STATE( R_TIMER_CTRL, clksel0, c6250kHz); - - *R_TIMER_CTRL = r_timer_ctrl_shadow = + + *R_TIMER_CTRL = r_timer_ctrl_shadow = IO_FIELD( R_TIMER_CTRL, timerdiv1, 0) | IO_FIELD( R_TIMER_CTRL, timerdiv0, 0) | IO_STATE( R_TIMER_CTRL, i1, nop) | @@ -228,18 +218,18 @@ time_init(void) IO_STATE( R_TIMER_CTRL, tm0, run) | IO_STATE( R_TIMER_CTRL, clksel0, c6250kHz); #else - *R_TIMER_CTRL = - IO_FIELD(R_TIMER_CTRL, timerdiv1, 192) | + *R_TIMER_CTRL = + IO_FIELD(R_TIMER_CTRL, timerdiv1, 192) | IO_FIELD(R_TIMER_CTRL, timerdiv0, TIMER0_DIV) | - IO_STATE(R_TIMER_CTRL, i1, nop) | + IO_STATE(R_TIMER_CTRL, i1, nop) | IO_STATE(R_TIMER_CTRL, tm1, stop_ld) | IO_STATE(R_TIMER_CTRL, clksel1, c19k2Hz) | IO_STATE(R_TIMER_CTRL, i0, nop) | IO_STATE(R_TIMER_CTRL, tm0, stop_ld) | IO_STATE(R_TIMER_CTRL, clksel0, flexible); - + *R_TIMER_CTRL = r_timer_ctrl_shadow = - IO_FIELD(R_TIMER_CTRL, timerdiv1, 192) | + IO_FIELD(R_TIMER_CTRL, timerdiv1, 192) | IO_FIELD(R_TIMER_CTRL, timerdiv0, TIMER0_DIV) | IO_STATE(R_TIMER_CTRL, i1, nop) | IO_STATE(R_TIMER_CTRL, tm1, run) | @@ -251,16 +241,14 @@ time_init(void) *R_TIMER_PRESCALE = PRESCALE_VALUE; #endif - *R_IRQ_MASK0_SET = - IO_STATE(R_IRQ_MASK0_SET, timer0, set); /* unmask the timer irq */ - - /* now actually register the timer irq handler that calls timer_interrupt() */ - + /* unmask the timer irq */ + *R_IRQ_MASK0_SET = IO_STATE(R_IRQ_MASK0_SET, timer0, set); + + /* now actually register the irq handler that calls timer_interrupt() */ setup_irq(2, &irq2); /* irq 2 is the timer0 irq in etrax */ /* enable watchdog if we should use one */ - -#if defined(CONFIG_ETRAX_WATCHDOG) && !defined(CONFIG_SVINTO_SIM) +#if defined(CONFIG_ETRAX_WATCHDOG) printk("Enabling watchdog...\n"); start_watchdog(); @@ -273,9 +261,7 @@ time_init(void) driver or infrastructure support yet. */ asm ("setf m"); - *R_IRQ_MASK0_SET = - IO_STATE(R_IRQ_MASK0_SET, watchdog_nmi, set); - *R_VECT_MASK_SET = - IO_STATE(R_VECT_MASK_SET, nmi, set); + *R_IRQ_MASK0_SET = IO_STATE(R_IRQ_MASK0_SET, watchdog_nmi, set); + *R_VECT_MASK_SET = IO_STATE(R_VECT_MASK_SET, nmi, set); #endif } diff --git a/arch/cris/arch-v10/lib/dram_init.S b/arch/cris/arch-v10/lib/dram_init.S index b9190ff..e541d3d 100644 --- a/arch/cris/arch-v10/lib/dram_init.S +++ b/arch/cris/arch-v10/lib/dram_init.S @@ -5,9 +5,7 @@ * Note: This file may not modify r9 because r9 is used to carry * information from the decompresser to the kernel * - * Copyright (C) 2000, 2001 Axis Communications AB - * - * Authors: Mikael Starvik (starvik@axis.com) + * Copyright (C) 2000-2012 Axis Communications AB * */ @@ -18,16 +16,15 @@ ;; WARNING! The registers r8 and r9 are used as parameters carrying - ;; information from the decompressor (if the kernel was compressed). + ;; information from the decompressor (if the kernel was compressed). ;; They should not be used in the code below. -#ifndef CONFIG_SVINTO_SIM move.d CONFIG_ETRAX_DEF_R_WAITSTATES, $r0 move.d $r0, [R_WAITSTATES] move.d CONFIG_ETRAX_DEF_R_BUS_CONFIG, $r0 move.d $r0, [R_BUS_CONFIG] - + #ifndef CONFIG_ETRAX_SDRAM move.d CONFIG_ETRAX_DEF_R_DRAM_CONFIG, $r0 move.d $r0, [R_DRAM_CONFIG] @@ -38,14 +35,14 @@ ;; Samsung SDRAMs seem to require to be initialized twice to work properly. moveq 2, $r6 _sdram_init: - + ; Refer to ETRAX 100LX Designers Reference for a description of SDRAM initialization - + ; Bank configuration move.d CONFIG_ETRAX_DEF_R_SDRAM_CONFIG, $r0 move.d $r0, [R_SDRAM_CONFIG] - ; Calculate value of mrs_data + ; Calculate value of mrs_data ; CAS latency = 2 && bus_width = 32 => 0x40 ; CAS latency = 3 && bus_width = 32 => 0x60 ; CAS latency = 2 && bus_width = 16 => 0x20 @@ -56,22 +53,22 @@ _sdram_init: and.d 0x00ff0000, $r2 bne _set_timing lsrq 16, $r2 - + move.d 0x40, $r2 ; Assume 32 bits and CAS latency = 2 move.d CONFIG_ETRAX_DEF_R_SDRAM_TIMING, $r1 move.d $r1, $r3 - and.d 0x03, $r1 ; Get CAS latency + and.d 0x03, $r1 ; Get CAS latency and.d 0x1000, $r3 ; 50 or 100 MHz? beq _speed_50 nop -_speed_100: +_speed_100: cmp.d 0x00, $r1 ; CAS latency = 2? beq _bw_check nop - or.d 0x20, $r2 ; CAS latency = 3 + or.d 0x20, $r2 ; CAS latency = 3 ba _bw_check nop -_speed_50: +_speed_50: cmp.d 0x01, $r1 ; CAS latency = 2? beq _bw_check nop @@ -86,19 +83,19 @@ _bw_check: ; Set timing parameters. Starts master clock _set_timing: move.d CONFIG_ETRAX_DEF_R_SDRAM_TIMING, $r1 - and.d 0x8000f9ff, $r1 ; Make sure mrs data and command is 0 + and.d 0x8000f9ff, $r1 ; Make sure mrs data and command is 0 or.d 0x80000000, $r1 ; Make sure sdram enable bit is set move.d $r1, $r5 or.d 0x0000c000, $r1 ; ref = disable lslq 16, $r2 ; mrs data starts at bit 16 - or.d $r2, $r1 - move.d $r1, [R_SDRAM_TIMING] - + or.d $r2, $r1 + move.d $r1, [R_SDRAM_TIMING] + ; Wait 200us move.d 10000, $r2 1: bne 1b subq 1, $r2 - + ; Issue initialization command sequence move.d _sdram_commands_start, $r2 and.d 0x000fffff, $r2 ; Make sure commands are read from flash @@ -144,7 +141,6 @@ _sdram_commands_start: .byte 2 ; refresh .byte 0 ; nop .byte 1 ; mrs - .byte 0 ; nop -_sdram_commands_end: -#endif + .byte 0 ; nop +_sdram_commands_end: #endif -- cgit v1.1