From 0e06b50dda5965e0f8a15b0be14b759ead54fd2a Mon Sep 17 00:00:00 2001
From: Mike Frysinger <vapier.adi@gmail.com>
Date: Thu, 14 Aug 2008 14:29:57 +0800
Subject: Blackfin arch: cleanup cache lock code

 - remove cheesy read_iloc() function
 - move invalidate_entire_icache function to lock.S
 - export proper prototypes for functions in lock.S
 - only build lock.S when BFIN_ICACHE_LOCK is enabled

Signed-off-by: Mike Frysinger <vapier.adi@gmail.com>
Signed-off-by: Bryan Wu <cooloney@kernel.org>
---
 arch/blackfin/kernel/setup.c       |  2 +-
 arch/blackfin/mach-common/Makefile |  3 ++-
 arch/blackfin/mach-common/lock.S   | 45 ++++++++++++++++++++++++++------------
 3 files changed, 34 insertions(+), 16 deletions(-)

(limited to 'arch/blackfin')

diff --git a/arch/blackfin/kernel/setup.c b/arch/blackfin/kernel/setup.c
index 936c06d..2ae84fe 100644
--- a/arch/blackfin/kernel/setup.c
+++ b/arch/blackfin/kernel/setup.c
@@ -1059,7 +1059,7 @@ static int show_cpuinfo(struct seq_file *m, void *v)
 		   dsup_banks, BFIN_DSUBBANKS, BFIN_DWAYS,
 		   BFIN_DLINES);
 #ifdef CONFIG_BFIN_ICACHE_LOCK
-	switch (read_iloc()) {
+	switch ((bfin_read_IMEM_CONTROL() >> 3) & WAYALL_L) {
 	case WAY0_L:
 		seq_printf(m, "Way0 Locked-Down\n");
 		break;
diff --git a/arch/blackfin/mach-common/Makefile b/arch/blackfin/mach-common/Makefile
index 862cd73..e6ed57c 100644
--- a/arch/blackfin/mach-common/Makefile
+++ b/arch/blackfin/mach-common/Makefile
@@ -4,8 +4,9 @@
 
 obj-y := \
 	cache.o entry.o head.o \
-	interrupt.o lock.o irqpanic.o arch_checks.o ints-priority.o
+	interrupt.o irqpanic.o arch_checks.o ints-priority.o
 
+obj-$(CONFIG_BFIN_ICACHE_LOCK) += lock.o
 obj-$(CONFIG_PM)          += pm.o dpmc_modes.o
 obj-$(CONFIG_CPU_FREQ)    += cpufreq.o
 obj-$(CONFIG_CPU_VOLTAGE) += dpmc.o
diff --git a/arch/blackfin/mach-common/lock.S b/arch/blackfin/mach-common/lock.S
index 30b887e..9daf012 100644
--- a/arch/blackfin/mach-common/lock.S
+++ b/arch/blackfin/mach-common/lock.S
@@ -28,13 +28,10 @@
  */
 
 #include <linux/linkage.h>
-#include <asm/cplb.h>
 #include <asm/blackfin.h>
 
 .text
 
-#ifdef CONFIG_BFIN_ICACHE_LOCK
-
 /* When you come here, it is assumed that
  * R0 - Which way to be locked
  */
@@ -189,18 +186,38 @@ ENTRY(_cache_lock)
 	RTS;
 ENDPROC(_cache_lock)
 
-#endif	/* BFIN_ICACHE_LOCK */
-
-/* Return the ILOC bits of IMEM_CONTROL
+/* Invalidate the Entire Instruction cache by
+ * disabling IMC bit
  */
+ENTRY(_invalidate_entire_icache)
+	[--SP] = ( R7:5);
 
-ENTRY(_read_iloc)
-	P1.H = HI(IMEM_CONTROL);
-	P1.L = LO(IMEM_CONTROL);
-	R1 = 0xF;
-	R0 = [P1];
-	R0 = R0 >> 3;
-	R0 = R0 & R1;
+	P0.L = LO(IMEM_CONTROL);
+	P0.H = HI(IMEM_CONTROL);
+	R7 = [P0];
+
+	/* Clear the IMC bit , All valid bits in the instruction
+	 * cache are set to the invalid state
+	 */
+	BITCLR(R7,IMC_P);
+	CLI R6;
+	SSYNC;		/* SSYNC required before invalidating cache. */
+	.align 8;
+	[P0] = R7;
+	SSYNC;
+	STI R6;
+
+	/* Configures the instruction cache agian */
+	R6 = (IMC | ENICPLB);
+	R7 = R7 | R6;
+
+	CLI R6;
+	SSYNC;		/* SSYNC required before writing to IMEM_CONTROL. */
+	.align 8;
+	[P0] = R7;
+	SSYNC;
+	STI R6;
 
+	( R7:5) = [SP++];
 	RTS;
-ENDPROC(_read_iloc)
+ENDPROC(_invalidate_entire_icache)
-- 
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