From b5f3294f0be5496aec01e5aa709a5fab8bb2f225 Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Tue, 22 Sep 2009 16:46:02 -0700 Subject: spi: add SPI driver for most known i.MX SoCs This driver has been tested on i.MX1/i.MX27/i.MX35 with an AT25 type EEPROM and on i.MX27/i.MX31 with a Freescale MC13783 PMIC. Signed-off-by: Sascha Hauer Tested-by: Guennadi Liakhovetski Acked-by: David Brownell Cc: Andrea Paterniani Cc: Russell King Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- arch/arm/plat-mxc/include/mach/spi.h | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) create mode 100644 arch/arm/plat-mxc/include/mach/spi.h (limited to 'arch/arm') diff --git a/arch/arm/plat-mxc/include/mach/spi.h b/arch/arm/plat-mxc/include/mach/spi.h new file mode 100644 index 0000000..08be445 --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/spi.h @@ -0,0 +1,27 @@ + +#ifndef __MACH_SPI_H_ +#define __MACH_SPI_H_ + +/* + * struct spi_imx_master - device.platform_data for SPI controller devices. + * @chipselect: Array of chipselects for this master. Numbers >= 0 mean gpio + * pins, numbers < 0 mean internal CSPI chipselects according + * to MXC_SPI_CS(). Normally you want to use gpio based chip + * selects as the CSPI module tries to be intelligent about + * when to assert the chipselect: The CSPI module deasserts the + * chipselect once it runs out of input data. The other problem + * is that it is not possible to mix between high active and low + * active chipselects on one single bus using the internal + * chipselects. Unfortunately Freescale decided to put some + * chipselects on dedicated pins which are not usable as gpios, + * so we have to support the internal chipselects. + * @num_chipselect: ARRAY_SIZE(chipselect) + */ +struct spi_imx_master { + int *chipselect; + int num_chipselect; +}; + +#define MXC_SPI_CS(no) ((no) - 32) + +#endif /* __MACH_SPI_H_*/ -- cgit v1.1