From 5eb43d2813b24153eebde2b09da75408fd443563 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Wed, 27 Feb 2013 22:38:38 +0100 Subject: ARM: nomadik: delete IRQ header This header is not used any more after the platform was switched to obtain resources from the device tree. Signed-off-by: Linus Walleij --- arch/arm/mach-nomadik/cpu-8815.c | 1 - arch/arm/mach-nomadik/include/mach/irqs.h | 79 ------------------------------- 2 files changed, 80 deletions(-) delete mode 100644 arch/arm/mach-nomadik/include/mach/irqs.h (limited to 'arch/arm') diff --git a/arch/arm/mach-nomadik/cpu-8815.c b/arch/arm/mach-nomadik/cpu-8815.c index 21c1aa5..59f6ff5 100644 --- a/arch/arm/mach-nomadik/cpu-8815.c +++ b/arch/arm/mach-nomadik/cpu-8815.c @@ -38,7 +38,6 @@ #include #include -#include #include #include #include diff --git a/arch/arm/mach-nomadik/include/mach/irqs.h b/arch/arm/mach-nomadik/include/mach/irqs.h deleted file mode 100644 index 90ac965..0000000 --- a/arch/arm/mach-nomadik/include/mach/irqs.h +++ /dev/null @@ -1,79 +0,0 @@ -/* - * mach-nomadik/include/mach/irqs.h - * - * Copyright (C) ST Microelectronics - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#ifndef __ASM_ARCH_IRQS_H -#define __ASM_ARCH_IRQS_H - -#define IRQ_VIC_START 32 /* first VIC interrupt is 1 */ - -/* - * Interrupt numbers generic for all Nomadik Chip cuts - */ -#define IRQ_WATCHDOG (IRQ_VIC_START+0) -#define IRQ_SOFTINT (IRQ_VIC_START+1) -#define IRQ_CRYPTO (IRQ_VIC_START+2) -#define IRQ_OWM (IRQ_VIC_START+3) -#define IRQ_MTU0 (IRQ_VIC_START+4) -#define IRQ_MTU1 (IRQ_VIC_START+5) -#define IRQ_GPIO0 (IRQ_VIC_START+6) -#define IRQ_GPIO1 (IRQ_VIC_START+7) -#define IRQ_GPIO2 (IRQ_VIC_START+8) -#define IRQ_GPIO3 (IRQ_VIC_START+9) -#define IRQ_RTC_RTT (IRQ_VIC_START+10) -#define IRQ_SSP (IRQ_VIC_START+11) -#define IRQ_UART0 (IRQ_VIC_START+12) -#define IRQ_DMA1 (IRQ_VIC_START+13) -#define IRQ_CLCD_MDIF (IRQ_VIC_START+14) -#define IRQ_DMA0 (IRQ_VIC_START+15) -#define IRQ_PWRFAIL (IRQ_VIC_START+16) -#define IRQ_UART1 (IRQ_VIC_START+17) -#define IRQ_FIRDA (IRQ_VIC_START+18) -#define IRQ_MSP0 (IRQ_VIC_START+19) -#define IRQ_I2C0 (IRQ_VIC_START+20) -#define IRQ_I2C1 (IRQ_VIC_START+21) -#define IRQ_SDMMC (IRQ_VIC_START+22) -#define IRQ_USBOTG (IRQ_VIC_START+23) -#define IRQ_SVA_IT0 (IRQ_VIC_START+24) -#define IRQ_SVA_IT1 (IRQ_VIC_START+25) -#define IRQ_SAA_IT0 (IRQ_VIC_START+26) -#define IRQ_SAA_IT1 (IRQ_VIC_START+27) -#define IRQ_UART2 (IRQ_VIC_START+28) -#define IRQ_MSP2 (IRQ_VIC_START+29) -#define IRQ_L2CC (IRQ_VIC_START+30) -#define IRQ_HPI (IRQ_VIC_START+31) -#define IRQ_SKE (IRQ_VIC_START+32) -#define IRQ_KP (IRQ_VIC_START+33) -#define IRQ_MEMST (IRQ_VIC_START+34) -#define IRQ_SGA_IT (IRQ_VIC_START+35) -#define IRQ_USBM (IRQ_VIC_START+36) -#define IRQ_MSP1 (IRQ_VIC_START+37) - -#define NOMADIK_GPIO_OFFSET (IRQ_VIC_START+64) - -/* After chip-specific IRQ numbers we have the GPIO ones */ -#define NOMADIK_NR_GPIO 128 /* last 4 not wired to pins */ -#define NOMADIK_GPIO_TO_IRQ(gpio) ((gpio) + NOMADIK_GPIO_OFFSET) -#define NOMADIK_IRQ_TO_GPIO(irq) ((irq) - NOMADIK_GPIO_OFFSET) -#define NOMADIK_NR_IRQS NOMADIK_GPIO_TO_IRQ(NOMADIK_NR_GPIO) - -/* Following two are used by entry_macro.S, to access our dual-vic */ -#define VIC_REG_IRQSR0 0 -#define VIC_REG_IRQSR1 0x20 - -#endif /* __ASM_ARCH_IRQS_H */ -- cgit v1.1 From 266c347924f59b642d0f016e7f9891fdd7463108 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Wed, 27 Feb 2013 22:39:57 +0100 Subject: ARM: nomadik: move debugmacro to debug includes This moves the Nomadik debug macro to the debug headers to make way for multiplatform support. Signed-off-by: Linus Walleij --- arch/arm/Kconfig.debug | 8 ++++++++ arch/arm/include/debug/nomadik.S | 20 ++++++++++++++++++++ arch/arm/mach-nomadik/include/mach/debug-macro.S | 20 -------------------- 3 files changed, 28 insertions(+), 20 deletions(-) create mode 100644 arch/arm/include/debug/nomadik.S delete mode 100644 arch/arm/mach-nomadik/include/mach/debug-macro.S (limited to 'arch/arm') diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug index acdddda..7d4b96d 100644 --- a/arch/arm/Kconfig.debug +++ b/arch/arm/Kconfig.debug @@ -298,6 +298,13 @@ choice Say Y here if you want kernel low-level debugging support on MVEBU based platforms. + config DEBUG_NOMADIK_UART + bool "Kernel low-level debugging messages via NOMADIK UART" + depends on ARCH_NOMADIK + help + Say Y here if you want kernel low-level debugging support + on NOMADIK based platforms. + config DEBUG_OMAP2PLUS_UART bool "Kernel low-level debugging messages via OMAP2PLUS UART" depends on ARCH_OMAP2PLUS @@ -590,6 +597,7 @@ config DEBUG_LL_INCLUDE DEBUG_IMX6Q_UART default "debug/highbank.S" if DEBUG_HIGHBANK_UART default "debug/mvebu.S" if DEBUG_MVEBU_UART + default "debug/nomadik.S" if DEBUG_NOMADIK_UART default "debug/omap2plus.S" if DEBUG_OMAP2PLUS_UART default "debug/picoxcell.S" if DEBUG_PICOXCELL_UART default "debug/socfpga.S" if DEBUG_SOCFPGA_UART diff --git a/arch/arm/include/debug/nomadik.S b/arch/arm/include/debug/nomadik.S new file mode 100644 index 0000000..7354179 --- /dev/null +++ b/arch/arm/include/debug/nomadik.S @@ -0,0 +1,20 @@ +/* + * Debugging macro include header + * + * Copyright (C) 1994-1999 Russell King + * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * +*/ + + .macro addruart, rp, rv, tmp + mov \rp, #0x00100000 + add \rp, \rp, #0x000fb000 + add \rv, \rp, #0xf0000000 @ virtual base + add \rp, \rp, #0x10000000 @ physical base address + .endm + +#include diff --git a/arch/arm/mach-nomadik/include/mach/debug-macro.S b/arch/arm/mach-nomadik/include/mach/debug-macro.S deleted file mode 100644 index 7354179..0000000 --- a/arch/arm/mach-nomadik/include/mach/debug-macro.S +++ /dev/null @@ -1,20 +0,0 @@ -/* - * Debugging macro include header - * - * Copyright (C) 1994-1999 Russell King - * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * -*/ - - .macro addruart, rp, rv, tmp - mov \rp, #0x00100000 - add \rp, \rp, #0x000fb000 - add \rv, \rp, #0xf0000000 @ virtual base - add \rp, \rp, #0x10000000 @ physical base address - .endm - -#include -- cgit v1.1 From 1187ed87723899816128ec9f75edf4fad9c07dc6 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Wed, 27 Feb 2013 23:32:41 +0100 Subject: ARM: nomadik: convert to multiplatform This converts the Nomadik to run in multiplatform mode, including the defconfig change. After this the "uImage" target in the kernel tree will no longer work, but we do not care about this. Instead we generate the uImage from the zImage using mkimage or update the bootloader to accept bootz. Some minor updates to the defconfig are done as part of this. Signed-off-by: Linus Walleij --- arch/arm/Kconfig | 17 --------------- arch/arm/configs/nhk8815_defconfig | 42 +++++++++++++++++--------------------- arch/arm/mach-nomadik/Kconfig | 22 +++++++++++++++++--- 3 files changed, 38 insertions(+), 43 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 5b71469..a5ddc36 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -916,23 +916,6 @@ config ARCH_U8500 help Support for ST-Ericsson's Ux500 architecture -config ARCH_NOMADIK - bool "STMicroelectronics Nomadik" - select ARCH_REQUIRE_GPIOLIB - select ARM_AMBA - select ARM_VIC - select CLKSRC_NOMADIK_MTU - select COMMON_CLK - select CPU_ARM926T - select GENERIC_CLOCKEVENTS - select MIGHT_HAVE_CACHE_L2X0 - select USE_OF - select PINCTRL - select PINCTRL_STN8815 - select SPARSE_IRQ - help - Support for the Nomadik platform by ST-Ericsson - config PLAT_SPEAR bool "ST SPEAr" select ARCH_HAS_CPUFREQ diff --git a/arch/arm/configs/nhk8815_defconfig b/arch/arm/configs/nhk8815_defconfig index 86cfd29..b01e763 100644 --- a/arch/arm/configs/nhk8815_defconfig +++ b/arch/arm/configs/nhk8815_defconfig @@ -1,11 +1,9 @@ -CONFIG_EXPERIMENTAL=y # CONFIG_LOCALVERSION_AUTO is not set # CONFIG_SWAP is not set CONFIG_SYSVIPC=y CONFIG_IKCONFIG=y CONFIG_IKCONFIG_PROC=y CONFIG_LOG_BUF_SHIFT=14 -CONFIG_SYSFS_DEPRECATED_V2=y CONFIG_BLK_DEV_INITRD=y CONFIG_EXPERT=y CONFIG_KALLSYMS_ALL=y @@ -13,6 +11,7 @@ CONFIG_SLAB=y CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y # CONFIG_BLK_DEV_BSG is not set +# CONFIG_ARCH_MULTI_V7 is not set CONFIG_ARCH_NOMADIK=y CONFIG_MACH_NOMADIK_8815NHK=y CONFIG_PREEMPT=y @@ -20,7 +19,6 @@ CONFIG_AEABI=y CONFIG_ZBOOT_ROM_TEXT=0x0 CONFIG_ZBOOT_ROM_BSS=0x0 CONFIG_FPE_NWFPE=y -CONFIG_PM=y CONFIG_NET=y CONFIG_PACKET=y CONFIG_UNIX=y @@ -32,14 +30,10 @@ CONFIG_IP_PNP=y CONFIG_IP_PNP_DHCP=y CONFIG_IP_PNP_BOOTP=y CONFIG_NET_IPIP=y -CONFIG_NET_IPGRE=y -CONFIG_NET_IPGRE_BROADCAST=y CONFIG_IP_MROUTE=y # CONFIG_INET_LRO is not set # CONFIG_IPV6 is not set CONFIG_BT=m -CONFIG_BT_L2CAP=m -CONFIG_BT_SCO=m CONFIG_BT_RFCOMM=m CONFIG_BT_RFCOMM_TTY=y CONFIG_BT_BNEP=m @@ -53,14 +47,16 @@ CONFIG_BT_HCIVHCI=m CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_MTD=y CONFIG_MTD_TESTS=m +CONFIG_MTD_CMDLINE_PARTS=y CONFIG_MTD_CHAR=y CONFIG_MTD_BLOCK=y -CONFIG_MTD_NAND=y CONFIG_MTD_NAND_ECC_SMC=y +CONFIG_MTD_NAND=y CONFIG_MTD_NAND_FSMC=y CONFIG_MTD_ONENAND=y CONFIG_MTD_ONENAND_VERIFY_WRITE=y CONFIG_MTD_ONENAND_GENERIC=y +CONFIG_PROC_DEVICETREE=y CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_DEV_CRYPTOLOOP=y CONFIG_BLK_DEV_RAM=y @@ -72,47 +68,48 @@ CONFIG_SCSI_CONSTANTS=y CONFIG_SCSI_LOGGING=y CONFIG_SCSI_SCAN_ASYNC=y CONFIG_NETDEVICES=y +CONFIG_NETCONSOLE=m CONFIG_TUN=y -CONFIG_NET_ETHERNET=y CONFIG_SMC91X=y CONFIG_PPP=m -CONFIG_PPP_ASYNC=m -CONFIG_PPP_SYNC_TTY=m -CONFIG_PPP_DEFLATE=m CONFIG_PPP_BSDCOMP=m +CONFIG_PPP_DEFLATE=m CONFIG_PPP_MPPE=m CONFIG_PPPOE=m -CONFIG_NETCONSOLE=m +CONFIG_PPP_ASYNC=m +CONFIG_PPP_SYNC_TTY=m # CONFIG_INPUT_MOUSEDEV is not set CONFIG_INPUT_EVDEV=y # CONFIG_KEYBOARD_ATKBD is not set # CONFIG_MOUSE_PS2 is not set # CONFIG_SERIO is not set +# CONFIG_LEGACY_PTYS is not set CONFIG_SERIAL_AMBA_PL011=y CONFIG_SERIAL_AMBA_PL011_CONSOLE=y -# CONFIG_LEGACY_PTYS is not set -# CONFIG_HW_RANDOM is not set -CONFIG_I2C=y +CONFIG_HW_RANDOM=y +CONFIG_HW_RANDOM_NOMADIK=y CONFIG_I2C_CHARDEV=y CONFIG_I2C_GPIO=y +CONFIG_I2C_NOMADIK=y CONFIG_DEBUG_GPIO=y -CONFIG_PINCTRL_NOMADIK=y # CONFIG_HWMON is not set -# CONFIG_VGA_CONSOLE is not set +CONFIG_MMC=y +CONFIG_MMC_CLKGATE=y +CONFIG_MMC_ARMMMCI=y CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_PL031=y +CONFIG_DMADEVICES=y +CONFIG_AMBA_PL08X=y CONFIG_EXT2_FS=y CONFIG_EXT3_FS=y -CONFIG_INOTIFY=y CONFIG_FUSE_FS=y CONFIG_MSDOS_FS=y CONFIG_VFAT_FS=y CONFIG_TMPFS=y CONFIG_JFFS2_FS=y CONFIG_NFS_FS=y -CONFIG_NFS_V3=y CONFIG_NFS_V3_ACL=y CONFIG_ROOT_NFS=y -CONFIG_SMB_FS=m CONFIG_CIFS=m CONFIG_CIFS_WEAK_PW_HASH=y CONFIG_NLS_CODEPAGE_437=y @@ -120,12 +117,11 @@ CONFIG_NLS_ASCII=y CONFIG_NLS_ISO8859_1=y CONFIG_NLS_ISO8859_15=y # CONFIG_ENABLE_MUST_CHECK is not set -CONFIG_DEBUG_KERNEL=y +CONFIG_DEBUG_FS=y # CONFIG_SCHED_DEBUG is not set # CONFIG_DEBUG_PREEMPT is not set # CONFIG_DEBUG_BUGVERBOSE is not set CONFIG_DEBUG_INFO=y -# CONFIG_RCU_CPU_STALL_DETECTOR is not set CONFIG_CRYPTO_MD5=y CONFIG_CRYPTO_SHA1=y CONFIG_CRYPTO_DES=y diff --git a/arch/arm/mach-nomadik/Kconfig b/arch/arm/mach-nomadik/Kconfig index 82226a5..954f0e3 100644 --- a/arch/arm/mach-nomadik/Kconfig +++ b/arch/arm/mach-nomadik/Kconfig @@ -1,4 +1,21 @@ -if ARCH_NOMADIK +config ARCH_NOMADIK + bool "ST-Ericsson Nomadik" + depends on ARCH_MULTI_V5 + select ARCH_REQUIRE_GPIOLIB + select ARM_AMBA + select ARM_VIC + select CLKSRC_NOMADIK_MTU + select COMMON_CLK + select CPU_ARM926T + select GENERIC_CLOCKEVENTS + select MIGHT_HAVE_CACHE_L2X0 + select PINCTRL + select PINCTRL_NOMADIK + select PINCTRL_STN8815 + select SPARSE_IRQ + select USE_OF + help + Support for the Nomadik platform by ST-Ericsson menu "Nomadik boards" @@ -11,6 +28,5 @@ config MACH_NOMADIK_8815NHK endmenu config NOMADIK_8815 + depends on ARCH_NOMADIK bool - -endif -- cgit v1.1 From a2823dd5f5e2f9da2eafc402612ae85526ed222c Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Wed, 27 Feb 2013 23:35:40 +0100 Subject: ARM: nomadik: delete remnant include files This deletes the leftover and and Makefile.boot that have no role in a multiplatform environment. Signed-off-by: Linus Walleij --- arch/arm/mach-nomadik/Makefile.boot | 4 -- arch/arm/mach-nomadik/include/mach/timex.h | 6 --- arch/arm/mach-nomadik/include/mach/uncompress.h | 60 ------------------------- 3 files changed, 70 deletions(-) delete mode 100644 arch/arm/mach-nomadik/Makefile.boot delete mode 100644 arch/arm/mach-nomadik/include/mach/timex.h delete mode 100644 arch/arm/mach-nomadik/include/mach/uncompress.h (limited to 'arch/arm') diff --git a/arch/arm/mach-nomadik/Makefile.boot b/arch/arm/mach-nomadik/Makefile.boot deleted file mode 100644 index ff0a4b5..0000000 --- a/arch/arm/mach-nomadik/Makefile.boot +++ /dev/null @@ -1,4 +0,0 @@ - zreladdr-y += 0x00008000 -params_phys-y := 0x00000100 -initrd_phys-y := 0x00800000 - diff --git a/arch/arm/mach-nomadik/include/mach/timex.h b/arch/arm/mach-nomadik/include/mach/timex.h deleted file mode 100644 index 318b889..0000000 --- a/arch/arm/mach-nomadik/include/mach/timex.h +++ /dev/null @@ -1,6 +0,0 @@ -#ifndef __ASM_ARCH_TIMEX_H -#define __ASM_ARCH_TIMEX_H - -#define CLOCK_TICK_RATE 2400000 - -#endif diff --git a/arch/arm/mach-nomadik/include/mach/uncompress.h b/arch/arm/mach-nomadik/include/mach/uncompress.h deleted file mode 100644 index 106fccc..0000000 --- a/arch/arm/mach-nomadik/include/mach/uncompress.h +++ /dev/null @@ -1,60 +0,0 @@ -/* - * Copyright (C) 2008 STMicroelectronics - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ - -#ifndef __ASM_ARCH_UNCOMPRESS_H -#define __ASM_ARCH_UNCOMPRESS_H - -#include -#include - -/* we need the constants in amba/serial.h, but it refers to amba_device */ -struct amba_device; -#include - -#define NOMADIK_UART_DR (void __iomem *)0x101FB000 -#define NOMADIK_UART_LCRH (void __iomem *)0x101FB02c -#define NOMADIK_UART_CR (void __iomem *)0x101FB030 -#define NOMADIK_UART_FR (void __iomem *)0x101FB018 - -static void putc(const char c) -{ - /* Do nothing if the UART is not enabled. */ - if (!(readb(NOMADIK_UART_CR) & UART01x_CR_UARTEN)) - return; - - if (c == '\n') - putc('\r'); - - while (readb(NOMADIK_UART_FR) & UART01x_FR_TXFF) - barrier(); - writeb(c, NOMADIK_UART_DR); -} - -static void flush(void) -{ - if (!(readb(NOMADIK_UART_CR) & UART01x_CR_UARTEN)) - return; - while (readb(NOMADIK_UART_FR) & UART01x_FR_BUSY) - barrier(); -} - -static inline void arch_decomp_setup(void) -{ -} - -#endif /* __ASM_ARCH_UNCOMPRESS_H */ -- cgit v1.1 From 17dd1094e49199c1b681e0dcd337547dbb2e3270 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Sun, 2 Dec 2012 01:31:53 +0100 Subject: ARM: spear13xx: make mach/dma.h local There is no reason for this header file to be globally visible, so let's just move it into the mach directory. Signed-off-by: Arnd Bergmann Acked-by: Viresh Kumar --- arch/arm/mach-spear13xx/include/mach/dma.h | 128 ----------------------------- arch/arm/mach-spear13xx/spear1340.c | 3 +- arch/arm/mach-spear13xx/spear13xx-dma.h | 128 +++++++++++++++++++++++++++++ arch/arm/mach-spear13xx/spear13xx.c | 3 +- 4 files changed, 132 insertions(+), 130 deletions(-) delete mode 100644 arch/arm/mach-spear13xx/include/mach/dma.h create mode 100644 arch/arm/mach-spear13xx/spear13xx-dma.h (limited to 'arch/arm') diff --git a/arch/arm/mach-spear13xx/include/mach/dma.h b/arch/arm/mach-spear13xx/include/mach/dma.h deleted file mode 100644 index d50bdb6..0000000 --- a/arch/arm/mach-spear13xx/include/mach/dma.h +++ /dev/null @@ -1,128 +0,0 @@ -/* - * arch/arm/mach-spear13xx/include/mach/dma.h - * - * DMA information for SPEAr13xx machine family - * - * Copyright (C) 2012 ST Microelectronics - * Viresh Kumar - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#ifndef __MACH_DMA_H -#define __MACH_DMA_H - -/* request id of all the peripherals */ -enum dma_master_info { - /* Accessible from only one master */ - DMA_MASTER_MCIF = 0, - DMA_MASTER_FSMC = 1, - /* Accessible from both 0 & 1 */ - DMA_MASTER_MEMORY = 0, - DMA_MASTER_ADC = 0, - DMA_MASTER_UART0 = 0, - DMA_MASTER_SSP0 = 0, - DMA_MASTER_I2C0 = 0, - -#ifdef CONFIG_MACH_SPEAR1310 - /* Accessible from only one master */ - SPEAR1310_DMA_MASTER_JPEG = 1, - - /* Accessible from both 0 & 1 */ - SPEAR1310_DMA_MASTER_I2S = 0, - SPEAR1310_DMA_MASTER_UART1 = 0, - SPEAR1310_DMA_MASTER_UART2 = 0, - SPEAR1310_DMA_MASTER_UART3 = 0, - SPEAR1310_DMA_MASTER_UART4 = 0, - SPEAR1310_DMA_MASTER_UART5 = 0, - SPEAR1310_DMA_MASTER_I2C1 = 0, - SPEAR1310_DMA_MASTER_I2C2 = 0, - SPEAR1310_DMA_MASTER_I2C3 = 0, - SPEAR1310_DMA_MASTER_I2C4 = 0, - SPEAR1310_DMA_MASTER_I2C5 = 0, - SPEAR1310_DMA_MASTER_I2C6 = 0, - SPEAR1310_DMA_MASTER_I2C7 = 0, - SPEAR1310_DMA_MASTER_SSP1 = 0, -#endif - -#ifdef CONFIG_MACH_SPEAR1340 - /* Accessible from only one master */ - SPEAR1340_DMA_MASTER_I2S_PLAY = 1, - SPEAR1340_DMA_MASTER_I2S_REC = 1, - SPEAR1340_DMA_MASTER_I2C1 = 1, - SPEAR1340_DMA_MASTER_UART1 = 1, - - /* following are accessible from both master 0 & 1 */ - SPEAR1340_DMA_MASTER_SPDIF = 0, - SPEAR1340_DMA_MASTER_CAM = 1, - SPEAR1340_DMA_MASTER_VIDEO_IN = 0, - SPEAR1340_DMA_MASTER_MALI = 0, -#endif -}; - -enum request_id { - DMA_REQ_ADC = 0, - DMA_REQ_SSP0_TX = 4, - DMA_REQ_SSP0_RX = 5, - DMA_REQ_UART0_TX = 6, - DMA_REQ_UART0_RX = 7, - DMA_REQ_I2C0_TX = 8, - DMA_REQ_I2C0_RX = 9, - -#ifdef CONFIG_MACH_SPEAR1310 - SPEAR1310_DMA_REQ_FROM_JPEG = 2, - SPEAR1310_DMA_REQ_TO_JPEG = 3, - SPEAR1310_DMA_REQ_I2S_TX = 10, - SPEAR1310_DMA_REQ_I2S_RX = 11, - - SPEAR1310_DMA_REQ_I2C1_RX = 0, - SPEAR1310_DMA_REQ_I2C1_TX = 1, - SPEAR1310_DMA_REQ_I2C2_RX = 2, - SPEAR1310_DMA_REQ_I2C2_TX = 3, - SPEAR1310_DMA_REQ_I2C3_RX = 4, - SPEAR1310_DMA_REQ_I2C3_TX = 5, - SPEAR1310_DMA_REQ_I2C4_RX = 6, - SPEAR1310_DMA_REQ_I2C4_TX = 7, - SPEAR1310_DMA_REQ_I2C5_RX = 8, - SPEAR1310_DMA_REQ_I2C5_TX = 9, - SPEAR1310_DMA_REQ_I2C6_RX = 10, - SPEAR1310_DMA_REQ_I2C6_TX = 11, - SPEAR1310_DMA_REQ_UART1_RX = 12, - SPEAR1310_DMA_REQ_UART1_TX = 13, - SPEAR1310_DMA_REQ_UART2_RX = 14, - SPEAR1310_DMA_REQ_UART2_TX = 15, - SPEAR1310_DMA_REQ_UART5_RX = 16, - SPEAR1310_DMA_REQ_UART5_TX = 17, - SPEAR1310_DMA_REQ_SSP1_RX = 18, - SPEAR1310_DMA_REQ_SSP1_TX = 19, - SPEAR1310_DMA_REQ_I2C7_RX = 20, - SPEAR1310_DMA_REQ_I2C7_TX = 21, - SPEAR1310_DMA_REQ_UART3_RX = 28, - SPEAR1310_DMA_REQ_UART3_TX = 29, - SPEAR1310_DMA_REQ_UART4_RX = 30, - SPEAR1310_DMA_REQ_UART4_TX = 31, -#endif - -#ifdef CONFIG_MACH_SPEAR1340 - SPEAR1340_DMA_REQ_SPDIF_TX = 2, - SPEAR1340_DMA_REQ_SPDIF_RX = 3, - SPEAR1340_DMA_REQ_I2S_TX = 10, - SPEAR1340_DMA_REQ_I2S_RX = 11, - SPEAR1340_DMA_REQ_UART1_TX = 12, - SPEAR1340_DMA_REQ_UART1_RX = 13, - SPEAR1340_DMA_REQ_I2C1_TX = 14, - SPEAR1340_DMA_REQ_I2C1_RX = 15, - SPEAR1340_DMA_REQ_CAM0_EVEN = 0, - SPEAR1340_DMA_REQ_CAM0_ODD = 1, - SPEAR1340_DMA_REQ_CAM1_EVEN = 2, - SPEAR1340_DMA_REQ_CAM1_ODD = 3, - SPEAR1340_DMA_REQ_CAM2_EVEN = 4, - SPEAR1340_DMA_REQ_CAM2_ODD = 5, - SPEAR1340_DMA_REQ_CAM3_EVEN = 6, - SPEAR1340_DMA_REQ_CAM3_ODD = 7, -#endif -}; - -#endif /* __MACH_DMA_H */ diff --git a/arch/arm/mach-spear13xx/spear1340.c b/arch/arm/mach-spear13xx/spear1340.c index 9a28beb..b01c4c7 100644 --- a/arch/arm/mach-spear13xx/spear1340.c +++ b/arch/arm/mach-spear13xx/spear1340.c @@ -20,10 +20,11 @@ #include #include #include -#include #include #include +#include "spear13xx-dma.h" + /* Base addresses */ #define SPEAR1340_SATA_BASE UL(0xB1000000) #define SPEAR1340_UART1_BASE UL(0xB4100000) diff --git a/arch/arm/mach-spear13xx/spear13xx-dma.h b/arch/arm/mach-spear13xx/spear13xx-dma.h new file mode 100644 index 0000000..d50bdb6 --- /dev/null +++ b/arch/arm/mach-spear13xx/spear13xx-dma.h @@ -0,0 +1,128 @@ +/* + * arch/arm/mach-spear13xx/include/mach/dma.h + * + * DMA information for SPEAr13xx machine family + * + * Copyright (C) 2012 ST Microelectronics + * Viresh Kumar + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __MACH_DMA_H +#define __MACH_DMA_H + +/* request id of all the peripherals */ +enum dma_master_info { + /* Accessible from only one master */ + DMA_MASTER_MCIF = 0, + DMA_MASTER_FSMC = 1, + /* Accessible from both 0 & 1 */ + DMA_MASTER_MEMORY = 0, + DMA_MASTER_ADC = 0, + DMA_MASTER_UART0 = 0, + DMA_MASTER_SSP0 = 0, + DMA_MASTER_I2C0 = 0, + +#ifdef CONFIG_MACH_SPEAR1310 + /* Accessible from only one master */ + SPEAR1310_DMA_MASTER_JPEG = 1, + + /* Accessible from both 0 & 1 */ + SPEAR1310_DMA_MASTER_I2S = 0, + SPEAR1310_DMA_MASTER_UART1 = 0, + SPEAR1310_DMA_MASTER_UART2 = 0, + SPEAR1310_DMA_MASTER_UART3 = 0, + SPEAR1310_DMA_MASTER_UART4 = 0, + SPEAR1310_DMA_MASTER_UART5 = 0, + SPEAR1310_DMA_MASTER_I2C1 = 0, + SPEAR1310_DMA_MASTER_I2C2 = 0, + SPEAR1310_DMA_MASTER_I2C3 = 0, + SPEAR1310_DMA_MASTER_I2C4 = 0, + SPEAR1310_DMA_MASTER_I2C5 = 0, + SPEAR1310_DMA_MASTER_I2C6 = 0, + SPEAR1310_DMA_MASTER_I2C7 = 0, + SPEAR1310_DMA_MASTER_SSP1 = 0, +#endif + +#ifdef CONFIG_MACH_SPEAR1340 + /* Accessible from only one master */ + SPEAR1340_DMA_MASTER_I2S_PLAY = 1, + SPEAR1340_DMA_MASTER_I2S_REC = 1, + SPEAR1340_DMA_MASTER_I2C1 = 1, + SPEAR1340_DMA_MASTER_UART1 = 1, + + /* following are accessible from both master 0 & 1 */ + SPEAR1340_DMA_MASTER_SPDIF = 0, + SPEAR1340_DMA_MASTER_CAM = 1, + SPEAR1340_DMA_MASTER_VIDEO_IN = 0, + SPEAR1340_DMA_MASTER_MALI = 0, +#endif +}; + +enum request_id { + DMA_REQ_ADC = 0, + DMA_REQ_SSP0_TX = 4, + DMA_REQ_SSP0_RX = 5, + DMA_REQ_UART0_TX = 6, + DMA_REQ_UART0_RX = 7, + DMA_REQ_I2C0_TX = 8, + DMA_REQ_I2C0_RX = 9, + +#ifdef CONFIG_MACH_SPEAR1310 + SPEAR1310_DMA_REQ_FROM_JPEG = 2, + SPEAR1310_DMA_REQ_TO_JPEG = 3, + SPEAR1310_DMA_REQ_I2S_TX = 10, + SPEAR1310_DMA_REQ_I2S_RX = 11, + + SPEAR1310_DMA_REQ_I2C1_RX = 0, + SPEAR1310_DMA_REQ_I2C1_TX = 1, + SPEAR1310_DMA_REQ_I2C2_RX = 2, + SPEAR1310_DMA_REQ_I2C2_TX = 3, + SPEAR1310_DMA_REQ_I2C3_RX = 4, + SPEAR1310_DMA_REQ_I2C3_TX = 5, + SPEAR1310_DMA_REQ_I2C4_RX = 6, + SPEAR1310_DMA_REQ_I2C4_TX = 7, + SPEAR1310_DMA_REQ_I2C5_RX = 8, + SPEAR1310_DMA_REQ_I2C5_TX = 9, + SPEAR1310_DMA_REQ_I2C6_RX = 10, + SPEAR1310_DMA_REQ_I2C6_TX = 11, + SPEAR1310_DMA_REQ_UART1_RX = 12, + SPEAR1310_DMA_REQ_UART1_TX = 13, + SPEAR1310_DMA_REQ_UART2_RX = 14, + SPEAR1310_DMA_REQ_UART2_TX = 15, + SPEAR1310_DMA_REQ_UART5_RX = 16, + SPEAR1310_DMA_REQ_UART5_TX = 17, + SPEAR1310_DMA_REQ_SSP1_RX = 18, + SPEAR1310_DMA_REQ_SSP1_TX = 19, + SPEAR1310_DMA_REQ_I2C7_RX = 20, + SPEAR1310_DMA_REQ_I2C7_TX = 21, + SPEAR1310_DMA_REQ_UART3_RX = 28, + SPEAR1310_DMA_REQ_UART3_TX = 29, + SPEAR1310_DMA_REQ_UART4_RX = 30, + SPEAR1310_DMA_REQ_UART4_TX = 31, +#endif + +#ifdef CONFIG_MACH_SPEAR1340 + SPEAR1340_DMA_REQ_SPDIF_TX = 2, + SPEAR1340_DMA_REQ_SPDIF_RX = 3, + SPEAR1340_DMA_REQ_I2S_TX = 10, + SPEAR1340_DMA_REQ_I2S_RX = 11, + SPEAR1340_DMA_REQ_UART1_TX = 12, + SPEAR1340_DMA_REQ_UART1_RX = 13, + SPEAR1340_DMA_REQ_I2C1_TX = 14, + SPEAR1340_DMA_REQ_I2C1_RX = 15, + SPEAR1340_DMA_REQ_CAM0_EVEN = 0, + SPEAR1340_DMA_REQ_CAM0_ODD = 1, + SPEAR1340_DMA_REQ_CAM1_EVEN = 2, + SPEAR1340_DMA_REQ_CAM1_ODD = 3, + SPEAR1340_DMA_REQ_CAM2_EVEN = 4, + SPEAR1340_DMA_REQ_CAM2_ODD = 5, + SPEAR1340_DMA_REQ_CAM3_EVEN = 6, + SPEAR1340_DMA_REQ_CAM3_ODD = 7, +#endif +}; + +#endif /* __MACH_DMA_H */ diff --git a/arch/arm/mach-spear13xx/spear13xx.c b/arch/arm/mach-spear13xx/spear13xx.c index c7d2b4a..988fefe 100644 --- a/arch/arm/mach-spear13xx/spear13xx.c +++ b/arch/arm/mach-spear13xx/spear13xx.c @@ -21,10 +21,11 @@ #include #include #include -#include #include #include +#include "spear13xx-dma.h" + /* common dw_dma filter routine to be used by peripherals */ bool dw_dma_filter(struct dma_chan *chan, void *slave) { -- cgit v1.1 From 5447521094b2948ee96aa61e110e3955ad88057c Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Tue, 12 Mar 2013 17:00:03 +0100 Subject: ARM: spear: unify mach/generic.h and mach/irqs.h These are indeed easy to combine, as there are no conflicting definitions in generic.h, and irqs.h will be obsolete once we enable SPARSE_IRQ. Signed-off-by: Arnd Bergmann Acked-by: Viresh Kumar --- arch/arm/mach-spear13xx/include/mach/generic.h | 21 ++++++++---- arch/arm/mach-spear13xx/include/mach/irqs.h | 23 ++++++++++--- arch/arm/mach-spear3xx/include/mach/generic.h | 42 +++++++++++++++++------ arch/arm/mach-spear3xx/include/mach/irqs.h | 24 ++++++++++--- arch/arm/mach-spear3xx/spear320.c | 1 + arch/arm/mach-spear3xx/spear3xx.c | 4 ++- arch/arm/mach-spear6xx/include/mach/generic.h | 47 ++++++++++++++++++++++---- arch/arm/mach-spear6xx/include/mach/irqs.h | 22 ++++++++---- 8 files changed, 146 insertions(+), 38 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-spear13xx/include/mach/generic.h b/arch/arm/mach-spear13xx/include/mach/generic.h index 633e678..af47d9b 100644 --- a/arch/arm/mach-spear13xx/include/mach/generic.h +++ b/arch/arm/mach-spear13xx/include/mach/generic.h @@ -1,9 +1,8 @@ /* - * arch/arm/mach-spear13xx/include/mach/generic.h + * spear machine family generic header file * - * spear13xx machine family generic header file - * - * Copyright (C) 2012 ST Microelectronics + * Copyright (C) 2009-2012 ST Microelectronics + * Rajeev Kumar * Viresh Kumar * * This file is licensed under the terms of the GNU General Public @@ -15,22 +14,30 @@ #define __MACH_GENERIC_H #include +#include +#include #include -/* Add spear13xx structure declarations here */ extern void spear13xx_timer_init(void); +extern void spear3xx_timer_init(void); extern struct pl022_ssp_controller pl022_plat_data; +extern struct pl08x_platform_data pl080_plat_data; extern struct dw_dma_platform_data dmac_plat_data; extern struct dw_dma_slave cf_dma_priv; extern struct dw_dma_slave nand_read_dma_priv; extern struct dw_dma_slave nand_write_dma_priv; +bool dw_dma_filter(struct dma_chan *chan, void *slave); -/* Add spear13xx family function declarations here */ void __init spear_setup_of_timer(void); +void __init spear3xx_clk_init(void); +void __init spear3xx_map_io(void); +void __init spear3xx_dt_init_irq(void); +void __init spear6xx_clk_init(void); void __init spear13xx_map_io(void); void __init spear13xx_l2x0_init(void); -bool dw_dma_filter(struct dma_chan *chan, void *slave); + void spear_restart(char, const char *); + void spear13xx_secondary_startup(void); void __cpuinit spear13xx_cpu_die(unsigned int cpu); diff --git a/arch/arm/mach-spear13xx/include/mach/irqs.h b/arch/arm/mach-spear13xx/include/mach/irqs.h index 271a62b..92da0a8 100644 --- a/arch/arm/mach-spear13xx/include/mach/irqs.h +++ b/arch/arm/mach-spear13xx/include/mach/irqs.h @@ -1,9 +1,8 @@ /* - * arch/arm/mach-spear13xx/include/mach/irqs.h + * IRQ helper macros for spear machine family * - * IRQ helper macros for spear13xx machine family - * - * Copyright (C) 2012 ST Microelectronics + * Copyright (C) 2009-2012 ST Microelectronics + * Rajeev Kumar * Viresh Kumar * * This file is licensed under the terms of the GNU General Public @@ -14,7 +13,23 @@ #ifndef __MACH_IRQS_H #define __MACH_IRQS_H +#ifdef CONFIG_ARCH_SPEAR3XX +#define NR_IRQS 256 +#endif + +#ifdef CONFIG_ARCH_SPEAR6XX +/* IRQ definitions */ +/* VIC 1 */ +#define IRQ_VIC_END 64 + +/* GPIO pins virtual irqs */ +#define VIRTUAL_IRQS 24 +#define NR_IRQS (IRQ_VIC_END + VIRTUAL_IRQS) +#endif + +#ifdef CONFIG_ARCH_SPEAR13XX #define IRQ_GIC_END 160 #define NR_IRQS IRQ_GIC_END +#endif #endif /* __MACH_IRQS_H */ diff --git a/arch/arm/mach-spear3xx/include/mach/generic.h b/arch/arm/mach-spear3xx/include/mach/generic.h index df31079..af47d9b 100644 --- a/arch/arm/mach-spear3xx/include/mach/generic.h +++ b/arch/arm/mach-spear3xx/include/mach/generic.h @@ -1,10 +1,9 @@ /* - * arch/arm/mach-spear3xx/generic.h + * spear machine family generic header file * - * SPEAr3XX machine family generic header file - * - * Copyright (C) 2009 ST Microelectronics - * Viresh Kumar + * Copyright (C) 2009-2012 ST Microelectronics + * Rajeev Kumar + * Viresh Kumar * * This file is licensed under the terms of the GNU General Public * License version 2. This program is licensed "as is" without any @@ -14,23 +13,46 @@ #ifndef __MACH_GENERIC_H #define __MACH_GENERIC_H +#include #include #include -#include -#include #include -#include -/* Add spear3xx family device structure declarations here */ +extern void spear13xx_timer_init(void); extern void spear3xx_timer_init(void); extern struct pl022_ssp_controller pl022_plat_data; extern struct pl08x_platform_data pl080_plat_data; +extern struct dw_dma_platform_data dmac_plat_data; +extern struct dw_dma_slave cf_dma_priv; +extern struct dw_dma_slave nand_read_dma_priv; +extern struct dw_dma_slave nand_write_dma_priv; +bool dw_dma_filter(struct dma_chan *chan, void *slave); -/* Add spear3xx family function declarations here */ void __init spear_setup_of_timer(void); void __init spear3xx_clk_init(void); void __init spear3xx_map_io(void); +void __init spear3xx_dt_init_irq(void); +void __init spear6xx_clk_init(void); +void __init spear13xx_map_io(void); +void __init spear13xx_l2x0_init(void); void spear_restart(char, const char *); +void spear13xx_secondary_startup(void); +void __cpuinit spear13xx_cpu_die(unsigned int cpu); + +extern struct smp_operations spear13xx_smp_ops; + +#ifdef CONFIG_MACH_SPEAR1310 +void __init spear1310_clk_init(void); +#else +static inline void spear1310_clk_init(void) {} +#endif + +#ifdef CONFIG_MACH_SPEAR1340 +void __init spear1340_clk_init(void); +#else +static inline void spear1340_clk_init(void) {} +#endif + #endif /* __MACH_GENERIC_H */ diff --git a/arch/arm/mach-spear3xx/include/mach/irqs.h b/arch/arm/mach-spear3xx/include/mach/irqs.h index f95e5b2..92da0a8 100644 --- a/arch/arm/mach-spear3xx/include/mach/irqs.h +++ b/arch/arm/mach-spear3xx/include/mach/irqs.h @@ -1,9 +1,8 @@ /* - * arch/arm/mach-spear3xx/include/mach/irqs.h + * IRQ helper macros for spear machine family * - * IRQ helper macros for SPEAr3xx machine family - * - * Copyright (C) 2009 ST Microelectronics + * Copyright (C) 2009-2012 ST Microelectronics + * Rajeev Kumar * Viresh Kumar * * This file is licensed under the terms of the GNU General Public @@ -14,6 +13,23 @@ #ifndef __MACH_IRQS_H #define __MACH_IRQS_H +#ifdef CONFIG_ARCH_SPEAR3XX #define NR_IRQS 256 +#endif + +#ifdef CONFIG_ARCH_SPEAR6XX +/* IRQ definitions */ +/* VIC 1 */ +#define IRQ_VIC_END 64 + +/* GPIO pins virtual irqs */ +#define VIRTUAL_IRQS 24 +#define NR_IRQS (IRQ_VIC_END + VIRTUAL_IRQS) +#endif + +#ifdef CONFIG_ARCH_SPEAR13XX +#define IRQ_GIC_END 160 +#define NR_IRQS IRQ_GIC_END +#endif #endif /* __MACH_IRQS_H */ diff --git a/arch/arm/mach-spear3xx/spear320.c b/arch/arm/mach-spear3xx/spear320.c index e1c7707..f671a0a 100644 --- a/arch/arm/mach-spear3xx/spear320.c +++ b/arch/arm/mach-spear3xx/spear320.c @@ -19,6 +19,7 @@ #include #include #include +#include #include #include diff --git a/arch/arm/mach-spear3xx/spear3xx.c b/arch/arm/mach-spear3xx/spear3xx.c index f9d754f..72e3ae7 100644 --- a/arch/arm/mach-spear3xx/spear3xx.c +++ b/arch/arm/mach-spear3xx/spear3xx.c @@ -14,8 +14,10 @@ #define pr_fmt(fmt) "SPEAr3xx: " fmt #include -#include +#include +#include #include +#include #include #include #include diff --git a/arch/arm/mach-spear6xx/include/mach/generic.h b/arch/arm/mach-spear6xx/include/mach/generic.h index 65514b15..af47d9b 100644 --- a/arch/arm/mach-spear6xx/include/mach/generic.h +++ b/arch/arm/mach-spear6xx/include/mach/generic.h @@ -1,10 +1,9 @@ /* - * arch/arm/mach-spear6xx/include/mach/generic.h + * spear machine family generic header file * - * SPEAr6XX machine family specific generic header file - * - * Copyright (C) 2009 ST Microelectronics - * Rajeev Kumar + * Copyright (C) 2009-2012 ST Microelectronics + * Rajeev Kumar + * Viresh Kumar * * This file is licensed under the terms of the GNU General Public * License version 2. This program is licensed "as is" without any @@ -14,10 +13,46 @@ #ifndef __MACH_GENERIC_H #define __MACH_GENERIC_H +#include +#include #include +#include + +extern void spear13xx_timer_init(void); +extern void spear3xx_timer_init(void); +extern struct pl022_ssp_controller pl022_plat_data; +extern struct pl08x_platform_data pl080_plat_data; +extern struct dw_dma_platform_data dmac_plat_data; +extern struct dw_dma_slave cf_dma_priv; +extern struct dw_dma_slave nand_read_dma_priv; +extern struct dw_dma_slave nand_write_dma_priv; +bool dw_dma_filter(struct dma_chan *chan, void *slave); void __init spear_setup_of_timer(void); -void spear_restart(char, const char *); +void __init spear3xx_clk_init(void); +void __init spear3xx_map_io(void); +void __init spear3xx_dt_init_irq(void); void __init spear6xx_clk_init(void); +void __init spear13xx_map_io(void); +void __init spear13xx_l2x0_init(void); + +void spear_restart(char, const char *); + +void spear13xx_secondary_startup(void); +void __cpuinit spear13xx_cpu_die(unsigned int cpu); + +extern struct smp_operations spear13xx_smp_ops; + +#ifdef CONFIG_MACH_SPEAR1310 +void __init spear1310_clk_init(void); +#else +static inline void spear1310_clk_init(void) {} +#endif + +#ifdef CONFIG_MACH_SPEAR1340 +void __init spear1340_clk_init(void); +#else +static inline void spear1340_clk_init(void) {} +#endif #endif /* __MACH_GENERIC_H */ diff --git a/arch/arm/mach-spear6xx/include/mach/irqs.h b/arch/arm/mach-spear6xx/include/mach/irqs.h index 37a5c41..92da0a8 100644 --- a/arch/arm/mach-spear6xx/include/mach/irqs.h +++ b/arch/arm/mach-spear6xx/include/mach/irqs.h @@ -1,10 +1,9 @@ /* - * arch/arm/mach-spear6xx/include/mach/irqs.h + * IRQ helper macros for spear machine family * - * IRQ helper macros for SPEAr6xx machine family - * - * Copyright (C) 2009 ST Microelectronics - * Rajeev Kumar + * Copyright (C) 2009-2012 ST Microelectronics + * Rajeev Kumar + * Viresh Kumar * * This file is licensed under the terms of the GNU General Public * License version 2. This program is licensed "as is" without any @@ -14,6 +13,11 @@ #ifndef __MACH_IRQS_H #define __MACH_IRQS_H +#ifdef CONFIG_ARCH_SPEAR3XX +#define NR_IRQS 256 +#endif + +#ifdef CONFIG_ARCH_SPEAR6XX /* IRQ definitions */ /* VIC 1 */ #define IRQ_VIC_END 64 @@ -21,5 +25,11 @@ /* GPIO pins virtual irqs */ #define VIRTUAL_IRQS 24 #define NR_IRQS (IRQ_VIC_END + VIRTUAL_IRQS) +#endif + +#ifdef CONFIG_ARCH_SPEAR13XX +#define IRQ_GIC_END 160 +#define NR_IRQS IRQ_GIC_END +#endif -#endif /* __MACH_IRQS_H */ +#endif /* __MACH_IRQS_H */ -- cgit v1.1 From 83f230f1121051d58603640535d0384a01605f6c Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Tue, 12 Mar 2013 17:04:40 +0100 Subject: ARM: spear: move identical headers to plat-spear/include/mach As an intermediate step towards unification of the three spear platforms, this gets rid of the mach/* header files that are obviously not platform specific. Signed-off-by: Arnd Bergmann Acked-by: Viresh Kumar --- arch/arm/mach-spear13xx/include/mach/debug-macro.S | 14 ------ arch/arm/mach-spear13xx/include/mach/generic.h | 58 ---------------------- arch/arm/mach-spear13xx/include/mach/hardware.h | 1 - arch/arm/mach-spear13xx/include/mach/irqs.h | 35 ------------- arch/arm/mach-spear13xx/include/mach/timex.h | 19 ------- arch/arm/mach-spear13xx/include/mach/uncompress.h | 19 ------- arch/arm/mach-spear3xx/include/mach/debug-macro.S | 14 ------ arch/arm/mach-spear3xx/include/mach/generic.h | 58 ---------------------- arch/arm/mach-spear3xx/include/mach/hardware.h | 1 - arch/arm/mach-spear3xx/include/mach/irqs.h | 35 ------------- arch/arm/mach-spear3xx/include/mach/timex.h | 19 ------- arch/arm/mach-spear3xx/include/mach/uncompress.h | 19 ------- arch/arm/mach-spear6xx/include/mach/debug-macro.S | 14 ------ arch/arm/mach-spear6xx/include/mach/generic.h | 58 ---------------------- arch/arm/mach-spear6xx/include/mach/hardware.h | 1 - arch/arm/mach-spear6xx/include/mach/irqs.h | 35 ------------- arch/arm/mach-spear6xx/include/mach/timex.h | 19 ------- arch/arm/mach-spear6xx/include/mach/uncompress.h | 19 ------- arch/arm/plat-spear/include/mach/debug-macro.S | 36 ++++++++++++++ arch/arm/plat-spear/include/mach/generic.h | 58 ++++++++++++++++++++++ arch/arm/plat-spear/include/mach/hardware.h | 1 + arch/arm/plat-spear/include/mach/irqs.h | 35 +++++++++++++ arch/arm/plat-spear/include/mach/timex.h | 19 +++++++ arch/arm/plat-spear/include/mach/uncompress.h | 42 ++++++++++++++++ arch/arm/plat-spear/include/plat/debug-macro.S | 36 -------------- arch/arm/plat-spear/include/plat/timex.h | 19 ------- arch/arm/plat-spear/include/plat/uncompress.h | 42 ---------------- 27 files changed, 191 insertions(+), 535 deletions(-) delete mode 100644 arch/arm/mach-spear13xx/include/mach/debug-macro.S delete mode 100644 arch/arm/mach-spear13xx/include/mach/generic.h delete mode 100644 arch/arm/mach-spear13xx/include/mach/hardware.h delete mode 100644 arch/arm/mach-spear13xx/include/mach/irqs.h delete mode 100644 arch/arm/mach-spear13xx/include/mach/timex.h delete mode 100644 arch/arm/mach-spear13xx/include/mach/uncompress.h delete mode 100644 arch/arm/mach-spear3xx/include/mach/debug-macro.S delete mode 100644 arch/arm/mach-spear3xx/include/mach/generic.h delete mode 100644 arch/arm/mach-spear3xx/include/mach/hardware.h delete mode 100644 arch/arm/mach-spear3xx/include/mach/irqs.h delete mode 100644 arch/arm/mach-spear3xx/include/mach/timex.h delete mode 100644 arch/arm/mach-spear3xx/include/mach/uncompress.h delete mode 100644 arch/arm/mach-spear6xx/include/mach/debug-macro.S delete mode 100644 arch/arm/mach-spear6xx/include/mach/generic.h delete mode 100644 arch/arm/mach-spear6xx/include/mach/hardware.h delete mode 100644 arch/arm/mach-spear6xx/include/mach/irqs.h delete mode 100644 arch/arm/mach-spear6xx/include/mach/timex.h delete mode 100644 arch/arm/mach-spear6xx/include/mach/uncompress.h create mode 100644 arch/arm/plat-spear/include/mach/debug-macro.S create mode 100644 arch/arm/plat-spear/include/mach/generic.h create mode 100644 arch/arm/plat-spear/include/mach/hardware.h create mode 100644 arch/arm/plat-spear/include/mach/irqs.h create mode 100644 arch/arm/plat-spear/include/mach/timex.h create mode 100644 arch/arm/plat-spear/include/mach/uncompress.h delete mode 100644 arch/arm/plat-spear/include/plat/debug-macro.S delete mode 100644 arch/arm/plat-spear/include/plat/timex.h delete mode 100644 arch/arm/plat-spear/include/plat/uncompress.h (limited to 'arch/arm') diff --git a/arch/arm/mach-spear13xx/include/mach/debug-macro.S b/arch/arm/mach-spear13xx/include/mach/debug-macro.S deleted file mode 100644 index 9e3ae6b..0000000 --- a/arch/arm/mach-spear13xx/include/mach/debug-macro.S +++ /dev/null @@ -1,14 +0,0 @@ -/* - * arch/arm/mach-spear13xx/include/mach/debug-macro.S - * - * Debugging macro include header spear13xx machine family - * - * Copyright (C) 2012 ST Microelectronics - * Viresh Kumar - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#include diff --git a/arch/arm/mach-spear13xx/include/mach/generic.h b/arch/arm/mach-spear13xx/include/mach/generic.h deleted file mode 100644 index af47d9b..0000000 --- a/arch/arm/mach-spear13xx/include/mach/generic.h +++ /dev/null @@ -1,58 +0,0 @@ -/* - * spear machine family generic header file - * - * Copyright (C) 2009-2012 ST Microelectronics - * Rajeev Kumar - * Viresh Kumar - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#ifndef __MACH_GENERIC_H -#define __MACH_GENERIC_H - -#include -#include -#include -#include - -extern void spear13xx_timer_init(void); -extern void spear3xx_timer_init(void); -extern struct pl022_ssp_controller pl022_plat_data; -extern struct pl08x_platform_data pl080_plat_data; -extern struct dw_dma_platform_data dmac_plat_data; -extern struct dw_dma_slave cf_dma_priv; -extern struct dw_dma_slave nand_read_dma_priv; -extern struct dw_dma_slave nand_write_dma_priv; -bool dw_dma_filter(struct dma_chan *chan, void *slave); - -void __init spear_setup_of_timer(void); -void __init spear3xx_clk_init(void); -void __init spear3xx_map_io(void); -void __init spear3xx_dt_init_irq(void); -void __init spear6xx_clk_init(void); -void __init spear13xx_map_io(void); -void __init spear13xx_l2x0_init(void); - -void spear_restart(char, const char *); - -void spear13xx_secondary_startup(void); -void __cpuinit spear13xx_cpu_die(unsigned int cpu); - -extern struct smp_operations spear13xx_smp_ops; - -#ifdef CONFIG_MACH_SPEAR1310 -void __init spear1310_clk_init(void); -#else -static inline void spear1310_clk_init(void) {} -#endif - -#ifdef CONFIG_MACH_SPEAR1340 -void __init spear1340_clk_init(void); -#else -static inline void spear1340_clk_init(void) {} -#endif - -#endif /* __MACH_GENERIC_H */ diff --git a/arch/arm/mach-spear13xx/include/mach/hardware.h b/arch/arm/mach-spear13xx/include/mach/hardware.h deleted file mode 100644 index 40a8c17..0000000 --- a/arch/arm/mach-spear13xx/include/mach/hardware.h +++ /dev/null @@ -1 +0,0 @@ -/* empty */ diff --git a/arch/arm/mach-spear13xx/include/mach/irqs.h b/arch/arm/mach-spear13xx/include/mach/irqs.h deleted file mode 100644 index 92da0a8..0000000 --- a/arch/arm/mach-spear13xx/include/mach/irqs.h +++ /dev/null @@ -1,35 +0,0 @@ -/* - * IRQ helper macros for spear machine family - * - * Copyright (C) 2009-2012 ST Microelectronics - * Rajeev Kumar - * Viresh Kumar - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#ifndef __MACH_IRQS_H -#define __MACH_IRQS_H - -#ifdef CONFIG_ARCH_SPEAR3XX -#define NR_IRQS 256 -#endif - -#ifdef CONFIG_ARCH_SPEAR6XX -/* IRQ definitions */ -/* VIC 1 */ -#define IRQ_VIC_END 64 - -/* GPIO pins virtual irqs */ -#define VIRTUAL_IRQS 24 -#define NR_IRQS (IRQ_VIC_END + VIRTUAL_IRQS) -#endif - -#ifdef CONFIG_ARCH_SPEAR13XX -#define IRQ_GIC_END 160 -#define NR_IRQS IRQ_GIC_END -#endif - -#endif /* __MACH_IRQS_H */ diff --git a/arch/arm/mach-spear13xx/include/mach/timex.h b/arch/arm/mach-spear13xx/include/mach/timex.h deleted file mode 100644 index 3a58b82..0000000 --- a/arch/arm/mach-spear13xx/include/mach/timex.h +++ /dev/null @@ -1,19 +0,0 @@ -/* - * arch/arm/mach-spear3xx/include/mach/timex.h - * - * SPEAr3XX machine family specific timex definitions - * - * Copyright (C) 2012 ST Microelectronics - * Viresh Kumar - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#ifndef __MACH_TIMEX_H -#define __MACH_TIMEX_H - -#include - -#endif /* __MACH_TIMEX_H */ diff --git a/arch/arm/mach-spear13xx/include/mach/uncompress.h b/arch/arm/mach-spear13xx/include/mach/uncompress.h deleted file mode 100644 index 70fe72f..0000000 --- a/arch/arm/mach-spear13xx/include/mach/uncompress.h +++ /dev/null @@ -1,19 +0,0 @@ -/* - * arch/arm/mach-spear13xx/include/mach/uncompress.h - * - * Serial port stubs for kernel decompress status messages - * - * Copyright (C) 2012 ST Microelectronics - * Viresh Kumar - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#ifndef __MACH_UNCOMPRESS_H -#define __MACH_UNCOMPRESS_H - -#include - -#endif /* __MACH_UNCOMPRESS_H */ diff --git a/arch/arm/mach-spear3xx/include/mach/debug-macro.S b/arch/arm/mach-spear3xx/include/mach/debug-macro.S deleted file mode 100644 index 0a6381f..0000000 --- a/arch/arm/mach-spear3xx/include/mach/debug-macro.S +++ /dev/null @@ -1,14 +0,0 @@ -/* - * arch/arm/mach-spear3xx/include/mach/debug-macro.S - * - * Debugging macro include header spear3xx machine family - * - * Copyright (C) 2009 ST Microelectronics - * Viresh Kumar - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#include diff --git a/arch/arm/mach-spear3xx/include/mach/generic.h b/arch/arm/mach-spear3xx/include/mach/generic.h deleted file mode 100644 index af47d9b..0000000 --- a/arch/arm/mach-spear3xx/include/mach/generic.h +++ /dev/null @@ -1,58 +0,0 @@ -/* - * spear machine family generic header file - * - * Copyright (C) 2009-2012 ST Microelectronics - * Rajeev Kumar - * Viresh Kumar - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#ifndef __MACH_GENERIC_H -#define __MACH_GENERIC_H - -#include -#include -#include -#include - -extern void spear13xx_timer_init(void); -extern void spear3xx_timer_init(void); -extern struct pl022_ssp_controller pl022_plat_data; -extern struct pl08x_platform_data pl080_plat_data; -extern struct dw_dma_platform_data dmac_plat_data; -extern struct dw_dma_slave cf_dma_priv; -extern struct dw_dma_slave nand_read_dma_priv; -extern struct dw_dma_slave nand_write_dma_priv; -bool dw_dma_filter(struct dma_chan *chan, void *slave); - -void __init spear_setup_of_timer(void); -void __init spear3xx_clk_init(void); -void __init spear3xx_map_io(void); -void __init spear3xx_dt_init_irq(void); -void __init spear6xx_clk_init(void); -void __init spear13xx_map_io(void); -void __init spear13xx_l2x0_init(void); - -void spear_restart(char, const char *); - -void spear13xx_secondary_startup(void); -void __cpuinit spear13xx_cpu_die(unsigned int cpu); - -extern struct smp_operations spear13xx_smp_ops; - -#ifdef CONFIG_MACH_SPEAR1310 -void __init spear1310_clk_init(void); -#else -static inline void spear1310_clk_init(void) {} -#endif - -#ifdef CONFIG_MACH_SPEAR1340 -void __init spear1340_clk_init(void); -#else -static inline void spear1340_clk_init(void) {} -#endif - -#endif /* __MACH_GENERIC_H */ diff --git a/arch/arm/mach-spear3xx/include/mach/hardware.h b/arch/arm/mach-spear3xx/include/mach/hardware.h deleted file mode 100644 index 40a8c17..0000000 --- a/arch/arm/mach-spear3xx/include/mach/hardware.h +++ /dev/null @@ -1 +0,0 @@ -/* empty */ diff --git a/arch/arm/mach-spear3xx/include/mach/irqs.h b/arch/arm/mach-spear3xx/include/mach/irqs.h deleted file mode 100644 index 92da0a8..0000000 --- a/arch/arm/mach-spear3xx/include/mach/irqs.h +++ /dev/null @@ -1,35 +0,0 @@ -/* - * IRQ helper macros for spear machine family - * - * Copyright (C) 2009-2012 ST Microelectronics - * Rajeev Kumar - * Viresh Kumar - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#ifndef __MACH_IRQS_H -#define __MACH_IRQS_H - -#ifdef CONFIG_ARCH_SPEAR3XX -#define NR_IRQS 256 -#endif - -#ifdef CONFIG_ARCH_SPEAR6XX -/* IRQ definitions */ -/* VIC 1 */ -#define IRQ_VIC_END 64 - -/* GPIO pins virtual irqs */ -#define VIRTUAL_IRQS 24 -#define NR_IRQS (IRQ_VIC_END + VIRTUAL_IRQS) -#endif - -#ifdef CONFIG_ARCH_SPEAR13XX -#define IRQ_GIC_END 160 -#define NR_IRQS IRQ_GIC_END -#endif - -#endif /* __MACH_IRQS_H */ diff --git a/arch/arm/mach-spear3xx/include/mach/timex.h b/arch/arm/mach-spear3xx/include/mach/timex.h deleted file mode 100644 index 9f5d08b..0000000 --- a/arch/arm/mach-spear3xx/include/mach/timex.h +++ /dev/null @@ -1,19 +0,0 @@ -/* - * arch/arm/mach-spear3xx/include/mach/timex.h - * - * SPEAr3XX machine family specific timex definitions - * - * Copyright (C) 2009 ST Microelectronics - * Viresh Kumar - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#ifndef __MACH_TIMEX_H -#define __MACH_TIMEX_H - -#include - -#endif /* __MACH_TIMEX_H */ diff --git a/arch/arm/mach-spear3xx/include/mach/uncompress.h b/arch/arm/mach-spear3xx/include/mach/uncompress.h deleted file mode 100644 index b909b01..0000000 --- a/arch/arm/mach-spear3xx/include/mach/uncompress.h +++ /dev/null @@ -1,19 +0,0 @@ -/* - * arch/arm/mach-spear3xx/include/mach/uncompress.h - * - * Serial port stubs for kernel decompress status messages - * - * Copyright (C) 2009 ST Microelectronics - * Viresh Kumar - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#ifndef __MACH_UNCOMPRESS_H -#define __MACH_UNCOMPRESS_H - -#include - -#endif /* __MACH_UNCOMPRESS_H */ diff --git a/arch/arm/mach-spear6xx/include/mach/debug-macro.S b/arch/arm/mach-spear6xx/include/mach/debug-macro.S deleted file mode 100644 index 0f3ea39..0000000 --- a/arch/arm/mach-spear6xx/include/mach/debug-macro.S +++ /dev/null @@ -1,14 +0,0 @@ -/* - * arch/arm/mach-spear6xx/include/mach/debug-macro.S - * - * Debugging macro include header for SPEAr6xx machine family - * - * Copyright (C) 2009 ST Microelectronics - * Rajeev Kumar - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#include diff --git a/arch/arm/mach-spear6xx/include/mach/generic.h b/arch/arm/mach-spear6xx/include/mach/generic.h deleted file mode 100644 index af47d9b..0000000 --- a/arch/arm/mach-spear6xx/include/mach/generic.h +++ /dev/null @@ -1,58 +0,0 @@ -/* - * spear machine family generic header file - * - * Copyright (C) 2009-2012 ST Microelectronics - * Rajeev Kumar - * Viresh Kumar - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#ifndef __MACH_GENERIC_H -#define __MACH_GENERIC_H - -#include -#include -#include -#include - -extern void spear13xx_timer_init(void); -extern void spear3xx_timer_init(void); -extern struct pl022_ssp_controller pl022_plat_data; -extern struct pl08x_platform_data pl080_plat_data; -extern struct dw_dma_platform_data dmac_plat_data; -extern struct dw_dma_slave cf_dma_priv; -extern struct dw_dma_slave nand_read_dma_priv; -extern struct dw_dma_slave nand_write_dma_priv; -bool dw_dma_filter(struct dma_chan *chan, void *slave); - -void __init spear_setup_of_timer(void); -void __init spear3xx_clk_init(void); -void __init spear3xx_map_io(void); -void __init spear3xx_dt_init_irq(void); -void __init spear6xx_clk_init(void); -void __init spear13xx_map_io(void); -void __init spear13xx_l2x0_init(void); - -void spear_restart(char, const char *); - -void spear13xx_secondary_startup(void); -void __cpuinit spear13xx_cpu_die(unsigned int cpu); - -extern struct smp_operations spear13xx_smp_ops; - -#ifdef CONFIG_MACH_SPEAR1310 -void __init spear1310_clk_init(void); -#else -static inline void spear1310_clk_init(void) {} -#endif - -#ifdef CONFIG_MACH_SPEAR1340 -void __init spear1340_clk_init(void); -#else -static inline void spear1340_clk_init(void) {} -#endif - -#endif /* __MACH_GENERIC_H */ diff --git a/arch/arm/mach-spear6xx/include/mach/hardware.h b/arch/arm/mach-spear6xx/include/mach/hardware.h deleted file mode 100644 index 40a8c17..0000000 --- a/arch/arm/mach-spear6xx/include/mach/hardware.h +++ /dev/null @@ -1 +0,0 @@ -/* empty */ diff --git a/arch/arm/mach-spear6xx/include/mach/irqs.h b/arch/arm/mach-spear6xx/include/mach/irqs.h deleted file mode 100644 index 92da0a8..0000000 --- a/arch/arm/mach-spear6xx/include/mach/irqs.h +++ /dev/null @@ -1,35 +0,0 @@ -/* - * IRQ helper macros for spear machine family - * - * Copyright (C) 2009-2012 ST Microelectronics - * Rajeev Kumar - * Viresh Kumar - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#ifndef __MACH_IRQS_H -#define __MACH_IRQS_H - -#ifdef CONFIG_ARCH_SPEAR3XX -#define NR_IRQS 256 -#endif - -#ifdef CONFIG_ARCH_SPEAR6XX -/* IRQ definitions */ -/* VIC 1 */ -#define IRQ_VIC_END 64 - -/* GPIO pins virtual irqs */ -#define VIRTUAL_IRQS 24 -#define NR_IRQS (IRQ_VIC_END + VIRTUAL_IRQS) -#endif - -#ifdef CONFIG_ARCH_SPEAR13XX -#define IRQ_GIC_END 160 -#define NR_IRQS IRQ_GIC_END -#endif - -#endif /* __MACH_IRQS_H */ diff --git a/arch/arm/mach-spear6xx/include/mach/timex.h b/arch/arm/mach-spear6xx/include/mach/timex.h deleted file mode 100644 index ac1c5b0..0000000 --- a/arch/arm/mach-spear6xx/include/mach/timex.h +++ /dev/null @@ -1,19 +0,0 @@ -/* - * arch/arm/mach-spear6xx/include/mach/timex.h - * - * SPEAr6XX machine family specific timex definitions - * - * Copyright (C) 2009 ST Microelectronics - * Rajeev Kumar - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#ifndef __MACH_TIMEX_H -#define __MACH_TIMEX_H - -#include - -#endif /* __MACH_TIMEX_H */ diff --git a/arch/arm/mach-spear6xx/include/mach/uncompress.h b/arch/arm/mach-spear6xx/include/mach/uncompress.h deleted file mode 100644 index 77f0765..0000000 --- a/arch/arm/mach-spear6xx/include/mach/uncompress.h +++ /dev/null @@ -1,19 +0,0 @@ -/* - * arch/arm/mach-spear6xx/include/mach/uncompress.h - * - * Serial port stubs for kernel decompress status messages - * - * Copyright (C) 2009 ST Microelectronics - * Rajeev Kumar - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#ifndef __MACH_UNCOMPRESS_H -#define __MACH_UNCOMPRESS_H - -#include - -#endif /* __MACH_UNCOMPRESS_H */ diff --git a/arch/arm/plat-spear/include/mach/debug-macro.S b/arch/arm/plat-spear/include/mach/debug-macro.S new file mode 100644 index 0000000..75b05ad --- /dev/null +++ b/arch/arm/plat-spear/include/mach/debug-macro.S @@ -0,0 +1,36 @@ +/* + * arch/arm/plat-spear/include/plat/debug-macro.S + * + * Debugging macro include header for spear platform + * + * Copyright (C) 2009 ST Microelectronics + * Viresh Kumar + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include +#include + + .macro addruart, rp, rv, tmp + mov \rp, #SPEAR_DBG_UART_BASE @ Physical base + mov \rv, #VA_SPEAR_DBG_UART_BASE @ Virtual base + .endm + + .macro senduart, rd, rx + strb \rd, [\rx, #UART01x_DR] @ ASC_TX_BUFFER + .endm + + .macro waituart, rd, rx +1001: ldr \rd, [\rx, #UART01x_FR] @ FLAG REGISTER + tst \rd, #UART01x_FR_TXFF @ TX_FULL + bne 1001b + .endm + + .macro busyuart, rd, rx +1002: ldr \rd, [\rx, #UART01x_FR] @ FLAG REGISTER + tst \rd, #UART011_FR_TXFE @ TX_EMPTY + beq 1002b + .endm diff --git a/arch/arm/plat-spear/include/mach/generic.h b/arch/arm/plat-spear/include/mach/generic.h new file mode 100644 index 0000000..af47d9b --- /dev/null +++ b/arch/arm/plat-spear/include/mach/generic.h @@ -0,0 +1,58 @@ +/* + * spear machine family generic header file + * + * Copyright (C) 2009-2012 ST Microelectronics + * Rajeev Kumar + * Viresh Kumar + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __MACH_GENERIC_H +#define __MACH_GENERIC_H + +#include +#include +#include +#include + +extern void spear13xx_timer_init(void); +extern void spear3xx_timer_init(void); +extern struct pl022_ssp_controller pl022_plat_data; +extern struct pl08x_platform_data pl080_plat_data; +extern struct dw_dma_platform_data dmac_plat_data; +extern struct dw_dma_slave cf_dma_priv; +extern struct dw_dma_slave nand_read_dma_priv; +extern struct dw_dma_slave nand_write_dma_priv; +bool dw_dma_filter(struct dma_chan *chan, void *slave); + +void __init spear_setup_of_timer(void); +void __init spear3xx_clk_init(void); +void __init spear3xx_map_io(void); +void __init spear3xx_dt_init_irq(void); +void __init spear6xx_clk_init(void); +void __init spear13xx_map_io(void); +void __init spear13xx_l2x0_init(void); + +void spear_restart(char, const char *); + +void spear13xx_secondary_startup(void); +void __cpuinit spear13xx_cpu_die(unsigned int cpu); + +extern struct smp_operations spear13xx_smp_ops; + +#ifdef CONFIG_MACH_SPEAR1310 +void __init spear1310_clk_init(void); +#else +static inline void spear1310_clk_init(void) {} +#endif + +#ifdef CONFIG_MACH_SPEAR1340 +void __init spear1340_clk_init(void); +#else +static inline void spear1340_clk_init(void) {} +#endif + +#endif /* __MACH_GENERIC_H */ diff --git a/arch/arm/plat-spear/include/mach/hardware.h b/arch/arm/plat-spear/include/mach/hardware.h new file mode 100644 index 0000000..40a8c17 --- /dev/null +++ b/arch/arm/plat-spear/include/mach/hardware.h @@ -0,0 +1 @@ +/* empty */ diff --git a/arch/arm/plat-spear/include/mach/irqs.h b/arch/arm/plat-spear/include/mach/irqs.h new file mode 100644 index 0000000..92da0a8 --- /dev/null +++ b/arch/arm/plat-spear/include/mach/irqs.h @@ -0,0 +1,35 @@ +/* + * IRQ helper macros for spear machine family + * + * Copyright (C) 2009-2012 ST Microelectronics + * Rajeev Kumar + * Viresh Kumar + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __MACH_IRQS_H +#define __MACH_IRQS_H + +#ifdef CONFIG_ARCH_SPEAR3XX +#define NR_IRQS 256 +#endif + +#ifdef CONFIG_ARCH_SPEAR6XX +/* IRQ definitions */ +/* VIC 1 */ +#define IRQ_VIC_END 64 + +/* GPIO pins virtual irqs */ +#define VIRTUAL_IRQS 24 +#define NR_IRQS (IRQ_VIC_END + VIRTUAL_IRQS) +#endif + +#ifdef CONFIG_ARCH_SPEAR13XX +#define IRQ_GIC_END 160 +#define NR_IRQS IRQ_GIC_END +#endif + +#endif /* __MACH_IRQS_H */ diff --git a/arch/arm/plat-spear/include/mach/timex.h b/arch/arm/plat-spear/include/mach/timex.h new file mode 100644 index 0000000..ef95e5b --- /dev/null +++ b/arch/arm/plat-spear/include/mach/timex.h @@ -0,0 +1,19 @@ +/* + * arch/arm/plat-spear/include/plat/timex.h + * + * SPEAr platform specific timex definitions + * + * Copyright (C) 2009 ST Microelectronics + * Viresh Kumar + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __PLAT_TIMEX_H +#define __PLAT_TIMEX_H + +#define CLOCK_TICK_RATE 48000000 + +#endif /* __PLAT_TIMEX_H */ diff --git a/arch/arm/plat-spear/include/mach/uncompress.h b/arch/arm/plat-spear/include/mach/uncompress.h new file mode 100644 index 0000000..51b2dc9 --- /dev/null +++ b/arch/arm/plat-spear/include/mach/uncompress.h @@ -0,0 +1,42 @@ +/* + * arch/arm/plat-spear/include/plat/uncompress.h + * + * Serial port stubs for kernel decompress status messages + * + * Copyright (C) 2009 ST Microelectronics + * Viresh Kumar + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include +#include +#include + +#ifndef __PLAT_UNCOMPRESS_H +#define __PLAT_UNCOMPRESS_H +/* + * This does not append a newline + */ +static inline void putc(int c) +{ + void __iomem *base = (void __iomem *)SPEAR_DBG_UART_BASE; + + while (readl_relaxed(base + UART01x_FR) & UART01x_FR_TXFF) + barrier(); + + writel_relaxed(c, base + UART01x_DR); +} + +static inline void flush(void) +{ +} + +/* + * nothing to do + */ +#define arch_decomp_setup() + +#endif /* __PLAT_UNCOMPRESS_H */ diff --git a/arch/arm/plat-spear/include/plat/debug-macro.S b/arch/arm/plat-spear/include/plat/debug-macro.S deleted file mode 100644 index 75b05ad..0000000 --- a/arch/arm/plat-spear/include/plat/debug-macro.S +++ /dev/null @@ -1,36 +0,0 @@ -/* - * arch/arm/plat-spear/include/plat/debug-macro.S - * - * Debugging macro include header for spear platform - * - * Copyright (C) 2009 ST Microelectronics - * Viresh Kumar - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#include -#include - - .macro addruart, rp, rv, tmp - mov \rp, #SPEAR_DBG_UART_BASE @ Physical base - mov \rv, #VA_SPEAR_DBG_UART_BASE @ Virtual base - .endm - - .macro senduart, rd, rx - strb \rd, [\rx, #UART01x_DR] @ ASC_TX_BUFFER - .endm - - .macro waituart, rd, rx -1001: ldr \rd, [\rx, #UART01x_FR] @ FLAG REGISTER - tst \rd, #UART01x_FR_TXFF @ TX_FULL - bne 1001b - .endm - - .macro busyuart, rd, rx -1002: ldr \rd, [\rx, #UART01x_FR] @ FLAG REGISTER - tst \rd, #UART011_FR_TXFE @ TX_EMPTY - beq 1002b - .endm diff --git a/arch/arm/plat-spear/include/plat/timex.h b/arch/arm/plat-spear/include/plat/timex.h deleted file mode 100644 index ef95e5b..0000000 --- a/arch/arm/plat-spear/include/plat/timex.h +++ /dev/null @@ -1,19 +0,0 @@ -/* - * arch/arm/plat-spear/include/plat/timex.h - * - * SPEAr platform specific timex definitions - * - * Copyright (C) 2009 ST Microelectronics - * Viresh Kumar - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#ifndef __PLAT_TIMEX_H -#define __PLAT_TIMEX_H - -#define CLOCK_TICK_RATE 48000000 - -#endif /* __PLAT_TIMEX_H */ diff --git a/arch/arm/plat-spear/include/plat/uncompress.h b/arch/arm/plat-spear/include/plat/uncompress.h deleted file mode 100644 index 51b2dc9..0000000 --- a/arch/arm/plat-spear/include/plat/uncompress.h +++ /dev/null @@ -1,42 +0,0 @@ -/* - * arch/arm/plat-spear/include/plat/uncompress.h - * - * Serial port stubs for kernel decompress status messages - * - * Copyright (C) 2009 ST Microelectronics - * Viresh Kumar - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#include -#include -#include - -#ifndef __PLAT_UNCOMPRESS_H -#define __PLAT_UNCOMPRESS_H -/* - * This does not append a newline - */ -static inline void putc(int c) -{ - void __iomem *base = (void __iomem *)SPEAR_DBG_UART_BASE; - - while (readl_relaxed(base + UART01x_FR) & UART01x_FR_TXFF) - barrier(); - - writel_relaxed(c, base + UART01x_DR); -} - -static inline void flush(void) -{ -} - -/* - * nothing to do - */ -#define arch_decomp_setup() - -#endif /* __PLAT_UNCOMPRESS_H */ -- cgit v1.1 From d42799b7827bcb92c47de26f900e75885bcb447b Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Sun, 2 Dec 2012 14:45:27 +0100 Subject: ARM: spear: make spear3xx/6xx mach/spear.h files identical The two files are almost identical already basically just differ in the identifier names. By changing the identifiers to be the same, we are able to merge the two as a preparation to building a combined kernel. Signed-off-by: Arnd Bergmann Acked-by: Viresh Kumar --- arch/arm/mach-spear3xx/include/mach/misc_regs.h | 2 +- arch/arm/mach-spear3xx/include/mach/spear.h | 47 ++++++++++--------- arch/arm/mach-spear3xx/spear300.c | 2 +- arch/arm/mach-spear3xx/spear310.c | 2 +- arch/arm/mach-spear3xx/spear320.c | 2 +- arch/arm/mach-spear3xx/spear3xx.c | 8 ++-- arch/arm/mach-spear6xx/include/mach/misc_regs.h | 2 +- arch/arm/mach-spear6xx/include/mach/spear.h | 61 +++++++++++++++---------- arch/arm/mach-spear6xx/spear6xx.c | 12 ++--- 9 files changed, 75 insertions(+), 63 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-spear3xx/include/mach/misc_regs.h b/arch/arm/mach-spear3xx/include/mach/misc_regs.h index 6309bf6..075812c 100644 --- a/arch/arm/mach-spear3xx/include/mach/misc_regs.h +++ b/arch/arm/mach-spear3xx/include/mach/misc_regs.h @@ -16,7 +16,7 @@ #include -#define MISC_BASE IOMEM(VA_SPEAR3XX_ICM3_MISC_REG_BASE) +#define MISC_BASE IOMEM(VA_SPEAR_ICM3_MISC_REG_BASE) #define DMA_CHN_CFG (MISC_BASE + 0x0A0) #endif /* __MACH_MISC_REGS_H */ diff --git a/arch/arm/mach-spear3xx/include/mach/spear.h b/arch/arm/mach-spear3xx/include/mach/spear.h index 8cca951..ee5a774 100644 --- a/arch/arm/mach-spear3xx/include/mach/spear.h +++ b/arch/arm/mach-spear3xx/include/mach/spear.h @@ -1,9 +1,8 @@ /* - * arch/arm/mach-spear3xx/include/mach/spear.h + * SPEAr3xx/6xx Machine family specific definition * - * SPEAr3xx Machine family specific definition - * - * Copyright (C) 2009 ST Microelectronics + * Copyright (C) 2009,2012 ST Microelectronics + * Rajeev Kumar * Viresh Kumar * * This file is licensed under the terms of the GNU General Public @@ -11,38 +10,38 @@ * warranty of any kind, whether express or implied. */ -#ifndef __MACH_SPEAR3XX_H -#define __MACH_SPEAR3XX_H +#ifndef __MACH_SPEAR_H +#define __MACH_SPEAR_H #include /* ICM1 - Low speed connection */ -#define SPEAR3XX_ICM1_2_BASE UL(0xD0000000) -#define VA_SPEAR3XX_ICM1_2_BASE UL(0xFD000000) -#define SPEAR3XX_ICM1_UART_BASE UL(0xD0000000) -#define VA_SPEAR3XX_ICM1_UART_BASE (VA_SPEAR3XX_ICM1_2_BASE | SPEAR3XX_ICM1_UART_BASE) +#define SPEAR_ICM1_2_BASE UL(0xD0000000) +#define VA_SPEAR_ICM1_2_BASE UL(0xFD000000) +#define SPEAR_ICM1_UART_BASE UL(0xD0000000) +#define VA_SPEAR_ICM1_UART_BASE (VA_SPEAR_ICM1_2_BASE | SPEAR_ICM1_UART_BASE) #define SPEAR3XX_ICM1_SSP_BASE UL(0xD0100000) -/* ML1 - Multi Layer CPU Subsystem */ -#define SPEAR3XX_ICM3_ML1_2_BASE UL(0xF0000000) +/* ML-1, 2 - Multi Layer CPU Subsystem */ +#define SPEAR_ICM3_ML1_2_BASE UL(0xF0000000) #define VA_SPEAR6XX_ML_CPU_BASE UL(0xF0000000) /* ICM3 - Basic Subsystem */ -#define SPEAR3XX_ICM3_SMI_CTRL_BASE UL(0xFC000000) -#define VA_SPEAR3XX_ICM3_SMI_CTRL_BASE UL(0xFC000000) -#define SPEAR3XX_ICM3_DMA_BASE UL(0xFC400000) -#define SPEAR3XX_ICM3_SYS_CTRL_BASE UL(0xFCA00000) -#define VA_SPEAR3XX_ICM3_SYS_CTRL_BASE (VA_SPEAR3XX_ICM3_SMI_CTRL_BASE | SPEAR3XX_ICM3_SYS_CTRL_BASE) -#define SPEAR3XX_ICM3_MISC_REG_BASE UL(0xFCA80000) -#define VA_SPEAR3XX_ICM3_MISC_REG_BASE (VA_SPEAR3XX_ICM3_SMI_CTRL_BASE | SPEAR3XX_ICM3_MISC_REG_BASE) +#define SPEAR_ICM3_SMI_CTRL_BASE UL(0xFC000000) +#define VA_SPEAR_ICM3_SMI_CTRL_BASE UL(0xFC000000) +#define SPEAR_ICM3_DMA_BASE UL(0xFC400000) +#define SPEAR_ICM3_SYS_CTRL_BASE UL(0xFCA00000) +#define VA_SPEAR_ICM3_SYS_CTRL_BASE (VA_SPEAR_ICM3_SMI_CTRL_BASE | SPEAR_ICM3_SYS_CTRL_BASE) +#define SPEAR_ICM3_MISC_REG_BASE UL(0xFCA80000) +#define VA_SPEAR_ICM3_MISC_REG_BASE (VA_SPEAR_ICM3_SMI_CTRL_BASE | SPEAR_ICM3_MISC_REG_BASE) /* Debug uart for linux, will be used for debug and uncompress messages */ -#define SPEAR_DBG_UART_BASE SPEAR3XX_ICM1_UART_BASE -#define VA_SPEAR_DBG_UART_BASE VA_SPEAR3XX_ICM1_UART_BASE +#define SPEAR_DBG_UART_BASE SPEAR_ICM1_UART_BASE +#define VA_SPEAR_DBG_UART_BASE VA_SPEAR_ICM1_UART_BASE /* Sysctl base for spear platform */ -#define SPEAR_SYS_CTRL_BASE SPEAR3XX_ICM3_SYS_CTRL_BASE -#define VA_SPEAR_SYS_CTRL_BASE VA_SPEAR3XX_ICM3_SYS_CTRL_BASE +#define SPEAR_SYS_CTRL_BASE SPEAR_ICM3_SYS_CTRL_BASE +#define VA_SPEAR_SYS_CTRL_BASE VA_SPEAR_ICM3_SYS_CTRL_BASE /* SPEAr320 Macros */ #define SPEAR320_SOC_CONFIG_BASE UL(0xB3000000) @@ -57,4 +56,4 @@ #define SPEAR320_UART6_PCLK_SHIFT 12 #define SPEAR320_RS485_PCLK_SHIFT 13 -#endif /* __MACH_SPEAR3XX_H */ +#endif /* __MACH_SPEAR_H */ diff --git a/arch/arm/mach-spear3xx/spear300.c b/arch/arm/mach-spear3xx/spear300.c index bbc9b7e..72449ee 100644 --- a/arch/arm/mach-spear3xx/spear300.c +++ b/arch/arm/mach-spear3xx/spear300.c @@ -185,7 +185,7 @@ struct pl08x_channel_data spear300_dma_info[] = { static struct of_dev_auxdata spear300_auxdata_lookup[] __initdata = { OF_DEV_AUXDATA("arm,pl022", SPEAR3XX_ICM1_SSP_BASE, NULL, &pl022_plat_data), - OF_DEV_AUXDATA("arm,pl080", SPEAR3XX_ICM3_DMA_BASE, NULL, + OF_DEV_AUXDATA("arm,pl080", SPEAR_ICM3_DMA_BASE, NULL, &pl080_plat_data), {} }; diff --git a/arch/arm/mach-spear3xx/spear310.c b/arch/arm/mach-spear3xx/spear310.c index c13a434..0b7962d 100644 --- a/arch/arm/mach-spear3xx/spear310.c +++ b/arch/arm/mach-spear3xx/spear310.c @@ -217,7 +217,7 @@ static struct amba_pl011_data spear310_uart_data[] = { static struct of_dev_auxdata spear310_auxdata_lookup[] __initdata = { OF_DEV_AUXDATA("arm,pl022", SPEAR3XX_ICM1_SSP_BASE, NULL, &pl022_plat_data), - OF_DEV_AUXDATA("arm,pl080", SPEAR3XX_ICM3_DMA_BASE, NULL, + OF_DEV_AUXDATA("arm,pl080", SPEAR_ICM3_DMA_BASE, NULL, &pl080_plat_data), OF_DEV_AUXDATA("arm,pl011", SPEAR310_UART1_BASE, NULL, &spear310_uart_data[0]), diff --git a/arch/arm/mach-spear3xx/spear320.c b/arch/arm/mach-spear3xx/spear320.c index f671a0a..e9db7db 100644 --- a/arch/arm/mach-spear3xx/spear320.c +++ b/arch/arm/mach-spear3xx/spear320.c @@ -223,7 +223,7 @@ static struct amba_pl011_data spear320_uart_data[] = { static struct of_dev_auxdata spear320_auxdata_lookup[] __initdata = { OF_DEV_AUXDATA("arm,pl022", SPEAR3XX_ICM1_SSP_BASE, NULL, &pl022_plat_data), - OF_DEV_AUXDATA("arm,pl080", SPEAR3XX_ICM3_DMA_BASE, NULL, + OF_DEV_AUXDATA("arm,pl080", SPEAR_ICM3_DMA_BASE, NULL, &pl080_plat_data), OF_DEV_AUXDATA("arm,pl022", SPEAR320_SSP0_BASE, NULL, &spear320_ssp_data[0]), diff --git a/arch/arm/mach-spear3xx/spear3xx.c b/arch/arm/mach-spear3xx/spear3xx.c index 72e3ae7..d7580f2 100644 --- a/arch/arm/mach-spear3xx/spear3xx.c +++ b/arch/arm/mach-spear3xx/spear3xx.c @@ -67,13 +67,13 @@ struct pl08x_platform_data pl080_plat_data = { */ struct map_desc spear3xx_io_desc[] __initdata = { { - .virtual = VA_SPEAR3XX_ICM1_2_BASE, - .pfn = __phys_to_pfn(SPEAR3XX_ICM1_2_BASE), + .virtual = VA_SPEAR_ICM1_2_BASE, + .pfn = __phys_to_pfn(SPEAR_ICM1_2_BASE), .length = SZ_16M, .type = MT_DEVICE }, { - .virtual = VA_SPEAR3XX_ICM3_SMI_CTRL_BASE, - .pfn = __phys_to_pfn(SPEAR3XX_ICM3_SMI_CTRL_BASE), + .virtual = VA_SPEAR_ICM3_SMI_CTRL_BASE, + .pfn = __phys_to_pfn(SPEAR_ICM3_SMI_CTRL_BASE), .length = SZ_16M, .type = MT_DEVICE }, diff --git a/arch/arm/mach-spear6xx/include/mach/misc_regs.h b/arch/arm/mach-spear6xx/include/mach/misc_regs.h index c34acc2..28aa508 100644 --- a/arch/arm/mach-spear6xx/include/mach/misc_regs.h +++ b/arch/arm/mach-spear6xx/include/mach/misc_regs.h @@ -16,7 +16,7 @@ #include -#define MISC_BASE IOMEM(VA_SPEAR6XX_ICM3_MISC_REG_BASE) +#define MISC_BASE IOMEM(VA_SPEAR_ICM3_MISC_REG_BASE) #define DMA_CHN_CFG (MISC_BASE + 0x0A0) #endif /* __MACH_MISC_REGS_H */ diff --git a/arch/arm/mach-spear6xx/include/mach/spear.h b/arch/arm/mach-spear6xx/include/mach/spear.h index cb8ed2f..ee5a774 100644 --- a/arch/arm/mach-spear6xx/include/mach/spear.h +++ b/arch/arm/mach-spear6xx/include/mach/spear.h @@ -1,46 +1,59 @@ /* - * arch/arm/mach-spear6xx/include/mach/spear.h + * SPEAr3xx/6xx Machine family specific definition * - * SPEAr6xx Machine family specific definition - * - * Copyright (C) 2009 ST Microelectronics + * Copyright (C) 2009,2012 ST Microelectronics * Rajeev Kumar + * Viresh Kumar * * This file is licensed under the terms of the GNU General Public * License version 2. This program is licensed "as is" without any * warranty of any kind, whether express or implied. */ -#ifndef __MACH_SPEAR6XX_H -#define __MACH_SPEAR6XX_H +#ifndef __MACH_SPEAR_H +#define __MACH_SPEAR_H #include /* ICM1 - Low speed connection */ -#define SPEAR6XX_ICM1_BASE UL(0xD0000000) -#define VA_SPEAR6XX_ICM1_BASE UL(0xFD000000) -#define SPEAR6XX_ICM1_UART0_BASE UL(0xD0000000) -#define VA_SPEAR6XX_ICM1_UART0_BASE (VA_SPEAR6XX_ICM1_2_BASE | SPEAR6XX_ICM1_UART0_BASE) +#define SPEAR_ICM1_2_BASE UL(0xD0000000) +#define VA_SPEAR_ICM1_2_BASE UL(0xFD000000) +#define SPEAR_ICM1_UART_BASE UL(0xD0000000) +#define VA_SPEAR_ICM1_UART_BASE (VA_SPEAR_ICM1_2_BASE | SPEAR_ICM1_UART_BASE) +#define SPEAR3XX_ICM1_SSP_BASE UL(0xD0100000) /* ML-1, 2 - Multi Layer CPU Subsystem */ -#define SPEAR6XX_ML_CPU_BASE UL(0xF0000000) +#define SPEAR_ICM3_ML1_2_BASE UL(0xF0000000) #define VA_SPEAR6XX_ML_CPU_BASE UL(0xF0000000) /* ICM3 - Basic Subsystem */ -#define SPEAR6XX_ICM3_SMI_CTRL_BASE UL(0xFC000000) -#define VA_SPEAR6XX_ICM3_SMI_CTRL_BASE UL(0xFC000000) -#define SPEAR6XX_ICM3_DMA_BASE UL(0xFC400000) -#define SPEAR6XX_ICM3_SYS_CTRL_BASE UL(0xFCA00000) -#define VA_SPEAR6XX_ICM3_SYS_CTRL_BASE (VA_SPEAR6XX_ICM3_SMI_CTRL_BASE | SPEAR6XX_ICM3_SYS_CTRL_BASE) -#define SPEAR6XX_ICM3_MISC_REG_BASE UL(0xFCA80000) -#define VA_SPEAR6XX_ICM3_MISC_REG_BASE (VA_SPEAR6XX_ICM3_SMI_CTRL_BASE | SPEAR6XX_ICM3_MISC_REG_BASE) +#define SPEAR_ICM3_SMI_CTRL_BASE UL(0xFC000000) +#define VA_SPEAR_ICM3_SMI_CTRL_BASE UL(0xFC000000) +#define SPEAR_ICM3_DMA_BASE UL(0xFC400000) +#define SPEAR_ICM3_SYS_CTRL_BASE UL(0xFCA00000) +#define VA_SPEAR_ICM3_SYS_CTRL_BASE (VA_SPEAR_ICM3_SMI_CTRL_BASE | SPEAR_ICM3_SYS_CTRL_BASE) +#define SPEAR_ICM3_MISC_REG_BASE UL(0xFCA80000) +#define VA_SPEAR_ICM3_MISC_REG_BASE (VA_SPEAR_ICM3_SMI_CTRL_BASE | SPEAR_ICM3_MISC_REG_BASE) /* Debug uart for linux, will be used for debug and uncompress messages */ -#define SPEAR_DBG_UART_BASE SPEAR6XX_ICM1_UART0_BASE -#define VA_SPEAR_DBG_UART_BASE VA_SPEAR6XX_ICM1_UART0_BASE +#define SPEAR_DBG_UART_BASE SPEAR_ICM1_UART_BASE +#define VA_SPEAR_DBG_UART_BASE VA_SPEAR_ICM1_UART_BASE /* Sysctl base for spear platform */ -#define SPEAR_SYS_CTRL_BASE SPEAR6XX_ICM3_SYS_CTRL_BASE -#define VA_SPEAR_SYS_CTRL_BASE VA_SPEAR6XX_ICM3_SYS_CTRL_BASE - -#endif /* __MACH_SPEAR6XX_H */ +#define SPEAR_SYS_CTRL_BASE SPEAR_ICM3_SYS_CTRL_BASE +#define VA_SPEAR_SYS_CTRL_BASE VA_SPEAR_ICM3_SYS_CTRL_BASE + +/* SPEAr320 Macros */ +#define SPEAR320_SOC_CONFIG_BASE UL(0xB3000000) +#define VA_SPEAR320_SOC_CONFIG_BASE UL(0xFE000000) +#define SPEAR320_CONTROL_REG IOMEM(VA_SPEAR320_SOC_CONFIG_BASE) +#define SPEAR320_EXT_CTRL_REG IOMEM(VA_SPEAR320_SOC_CONFIG_BASE + 0x0018) + #define SPEAR320_UARTX_PCLK_MASK 0x1 + #define SPEAR320_UART2_PCLK_SHIFT 8 + #define SPEAR320_UART3_PCLK_SHIFT 9 + #define SPEAR320_UART4_PCLK_SHIFT 10 + #define SPEAR320_UART5_PCLK_SHIFT 11 + #define SPEAR320_UART6_PCLK_SHIFT 12 + #define SPEAR320_RS485_PCLK_SHIFT 13 + +#endif /* __MACH_SPEAR_H */ diff --git a/arch/arm/mach-spear6xx/spear6xx.c b/arch/arm/mach-spear6xx/spear6xx.c index 8904d8a..97fb31d 100644 --- a/arch/arm/mach-spear6xx/spear6xx.c +++ b/arch/arm/mach-spear6xx/spear6xx.c @@ -351,17 +351,17 @@ struct pl08x_platform_data pl080_plat_data = { struct map_desc spear6xx_io_desc[] __initdata = { { .virtual = VA_SPEAR6XX_ML_CPU_BASE, - .pfn = __phys_to_pfn(SPEAR6XX_ML_CPU_BASE), + .pfn = __phys_to_pfn(SPEAR_ICM3_ML1_2_BASE), .length = 2 * SZ_16M, .type = MT_DEVICE }, { - .virtual = VA_SPEAR6XX_ICM1_BASE, - .pfn = __phys_to_pfn(SPEAR6XX_ICM1_BASE), + .virtual = VA_SPEAR_ICM1_2_BASE, + .pfn = __phys_to_pfn(SPEAR_ICM1_2_BASE), .length = SZ_16M, .type = MT_DEVICE }, { - .virtual = VA_SPEAR6XX_ICM3_SMI_CTRL_BASE, - .pfn = __phys_to_pfn(SPEAR6XX_ICM3_SMI_CTRL_BASE), + .virtual = VA_SPEAR_ICM3_SMI_CTRL_BASE, + .pfn = __phys_to_pfn(SPEAR_ICM3_SMI_CTRL_BASE), .length = SZ_16M, .type = MT_DEVICE }, @@ -404,7 +404,7 @@ void __init spear6xx_timer_init(void) /* Add auxdata to pass platform data */ struct of_dev_auxdata spear6xx_auxdata_lookup[] __initdata = { - OF_DEV_AUXDATA("arm,pl080", SPEAR6XX_ICM3_DMA_BASE, NULL, + OF_DEV_AUXDATA("arm,pl080", SPEAR_ICM3_DMA_BASE, NULL, &pl080_plat_data), {} }; -- cgit v1.1 From 4b6effb6ff38aab60d224cefba76b016552f8bf8 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Sun, 2 Dec 2012 14:51:55 +0100 Subject: ARM: spear: merge Kconfig files As a preparation to merging the spear platforms into one directory, this merges the four Kconfig files into one. Signed-off-by: Arnd Bergmann Acked-by: Viresh Kumar --- arch/arm/mach-spear13xx/Kconfig | 20 ---------------- arch/arm/mach-spear3xx/Kconfig | 26 --------------------- arch/arm/mach-spear6xx/Kconfig | 10 -------- arch/arm/plat-spear/Kconfig | 51 +++++++++++++++++++++++++++++++++++++---- 4 files changed, 47 insertions(+), 60 deletions(-) delete mode 100644 arch/arm/mach-spear13xx/Kconfig delete mode 100644 arch/arm/mach-spear3xx/Kconfig delete mode 100644 arch/arm/mach-spear6xx/Kconfig (limited to 'arch/arm') diff --git a/arch/arm/mach-spear13xx/Kconfig b/arch/arm/mach-spear13xx/Kconfig deleted file mode 100644 index eaadc66..0000000 --- a/arch/arm/mach-spear13xx/Kconfig +++ /dev/null @@ -1,20 +0,0 @@ -# -# SPEAr13XX Machine configuration file -# - -if ARCH_SPEAR13XX - -menu "SPEAr13xx Implementations" -config MACH_SPEAR1310 - bool "SPEAr1310 Machine support with Device Tree" - select PINCTRL_SPEAR1310 - help - Supports ST SPEAr1310 machine configured via the device-tree - -config MACH_SPEAR1340 - bool "SPEAr1340 Machine support with Device Tree" - select PINCTRL_SPEAR1340 - help - Supports ST SPEAr1340 machine configured via the device-tree -endmenu -endif #ARCH_SPEAR13XX diff --git a/arch/arm/mach-spear3xx/Kconfig b/arch/arm/mach-spear3xx/Kconfig deleted file mode 100644 index 8bd3729..0000000 --- a/arch/arm/mach-spear3xx/Kconfig +++ /dev/null @@ -1,26 +0,0 @@ -# -# SPEAr3XX Machine configuration file -# - -if ARCH_SPEAR3XX - -menu "SPEAr3xx Implementations" -config MACH_SPEAR300 - bool "SPEAr300 Machine support with Device Tree" - select PINCTRL_SPEAR300 - help - Supports ST SPEAr300 machine configured via the device-tree - -config MACH_SPEAR310 - bool "SPEAr310 Machine support with Device Tree" - select PINCTRL_SPEAR310 - help - Supports ST SPEAr310 machine configured via the device-tree - -config MACH_SPEAR320 - bool "SPEAr320 Machine support with Device Tree" - select PINCTRL_SPEAR320 - help - Supports ST SPEAr320 machine configured via the device-tree -endmenu -endif #ARCH_SPEAR3XX diff --git a/arch/arm/mach-spear6xx/Kconfig b/arch/arm/mach-spear6xx/Kconfig deleted file mode 100644 index 339f397..0000000 --- a/arch/arm/mach-spear6xx/Kconfig +++ /dev/null @@ -1,10 +0,0 @@ -# -# SPEAr6XX Machine configuration file -# - -config MACH_SPEAR600 - def_bool y - depends on ARCH_SPEAR6XX - select USE_OF - help - Supports ST SPEAr600 boards configured via the device-tree diff --git a/arch/arm/plat-spear/Kconfig b/arch/arm/plat-spear/Kconfig index 739d016..e288df9 100644 --- a/arch/arm/plat-spear/Kconfig +++ b/arch/arm/plat-spear/Kconfig @@ -39,9 +39,52 @@ config ARCH_SPEAR6XX endchoice -# Adding SPEAr machine specific configuration files -source "arch/arm/mach-spear13xx/Kconfig" -source "arch/arm/mach-spear3xx/Kconfig" -source "arch/arm/mach-spear6xx/Kconfig" +if ARCH_SPEAR13XX + +menu "SPEAr13xx Implementations" +config MACH_SPEAR1310 + bool "SPEAr1310 Machine support with Device Tree" + select PINCTRL_SPEAR1310 + help + Supports ST SPEAr1310 machine configured via the device-tree + +config MACH_SPEAR1340 + bool "SPEAr1340 Machine support with Device Tree" + select PINCTRL_SPEAR1340 + help + Supports ST SPEAr1340 machine configured via the device-tree +endmenu +endif #ARCH_SPEAR13XX + +if ARCH_SPEAR3XX + +menu "SPEAr3xx Implementations" +config MACH_SPEAR300 + bool "SPEAr300 Machine support with Device Tree" + select PINCTRL_SPEAR300 + help + Supports ST SPEAr300 machine configured via the device-tree + +config MACH_SPEAR310 + bool "SPEAr310 Machine support with Device Tree" + select PINCTRL_SPEAR310 + help + Supports ST SPEAr310 machine configured via the device-tree + +config MACH_SPEAR320 + bool "SPEAr320 Machine support with Device Tree" + select PINCTRL_SPEAR320 + help + Supports ST SPEAr320 machine configured via the device-tree +endmenu + +endif + +config MACH_SPEAR600 + def_bool y + depends on ARCH_SPEAR6XX + select USE_OF + help + Supports ST SPEAr600 boards configured via the device-treesource "arch/arm/mach-spear6xx/Kconfig" endif -- cgit v1.1 From 0ec05c3e4ac6548fcab4b6a74254a22ef251e1fd Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Sun, 2 Dec 2012 15:01:11 +0100 Subject: ARM: spear: move spear.h and misc_regs.h into plat-spear The spear13xx version of spear.h is completely different from the newly combined spear3xx/spear6xx version, but we can never build ARMv5 and ARMv7 platforms together, so there is no harm in putting all the contents into a single file and adding appropriate ifdefs. Signed-off-by: Arnd Bergmann Acked-by: Viresh Kumar --- arch/arm/mach-spear13xx/include/mach/spear.h | 54 ------------- arch/arm/mach-spear3xx/include/mach/misc_regs.h | 22 ------ arch/arm/mach-spear3xx/include/mach/spear.h | 59 -------------- arch/arm/mach-spear6xx/include/mach/misc_regs.h | 22 ------ arch/arm/mach-spear6xx/include/mach/spear.h | 59 -------------- arch/arm/plat-spear/include/mach/misc_regs.h | 22 ++++++ arch/arm/plat-spear/include/mach/spear.h | 101 ++++++++++++++++++++++++ 7 files changed, 123 insertions(+), 216 deletions(-) delete mode 100644 arch/arm/mach-spear13xx/include/mach/spear.h delete mode 100644 arch/arm/mach-spear3xx/include/mach/misc_regs.h delete mode 100644 arch/arm/mach-spear3xx/include/mach/spear.h delete mode 100644 arch/arm/mach-spear6xx/include/mach/misc_regs.h delete mode 100644 arch/arm/mach-spear6xx/include/mach/spear.h create mode 100644 arch/arm/plat-spear/include/mach/misc_regs.h create mode 100644 arch/arm/plat-spear/include/mach/spear.h (limited to 'arch/arm') diff --git a/arch/arm/mach-spear13xx/include/mach/spear.h b/arch/arm/mach-spear13xx/include/mach/spear.h deleted file mode 100644 index 7cfa681..0000000 --- a/arch/arm/mach-spear13xx/include/mach/spear.h +++ /dev/null @@ -1,54 +0,0 @@ -/* - * arch/arm/mach-spear13xx/include/mach/spear.h - * - * spear13xx Machine family specific definition - * - * Copyright (C) 2012 ST Microelectronics - * Viresh Kumar - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#ifndef __MACH_SPEAR13XX_H -#define __MACH_SPEAR13XX_H - -#include - -#define PERIP_GRP2_BASE UL(0xB3000000) -#define VA_PERIP_GRP2_BASE IOMEM(0xFE000000) -#define MCIF_SDHCI_BASE UL(0xB3000000) -#define SYSRAM0_BASE UL(0xB3800000) -#define VA_SYSRAM0_BASE IOMEM(0xFE800000) -#define SYS_LOCATION (VA_SYSRAM0_BASE + 0x600) - -#define PERIP_GRP1_BASE UL(0xE0000000) -#define VA_PERIP_GRP1_BASE IOMEM(0xFD000000) -#define UART_BASE UL(0xE0000000) -#define VA_UART_BASE IOMEM(0xFD000000) -#define SSP_BASE UL(0xE0100000) -#define MISC_BASE UL(0xE0700000) -#define VA_MISC_BASE IOMEM(0xFD700000) - -#define A9SM_AND_MPMC_BASE UL(0xEC000000) -#define VA_A9SM_AND_MPMC_BASE IOMEM(0xFC000000) - -/* A9SM peripheral offsets */ -#define A9SM_PERIP_BASE UL(0xEC800000) -#define VA_A9SM_PERIP_BASE IOMEM(0xFC800000) -#define VA_SCU_BASE (VA_A9SM_PERIP_BASE + 0x00) - -#define L2CC_BASE UL(0xED000000) -#define VA_L2CC_BASE IOMEM(UL(0xFB000000)) - -/* others */ -#define DMAC0_BASE UL(0xEA800000) -#define DMAC1_BASE UL(0xEB000000) -#define MCIF_CF_BASE UL(0xB2800000) - -/* Debug uart for linux, will be used for debug and uncompress messages */ -#define SPEAR_DBG_UART_BASE UART_BASE -#define VA_SPEAR_DBG_UART_BASE VA_UART_BASE - -#endif /* __MACH_SPEAR13XX_H */ diff --git a/arch/arm/mach-spear3xx/include/mach/misc_regs.h b/arch/arm/mach-spear3xx/include/mach/misc_regs.h deleted file mode 100644 index 075812c..0000000 --- a/arch/arm/mach-spear3xx/include/mach/misc_regs.h +++ /dev/null @@ -1,22 +0,0 @@ -/* - * arch/arm/mach-spear3xx/include/mach/misc_regs.h - * - * Miscellaneous registers definitions for SPEAr3xx machine family - * - * Copyright (C) 2009 ST Microelectronics - * Viresh Kumar - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#ifndef __MACH_MISC_REGS_H -#define __MACH_MISC_REGS_H - -#include - -#define MISC_BASE IOMEM(VA_SPEAR_ICM3_MISC_REG_BASE) -#define DMA_CHN_CFG (MISC_BASE + 0x0A0) - -#endif /* __MACH_MISC_REGS_H */ diff --git a/arch/arm/mach-spear3xx/include/mach/spear.h b/arch/arm/mach-spear3xx/include/mach/spear.h deleted file mode 100644 index ee5a774..0000000 --- a/arch/arm/mach-spear3xx/include/mach/spear.h +++ /dev/null @@ -1,59 +0,0 @@ -/* - * SPEAr3xx/6xx Machine family specific definition - * - * Copyright (C) 2009,2012 ST Microelectronics - * Rajeev Kumar - * Viresh Kumar - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#ifndef __MACH_SPEAR_H -#define __MACH_SPEAR_H - -#include - -/* ICM1 - Low speed connection */ -#define SPEAR_ICM1_2_BASE UL(0xD0000000) -#define VA_SPEAR_ICM1_2_BASE UL(0xFD000000) -#define SPEAR_ICM1_UART_BASE UL(0xD0000000) -#define VA_SPEAR_ICM1_UART_BASE (VA_SPEAR_ICM1_2_BASE | SPEAR_ICM1_UART_BASE) -#define SPEAR3XX_ICM1_SSP_BASE UL(0xD0100000) - -/* ML-1, 2 - Multi Layer CPU Subsystem */ -#define SPEAR_ICM3_ML1_2_BASE UL(0xF0000000) -#define VA_SPEAR6XX_ML_CPU_BASE UL(0xF0000000) - -/* ICM3 - Basic Subsystem */ -#define SPEAR_ICM3_SMI_CTRL_BASE UL(0xFC000000) -#define VA_SPEAR_ICM3_SMI_CTRL_BASE UL(0xFC000000) -#define SPEAR_ICM3_DMA_BASE UL(0xFC400000) -#define SPEAR_ICM3_SYS_CTRL_BASE UL(0xFCA00000) -#define VA_SPEAR_ICM3_SYS_CTRL_BASE (VA_SPEAR_ICM3_SMI_CTRL_BASE | SPEAR_ICM3_SYS_CTRL_BASE) -#define SPEAR_ICM3_MISC_REG_BASE UL(0xFCA80000) -#define VA_SPEAR_ICM3_MISC_REG_BASE (VA_SPEAR_ICM3_SMI_CTRL_BASE | SPEAR_ICM3_MISC_REG_BASE) - -/* Debug uart for linux, will be used for debug and uncompress messages */ -#define SPEAR_DBG_UART_BASE SPEAR_ICM1_UART_BASE -#define VA_SPEAR_DBG_UART_BASE VA_SPEAR_ICM1_UART_BASE - -/* Sysctl base for spear platform */ -#define SPEAR_SYS_CTRL_BASE SPEAR_ICM3_SYS_CTRL_BASE -#define VA_SPEAR_SYS_CTRL_BASE VA_SPEAR_ICM3_SYS_CTRL_BASE - -/* SPEAr320 Macros */ -#define SPEAR320_SOC_CONFIG_BASE UL(0xB3000000) -#define VA_SPEAR320_SOC_CONFIG_BASE UL(0xFE000000) -#define SPEAR320_CONTROL_REG IOMEM(VA_SPEAR320_SOC_CONFIG_BASE) -#define SPEAR320_EXT_CTRL_REG IOMEM(VA_SPEAR320_SOC_CONFIG_BASE + 0x0018) - #define SPEAR320_UARTX_PCLK_MASK 0x1 - #define SPEAR320_UART2_PCLK_SHIFT 8 - #define SPEAR320_UART3_PCLK_SHIFT 9 - #define SPEAR320_UART4_PCLK_SHIFT 10 - #define SPEAR320_UART5_PCLK_SHIFT 11 - #define SPEAR320_UART6_PCLK_SHIFT 12 - #define SPEAR320_RS485_PCLK_SHIFT 13 - -#endif /* __MACH_SPEAR_H */ diff --git a/arch/arm/mach-spear6xx/include/mach/misc_regs.h b/arch/arm/mach-spear6xx/include/mach/misc_regs.h deleted file mode 100644 index 28aa508..0000000 --- a/arch/arm/mach-spear6xx/include/mach/misc_regs.h +++ /dev/null @@ -1,22 +0,0 @@ -/* - * arch/arm/mach-spear6xx/include/mach/misc_regs.h - * - * Miscellaneous registers definitions for SPEAr6xx machine family - * - * Copyright (C) 2009 ST Microelectronics - * Viresh Kumar - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#ifndef __MACH_MISC_REGS_H -#define __MACH_MISC_REGS_H - -#include - -#define MISC_BASE IOMEM(VA_SPEAR_ICM3_MISC_REG_BASE) -#define DMA_CHN_CFG (MISC_BASE + 0x0A0) - -#endif /* __MACH_MISC_REGS_H */ diff --git a/arch/arm/mach-spear6xx/include/mach/spear.h b/arch/arm/mach-spear6xx/include/mach/spear.h deleted file mode 100644 index ee5a774..0000000 --- a/arch/arm/mach-spear6xx/include/mach/spear.h +++ /dev/null @@ -1,59 +0,0 @@ -/* - * SPEAr3xx/6xx Machine family specific definition - * - * Copyright (C) 2009,2012 ST Microelectronics - * Rajeev Kumar - * Viresh Kumar - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#ifndef __MACH_SPEAR_H -#define __MACH_SPEAR_H - -#include - -/* ICM1 - Low speed connection */ -#define SPEAR_ICM1_2_BASE UL(0xD0000000) -#define VA_SPEAR_ICM1_2_BASE UL(0xFD000000) -#define SPEAR_ICM1_UART_BASE UL(0xD0000000) -#define VA_SPEAR_ICM1_UART_BASE (VA_SPEAR_ICM1_2_BASE | SPEAR_ICM1_UART_BASE) -#define SPEAR3XX_ICM1_SSP_BASE UL(0xD0100000) - -/* ML-1, 2 - Multi Layer CPU Subsystem */ -#define SPEAR_ICM3_ML1_2_BASE UL(0xF0000000) -#define VA_SPEAR6XX_ML_CPU_BASE UL(0xF0000000) - -/* ICM3 - Basic Subsystem */ -#define SPEAR_ICM3_SMI_CTRL_BASE UL(0xFC000000) -#define VA_SPEAR_ICM3_SMI_CTRL_BASE UL(0xFC000000) -#define SPEAR_ICM3_DMA_BASE UL(0xFC400000) -#define SPEAR_ICM3_SYS_CTRL_BASE UL(0xFCA00000) -#define VA_SPEAR_ICM3_SYS_CTRL_BASE (VA_SPEAR_ICM3_SMI_CTRL_BASE | SPEAR_ICM3_SYS_CTRL_BASE) -#define SPEAR_ICM3_MISC_REG_BASE UL(0xFCA80000) -#define VA_SPEAR_ICM3_MISC_REG_BASE (VA_SPEAR_ICM3_SMI_CTRL_BASE | SPEAR_ICM3_MISC_REG_BASE) - -/* Debug uart for linux, will be used for debug and uncompress messages */ -#define SPEAR_DBG_UART_BASE SPEAR_ICM1_UART_BASE -#define VA_SPEAR_DBG_UART_BASE VA_SPEAR_ICM1_UART_BASE - -/* Sysctl base for spear platform */ -#define SPEAR_SYS_CTRL_BASE SPEAR_ICM3_SYS_CTRL_BASE -#define VA_SPEAR_SYS_CTRL_BASE VA_SPEAR_ICM3_SYS_CTRL_BASE - -/* SPEAr320 Macros */ -#define SPEAR320_SOC_CONFIG_BASE UL(0xB3000000) -#define VA_SPEAR320_SOC_CONFIG_BASE UL(0xFE000000) -#define SPEAR320_CONTROL_REG IOMEM(VA_SPEAR320_SOC_CONFIG_BASE) -#define SPEAR320_EXT_CTRL_REG IOMEM(VA_SPEAR320_SOC_CONFIG_BASE + 0x0018) - #define SPEAR320_UARTX_PCLK_MASK 0x1 - #define SPEAR320_UART2_PCLK_SHIFT 8 - #define SPEAR320_UART3_PCLK_SHIFT 9 - #define SPEAR320_UART4_PCLK_SHIFT 10 - #define SPEAR320_UART5_PCLK_SHIFT 11 - #define SPEAR320_UART6_PCLK_SHIFT 12 - #define SPEAR320_RS485_PCLK_SHIFT 13 - -#endif /* __MACH_SPEAR_H */ diff --git a/arch/arm/plat-spear/include/mach/misc_regs.h b/arch/arm/plat-spear/include/mach/misc_regs.h new file mode 100644 index 0000000..075812c --- /dev/null +++ b/arch/arm/plat-spear/include/mach/misc_regs.h @@ -0,0 +1,22 @@ +/* + * arch/arm/mach-spear3xx/include/mach/misc_regs.h + * + * Miscellaneous registers definitions for SPEAr3xx machine family + * + * Copyright (C) 2009 ST Microelectronics + * Viresh Kumar + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __MACH_MISC_REGS_H +#define __MACH_MISC_REGS_H + +#include + +#define MISC_BASE IOMEM(VA_SPEAR_ICM3_MISC_REG_BASE) +#define DMA_CHN_CFG (MISC_BASE + 0x0A0) + +#endif /* __MACH_MISC_REGS_H */ diff --git a/arch/arm/plat-spear/include/mach/spear.h b/arch/arm/plat-spear/include/mach/spear.h new file mode 100644 index 0000000..2198ab9 --- /dev/null +++ b/arch/arm/plat-spear/include/mach/spear.h @@ -0,0 +1,101 @@ +/* + * SPEAr3xx/6xx Machine family specific definition + * + * Copyright (C) 2009,2012 ST Microelectronics + * Rajeev Kumar + * Viresh Kumar + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __MACH_SPEAR_H +#define __MACH_SPEAR_H + +#include + +#if defined(CONFIG_ARCH_SPEAR3XX) || defined (CONFIG_ARCH_SPEAR6XX) + +/* ICM1 - Low speed connection */ +#define SPEAR_ICM1_2_BASE UL(0xD0000000) +#define VA_SPEAR_ICM1_2_BASE UL(0xFD000000) +#define SPEAR_ICM1_UART_BASE UL(0xD0000000) +#define VA_SPEAR_ICM1_UART_BASE (VA_SPEAR_ICM1_2_BASE | SPEAR_ICM1_UART_BASE) +#define SPEAR3XX_ICM1_SSP_BASE UL(0xD0100000) + +/* ML-1, 2 - Multi Layer CPU Subsystem */ +#define SPEAR_ICM3_ML1_2_BASE UL(0xF0000000) +#define VA_SPEAR6XX_ML_CPU_BASE UL(0xF0000000) + +/* ICM3 - Basic Subsystem */ +#define SPEAR_ICM3_SMI_CTRL_BASE UL(0xFC000000) +#define VA_SPEAR_ICM3_SMI_CTRL_BASE UL(0xFC000000) +#define SPEAR_ICM3_DMA_BASE UL(0xFC400000) +#define SPEAR_ICM3_SYS_CTRL_BASE UL(0xFCA00000) +#define VA_SPEAR_ICM3_SYS_CTRL_BASE (VA_SPEAR_ICM3_SMI_CTRL_BASE | SPEAR_ICM3_SYS_CTRL_BASE) +#define SPEAR_ICM3_MISC_REG_BASE UL(0xFCA80000) +#define VA_SPEAR_ICM3_MISC_REG_BASE (VA_SPEAR_ICM3_SMI_CTRL_BASE | SPEAR_ICM3_MISC_REG_BASE) + +/* Debug uart for linux, will be used for debug and uncompress messages */ +#define SPEAR_DBG_UART_BASE SPEAR_ICM1_UART_BASE +#define VA_SPEAR_DBG_UART_BASE VA_SPEAR_ICM1_UART_BASE + +/* Sysctl base for spear platform */ +#define SPEAR_SYS_CTRL_BASE SPEAR_ICM3_SYS_CTRL_BASE +#define VA_SPEAR_SYS_CTRL_BASE VA_SPEAR_ICM3_SYS_CTRL_BASE + +/* SPEAr320 Macros */ +#define SPEAR320_SOC_CONFIG_BASE UL(0xB3000000) +#define VA_SPEAR320_SOC_CONFIG_BASE UL(0xFE000000) +#define SPEAR320_CONTROL_REG IOMEM(VA_SPEAR320_SOC_CONFIG_BASE) +#define SPEAR320_EXT_CTRL_REG IOMEM(VA_SPEAR320_SOC_CONFIG_BASE + 0x0018) + #define SPEAR320_UARTX_PCLK_MASK 0x1 + #define SPEAR320_UART2_PCLK_SHIFT 8 + #define SPEAR320_UART3_PCLK_SHIFT 9 + #define SPEAR320_UART4_PCLK_SHIFT 10 + #define SPEAR320_UART5_PCLK_SHIFT 11 + #define SPEAR320_UART6_PCLK_SHIFT 12 + #define SPEAR320_RS485_PCLK_SHIFT 13 +#endif /* SPEAR3xx || SPEAR6XX */ + +#ifdef CONFIG_ARCH_SPEAR13XX + +#define PERIP_GRP2_BASE UL(0xB3000000) +#define VA_PERIP_GRP2_BASE IOMEM(0xFE000000) +#define MCIF_SDHCI_BASE UL(0xB3000000) +#define SYSRAM0_BASE UL(0xB3800000) +#define VA_SYSRAM0_BASE IOMEM(0xFE800000) +#define SYS_LOCATION (VA_SYSRAM0_BASE + 0x600) + +#define PERIP_GRP1_BASE UL(0xE0000000) +#define VA_PERIP_GRP1_BASE IOMEM(0xFD000000) +#define UART_BASE UL(0xE0000000) +#define VA_UART_BASE IOMEM(0xFD000000) +#define SSP_BASE UL(0xE0100000) +#define MISC_BASE UL(0xE0700000) +#define VA_MISC_BASE IOMEM(0xFD700000) + +#define A9SM_AND_MPMC_BASE UL(0xEC000000) +#define VA_A9SM_AND_MPMC_BASE IOMEM(0xFC000000) + +/* A9SM peripheral offsets */ +#define A9SM_PERIP_BASE UL(0xEC800000) +#define VA_A9SM_PERIP_BASE IOMEM(0xFC800000) +#define VA_SCU_BASE (VA_A9SM_PERIP_BASE + 0x00) + +#define L2CC_BASE UL(0xED000000) +#define VA_L2CC_BASE IOMEM(UL(0xFB000000)) + +/* others */ +#define DMAC0_BASE UL(0xEA800000) +#define DMAC1_BASE UL(0xEB000000) +#define MCIF_CF_BASE UL(0xB2800000) + +/* Debug uart for linux, will be used for debug and uncompress messages */ +#define SPEAR_DBG_UART_BASE UART_BASE +#define VA_SPEAR_DBG_UART_BASE VA_UART_BASE + +#endif /* SPEAR13XX */ + +#endif /* __MACH_SPEAR_H */ -- cgit v1.1 From a7ed099ffc8edf2a6dccd8a22469347f5cdcfa57 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Sun, 2 Dec 2012 15:12:47 +0100 Subject: ARM: spear: move all files to mach-spear There are no conflicting files between the three mach-spear* directories and plat-spear any more, so we can now move all file to a common mach-spear directory. Signed-off-by: Arnd Bergmann Acked-by: Viresh Kumar --- arch/arm/Kconfig | 2 +- arch/arm/Makefile | 5 +- arch/arm/mach-spear/Kconfig | 90 ++++++ arch/arm/mach-spear/Makefile | 22 ++ arch/arm/mach-spear/Makefile.boot | 3 + arch/arm/mach-spear/headsmp.S | 47 +++ arch/arm/mach-spear/hotplug.c | 103 ++++++ arch/arm/mach-spear/include/mach/debug-macro.S | 36 +++ arch/arm/mach-spear/include/mach/generic.h | 58 ++++ arch/arm/mach-spear/include/mach/hardware.h | 1 + arch/arm/mach-spear/include/mach/irqs.h | 35 ++ arch/arm/mach-spear/include/mach/misc_regs.h | 22 ++ arch/arm/mach-spear/include/mach/spear.h | 101 ++++++ arch/arm/mach-spear/include/mach/timex.h | 19 ++ arch/arm/mach-spear/include/mach/uncompress.h | 42 +++ arch/arm/mach-spear/include/plat/pl080.h | 21 ++ arch/arm/mach-spear/pl080.c | 78 +++++ arch/arm/mach-spear/platsmp.c | 130 ++++++++ arch/arm/mach-spear/restart.c | 33 ++ arch/arm/mach-spear/spear1310.c | 98 ++++++ arch/arm/mach-spear/spear1340.c | 193 +++++++++++ arch/arm/mach-spear/spear13xx-dma.h | 128 ++++++++ arch/arm/mach-spear/spear13xx.c | 184 +++++++++++ arch/arm/mach-spear/spear300.c | 220 +++++++++++++ arch/arm/mach-spear/spear310.c | 262 +++++++++++++++ arch/arm/mach-spear/spear320.c | 277 ++++++++++++++++ arch/arm/mach-spear/spear3xx.c | 115 +++++++ arch/arm/mach-spear/spear6xx.c | 430 +++++++++++++++++++++++++ arch/arm/mach-spear/time.c | 245 ++++++++++++++ arch/arm/mach-spear13xx/Makefile | 10 - arch/arm/mach-spear13xx/Makefile.boot | 3 - arch/arm/mach-spear13xx/headsmp.S | 47 --- arch/arm/mach-spear13xx/hotplug.c | 103 ------ arch/arm/mach-spear13xx/platsmp.c | 130 -------- arch/arm/mach-spear13xx/spear1310.c | 98 ------ arch/arm/mach-spear13xx/spear1340.c | 193 ----------- arch/arm/mach-spear13xx/spear13xx-dma.h | 128 -------- arch/arm/mach-spear13xx/spear13xx.c | 184 ----------- arch/arm/mach-spear3xx/Makefile | 15 - arch/arm/mach-spear3xx/Makefile.boot | 3 - arch/arm/mach-spear3xx/spear300.c | 220 ------------- arch/arm/mach-spear3xx/spear310.c | 262 --------------- arch/arm/mach-spear3xx/spear320.c | 277 ---------------- arch/arm/mach-spear3xx/spear3xx.c | 115 ------- arch/arm/mach-spear6xx/Makefile | 6 - arch/arm/mach-spear6xx/Makefile.boot | 3 - arch/arm/mach-spear6xx/spear6xx.c | 430 ------------------------- arch/arm/plat-spear/Kconfig | 90 ------ arch/arm/plat-spear/Makefile | 9 - arch/arm/plat-spear/include/mach/debug-macro.S | 36 --- arch/arm/plat-spear/include/mach/generic.h | 58 ---- arch/arm/plat-spear/include/mach/hardware.h | 1 - arch/arm/plat-spear/include/mach/irqs.h | 35 -- arch/arm/plat-spear/include/mach/misc_regs.h | 22 -- arch/arm/plat-spear/include/mach/spear.h | 101 ------ arch/arm/plat-spear/include/mach/timex.h | 19 -- arch/arm/plat-spear/include/mach/uncompress.h | 42 --- arch/arm/plat-spear/include/plat/pl080.h | 21 -- arch/arm/plat-spear/pl080.c | 78 ----- arch/arm/plat-spear/restart.c | 33 -- arch/arm/plat-spear/time.c | 245 -------------- 61 files changed, 2995 insertions(+), 3022 deletions(-) create mode 100644 arch/arm/mach-spear/Kconfig create mode 100644 arch/arm/mach-spear/Makefile create mode 100644 arch/arm/mach-spear/Makefile.boot create mode 100644 arch/arm/mach-spear/headsmp.S create mode 100644 arch/arm/mach-spear/hotplug.c create mode 100644 arch/arm/mach-spear/include/mach/debug-macro.S create mode 100644 arch/arm/mach-spear/include/mach/generic.h create mode 100644 arch/arm/mach-spear/include/mach/hardware.h create mode 100644 arch/arm/mach-spear/include/mach/irqs.h create mode 100644 arch/arm/mach-spear/include/mach/misc_regs.h create mode 100644 arch/arm/mach-spear/include/mach/spear.h create mode 100644 arch/arm/mach-spear/include/mach/timex.h create mode 100644 arch/arm/mach-spear/include/mach/uncompress.h create mode 100644 arch/arm/mach-spear/include/plat/pl080.h create mode 100644 arch/arm/mach-spear/pl080.c create mode 100644 arch/arm/mach-spear/platsmp.c create mode 100644 arch/arm/mach-spear/restart.c create mode 100644 arch/arm/mach-spear/spear1310.c create mode 100644 arch/arm/mach-spear/spear1340.c create mode 100644 arch/arm/mach-spear/spear13xx-dma.h create mode 100644 arch/arm/mach-spear/spear13xx.c create mode 100644 arch/arm/mach-spear/spear300.c create mode 100644 arch/arm/mach-spear/spear310.c create mode 100644 arch/arm/mach-spear/spear320.c create mode 100644 arch/arm/mach-spear/spear3xx.c create mode 100644 arch/arm/mach-spear/spear6xx.c create mode 100644 arch/arm/mach-spear/time.c delete mode 100644 arch/arm/mach-spear13xx/Makefile delete mode 100644 arch/arm/mach-spear13xx/Makefile.boot delete mode 100644 arch/arm/mach-spear13xx/headsmp.S delete mode 100644 arch/arm/mach-spear13xx/hotplug.c delete mode 100644 arch/arm/mach-spear13xx/platsmp.c delete mode 100644 arch/arm/mach-spear13xx/spear1310.c delete mode 100644 arch/arm/mach-spear13xx/spear1340.c delete mode 100644 arch/arm/mach-spear13xx/spear13xx-dma.h delete mode 100644 arch/arm/mach-spear13xx/spear13xx.c delete mode 100644 arch/arm/mach-spear3xx/Makefile delete mode 100644 arch/arm/mach-spear3xx/Makefile.boot delete mode 100644 arch/arm/mach-spear3xx/spear300.c delete mode 100644 arch/arm/mach-spear3xx/spear310.c delete mode 100644 arch/arm/mach-spear3xx/spear320.c delete mode 100644 arch/arm/mach-spear3xx/spear3xx.c delete mode 100644 arch/arm/mach-spear6xx/Makefile delete mode 100644 arch/arm/mach-spear6xx/Makefile.boot delete mode 100644 arch/arm/mach-spear6xx/spear6xx.c delete mode 100644 arch/arm/plat-spear/Kconfig delete mode 100644 arch/arm/plat-spear/Makefile delete mode 100644 arch/arm/plat-spear/include/mach/debug-macro.S delete mode 100644 arch/arm/plat-spear/include/mach/generic.h delete mode 100644 arch/arm/plat-spear/include/mach/hardware.h delete mode 100644 arch/arm/plat-spear/include/mach/irqs.h delete mode 100644 arch/arm/plat-spear/include/mach/misc_regs.h delete mode 100644 arch/arm/plat-spear/include/mach/spear.h delete mode 100644 arch/arm/plat-spear/include/mach/timex.h delete mode 100644 arch/arm/plat-spear/include/mach/uncompress.h delete mode 100644 arch/arm/plat-spear/include/plat/pl080.h delete mode 100644 arch/arm/plat-spear/pl080.c delete mode 100644 arch/arm/plat-spear/restart.c delete mode 100644 arch/arm/plat-spear/time.c (limited to 'arch/arm') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 5b71469..4d2b1cf 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1104,7 +1104,7 @@ source "arch/arm/plat-samsung/Kconfig" source "arch/arm/mach-socfpga/Kconfig" -source "arch/arm/plat-spear/Kconfig" +source "arch/arm/mach-spear/Kconfig" source "arch/arm/mach-s3c24xx/Kconfig" diff --git a/arch/arm/Makefile b/arch/arm/Makefile index ee4605f..82765368 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -191,9 +191,7 @@ machine-$(CONFIG_ARCH_VT8500) += vt8500 machine-$(CONFIG_ARCH_W90X900) += w90x900 machine-$(CONFIG_FOOTBRIDGE) += footbridge machine-$(CONFIG_ARCH_SOCFPGA) += socfpga -machine-$(CONFIG_ARCH_SPEAR13XX) += spear13xx -machine-$(CONFIG_ARCH_SPEAR3XX) += spear3xx -machine-$(CONFIG_MACH_SPEAR600) += spear6xx +machine-$(CONFIG_PLAT_SPEAR) += spear machine-$(CONFIG_ARCH_VIRT) += virt machine-$(CONFIG_ARCH_ZYNQ) += zynq machine-$(CONFIG_ARCH_SUNXI) += sunxi @@ -207,7 +205,6 @@ plat-$(CONFIG_PLAT_ORION) += orion plat-$(CONFIG_PLAT_PXA) += pxa plat-$(CONFIG_PLAT_S3C24XX) += samsung plat-$(CONFIG_PLAT_S5P) += samsung -plat-$(CONFIG_PLAT_SPEAR) += spear plat-$(CONFIG_PLAT_VERSATILE) += versatile ifeq ($(CONFIG_ARCH_EBSA110),y) diff --git a/arch/arm/mach-spear/Kconfig b/arch/arm/mach-spear/Kconfig new file mode 100644 index 0000000..e288df9 --- /dev/null +++ b/arch/arm/mach-spear/Kconfig @@ -0,0 +1,90 @@ +# +# SPEAr Platform configuration file +# + +if PLAT_SPEAR + +choice + prompt "ST SPEAr Family" + default ARCH_SPEAR3XX + +config ARCH_SPEAR13XX + bool "ST SPEAr13xx with Device Tree" + select ARCH_HAVE_CPUFREQ + select ARM_GIC + select CPU_V7 + select GPIO_SPEAR_SPICS + select HAVE_SMP + select MIGHT_HAVE_CACHE_L2X0 + select PINCTRL + select USE_OF + help + Supports for ARM's SPEAR13XX family + +config ARCH_SPEAR3XX + bool "ST SPEAr3xx with Device Tree" + select ARM_VIC + select CPU_ARM926T + select PINCTRL + select USE_OF + help + Supports for ARM's SPEAR3XX family + +config ARCH_SPEAR6XX + bool "SPEAr6XX" + select ARM_VIC + select CPU_ARM926T + help + Supports for ARM's SPEAR6XX family + +endchoice + +if ARCH_SPEAR13XX + +menu "SPEAr13xx Implementations" +config MACH_SPEAR1310 + bool "SPEAr1310 Machine support with Device Tree" + select PINCTRL_SPEAR1310 + help + Supports ST SPEAr1310 machine configured via the device-tree + +config MACH_SPEAR1340 + bool "SPEAr1340 Machine support with Device Tree" + select PINCTRL_SPEAR1340 + help + Supports ST SPEAr1340 machine configured via the device-tree +endmenu +endif #ARCH_SPEAR13XX + +if ARCH_SPEAR3XX + +menu "SPEAr3xx Implementations" +config MACH_SPEAR300 + bool "SPEAr300 Machine support with Device Tree" + select PINCTRL_SPEAR300 + help + Supports ST SPEAr300 machine configured via the device-tree + +config MACH_SPEAR310 + bool "SPEAr310 Machine support with Device Tree" + select PINCTRL_SPEAR310 + help + Supports ST SPEAr310 machine configured via the device-tree + +config MACH_SPEAR320 + bool "SPEAr320 Machine support with Device Tree" + select PINCTRL_SPEAR320 + help + Supports ST SPEAr320 machine configured via the device-tree +endmenu + +endif + +config MACH_SPEAR600 + def_bool y + depends on ARCH_SPEAR6XX + select USE_OF + help + Supports ST SPEAr600 boards configured via the device-treesource "arch/arm/mach-spear6xx/Kconfig" + +endif diff --git a/arch/arm/mach-spear/Makefile b/arch/arm/mach-spear/Makefile new file mode 100644 index 0000000..8a937bf --- /dev/null +++ b/arch/arm/mach-spear/Makefile @@ -0,0 +1,22 @@ +# +# SPEAr Platform specific Makefile +# + +# Common support +obj-y := restart.o time.o + +obj-$(CONFIG_SMP) += headsmp.o platsmp.o +obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o + +obj-$(CONFIG_ARCH_SPEAR13XX) += spear13xx.o +obj-$(CONFIG_MACH_SPEAR1310) += spear1310.o +obj-$(CONFIG_MACH_SPEAR1340) += spear1340.o + +obj-$(CONFIG_ARCH_SPEAR3XX) += spear3xx.o +obj-$(CONFIG_ARCH_SPEAR3XX) += pl080.o +obj-$(CONFIG_MACH_SPEAR300) += spear300.o +obj-$(CONFIG_MACH_SPEAR310) += spear310.o +obj-$(CONFIG_MACH_SPEAR320) += spear320.o + +obj-$(CONFIG_ARCH_SPEAR6XX) += spear6xx.o +obj-$(CONFIG_ARCH_SPEAR6XX) += pl080.o diff --git a/arch/arm/mach-spear/Makefile.boot b/arch/arm/mach-spear/Makefile.boot new file mode 100644 index 0000000..4674a4c --- /dev/null +++ b/arch/arm/mach-spear/Makefile.boot @@ -0,0 +1,3 @@ +zreladdr-y += 0x00008000 +params_phys-y := 0x00000100 +initrd_phys-y := 0x00800000 diff --git a/arch/arm/mach-spear/headsmp.S b/arch/arm/mach-spear/headsmp.S new file mode 100644 index 0000000..ed85473 --- /dev/null +++ b/arch/arm/mach-spear/headsmp.S @@ -0,0 +1,47 @@ +/* + * arch/arm/mach-spear13XX/headsmp.S + * + * Picked from realview + * Copyright (c) 2012 ST Microelectronics Limited + * Shiraz Hashim + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include + + __INIT + +/* + * spear13xx specific entry point for secondary CPUs. This provides + * a "holding pen" into which all secondary cores are held until we're + * ready for them to initialise. + */ +ENTRY(spear13xx_secondary_startup) + mrc p15, 0, r0, c0, c0, 5 + and r0, r0, #15 + adr r4, 1f + ldmia r4, {r5, r6} + sub r4, r4, r5 + add r6, r6, r4 +pen: ldr r7, [r6] + cmp r7, r0 + bne pen + + /* re-enable coherency */ + mrc p15, 0, r0, c1, c0, 1 + orr r0, r0, #(1 << 6) | (1 << 0) + mcr p15, 0, r0, c1, c0, 1 + /* + * we've been released from the holding pen: secondary_stack + * should now contain the SVC stack for this core + */ + b secondary_startup + + .align +1: .long . + .long pen_release +ENDPROC(spear13xx_secondary_startup) diff --git a/arch/arm/mach-spear/hotplug.c b/arch/arm/mach-spear/hotplug.c new file mode 100644 index 0000000..a7d2dd1 --- /dev/null +++ b/arch/arm/mach-spear/hotplug.c @@ -0,0 +1,103 @@ +/* + * linux/arch/arm/mach-spear13xx/hotplug.c + * + * Copyright (C) 2012 ST Microelectronics Ltd. + * Deepak Sikri + * + * based upon linux/arch/arm/mach-realview/hotplug.c + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#include +#include +#include +#include +#include +#include + +static inline void cpu_enter_lowpower(void) +{ + unsigned int v; + + flush_cache_all(); + asm volatile( + " mcr p15, 0, %1, c7, c5, 0\n" + " dsb\n" + /* + * Turn off coherency + */ + " mrc p15, 0, %0, c1, c0, 1\n" + " bic %0, %0, #0x20\n" + " mcr p15, 0, %0, c1, c0, 1\n" + " mrc p15, 0, %0, c1, c0, 0\n" + " bic %0, %0, %2\n" + " mcr p15, 0, %0, c1, c0, 0\n" + : "=&r" (v) + : "r" (0), "Ir" (CR_C) + : "cc", "memory"); +} + +static inline void cpu_leave_lowpower(void) +{ + unsigned int v; + + asm volatile("mrc p15, 0, %0, c1, c0, 0\n" + " orr %0, %0, %1\n" + " mcr p15, 0, %0, c1, c0, 0\n" + " mrc p15, 0, %0, c1, c0, 1\n" + " orr %0, %0, #0x20\n" + " mcr p15, 0, %0, c1, c0, 1\n" + : "=&r" (v) + : "Ir" (CR_C) + : "cc"); +} + +static inline void spear13xx_do_lowpower(unsigned int cpu, int *spurious) +{ + for (;;) { + wfi(); + + if (pen_release == cpu) { + /* + * OK, proper wakeup, we're done + */ + break; + } + + /* + * Getting here, means that we have come out of WFI without + * having been woken up - this shouldn't happen + * + * Just note it happening - when we're woken, we can report + * its occurrence. + */ + (*spurious)++; + } +} + +/* + * platform-specific code to shutdown a CPU + * + * Called with IRQs disabled + */ +void __ref spear13xx_cpu_die(unsigned int cpu) +{ + int spurious = 0; + + /* + * we're ready for shutdown now, so do it + */ + cpu_enter_lowpower(); + spear13xx_do_lowpower(cpu, &spurious); + + /* + * bring this CPU back into the world of cache + * coherency, and then restore interrupts + */ + cpu_leave_lowpower(); + + if (spurious) + pr_warn("CPU%u: %u spurious wakeup calls\n", cpu, spurious); +} diff --git a/arch/arm/mach-spear/include/mach/debug-macro.S b/arch/arm/mach-spear/include/mach/debug-macro.S new file mode 100644 index 0000000..75b05ad --- /dev/null +++ b/arch/arm/mach-spear/include/mach/debug-macro.S @@ -0,0 +1,36 @@ +/* + * arch/arm/plat-spear/include/plat/debug-macro.S + * + * Debugging macro include header for spear platform + * + * Copyright (C) 2009 ST Microelectronics + * Viresh Kumar + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include +#include + + .macro addruart, rp, rv, tmp + mov \rp, #SPEAR_DBG_UART_BASE @ Physical base + mov \rv, #VA_SPEAR_DBG_UART_BASE @ Virtual base + .endm + + .macro senduart, rd, rx + strb \rd, [\rx, #UART01x_DR] @ ASC_TX_BUFFER + .endm + + .macro waituart, rd, rx +1001: ldr \rd, [\rx, #UART01x_FR] @ FLAG REGISTER + tst \rd, #UART01x_FR_TXFF @ TX_FULL + bne 1001b + .endm + + .macro busyuart, rd, rx +1002: ldr \rd, [\rx, #UART01x_FR] @ FLAG REGISTER + tst \rd, #UART011_FR_TXFE @ TX_EMPTY + beq 1002b + .endm diff --git a/arch/arm/mach-spear/include/mach/generic.h b/arch/arm/mach-spear/include/mach/generic.h new file mode 100644 index 0000000..af47d9b --- /dev/null +++ b/arch/arm/mach-spear/include/mach/generic.h @@ -0,0 +1,58 @@ +/* + * spear machine family generic header file + * + * Copyright (C) 2009-2012 ST Microelectronics + * Rajeev Kumar + * Viresh Kumar + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __MACH_GENERIC_H +#define __MACH_GENERIC_H + +#include +#include +#include +#include + +extern void spear13xx_timer_init(void); +extern void spear3xx_timer_init(void); +extern struct pl022_ssp_controller pl022_plat_data; +extern struct pl08x_platform_data pl080_plat_data; +extern struct dw_dma_platform_data dmac_plat_data; +extern struct dw_dma_slave cf_dma_priv; +extern struct dw_dma_slave nand_read_dma_priv; +extern struct dw_dma_slave nand_write_dma_priv; +bool dw_dma_filter(struct dma_chan *chan, void *slave); + +void __init spear_setup_of_timer(void); +void __init spear3xx_clk_init(void); +void __init spear3xx_map_io(void); +void __init spear3xx_dt_init_irq(void); +void __init spear6xx_clk_init(void); +void __init spear13xx_map_io(void); +void __init spear13xx_l2x0_init(void); + +void spear_restart(char, const char *); + +void spear13xx_secondary_startup(void); +void __cpuinit spear13xx_cpu_die(unsigned int cpu); + +extern struct smp_operations spear13xx_smp_ops; + +#ifdef CONFIG_MACH_SPEAR1310 +void __init spear1310_clk_init(void); +#else +static inline void spear1310_clk_init(void) {} +#endif + +#ifdef CONFIG_MACH_SPEAR1340 +void __init spear1340_clk_init(void); +#else +static inline void spear1340_clk_init(void) {} +#endif + +#endif /* __MACH_GENERIC_H */ diff --git a/arch/arm/mach-spear/include/mach/hardware.h b/arch/arm/mach-spear/include/mach/hardware.h new file mode 100644 index 0000000..40a8c17 --- /dev/null +++ b/arch/arm/mach-spear/include/mach/hardware.h @@ -0,0 +1 @@ +/* empty */ diff --git a/arch/arm/mach-spear/include/mach/irqs.h b/arch/arm/mach-spear/include/mach/irqs.h new file mode 100644 index 0000000..92da0a8 --- /dev/null +++ b/arch/arm/mach-spear/include/mach/irqs.h @@ -0,0 +1,35 @@ +/* + * IRQ helper macros for spear machine family + * + * Copyright (C) 2009-2012 ST Microelectronics + * Rajeev Kumar + * Viresh Kumar + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __MACH_IRQS_H +#define __MACH_IRQS_H + +#ifdef CONFIG_ARCH_SPEAR3XX +#define NR_IRQS 256 +#endif + +#ifdef CONFIG_ARCH_SPEAR6XX +/* IRQ definitions */ +/* VIC 1 */ +#define IRQ_VIC_END 64 + +/* GPIO pins virtual irqs */ +#define VIRTUAL_IRQS 24 +#define NR_IRQS (IRQ_VIC_END + VIRTUAL_IRQS) +#endif + +#ifdef CONFIG_ARCH_SPEAR13XX +#define IRQ_GIC_END 160 +#define NR_IRQS IRQ_GIC_END +#endif + +#endif /* __MACH_IRQS_H */ diff --git a/arch/arm/mach-spear/include/mach/misc_regs.h b/arch/arm/mach-spear/include/mach/misc_regs.h new file mode 100644 index 0000000..075812c --- /dev/null +++ b/arch/arm/mach-spear/include/mach/misc_regs.h @@ -0,0 +1,22 @@ +/* + * arch/arm/mach-spear3xx/include/mach/misc_regs.h + * + * Miscellaneous registers definitions for SPEAr3xx machine family + * + * Copyright (C) 2009 ST Microelectronics + * Viresh Kumar + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __MACH_MISC_REGS_H +#define __MACH_MISC_REGS_H + +#include + +#define MISC_BASE IOMEM(VA_SPEAR_ICM3_MISC_REG_BASE) +#define DMA_CHN_CFG (MISC_BASE + 0x0A0) + +#endif /* __MACH_MISC_REGS_H */ diff --git a/arch/arm/mach-spear/include/mach/spear.h b/arch/arm/mach-spear/include/mach/spear.h new file mode 100644 index 0000000..2198ab9 --- /dev/null +++ b/arch/arm/mach-spear/include/mach/spear.h @@ -0,0 +1,101 @@ +/* + * SPEAr3xx/6xx Machine family specific definition + * + * Copyright (C) 2009,2012 ST Microelectronics + * Rajeev Kumar + * Viresh Kumar + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __MACH_SPEAR_H +#define __MACH_SPEAR_H + +#include + +#if defined(CONFIG_ARCH_SPEAR3XX) || defined (CONFIG_ARCH_SPEAR6XX) + +/* ICM1 - Low speed connection */ +#define SPEAR_ICM1_2_BASE UL(0xD0000000) +#define VA_SPEAR_ICM1_2_BASE UL(0xFD000000) +#define SPEAR_ICM1_UART_BASE UL(0xD0000000) +#define VA_SPEAR_ICM1_UART_BASE (VA_SPEAR_ICM1_2_BASE | SPEAR_ICM1_UART_BASE) +#define SPEAR3XX_ICM1_SSP_BASE UL(0xD0100000) + +/* ML-1, 2 - Multi Layer CPU Subsystem */ +#define SPEAR_ICM3_ML1_2_BASE UL(0xF0000000) +#define VA_SPEAR6XX_ML_CPU_BASE UL(0xF0000000) + +/* ICM3 - Basic Subsystem */ +#define SPEAR_ICM3_SMI_CTRL_BASE UL(0xFC000000) +#define VA_SPEAR_ICM3_SMI_CTRL_BASE UL(0xFC000000) +#define SPEAR_ICM3_DMA_BASE UL(0xFC400000) +#define SPEAR_ICM3_SYS_CTRL_BASE UL(0xFCA00000) +#define VA_SPEAR_ICM3_SYS_CTRL_BASE (VA_SPEAR_ICM3_SMI_CTRL_BASE | SPEAR_ICM3_SYS_CTRL_BASE) +#define SPEAR_ICM3_MISC_REG_BASE UL(0xFCA80000) +#define VA_SPEAR_ICM3_MISC_REG_BASE (VA_SPEAR_ICM3_SMI_CTRL_BASE | SPEAR_ICM3_MISC_REG_BASE) + +/* Debug uart for linux, will be used for debug and uncompress messages */ +#define SPEAR_DBG_UART_BASE SPEAR_ICM1_UART_BASE +#define VA_SPEAR_DBG_UART_BASE VA_SPEAR_ICM1_UART_BASE + +/* Sysctl base for spear platform */ +#define SPEAR_SYS_CTRL_BASE SPEAR_ICM3_SYS_CTRL_BASE +#define VA_SPEAR_SYS_CTRL_BASE VA_SPEAR_ICM3_SYS_CTRL_BASE + +/* SPEAr320 Macros */ +#define SPEAR320_SOC_CONFIG_BASE UL(0xB3000000) +#define VA_SPEAR320_SOC_CONFIG_BASE UL(0xFE000000) +#define SPEAR320_CONTROL_REG IOMEM(VA_SPEAR320_SOC_CONFIG_BASE) +#define SPEAR320_EXT_CTRL_REG IOMEM(VA_SPEAR320_SOC_CONFIG_BASE + 0x0018) + #define SPEAR320_UARTX_PCLK_MASK 0x1 + #define SPEAR320_UART2_PCLK_SHIFT 8 + #define SPEAR320_UART3_PCLK_SHIFT 9 + #define SPEAR320_UART4_PCLK_SHIFT 10 + #define SPEAR320_UART5_PCLK_SHIFT 11 + #define SPEAR320_UART6_PCLK_SHIFT 12 + #define SPEAR320_RS485_PCLK_SHIFT 13 +#endif /* SPEAR3xx || SPEAR6XX */ + +#ifdef CONFIG_ARCH_SPEAR13XX + +#define PERIP_GRP2_BASE UL(0xB3000000) +#define VA_PERIP_GRP2_BASE IOMEM(0xFE000000) +#define MCIF_SDHCI_BASE UL(0xB3000000) +#define SYSRAM0_BASE UL(0xB3800000) +#define VA_SYSRAM0_BASE IOMEM(0xFE800000) +#define SYS_LOCATION (VA_SYSRAM0_BASE + 0x600) + +#define PERIP_GRP1_BASE UL(0xE0000000) +#define VA_PERIP_GRP1_BASE IOMEM(0xFD000000) +#define UART_BASE UL(0xE0000000) +#define VA_UART_BASE IOMEM(0xFD000000) +#define SSP_BASE UL(0xE0100000) +#define MISC_BASE UL(0xE0700000) +#define VA_MISC_BASE IOMEM(0xFD700000) + +#define A9SM_AND_MPMC_BASE UL(0xEC000000) +#define VA_A9SM_AND_MPMC_BASE IOMEM(0xFC000000) + +/* A9SM peripheral offsets */ +#define A9SM_PERIP_BASE UL(0xEC800000) +#define VA_A9SM_PERIP_BASE IOMEM(0xFC800000) +#define VA_SCU_BASE (VA_A9SM_PERIP_BASE + 0x00) + +#define L2CC_BASE UL(0xED000000) +#define VA_L2CC_BASE IOMEM(UL(0xFB000000)) + +/* others */ +#define DMAC0_BASE UL(0xEA800000) +#define DMAC1_BASE UL(0xEB000000) +#define MCIF_CF_BASE UL(0xB2800000) + +/* Debug uart for linux, will be used for debug and uncompress messages */ +#define SPEAR_DBG_UART_BASE UART_BASE +#define VA_SPEAR_DBG_UART_BASE VA_UART_BASE + +#endif /* SPEAR13XX */ + +#endif /* __MACH_SPEAR_H */ diff --git a/arch/arm/mach-spear/include/mach/timex.h b/arch/arm/mach-spear/include/mach/timex.h new file mode 100644 index 0000000..ef95e5b --- /dev/null +++ b/arch/arm/mach-spear/include/mach/timex.h @@ -0,0 +1,19 @@ +/* + * arch/arm/plat-spear/include/plat/timex.h + * + * SPEAr platform specific timex definitions + * + * Copyright (C) 2009 ST Microelectronics + * Viresh Kumar + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __PLAT_TIMEX_H +#define __PLAT_TIMEX_H + +#define CLOCK_TICK_RATE 48000000 + +#endif /* __PLAT_TIMEX_H */ diff --git a/arch/arm/mach-spear/include/mach/uncompress.h b/arch/arm/mach-spear/include/mach/uncompress.h new file mode 100644 index 0000000..51b2dc9 --- /dev/null +++ b/arch/arm/mach-spear/include/mach/uncompress.h @@ -0,0 +1,42 @@ +/* + * arch/arm/plat-spear/include/plat/uncompress.h + * + * Serial port stubs for kernel decompress status messages + * + * Copyright (C) 2009 ST Microelectronics + * Viresh Kumar + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include +#include +#include + +#ifndef __PLAT_UNCOMPRESS_H +#define __PLAT_UNCOMPRESS_H +/* + * This does not append a newline + */ +static inline void putc(int c) +{ + void __iomem *base = (void __iomem *)SPEAR_DBG_UART_BASE; + + while (readl_relaxed(base + UART01x_FR) & UART01x_FR_TXFF) + barrier(); + + writel_relaxed(c, base + UART01x_DR); +} + +static inline void flush(void) +{ +} + +/* + * nothing to do + */ +#define arch_decomp_setup() + +#endif /* __PLAT_UNCOMPRESS_H */ diff --git a/arch/arm/mach-spear/include/plat/pl080.h b/arch/arm/mach-spear/include/plat/pl080.h new file mode 100644 index 0000000..eb6590d --- /dev/null +++ b/arch/arm/mach-spear/include/plat/pl080.h @@ -0,0 +1,21 @@ +/* + * arch/arm/plat-spear/include/plat/pl080.h + * + * DMAC pl080 definitions for SPEAr platform + * + * Copyright (C) 2012 ST Microelectronics + * Viresh Kumar + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __PLAT_PL080_H +#define __PLAT_PL080_H + +struct pl08x_channel_data; +int pl080_get_signal(const struct pl08x_channel_data *cd); +void pl080_put_signal(const struct pl08x_channel_data *cd, int signal); + +#endif /* __PLAT_PL080_H */ diff --git a/arch/arm/mach-spear/pl080.c b/arch/arm/mach-spear/pl080.c new file mode 100644 index 0000000..cfa1199 --- /dev/null +++ b/arch/arm/mach-spear/pl080.c @@ -0,0 +1,78 @@ +/* + * arch/arm/plat-spear/pl080.c + * + * DMAC pl080 definitions for SPEAr platform + * + * Copyright (C) 2012 ST Microelectronics + * Viresh Kumar + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +static spinlock_t lock = __SPIN_LOCK_UNLOCKED(x); + +struct { + unsigned char busy; + unsigned char val; +} signals[16] = {{0, 0}, }; + +int pl080_get_signal(const struct pl08x_channel_data *cd) +{ + unsigned int signal = cd->min_signal, val; + unsigned long flags; + + spin_lock_irqsave(&lock, flags); + + /* Return if signal is already acquired by somebody else */ + if (signals[signal].busy && + (signals[signal].val != cd->muxval)) { + spin_unlock_irqrestore(&lock, flags); + return -EBUSY; + } + + /* If acquiring for the first time, configure it */ + if (!signals[signal].busy) { + val = readl(DMA_CHN_CFG); + + /* + * Each request line has two bits in DMA_CHN_CFG register. To + * goto the bits of current request line, do left shift of + * value by 2 * signal number. + */ + val &= ~(0x3 << (signal * 2)); + val |= cd->muxval << (signal * 2); + writel(val, DMA_CHN_CFG); + } + + signals[signal].busy++; + signals[signal].val = cd->muxval; + spin_unlock_irqrestore(&lock, flags); + + return signal; +} + +void pl080_put_signal(const struct pl08x_channel_data *cd, int signal) +{ + unsigned long flags; + + spin_lock_irqsave(&lock, flags); + + /* if signal is not used */ + if (!signals[signal].busy) + BUG(); + + signals[signal].busy--; + + spin_unlock_irqrestore(&lock, flags); +} diff --git a/arch/arm/mach-spear/platsmp.c b/arch/arm/mach-spear/platsmp.c new file mode 100644 index 0000000..af4ade6 --- /dev/null +++ b/arch/arm/mach-spear/platsmp.c @@ -0,0 +1,130 @@ +/* + * arch/arm/mach-spear13xx/platsmp.c + * + * based upon linux/arch/arm/mach-realview/platsmp.c + * + * Copyright (C) 2012 ST Microelectronics Ltd. + * Shiraz Hashim + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static DEFINE_SPINLOCK(boot_lock); + +static void __iomem *scu_base = IOMEM(VA_SCU_BASE); + +static void __cpuinit spear13xx_secondary_init(unsigned int cpu) +{ + /* + * if any interrupts are already enabled for the primary + * core (e.g. timer irq), then they will not have been enabled + * for us: do so + */ + gic_secondary_init(0); + + /* + * let the primary processor know we're out of the + * pen, then head off into the C entry point + */ + pen_release = -1; + smp_wmb(); + + /* + * Synchronise with the boot thread. + */ + spin_lock(&boot_lock); + spin_unlock(&boot_lock); +} + +static int __cpuinit spear13xx_boot_secondary(unsigned int cpu, struct task_struct *idle) +{ + unsigned long timeout; + + /* + * set synchronisation state between this boot processor + * and the secondary one + */ + spin_lock(&boot_lock); + + /* + * The secondary processor is waiting to be released from + * the holding pen - release it, then wait for it to flag + * that it has been released by resetting pen_release. + * + * Note that "pen_release" is the hardware CPU ID, whereas + * "cpu" is Linux's internal ID. + */ + pen_release = cpu; + flush_cache_all(); + outer_flush_all(); + + timeout = jiffies + (1 * HZ); + while (time_before(jiffies, timeout)) { + smp_rmb(); + if (pen_release == -1) + break; + + udelay(10); + } + + /* + * now the secondary core is starting up let it run its + * calibrations, then wait for it to finish + */ + spin_unlock(&boot_lock); + + return pen_release != -1 ? -ENOSYS : 0; +} + +/* + * Initialise the CPU possible map early - this describes the CPUs + * which may be present or become present in the system. + */ +static void __init spear13xx_smp_init_cpus(void) +{ + unsigned int i, ncores = scu_get_core_count(scu_base); + + if (ncores > nr_cpu_ids) { + pr_warn("SMP: %u cores greater than maximum (%u), clipping\n", + ncores, nr_cpu_ids); + ncores = nr_cpu_ids; + } + + for (i = 0; i < ncores; i++) + set_cpu_possible(i, true); +} + +static void __init spear13xx_smp_prepare_cpus(unsigned int max_cpus) +{ + + scu_enable(scu_base); + + /* + * Write the address of secondary startup into the system-wide location + * (presently it is in SRAM). The BootMonitor waits until it receives a + * soft interrupt, and then the secondary CPU branches to this address. + */ + __raw_writel(virt_to_phys(spear13xx_secondary_startup), SYS_LOCATION); +} + +struct smp_operations spear13xx_smp_ops __initdata = { + .smp_init_cpus = spear13xx_smp_init_cpus, + .smp_prepare_cpus = spear13xx_smp_prepare_cpus, + .smp_secondary_init = spear13xx_secondary_init, + .smp_boot_secondary = spear13xx_boot_secondary, +#ifdef CONFIG_HOTPLUG_CPU + .cpu_die = spear13xx_cpu_die, +#endif +}; diff --git a/arch/arm/mach-spear/restart.c b/arch/arm/mach-spear/restart.c new file mode 100644 index 0000000..7d4616d5 --- /dev/null +++ b/arch/arm/mach-spear/restart.c @@ -0,0 +1,33 @@ +/* + * arch/arm/plat-spear/restart.c + * + * SPEAr platform specific restart functions + * + * Copyright (C) 2009 ST Microelectronics + * Viresh Kumar + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ +#include +#include +#include +#include +#include + +#define SPEAR13XX_SYS_SW_RES (VA_MISC_BASE + 0x204) +void spear_restart(char mode, const char *cmd) +{ + if (mode == 's') { + /* software reset, Jump into ROM at address 0 */ + soft_restart(0); + } else { + /* hardware reset, Use on-chip reset capability */ +#ifdef CONFIG_ARCH_SPEAR13XX + writel_relaxed(0x01, SPEAR13XX_SYS_SW_RES); +#else + sysctl_soft_reset((void __iomem *)VA_SPEAR_SYS_CTRL_BASE); +#endif + } +} diff --git a/arch/arm/mach-spear/spear1310.c b/arch/arm/mach-spear/spear1310.c new file mode 100644 index 0000000..56214d1 --- /dev/null +++ b/arch/arm/mach-spear/spear1310.c @@ -0,0 +1,98 @@ +/* + * arch/arm/mach-spear13xx/spear1310.c + * + * SPEAr1310 machine source file + * + * Copyright (C) 2012 ST Microelectronics + * Viresh Kumar + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#define pr_fmt(fmt) "SPEAr1310: " fmt + +#include +#include +#include +#include +#include +#include +#include +#include + +/* Base addresses */ +#define SPEAR1310_SSP1_BASE UL(0x5D400000) +#define SPEAR1310_SATA0_BASE UL(0xB1000000) +#define SPEAR1310_SATA1_BASE UL(0xB1800000) +#define SPEAR1310_SATA2_BASE UL(0xB4000000) + +#define SPEAR1310_RAS_GRP1_BASE UL(0xD8000000) +#define VA_SPEAR1310_RAS_GRP1_BASE UL(0xFA000000) +#define SPEAR1310_RAS_BASE UL(0xD8400000) +#define VA_SPEAR1310_RAS_BASE IOMEM(UL(0xFA400000)) + +static struct arasan_cf_pdata cf_pdata = { + .cf_if_clk = CF_IF_CLK_166M, + .quirk = CF_BROKEN_UDMA, + .dma_priv = &cf_dma_priv, +}; + +/* ssp device registration */ +static struct pl022_ssp_controller ssp1_plat_data = { + .enable_dma = 0, +}; + +/* Add SPEAr1310 auxdata to pass platform data */ +static struct of_dev_auxdata spear1310_auxdata_lookup[] __initdata = { + OF_DEV_AUXDATA("arasan,cf-spear1340", MCIF_CF_BASE, NULL, &cf_pdata), + OF_DEV_AUXDATA("snps,dma-spear1340", DMAC0_BASE, NULL, &dmac_plat_data), + OF_DEV_AUXDATA("snps,dma-spear1340", DMAC1_BASE, NULL, &dmac_plat_data), + OF_DEV_AUXDATA("arm,pl022", SSP_BASE, NULL, &pl022_plat_data), + + OF_DEV_AUXDATA("arm,pl022", SPEAR1310_SSP1_BASE, NULL, &ssp1_plat_data), + {} +}; + +static void __init spear1310_dt_init(void) +{ + of_platform_populate(NULL, of_default_bus_match_table, + spear1310_auxdata_lookup, NULL); +} + +static const char * const spear1310_dt_board_compat[] = { + "st,spear1310", + "st,spear1310-evb", + NULL, +}; + +/* + * Following will create 16MB static virtual/physical mappings + * PHYSICAL VIRTUAL + * 0xD8000000 0xFA000000 + */ +struct map_desc spear1310_io_desc[] __initdata = { + { + .virtual = VA_SPEAR1310_RAS_GRP1_BASE, + .pfn = __phys_to_pfn(SPEAR1310_RAS_GRP1_BASE), + .length = SZ_16M, + .type = MT_DEVICE + }, +}; + +static void __init spear1310_map_io(void) +{ + iotable_init(spear1310_io_desc, ARRAY_SIZE(spear1310_io_desc)); + spear13xx_map_io(); +} + +DT_MACHINE_START(SPEAR1310_DT, "ST SPEAr1310 SoC with Flattened Device Tree") + .smp = smp_ops(spear13xx_smp_ops), + .map_io = spear1310_map_io, + .init_irq = irqchip_init, + .init_time = spear13xx_timer_init, + .init_machine = spear1310_dt_init, + .restart = spear_restart, + .dt_compat = spear1310_dt_board_compat, +MACHINE_END diff --git a/arch/arm/mach-spear/spear1340.c b/arch/arm/mach-spear/spear1340.c new file mode 100644 index 0000000..b01c4c7 --- /dev/null +++ b/arch/arm/mach-spear/spear1340.c @@ -0,0 +1,193 @@ +/* + * arch/arm/mach-spear13xx/spear1340.c + * + * SPEAr1340 machine source file + * + * Copyright (C) 2012 ST Microelectronics + * Viresh Kumar + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#define pr_fmt(fmt) "SPEAr1340: " fmt + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "spear13xx-dma.h" + +/* Base addresses */ +#define SPEAR1340_SATA_BASE UL(0xB1000000) +#define SPEAR1340_UART1_BASE UL(0xB4100000) + +/* Power Management Registers */ +#define SPEAR1340_PCM_CFG (VA_MISC_BASE + 0x100) +#define SPEAR1340_PCM_WKUP_CFG (VA_MISC_BASE + 0x104) +#define SPEAR1340_SWITCH_CTR (VA_MISC_BASE + 0x108) + +#define SPEAR1340_PERIP1_SW_RST (VA_MISC_BASE + 0x318) +#define SPEAR1340_PERIP2_SW_RST (VA_MISC_BASE + 0x31C) +#define SPEAR1340_PERIP3_SW_RST (VA_MISC_BASE + 0x320) + +/* PCIE - SATA configuration registers */ +#define SPEAR1340_PCIE_SATA_CFG (VA_MISC_BASE + 0x424) + /* PCIE CFG MASks */ + #define SPEAR1340_PCIE_CFG_DEVICE_PRESENT (1 << 11) + #define SPEAR1340_PCIE_CFG_POWERUP_RESET (1 << 10) + #define SPEAR1340_PCIE_CFG_CORE_CLK_EN (1 << 9) + #define SPEAR1340_PCIE_CFG_AUX_CLK_EN (1 << 8) + #define SPEAR1340_SATA_CFG_TX_CLK_EN (1 << 4) + #define SPEAR1340_SATA_CFG_RX_CLK_EN (1 << 3) + #define SPEAR1340_SATA_CFG_POWERUP_RESET (1 << 2) + #define SPEAR1340_SATA_CFG_PM_CLK_EN (1 << 1) + #define SPEAR1340_PCIE_SATA_SEL_PCIE (0) + #define SPEAR1340_PCIE_SATA_SEL_SATA (1) + #define SPEAR1340_SATA_PCIE_CFG_MASK 0xF1F + #define SPEAR1340_PCIE_CFG_VAL (SPEAR1340_PCIE_SATA_SEL_PCIE | \ + SPEAR1340_PCIE_CFG_AUX_CLK_EN | \ + SPEAR1340_PCIE_CFG_CORE_CLK_EN | \ + SPEAR1340_PCIE_CFG_POWERUP_RESET | \ + SPEAR1340_PCIE_CFG_DEVICE_PRESENT) + #define SPEAR1340_SATA_CFG_VAL (SPEAR1340_PCIE_SATA_SEL_SATA | \ + SPEAR1340_SATA_CFG_PM_CLK_EN | \ + SPEAR1340_SATA_CFG_POWERUP_RESET | \ + SPEAR1340_SATA_CFG_RX_CLK_EN | \ + SPEAR1340_SATA_CFG_TX_CLK_EN) + +#define SPEAR1340_PCIE_MIPHY_CFG (VA_MISC_BASE + 0x428) + #define SPEAR1340_MIPHY_OSC_BYPASS_EXT (1 << 31) + #define SPEAR1340_MIPHY_CLK_REF_DIV2 (1 << 27) + #define SPEAR1340_MIPHY_CLK_REF_DIV4 (2 << 27) + #define SPEAR1340_MIPHY_CLK_REF_DIV8 (3 << 27) + #define SPEAR1340_MIPHY_PLL_RATIO_TOP(x) (x << 0) + #define SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA \ + (SPEAR1340_MIPHY_OSC_BYPASS_EXT | \ + SPEAR1340_MIPHY_CLK_REF_DIV2 | \ + SPEAR1340_MIPHY_PLL_RATIO_TOP(60)) + #define SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA_25M_CRYSTAL_CLK \ + (SPEAR1340_MIPHY_PLL_RATIO_TOP(120)) + #define SPEAR1340_PCIE_SATA_MIPHY_CFG_PCIE \ + (SPEAR1340_MIPHY_OSC_BYPASS_EXT | \ + SPEAR1340_MIPHY_PLL_RATIO_TOP(25)) + +static struct dw_dma_slave uart1_dma_param[] = { + { + /* Tx */ + .cfg_hi = DWC_CFGH_DST_PER(SPEAR1340_DMA_REQ_UART1_TX), + .cfg_lo = 0, + .src_master = DMA_MASTER_MEMORY, + .dst_master = SPEAR1340_DMA_MASTER_UART1, + }, { + /* Rx */ + .cfg_hi = DWC_CFGH_SRC_PER(SPEAR1340_DMA_REQ_UART1_RX), + .cfg_lo = 0, + .src_master = SPEAR1340_DMA_MASTER_UART1, + .dst_master = DMA_MASTER_MEMORY, + } +}; + +static struct amba_pl011_data uart1_data = { + .dma_filter = dw_dma_filter, + .dma_tx_param = &uart1_dma_param[0], + .dma_rx_param = &uart1_dma_param[1], +}; + +/* SATA device registration */ +static int sata_miphy_init(struct device *dev, void __iomem *addr) +{ + writel(SPEAR1340_SATA_CFG_VAL, SPEAR1340_PCIE_SATA_CFG); + writel(SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA_25M_CRYSTAL_CLK, + SPEAR1340_PCIE_MIPHY_CFG); + /* Switch on sata power domain */ + writel((readl(SPEAR1340_PCM_CFG) | (0x800)), SPEAR1340_PCM_CFG); + msleep(20); + /* Disable PCIE SATA Controller reset */ + writel((readl(SPEAR1340_PERIP1_SW_RST) & (~0x1000)), + SPEAR1340_PERIP1_SW_RST); + msleep(20); + + return 0; +} + +void sata_miphy_exit(struct device *dev) +{ + writel(0, SPEAR1340_PCIE_SATA_CFG); + writel(0, SPEAR1340_PCIE_MIPHY_CFG); + + /* Enable PCIE SATA Controller reset */ + writel((readl(SPEAR1340_PERIP1_SW_RST) | (0x1000)), + SPEAR1340_PERIP1_SW_RST); + msleep(20); + /* Switch off sata power domain */ + writel((readl(SPEAR1340_PCM_CFG) & (~0x800)), SPEAR1340_PCM_CFG); + msleep(20); +} + +int sata_suspend(struct device *dev) +{ + if (dev->power.power_state.event == PM_EVENT_FREEZE) + return 0; + + sata_miphy_exit(dev); + + return 0; +} + +int sata_resume(struct device *dev) +{ + if (dev->power.power_state.event == PM_EVENT_THAW) + return 0; + + return sata_miphy_init(dev, NULL); +} + +static struct ahci_platform_data sata_pdata = { + .init = sata_miphy_init, + .exit = sata_miphy_exit, + .suspend = sata_suspend, + .resume = sata_resume, +}; + +/* Add SPEAr1340 auxdata to pass platform data */ +static struct of_dev_auxdata spear1340_auxdata_lookup[] __initdata = { + OF_DEV_AUXDATA("arasan,cf-spear1340", MCIF_CF_BASE, NULL, &cf_dma_priv), + OF_DEV_AUXDATA("snps,dma-spear1340", DMAC0_BASE, NULL, &dmac_plat_data), + OF_DEV_AUXDATA("snps,dma-spear1340", DMAC1_BASE, NULL, &dmac_plat_data), + OF_DEV_AUXDATA("arm,pl022", SSP_BASE, NULL, &pl022_plat_data), + + OF_DEV_AUXDATA("snps,spear-ahci", SPEAR1340_SATA_BASE, NULL, + &sata_pdata), + OF_DEV_AUXDATA("arm,pl011", SPEAR1340_UART1_BASE, NULL, &uart1_data), + {} +}; + +static void __init spear1340_dt_init(void) +{ + of_platform_populate(NULL, of_default_bus_match_table, + spear1340_auxdata_lookup, NULL); +} + +static const char * const spear1340_dt_board_compat[] = { + "st,spear1340", + "st,spear1340-evb", + NULL, +}; + +DT_MACHINE_START(SPEAR1340_DT, "ST SPEAr1340 SoC with Flattened Device Tree") + .smp = smp_ops(spear13xx_smp_ops), + .map_io = spear13xx_map_io, + .init_irq = irqchip_init, + .init_time = spear13xx_timer_init, + .init_machine = spear1340_dt_init, + .restart = spear_restart, + .dt_compat = spear1340_dt_board_compat, +MACHINE_END diff --git a/arch/arm/mach-spear/spear13xx-dma.h b/arch/arm/mach-spear/spear13xx-dma.h new file mode 100644 index 0000000..d50bdb6 --- /dev/null +++ b/arch/arm/mach-spear/spear13xx-dma.h @@ -0,0 +1,128 @@ +/* + * arch/arm/mach-spear13xx/include/mach/dma.h + * + * DMA information for SPEAr13xx machine family + * + * Copyright (C) 2012 ST Microelectronics + * Viresh Kumar + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __MACH_DMA_H +#define __MACH_DMA_H + +/* request id of all the peripherals */ +enum dma_master_info { + /* Accessible from only one master */ + DMA_MASTER_MCIF = 0, + DMA_MASTER_FSMC = 1, + /* Accessible from both 0 & 1 */ + DMA_MASTER_MEMORY = 0, + DMA_MASTER_ADC = 0, + DMA_MASTER_UART0 = 0, + DMA_MASTER_SSP0 = 0, + DMA_MASTER_I2C0 = 0, + +#ifdef CONFIG_MACH_SPEAR1310 + /* Accessible from only one master */ + SPEAR1310_DMA_MASTER_JPEG = 1, + + /* Accessible from both 0 & 1 */ + SPEAR1310_DMA_MASTER_I2S = 0, + SPEAR1310_DMA_MASTER_UART1 = 0, + SPEAR1310_DMA_MASTER_UART2 = 0, + SPEAR1310_DMA_MASTER_UART3 = 0, + SPEAR1310_DMA_MASTER_UART4 = 0, + SPEAR1310_DMA_MASTER_UART5 = 0, + SPEAR1310_DMA_MASTER_I2C1 = 0, + SPEAR1310_DMA_MASTER_I2C2 = 0, + SPEAR1310_DMA_MASTER_I2C3 = 0, + SPEAR1310_DMA_MASTER_I2C4 = 0, + SPEAR1310_DMA_MASTER_I2C5 = 0, + SPEAR1310_DMA_MASTER_I2C6 = 0, + SPEAR1310_DMA_MASTER_I2C7 = 0, + SPEAR1310_DMA_MASTER_SSP1 = 0, +#endif + +#ifdef CONFIG_MACH_SPEAR1340 + /* Accessible from only one master */ + SPEAR1340_DMA_MASTER_I2S_PLAY = 1, + SPEAR1340_DMA_MASTER_I2S_REC = 1, + SPEAR1340_DMA_MASTER_I2C1 = 1, + SPEAR1340_DMA_MASTER_UART1 = 1, + + /* following are accessible from both master 0 & 1 */ + SPEAR1340_DMA_MASTER_SPDIF = 0, + SPEAR1340_DMA_MASTER_CAM = 1, + SPEAR1340_DMA_MASTER_VIDEO_IN = 0, + SPEAR1340_DMA_MASTER_MALI = 0, +#endif +}; + +enum request_id { + DMA_REQ_ADC = 0, + DMA_REQ_SSP0_TX = 4, + DMA_REQ_SSP0_RX = 5, + DMA_REQ_UART0_TX = 6, + DMA_REQ_UART0_RX = 7, + DMA_REQ_I2C0_TX = 8, + DMA_REQ_I2C0_RX = 9, + +#ifdef CONFIG_MACH_SPEAR1310 + SPEAR1310_DMA_REQ_FROM_JPEG = 2, + SPEAR1310_DMA_REQ_TO_JPEG = 3, + SPEAR1310_DMA_REQ_I2S_TX = 10, + SPEAR1310_DMA_REQ_I2S_RX = 11, + + SPEAR1310_DMA_REQ_I2C1_RX = 0, + SPEAR1310_DMA_REQ_I2C1_TX = 1, + SPEAR1310_DMA_REQ_I2C2_RX = 2, + SPEAR1310_DMA_REQ_I2C2_TX = 3, + SPEAR1310_DMA_REQ_I2C3_RX = 4, + SPEAR1310_DMA_REQ_I2C3_TX = 5, + SPEAR1310_DMA_REQ_I2C4_RX = 6, + SPEAR1310_DMA_REQ_I2C4_TX = 7, + SPEAR1310_DMA_REQ_I2C5_RX = 8, + SPEAR1310_DMA_REQ_I2C5_TX = 9, + SPEAR1310_DMA_REQ_I2C6_RX = 10, + SPEAR1310_DMA_REQ_I2C6_TX = 11, + SPEAR1310_DMA_REQ_UART1_RX = 12, + SPEAR1310_DMA_REQ_UART1_TX = 13, + SPEAR1310_DMA_REQ_UART2_RX = 14, + SPEAR1310_DMA_REQ_UART2_TX = 15, + SPEAR1310_DMA_REQ_UART5_RX = 16, + SPEAR1310_DMA_REQ_UART5_TX = 17, + SPEAR1310_DMA_REQ_SSP1_RX = 18, + SPEAR1310_DMA_REQ_SSP1_TX = 19, + SPEAR1310_DMA_REQ_I2C7_RX = 20, + SPEAR1310_DMA_REQ_I2C7_TX = 21, + SPEAR1310_DMA_REQ_UART3_RX = 28, + SPEAR1310_DMA_REQ_UART3_TX = 29, + SPEAR1310_DMA_REQ_UART4_RX = 30, + SPEAR1310_DMA_REQ_UART4_TX = 31, +#endif + +#ifdef CONFIG_MACH_SPEAR1340 + SPEAR1340_DMA_REQ_SPDIF_TX = 2, + SPEAR1340_DMA_REQ_SPDIF_RX = 3, + SPEAR1340_DMA_REQ_I2S_TX = 10, + SPEAR1340_DMA_REQ_I2S_RX = 11, + SPEAR1340_DMA_REQ_UART1_TX = 12, + SPEAR1340_DMA_REQ_UART1_RX = 13, + SPEAR1340_DMA_REQ_I2C1_TX = 14, + SPEAR1340_DMA_REQ_I2C1_RX = 15, + SPEAR1340_DMA_REQ_CAM0_EVEN = 0, + SPEAR1340_DMA_REQ_CAM0_ODD = 1, + SPEAR1340_DMA_REQ_CAM1_EVEN = 2, + SPEAR1340_DMA_REQ_CAM1_ODD = 3, + SPEAR1340_DMA_REQ_CAM2_EVEN = 4, + SPEAR1340_DMA_REQ_CAM2_ODD = 5, + SPEAR1340_DMA_REQ_CAM3_EVEN = 6, + SPEAR1340_DMA_REQ_CAM3_ODD = 7, +#endif +}; + +#endif /* __MACH_DMA_H */ diff --git a/arch/arm/mach-spear/spear13xx.c b/arch/arm/mach-spear/spear13xx.c new file mode 100644 index 0000000..988fefe --- /dev/null +++ b/arch/arm/mach-spear/spear13xx.c @@ -0,0 +1,184 @@ +/* + * arch/arm/mach-spear13xx/spear13xx.c + * + * SPEAr13XX machines common source file + * + * Copyright (C) 2012 ST Microelectronics + * Viresh Kumar + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#define pr_fmt(fmt) "SPEAr13xx: " fmt + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "spear13xx-dma.h" + +/* common dw_dma filter routine to be used by peripherals */ +bool dw_dma_filter(struct dma_chan *chan, void *slave) +{ + struct dw_dma_slave *dws = (struct dw_dma_slave *)slave; + + if (chan->device->dev == dws->dma_dev) { + chan->private = slave; + return true; + } else { + return false; + } +} + +/* ssp device registration */ +static struct dw_dma_slave ssp_dma_param[] = { + { + /* Tx */ + .cfg_hi = DWC_CFGH_DST_PER(DMA_REQ_SSP0_TX), + .cfg_lo = 0, + .src_master = DMA_MASTER_MEMORY, + .dst_master = DMA_MASTER_SSP0, + }, { + /* Rx */ + .cfg_hi = DWC_CFGH_SRC_PER(DMA_REQ_SSP0_RX), + .cfg_lo = 0, + .src_master = DMA_MASTER_SSP0, + .dst_master = DMA_MASTER_MEMORY, + } +}; + +struct pl022_ssp_controller pl022_plat_data = { + .enable_dma = 1, + .dma_filter = dw_dma_filter, + .dma_rx_param = &ssp_dma_param[1], + .dma_tx_param = &ssp_dma_param[0], +}; + +/* CF device registration */ +struct dw_dma_slave cf_dma_priv = { + .cfg_hi = 0, + .cfg_lo = 0, + .src_master = 0, + .dst_master = 0, +}; + +/* dmac device registeration */ +struct dw_dma_platform_data dmac_plat_data = { + .nr_channels = 8, + .chan_allocation_order = CHAN_ALLOCATION_DESCENDING, + .chan_priority = CHAN_PRIORITY_DESCENDING, + .block_size = 4095U, + .nr_masters = 2, + .data_width = { 3, 3, 0, 0 }, +}; + +void __init spear13xx_l2x0_init(void) +{ + /* + * 512KB (64KB/way), 8-way associativity, parity supported + * + * FIXME: 9th bit, of Auxillary Controller register must be set + * for some spear13xx devices for stable L2 operation. + * + * Enable Early BRESP, L2 prefetch for Instruction and Data, + * write alloc and 'Full line of zero' options + * + */ + + writel_relaxed(0x06, VA_L2CC_BASE + L2X0_PREFETCH_CTRL); + + /* + * Program following latencies in order to make + * SPEAr1340 work at 600 MHz + */ + writel_relaxed(0x221, VA_L2CC_BASE + L2X0_TAG_LATENCY_CTRL); + writel_relaxed(0x441, VA_L2CC_BASE + L2X0_DATA_LATENCY_CTRL); + l2x0_init(VA_L2CC_BASE, 0x70A60001, 0xfe00ffff); +} + +/* + * Following will create 16MB static virtual/physical mappings + * PHYSICAL VIRTUAL + * 0xB3000000 0xFE000000 + * 0xE0000000 0xFD000000 + * 0xEC000000 0xFC000000 + * 0xED000000 0xFB000000 + */ +struct map_desc spear13xx_io_desc[] __initdata = { + { + .virtual = (unsigned long)VA_PERIP_GRP2_BASE, + .pfn = __phys_to_pfn(PERIP_GRP2_BASE), + .length = SZ_16M, + .type = MT_DEVICE + }, { + .virtual = (unsigned long)VA_PERIP_GRP1_BASE, + .pfn = __phys_to_pfn(PERIP_GRP1_BASE), + .length = SZ_16M, + .type = MT_DEVICE + }, { + .virtual = (unsigned long)VA_A9SM_AND_MPMC_BASE, + .pfn = __phys_to_pfn(A9SM_AND_MPMC_BASE), + .length = SZ_16M, + .type = MT_DEVICE + }, { + .virtual = (unsigned long)VA_L2CC_BASE, + .pfn = __phys_to_pfn(L2CC_BASE), + .length = SZ_4K, + .type = MT_DEVICE + }, +}; + +/* This will create static memory mapping for selected devices */ +void __init spear13xx_map_io(void) +{ + iotable_init(spear13xx_io_desc, ARRAY_SIZE(spear13xx_io_desc)); +} + +static void __init spear13xx_clk_init(void) +{ + if (of_machine_is_compatible("st,spear1310")) + spear1310_clk_init(); + else if (of_machine_is_compatible("st,spear1340")) + spear1340_clk_init(); + else + pr_err("%s: Unknown machine\n", __func__); +} + +void __init spear13xx_timer_init(void) +{ + char pclk_name[] = "osc_24m_clk"; + struct clk *gpt_clk, *pclk; + + spear13xx_clk_init(); + + /* get the system timer clock */ + gpt_clk = clk_get_sys("gpt0", NULL); + if (IS_ERR(gpt_clk)) { + pr_err("%s:couldn't get clk for gpt\n", __func__); + BUG(); + } + + /* get the suitable parent clock for timer*/ + pclk = clk_get(NULL, pclk_name); + if (IS_ERR(pclk)) { + pr_err("%s:couldn't get %s as parent for gpt\n", __func__, + pclk_name); + BUG(); + } + + clk_set_parent(gpt_clk, pclk); + clk_put(gpt_clk); + clk_put(pclk); + + spear_setup_of_timer(); + twd_local_timer_of_register(); +} diff --git a/arch/arm/mach-spear/spear300.c b/arch/arm/mach-spear/spear300.c new file mode 100644 index 0000000..72449ee --- /dev/null +++ b/arch/arm/mach-spear/spear300.c @@ -0,0 +1,220 @@ +/* + * arch/arm/mach-spear3xx/spear300.c + * + * SPEAr300 machine source file + * + * Copyright (C) 2009-2012 ST Microelectronics + * Viresh Kumar + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#define pr_fmt(fmt) "SPEAr300: " fmt + +#include +#include +#include +#include +#include +#include + +/* DMAC platform data's slave info */ +struct pl08x_channel_data spear300_dma_info[] = { + { + .bus_id = "uart0_rx", + .min_signal = 2, + .max_signal = 2, + .muxval = 0, + .periph_buses = PL08X_AHB1, + }, { + .bus_id = "uart0_tx", + .min_signal = 3, + .max_signal = 3, + .muxval = 0, + .periph_buses = PL08X_AHB1, + }, { + .bus_id = "ssp0_rx", + .min_signal = 8, + .max_signal = 8, + .muxval = 0, + .periph_buses = PL08X_AHB1, + }, { + .bus_id = "ssp0_tx", + .min_signal = 9, + .max_signal = 9, + .muxval = 0, + .periph_buses = PL08X_AHB1, + }, { + .bus_id = "i2c_rx", + .min_signal = 10, + .max_signal = 10, + .muxval = 0, + .periph_buses = PL08X_AHB1, + }, { + .bus_id = "i2c_tx", + .min_signal = 11, + .max_signal = 11, + .muxval = 0, + .periph_buses = PL08X_AHB1, + }, { + .bus_id = "irda", + .min_signal = 12, + .max_signal = 12, + .muxval = 0, + .periph_buses = PL08X_AHB1, + }, { + .bus_id = "adc", + .min_signal = 13, + .max_signal = 13, + .muxval = 0, + .periph_buses = PL08X_AHB1, + }, { + .bus_id = "to_jpeg", + .min_signal = 14, + .max_signal = 14, + .muxval = 0, + .periph_buses = PL08X_AHB1, + }, { + .bus_id = "from_jpeg", + .min_signal = 15, + .max_signal = 15, + .muxval = 0, + .periph_buses = PL08X_AHB1, + }, { + .bus_id = "ras0_rx", + .min_signal = 0, + .max_signal = 0, + .muxval = 1, + .periph_buses = PL08X_AHB1, + }, { + .bus_id = "ras0_tx", + .min_signal = 1, + .max_signal = 1, + .muxval = 1, + .periph_buses = PL08X_AHB1, + }, { + .bus_id = "ras1_rx", + .min_signal = 2, + .max_signal = 2, + .muxval = 1, + .periph_buses = PL08X_AHB1, + }, { + .bus_id = "ras1_tx", + .min_signal = 3, + .max_signal = 3, + .muxval = 1, + .periph_buses = PL08X_AHB1, + }, { + .bus_id = "ras2_rx", + .min_signal = 4, + .max_signal = 4, + .muxval = 1, + .periph_buses = PL08X_AHB1, + }, { + .bus_id = "ras2_tx", + .min_signal = 5, + .max_signal = 5, + .muxval = 1, + .periph_buses = PL08X_AHB1, + }, { + .bus_id = "ras3_rx", + .min_signal = 6, + .max_signal = 6, + .muxval = 1, + .periph_buses = PL08X_AHB1, + }, { + .bus_id = "ras3_tx", + .min_signal = 7, + .max_signal = 7, + .muxval = 1, + .periph_buses = PL08X_AHB1, + }, { + .bus_id = "ras4_rx", + .min_signal = 8, + .max_signal = 8, + .muxval = 1, + .periph_buses = PL08X_AHB1, + }, { + .bus_id = "ras4_tx", + .min_signal = 9, + .max_signal = 9, + .muxval = 1, + .periph_buses = PL08X_AHB1, + }, { + .bus_id = "ras5_rx", + .min_signal = 10, + .max_signal = 10, + .muxval = 1, + .periph_buses = PL08X_AHB1, + }, { + .bus_id = "ras5_tx", + .min_signal = 11, + .max_signal = 11, + .muxval = 1, + .periph_buses = PL08X_AHB1, + }, { + .bus_id = "ras6_rx", + .min_signal = 12, + .max_signal = 12, + .muxval = 1, + .periph_buses = PL08X_AHB1, + }, { + .bus_id = "ras6_tx", + .min_signal = 13, + .max_signal = 13, + .muxval = 1, + .periph_buses = PL08X_AHB1, + }, { + .bus_id = "ras7_rx", + .min_signal = 14, + .max_signal = 14, + .muxval = 1, + .periph_buses = PL08X_AHB1, + }, { + .bus_id = "ras7_tx", + .min_signal = 15, + .max_signal = 15, + .muxval = 1, + .periph_buses = PL08X_AHB1, + }, +}; + +/* Add SPEAr300 auxdata to pass platform data */ +static struct of_dev_auxdata spear300_auxdata_lookup[] __initdata = { + OF_DEV_AUXDATA("arm,pl022", SPEAR3XX_ICM1_SSP_BASE, NULL, + &pl022_plat_data), + OF_DEV_AUXDATA("arm,pl080", SPEAR_ICM3_DMA_BASE, NULL, + &pl080_plat_data), + {} +}; + +static void __init spear300_dt_init(void) +{ + pl080_plat_data.slave_channels = spear300_dma_info; + pl080_plat_data.num_slave_channels = ARRAY_SIZE(spear300_dma_info); + + of_platform_populate(NULL, of_default_bus_match_table, + spear300_auxdata_lookup, NULL); +} + +static const char * const spear300_dt_board_compat[] = { + "st,spear300", + "st,spear300-evb", + NULL, +}; + +static void __init spear300_map_io(void) +{ + spear3xx_map_io(); +} + +DT_MACHINE_START(SPEAR300_DT, "ST SPEAr300 SoC with Flattened Device Tree") + .map_io = spear300_map_io, + .init_irq = irqchip_init, + .init_time = spear3xx_timer_init, + .init_machine = spear300_dt_init, + .restart = spear_restart, + .dt_compat = spear300_dt_board_compat, +MACHINE_END diff --git a/arch/arm/mach-spear/spear310.c b/arch/arm/mach-spear/spear310.c new file mode 100644 index 0000000..0b7962d --- /dev/null +++ b/arch/arm/mach-spear/spear310.c @@ -0,0 +1,262 @@ +/* + * arch/arm/mach-spear3xx/spear310.c + * + * SPEAr310 machine source file + * + * Copyright (C) 2009-2012 ST Microelectronics + * Viresh Kumar + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#define pr_fmt(fmt) "SPEAr310: " fmt + +#include +#include +#include +#include +#include +#include +#include + +#define SPEAR310_UART1_BASE UL(0xB2000000) +#define SPEAR310_UART2_BASE UL(0xB2080000) +#define SPEAR310_UART3_BASE UL(0xB2100000) +#define SPEAR310_UART4_BASE UL(0xB2180000) +#define SPEAR310_UART5_BASE UL(0xB2200000) + +/* DMAC platform data's slave info */ +struct pl08x_channel_data spear310_dma_info[] = { + { + .bus_id = "uart0_rx", + .min_signal = 2, + .max_signal = 2, + .muxval = 0, + .periph_buses = PL08X_AHB1, + }, { + .bus_id = "uart0_tx", + .min_signal = 3, + .max_signal = 3, + .muxval = 0, + .periph_buses = PL08X_AHB1, + }, { + .bus_id = "ssp0_rx", + .min_signal = 8, + .max_signal = 8, + .muxval = 0, + .periph_buses = PL08X_AHB1, + }, { + .bus_id = "ssp0_tx", + .min_signal = 9, + .max_signal = 9, + .muxval = 0, + .periph_buses = PL08X_AHB1, + }, { + .bus_id = "i2c_rx", + .min_signal = 10, + .max_signal = 10, + .muxval = 0, + .periph_buses = PL08X_AHB1, + }, { + .bus_id = "i2c_tx", + .min_signal = 11, + .max_signal = 11, + .muxval = 0, + .periph_buses = PL08X_AHB1, + }, { + .bus_id = "irda", + .min_signal = 12, + .max_signal = 12, + .muxval = 0, + .periph_buses = PL08X_AHB1, + }, { + .bus_id = "adc", + .min_signal = 13, + .max_signal = 13, + .muxval = 0, + .periph_buses = PL08X_AHB1, + }, { + .bus_id = "to_jpeg", + .min_signal = 14, + .max_signal = 14, + .muxval = 0, + .periph_buses = PL08X_AHB1, + }, { + .bus_id = "from_jpeg", + .min_signal = 15, + .max_signal = 15, + .muxval = 0, + .periph_buses = PL08X_AHB1, + }, { + .bus_id = "uart1_rx", + .min_signal = 0, + .max_signal = 0, + .muxval = 1, + .periph_buses = PL08X_AHB1, + }, { + .bus_id = "uart1_tx", + .min_signal = 1, + .max_signal = 1, + .muxval = 1, + .periph_buses = PL08X_AHB1, + }, { + .bus_id = "uart2_rx", + .min_signal = 2, + .max_signal = 2, + .muxval = 1, + .periph_buses = PL08X_AHB1, + }, { + .bus_id = "uart2_tx", + .min_signal = 3, + .max_signal = 3, + .muxval = 1, + .periph_buses = PL08X_AHB1, + }, { + .bus_id = "uart3_rx", + .min_signal = 4, + .max_signal = 4, + .muxval = 1, + .periph_buses = PL08X_AHB1, + }, { + .bus_id = "uart3_tx", + .min_signal = 5, + .max_signal = 5, + .muxval = 1, + .periph_buses = PL08X_AHB1, + }, { + .bus_id = "uart4_rx", + .min_signal = 6, + .max_signal = 6, + .muxval = 1, + .periph_buses = PL08X_AHB1, + }, { + .bus_id = "uart4_tx", + .min_signal = 7, + .max_signal = 7, + .muxval = 1, + .periph_buses = PL08X_AHB1, + }, { + .bus_id = "uart5_rx", + .min_signal = 8, + .max_signal = 8, + .muxval = 1, + .periph_buses = PL08X_AHB1, + }, { + .bus_id = "uart5_tx", + .min_signal = 9, + .max_signal = 9, + .muxval = 1, + .periph_buses = PL08X_AHB1, + }, { + .bus_id = "ras5_rx", + .min_signal = 10, + .max_signal = 10, + .muxval = 1, + .periph_buses = PL08X_AHB1, + }, { + .bus_id = "ras5_tx", + .min_signal = 11, + .max_signal = 11, + .muxval = 1, + .periph_buses = PL08X_AHB1, + }, { + .bus_id = "ras6_rx", + .min_signal = 12, + .max_signal = 12, + .muxval = 1, + .periph_buses = PL08X_AHB1, + }, { + .bus_id = "ras6_tx", + .min_signal = 13, + .max_signal = 13, + .muxval = 1, + .periph_buses = PL08X_AHB1, + }, { + .bus_id = "ras7_rx", + .min_signal = 14, + .max_signal = 14, + .muxval = 1, + .periph_buses = PL08X_AHB1, + }, { + .bus_id = "ras7_tx", + .min_signal = 15, + .max_signal = 15, + .muxval = 1, + .periph_buses = PL08X_AHB1, + }, +}; + +/* uart devices plat data */ +static struct amba_pl011_data spear310_uart_data[] = { + { + .dma_filter = pl08x_filter_id, + .dma_tx_param = "uart1_tx", + .dma_rx_param = "uart1_rx", + }, { + .dma_filter = pl08x_filter_id, + .dma_tx_param = "uart2_tx", + .dma_rx_param = "uart2_rx", + }, { + .dma_filter = pl08x_filter_id, + .dma_tx_param = "uart3_tx", + .dma_rx_param = "uart3_rx", + }, { + .dma_filter = pl08x_filter_id, + .dma_tx_param = "uart4_tx", + .dma_rx_param = "uart4_rx", + }, { + .dma_filter = pl08x_filter_id, + .dma_tx_param = "uart5_tx", + .dma_rx_param = "uart5_rx", + }, +}; + +/* Add SPEAr310 auxdata to pass platform data */ +static struct of_dev_auxdata spear310_auxdata_lookup[] __initdata = { + OF_DEV_AUXDATA("arm,pl022", SPEAR3XX_ICM1_SSP_BASE, NULL, + &pl022_plat_data), + OF_DEV_AUXDATA("arm,pl080", SPEAR_ICM3_DMA_BASE, NULL, + &pl080_plat_data), + OF_DEV_AUXDATA("arm,pl011", SPEAR310_UART1_BASE, NULL, + &spear310_uart_data[0]), + OF_DEV_AUXDATA("arm,pl011", SPEAR310_UART2_BASE, NULL, + &spear310_uart_data[1]), + OF_DEV_AUXDATA("arm,pl011", SPEAR310_UART3_BASE, NULL, + &spear310_uart_data[2]), + OF_DEV_AUXDATA("arm,pl011", SPEAR310_UART4_BASE, NULL, + &spear310_uart_data[3]), + OF_DEV_AUXDATA("arm,pl011", SPEAR310_UART5_BASE, NULL, + &spear310_uart_data[4]), + {} +}; + +static void __init spear310_dt_init(void) +{ + pl080_plat_data.slave_channels = spear310_dma_info; + pl080_plat_data.num_slave_channels = ARRAY_SIZE(spear310_dma_info); + + of_platform_populate(NULL, of_default_bus_match_table, + spear310_auxdata_lookup, NULL); +} + +static const char * const spear310_dt_board_compat[] = { + "st,spear310", + "st,spear310-evb", + NULL, +}; + +static void __init spear310_map_io(void) +{ + spear3xx_map_io(); +} + +DT_MACHINE_START(SPEAR310_DT, "ST SPEAr310 SoC with Flattened Device Tree") + .map_io = spear310_map_io, + .init_irq = irqchip_init, + .init_time = spear3xx_timer_init, + .init_machine = spear310_dt_init, + .restart = spear_restart, + .dt_compat = spear310_dt_board_compat, +MACHINE_END diff --git a/arch/arm/mach-spear/spear320.c b/arch/arm/mach-spear/spear320.c new file mode 100644 index 0000000..e9db7db --- /dev/null +++ b/arch/arm/mach-spear/spear320.c @@ -0,0 +1,277 @@ +/* + * arch/arm/mach-spear3xx/spear320.c + * + * SPEAr320 machine source file + * + * Copyright (C) 2009-2012 ST Microelectronics + * Viresh Kumar + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#define pr_fmt(fmt) "SPEAr320: " fmt + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define SPEAR320_UART1_BASE UL(0xA3000000) +#define SPEAR320_UART2_BASE UL(0xA4000000) +#define SPEAR320_SSP0_BASE UL(0xA5000000) +#define SPEAR320_SSP1_BASE UL(0xA6000000) + +/* DMAC platform data's slave info */ +struct pl08x_channel_data spear320_dma_info[] = { + { + .bus_id = "uart0_rx", + .min_signal = 2, + .max_signal = 2, + .muxval = 0, + .periph_buses = PL08X_AHB1, + }, { + .bus_id = "uart0_tx", + .min_signal = 3, + .max_signal = 3, + .muxval = 0, + .periph_buses = PL08X_AHB1, + }, { + .bus_id = "ssp0_rx", + .min_signal = 8, + .max_signal = 8, + .muxval = 0, + .periph_buses = PL08X_AHB1, + }, { + .bus_id = "ssp0_tx", + .min_signal = 9, + .max_signal = 9, + .muxval = 0, + .periph_buses = PL08X_AHB1, + }, { + .bus_id = "i2c0_rx", + .min_signal = 10, + .max_signal = 10, + .muxval = 0, + .periph_buses = PL08X_AHB1, + }, { + .bus_id = "i2c0_tx", + .min_signal = 11, + .max_signal = 11, + .muxval = 0, + .periph_buses = PL08X_AHB1, + }, { + .bus_id = "irda", + .min_signal = 12, + .max_signal = 12, + .muxval = 0, + .periph_buses = PL08X_AHB1, + }, { + .bus_id = "adc", + .min_signal = 13, + .max_signal = 13, + .muxval = 0, + .periph_buses = PL08X_AHB1, + }, { + .bus_id = "to_jpeg", + .min_signal = 14, + .max_signal = 14, + .muxval = 0, + .periph_buses = PL08X_AHB1, + }, { + .bus_id = "from_jpeg", + .min_signal = 15, + .max_signal = 15, + .muxval = 0, + .periph_buses = PL08X_AHB1, + }, { + .bus_id = "ssp1_rx", + .min_signal = 0, + .max_signal = 0, + .muxval = 1, + .periph_buses = PL08X_AHB2, + }, { + .bus_id = "ssp1_tx", + .min_signal = 1, + .max_signal = 1, + .muxval = 1, + .periph_buses = PL08X_AHB2, + }, { + .bus_id = "ssp2_rx", + .min_signal = 2, + .max_signal = 2, + .muxval = 1, + .periph_buses = PL08X_AHB2, + }, { + .bus_id = "ssp2_tx", + .min_signal = 3, + .max_signal = 3, + .muxval = 1, + .periph_buses = PL08X_AHB2, + }, { + .bus_id = "uart1_rx", + .min_signal = 4, + .max_signal = 4, + .muxval = 1, + .periph_buses = PL08X_AHB2, + }, { + .bus_id = "uart1_tx", + .min_signal = 5, + .max_signal = 5, + .muxval = 1, + .periph_buses = PL08X_AHB2, + }, { + .bus_id = "uart2_rx", + .min_signal = 6, + .max_signal = 6, + .muxval = 1, + .periph_buses = PL08X_AHB2, + }, { + .bus_id = "uart2_tx", + .min_signal = 7, + .max_signal = 7, + .muxval = 1, + .periph_buses = PL08X_AHB2, + }, { + .bus_id = "i2c1_rx", + .min_signal = 8, + .max_signal = 8, + .muxval = 1, + .periph_buses = PL08X_AHB2, + }, { + .bus_id = "i2c1_tx", + .min_signal = 9, + .max_signal = 9, + .muxval = 1, + .periph_buses = PL08X_AHB2, + }, { + .bus_id = "i2c2_rx", + .min_signal = 10, + .max_signal = 10, + .muxval = 1, + .periph_buses = PL08X_AHB2, + }, { + .bus_id = "i2c2_tx", + .min_signal = 11, + .max_signal = 11, + .muxval = 1, + .periph_buses = PL08X_AHB2, + }, { + .bus_id = "i2s_rx", + .min_signal = 12, + .max_signal = 12, + .muxval = 1, + .periph_buses = PL08X_AHB2, + }, { + .bus_id = "i2s_tx", + .min_signal = 13, + .max_signal = 13, + .muxval = 1, + .periph_buses = PL08X_AHB2, + }, { + .bus_id = "rs485_rx", + .min_signal = 14, + .max_signal = 14, + .muxval = 1, + .periph_buses = PL08X_AHB2, + }, { + .bus_id = "rs485_tx", + .min_signal = 15, + .max_signal = 15, + .muxval = 1, + .periph_buses = PL08X_AHB2, + }, +}; + +static struct pl022_ssp_controller spear320_ssp_data[] = { + { + .bus_id = 1, + .enable_dma = 1, + .dma_filter = pl08x_filter_id, + .dma_tx_param = "ssp1_tx", + .dma_rx_param = "ssp1_rx", + .num_chipselect = 2, + }, { + .bus_id = 2, + .enable_dma = 1, + .dma_filter = pl08x_filter_id, + .dma_tx_param = "ssp2_tx", + .dma_rx_param = "ssp2_rx", + .num_chipselect = 2, + } +}; + +static struct amba_pl011_data spear320_uart_data[] = { + { + .dma_filter = pl08x_filter_id, + .dma_tx_param = "uart1_tx", + .dma_rx_param = "uart1_rx", + }, { + .dma_filter = pl08x_filter_id, + .dma_tx_param = "uart2_tx", + .dma_rx_param = "uart2_rx", + }, +}; + +/* Add SPEAr310 auxdata to pass platform data */ +static struct of_dev_auxdata spear320_auxdata_lookup[] __initdata = { + OF_DEV_AUXDATA("arm,pl022", SPEAR3XX_ICM1_SSP_BASE, NULL, + &pl022_plat_data), + OF_DEV_AUXDATA("arm,pl080", SPEAR_ICM3_DMA_BASE, NULL, + &pl080_plat_data), + OF_DEV_AUXDATA("arm,pl022", SPEAR320_SSP0_BASE, NULL, + &spear320_ssp_data[0]), + OF_DEV_AUXDATA("arm,pl022", SPEAR320_SSP1_BASE, NULL, + &spear320_ssp_data[1]), + OF_DEV_AUXDATA("arm,pl011", SPEAR320_UART1_BASE, NULL, + &spear320_uart_data[0]), + OF_DEV_AUXDATA("arm,pl011", SPEAR320_UART2_BASE, NULL, + &spear320_uart_data[1]), + {} +}; + +static void __init spear320_dt_init(void) +{ + pl080_plat_data.slave_channels = spear320_dma_info; + pl080_plat_data.num_slave_channels = ARRAY_SIZE(spear320_dma_info); + + of_platform_populate(NULL, of_default_bus_match_table, + spear320_auxdata_lookup, NULL); +} + +static const char * const spear320_dt_board_compat[] = { + "st,spear320", + "st,spear320-evb", + "st,spear320-hmi", + NULL, +}; + +struct map_desc spear320_io_desc[] __initdata = { + { + .virtual = VA_SPEAR320_SOC_CONFIG_BASE, + .pfn = __phys_to_pfn(SPEAR320_SOC_CONFIG_BASE), + .length = SZ_16M, + .type = MT_DEVICE + }, +}; + +static void __init spear320_map_io(void) +{ + iotable_init(spear320_io_desc, ARRAY_SIZE(spear320_io_desc)); + spear3xx_map_io(); +} + +DT_MACHINE_START(SPEAR320_DT, "ST SPEAr320 SoC with Flattened Device Tree") + .map_io = spear320_map_io, + .init_irq = irqchip_init, + .init_time = spear3xx_timer_init, + .init_machine = spear320_dt_init, + .restart = spear_restart, + .dt_compat = spear320_dt_board_compat, +MACHINE_END diff --git a/arch/arm/mach-spear/spear3xx.c b/arch/arm/mach-spear/spear3xx.c new file mode 100644 index 0000000..d7580f2 --- /dev/null +++ b/arch/arm/mach-spear/spear3xx.c @@ -0,0 +1,115 @@ +/* + * arch/arm/mach-spear3xx/spear3xx.c + * + * SPEAr3XX machines common source file + * + * Copyright (C) 2009-2012 ST Microelectronics + * Viresh Kumar + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#define pr_fmt(fmt) "SPEAr3xx: " fmt + +#include +#include +#include +#include +#include +#include +#include +#include + +/* ssp device registration */ +struct pl022_ssp_controller pl022_plat_data = { + .bus_id = 0, + .enable_dma = 1, + .dma_filter = pl08x_filter_id, + .dma_tx_param = "ssp0_tx", + .dma_rx_param = "ssp0_rx", + /* + * This is number of spi devices that can be connected to spi. There are + * two type of chipselects on which slave devices can work. One is chip + * select provided by spi masters other is controlled through external + * gpio's. We can't use chipselect provided from spi master (because as + * soon as FIFO becomes empty, CS is disabled and transfer ends). So + * this number now depends on number of gpios available for spi. each + * slave on each master requires a separate gpio pin. + */ + .num_chipselect = 2, +}; + +/* dmac device registration */ +struct pl08x_platform_data pl080_plat_data = { + .memcpy_channel = { + .bus_id = "memcpy", + .cctl_memcpy = + (PL080_BSIZE_16 << PL080_CONTROL_SB_SIZE_SHIFT | \ + PL080_BSIZE_16 << PL080_CONTROL_DB_SIZE_SHIFT | \ + PL080_WIDTH_32BIT << PL080_CONTROL_SWIDTH_SHIFT | \ + PL080_WIDTH_32BIT << PL080_CONTROL_DWIDTH_SHIFT | \ + PL080_CONTROL_PROT_BUFF | PL080_CONTROL_PROT_CACHE | \ + PL080_CONTROL_PROT_SYS), + }, + .lli_buses = PL08X_AHB1, + .mem_buses = PL08X_AHB1, + .get_signal = pl080_get_signal, + .put_signal = pl080_put_signal, +}; + +/* + * Following will create 16MB static virtual/physical mappings + * PHYSICAL VIRTUAL + * 0xD0000000 0xFD000000 + * 0xFC000000 0xFC000000 + */ +struct map_desc spear3xx_io_desc[] __initdata = { + { + .virtual = VA_SPEAR_ICM1_2_BASE, + .pfn = __phys_to_pfn(SPEAR_ICM1_2_BASE), + .length = SZ_16M, + .type = MT_DEVICE + }, { + .virtual = VA_SPEAR_ICM3_SMI_CTRL_BASE, + .pfn = __phys_to_pfn(SPEAR_ICM3_SMI_CTRL_BASE), + .length = SZ_16M, + .type = MT_DEVICE + }, +}; + +/* This will create static memory mapping for selected devices */ +void __init spear3xx_map_io(void) +{ + iotable_init(spear3xx_io_desc, ARRAY_SIZE(spear3xx_io_desc)); +} + +void __init spear3xx_timer_init(void) +{ + char pclk_name[] = "pll3_clk"; + struct clk *gpt_clk, *pclk; + + spear3xx_clk_init(); + + /* get the system timer clock */ + gpt_clk = clk_get_sys("gpt0", NULL); + if (IS_ERR(gpt_clk)) { + pr_err("%s:couldn't get clk for gpt\n", __func__); + BUG(); + } + + /* get the suitable parent clock for timer*/ + pclk = clk_get(NULL, pclk_name); + if (IS_ERR(pclk)) { + pr_err("%s:couldn't get %s as parent for gpt\n", + __func__, pclk_name); + BUG(); + } + + clk_set_parent(gpt_clk, pclk); + clk_put(gpt_clk); + clk_put(pclk); + + spear_setup_of_timer(); +} diff --git a/arch/arm/mach-spear/spear6xx.c b/arch/arm/mach-spear/spear6xx.c new file mode 100644 index 0000000..97fb31d --- /dev/null +++ b/arch/arm/mach-spear/spear6xx.c @@ -0,0 +1,430 @@ +/* + * arch/arm/mach-spear6xx/spear6xx.c + * + * SPEAr6XX machines common source file + * + * Copyright (C) 2009 ST Microelectronics + * Rajeev Kumar + * + * Copyright 2012 Stefan Roese + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* dmac device registration */ +static struct pl08x_channel_data spear600_dma_info[] = { + { + .bus_id = "ssp1_rx", + .min_signal = 0, + .max_signal = 0, + .muxval = 0, + .periph_buses = PL08X_AHB1, + }, { + .bus_id = "ssp1_tx", + .min_signal = 1, + .max_signal = 1, + .muxval = 0, + .periph_buses = PL08X_AHB1, + }, { + .bus_id = "uart0_rx", + .min_signal = 2, + .max_signal = 2, + .muxval = 0, + .periph_buses = PL08X_AHB1, + }, { + .bus_id = "uart0_tx", + .min_signal = 3, + .max_signal = 3, + .muxval = 0, + .periph_buses = PL08X_AHB1, + }, { + .bus_id = "uart1_rx", + .min_signal = 4, + .max_signal = 4, + .muxval = 0, + .periph_buses = PL08X_AHB1, + }, { + .bus_id = "uart1_tx", + .min_signal = 5, + .max_signal = 5, + .muxval = 0, + .periph_buses = PL08X_AHB1, + }, { + .bus_id = "ssp2_rx", + .min_signal = 6, + .max_signal = 6, + .muxval = 0, + .periph_buses = PL08X_AHB2, + }, { + .bus_id = "ssp2_tx", + .min_signal = 7, + .max_signal = 7, + .muxval = 0, + .periph_buses = PL08X_AHB2, + }, { + .bus_id = "ssp0_rx", + .min_signal = 8, + .max_signal = 8, + .muxval = 0, + .periph_buses = PL08X_AHB1, + }, { + .bus_id = "ssp0_tx", + .min_signal = 9, + .max_signal = 9, + .muxval = 0, + .periph_buses = PL08X_AHB1, + }, { + .bus_id = "i2c_rx", + .min_signal = 10, + .max_signal = 10, + .muxval = 0, + .periph_buses = PL08X_AHB1, + }, { + .bus_id = "i2c_tx", + .min_signal = 11, + .max_signal = 11, + .muxval = 0, + .periph_buses = PL08X_AHB1, + }, { + .bus_id = "irda", + .min_signal = 12, + .max_signal = 12, + .muxval = 0, + .periph_buses = PL08X_AHB1, + }, { + .bus_id = "adc", + .min_signal = 13, + .max_signal = 13, + .muxval = 0, + .periph_buses = PL08X_AHB2, + }, { + .bus_id = "to_jpeg", + .min_signal = 14, + .max_signal = 14, + .muxval = 0, + .periph_buses = PL08X_AHB1, + }, { + .bus_id = "from_jpeg", + .min_signal = 15, + .max_signal = 15, + .muxval = 0, + .periph_buses = PL08X_AHB1, + }, { + .bus_id = "ras0_rx", + .min_signal = 0, + .max_signal = 0, + .muxval = 1, + .periph_buses = PL08X_AHB1, + }, { + .bus_id = "ras0_tx", + .min_signal = 1, + .max_signal = 1, + .muxval = 1, + .periph_buses = PL08X_AHB1, + }, { + .bus_id = "ras1_rx", + .min_signal = 2, + .max_signal = 2, + .muxval = 1, + .periph_buses = PL08X_AHB1, + }, { + .bus_id = "ras1_tx", + .min_signal = 3, + .max_signal = 3, + .muxval = 1, + .periph_buses = PL08X_AHB1, + }, { + .bus_id = "ras2_rx", + .min_signal = 4, + .max_signal = 4, + .muxval = 1, + .periph_buses = PL08X_AHB1, + }, { + .bus_id = "ras2_tx", + .min_signal = 5, + .max_signal = 5, + .muxval = 1, + .periph_buses = PL08X_AHB1, + }, { + .bus_id = "ras3_rx", + .min_signal = 6, + .max_signal = 6, + .muxval = 1, + .periph_buses = PL08X_AHB1, + }, { + .bus_id = "ras3_tx", + .min_signal = 7, + .max_signal = 7, + .muxval = 1, + .periph_buses = PL08X_AHB1, + }, { + .bus_id = "ras4_rx", + .min_signal = 8, + .max_signal = 8, + .muxval = 1, + .periph_buses = PL08X_AHB1, + }, { + .bus_id = "ras4_tx", + .min_signal = 9, + .max_signal = 9, + .muxval = 1, + .periph_buses = PL08X_AHB1, + }, { + .bus_id = "ras5_rx", + .min_signal = 10, + .max_signal = 10, + .muxval = 1, + .periph_buses = PL08X_AHB1, + }, { + .bus_id = "ras5_tx", + .min_signal = 11, + .max_signal = 11, + .muxval = 1, + .periph_buses = PL08X_AHB1, + }, { + .bus_id = "ras6_rx", + .min_signal = 12, + .max_signal = 12, + .muxval = 1, + .periph_buses = PL08X_AHB1, + }, { + .bus_id = "ras6_tx", + .min_signal = 13, + .max_signal = 13, + .muxval = 1, + .periph_buses = PL08X_AHB1, + }, { + .bus_id = "ras7_rx", + .min_signal = 14, + .max_signal = 14, + .muxval = 1, + .periph_buses = PL08X_AHB1, + }, { + .bus_id = "ras7_tx", + .min_signal = 15, + .max_signal = 15, + .muxval = 1, + .periph_buses = PL08X_AHB1, + }, { + .bus_id = "ext0_rx", + .min_signal = 0, + .max_signal = 0, + .muxval = 2, + .periph_buses = PL08X_AHB2, + }, { + .bus_id = "ext0_tx", + .min_signal = 1, + .max_signal = 1, + .muxval = 2, + .periph_buses = PL08X_AHB2, + }, { + .bus_id = "ext1_rx", + .min_signal = 2, + .max_signal = 2, + .muxval = 2, + .periph_buses = PL08X_AHB2, + }, { + .bus_id = "ext1_tx", + .min_signal = 3, + .max_signal = 3, + .muxval = 2, + .periph_buses = PL08X_AHB2, + }, { + .bus_id = "ext2_rx", + .min_signal = 4, + .max_signal = 4, + .muxval = 2, + .periph_buses = PL08X_AHB2, + }, { + .bus_id = "ext2_tx", + .min_signal = 5, + .max_signal = 5, + .muxval = 2, + .periph_buses = PL08X_AHB2, + }, { + .bus_id = "ext3_rx", + .min_signal = 6, + .max_signal = 6, + .muxval = 2, + .periph_buses = PL08X_AHB2, + }, { + .bus_id = "ext3_tx", + .min_signal = 7, + .max_signal = 7, + .muxval = 2, + .periph_buses = PL08X_AHB2, + }, { + .bus_id = "ext4_rx", + .min_signal = 8, + .max_signal = 8, + .muxval = 2, + .periph_buses = PL08X_AHB2, + }, { + .bus_id = "ext4_tx", + .min_signal = 9, + .max_signal = 9, + .muxval = 2, + .periph_buses = PL08X_AHB2, + }, { + .bus_id = "ext5_rx", + .min_signal = 10, + .max_signal = 10, + .muxval = 2, + .periph_buses = PL08X_AHB2, + }, { + .bus_id = "ext5_tx", + .min_signal = 11, + .max_signal = 11, + .muxval = 2, + .periph_buses = PL08X_AHB2, + }, { + .bus_id = "ext6_rx", + .min_signal = 12, + .max_signal = 12, + .muxval = 2, + .periph_buses = PL08X_AHB2, + }, { + .bus_id = "ext6_tx", + .min_signal = 13, + .max_signal = 13, + .muxval = 2, + .periph_buses = PL08X_AHB2, + }, { + .bus_id = "ext7_rx", + .min_signal = 14, + .max_signal = 14, + .muxval = 2, + .periph_buses = PL08X_AHB2, + }, { + .bus_id = "ext7_tx", + .min_signal = 15, + .max_signal = 15, + .muxval = 2, + .periph_buses = PL08X_AHB2, + }, +}; + +struct pl08x_platform_data pl080_plat_data = { + .memcpy_channel = { + .bus_id = "memcpy", + .cctl_memcpy = + (PL080_BSIZE_16 << PL080_CONTROL_SB_SIZE_SHIFT | \ + PL080_BSIZE_16 << PL080_CONTROL_DB_SIZE_SHIFT | \ + PL080_WIDTH_32BIT << PL080_CONTROL_SWIDTH_SHIFT | \ + PL080_WIDTH_32BIT << PL080_CONTROL_DWIDTH_SHIFT | \ + PL080_CONTROL_PROT_BUFF | PL080_CONTROL_PROT_CACHE | \ + PL080_CONTROL_PROT_SYS), + }, + .lli_buses = PL08X_AHB1, + .mem_buses = PL08X_AHB1, + .get_signal = pl080_get_signal, + .put_signal = pl080_put_signal, + .slave_channels = spear600_dma_info, + .num_slave_channels = ARRAY_SIZE(spear600_dma_info), +}; + +/* + * Following will create 16MB static virtual/physical mappings + * PHYSICAL VIRTUAL + * 0xF0000000 0xF0000000 + * 0xF1000000 0xF1000000 + * 0xD0000000 0xFD000000 + * 0xFC000000 0xFC000000 + */ +struct map_desc spear6xx_io_desc[] __initdata = { + { + .virtual = VA_SPEAR6XX_ML_CPU_BASE, + .pfn = __phys_to_pfn(SPEAR_ICM3_ML1_2_BASE), + .length = 2 * SZ_16M, + .type = MT_DEVICE + }, { + .virtual = VA_SPEAR_ICM1_2_BASE, + .pfn = __phys_to_pfn(SPEAR_ICM1_2_BASE), + .length = SZ_16M, + .type = MT_DEVICE + }, { + .virtual = VA_SPEAR_ICM3_SMI_CTRL_BASE, + .pfn = __phys_to_pfn(SPEAR_ICM3_SMI_CTRL_BASE), + .length = SZ_16M, + .type = MT_DEVICE + }, +}; + +/* This will create static memory mapping for selected devices */ +void __init spear6xx_map_io(void) +{ + iotable_init(spear6xx_io_desc, ARRAY_SIZE(spear6xx_io_desc)); +} + +void __init spear6xx_timer_init(void) +{ + char pclk_name[] = "pll3_clk"; + struct clk *gpt_clk, *pclk; + + spear6xx_clk_init(); + + /* get the system timer clock */ + gpt_clk = clk_get_sys("gpt0", NULL); + if (IS_ERR(gpt_clk)) { + pr_err("%s:couldn't get clk for gpt\n", __func__); + BUG(); + } + + /* get the suitable parent clock for timer*/ + pclk = clk_get(NULL, pclk_name); + if (IS_ERR(pclk)) { + pr_err("%s:couldn't get %s as parent for gpt\n", + __func__, pclk_name); + BUG(); + } + + clk_set_parent(gpt_clk, pclk); + clk_put(gpt_clk); + clk_put(pclk); + + spear_setup_of_timer(); +} + +/* Add auxdata to pass platform data */ +struct of_dev_auxdata spear6xx_auxdata_lookup[] __initdata = { + OF_DEV_AUXDATA("arm,pl080", SPEAR_ICM3_DMA_BASE, NULL, + &pl080_plat_data), + {} +}; + +static void __init spear600_dt_init(void) +{ + of_platform_populate(NULL, of_default_bus_match_table, + spear6xx_auxdata_lookup, NULL); +} + +static const char *spear600_dt_board_compat[] = { + "st,spear600", + NULL +}; + +DT_MACHINE_START(SPEAR600_DT, "ST SPEAr600 (Flattened Device Tree)") + .map_io = spear6xx_map_io, + .init_irq = irqchip_init, + .init_time = spear6xx_timer_init, + .init_machine = spear600_dt_init, + .restart = spear_restart, + .dt_compat = spear600_dt_board_compat, +MACHINE_END diff --git a/arch/arm/mach-spear/time.c b/arch/arm/mach-spear/time.c new file mode 100644 index 0000000..bd5c53c --- /dev/null +++ b/arch/arm/mach-spear/time.c @@ -0,0 +1,245 @@ +/* + * arch/arm/plat-spear/time.c + * + * Copyright (C) 2010 ST Microelectronics + * Shiraz Hashim + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* + * We would use TIMER0 and TIMER1 as clockevent and clocksource. + * Timer0 and Timer1 both belong to same gpt block in cpu subbsystem. Further + * they share same functional clock. Any change in one's functional clock will + * also affect other timer. + */ + +#define CLKEVT 0 /* gpt0, channel0 as clockevent */ +#define CLKSRC 1 /* gpt0, channel1 as clocksource */ + +/* Register offsets, x is channel number */ +#define CR(x) ((x) * 0x80 + 0x80) +#define IR(x) ((x) * 0x80 + 0x84) +#define LOAD(x) ((x) * 0x80 + 0x88) +#define COUNT(x) ((x) * 0x80 + 0x8C) + +/* Reg bit definitions */ +#define CTRL_INT_ENABLE 0x0100 +#define CTRL_ENABLE 0x0020 +#define CTRL_ONE_SHOT 0x0010 + +#define CTRL_PRESCALER1 0x0 +#define CTRL_PRESCALER2 0x1 +#define CTRL_PRESCALER4 0x2 +#define CTRL_PRESCALER8 0x3 +#define CTRL_PRESCALER16 0x4 +#define CTRL_PRESCALER32 0x5 +#define CTRL_PRESCALER64 0x6 +#define CTRL_PRESCALER128 0x7 +#define CTRL_PRESCALER256 0x8 + +#define INT_STATUS 0x1 + +/* + * Minimum clocksource/clockevent timer range in seconds + */ +#define SPEAR_MIN_RANGE 4 + +static __iomem void *gpt_base; +static struct clk *gpt_clk; + +static void clockevent_set_mode(enum clock_event_mode mode, + struct clock_event_device *clk_event_dev); +static int clockevent_next_event(unsigned long evt, + struct clock_event_device *clk_event_dev); + +static void spear_clocksource_init(void) +{ + u32 tick_rate; + u16 val; + + /* program the prescaler (/256)*/ + writew(CTRL_PRESCALER256, gpt_base + CR(CLKSRC)); + + /* find out actual clock driving Timer */ + tick_rate = clk_get_rate(gpt_clk); + tick_rate >>= CTRL_PRESCALER256; + + writew(0xFFFF, gpt_base + LOAD(CLKSRC)); + + val = readw(gpt_base + CR(CLKSRC)); + val &= ~CTRL_ONE_SHOT; /* autoreload mode */ + val |= CTRL_ENABLE ; + writew(val, gpt_base + CR(CLKSRC)); + + /* register the clocksource */ + clocksource_mmio_init(gpt_base + COUNT(CLKSRC), "tmr1", tick_rate, + 200, 16, clocksource_mmio_readw_up); +} + +static struct clock_event_device clkevt = { + .name = "tmr0", + .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, + .set_mode = clockevent_set_mode, + .set_next_event = clockevent_next_event, + .shift = 0, /* to be computed */ +}; + +static void clockevent_set_mode(enum clock_event_mode mode, + struct clock_event_device *clk_event_dev) +{ + u32 period; + u16 val; + + /* stop the timer */ + val = readw(gpt_base + CR(CLKEVT)); + val &= ~CTRL_ENABLE; + writew(val, gpt_base + CR(CLKEVT)); + + switch (mode) { + case CLOCK_EVT_MODE_PERIODIC: + period = clk_get_rate(gpt_clk) / HZ; + period >>= CTRL_PRESCALER16; + writew(period, gpt_base + LOAD(CLKEVT)); + + val = readw(gpt_base + CR(CLKEVT)); + val &= ~CTRL_ONE_SHOT; + val |= CTRL_ENABLE | CTRL_INT_ENABLE; + writew(val, gpt_base + CR(CLKEVT)); + + break; + case CLOCK_EVT_MODE_ONESHOT: + val = readw(gpt_base + CR(CLKEVT)); + val |= CTRL_ONE_SHOT; + writew(val, gpt_base + CR(CLKEVT)); + + break; + case CLOCK_EVT_MODE_UNUSED: + case CLOCK_EVT_MODE_SHUTDOWN: + case CLOCK_EVT_MODE_RESUME: + + break; + default: + pr_err("Invalid mode requested\n"); + break; + } +} + +static int clockevent_next_event(unsigned long cycles, + struct clock_event_device *clk_event_dev) +{ + u16 val = readw(gpt_base + CR(CLKEVT)); + + if (val & CTRL_ENABLE) + writew(val & ~CTRL_ENABLE, gpt_base + CR(CLKEVT)); + + writew(cycles, gpt_base + LOAD(CLKEVT)); + + val |= CTRL_ENABLE | CTRL_INT_ENABLE; + writew(val, gpt_base + CR(CLKEVT)); + + return 0; +} + +static irqreturn_t spear_timer_interrupt(int irq, void *dev_id) +{ + struct clock_event_device *evt = &clkevt; + + writew(INT_STATUS, gpt_base + IR(CLKEVT)); + + evt->event_handler(evt); + + return IRQ_HANDLED; +} + +static struct irqaction spear_timer_irq = { + .name = "timer", + .flags = IRQF_DISABLED | IRQF_TIMER, + .handler = spear_timer_interrupt +}; + +static void __init spear_clockevent_init(int irq) +{ + u32 tick_rate; + + /* program the prescaler */ + writew(CTRL_PRESCALER16, gpt_base + CR(CLKEVT)); + + tick_rate = clk_get_rate(gpt_clk); + tick_rate >>= CTRL_PRESCALER16; + + clkevt.cpumask = cpumask_of(0); + + clockevents_config_and_register(&clkevt, tick_rate, 3, 0xfff0); + + setup_irq(irq, &spear_timer_irq); +} + +const static struct of_device_id timer_of_match[] __initconst = { + { .compatible = "st,spear-timer", }, + { }, +}; + +void __init spear_setup_of_timer(void) +{ + struct device_node *np; + int irq, ret; + + np = of_find_matching_node(NULL, timer_of_match); + if (!np) { + pr_err("%s: No timer passed via DT\n", __func__); + return; + } + + irq = irq_of_parse_and_map(np, 0); + if (!irq) { + pr_err("%s: No irq passed for timer via DT\n", __func__); + return; + } + + gpt_base = of_iomap(np, 0); + if (!gpt_base) { + pr_err("%s: of iomap failed\n", __func__); + return; + } + + gpt_clk = clk_get_sys("gpt0", NULL); + if (!gpt_clk) { + pr_err("%s:couldn't get clk for gpt\n", __func__); + goto err_iomap; + } + + ret = clk_prepare_enable(gpt_clk); + if (ret < 0) { + pr_err("%s:couldn't prepare-enable gpt clock\n", __func__); + goto err_prepare_enable_clk; + } + + spear_clockevent_init(irq); + spear_clocksource_init(); + + return; + +err_prepare_enable_clk: + clk_put(gpt_clk); +err_iomap: + iounmap(gpt_base); +} diff --git a/arch/arm/mach-spear13xx/Makefile b/arch/arm/mach-spear13xx/Makefile deleted file mode 100644 index 3435ea7..0000000 --- a/arch/arm/mach-spear13xx/Makefile +++ /dev/null @@ -1,10 +0,0 @@ -# -# Makefile for SPEAr13XX machine series -# - -obj-$(CONFIG_SMP) += headsmp.o platsmp.o -obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o - -obj-$(CONFIG_ARCH_SPEAR13XX) += spear13xx.o -obj-$(CONFIG_MACH_SPEAR1310) += spear1310.o -obj-$(CONFIG_MACH_SPEAR1340) += spear1340.o diff --git a/arch/arm/mach-spear13xx/Makefile.boot b/arch/arm/mach-spear13xx/Makefile.boot deleted file mode 100644 index 4674a4c..0000000 --- a/arch/arm/mach-spear13xx/Makefile.boot +++ /dev/null @@ -1,3 +0,0 @@ -zreladdr-y += 0x00008000 -params_phys-y := 0x00000100 -initrd_phys-y := 0x00800000 diff --git a/arch/arm/mach-spear13xx/headsmp.S b/arch/arm/mach-spear13xx/headsmp.S deleted file mode 100644 index ed85473..0000000 --- a/arch/arm/mach-spear13xx/headsmp.S +++ /dev/null @@ -1,47 +0,0 @@ -/* - * arch/arm/mach-spear13XX/headsmp.S - * - * Picked from realview - * Copyright (c) 2012 ST Microelectronics Limited - * Shiraz Hashim - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include -#include - - __INIT - -/* - * spear13xx specific entry point for secondary CPUs. This provides - * a "holding pen" into which all secondary cores are held until we're - * ready for them to initialise. - */ -ENTRY(spear13xx_secondary_startup) - mrc p15, 0, r0, c0, c0, 5 - and r0, r0, #15 - adr r4, 1f - ldmia r4, {r5, r6} - sub r4, r4, r5 - add r6, r6, r4 -pen: ldr r7, [r6] - cmp r7, r0 - bne pen - - /* re-enable coherency */ - mrc p15, 0, r0, c1, c0, 1 - orr r0, r0, #(1 << 6) | (1 << 0) - mcr p15, 0, r0, c1, c0, 1 - /* - * we've been released from the holding pen: secondary_stack - * should now contain the SVC stack for this core - */ - b secondary_startup - - .align -1: .long . - .long pen_release -ENDPROC(spear13xx_secondary_startup) diff --git a/arch/arm/mach-spear13xx/hotplug.c b/arch/arm/mach-spear13xx/hotplug.c deleted file mode 100644 index a7d2dd1..0000000 --- a/arch/arm/mach-spear13xx/hotplug.c +++ /dev/null @@ -1,103 +0,0 @@ -/* - * linux/arch/arm/mach-spear13xx/hotplug.c - * - * Copyright (C) 2012 ST Microelectronics Ltd. - * Deepak Sikri - * - * based upon linux/arch/arm/mach-realview/hotplug.c - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#include -#include -#include -#include -#include -#include - -static inline void cpu_enter_lowpower(void) -{ - unsigned int v; - - flush_cache_all(); - asm volatile( - " mcr p15, 0, %1, c7, c5, 0\n" - " dsb\n" - /* - * Turn off coherency - */ - " mrc p15, 0, %0, c1, c0, 1\n" - " bic %0, %0, #0x20\n" - " mcr p15, 0, %0, c1, c0, 1\n" - " mrc p15, 0, %0, c1, c0, 0\n" - " bic %0, %0, %2\n" - " mcr p15, 0, %0, c1, c0, 0\n" - : "=&r" (v) - : "r" (0), "Ir" (CR_C) - : "cc", "memory"); -} - -static inline void cpu_leave_lowpower(void) -{ - unsigned int v; - - asm volatile("mrc p15, 0, %0, c1, c0, 0\n" - " orr %0, %0, %1\n" - " mcr p15, 0, %0, c1, c0, 0\n" - " mrc p15, 0, %0, c1, c0, 1\n" - " orr %0, %0, #0x20\n" - " mcr p15, 0, %0, c1, c0, 1\n" - : "=&r" (v) - : "Ir" (CR_C) - : "cc"); -} - -static inline void spear13xx_do_lowpower(unsigned int cpu, int *spurious) -{ - for (;;) { - wfi(); - - if (pen_release == cpu) { - /* - * OK, proper wakeup, we're done - */ - break; - } - - /* - * Getting here, means that we have come out of WFI without - * having been woken up - this shouldn't happen - * - * Just note it happening - when we're woken, we can report - * its occurrence. - */ - (*spurious)++; - } -} - -/* - * platform-specific code to shutdown a CPU - * - * Called with IRQs disabled - */ -void __ref spear13xx_cpu_die(unsigned int cpu) -{ - int spurious = 0; - - /* - * we're ready for shutdown now, so do it - */ - cpu_enter_lowpower(); - spear13xx_do_lowpower(cpu, &spurious); - - /* - * bring this CPU back into the world of cache - * coherency, and then restore interrupts - */ - cpu_leave_lowpower(); - - if (spurious) - pr_warn("CPU%u: %u spurious wakeup calls\n", cpu, spurious); -} diff --git a/arch/arm/mach-spear13xx/platsmp.c b/arch/arm/mach-spear13xx/platsmp.c deleted file mode 100644 index af4ade6..0000000 --- a/arch/arm/mach-spear13xx/platsmp.c +++ /dev/null @@ -1,130 +0,0 @@ -/* - * arch/arm/mach-spear13xx/platsmp.c - * - * based upon linux/arch/arm/mach-realview/platsmp.c - * - * Copyright (C) 2012 ST Microelectronics Ltd. - * Shiraz Hashim - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -static DEFINE_SPINLOCK(boot_lock); - -static void __iomem *scu_base = IOMEM(VA_SCU_BASE); - -static void __cpuinit spear13xx_secondary_init(unsigned int cpu) -{ - /* - * if any interrupts are already enabled for the primary - * core (e.g. timer irq), then they will not have been enabled - * for us: do so - */ - gic_secondary_init(0); - - /* - * let the primary processor know we're out of the - * pen, then head off into the C entry point - */ - pen_release = -1; - smp_wmb(); - - /* - * Synchronise with the boot thread. - */ - spin_lock(&boot_lock); - spin_unlock(&boot_lock); -} - -static int __cpuinit spear13xx_boot_secondary(unsigned int cpu, struct task_struct *idle) -{ - unsigned long timeout; - - /* - * set synchronisation state between this boot processor - * and the secondary one - */ - spin_lock(&boot_lock); - - /* - * The secondary processor is waiting to be released from - * the holding pen - release it, then wait for it to flag - * that it has been released by resetting pen_release. - * - * Note that "pen_release" is the hardware CPU ID, whereas - * "cpu" is Linux's internal ID. - */ - pen_release = cpu; - flush_cache_all(); - outer_flush_all(); - - timeout = jiffies + (1 * HZ); - while (time_before(jiffies, timeout)) { - smp_rmb(); - if (pen_release == -1) - break; - - udelay(10); - } - - /* - * now the secondary core is starting up let it run its - * calibrations, then wait for it to finish - */ - spin_unlock(&boot_lock); - - return pen_release != -1 ? -ENOSYS : 0; -} - -/* - * Initialise the CPU possible map early - this describes the CPUs - * which may be present or become present in the system. - */ -static void __init spear13xx_smp_init_cpus(void) -{ - unsigned int i, ncores = scu_get_core_count(scu_base); - - if (ncores > nr_cpu_ids) { - pr_warn("SMP: %u cores greater than maximum (%u), clipping\n", - ncores, nr_cpu_ids); - ncores = nr_cpu_ids; - } - - for (i = 0; i < ncores; i++) - set_cpu_possible(i, true); -} - -static void __init spear13xx_smp_prepare_cpus(unsigned int max_cpus) -{ - - scu_enable(scu_base); - - /* - * Write the address of secondary startup into the system-wide location - * (presently it is in SRAM). The BootMonitor waits until it receives a - * soft interrupt, and then the secondary CPU branches to this address. - */ - __raw_writel(virt_to_phys(spear13xx_secondary_startup), SYS_LOCATION); -} - -struct smp_operations spear13xx_smp_ops __initdata = { - .smp_init_cpus = spear13xx_smp_init_cpus, - .smp_prepare_cpus = spear13xx_smp_prepare_cpus, - .smp_secondary_init = spear13xx_secondary_init, - .smp_boot_secondary = spear13xx_boot_secondary, -#ifdef CONFIG_HOTPLUG_CPU - .cpu_die = spear13xx_cpu_die, -#endif -}; diff --git a/arch/arm/mach-spear13xx/spear1310.c b/arch/arm/mach-spear13xx/spear1310.c deleted file mode 100644 index 56214d1..0000000 --- a/arch/arm/mach-spear13xx/spear1310.c +++ /dev/null @@ -1,98 +0,0 @@ -/* - * arch/arm/mach-spear13xx/spear1310.c - * - * SPEAr1310 machine source file - * - * Copyright (C) 2012 ST Microelectronics - * Viresh Kumar - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#define pr_fmt(fmt) "SPEAr1310: " fmt - -#include -#include -#include -#include -#include -#include -#include -#include - -/* Base addresses */ -#define SPEAR1310_SSP1_BASE UL(0x5D400000) -#define SPEAR1310_SATA0_BASE UL(0xB1000000) -#define SPEAR1310_SATA1_BASE UL(0xB1800000) -#define SPEAR1310_SATA2_BASE UL(0xB4000000) - -#define SPEAR1310_RAS_GRP1_BASE UL(0xD8000000) -#define VA_SPEAR1310_RAS_GRP1_BASE UL(0xFA000000) -#define SPEAR1310_RAS_BASE UL(0xD8400000) -#define VA_SPEAR1310_RAS_BASE IOMEM(UL(0xFA400000)) - -static struct arasan_cf_pdata cf_pdata = { - .cf_if_clk = CF_IF_CLK_166M, - .quirk = CF_BROKEN_UDMA, - .dma_priv = &cf_dma_priv, -}; - -/* ssp device registration */ -static struct pl022_ssp_controller ssp1_plat_data = { - .enable_dma = 0, -}; - -/* Add SPEAr1310 auxdata to pass platform data */ -static struct of_dev_auxdata spear1310_auxdata_lookup[] __initdata = { - OF_DEV_AUXDATA("arasan,cf-spear1340", MCIF_CF_BASE, NULL, &cf_pdata), - OF_DEV_AUXDATA("snps,dma-spear1340", DMAC0_BASE, NULL, &dmac_plat_data), - OF_DEV_AUXDATA("snps,dma-spear1340", DMAC1_BASE, NULL, &dmac_plat_data), - OF_DEV_AUXDATA("arm,pl022", SSP_BASE, NULL, &pl022_plat_data), - - OF_DEV_AUXDATA("arm,pl022", SPEAR1310_SSP1_BASE, NULL, &ssp1_plat_data), - {} -}; - -static void __init spear1310_dt_init(void) -{ - of_platform_populate(NULL, of_default_bus_match_table, - spear1310_auxdata_lookup, NULL); -} - -static const char * const spear1310_dt_board_compat[] = { - "st,spear1310", - "st,spear1310-evb", - NULL, -}; - -/* - * Following will create 16MB static virtual/physical mappings - * PHYSICAL VIRTUAL - * 0xD8000000 0xFA000000 - */ -struct map_desc spear1310_io_desc[] __initdata = { - { - .virtual = VA_SPEAR1310_RAS_GRP1_BASE, - .pfn = __phys_to_pfn(SPEAR1310_RAS_GRP1_BASE), - .length = SZ_16M, - .type = MT_DEVICE - }, -}; - -static void __init spear1310_map_io(void) -{ - iotable_init(spear1310_io_desc, ARRAY_SIZE(spear1310_io_desc)); - spear13xx_map_io(); -} - -DT_MACHINE_START(SPEAR1310_DT, "ST SPEAr1310 SoC with Flattened Device Tree") - .smp = smp_ops(spear13xx_smp_ops), - .map_io = spear1310_map_io, - .init_irq = irqchip_init, - .init_time = spear13xx_timer_init, - .init_machine = spear1310_dt_init, - .restart = spear_restart, - .dt_compat = spear1310_dt_board_compat, -MACHINE_END diff --git a/arch/arm/mach-spear13xx/spear1340.c b/arch/arm/mach-spear13xx/spear1340.c deleted file mode 100644 index b01c4c7..0000000 --- a/arch/arm/mach-spear13xx/spear1340.c +++ /dev/null @@ -1,193 +0,0 @@ -/* - * arch/arm/mach-spear13xx/spear1340.c - * - * SPEAr1340 machine source file - * - * Copyright (C) 2012 ST Microelectronics - * Viresh Kumar - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#define pr_fmt(fmt) "SPEAr1340: " fmt - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "spear13xx-dma.h" - -/* Base addresses */ -#define SPEAR1340_SATA_BASE UL(0xB1000000) -#define SPEAR1340_UART1_BASE UL(0xB4100000) - -/* Power Management Registers */ -#define SPEAR1340_PCM_CFG (VA_MISC_BASE + 0x100) -#define SPEAR1340_PCM_WKUP_CFG (VA_MISC_BASE + 0x104) -#define SPEAR1340_SWITCH_CTR (VA_MISC_BASE + 0x108) - -#define SPEAR1340_PERIP1_SW_RST (VA_MISC_BASE + 0x318) -#define SPEAR1340_PERIP2_SW_RST (VA_MISC_BASE + 0x31C) -#define SPEAR1340_PERIP3_SW_RST (VA_MISC_BASE + 0x320) - -/* PCIE - SATA configuration registers */ -#define SPEAR1340_PCIE_SATA_CFG (VA_MISC_BASE + 0x424) - /* PCIE CFG MASks */ - #define SPEAR1340_PCIE_CFG_DEVICE_PRESENT (1 << 11) - #define SPEAR1340_PCIE_CFG_POWERUP_RESET (1 << 10) - #define SPEAR1340_PCIE_CFG_CORE_CLK_EN (1 << 9) - #define SPEAR1340_PCIE_CFG_AUX_CLK_EN (1 << 8) - #define SPEAR1340_SATA_CFG_TX_CLK_EN (1 << 4) - #define SPEAR1340_SATA_CFG_RX_CLK_EN (1 << 3) - #define SPEAR1340_SATA_CFG_POWERUP_RESET (1 << 2) - #define SPEAR1340_SATA_CFG_PM_CLK_EN (1 << 1) - #define SPEAR1340_PCIE_SATA_SEL_PCIE (0) - #define SPEAR1340_PCIE_SATA_SEL_SATA (1) - #define SPEAR1340_SATA_PCIE_CFG_MASK 0xF1F - #define SPEAR1340_PCIE_CFG_VAL (SPEAR1340_PCIE_SATA_SEL_PCIE | \ - SPEAR1340_PCIE_CFG_AUX_CLK_EN | \ - SPEAR1340_PCIE_CFG_CORE_CLK_EN | \ - SPEAR1340_PCIE_CFG_POWERUP_RESET | \ - SPEAR1340_PCIE_CFG_DEVICE_PRESENT) - #define SPEAR1340_SATA_CFG_VAL (SPEAR1340_PCIE_SATA_SEL_SATA | \ - SPEAR1340_SATA_CFG_PM_CLK_EN | \ - SPEAR1340_SATA_CFG_POWERUP_RESET | \ - SPEAR1340_SATA_CFG_RX_CLK_EN | \ - SPEAR1340_SATA_CFG_TX_CLK_EN) - -#define SPEAR1340_PCIE_MIPHY_CFG (VA_MISC_BASE + 0x428) - #define SPEAR1340_MIPHY_OSC_BYPASS_EXT (1 << 31) - #define SPEAR1340_MIPHY_CLK_REF_DIV2 (1 << 27) - #define SPEAR1340_MIPHY_CLK_REF_DIV4 (2 << 27) - #define SPEAR1340_MIPHY_CLK_REF_DIV8 (3 << 27) - #define SPEAR1340_MIPHY_PLL_RATIO_TOP(x) (x << 0) - #define SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA \ - (SPEAR1340_MIPHY_OSC_BYPASS_EXT | \ - SPEAR1340_MIPHY_CLK_REF_DIV2 | \ - SPEAR1340_MIPHY_PLL_RATIO_TOP(60)) - #define SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA_25M_CRYSTAL_CLK \ - (SPEAR1340_MIPHY_PLL_RATIO_TOP(120)) - #define SPEAR1340_PCIE_SATA_MIPHY_CFG_PCIE \ - (SPEAR1340_MIPHY_OSC_BYPASS_EXT | \ - SPEAR1340_MIPHY_PLL_RATIO_TOP(25)) - -static struct dw_dma_slave uart1_dma_param[] = { - { - /* Tx */ - .cfg_hi = DWC_CFGH_DST_PER(SPEAR1340_DMA_REQ_UART1_TX), - .cfg_lo = 0, - .src_master = DMA_MASTER_MEMORY, - .dst_master = SPEAR1340_DMA_MASTER_UART1, - }, { - /* Rx */ - .cfg_hi = DWC_CFGH_SRC_PER(SPEAR1340_DMA_REQ_UART1_RX), - .cfg_lo = 0, - .src_master = SPEAR1340_DMA_MASTER_UART1, - .dst_master = DMA_MASTER_MEMORY, - } -}; - -static struct amba_pl011_data uart1_data = { - .dma_filter = dw_dma_filter, - .dma_tx_param = &uart1_dma_param[0], - .dma_rx_param = &uart1_dma_param[1], -}; - -/* SATA device registration */ -static int sata_miphy_init(struct device *dev, void __iomem *addr) -{ - writel(SPEAR1340_SATA_CFG_VAL, SPEAR1340_PCIE_SATA_CFG); - writel(SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA_25M_CRYSTAL_CLK, - SPEAR1340_PCIE_MIPHY_CFG); - /* Switch on sata power domain */ - writel((readl(SPEAR1340_PCM_CFG) | (0x800)), SPEAR1340_PCM_CFG); - msleep(20); - /* Disable PCIE SATA Controller reset */ - writel((readl(SPEAR1340_PERIP1_SW_RST) & (~0x1000)), - SPEAR1340_PERIP1_SW_RST); - msleep(20); - - return 0; -} - -void sata_miphy_exit(struct device *dev) -{ - writel(0, SPEAR1340_PCIE_SATA_CFG); - writel(0, SPEAR1340_PCIE_MIPHY_CFG); - - /* Enable PCIE SATA Controller reset */ - writel((readl(SPEAR1340_PERIP1_SW_RST) | (0x1000)), - SPEAR1340_PERIP1_SW_RST); - msleep(20); - /* Switch off sata power domain */ - writel((readl(SPEAR1340_PCM_CFG) & (~0x800)), SPEAR1340_PCM_CFG); - msleep(20); -} - -int sata_suspend(struct device *dev) -{ - if (dev->power.power_state.event == PM_EVENT_FREEZE) - return 0; - - sata_miphy_exit(dev); - - return 0; -} - -int sata_resume(struct device *dev) -{ - if (dev->power.power_state.event == PM_EVENT_THAW) - return 0; - - return sata_miphy_init(dev, NULL); -} - -static struct ahci_platform_data sata_pdata = { - .init = sata_miphy_init, - .exit = sata_miphy_exit, - .suspend = sata_suspend, - .resume = sata_resume, -}; - -/* Add SPEAr1340 auxdata to pass platform data */ -static struct of_dev_auxdata spear1340_auxdata_lookup[] __initdata = { - OF_DEV_AUXDATA("arasan,cf-spear1340", MCIF_CF_BASE, NULL, &cf_dma_priv), - OF_DEV_AUXDATA("snps,dma-spear1340", DMAC0_BASE, NULL, &dmac_plat_data), - OF_DEV_AUXDATA("snps,dma-spear1340", DMAC1_BASE, NULL, &dmac_plat_data), - OF_DEV_AUXDATA("arm,pl022", SSP_BASE, NULL, &pl022_plat_data), - - OF_DEV_AUXDATA("snps,spear-ahci", SPEAR1340_SATA_BASE, NULL, - &sata_pdata), - OF_DEV_AUXDATA("arm,pl011", SPEAR1340_UART1_BASE, NULL, &uart1_data), - {} -}; - -static void __init spear1340_dt_init(void) -{ - of_platform_populate(NULL, of_default_bus_match_table, - spear1340_auxdata_lookup, NULL); -} - -static const char * const spear1340_dt_board_compat[] = { - "st,spear1340", - "st,spear1340-evb", - NULL, -}; - -DT_MACHINE_START(SPEAR1340_DT, "ST SPEAr1340 SoC with Flattened Device Tree") - .smp = smp_ops(spear13xx_smp_ops), - .map_io = spear13xx_map_io, - .init_irq = irqchip_init, - .init_time = spear13xx_timer_init, - .init_machine = spear1340_dt_init, - .restart = spear_restart, - .dt_compat = spear1340_dt_board_compat, -MACHINE_END diff --git a/arch/arm/mach-spear13xx/spear13xx-dma.h b/arch/arm/mach-spear13xx/spear13xx-dma.h deleted file mode 100644 index d50bdb6..0000000 --- a/arch/arm/mach-spear13xx/spear13xx-dma.h +++ /dev/null @@ -1,128 +0,0 @@ -/* - * arch/arm/mach-spear13xx/include/mach/dma.h - * - * DMA information for SPEAr13xx machine family - * - * Copyright (C) 2012 ST Microelectronics - * Viresh Kumar - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#ifndef __MACH_DMA_H -#define __MACH_DMA_H - -/* request id of all the peripherals */ -enum dma_master_info { - /* Accessible from only one master */ - DMA_MASTER_MCIF = 0, - DMA_MASTER_FSMC = 1, - /* Accessible from both 0 & 1 */ - DMA_MASTER_MEMORY = 0, - DMA_MASTER_ADC = 0, - DMA_MASTER_UART0 = 0, - DMA_MASTER_SSP0 = 0, - DMA_MASTER_I2C0 = 0, - -#ifdef CONFIG_MACH_SPEAR1310 - /* Accessible from only one master */ - SPEAR1310_DMA_MASTER_JPEG = 1, - - /* Accessible from both 0 & 1 */ - SPEAR1310_DMA_MASTER_I2S = 0, - SPEAR1310_DMA_MASTER_UART1 = 0, - SPEAR1310_DMA_MASTER_UART2 = 0, - SPEAR1310_DMA_MASTER_UART3 = 0, - SPEAR1310_DMA_MASTER_UART4 = 0, - SPEAR1310_DMA_MASTER_UART5 = 0, - SPEAR1310_DMA_MASTER_I2C1 = 0, - SPEAR1310_DMA_MASTER_I2C2 = 0, - SPEAR1310_DMA_MASTER_I2C3 = 0, - SPEAR1310_DMA_MASTER_I2C4 = 0, - SPEAR1310_DMA_MASTER_I2C5 = 0, - SPEAR1310_DMA_MASTER_I2C6 = 0, - SPEAR1310_DMA_MASTER_I2C7 = 0, - SPEAR1310_DMA_MASTER_SSP1 = 0, -#endif - -#ifdef CONFIG_MACH_SPEAR1340 - /* Accessible from only one master */ - SPEAR1340_DMA_MASTER_I2S_PLAY = 1, - SPEAR1340_DMA_MASTER_I2S_REC = 1, - SPEAR1340_DMA_MASTER_I2C1 = 1, - SPEAR1340_DMA_MASTER_UART1 = 1, - - /* following are accessible from both master 0 & 1 */ - SPEAR1340_DMA_MASTER_SPDIF = 0, - SPEAR1340_DMA_MASTER_CAM = 1, - SPEAR1340_DMA_MASTER_VIDEO_IN = 0, - SPEAR1340_DMA_MASTER_MALI = 0, -#endif -}; - -enum request_id { - DMA_REQ_ADC = 0, - DMA_REQ_SSP0_TX = 4, - DMA_REQ_SSP0_RX = 5, - DMA_REQ_UART0_TX = 6, - DMA_REQ_UART0_RX = 7, - DMA_REQ_I2C0_TX = 8, - DMA_REQ_I2C0_RX = 9, - -#ifdef CONFIG_MACH_SPEAR1310 - SPEAR1310_DMA_REQ_FROM_JPEG = 2, - SPEAR1310_DMA_REQ_TO_JPEG = 3, - SPEAR1310_DMA_REQ_I2S_TX = 10, - SPEAR1310_DMA_REQ_I2S_RX = 11, - - SPEAR1310_DMA_REQ_I2C1_RX = 0, - SPEAR1310_DMA_REQ_I2C1_TX = 1, - SPEAR1310_DMA_REQ_I2C2_RX = 2, - SPEAR1310_DMA_REQ_I2C2_TX = 3, - SPEAR1310_DMA_REQ_I2C3_RX = 4, - SPEAR1310_DMA_REQ_I2C3_TX = 5, - SPEAR1310_DMA_REQ_I2C4_RX = 6, - SPEAR1310_DMA_REQ_I2C4_TX = 7, - SPEAR1310_DMA_REQ_I2C5_RX = 8, - SPEAR1310_DMA_REQ_I2C5_TX = 9, - SPEAR1310_DMA_REQ_I2C6_RX = 10, - SPEAR1310_DMA_REQ_I2C6_TX = 11, - SPEAR1310_DMA_REQ_UART1_RX = 12, - SPEAR1310_DMA_REQ_UART1_TX = 13, - SPEAR1310_DMA_REQ_UART2_RX = 14, - SPEAR1310_DMA_REQ_UART2_TX = 15, - SPEAR1310_DMA_REQ_UART5_RX = 16, - SPEAR1310_DMA_REQ_UART5_TX = 17, - SPEAR1310_DMA_REQ_SSP1_RX = 18, - SPEAR1310_DMA_REQ_SSP1_TX = 19, - SPEAR1310_DMA_REQ_I2C7_RX = 20, - SPEAR1310_DMA_REQ_I2C7_TX = 21, - SPEAR1310_DMA_REQ_UART3_RX = 28, - SPEAR1310_DMA_REQ_UART3_TX = 29, - SPEAR1310_DMA_REQ_UART4_RX = 30, - SPEAR1310_DMA_REQ_UART4_TX = 31, -#endif - -#ifdef CONFIG_MACH_SPEAR1340 - SPEAR1340_DMA_REQ_SPDIF_TX = 2, - SPEAR1340_DMA_REQ_SPDIF_RX = 3, - SPEAR1340_DMA_REQ_I2S_TX = 10, - SPEAR1340_DMA_REQ_I2S_RX = 11, - SPEAR1340_DMA_REQ_UART1_TX = 12, - SPEAR1340_DMA_REQ_UART1_RX = 13, - SPEAR1340_DMA_REQ_I2C1_TX = 14, - SPEAR1340_DMA_REQ_I2C1_RX = 15, - SPEAR1340_DMA_REQ_CAM0_EVEN = 0, - SPEAR1340_DMA_REQ_CAM0_ODD = 1, - SPEAR1340_DMA_REQ_CAM1_EVEN = 2, - SPEAR1340_DMA_REQ_CAM1_ODD = 3, - SPEAR1340_DMA_REQ_CAM2_EVEN = 4, - SPEAR1340_DMA_REQ_CAM2_ODD = 5, - SPEAR1340_DMA_REQ_CAM3_EVEN = 6, - SPEAR1340_DMA_REQ_CAM3_ODD = 7, -#endif -}; - -#endif /* __MACH_DMA_H */ diff --git a/arch/arm/mach-spear13xx/spear13xx.c b/arch/arm/mach-spear13xx/spear13xx.c deleted file mode 100644 index 988fefe..0000000 --- a/arch/arm/mach-spear13xx/spear13xx.c +++ /dev/null @@ -1,184 +0,0 @@ -/* - * arch/arm/mach-spear13xx/spear13xx.c - * - * SPEAr13XX machines common source file - * - * Copyright (C) 2012 ST Microelectronics - * Viresh Kumar - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#define pr_fmt(fmt) "SPEAr13xx: " fmt - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "spear13xx-dma.h" - -/* common dw_dma filter routine to be used by peripherals */ -bool dw_dma_filter(struct dma_chan *chan, void *slave) -{ - struct dw_dma_slave *dws = (struct dw_dma_slave *)slave; - - if (chan->device->dev == dws->dma_dev) { - chan->private = slave; - return true; - } else { - return false; - } -} - -/* ssp device registration */ -static struct dw_dma_slave ssp_dma_param[] = { - { - /* Tx */ - .cfg_hi = DWC_CFGH_DST_PER(DMA_REQ_SSP0_TX), - .cfg_lo = 0, - .src_master = DMA_MASTER_MEMORY, - .dst_master = DMA_MASTER_SSP0, - }, { - /* Rx */ - .cfg_hi = DWC_CFGH_SRC_PER(DMA_REQ_SSP0_RX), - .cfg_lo = 0, - .src_master = DMA_MASTER_SSP0, - .dst_master = DMA_MASTER_MEMORY, - } -}; - -struct pl022_ssp_controller pl022_plat_data = { - .enable_dma = 1, - .dma_filter = dw_dma_filter, - .dma_rx_param = &ssp_dma_param[1], - .dma_tx_param = &ssp_dma_param[0], -}; - -/* CF device registration */ -struct dw_dma_slave cf_dma_priv = { - .cfg_hi = 0, - .cfg_lo = 0, - .src_master = 0, - .dst_master = 0, -}; - -/* dmac device registeration */ -struct dw_dma_platform_data dmac_plat_data = { - .nr_channels = 8, - .chan_allocation_order = CHAN_ALLOCATION_DESCENDING, - .chan_priority = CHAN_PRIORITY_DESCENDING, - .block_size = 4095U, - .nr_masters = 2, - .data_width = { 3, 3, 0, 0 }, -}; - -void __init spear13xx_l2x0_init(void) -{ - /* - * 512KB (64KB/way), 8-way associativity, parity supported - * - * FIXME: 9th bit, of Auxillary Controller register must be set - * for some spear13xx devices for stable L2 operation. - * - * Enable Early BRESP, L2 prefetch for Instruction and Data, - * write alloc and 'Full line of zero' options - * - */ - - writel_relaxed(0x06, VA_L2CC_BASE + L2X0_PREFETCH_CTRL); - - /* - * Program following latencies in order to make - * SPEAr1340 work at 600 MHz - */ - writel_relaxed(0x221, VA_L2CC_BASE + L2X0_TAG_LATENCY_CTRL); - writel_relaxed(0x441, VA_L2CC_BASE + L2X0_DATA_LATENCY_CTRL); - l2x0_init(VA_L2CC_BASE, 0x70A60001, 0xfe00ffff); -} - -/* - * Following will create 16MB static virtual/physical mappings - * PHYSICAL VIRTUAL - * 0xB3000000 0xFE000000 - * 0xE0000000 0xFD000000 - * 0xEC000000 0xFC000000 - * 0xED000000 0xFB000000 - */ -struct map_desc spear13xx_io_desc[] __initdata = { - { - .virtual = (unsigned long)VA_PERIP_GRP2_BASE, - .pfn = __phys_to_pfn(PERIP_GRP2_BASE), - .length = SZ_16M, - .type = MT_DEVICE - }, { - .virtual = (unsigned long)VA_PERIP_GRP1_BASE, - .pfn = __phys_to_pfn(PERIP_GRP1_BASE), - .length = SZ_16M, - .type = MT_DEVICE - }, { - .virtual = (unsigned long)VA_A9SM_AND_MPMC_BASE, - .pfn = __phys_to_pfn(A9SM_AND_MPMC_BASE), - .length = SZ_16M, - .type = MT_DEVICE - }, { - .virtual = (unsigned long)VA_L2CC_BASE, - .pfn = __phys_to_pfn(L2CC_BASE), - .length = SZ_4K, - .type = MT_DEVICE - }, -}; - -/* This will create static memory mapping for selected devices */ -void __init spear13xx_map_io(void) -{ - iotable_init(spear13xx_io_desc, ARRAY_SIZE(spear13xx_io_desc)); -} - -static void __init spear13xx_clk_init(void) -{ - if (of_machine_is_compatible("st,spear1310")) - spear1310_clk_init(); - else if (of_machine_is_compatible("st,spear1340")) - spear1340_clk_init(); - else - pr_err("%s: Unknown machine\n", __func__); -} - -void __init spear13xx_timer_init(void) -{ - char pclk_name[] = "osc_24m_clk"; - struct clk *gpt_clk, *pclk; - - spear13xx_clk_init(); - - /* get the system timer clock */ - gpt_clk = clk_get_sys("gpt0", NULL); - if (IS_ERR(gpt_clk)) { - pr_err("%s:couldn't get clk for gpt\n", __func__); - BUG(); - } - - /* get the suitable parent clock for timer*/ - pclk = clk_get(NULL, pclk_name); - if (IS_ERR(pclk)) { - pr_err("%s:couldn't get %s as parent for gpt\n", __func__, - pclk_name); - BUG(); - } - - clk_set_parent(gpt_clk, pclk); - clk_put(gpt_clk); - clk_put(pclk); - - spear_setup_of_timer(); - twd_local_timer_of_register(); -} diff --git a/arch/arm/mach-spear3xx/Makefile b/arch/arm/mach-spear3xx/Makefile deleted file mode 100644 index 8d12faa..0000000 --- a/arch/arm/mach-spear3xx/Makefile +++ /dev/null @@ -1,15 +0,0 @@ -# -# Makefile for SPEAr3XX machine series -# - -# common files -obj-$(CONFIG_ARCH_SPEAR3XX) += spear3xx.o - -# spear300 specific files -obj-$(CONFIG_MACH_SPEAR300) += spear300.o - -# spear310 specific files -obj-$(CONFIG_MACH_SPEAR310) += spear310.o - -# spear320 specific files -obj-$(CONFIG_MACH_SPEAR320) += spear320.o diff --git a/arch/arm/mach-spear3xx/Makefile.boot b/arch/arm/mach-spear3xx/Makefile.boot deleted file mode 100644 index 4674a4c..0000000 --- a/arch/arm/mach-spear3xx/Makefile.boot +++ /dev/null @@ -1,3 +0,0 @@ -zreladdr-y += 0x00008000 -params_phys-y := 0x00000100 -initrd_phys-y := 0x00800000 diff --git a/arch/arm/mach-spear3xx/spear300.c b/arch/arm/mach-spear3xx/spear300.c deleted file mode 100644 index 72449ee..0000000 --- a/arch/arm/mach-spear3xx/spear300.c +++ /dev/null @@ -1,220 +0,0 @@ -/* - * arch/arm/mach-spear3xx/spear300.c - * - * SPEAr300 machine source file - * - * Copyright (C) 2009-2012 ST Microelectronics - * Viresh Kumar - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#define pr_fmt(fmt) "SPEAr300: " fmt - -#include -#include -#include -#include -#include -#include - -/* DMAC platform data's slave info */ -struct pl08x_channel_data spear300_dma_info[] = { - { - .bus_id = "uart0_rx", - .min_signal = 2, - .max_signal = 2, - .muxval = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "uart0_tx", - .min_signal = 3, - .max_signal = 3, - .muxval = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "ssp0_rx", - .min_signal = 8, - .max_signal = 8, - .muxval = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "ssp0_tx", - .min_signal = 9, - .max_signal = 9, - .muxval = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "i2c_rx", - .min_signal = 10, - .max_signal = 10, - .muxval = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "i2c_tx", - .min_signal = 11, - .max_signal = 11, - .muxval = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "irda", - .min_signal = 12, - .max_signal = 12, - .muxval = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "adc", - .min_signal = 13, - .max_signal = 13, - .muxval = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "to_jpeg", - .min_signal = 14, - .max_signal = 14, - .muxval = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "from_jpeg", - .min_signal = 15, - .max_signal = 15, - .muxval = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "ras0_rx", - .min_signal = 0, - .max_signal = 0, - .muxval = 1, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "ras0_tx", - .min_signal = 1, - .max_signal = 1, - .muxval = 1, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "ras1_rx", - .min_signal = 2, - .max_signal = 2, - .muxval = 1, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "ras1_tx", - .min_signal = 3, - .max_signal = 3, - .muxval = 1, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "ras2_rx", - .min_signal = 4, - .max_signal = 4, - .muxval = 1, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "ras2_tx", - .min_signal = 5, - .max_signal = 5, - .muxval = 1, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "ras3_rx", - .min_signal = 6, - .max_signal = 6, - .muxval = 1, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "ras3_tx", - .min_signal = 7, - .max_signal = 7, - .muxval = 1, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "ras4_rx", - .min_signal = 8, - .max_signal = 8, - .muxval = 1, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "ras4_tx", - .min_signal = 9, - .max_signal = 9, - .muxval = 1, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "ras5_rx", - .min_signal = 10, - .max_signal = 10, - .muxval = 1, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "ras5_tx", - .min_signal = 11, - .max_signal = 11, - .muxval = 1, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "ras6_rx", - .min_signal = 12, - .max_signal = 12, - .muxval = 1, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "ras6_tx", - .min_signal = 13, - .max_signal = 13, - .muxval = 1, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "ras7_rx", - .min_signal = 14, - .max_signal = 14, - .muxval = 1, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "ras7_tx", - .min_signal = 15, - .max_signal = 15, - .muxval = 1, - .periph_buses = PL08X_AHB1, - }, -}; - -/* Add SPEAr300 auxdata to pass platform data */ -static struct of_dev_auxdata spear300_auxdata_lookup[] __initdata = { - OF_DEV_AUXDATA("arm,pl022", SPEAR3XX_ICM1_SSP_BASE, NULL, - &pl022_plat_data), - OF_DEV_AUXDATA("arm,pl080", SPEAR_ICM3_DMA_BASE, NULL, - &pl080_plat_data), - {} -}; - -static void __init spear300_dt_init(void) -{ - pl080_plat_data.slave_channels = spear300_dma_info; - pl080_plat_data.num_slave_channels = ARRAY_SIZE(spear300_dma_info); - - of_platform_populate(NULL, of_default_bus_match_table, - spear300_auxdata_lookup, NULL); -} - -static const char * const spear300_dt_board_compat[] = { - "st,spear300", - "st,spear300-evb", - NULL, -}; - -static void __init spear300_map_io(void) -{ - spear3xx_map_io(); -} - -DT_MACHINE_START(SPEAR300_DT, "ST SPEAr300 SoC with Flattened Device Tree") - .map_io = spear300_map_io, - .init_irq = irqchip_init, - .init_time = spear3xx_timer_init, - .init_machine = spear300_dt_init, - .restart = spear_restart, - .dt_compat = spear300_dt_board_compat, -MACHINE_END diff --git a/arch/arm/mach-spear3xx/spear310.c b/arch/arm/mach-spear3xx/spear310.c deleted file mode 100644 index 0b7962d..0000000 --- a/arch/arm/mach-spear3xx/spear310.c +++ /dev/null @@ -1,262 +0,0 @@ -/* - * arch/arm/mach-spear3xx/spear310.c - * - * SPEAr310 machine source file - * - * Copyright (C) 2009-2012 ST Microelectronics - * Viresh Kumar - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#define pr_fmt(fmt) "SPEAr310: " fmt - -#include -#include -#include -#include -#include -#include -#include - -#define SPEAR310_UART1_BASE UL(0xB2000000) -#define SPEAR310_UART2_BASE UL(0xB2080000) -#define SPEAR310_UART3_BASE UL(0xB2100000) -#define SPEAR310_UART4_BASE UL(0xB2180000) -#define SPEAR310_UART5_BASE UL(0xB2200000) - -/* DMAC platform data's slave info */ -struct pl08x_channel_data spear310_dma_info[] = { - { - .bus_id = "uart0_rx", - .min_signal = 2, - .max_signal = 2, - .muxval = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "uart0_tx", - .min_signal = 3, - .max_signal = 3, - .muxval = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "ssp0_rx", - .min_signal = 8, - .max_signal = 8, - .muxval = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "ssp0_tx", - .min_signal = 9, - .max_signal = 9, - .muxval = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "i2c_rx", - .min_signal = 10, - .max_signal = 10, - .muxval = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "i2c_tx", - .min_signal = 11, - .max_signal = 11, - .muxval = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "irda", - .min_signal = 12, - .max_signal = 12, - .muxval = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "adc", - .min_signal = 13, - .max_signal = 13, - .muxval = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "to_jpeg", - .min_signal = 14, - .max_signal = 14, - .muxval = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "from_jpeg", - .min_signal = 15, - .max_signal = 15, - .muxval = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "uart1_rx", - .min_signal = 0, - .max_signal = 0, - .muxval = 1, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "uart1_tx", - .min_signal = 1, - .max_signal = 1, - .muxval = 1, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "uart2_rx", - .min_signal = 2, - .max_signal = 2, - .muxval = 1, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "uart2_tx", - .min_signal = 3, - .max_signal = 3, - .muxval = 1, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "uart3_rx", - .min_signal = 4, - .max_signal = 4, - .muxval = 1, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "uart3_tx", - .min_signal = 5, - .max_signal = 5, - .muxval = 1, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "uart4_rx", - .min_signal = 6, - .max_signal = 6, - .muxval = 1, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "uart4_tx", - .min_signal = 7, - .max_signal = 7, - .muxval = 1, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "uart5_rx", - .min_signal = 8, - .max_signal = 8, - .muxval = 1, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "uart5_tx", - .min_signal = 9, - .max_signal = 9, - .muxval = 1, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "ras5_rx", - .min_signal = 10, - .max_signal = 10, - .muxval = 1, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "ras5_tx", - .min_signal = 11, - .max_signal = 11, - .muxval = 1, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "ras6_rx", - .min_signal = 12, - .max_signal = 12, - .muxval = 1, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "ras6_tx", - .min_signal = 13, - .max_signal = 13, - .muxval = 1, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "ras7_rx", - .min_signal = 14, - .max_signal = 14, - .muxval = 1, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "ras7_tx", - .min_signal = 15, - .max_signal = 15, - .muxval = 1, - .periph_buses = PL08X_AHB1, - }, -}; - -/* uart devices plat data */ -static struct amba_pl011_data spear310_uart_data[] = { - { - .dma_filter = pl08x_filter_id, - .dma_tx_param = "uart1_tx", - .dma_rx_param = "uart1_rx", - }, { - .dma_filter = pl08x_filter_id, - .dma_tx_param = "uart2_tx", - .dma_rx_param = "uart2_rx", - }, { - .dma_filter = pl08x_filter_id, - .dma_tx_param = "uart3_tx", - .dma_rx_param = "uart3_rx", - }, { - .dma_filter = pl08x_filter_id, - .dma_tx_param = "uart4_tx", - .dma_rx_param = "uart4_rx", - }, { - .dma_filter = pl08x_filter_id, - .dma_tx_param = "uart5_tx", - .dma_rx_param = "uart5_rx", - }, -}; - -/* Add SPEAr310 auxdata to pass platform data */ -static struct of_dev_auxdata spear310_auxdata_lookup[] __initdata = { - OF_DEV_AUXDATA("arm,pl022", SPEAR3XX_ICM1_SSP_BASE, NULL, - &pl022_plat_data), - OF_DEV_AUXDATA("arm,pl080", SPEAR_ICM3_DMA_BASE, NULL, - &pl080_plat_data), - OF_DEV_AUXDATA("arm,pl011", SPEAR310_UART1_BASE, NULL, - &spear310_uart_data[0]), - OF_DEV_AUXDATA("arm,pl011", SPEAR310_UART2_BASE, NULL, - &spear310_uart_data[1]), - OF_DEV_AUXDATA("arm,pl011", SPEAR310_UART3_BASE, NULL, - &spear310_uart_data[2]), - OF_DEV_AUXDATA("arm,pl011", SPEAR310_UART4_BASE, NULL, - &spear310_uart_data[3]), - OF_DEV_AUXDATA("arm,pl011", SPEAR310_UART5_BASE, NULL, - &spear310_uart_data[4]), - {} -}; - -static void __init spear310_dt_init(void) -{ - pl080_plat_data.slave_channels = spear310_dma_info; - pl080_plat_data.num_slave_channels = ARRAY_SIZE(spear310_dma_info); - - of_platform_populate(NULL, of_default_bus_match_table, - spear310_auxdata_lookup, NULL); -} - -static const char * const spear310_dt_board_compat[] = { - "st,spear310", - "st,spear310-evb", - NULL, -}; - -static void __init spear310_map_io(void) -{ - spear3xx_map_io(); -} - -DT_MACHINE_START(SPEAR310_DT, "ST SPEAr310 SoC with Flattened Device Tree") - .map_io = spear310_map_io, - .init_irq = irqchip_init, - .init_time = spear3xx_timer_init, - .init_machine = spear310_dt_init, - .restart = spear_restart, - .dt_compat = spear310_dt_board_compat, -MACHINE_END diff --git a/arch/arm/mach-spear3xx/spear320.c b/arch/arm/mach-spear3xx/spear320.c deleted file mode 100644 index e9db7db..0000000 --- a/arch/arm/mach-spear3xx/spear320.c +++ /dev/null @@ -1,277 +0,0 @@ -/* - * arch/arm/mach-spear3xx/spear320.c - * - * SPEAr320 machine source file - * - * Copyright (C) 2009-2012 ST Microelectronics - * Viresh Kumar - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#define pr_fmt(fmt) "SPEAr320: " fmt - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#define SPEAR320_UART1_BASE UL(0xA3000000) -#define SPEAR320_UART2_BASE UL(0xA4000000) -#define SPEAR320_SSP0_BASE UL(0xA5000000) -#define SPEAR320_SSP1_BASE UL(0xA6000000) - -/* DMAC platform data's slave info */ -struct pl08x_channel_data spear320_dma_info[] = { - { - .bus_id = "uart0_rx", - .min_signal = 2, - .max_signal = 2, - .muxval = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "uart0_tx", - .min_signal = 3, - .max_signal = 3, - .muxval = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "ssp0_rx", - .min_signal = 8, - .max_signal = 8, - .muxval = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "ssp0_tx", - .min_signal = 9, - .max_signal = 9, - .muxval = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "i2c0_rx", - .min_signal = 10, - .max_signal = 10, - .muxval = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "i2c0_tx", - .min_signal = 11, - .max_signal = 11, - .muxval = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "irda", - .min_signal = 12, - .max_signal = 12, - .muxval = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "adc", - .min_signal = 13, - .max_signal = 13, - .muxval = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "to_jpeg", - .min_signal = 14, - .max_signal = 14, - .muxval = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "from_jpeg", - .min_signal = 15, - .max_signal = 15, - .muxval = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "ssp1_rx", - .min_signal = 0, - .max_signal = 0, - .muxval = 1, - .periph_buses = PL08X_AHB2, - }, { - .bus_id = "ssp1_tx", - .min_signal = 1, - .max_signal = 1, - .muxval = 1, - .periph_buses = PL08X_AHB2, - }, { - .bus_id = "ssp2_rx", - .min_signal = 2, - .max_signal = 2, - .muxval = 1, - .periph_buses = PL08X_AHB2, - }, { - .bus_id = "ssp2_tx", - .min_signal = 3, - .max_signal = 3, - .muxval = 1, - .periph_buses = PL08X_AHB2, - }, { - .bus_id = "uart1_rx", - .min_signal = 4, - .max_signal = 4, - .muxval = 1, - .periph_buses = PL08X_AHB2, - }, { - .bus_id = "uart1_tx", - .min_signal = 5, - .max_signal = 5, - .muxval = 1, - .periph_buses = PL08X_AHB2, - }, { - .bus_id = "uart2_rx", - .min_signal = 6, - .max_signal = 6, - .muxval = 1, - .periph_buses = PL08X_AHB2, - }, { - .bus_id = "uart2_tx", - .min_signal = 7, - .max_signal = 7, - .muxval = 1, - .periph_buses = PL08X_AHB2, - }, { - .bus_id = "i2c1_rx", - .min_signal = 8, - .max_signal = 8, - .muxval = 1, - .periph_buses = PL08X_AHB2, - }, { - .bus_id = "i2c1_tx", - .min_signal = 9, - .max_signal = 9, - .muxval = 1, - .periph_buses = PL08X_AHB2, - }, { - .bus_id = "i2c2_rx", - .min_signal = 10, - .max_signal = 10, - .muxval = 1, - .periph_buses = PL08X_AHB2, - }, { - .bus_id = "i2c2_tx", - .min_signal = 11, - .max_signal = 11, - .muxval = 1, - .periph_buses = PL08X_AHB2, - }, { - .bus_id = "i2s_rx", - .min_signal = 12, - .max_signal = 12, - .muxval = 1, - .periph_buses = PL08X_AHB2, - }, { - .bus_id = "i2s_tx", - .min_signal = 13, - .max_signal = 13, - .muxval = 1, - .periph_buses = PL08X_AHB2, - }, { - .bus_id = "rs485_rx", - .min_signal = 14, - .max_signal = 14, - .muxval = 1, - .periph_buses = PL08X_AHB2, - }, { - .bus_id = "rs485_tx", - .min_signal = 15, - .max_signal = 15, - .muxval = 1, - .periph_buses = PL08X_AHB2, - }, -}; - -static struct pl022_ssp_controller spear320_ssp_data[] = { - { - .bus_id = 1, - .enable_dma = 1, - .dma_filter = pl08x_filter_id, - .dma_tx_param = "ssp1_tx", - .dma_rx_param = "ssp1_rx", - .num_chipselect = 2, - }, { - .bus_id = 2, - .enable_dma = 1, - .dma_filter = pl08x_filter_id, - .dma_tx_param = "ssp2_tx", - .dma_rx_param = "ssp2_rx", - .num_chipselect = 2, - } -}; - -static struct amba_pl011_data spear320_uart_data[] = { - { - .dma_filter = pl08x_filter_id, - .dma_tx_param = "uart1_tx", - .dma_rx_param = "uart1_rx", - }, { - .dma_filter = pl08x_filter_id, - .dma_tx_param = "uart2_tx", - .dma_rx_param = "uart2_rx", - }, -}; - -/* Add SPEAr310 auxdata to pass platform data */ -static struct of_dev_auxdata spear320_auxdata_lookup[] __initdata = { - OF_DEV_AUXDATA("arm,pl022", SPEAR3XX_ICM1_SSP_BASE, NULL, - &pl022_plat_data), - OF_DEV_AUXDATA("arm,pl080", SPEAR_ICM3_DMA_BASE, NULL, - &pl080_plat_data), - OF_DEV_AUXDATA("arm,pl022", SPEAR320_SSP0_BASE, NULL, - &spear320_ssp_data[0]), - OF_DEV_AUXDATA("arm,pl022", SPEAR320_SSP1_BASE, NULL, - &spear320_ssp_data[1]), - OF_DEV_AUXDATA("arm,pl011", SPEAR320_UART1_BASE, NULL, - &spear320_uart_data[0]), - OF_DEV_AUXDATA("arm,pl011", SPEAR320_UART2_BASE, NULL, - &spear320_uart_data[1]), - {} -}; - -static void __init spear320_dt_init(void) -{ - pl080_plat_data.slave_channels = spear320_dma_info; - pl080_plat_data.num_slave_channels = ARRAY_SIZE(spear320_dma_info); - - of_platform_populate(NULL, of_default_bus_match_table, - spear320_auxdata_lookup, NULL); -} - -static const char * const spear320_dt_board_compat[] = { - "st,spear320", - "st,spear320-evb", - "st,spear320-hmi", - NULL, -}; - -struct map_desc spear320_io_desc[] __initdata = { - { - .virtual = VA_SPEAR320_SOC_CONFIG_BASE, - .pfn = __phys_to_pfn(SPEAR320_SOC_CONFIG_BASE), - .length = SZ_16M, - .type = MT_DEVICE - }, -}; - -static void __init spear320_map_io(void) -{ - iotable_init(spear320_io_desc, ARRAY_SIZE(spear320_io_desc)); - spear3xx_map_io(); -} - -DT_MACHINE_START(SPEAR320_DT, "ST SPEAr320 SoC with Flattened Device Tree") - .map_io = spear320_map_io, - .init_irq = irqchip_init, - .init_time = spear3xx_timer_init, - .init_machine = spear320_dt_init, - .restart = spear_restart, - .dt_compat = spear320_dt_board_compat, -MACHINE_END diff --git a/arch/arm/mach-spear3xx/spear3xx.c b/arch/arm/mach-spear3xx/spear3xx.c deleted file mode 100644 index d7580f2..0000000 --- a/arch/arm/mach-spear3xx/spear3xx.c +++ /dev/null @@ -1,115 +0,0 @@ -/* - * arch/arm/mach-spear3xx/spear3xx.c - * - * SPEAr3XX machines common source file - * - * Copyright (C) 2009-2012 ST Microelectronics - * Viresh Kumar - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#define pr_fmt(fmt) "SPEAr3xx: " fmt - -#include -#include -#include -#include -#include -#include -#include -#include - -/* ssp device registration */ -struct pl022_ssp_controller pl022_plat_data = { - .bus_id = 0, - .enable_dma = 1, - .dma_filter = pl08x_filter_id, - .dma_tx_param = "ssp0_tx", - .dma_rx_param = "ssp0_rx", - /* - * This is number of spi devices that can be connected to spi. There are - * two type of chipselects on which slave devices can work. One is chip - * select provided by spi masters other is controlled through external - * gpio's. We can't use chipselect provided from spi master (because as - * soon as FIFO becomes empty, CS is disabled and transfer ends). So - * this number now depends on number of gpios available for spi. each - * slave on each master requires a separate gpio pin. - */ - .num_chipselect = 2, -}; - -/* dmac device registration */ -struct pl08x_platform_data pl080_plat_data = { - .memcpy_channel = { - .bus_id = "memcpy", - .cctl_memcpy = - (PL080_BSIZE_16 << PL080_CONTROL_SB_SIZE_SHIFT | \ - PL080_BSIZE_16 << PL080_CONTROL_DB_SIZE_SHIFT | \ - PL080_WIDTH_32BIT << PL080_CONTROL_SWIDTH_SHIFT | \ - PL080_WIDTH_32BIT << PL080_CONTROL_DWIDTH_SHIFT | \ - PL080_CONTROL_PROT_BUFF | PL080_CONTROL_PROT_CACHE | \ - PL080_CONTROL_PROT_SYS), - }, - .lli_buses = PL08X_AHB1, - .mem_buses = PL08X_AHB1, - .get_signal = pl080_get_signal, - .put_signal = pl080_put_signal, -}; - -/* - * Following will create 16MB static virtual/physical mappings - * PHYSICAL VIRTUAL - * 0xD0000000 0xFD000000 - * 0xFC000000 0xFC000000 - */ -struct map_desc spear3xx_io_desc[] __initdata = { - { - .virtual = VA_SPEAR_ICM1_2_BASE, - .pfn = __phys_to_pfn(SPEAR_ICM1_2_BASE), - .length = SZ_16M, - .type = MT_DEVICE - }, { - .virtual = VA_SPEAR_ICM3_SMI_CTRL_BASE, - .pfn = __phys_to_pfn(SPEAR_ICM3_SMI_CTRL_BASE), - .length = SZ_16M, - .type = MT_DEVICE - }, -}; - -/* This will create static memory mapping for selected devices */ -void __init spear3xx_map_io(void) -{ - iotable_init(spear3xx_io_desc, ARRAY_SIZE(spear3xx_io_desc)); -} - -void __init spear3xx_timer_init(void) -{ - char pclk_name[] = "pll3_clk"; - struct clk *gpt_clk, *pclk; - - spear3xx_clk_init(); - - /* get the system timer clock */ - gpt_clk = clk_get_sys("gpt0", NULL); - if (IS_ERR(gpt_clk)) { - pr_err("%s:couldn't get clk for gpt\n", __func__); - BUG(); - } - - /* get the suitable parent clock for timer*/ - pclk = clk_get(NULL, pclk_name); - if (IS_ERR(pclk)) { - pr_err("%s:couldn't get %s as parent for gpt\n", - __func__, pclk_name); - BUG(); - } - - clk_set_parent(gpt_clk, pclk); - clk_put(gpt_clk); - clk_put(pclk); - - spear_setup_of_timer(); -} diff --git a/arch/arm/mach-spear6xx/Makefile b/arch/arm/mach-spear6xx/Makefile deleted file mode 100644 index 898831d..0000000 --- a/arch/arm/mach-spear6xx/Makefile +++ /dev/null @@ -1,6 +0,0 @@ -# -# Makefile for SPEAr6XX machine series -# - -# common files -obj-y += spear6xx.o diff --git a/arch/arm/mach-spear6xx/Makefile.boot b/arch/arm/mach-spear6xx/Makefile.boot deleted file mode 100644 index 4674a4c..0000000 --- a/arch/arm/mach-spear6xx/Makefile.boot +++ /dev/null @@ -1,3 +0,0 @@ -zreladdr-y += 0x00008000 -params_phys-y := 0x00000100 -initrd_phys-y := 0x00800000 diff --git a/arch/arm/mach-spear6xx/spear6xx.c b/arch/arm/mach-spear6xx/spear6xx.c deleted file mode 100644 index 97fb31d..0000000 --- a/arch/arm/mach-spear6xx/spear6xx.c +++ /dev/null @@ -1,430 +0,0 @@ -/* - * arch/arm/mach-spear6xx/spear6xx.c - * - * SPEAr6XX machines common source file - * - * Copyright (C) 2009 ST Microelectronics - * Rajeev Kumar - * - * Copyright 2012 Stefan Roese - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/* dmac device registration */ -static struct pl08x_channel_data spear600_dma_info[] = { - { - .bus_id = "ssp1_rx", - .min_signal = 0, - .max_signal = 0, - .muxval = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "ssp1_tx", - .min_signal = 1, - .max_signal = 1, - .muxval = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "uart0_rx", - .min_signal = 2, - .max_signal = 2, - .muxval = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "uart0_tx", - .min_signal = 3, - .max_signal = 3, - .muxval = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "uart1_rx", - .min_signal = 4, - .max_signal = 4, - .muxval = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "uart1_tx", - .min_signal = 5, - .max_signal = 5, - .muxval = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "ssp2_rx", - .min_signal = 6, - .max_signal = 6, - .muxval = 0, - .periph_buses = PL08X_AHB2, - }, { - .bus_id = "ssp2_tx", - .min_signal = 7, - .max_signal = 7, - .muxval = 0, - .periph_buses = PL08X_AHB2, - }, { - .bus_id = "ssp0_rx", - .min_signal = 8, - .max_signal = 8, - .muxval = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "ssp0_tx", - .min_signal = 9, - .max_signal = 9, - .muxval = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "i2c_rx", - .min_signal = 10, - .max_signal = 10, - .muxval = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "i2c_tx", - .min_signal = 11, - .max_signal = 11, - .muxval = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "irda", - .min_signal = 12, - .max_signal = 12, - .muxval = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "adc", - .min_signal = 13, - .max_signal = 13, - .muxval = 0, - .periph_buses = PL08X_AHB2, - }, { - .bus_id = "to_jpeg", - .min_signal = 14, - .max_signal = 14, - .muxval = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "from_jpeg", - .min_signal = 15, - .max_signal = 15, - .muxval = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "ras0_rx", - .min_signal = 0, - .max_signal = 0, - .muxval = 1, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "ras0_tx", - .min_signal = 1, - .max_signal = 1, - .muxval = 1, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "ras1_rx", - .min_signal = 2, - .max_signal = 2, - .muxval = 1, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "ras1_tx", - .min_signal = 3, - .max_signal = 3, - .muxval = 1, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "ras2_rx", - .min_signal = 4, - .max_signal = 4, - .muxval = 1, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "ras2_tx", - .min_signal = 5, - .max_signal = 5, - .muxval = 1, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "ras3_rx", - .min_signal = 6, - .max_signal = 6, - .muxval = 1, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "ras3_tx", - .min_signal = 7, - .max_signal = 7, - .muxval = 1, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "ras4_rx", - .min_signal = 8, - .max_signal = 8, - .muxval = 1, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "ras4_tx", - .min_signal = 9, - .max_signal = 9, - .muxval = 1, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "ras5_rx", - .min_signal = 10, - .max_signal = 10, - .muxval = 1, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "ras5_tx", - .min_signal = 11, - .max_signal = 11, - .muxval = 1, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "ras6_rx", - .min_signal = 12, - .max_signal = 12, - .muxval = 1, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "ras6_tx", - .min_signal = 13, - .max_signal = 13, - .muxval = 1, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "ras7_rx", - .min_signal = 14, - .max_signal = 14, - .muxval = 1, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "ras7_tx", - .min_signal = 15, - .max_signal = 15, - .muxval = 1, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "ext0_rx", - .min_signal = 0, - .max_signal = 0, - .muxval = 2, - .periph_buses = PL08X_AHB2, - }, { - .bus_id = "ext0_tx", - .min_signal = 1, - .max_signal = 1, - .muxval = 2, - .periph_buses = PL08X_AHB2, - }, { - .bus_id = "ext1_rx", - .min_signal = 2, - .max_signal = 2, - .muxval = 2, - .periph_buses = PL08X_AHB2, - }, { - .bus_id = "ext1_tx", - .min_signal = 3, - .max_signal = 3, - .muxval = 2, - .periph_buses = PL08X_AHB2, - }, { - .bus_id = "ext2_rx", - .min_signal = 4, - .max_signal = 4, - .muxval = 2, - .periph_buses = PL08X_AHB2, - }, { - .bus_id = "ext2_tx", - .min_signal = 5, - .max_signal = 5, - .muxval = 2, - .periph_buses = PL08X_AHB2, - }, { - .bus_id = "ext3_rx", - .min_signal = 6, - .max_signal = 6, - .muxval = 2, - .periph_buses = PL08X_AHB2, - }, { - .bus_id = "ext3_tx", - .min_signal = 7, - .max_signal = 7, - .muxval = 2, - .periph_buses = PL08X_AHB2, - }, { - .bus_id = "ext4_rx", - .min_signal = 8, - .max_signal = 8, - .muxval = 2, - .periph_buses = PL08X_AHB2, - }, { - .bus_id = "ext4_tx", - .min_signal = 9, - .max_signal = 9, - .muxval = 2, - .periph_buses = PL08X_AHB2, - }, { - .bus_id = "ext5_rx", - .min_signal = 10, - .max_signal = 10, - .muxval = 2, - .periph_buses = PL08X_AHB2, - }, { - .bus_id = "ext5_tx", - .min_signal = 11, - .max_signal = 11, - .muxval = 2, - .periph_buses = PL08X_AHB2, - }, { - .bus_id = "ext6_rx", - .min_signal = 12, - .max_signal = 12, - .muxval = 2, - .periph_buses = PL08X_AHB2, - }, { - .bus_id = "ext6_tx", - .min_signal = 13, - .max_signal = 13, - .muxval = 2, - .periph_buses = PL08X_AHB2, - }, { - .bus_id = "ext7_rx", - .min_signal = 14, - .max_signal = 14, - .muxval = 2, - .periph_buses = PL08X_AHB2, - }, { - .bus_id = "ext7_tx", - .min_signal = 15, - .max_signal = 15, - .muxval = 2, - .periph_buses = PL08X_AHB2, - }, -}; - -struct pl08x_platform_data pl080_plat_data = { - .memcpy_channel = { - .bus_id = "memcpy", - .cctl_memcpy = - (PL080_BSIZE_16 << PL080_CONTROL_SB_SIZE_SHIFT | \ - PL080_BSIZE_16 << PL080_CONTROL_DB_SIZE_SHIFT | \ - PL080_WIDTH_32BIT << PL080_CONTROL_SWIDTH_SHIFT | \ - PL080_WIDTH_32BIT << PL080_CONTROL_DWIDTH_SHIFT | \ - PL080_CONTROL_PROT_BUFF | PL080_CONTROL_PROT_CACHE | \ - PL080_CONTROL_PROT_SYS), - }, - .lli_buses = PL08X_AHB1, - .mem_buses = PL08X_AHB1, - .get_signal = pl080_get_signal, - .put_signal = pl080_put_signal, - .slave_channels = spear600_dma_info, - .num_slave_channels = ARRAY_SIZE(spear600_dma_info), -}; - -/* - * Following will create 16MB static virtual/physical mappings - * PHYSICAL VIRTUAL - * 0xF0000000 0xF0000000 - * 0xF1000000 0xF1000000 - * 0xD0000000 0xFD000000 - * 0xFC000000 0xFC000000 - */ -struct map_desc spear6xx_io_desc[] __initdata = { - { - .virtual = VA_SPEAR6XX_ML_CPU_BASE, - .pfn = __phys_to_pfn(SPEAR_ICM3_ML1_2_BASE), - .length = 2 * SZ_16M, - .type = MT_DEVICE - }, { - .virtual = VA_SPEAR_ICM1_2_BASE, - .pfn = __phys_to_pfn(SPEAR_ICM1_2_BASE), - .length = SZ_16M, - .type = MT_DEVICE - }, { - .virtual = VA_SPEAR_ICM3_SMI_CTRL_BASE, - .pfn = __phys_to_pfn(SPEAR_ICM3_SMI_CTRL_BASE), - .length = SZ_16M, - .type = MT_DEVICE - }, -}; - -/* This will create static memory mapping for selected devices */ -void __init spear6xx_map_io(void) -{ - iotable_init(spear6xx_io_desc, ARRAY_SIZE(spear6xx_io_desc)); -} - -void __init spear6xx_timer_init(void) -{ - char pclk_name[] = "pll3_clk"; - struct clk *gpt_clk, *pclk; - - spear6xx_clk_init(); - - /* get the system timer clock */ - gpt_clk = clk_get_sys("gpt0", NULL); - if (IS_ERR(gpt_clk)) { - pr_err("%s:couldn't get clk for gpt\n", __func__); - BUG(); - } - - /* get the suitable parent clock for timer*/ - pclk = clk_get(NULL, pclk_name); - if (IS_ERR(pclk)) { - pr_err("%s:couldn't get %s as parent for gpt\n", - __func__, pclk_name); - BUG(); - } - - clk_set_parent(gpt_clk, pclk); - clk_put(gpt_clk); - clk_put(pclk); - - spear_setup_of_timer(); -} - -/* Add auxdata to pass platform data */ -struct of_dev_auxdata spear6xx_auxdata_lookup[] __initdata = { - OF_DEV_AUXDATA("arm,pl080", SPEAR_ICM3_DMA_BASE, NULL, - &pl080_plat_data), - {} -}; - -static void __init spear600_dt_init(void) -{ - of_platform_populate(NULL, of_default_bus_match_table, - spear6xx_auxdata_lookup, NULL); -} - -static const char *spear600_dt_board_compat[] = { - "st,spear600", - NULL -}; - -DT_MACHINE_START(SPEAR600_DT, "ST SPEAr600 (Flattened Device Tree)") - .map_io = spear6xx_map_io, - .init_irq = irqchip_init, - .init_time = spear6xx_timer_init, - .init_machine = spear600_dt_init, - .restart = spear_restart, - .dt_compat = spear600_dt_board_compat, -MACHINE_END diff --git a/arch/arm/plat-spear/Kconfig b/arch/arm/plat-spear/Kconfig deleted file mode 100644 index e288df9..0000000 --- a/arch/arm/plat-spear/Kconfig +++ /dev/null @@ -1,90 +0,0 @@ -# -# SPEAr Platform configuration file -# - -if PLAT_SPEAR - -choice - prompt "ST SPEAr Family" - default ARCH_SPEAR3XX - -config ARCH_SPEAR13XX - bool "ST SPEAr13xx with Device Tree" - select ARCH_HAVE_CPUFREQ - select ARM_GIC - select CPU_V7 - select GPIO_SPEAR_SPICS - select HAVE_SMP - select MIGHT_HAVE_CACHE_L2X0 - select PINCTRL - select USE_OF - help - Supports for ARM's SPEAR13XX family - -config ARCH_SPEAR3XX - bool "ST SPEAr3xx with Device Tree" - select ARM_VIC - select CPU_ARM926T - select PINCTRL - select USE_OF - help - Supports for ARM's SPEAR3XX family - -config ARCH_SPEAR6XX - bool "SPEAr6XX" - select ARM_VIC - select CPU_ARM926T - help - Supports for ARM's SPEAR6XX family - -endchoice - -if ARCH_SPEAR13XX - -menu "SPEAr13xx Implementations" -config MACH_SPEAR1310 - bool "SPEAr1310 Machine support with Device Tree" - select PINCTRL_SPEAR1310 - help - Supports ST SPEAr1310 machine configured via the device-tree - -config MACH_SPEAR1340 - bool "SPEAr1340 Machine support with Device Tree" - select PINCTRL_SPEAR1340 - help - Supports ST SPEAr1340 machine configured via the device-tree -endmenu -endif #ARCH_SPEAR13XX - -if ARCH_SPEAR3XX - -menu "SPEAr3xx Implementations" -config MACH_SPEAR300 - bool "SPEAr300 Machine support with Device Tree" - select PINCTRL_SPEAR300 - help - Supports ST SPEAr300 machine configured via the device-tree - -config MACH_SPEAR310 - bool "SPEAr310 Machine support with Device Tree" - select PINCTRL_SPEAR310 - help - Supports ST SPEAr310 machine configured via the device-tree - -config MACH_SPEAR320 - bool "SPEAr320 Machine support with Device Tree" - select PINCTRL_SPEAR320 - help - Supports ST SPEAr320 machine configured via the device-tree -endmenu - -endif - -config MACH_SPEAR600 - def_bool y - depends on ARCH_SPEAR6XX - select USE_OF - help - Supports ST SPEAr600 boards configured via the device-treesource "arch/arm/mach-spear6xx/Kconfig" - -endif diff --git a/arch/arm/plat-spear/Makefile b/arch/arm/plat-spear/Makefile deleted file mode 100644 index 01e8853..0000000 --- a/arch/arm/plat-spear/Makefile +++ /dev/null @@ -1,9 +0,0 @@ -# -# SPEAr Platform specific Makefile -# - -# Common support -obj-y := restart.o time.o - -obj-$(CONFIG_ARCH_SPEAR3XX) += pl080.o -obj-$(CONFIG_ARCH_SPEAR6XX) += pl080.o diff --git a/arch/arm/plat-spear/include/mach/debug-macro.S b/arch/arm/plat-spear/include/mach/debug-macro.S deleted file mode 100644 index 75b05ad..0000000 --- a/arch/arm/plat-spear/include/mach/debug-macro.S +++ /dev/null @@ -1,36 +0,0 @@ -/* - * arch/arm/plat-spear/include/plat/debug-macro.S - * - * Debugging macro include header for spear platform - * - * Copyright (C) 2009 ST Microelectronics - * Viresh Kumar - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#include -#include - - .macro addruart, rp, rv, tmp - mov \rp, #SPEAR_DBG_UART_BASE @ Physical base - mov \rv, #VA_SPEAR_DBG_UART_BASE @ Virtual base - .endm - - .macro senduart, rd, rx - strb \rd, [\rx, #UART01x_DR] @ ASC_TX_BUFFER - .endm - - .macro waituart, rd, rx -1001: ldr \rd, [\rx, #UART01x_FR] @ FLAG REGISTER - tst \rd, #UART01x_FR_TXFF @ TX_FULL - bne 1001b - .endm - - .macro busyuart, rd, rx -1002: ldr \rd, [\rx, #UART01x_FR] @ FLAG REGISTER - tst \rd, #UART011_FR_TXFE @ TX_EMPTY - beq 1002b - .endm diff --git a/arch/arm/plat-spear/include/mach/generic.h b/arch/arm/plat-spear/include/mach/generic.h deleted file mode 100644 index af47d9b..0000000 --- a/arch/arm/plat-spear/include/mach/generic.h +++ /dev/null @@ -1,58 +0,0 @@ -/* - * spear machine family generic header file - * - * Copyright (C) 2009-2012 ST Microelectronics - * Rajeev Kumar - * Viresh Kumar - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#ifndef __MACH_GENERIC_H -#define __MACH_GENERIC_H - -#include -#include -#include -#include - -extern void spear13xx_timer_init(void); -extern void spear3xx_timer_init(void); -extern struct pl022_ssp_controller pl022_plat_data; -extern struct pl08x_platform_data pl080_plat_data; -extern struct dw_dma_platform_data dmac_plat_data; -extern struct dw_dma_slave cf_dma_priv; -extern struct dw_dma_slave nand_read_dma_priv; -extern struct dw_dma_slave nand_write_dma_priv; -bool dw_dma_filter(struct dma_chan *chan, void *slave); - -void __init spear_setup_of_timer(void); -void __init spear3xx_clk_init(void); -void __init spear3xx_map_io(void); -void __init spear3xx_dt_init_irq(void); -void __init spear6xx_clk_init(void); -void __init spear13xx_map_io(void); -void __init spear13xx_l2x0_init(void); - -void spear_restart(char, const char *); - -void spear13xx_secondary_startup(void); -void __cpuinit spear13xx_cpu_die(unsigned int cpu); - -extern struct smp_operations spear13xx_smp_ops; - -#ifdef CONFIG_MACH_SPEAR1310 -void __init spear1310_clk_init(void); -#else -static inline void spear1310_clk_init(void) {} -#endif - -#ifdef CONFIG_MACH_SPEAR1340 -void __init spear1340_clk_init(void); -#else -static inline void spear1340_clk_init(void) {} -#endif - -#endif /* __MACH_GENERIC_H */ diff --git a/arch/arm/plat-spear/include/mach/hardware.h b/arch/arm/plat-spear/include/mach/hardware.h deleted file mode 100644 index 40a8c17..0000000 --- a/arch/arm/plat-spear/include/mach/hardware.h +++ /dev/null @@ -1 +0,0 @@ -/* empty */ diff --git a/arch/arm/plat-spear/include/mach/irqs.h b/arch/arm/plat-spear/include/mach/irqs.h deleted file mode 100644 index 92da0a8..0000000 --- a/arch/arm/plat-spear/include/mach/irqs.h +++ /dev/null @@ -1,35 +0,0 @@ -/* - * IRQ helper macros for spear machine family - * - * Copyright (C) 2009-2012 ST Microelectronics - * Rajeev Kumar - * Viresh Kumar - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#ifndef __MACH_IRQS_H -#define __MACH_IRQS_H - -#ifdef CONFIG_ARCH_SPEAR3XX -#define NR_IRQS 256 -#endif - -#ifdef CONFIG_ARCH_SPEAR6XX -/* IRQ definitions */ -/* VIC 1 */ -#define IRQ_VIC_END 64 - -/* GPIO pins virtual irqs */ -#define VIRTUAL_IRQS 24 -#define NR_IRQS (IRQ_VIC_END + VIRTUAL_IRQS) -#endif - -#ifdef CONFIG_ARCH_SPEAR13XX -#define IRQ_GIC_END 160 -#define NR_IRQS IRQ_GIC_END -#endif - -#endif /* __MACH_IRQS_H */ diff --git a/arch/arm/plat-spear/include/mach/misc_regs.h b/arch/arm/plat-spear/include/mach/misc_regs.h deleted file mode 100644 index 075812c..0000000 --- a/arch/arm/plat-spear/include/mach/misc_regs.h +++ /dev/null @@ -1,22 +0,0 @@ -/* - * arch/arm/mach-spear3xx/include/mach/misc_regs.h - * - * Miscellaneous registers definitions for SPEAr3xx machine family - * - * Copyright (C) 2009 ST Microelectronics - * Viresh Kumar - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#ifndef __MACH_MISC_REGS_H -#define __MACH_MISC_REGS_H - -#include - -#define MISC_BASE IOMEM(VA_SPEAR_ICM3_MISC_REG_BASE) -#define DMA_CHN_CFG (MISC_BASE + 0x0A0) - -#endif /* __MACH_MISC_REGS_H */ diff --git a/arch/arm/plat-spear/include/mach/spear.h b/arch/arm/plat-spear/include/mach/spear.h deleted file mode 100644 index 2198ab9..0000000 --- a/arch/arm/plat-spear/include/mach/spear.h +++ /dev/null @@ -1,101 +0,0 @@ -/* - * SPEAr3xx/6xx Machine family specific definition - * - * Copyright (C) 2009,2012 ST Microelectronics - * Rajeev Kumar - * Viresh Kumar - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#ifndef __MACH_SPEAR_H -#define __MACH_SPEAR_H - -#include - -#if defined(CONFIG_ARCH_SPEAR3XX) || defined (CONFIG_ARCH_SPEAR6XX) - -/* ICM1 - Low speed connection */ -#define SPEAR_ICM1_2_BASE UL(0xD0000000) -#define VA_SPEAR_ICM1_2_BASE UL(0xFD000000) -#define SPEAR_ICM1_UART_BASE UL(0xD0000000) -#define VA_SPEAR_ICM1_UART_BASE (VA_SPEAR_ICM1_2_BASE | SPEAR_ICM1_UART_BASE) -#define SPEAR3XX_ICM1_SSP_BASE UL(0xD0100000) - -/* ML-1, 2 - Multi Layer CPU Subsystem */ -#define SPEAR_ICM3_ML1_2_BASE UL(0xF0000000) -#define VA_SPEAR6XX_ML_CPU_BASE UL(0xF0000000) - -/* ICM3 - Basic Subsystem */ -#define SPEAR_ICM3_SMI_CTRL_BASE UL(0xFC000000) -#define VA_SPEAR_ICM3_SMI_CTRL_BASE UL(0xFC000000) -#define SPEAR_ICM3_DMA_BASE UL(0xFC400000) -#define SPEAR_ICM3_SYS_CTRL_BASE UL(0xFCA00000) -#define VA_SPEAR_ICM3_SYS_CTRL_BASE (VA_SPEAR_ICM3_SMI_CTRL_BASE | SPEAR_ICM3_SYS_CTRL_BASE) -#define SPEAR_ICM3_MISC_REG_BASE UL(0xFCA80000) -#define VA_SPEAR_ICM3_MISC_REG_BASE (VA_SPEAR_ICM3_SMI_CTRL_BASE | SPEAR_ICM3_MISC_REG_BASE) - -/* Debug uart for linux, will be used for debug and uncompress messages */ -#define SPEAR_DBG_UART_BASE SPEAR_ICM1_UART_BASE -#define VA_SPEAR_DBG_UART_BASE VA_SPEAR_ICM1_UART_BASE - -/* Sysctl base for spear platform */ -#define SPEAR_SYS_CTRL_BASE SPEAR_ICM3_SYS_CTRL_BASE -#define VA_SPEAR_SYS_CTRL_BASE VA_SPEAR_ICM3_SYS_CTRL_BASE - -/* SPEAr320 Macros */ -#define SPEAR320_SOC_CONFIG_BASE UL(0xB3000000) -#define VA_SPEAR320_SOC_CONFIG_BASE UL(0xFE000000) -#define SPEAR320_CONTROL_REG IOMEM(VA_SPEAR320_SOC_CONFIG_BASE) -#define SPEAR320_EXT_CTRL_REG IOMEM(VA_SPEAR320_SOC_CONFIG_BASE + 0x0018) - #define SPEAR320_UARTX_PCLK_MASK 0x1 - #define SPEAR320_UART2_PCLK_SHIFT 8 - #define SPEAR320_UART3_PCLK_SHIFT 9 - #define SPEAR320_UART4_PCLK_SHIFT 10 - #define SPEAR320_UART5_PCLK_SHIFT 11 - #define SPEAR320_UART6_PCLK_SHIFT 12 - #define SPEAR320_RS485_PCLK_SHIFT 13 -#endif /* SPEAR3xx || SPEAR6XX */ - -#ifdef CONFIG_ARCH_SPEAR13XX - -#define PERIP_GRP2_BASE UL(0xB3000000) -#define VA_PERIP_GRP2_BASE IOMEM(0xFE000000) -#define MCIF_SDHCI_BASE UL(0xB3000000) -#define SYSRAM0_BASE UL(0xB3800000) -#define VA_SYSRAM0_BASE IOMEM(0xFE800000) -#define SYS_LOCATION (VA_SYSRAM0_BASE + 0x600) - -#define PERIP_GRP1_BASE UL(0xE0000000) -#define VA_PERIP_GRP1_BASE IOMEM(0xFD000000) -#define UART_BASE UL(0xE0000000) -#define VA_UART_BASE IOMEM(0xFD000000) -#define SSP_BASE UL(0xE0100000) -#define MISC_BASE UL(0xE0700000) -#define VA_MISC_BASE IOMEM(0xFD700000) - -#define A9SM_AND_MPMC_BASE UL(0xEC000000) -#define VA_A9SM_AND_MPMC_BASE IOMEM(0xFC000000) - -/* A9SM peripheral offsets */ -#define A9SM_PERIP_BASE UL(0xEC800000) -#define VA_A9SM_PERIP_BASE IOMEM(0xFC800000) -#define VA_SCU_BASE (VA_A9SM_PERIP_BASE + 0x00) - -#define L2CC_BASE UL(0xED000000) -#define VA_L2CC_BASE IOMEM(UL(0xFB000000)) - -/* others */ -#define DMAC0_BASE UL(0xEA800000) -#define DMAC1_BASE UL(0xEB000000) -#define MCIF_CF_BASE UL(0xB2800000) - -/* Debug uart for linux, will be used for debug and uncompress messages */ -#define SPEAR_DBG_UART_BASE UART_BASE -#define VA_SPEAR_DBG_UART_BASE VA_UART_BASE - -#endif /* SPEAR13XX */ - -#endif /* __MACH_SPEAR_H */ diff --git a/arch/arm/plat-spear/include/mach/timex.h b/arch/arm/plat-spear/include/mach/timex.h deleted file mode 100644 index ef95e5b..0000000 --- a/arch/arm/plat-spear/include/mach/timex.h +++ /dev/null @@ -1,19 +0,0 @@ -/* - * arch/arm/plat-spear/include/plat/timex.h - * - * SPEAr platform specific timex definitions - * - * Copyright (C) 2009 ST Microelectronics - * Viresh Kumar - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#ifndef __PLAT_TIMEX_H -#define __PLAT_TIMEX_H - -#define CLOCK_TICK_RATE 48000000 - -#endif /* __PLAT_TIMEX_H */ diff --git a/arch/arm/plat-spear/include/mach/uncompress.h b/arch/arm/plat-spear/include/mach/uncompress.h deleted file mode 100644 index 51b2dc9..0000000 --- a/arch/arm/plat-spear/include/mach/uncompress.h +++ /dev/null @@ -1,42 +0,0 @@ -/* - * arch/arm/plat-spear/include/plat/uncompress.h - * - * Serial port stubs for kernel decompress status messages - * - * Copyright (C) 2009 ST Microelectronics - * Viresh Kumar - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#include -#include -#include - -#ifndef __PLAT_UNCOMPRESS_H -#define __PLAT_UNCOMPRESS_H -/* - * This does not append a newline - */ -static inline void putc(int c) -{ - void __iomem *base = (void __iomem *)SPEAR_DBG_UART_BASE; - - while (readl_relaxed(base + UART01x_FR) & UART01x_FR_TXFF) - barrier(); - - writel_relaxed(c, base + UART01x_DR); -} - -static inline void flush(void) -{ -} - -/* - * nothing to do - */ -#define arch_decomp_setup() - -#endif /* __PLAT_UNCOMPRESS_H */ diff --git a/arch/arm/plat-spear/include/plat/pl080.h b/arch/arm/plat-spear/include/plat/pl080.h deleted file mode 100644 index eb6590d..0000000 --- a/arch/arm/plat-spear/include/plat/pl080.h +++ /dev/null @@ -1,21 +0,0 @@ -/* - * arch/arm/plat-spear/include/plat/pl080.h - * - * DMAC pl080 definitions for SPEAr platform - * - * Copyright (C) 2012 ST Microelectronics - * Viresh Kumar - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#ifndef __PLAT_PL080_H -#define __PLAT_PL080_H - -struct pl08x_channel_data; -int pl080_get_signal(const struct pl08x_channel_data *cd); -void pl080_put_signal(const struct pl08x_channel_data *cd, int signal); - -#endif /* __PLAT_PL080_H */ diff --git a/arch/arm/plat-spear/pl080.c b/arch/arm/plat-spear/pl080.c deleted file mode 100644 index cfa1199..0000000 --- a/arch/arm/plat-spear/pl080.c +++ /dev/null @@ -1,78 +0,0 @@ -/* - * arch/arm/plat-spear/pl080.c - * - * DMAC pl080 definitions for SPEAr platform - * - * Copyright (C) 2012 ST Microelectronics - * Viresh Kumar - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -static spinlock_t lock = __SPIN_LOCK_UNLOCKED(x); - -struct { - unsigned char busy; - unsigned char val; -} signals[16] = {{0, 0}, }; - -int pl080_get_signal(const struct pl08x_channel_data *cd) -{ - unsigned int signal = cd->min_signal, val; - unsigned long flags; - - spin_lock_irqsave(&lock, flags); - - /* Return if signal is already acquired by somebody else */ - if (signals[signal].busy && - (signals[signal].val != cd->muxval)) { - spin_unlock_irqrestore(&lock, flags); - return -EBUSY; - } - - /* If acquiring for the first time, configure it */ - if (!signals[signal].busy) { - val = readl(DMA_CHN_CFG); - - /* - * Each request line has two bits in DMA_CHN_CFG register. To - * goto the bits of current request line, do left shift of - * value by 2 * signal number. - */ - val &= ~(0x3 << (signal * 2)); - val |= cd->muxval << (signal * 2); - writel(val, DMA_CHN_CFG); - } - - signals[signal].busy++; - signals[signal].val = cd->muxval; - spin_unlock_irqrestore(&lock, flags); - - return signal; -} - -void pl080_put_signal(const struct pl08x_channel_data *cd, int signal) -{ - unsigned long flags; - - spin_lock_irqsave(&lock, flags); - - /* if signal is not used */ - if (!signals[signal].busy) - BUG(); - - signals[signal].busy--; - - spin_unlock_irqrestore(&lock, flags); -} diff --git a/arch/arm/plat-spear/restart.c b/arch/arm/plat-spear/restart.c deleted file mode 100644 index 7d4616d5..0000000 --- a/arch/arm/plat-spear/restart.c +++ /dev/null @@ -1,33 +0,0 @@ -/* - * arch/arm/plat-spear/restart.c - * - * SPEAr platform specific restart functions - * - * Copyright (C) 2009 ST Microelectronics - * Viresh Kumar - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ -#include -#include -#include -#include -#include - -#define SPEAR13XX_SYS_SW_RES (VA_MISC_BASE + 0x204) -void spear_restart(char mode, const char *cmd) -{ - if (mode == 's') { - /* software reset, Jump into ROM at address 0 */ - soft_restart(0); - } else { - /* hardware reset, Use on-chip reset capability */ -#ifdef CONFIG_ARCH_SPEAR13XX - writel_relaxed(0x01, SPEAR13XX_SYS_SW_RES); -#else - sysctl_soft_reset((void __iomem *)VA_SPEAR_SYS_CTRL_BASE); -#endif - } -} diff --git a/arch/arm/plat-spear/time.c b/arch/arm/plat-spear/time.c deleted file mode 100644 index bd5c53c..0000000 --- a/arch/arm/plat-spear/time.c +++ /dev/null @@ -1,245 +0,0 @@ -/* - * arch/arm/plat-spear/time.c - * - * Copyright (C) 2010 ST Microelectronics - * Shiraz Hashim - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/* - * We would use TIMER0 and TIMER1 as clockevent and clocksource. - * Timer0 and Timer1 both belong to same gpt block in cpu subbsystem. Further - * they share same functional clock. Any change in one's functional clock will - * also affect other timer. - */ - -#define CLKEVT 0 /* gpt0, channel0 as clockevent */ -#define CLKSRC 1 /* gpt0, channel1 as clocksource */ - -/* Register offsets, x is channel number */ -#define CR(x) ((x) * 0x80 + 0x80) -#define IR(x) ((x) * 0x80 + 0x84) -#define LOAD(x) ((x) * 0x80 + 0x88) -#define COUNT(x) ((x) * 0x80 + 0x8C) - -/* Reg bit definitions */ -#define CTRL_INT_ENABLE 0x0100 -#define CTRL_ENABLE 0x0020 -#define CTRL_ONE_SHOT 0x0010 - -#define CTRL_PRESCALER1 0x0 -#define CTRL_PRESCALER2 0x1 -#define CTRL_PRESCALER4 0x2 -#define CTRL_PRESCALER8 0x3 -#define CTRL_PRESCALER16 0x4 -#define CTRL_PRESCALER32 0x5 -#define CTRL_PRESCALER64 0x6 -#define CTRL_PRESCALER128 0x7 -#define CTRL_PRESCALER256 0x8 - -#define INT_STATUS 0x1 - -/* - * Minimum clocksource/clockevent timer range in seconds - */ -#define SPEAR_MIN_RANGE 4 - -static __iomem void *gpt_base; -static struct clk *gpt_clk; - -static void clockevent_set_mode(enum clock_event_mode mode, - struct clock_event_device *clk_event_dev); -static int clockevent_next_event(unsigned long evt, - struct clock_event_device *clk_event_dev); - -static void spear_clocksource_init(void) -{ - u32 tick_rate; - u16 val; - - /* program the prescaler (/256)*/ - writew(CTRL_PRESCALER256, gpt_base + CR(CLKSRC)); - - /* find out actual clock driving Timer */ - tick_rate = clk_get_rate(gpt_clk); - tick_rate >>= CTRL_PRESCALER256; - - writew(0xFFFF, gpt_base + LOAD(CLKSRC)); - - val = readw(gpt_base + CR(CLKSRC)); - val &= ~CTRL_ONE_SHOT; /* autoreload mode */ - val |= CTRL_ENABLE ; - writew(val, gpt_base + CR(CLKSRC)); - - /* register the clocksource */ - clocksource_mmio_init(gpt_base + COUNT(CLKSRC), "tmr1", tick_rate, - 200, 16, clocksource_mmio_readw_up); -} - -static struct clock_event_device clkevt = { - .name = "tmr0", - .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, - .set_mode = clockevent_set_mode, - .set_next_event = clockevent_next_event, - .shift = 0, /* to be computed */ -}; - -static void clockevent_set_mode(enum clock_event_mode mode, - struct clock_event_device *clk_event_dev) -{ - u32 period; - u16 val; - - /* stop the timer */ - val = readw(gpt_base + CR(CLKEVT)); - val &= ~CTRL_ENABLE; - writew(val, gpt_base + CR(CLKEVT)); - - switch (mode) { - case CLOCK_EVT_MODE_PERIODIC: - period = clk_get_rate(gpt_clk) / HZ; - period >>= CTRL_PRESCALER16; - writew(period, gpt_base + LOAD(CLKEVT)); - - val = readw(gpt_base + CR(CLKEVT)); - val &= ~CTRL_ONE_SHOT; - val |= CTRL_ENABLE | CTRL_INT_ENABLE; - writew(val, gpt_base + CR(CLKEVT)); - - break; - case CLOCK_EVT_MODE_ONESHOT: - val = readw(gpt_base + CR(CLKEVT)); - val |= CTRL_ONE_SHOT; - writew(val, gpt_base + CR(CLKEVT)); - - break; - case CLOCK_EVT_MODE_UNUSED: - case CLOCK_EVT_MODE_SHUTDOWN: - case CLOCK_EVT_MODE_RESUME: - - break; - default: - pr_err("Invalid mode requested\n"); - break; - } -} - -static int clockevent_next_event(unsigned long cycles, - struct clock_event_device *clk_event_dev) -{ - u16 val = readw(gpt_base + CR(CLKEVT)); - - if (val & CTRL_ENABLE) - writew(val & ~CTRL_ENABLE, gpt_base + CR(CLKEVT)); - - writew(cycles, gpt_base + LOAD(CLKEVT)); - - val |= CTRL_ENABLE | CTRL_INT_ENABLE; - writew(val, gpt_base + CR(CLKEVT)); - - return 0; -} - -static irqreturn_t spear_timer_interrupt(int irq, void *dev_id) -{ - struct clock_event_device *evt = &clkevt; - - writew(INT_STATUS, gpt_base + IR(CLKEVT)); - - evt->event_handler(evt); - - return IRQ_HANDLED; -} - -static struct irqaction spear_timer_irq = { - .name = "timer", - .flags = IRQF_DISABLED | IRQF_TIMER, - .handler = spear_timer_interrupt -}; - -static void __init spear_clockevent_init(int irq) -{ - u32 tick_rate; - - /* program the prescaler */ - writew(CTRL_PRESCALER16, gpt_base + CR(CLKEVT)); - - tick_rate = clk_get_rate(gpt_clk); - tick_rate >>= CTRL_PRESCALER16; - - clkevt.cpumask = cpumask_of(0); - - clockevents_config_and_register(&clkevt, tick_rate, 3, 0xfff0); - - setup_irq(irq, &spear_timer_irq); -} - -const static struct of_device_id timer_of_match[] __initconst = { - { .compatible = "st,spear-timer", }, - { }, -}; - -void __init spear_setup_of_timer(void) -{ - struct device_node *np; - int irq, ret; - - np = of_find_matching_node(NULL, timer_of_match); - if (!np) { - pr_err("%s: No timer passed via DT\n", __func__); - return; - } - - irq = irq_of_parse_and_map(np, 0); - if (!irq) { - pr_err("%s: No irq passed for timer via DT\n", __func__); - return; - } - - gpt_base = of_iomap(np, 0); - if (!gpt_base) { - pr_err("%s: of iomap failed\n", __func__); - return; - } - - gpt_clk = clk_get_sys("gpt0", NULL); - if (!gpt_clk) { - pr_err("%s:couldn't get clk for gpt\n", __func__); - goto err_iomap; - } - - ret = clk_prepare_enable(gpt_clk); - if (ret < 0) { - pr_err("%s:couldn't prepare-enable gpt clock\n", __func__); - goto err_prepare_enable_clk; - } - - spear_clockevent_init(irq); - spear_clocksource_init(); - - return; - -err_prepare_enable_clk: - clk_put(gpt_clk); -err_iomap: - iounmap(gpt_base); -} -- cgit v1.1 From 2b9c613c4ee1756664fcbf6fc4926fee3e7139c3 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Sun, 2 Dec 2012 15:49:04 +0100 Subject: ARM: spear: move generic.h and pl080.h into private dir No file outside of mach-spear includes these files any more, so they don't have to be globally visible now. Signed-off-by: Arnd Bergmann Acked-by: Viresh Kumar --- arch/arm/mach-spear/generic.h | 58 +++++++++++++++++++++++++++++ arch/arm/mach-spear/include/mach/generic.h | 58 ----------------------------- arch/arm/mach-spear/include/mach/hardware.h | 1 - arch/arm/mach-spear/include/plat/pl080.h | 21 ----------- arch/arm/mach-spear/pl080.h | 21 +++++++++++ arch/arm/mach-spear/platsmp.c | 2 +- arch/arm/mach-spear/restart.c | 2 +- arch/arm/mach-spear/spear1310.c | 2 +- arch/arm/mach-spear/spear1340.c | 2 +- arch/arm/mach-spear/spear13xx.c | 2 +- arch/arm/mach-spear/spear300.c | 2 +- arch/arm/mach-spear/spear310.c | 2 +- arch/arm/mach-spear/spear320.c | 2 +- arch/arm/mach-spear/spear3xx.c | 4 +- arch/arm/mach-spear/spear6xx.c | 4 +- arch/arm/mach-spear/time.c | 2 +- 16 files changed, 92 insertions(+), 93 deletions(-) create mode 100644 arch/arm/mach-spear/generic.h delete mode 100644 arch/arm/mach-spear/include/mach/generic.h delete mode 100644 arch/arm/mach-spear/include/mach/hardware.h delete mode 100644 arch/arm/mach-spear/include/plat/pl080.h create mode 100644 arch/arm/mach-spear/pl080.h (limited to 'arch/arm') diff --git a/arch/arm/mach-spear/generic.h b/arch/arm/mach-spear/generic.h new file mode 100644 index 0000000..af47d9b --- /dev/null +++ b/arch/arm/mach-spear/generic.h @@ -0,0 +1,58 @@ +/* + * spear machine family generic header file + * + * Copyright (C) 2009-2012 ST Microelectronics + * Rajeev Kumar + * Viresh Kumar + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __MACH_GENERIC_H +#define __MACH_GENERIC_H + +#include +#include +#include +#include + +extern void spear13xx_timer_init(void); +extern void spear3xx_timer_init(void); +extern struct pl022_ssp_controller pl022_plat_data; +extern struct pl08x_platform_data pl080_plat_data; +extern struct dw_dma_platform_data dmac_plat_data; +extern struct dw_dma_slave cf_dma_priv; +extern struct dw_dma_slave nand_read_dma_priv; +extern struct dw_dma_slave nand_write_dma_priv; +bool dw_dma_filter(struct dma_chan *chan, void *slave); + +void __init spear_setup_of_timer(void); +void __init spear3xx_clk_init(void); +void __init spear3xx_map_io(void); +void __init spear3xx_dt_init_irq(void); +void __init spear6xx_clk_init(void); +void __init spear13xx_map_io(void); +void __init spear13xx_l2x0_init(void); + +void spear_restart(char, const char *); + +void spear13xx_secondary_startup(void); +void __cpuinit spear13xx_cpu_die(unsigned int cpu); + +extern struct smp_operations spear13xx_smp_ops; + +#ifdef CONFIG_MACH_SPEAR1310 +void __init spear1310_clk_init(void); +#else +static inline void spear1310_clk_init(void) {} +#endif + +#ifdef CONFIG_MACH_SPEAR1340 +void __init spear1340_clk_init(void); +#else +static inline void spear1340_clk_init(void) {} +#endif + +#endif /* __MACH_GENERIC_H */ diff --git a/arch/arm/mach-spear/include/mach/generic.h b/arch/arm/mach-spear/include/mach/generic.h deleted file mode 100644 index af47d9b..0000000 --- a/arch/arm/mach-spear/include/mach/generic.h +++ /dev/null @@ -1,58 +0,0 @@ -/* - * spear machine family generic header file - * - * Copyright (C) 2009-2012 ST Microelectronics - * Rajeev Kumar - * Viresh Kumar - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#ifndef __MACH_GENERIC_H -#define __MACH_GENERIC_H - -#include -#include -#include -#include - -extern void spear13xx_timer_init(void); -extern void spear3xx_timer_init(void); -extern struct pl022_ssp_controller pl022_plat_data; -extern struct pl08x_platform_data pl080_plat_data; -extern struct dw_dma_platform_data dmac_plat_data; -extern struct dw_dma_slave cf_dma_priv; -extern struct dw_dma_slave nand_read_dma_priv; -extern struct dw_dma_slave nand_write_dma_priv; -bool dw_dma_filter(struct dma_chan *chan, void *slave); - -void __init spear_setup_of_timer(void); -void __init spear3xx_clk_init(void); -void __init spear3xx_map_io(void); -void __init spear3xx_dt_init_irq(void); -void __init spear6xx_clk_init(void); -void __init spear13xx_map_io(void); -void __init spear13xx_l2x0_init(void); - -void spear_restart(char, const char *); - -void spear13xx_secondary_startup(void); -void __cpuinit spear13xx_cpu_die(unsigned int cpu); - -extern struct smp_operations spear13xx_smp_ops; - -#ifdef CONFIG_MACH_SPEAR1310 -void __init spear1310_clk_init(void); -#else -static inline void spear1310_clk_init(void) {} -#endif - -#ifdef CONFIG_MACH_SPEAR1340 -void __init spear1340_clk_init(void); -#else -static inline void spear1340_clk_init(void) {} -#endif - -#endif /* __MACH_GENERIC_H */ diff --git a/arch/arm/mach-spear/include/mach/hardware.h b/arch/arm/mach-spear/include/mach/hardware.h deleted file mode 100644 index 40a8c17..0000000 --- a/arch/arm/mach-spear/include/mach/hardware.h +++ /dev/null @@ -1 +0,0 @@ -/* empty */ diff --git a/arch/arm/mach-spear/include/plat/pl080.h b/arch/arm/mach-spear/include/plat/pl080.h deleted file mode 100644 index eb6590d..0000000 --- a/arch/arm/mach-spear/include/plat/pl080.h +++ /dev/null @@ -1,21 +0,0 @@ -/* - * arch/arm/plat-spear/include/plat/pl080.h - * - * DMAC pl080 definitions for SPEAr platform - * - * Copyright (C) 2012 ST Microelectronics - * Viresh Kumar - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#ifndef __PLAT_PL080_H -#define __PLAT_PL080_H - -struct pl08x_channel_data; -int pl080_get_signal(const struct pl08x_channel_data *cd); -void pl080_put_signal(const struct pl08x_channel_data *cd, int signal); - -#endif /* __PLAT_PL080_H */ diff --git a/arch/arm/mach-spear/pl080.h b/arch/arm/mach-spear/pl080.h new file mode 100644 index 0000000..eb6590d --- /dev/null +++ b/arch/arm/mach-spear/pl080.h @@ -0,0 +1,21 @@ +/* + * arch/arm/plat-spear/include/plat/pl080.h + * + * DMAC pl080 definitions for SPEAr platform + * + * Copyright (C) 2012 ST Microelectronics + * Viresh Kumar + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __PLAT_PL080_H +#define __PLAT_PL080_H + +struct pl08x_channel_data; +int pl080_get_signal(const struct pl08x_channel_data *cd); +void pl080_put_signal(const struct pl08x_channel_data *cd, int signal); + +#endif /* __PLAT_PL080_H */ diff --git a/arch/arm/mach-spear/platsmp.c b/arch/arm/mach-spear/platsmp.c index af4ade6..927979e 100644 --- a/arch/arm/mach-spear/platsmp.c +++ b/arch/arm/mach-spear/platsmp.c @@ -19,7 +19,7 @@ #include #include #include -#include +#include "generic.h" static DEFINE_SPINLOCK(boot_lock); diff --git a/arch/arm/mach-spear/restart.c b/arch/arm/mach-spear/restart.c index 7d4616d5..004f0f2 100644 --- a/arch/arm/mach-spear/restart.c +++ b/arch/arm/mach-spear/restart.c @@ -14,7 +14,7 @@ #include #include #include -#include +#include "generic.h" #define SPEAR13XX_SYS_SW_RES (VA_MISC_BASE + 0x204) void spear_restart(char mode, const char *cmd) diff --git a/arch/arm/mach-spear/spear1310.c b/arch/arm/mach-spear/spear1310.c index 56214d1..fe868b2 100644 --- a/arch/arm/mach-spear/spear1310.c +++ b/arch/arm/mach-spear/spear1310.c @@ -19,7 +19,7 @@ #include #include #include -#include +#include "generic.h" #include /* Base addresses */ diff --git a/arch/arm/mach-spear/spear1340.c b/arch/arm/mach-spear/spear1340.c index b01c4c7..75e3864 100644 --- a/arch/arm/mach-spear/spear1340.c +++ b/arch/arm/mach-spear/spear1340.c @@ -20,7 +20,7 @@ #include #include #include -#include +#include "generic.h" #include #include "spear13xx-dma.h" diff --git a/arch/arm/mach-spear/spear13xx.c b/arch/arm/mach-spear/spear13xx.c index 988fefe..6f62dd5 100644 --- a/arch/arm/mach-spear/spear13xx.c +++ b/arch/arm/mach-spear/spear13xx.c @@ -21,7 +21,7 @@ #include #include #include -#include +#include "generic.h" #include #include "spear13xx-dma.h" diff --git a/arch/arm/mach-spear/spear300.c b/arch/arm/mach-spear/spear300.c index 72449ee..bac56e8 100644 --- a/arch/arm/mach-spear/spear300.c +++ b/arch/arm/mach-spear/spear300.c @@ -17,7 +17,7 @@ #include #include #include -#include +#include "generic.h" #include /* DMAC platform data's slave info */ diff --git a/arch/arm/mach-spear/spear310.c b/arch/arm/mach-spear/spear310.c index 0b7962d..6ffbc63 100644 --- a/arch/arm/mach-spear/spear310.c +++ b/arch/arm/mach-spear/spear310.c @@ -18,7 +18,7 @@ #include #include #include -#include +#include "generic.h" #include #define SPEAR310_UART1_BASE UL(0xB2000000) diff --git a/arch/arm/mach-spear/spear320.c b/arch/arm/mach-spear/spear320.c index e9db7db..b8a4bb5 100644 --- a/arch/arm/mach-spear/spear320.c +++ b/arch/arm/mach-spear/spear320.c @@ -20,7 +20,7 @@ #include #include #include -#include +#include "generic.h" #include #define SPEAR320_UART1_BASE UL(0xA3000000) diff --git a/arch/arm/mach-spear/spear3xx.c b/arch/arm/mach-spear/spear3xx.c index d7580f2..be0c94d 100644 --- a/arch/arm/mach-spear/spear3xx.c +++ b/arch/arm/mach-spear/spear3xx.c @@ -18,8 +18,8 @@ #include #include #include -#include -#include +#include "pl080.h" +#include "generic.h" #include /* ssp device registration */ diff --git a/arch/arm/mach-spear/spear6xx.c b/arch/arm/mach-spear/spear6xx.c index 97fb31d..78e1359 100644 --- a/arch/arm/mach-spear/spear6xx.c +++ b/arch/arm/mach-spear/spear6xx.c @@ -24,8 +24,8 @@ #include #include #include -#include -#include +#include "pl080.h" +#include "generic.h" #include /* dmac device registration */ diff --git a/arch/arm/mach-spear/time.c b/arch/arm/mach-spear/time.c index bd5c53c..d449673 100644 --- a/arch/arm/mach-spear/time.c +++ b/arch/arm/mach-spear/time.c @@ -23,7 +23,7 @@ #include #include #include -#include +#include "generic.h" /* * We would use TIMER0 and TIMER1 as clockevent and clocksource. -- cgit v1.1 From d9909ebe650f028459b9be5a2321fee520b446b0 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Sun, 2 Dec 2012 17:59:57 +0100 Subject: ARM: spear: make clock driver independent of headers Device drivers should not access MMIO registers through hardcoded platform specific address constants. Instead, we can pass the MMIO token to the spear clock driver in the initialization routine to contain that knowledge in the platform code itself. Ideally, the clock driver would use of_iomap() or similar to get the address, and that can be used later, but for now, this is the minimal change. Signed-off-by: Arnd Bergmann Acked-by: Viresh Kumar --- arch/arm/mach-spear/generic.h | 13 +++++++------ arch/arm/mach-spear/include/mach/misc_regs.h | 2 +- arch/arm/mach-spear/include/mach/spear.h | 28 +++++++++++----------------- arch/arm/mach-spear/spear1310.c | 2 -- arch/arm/mach-spear/spear13xx.c | 4 ++-- arch/arm/mach-spear/spear320.c | 2 +- arch/arm/mach-spear/spear3xx.c | 7 ++++--- arch/arm/mach-spear/spear6xx.c | 9 +++++---- 8 files changed, 31 insertions(+), 36 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-spear/generic.h b/arch/arm/mach-spear/generic.h index af47d9b..8ba7e75 100644 --- a/arch/arm/mach-spear/generic.h +++ b/arch/arm/mach-spear/generic.h @@ -29,10 +29,11 @@ extern struct dw_dma_slave nand_write_dma_priv; bool dw_dma_filter(struct dma_chan *chan, void *slave); void __init spear_setup_of_timer(void); -void __init spear3xx_clk_init(void); +void __init spear3xx_clk_init(void __iomem *misc_base, + void __iomem *soc_config_base); void __init spear3xx_map_io(void); void __init spear3xx_dt_init_irq(void); -void __init spear6xx_clk_init(void); +void __init spear6xx_clk_init(void __iomem *misc_base); void __init spear13xx_map_io(void); void __init spear13xx_l2x0_init(void); @@ -44,15 +45,15 @@ void __cpuinit spear13xx_cpu_die(unsigned int cpu); extern struct smp_operations spear13xx_smp_ops; #ifdef CONFIG_MACH_SPEAR1310 -void __init spear1310_clk_init(void); +void __init spear1310_clk_init(void __iomem *misc_base, void __iomem *ras_base); #else -static inline void spear1310_clk_init(void) {} +static inline void spear1310_clk_init(void __iomem *misc_base, void __iomem *ras_base) {} #endif #ifdef CONFIG_MACH_SPEAR1340 -void __init spear1340_clk_init(void); +void __init spear1340_clk_init(void __iomem *misc_base); #else -static inline void spear1340_clk_init(void) {} +static inline void spear1340_clk_init(void __iomem *misc_base) {} #endif #endif /* __MACH_GENERIC_H */ diff --git a/arch/arm/mach-spear/include/mach/misc_regs.h b/arch/arm/mach-spear/include/mach/misc_regs.h index 075812c..935639c 100644 --- a/arch/arm/mach-spear/include/mach/misc_regs.h +++ b/arch/arm/mach-spear/include/mach/misc_regs.h @@ -16,7 +16,7 @@ #include -#define MISC_BASE IOMEM(VA_SPEAR_ICM3_MISC_REG_BASE) +#define MISC_BASE (VA_SPEAR_ICM3_MISC_REG_BASE) #define DMA_CHN_CFG (MISC_BASE + 0x0A0) #endif /* __MACH_MISC_REGS_H */ diff --git a/arch/arm/mach-spear/include/mach/spear.h b/arch/arm/mach-spear/include/mach/spear.h index 2198ab9..374ddc3 100644 --- a/arch/arm/mach-spear/include/mach/spear.h +++ b/arch/arm/mach-spear/include/mach/spear.h @@ -19,23 +19,23 @@ /* ICM1 - Low speed connection */ #define SPEAR_ICM1_2_BASE UL(0xD0000000) -#define VA_SPEAR_ICM1_2_BASE UL(0xFD000000) +#define VA_SPEAR_ICM1_2_BASE IOMEM(0xFD000000) #define SPEAR_ICM1_UART_BASE UL(0xD0000000) -#define VA_SPEAR_ICM1_UART_BASE (VA_SPEAR_ICM1_2_BASE | SPEAR_ICM1_UART_BASE) +#define VA_SPEAR_ICM1_UART_BASE (VA_SPEAR_ICM1_2_BASE - SPEAR_ICM1_2_BASE + SPEAR_ICM1_UART_BASE) #define SPEAR3XX_ICM1_SSP_BASE UL(0xD0100000) /* ML-1, 2 - Multi Layer CPU Subsystem */ #define SPEAR_ICM3_ML1_2_BASE UL(0xF0000000) -#define VA_SPEAR6XX_ML_CPU_BASE UL(0xF0000000) +#define VA_SPEAR6XX_ML_CPU_BASE IOMEM(0xF0000000) /* ICM3 - Basic Subsystem */ #define SPEAR_ICM3_SMI_CTRL_BASE UL(0xFC000000) -#define VA_SPEAR_ICM3_SMI_CTRL_BASE UL(0xFC000000) +#define VA_SPEAR_ICM3_SMI_CTRL_BASE IOMEM(0xFC000000) #define SPEAR_ICM3_DMA_BASE UL(0xFC400000) #define SPEAR_ICM3_SYS_CTRL_BASE UL(0xFCA00000) -#define VA_SPEAR_ICM3_SYS_CTRL_BASE (VA_SPEAR_ICM3_SMI_CTRL_BASE | SPEAR_ICM3_SYS_CTRL_BASE) +#define VA_SPEAR_ICM3_SYS_CTRL_BASE (VA_SPEAR_ICM3_SMI_CTRL_BASE - SPEAR_ICM3_SMI_CTRL_BASE + SPEAR_ICM3_SYS_CTRL_BASE) #define SPEAR_ICM3_MISC_REG_BASE UL(0xFCA80000) -#define VA_SPEAR_ICM3_MISC_REG_BASE (VA_SPEAR_ICM3_SMI_CTRL_BASE | SPEAR_ICM3_MISC_REG_BASE) +#define VA_SPEAR_ICM3_MISC_REG_BASE (VA_SPEAR_ICM3_SMI_CTRL_BASE - SPEAR_ICM3_SMI_CTRL_BASE + SPEAR_ICM3_MISC_REG_BASE) /* Debug uart for linux, will be used for debug and uncompress messages */ #define SPEAR_DBG_UART_BASE SPEAR_ICM1_UART_BASE @@ -44,20 +44,11 @@ /* Sysctl base for spear platform */ #define SPEAR_SYS_CTRL_BASE SPEAR_ICM3_SYS_CTRL_BASE #define VA_SPEAR_SYS_CTRL_BASE VA_SPEAR_ICM3_SYS_CTRL_BASE +#endif /* SPEAR3xx || SPEAR6XX */ /* SPEAr320 Macros */ #define SPEAR320_SOC_CONFIG_BASE UL(0xB3000000) -#define VA_SPEAR320_SOC_CONFIG_BASE UL(0xFE000000) -#define SPEAR320_CONTROL_REG IOMEM(VA_SPEAR320_SOC_CONFIG_BASE) -#define SPEAR320_EXT_CTRL_REG IOMEM(VA_SPEAR320_SOC_CONFIG_BASE + 0x0018) - #define SPEAR320_UARTX_PCLK_MASK 0x1 - #define SPEAR320_UART2_PCLK_SHIFT 8 - #define SPEAR320_UART3_PCLK_SHIFT 9 - #define SPEAR320_UART4_PCLK_SHIFT 10 - #define SPEAR320_UART5_PCLK_SHIFT 11 - #define SPEAR320_UART6_PCLK_SHIFT 12 - #define SPEAR320_RS485_PCLK_SHIFT 13 -#endif /* SPEAR3xx || SPEAR6XX */ +#define VA_SPEAR320_SOC_CONFIG_BASE IOMEM(0xFE000000) #ifdef CONFIG_ARCH_SPEAR13XX @@ -79,6 +70,9 @@ #define A9SM_AND_MPMC_BASE UL(0xEC000000) #define VA_A9SM_AND_MPMC_BASE IOMEM(0xFC000000) +#define SPEAR1310_RAS_BASE UL(0xD8400000) +#define VA_SPEAR1310_RAS_BASE IOMEM(UL(0xFA400000)) + /* A9SM peripheral offsets */ #define A9SM_PERIP_BASE UL(0xEC800000) #define VA_A9SM_PERIP_BASE IOMEM(0xFC800000) diff --git a/arch/arm/mach-spear/spear1310.c b/arch/arm/mach-spear/spear1310.c index fe868b2..ed3b5c2 100644 --- a/arch/arm/mach-spear/spear1310.c +++ b/arch/arm/mach-spear/spear1310.c @@ -30,8 +30,6 @@ #define SPEAR1310_RAS_GRP1_BASE UL(0xD8000000) #define VA_SPEAR1310_RAS_GRP1_BASE UL(0xFA000000) -#define SPEAR1310_RAS_BASE UL(0xD8400000) -#define VA_SPEAR1310_RAS_BASE IOMEM(UL(0xFA400000)) static struct arasan_cf_pdata cf_pdata = { .cf_if_clk = CF_IF_CLK_166M, diff --git a/arch/arm/mach-spear/spear13xx.c b/arch/arm/mach-spear/spear13xx.c index 6f62dd5..1b97e86 100644 --- a/arch/arm/mach-spear/spear13xx.c +++ b/arch/arm/mach-spear/spear13xx.c @@ -146,9 +146,9 @@ void __init spear13xx_map_io(void) static void __init spear13xx_clk_init(void) { if (of_machine_is_compatible("st,spear1310")) - spear1310_clk_init(); + spear1310_clk_init(VA_MISC_BASE, VA_SPEAR1310_RAS_BASE); else if (of_machine_is_compatible("st,spear1340")) - spear1340_clk_init(); + spear1340_clk_init(VA_MISC_BASE); else pr_err("%s: Unknown machine\n", __func__); } diff --git a/arch/arm/mach-spear/spear320.c b/arch/arm/mach-spear/spear320.c index b8a4bb5..6eb3eec 100644 --- a/arch/arm/mach-spear/spear320.c +++ b/arch/arm/mach-spear/spear320.c @@ -254,7 +254,7 @@ static const char * const spear320_dt_board_compat[] = { struct map_desc spear320_io_desc[] __initdata = { { - .virtual = VA_SPEAR320_SOC_CONFIG_BASE, + .virtual = (unsigned long)VA_SPEAR320_SOC_CONFIG_BASE, .pfn = __phys_to_pfn(SPEAR320_SOC_CONFIG_BASE), .length = SZ_16M, .type = MT_DEVICE diff --git a/arch/arm/mach-spear/spear3xx.c b/arch/arm/mach-spear/spear3xx.c index be0c94d..0227c97 100644 --- a/arch/arm/mach-spear/spear3xx.c +++ b/arch/arm/mach-spear/spear3xx.c @@ -21,6 +21,7 @@ #include "pl080.h" #include "generic.h" #include +#include /* ssp device registration */ struct pl022_ssp_controller pl022_plat_data = { @@ -67,12 +68,12 @@ struct pl08x_platform_data pl080_plat_data = { */ struct map_desc spear3xx_io_desc[] __initdata = { { - .virtual = VA_SPEAR_ICM1_2_BASE, + .virtual = (unsigned long)VA_SPEAR_ICM1_2_BASE, .pfn = __phys_to_pfn(SPEAR_ICM1_2_BASE), .length = SZ_16M, .type = MT_DEVICE }, { - .virtual = VA_SPEAR_ICM3_SMI_CTRL_BASE, + .virtual = (unsigned long)VA_SPEAR_ICM3_SMI_CTRL_BASE, .pfn = __phys_to_pfn(SPEAR_ICM3_SMI_CTRL_BASE), .length = SZ_16M, .type = MT_DEVICE @@ -90,7 +91,7 @@ void __init spear3xx_timer_init(void) char pclk_name[] = "pll3_clk"; struct clk *gpt_clk, *pclk; - spear3xx_clk_init(); + spear3xx_clk_init(MISC_BASE, VA_SPEAR320_SOC_CONFIG_BASE); /* get the system timer clock */ gpt_clk = clk_get_sys("gpt0", NULL); diff --git a/arch/arm/mach-spear/spear6xx.c b/arch/arm/mach-spear/spear6xx.c index 78e1359..9b5ea25 100644 --- a/arch/arm/mach-spear/spear6xx.c +++ b/arch/arm/mach-spear/spear6xx.c @@ -27,6 +27,7 @@ #include "pl080.h" #include "generic.h" #include +#include /* dmac device registration */ static struct pl08x_channel_data spear600_dma_info[] = { @@ -350,17 +351,17 @@ struct pl08x_platform_data pl080_plat_data = { */ struct map_desc spear6xx_io_desc[] __initdata = { { - .virtual = VA_SPEAR6XX_ML_CPU_BASE, + .virtual = (unsigned long)VA_SPEAR6XX_ML_CPU_BASE, .pfn = __phys_to_pfn(SPEAR_ICM3_ML1_2_BASE), .length = 2 * SZ_16M, .type = MT_DEVICE }, { - .virtual = VA_SPEAR_ICM1_2_BASE, + .virtual = (unsigned long)VA_SPEAR_ICM1_2_BASE, .pfn = __phys_to_pfn(SPEAR_ICM1_2_BASE), .length = SZ_16M, .type = MT_DEVICE }, { - .virtual = VA_SPEAR_ICM3_SMI_CTRL_BASE, + .virtual = (unsigned long)VA_SPEAR_ICM3_SMI_CTRL_BASE, .pfn = __phys_to_pfn(SPEAR_ICM3_SMI_CTRL_BASE), .length = SZ_16M, .type = MT_DEVICE @@ -378,7 +379,7 @@ void __init spear6xx_timer_init(void) char pclk_name[] = "pll3_clk"; struct clk *gpt_clk, *pclk; - spear6xx_clk_init(); + spear6xx_clk_init(MISC_BASE); /* get the system timer clock */ gpt_clk = clk_get_sys("gpt0", NULL); -- cgit v1.1 From 553e7f75a171654d032d0eacbb1ba75bd9be7e8a Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Thu, 6 Dec 2012 14:48:28 +0100 Subject: ARM: spear: rename duplicate pl080_plat_data Both spear3xx and spear6xx have a global symbol named pl080_plat_data. Eventually, both should be removed, but for now, we can rename one to pl080_plat_data and declare it static, since that one does not actually need to be visible outside of spear6xx.c. Signed-off-by: Arnd Bergmann Acked-by: Viresh Kumar --- arch/arm/mach-spear/spear6xx.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-spear/spear6xx.c b/arch/arm/mach-spear/spear6xx.c index 9b5ea25..ec8eefb 100644 --- a/arch/arm/mach-spear/spear6xx.c +++ b/arch/arm/mach-spear/spear6xx.c @@ -322,7 +322,7 @@ static struct pl08x_channel_data spear600_dma_info[] = { }, }; -struct pl08x_platform_data pl080_plat_data = { +static struct pl08x_platform_data spear6xx_pl080_plat_data = { .memcpy_channel = { .bus_id = "memcpy", .cctl_memcpy = @@ -406,7 +406,7 @@ void __init spear6xx_timer_init(void) /* Add auxdata to pass platform data */ struct of_dev_auxdata spear6xx_auxdata_lookup[] __initdata = { OF_DEV_AUXDATA("arm,pl080", SPEAR_ICM3_DMA_BASE, NULL, - &pl080_plat_data), + &spear6xx_pl080_plat_data), {} }; -- cgit v1.1 From 5b65fc560398dd849dbe9f0df68d3934089c894a Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Thu, 6 Dec 2012 14:51:56 +0100 Subject: ARM: spear: use multiplatform configuration options. The spear platform is now multiplatform capable in principle, and everything still builds when enabled. This slightly rearranges the Kconfig options for spear to enable both single- and multiplatform support. As a side-effect, even building the single spear kernel can now enable spear3xx and spear6xx simultaneously, although not together with spear13xx, because they are a different archicture version (v7 instead of v5). Signed-off-by: Arnd Bergmann Acked-by: Viresh Kumar --- arch/arm/Kconfig | 10 +----- arch/arm/configs/spear3xx_defconfig | 2 ++ arch/arm/configs/spear6xx_defconfig | 1 + arch/arm/mach-spear/Kconfig | 67 ++++++++++++++++++++++--------------- arch/arm/mach-spear/Makefile | 2 ++ 5 files changed, 46 insertions(+), 36 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 4d2b1cf..4b82c7b 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -933,16 +933,8 @@ config ARCH_NOMADIK help Support for the Nomadik platform by ST-Ericsson -config PLAT_SPEAR +config PLAT_SPEAR_SINGLE bool "ST SPEAr" - select ARCH_HAS_CPUFREQ - select ARCH_REQUIRE_GPIOLIB - select ARM_AMBA - select CLKDEV_LOOKUP - select CLKSRC_MMIO - select COMMON_CLK - select GENERIC_CLOCKEVENTS - select HAVE_CLK help Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx). diff --git a/arch/arm/configs/spear3xx_defconfig b/arch/arm/configs/spear3xx_defconfig index 865980c..7ff23a0 100644 --- a/arch/arm/configs/spear3xx_defconfig +++ b/arch/arm/configs/spear3xx_defconfig @@ -6,7 +6,9 @@ CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y CONFIG_MODVERSIONS=y CONFIG_PARTITION_ADVANCED=y +# CONFIG_ARCH_MULTI_V7 is not set CONFIG_PLAT_SPEAR=y +CONFIG_ARCH_SPEAR3XX=y CONFIG_MACH_SPEAR300=y CONFIG_MACH_SPEAR310=y CONFIG_MACH_SPEAR320=y diff --git a/arch/arm/configs/spear6xx_defconfig b/arch/arm/configs/spear6xx_defconfig index a2a1265..7822980 100644 --- a/arch/arm/configs/spear6xx_defconfig +++ b/arch/arm/configs/spear6xx_defconfig @@ -6,6 +6,7 @@ CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y CONFIG_MODVERSIONS=y CONFIG_PARTITION_ADVANCED=y +# CONFIG_ARCH_MULTI_V7 is not set CONFIG_PLAT_SPEAR=y CONFIG_ARCH_SPEAR6XX=y CONFIG_BINFMT_MISC=y diff --git a/arch/arm/mach-spear/Kconfig b/arch/arm/mach-spear/Kconfig index e288df9..4c52ee2 100644 --- a/arch/arm/mach-spear/Kconfig +++ b/arch/arm/mach-spear/Kconfig @@ -2,14 +2,22 @@ # SPEAr Platform configuration file # -if PLAT_SPEAR +menuconfig PLAT_SPEAR + bool "ST SPEAr Family" if ARCH_MULTI_V7 || ARCH_MULTI_V5 + default PLAT_SPEAR_SINGLE + select ARCH_REQUIRE_GPIOLIB + select ARM_AMBA + select CLKDEV_LOOKUP + select CLKSRC_MMIO + select COMMON_CLK + select GENERIC_CLOCKEVENTS + select HAVE_CLK -choice - prompt "ST SPEAr Family" - default ARCH_SPEAR3XX +if PLAT_SPEAR config ARCH_SPEAR13XX - bool "ST SPEAr13xx with Device Tree" + bool "ST SPEAr13xx" + depends on ARCH_MULTI_V7 || PLAT_SPEAR_SINGLE select ARCH_HAVE_CPUFREQ select ARM_GIC select CPU_V7 @@ -21,27 +29,8 @@ config ARCH_SPEAR13XX help Supports for ARM's SPEAR13XX family -config ARCH_SPEAR3XX - bool "ST SPEAr3xx with Device Tree" - select ARM_VIC - select CPU_ARM926T - select PINCTRL - select USE_OF - help - Supports for ARM's SPEAR3XX family - -config ARCH_SPEAR6XX - bool "SPEAr6XX" - select ARM_VIC - select CPU_ARM926T - help - Supports for ARM's SPEAR6XX family - -endchoice - if ARCH_SPEAR13XX -menu "SPEAr13xx Implementations" config MACH_SPEAR1310 bool "SPEAr1310 Machine support with Device Tree" select PINCTRL_SPEAR1310 @@ -53,12 +42,22 @@ config MACH_SPEAR1340 select PINCTRL_SPEAR1340 help Supports ST SPEAr1340 machine configured via the device-tree -endmenu + endif #ARCH_SPEAR13XX +config ARCH_SPEAR3XX + bool "ST SPEAr3xx" + depends on ARCH_MULTI_V5 || PLAT_SPEAR_SINGLE + depends on !ARCH_SPEAR13XX + select ARM_VIC + select CPU_ARM926T + select PINCTRL + select USE_OF + help + Supports for ARM's SPEAR3XX family + if ARCH_SPEAR3XX -menu "SPEAr3xx Implementations" config MACH_SPEAR300 bool "SPEAr300 Machine support with Device Tree" select PINCTRL_SPEAR300 @@ -76,10 +75,18 @@ config MACH_SPEAR320 select PINCTRL_SPEAR320 help Supports ST SPEAr320 machine configured via the device-tree -endmenu endif +config ARCH_SPEAR6XX + bool "ST SPEAr6XX" + depends on ARCH_MULTI_V5 || PLAT_SPEAR_SINGLE + depends on !ARCH_SPEAR13XX + select ARM_VIC + select CPU_ARM926T + help + Supports for ARM's SPEAR6XX family + config MACH_SPEAR600 def_bool y depends on ARCH_SPEAR6XX @@ -87,4 +94,10 @@ config MACH_SPEAR600 help Supports ST SPEAr600 boards configured via the device-treesource "arch/arm/mach-spear6xx/Kconfig" +config ARCH_SPEAR_AUTO + def_bool PLAT_SPEAR_SINGLE + depends on !ARCH_SPEAR13XX && !ARCH_SPEAR6XX + select ARCH_SPEAR3XX + endif + diff --git a/arch/arm/mach-spear/Makefile b/arch/arm/mach-spear/Makefile index 8a937bf..dc9ce80 100644 --- a/arch/arm/mach-spear/Makefile +++ b/arch/arm/mach-spear/Makefile @@ -2,6 +2,8 @@ # SPEAr Platform specific Makefile # +ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include + # Common support obj-y := restart.o time.o -- cgit v1.1 From af63275bc4da161f4c78c8ddcddc9f90c2d2d194 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Fri, 25 Jan 2013 23:09:57 +0000 Subject: ARM: spear: fix build error in restart.c We can now enable mach-spear without selecting any of the machines in a multiplatform configuration. Doing so causes a build error that is trivial to fix by making both the spear13xx and the spear3xx/6xx portion of this file conditional rather than alternatives. Signed-off-by: Arnd Bergmann Acked-by: Viresh Kumar --- arch/arm/mach-spear/restart.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-spear/restart.c b/arch/arm/mach-spear/restart.c index 004f0f2..2b44500 100644 --- a/arch/arm/mach-spear/restart.c +++ b/arch/arm/mach-spear/restart.c @@ -26,7 +26,8 @@ void spear_restart(char mode, const char *cmd) /* hardware reset, Use on-chip reset capability */ #ifdef CONFIG_ARCH_SPEAR13XX writel_relaxed(0x01, SPEAR13XX_SYS_SW_RES); -#else +#endif +#if defined(CONFIG_ARCH_SPEAR3XX) || defined(CONFIG_ARCH_SPEAR6XX) sysctl_soft_reset((void __iomem *)VA_SPEAR_SYS_CTRL_BASE); #endif } -- cgit v1.1 From bcf3e72eff584136600a51a5b30ef7a794664d19 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Tue, 12 Mar 2013 17:32:16 +0100 Subject: ARM: spear: enable spear13xx in multi_v7_defconfig SPEAr13xx can now be part of the regular multiplatform defconfig, so let's enable it there. Signed-off-by: Arnd Bergmann --- arch/arm/configs/multi_v7_defconfig | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig index e31d442..3bf0c54 100644 --- a/arch/arm/configs/multi_v7_defconfig +++ b/arch/arm/configs/multi_v7_defconfig @@ -10,6 +10,10 @@ CONFIG_ARCH_SUNXI=y # CONFIG_ARCH_VEXPRESS_CORTEX_A5_A9_ERRATA is not set CONFIG_ARCH_ZYNQ=y CONFIG_ARM_ERRATA_754322=y +CONFIG_PLAT_SPEAR=y +CONFIG_ARCH_SPEAR13XX=y +CONFIG_MACH_SPEAR1310=y +CONFIG_MACH_SPEAR1340=y CONFIG_SMP=y CONFIG_ARM_ARCH_TIMER=y CONFIG_AEABI=y @@ -23,6 +27,7 @@ CONFIG_BLK_DEV_SD=y CONFIG_ATA=y CONFIG_SATA_HIGHBANK=y CONFIG_SATA_MV=y +CONFIG_SATA_AHCI_PLATFORM=y CONFIG_NETDEVICES=y CONFIG_NET_CALXEDA_XGMAC=y CONFIG_SMSC911X=y @@ -31,6 +36,7 @@ CONFIG_SERIO_AMBAKMI=y CONFIG_SERIAL_8250=y CONFIG_SERIAL_8250_CONSOLE=y CONFIG_SERIAL_8250_DW=y +CONFIG_KEYBOARD_SPEAR=y CONFIG_SERIAL_AMBA_PL011=y CONFIG_SERIAL_AMBA_PL011_CONSOLE=y CONFIG_SERIAL_OF_PLATFORM=y @@ -40,6 +46,7 @@ CONFIG_I2C=y CONFIG_I2C_DESIGNWARE_PLATFORM=y CONFIG_SPI=y CONFIG_SPI_PL022=y +CONFIG_GPIO_PL061=y CONFIG_FB=y CONFIG_FB_ARMCLCD=y CONFIG_FRAMEBUFFER_CONSOLE=y @@ -50,6 +57,7 @@ CONFIG_MMC=y CONFIG_MMC_ARMMMCI=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_PLTFM=y +CONFIG_MMC_SDHCI_SPEAR=y CONFIG_EDAC=y CONFIG_EDAC_MM_EDAC=y CONFIG_EDAC_HIGHBANK_MC=y @@ -58,3 +66,4 @@ CONFIG_RTC_CLASS=y CONFIG_RTC_DRV_PL031=y CONFIG_DMADEVICES=y CONFIG_PL330_DMA=y +CONFIG_DW_DMAC=y -- cgit v1.1 From f1ac922dec7ed36659344eadc65b9c06efe14d7f Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Mon, 11 Mar 2013 22:40:18 -0600 Subject: ARM: bcm2835: convert to multi-platform This allows BCM2835 be included in a kernel build that supports multiple SoCs at once, which is useful for distro kernels. This change: * Moves bcm2835's debug-macro.S into ARM's include/debug/, and hooks it into the relevant menu. * Moves bcm2835's Kconfig into its own directory, as seems typical for multi-platform conversions. * Removes bcm2835_soc.h, and moves the content to the files where it was used; just one usage per define. * Deletes some headers and Makefile.boot that aren't needed now that we support multi-platform. Signed-off-by: Stephen Warren Acked-by: Arnd Bergmann --- arch/arm/Kconfig | 22 ++---------- arch/arm/Kconfig.debug | 5 +++ arch/arm/configs/bcm2835_defconfig | 2 ++ arch/arm/include/debug/bcm2835.S | 22 ++++++++++++ arch/arm/mach-bcm2835/Kconfig | 15 ++++++++ arch/arm/mach-bcm2835/Makefile.boot | 1 - arch/arm/mach-bcm2835/bcm2835.c | 6 ++-- arch/arm/mach-bcm2835/include/mach/bcm2835_soc.h | 29 ---------------- arch/arm/mach-bcm2835/include/mach/debug-macro.S | 21 ----------- arch/arm/mach-bcm2835/include/mach/gpio.h | 1 - arch/arm/mach-bcm2835/include/mach/timex.h | 26 -------------- arch/arm/mach-bcm2835/include/mach/uncompress.h | 44 ------------------------ 12 files changed, 50 insertions(+), 144 deletions(-) create mode 100644 arch/arm/include/debug/bcm2835.S create mode 100644 arch/arm/mach-bcm2835/Kconfig delete mode 100644 arch/arm/mach-bcm2835/Makefile.boot delete mode 100644 arch/arm/mach-bcm2835/include/mach/bcm2835_soc.h delete mode 100644 arch/arm/mach-bcm2835/include/mach/debug-macro.S delete mode 100644 arch/arm/mach-bcm2835/include/mach/gpio.h delete mode 100644 arch/arm/mach-bcm2835/include/mach/timex.h delete mode 100644 arch/arm/mach-bcm2835/include/mach/uncompress.h (limited to 'arch/arm') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 5b71469..0d3daa6 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -362,26 +362,6 @@ config ARCH_AT91 This enables support for systems based on Atmel AT91RM9200 and AT91SAM9* processors. -config ARCH_BCM2835 - bool "Broadcom BCM2835 family" - select ARCH_REQUIRE_GPIOLIB - select ARM_AMBA - select ARM_ERRATA_411920 - select ARM_TIMER_SP804 - select CLKDEV_LOOKUP - select CLKSRC_OF - select COMMON_CLK - select CPU_V6 - select GENERIC_CLOCKEVENTS - select MULTI_IRQ_HANDLER - select PINCTRL - select PINCTRL_BCM2835 - select SPARSE_IRQ - select USE_OF - help - This enables support for the Broadcom BCM2835 SoC. This SoC is - use in the Raspberry Pi, and Roku 2 devices. - config ARCH_CNS3XXX bool "Cavium Networks CNS3XXX family" select ARM_GIC @@ -1037,6 +1017,8 @@ source "arch/arm/mach-at91/Kconfig" source "arch/arm/mach-bcm/Kconfig" +source "arch/arm/mach-bcm2835/Kconfig" + source "arch/arm/mach-clps711x/Kconfig" source "arch/arm/mach-cns3xxx/Kconfig" diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug index acdddda..a877d51 100644 --- a/arch/arm/Kconfig.debug +++ b/arch/arm/Kconfig.debug @@ -89,6 +89,10 @@ choice bool "Kernel low-level debugging on 9263 and 9g45" depends on HAVE_AT91_DBGU1 + config DEBUG_BCM2835 + bool "Kernel low-level debugging on BCM2835 PL011 UART" + depends on ARCH_BCM2835 + config DEBUG_CLPS711X_UART1 bool "Kernel low-level debugging messages via UART1" depends on ARCH_CLPS711X @@ -579,6 +583,7 @@ endchoice config DEBUG_LL_INCLUDE string + default "debug/bcm2835.S" if DEBUG_BCM2835 default "debug/icedcc.S" if DEBUG_ICEDCC default "debug/imx.S" if DEBUG_IMX1_UART || \ DEBUG_IMX25_UART || \ diff --git a/arch/arm/configs/bcm2835_defconfig b/arch/arm/configs/bcm2835_defconfig index af472e4..3a1c939 100644 --- a/arch/arm/configs/bcm2835_defconfig +++ b/arch/arm/configs/bcm2835_defconfig @@ -29,6 +29,8 @@ CONFIG_EMBEDDED=y CONFIG_PROFILING=y CONFIG_OPROFILE=y CONFIG_JUMP_LABEL=y +CONFIG_ARCH_MULTI_V6=y +# CONFIG_ARCH_MULTI_V7 is not set CONFIG_ARCH_BCM2835=y CONFIG_PREEMPT_VOLUNTARY=y CONFIG_AEABI=y diff --git a/arch/arm/include/debug/bcm2835.S b/arch/arm/include/debug/bcm2835.S new file mode 100644 index 0000000..aed9199 --- /dev/null +++ b/arch/arm/include/debug/bcm2835.S @@ -0,0 +1,22 @@ +/* + * Debugging macro include header + * + * Copyright (C) 2010 Broadcom + * Copyright (C) 1994-1999 Russell King + * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#define BCM2835_DEBUG_PHYS 0x20201000 +#define BCM2835_DEBUG_VIRT 0xf0201000 + + .macro addruart, rp, rv, tmp + ldr \rp, =BCM2835_DEBUG_PHYS + ldr \rv, =BCM2835_DEBUG_VIRT + .endm + +#include diff --git a/arch/arm/mach-bcm2835/Kconfig b/arch/arm/mach-bcm2835/Kconfig new file mode 100644 index 0000000..560045c --- /dev/null +++ b/arch/arm/mach-bcm2835/Kconfig @@ -0,0 +1,15 @@ +config ARCH_BCM2835 + bool "Broadcom BCM2835 family" if ARCH_MULTI_V6 + select ARCH_REQUIRE_GPIOLIB + select ARM_AMBA + select ARM_ERRATA_411920 + select ARM_TIMER_SP804 + select CLKDEV_LOOKUP + select CLKSRC_OF + select CPU_V6 + select GENERIC_CLOCKEVENTS + select PINCTRL + select PINCTRL_BCM2835 + help + This enables support for the Broadcom BCM2835 SoC. This SoC is + use in the Raspberry Pi, and Roku 2 devices. diff --git a/arch/arm/mach-bcm2835/Makefile.boot b/arch/arm/mach-bcm2835/Makefile.boot deleted file mode 100644 index b327175..0000000 --- a/arch/arm/mach-bcm2835/Makefile.boot +++ /dev/null @@ -1 +0,0 @@ -zreladdr-y := 0x00008000 diff --git a/arch/arm/mach-bcm2835/bcm2835.c b/arch/arm/mach-bcm2835/bcm2835.c index 6f57859..740fa9e 100644 --- a/arch/arm/mach-bcm2835/bcm2835.c +++ b/arch/arm/mach-bcm2835/bcm2835.c @@ -23,8 +23,6 @@ #include #include -#include - #define PM_RSTC 0x1c #define PM_RSTS 0x20 #define PM_WDOG 0x24 @@ -34,6 +32,10 @@ #define PM_RSTC_WRCFG_FULL_RESET 0x00000020 #define PM_RSTS_HADWRH_SET 0x00000040 +#define BCM2835_PERIPH_PHYS 0x20000000 +#define BCM2835_PERIPH_VIRT 0xf0000000 +#define BCM2835_PERIPH_SIZE SZ_16M + static void __iomem *wdt_regs; /* diff --git a/arch/arm/mach-bcm2835/include/mach/bcm2835_soc.h b/arch/arm/mach-bcm2835/include/mach/bcm2835_soc.h deleted file mode 100644 index d4dfcf7..0000000 --- a/arch/arm/mach-bcm2835/include/mach/bcm2835_soc.h +++ /dev/null @@ -1,29 +0,0 @@ -/* - * Copyright (C) 2012 Stephen Warren - * - * Derived from code: - * Copyright (C) 2010 Broadcom - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __MACH_BCM2835_BCM2835_SOC_H__ -#define __MACH_BCM2835_BCM2835_SOC_H__ - -#include - -#define BCM2835_PERIPH_PHYS 0x20000000 -#define BCM2835_PERIPH_VIRT 0xf0000000 -#define BCM2835_PERIPH_SIZE SZ_16M -#define BCM2835_DEBUG_PHYS 0x20201000 -#define BCM2835_DEBUG_VIRT 0xf0201000 - -#endif diff --git a/arch/arm/mach-bcm2835/include/mach/debug-macro.S b/arch/arm/mach-bcm2835/include/mach/debug-macro.S deleted file mode 100644 index 8a161e4..0000000 --- a/arch/arm/mach-bcm2835/include/mach/debug-macro.S +++ /dev/null @@ -1,21 +0,0 @@ -/* - * Debugging macro include header - * - * Copyright (C) 2010 Broadcom - * Copyright (C) 1994-1999 Russell King - * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - */ - -#include - - .macro addruart, rp, rv, tmp - ldr \rp, =BCM2835_DEBUG_PHYS - ldr \rv, =BCM2835_DEBUG_VIRT - .endm - -#include diff --git a/arch/arm/mach-bcm2835/include/mach/gpio.h b/arch/arm/mach-bcm2835/include/mach/gpio.h deleted file mode 100644 index 40a8c17..0000000 --- a/arch/arm/mach-bcm2835/include/mach/gpio.h +++ /dev/null @@ -1 +0,0 @@ -/* empty */ diff --git a/arch/arm/mach-bcm2835/include/mach/timex.h b/arch/arm/mach-bcm2835/include/mach/timex.h deleted file mode 100644 index 6d021e1..0000000 --- a/arch/arm/mach-bcm2835/include/mach/timex.h +++ /dev/null @@ -1,26 +0,0 @@ -/* - * BCM2835 system clock frequency - * - * Copyright (C) 2010 Broadcom - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ - -#ifndef __ASM_ARCH_TIMEX_H -#define __ASM_ARCH_TIMEX_H - -#define CLOCK_TICK_RATE (1000000) - -#endif diff --git a/arch/arm/mach-bcm2835/include/mach/uncompress.h b/arch/arm/mach-bcm2835/include/mach/uncompress.h deleted file mode 100644 index bf86dca..0000000 --- a/arch/arm/mach-bcm2835/include/mach/uncompress.h +++ /dev/null @@ -1,44 +0,0 @@ -/* - * Copyright (C) 2010 Broadcom - * Copyright (C) 2003 ARM Limited - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include - -#define UART0_BASE BCM2835_DEBUG_PHYS - -#define BCM2835_UART_DR IOMEM(UART0_BASE + UART01x_DR) -#define BCM2835_UART_FR IOMEM(UART0_BASE + UART01x_FR) -#define BCM2835_UART_CR IOMEM(UART0_BASE + UART011_CR) - -static inline void putc(int c) -{ - while (__raw_readl(BCM2835_UART_FR) & UART01x_FR_TXFF) - barrier(); - - __raw_writel(c, BCM2835_UART_DR); -} - -static inline void flush(void) -{ - int fr; - - do { - fr = __raw_readl(BCM2835_UART_FR); - barrier(); - } while ((fr & (UART011_FR_TXFE | UART01x_FR_BUSY)) != UART011_FR_TXFE); -} - -#define arch_decomp_setup() -- cgit v1.1 From 3f9fb2a08f55c79b4c6cde423c1e8ddcc5a49781 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Wed, 13 Mar 2013 13:15:25 +0100 Subject: ARM: cns3xxx: make mach header files local The mach/cns3xxx.h and mach/pm.h header files are used only in the platform code itself, so there is no need to make them globally visible. This gets us closer to multiplatform configuration for cns3xxx. Signed-off-by: Arnd Bergmann --- arch/arm/mach-cns3xxx/cns3420vb.c | 5 +- arch/arm/mach-cns3xxx/cns3xxx.h | 629 +++++++++++++++++++++++ arch/arm/mach-cns3xxx/core.c | 2 +- arch/arm/mach-cns3xxx/devices.c | 5 +- arch/arm/mach-cns3xxx/include/mach/cns3xxx.h | 632 ------------------------ arch/arm/mach-cns3xxx/include/mach/pm.h | 23 - arch/arm/mach-cns3xxx/include/mach/uncompress.h | 2 +- arch/arm/mach-cns3xxx/pcie.c | 2 +- arch/arm/mach-cns3xxx/pm.c | 4 +- arch/arm/mach-cns3xxx/pm.h | 23 + 10 files changed, 661 insertions(+), 666 deletions(-) create mode 100644 arch/arm/mach-cns3xxx/cns3xxx.h delete mode 100644 arch/arm/mach-cns3xxx/include/mach/cns3xxx.h delete mode 100644 arch/arm/mach-cns3xxx/include/mach/pm.h create mode 100644 arch/arm/mach-cns3xxx/pm.h (limited to 'arch/arm') diff --git a/arch/arm/mach-cns3xxx/cns3420vb.c b/arch/arm/mach-cns3xxx/cns3420vb.c index a71867e..d863d87 100644 --- a/arch/arm/mach-cns3xxx/cns3420vb.c +++ b/arch/arm/mach-cns3xxx/cns3420vb.c @@ -31,9 +31,8 @@ #include #include #include -#include -#include -#include +#include "cns3xxx.h" +#include "pm.h" #include "core.h" #include "devices.h" diff --git a/arch/arm/mach-cns3xxx/cns3xxx.h b/arch/arm/mach-cns3xxx/cns3xxx.h new file mode 100644 index 0000000..d7d3a8d --- /dev/null +++ b/arch/arm/mach-cns3xxx/cns3xxx.h @@ -0,0 +1,629 @@ +/* + * Copyright 2008 Cavium Networks + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + */ + +#ifndef __MACH_BOARD_CNS3XXXH +#define __MACH_BOARD_CNS3XXXH + +/* + * Memory map + */ +#define CNS3XXX_FLASH_BASE 0x10000000 /* Flash/SRAM Memory Bank 0 */ +#define CNS3XXX_FLASH_SIZE SZ_256M + +#define CNS3XXX_DDR2SDRAM_BASE 0x20000000 /* DDR2 SDRAM Memory */ + +#define CNS3XXX_SPI_FLASH_BASE 0x60000000 /* SPI Serial Flash Memory */ + +#define CNS3XXX_SWITCH_BASE 0x70000000 /* Switch and HNAT Control */ +#define CNS3XXX_SWITCH_BASE_VIRT 0xFFF00000 + +#define CNS3XXX_PPE_BASE 0x70001000 /* HANT */ +#define CNS3XXX_PPE_BASE_VIRT 0xFFF50000 + +#define CNS3XXX_EMBEDDED_SRAM_BASE 0x70002000 /* HANT Embedded SRAM */ +#define CNS3XXX_EMBEDDED_SRAM_BASE_VIRT 0xFFF60000 + +#define CNS3XXX_SSP_BASE 0x71000000 /* Synchronous Serial Port - SPI/PCM/I2C */ +#define CNS3XXX_SSP_BASE_VIRT 0xFFF01000 + +#define CNS3XXX_DMC_BASE 0x72000000 /* DMC Control (DDR2 SDRAM) */ +#define CNS3XXX_DMC_BASE_VIRT 0xFFF02000 + +#define CNS3XXX_SMC_BASE 0x73000000 /* SMC Control */ +#define CNS3XXX_SMC_BASE_VIRT 0xFFF03000 + +#define SMC_MEMC_STATUS_OFFSET 0x000 +#define SMC_MEMIF_CFG_OFFSET 0x004 +#define SMC_MEMC_CFG_SET_OFFSET 0x008 +#define SMC_MEMC_CFG_CLR_OFFSET 0x00C +#define SMC_DIRECT_CMD_OFFSET 0x010 +#define SMC_SET_CYCLES_OFFSET 0x014 +#define SMC_SET_OPMODE_OFFSET 0x018 +#define SMC_REFRESH_PERIOD_0_OFFSET 0x020 +#define SMC_REFRESH_PERIOD_1_OFFSET 0x024 +#define SMC_SRAM_CYCLES0_0_OFFSET 0x100 +#define SMC_NAND_CYCLES0_0_OFFSET 0x100 +#define SMC_OPMODE0_0_OFFSET 0x104 +#define SMC_SRAM_CYCLES0_1_OFFSET 0x120 +#define SMC_NAND_CYCLES0_1_OFFSET 0x120 +#define SMC_OPMODE0_1_OFFSET 0x124 +#define SMC_USER_STATUS_OFFSET 0x200 +#define SMC_USER_CONFIG_OFFSET 0x204 +#define SMC_ECC_STATUS_OFFSET 0x300 +#define SMC_ECC_MEMCFG_OFFSET 0x304 +#define SMC_ECC_MEMCOMMAND1_OFFSET 0x308 +#define SMC_ECC_MEMCOMMAND2_OFFSET 0x30C +#define SMC_ECC_ADDR0_OFFSET 0x310 +#define SMC_ECC_ADDR1_OFFSET 0x314 +#define SMC_ECC_VALUE0_OFFSET 0x318 +#define SMC_ECC_VALUE1_OFFSET 0x31C +#define SMC_ECC_VALUE2_OFFSET 0x320 +#define SMC_ECC_VALUE3_OFFSET 0x324 +#define SMC_PERIPH_ID_0_OFFSET 0xFE0 +#define SMC_PERIPH_ID_1_OFFSET 0xFE4 +#define SMC_PERIPH_ID_2_OFFSET 0xFE8 +#define SMC_PERIPH_ID_3_OFFSET 0xFEC +#define SMC_PCELL_ID_0_OFFSET 0xFF0 +#define SMC_PCELL_ID_1_OFFSET 0xFF4 +#define SMC_PCELL_ID_2_OFFSET 0xFF8 +#define SMC_PCELL_ID_3_OFFSET 0xFFC + +#define CNS3XXX_GPIOA_BASE 0x74000000 /* GPIO port A */ +#define CNS3XXX_GPIOA_BASE_VIRT 0xFFF04000 + +#define CNS3XXX_GPIOB_BASE 0x74800000 /* GPIO port B */ +#define CNS3XXX_GPIOB_BASE_VIRT 0xFFF05000 + +#define CNS3XXX_RTC_BASE 0x75000000 /* Real Time Clock */ +#define CNS3XXX_RTC_BASE_VIRT 0xFFF06000 + +#define RTC_SEC_OFFSET 0x00 +#define RTC_MIN_OFFSET 0x04 +#define RTC_HOUR_OFFSET 0x08 +#define RTC_DAY_OFFSET 0x0C +#define RTC_SEC_ALM_OFFSET 0x10 +#define RTC_MIN_ALM_OFFSET 0x14 +#define RTC_HOUR_ALM_OFFSET 0x18 +#define RTC_REC_OFFSET 0x1C +#define RTC_CTRL_OFFSET 0x20 +#define RTC_INTR_STS_OFFSET 0x34 + +#define CNS3XXX_MISC_BASE 0x76000000 /* Misc Control */ +#define CNS3XXX_MISC_BASE_VIRT 0xFFF07000 /* Misc Control */ + +#define CNS3XXX_PM_BASE 0x77000000 /* Power Management Control */ +#define CNS3XXX_PM_BASE_VIRT 0xFFF08000 + +#define PM_CLK_GATE_OFFSET 0x00 +#define PM_SOFT_RST_OFFSET 0x04 +#define PM_HS_CFG_OFFSET 0x08 +#define PM_CACTIVE_STA_OFFSET 0x0C +#define PM_PWR_STA_OFFSET 0x10 +#define PM_SYS_CLK_CTRL_OFFSET 0x14 +#define PM_PLL_LCD_I2S_CTRL_OFFSET 0x18 +#define PM_PLL_HM_PD_OFFSET 0x1C + +#define CNS3XXX_UART0_BASE 0x78000000 /* UART 0 */ +#define CNS3XXX_UART0_BASE_VIRT 0xFFF09000 + +#define CNS3XXX_UART1_BASE 0x78400000 /* UART 1 */ +#define CNS3XXX_UART1_BASE_VIRT 0xFFF0A000 + +#define CNS3XXX_UART2_BASE 0x78800000 /* UART 2 */ +#define CNS3XXX_UART2_BASE_VIRT 0xFFF0B000 + +#define CNS3XXX_DMAC_BASE 0x79000000 /* Generic DMA Control */ +#define CNS3XXX_DMAC_BASE_VIRT 0xFFF0D000 + +#define CNS3XXX_CORESIGHT_BASE 0x7A000000 /* CoreSight */ +#define CNS3XXX_CORESIGHT_BASE_VIRT 0xFFF0E000 + +#define CNS3XXX_CRYPTO_BASE 0x7B000000 /* Crypto */ +#define CNS3XXX_CRYPTO_BASE_VIRT 0xFFF0F000 + +#define CNS3XXX_I2S_BASE 0x7C000000 /* I2S */ +#define CNS3XXX_I2S_BASE_VIRT 0xFFF10000 + +#define CNS3XXX_TIMER1_2_3_BASE 0x7C800000 /* Timer */ +#define CNS3XXX_TIMER1_2_3_BASE_VIRT 0xFFF10800 + +#define TIMER1_COUNTER_OFFSET 0x00 +#define TIMER1_AUTO_RELOAD_OFFSET 0x04 +#define TIMER1_MATCH_V1_OFFSET 0x08 +#define TIMER1_MATCH_V2_OFFSET 0x0C + +#define TIMER2_COUNTER_OFFSET 0x10 +#define TIMER2_AUTO_RELOAD_OFFSET 0x14 +#define TIMER2_MATCH_V1_OFFSET 0x18 +#define TIMER2_MATCH_V2_OFFSET 0x1C + +#define TIMER1_2_CONTROL_OFFSET 0x30 +#define TIMER1_2_INTERRUPT_STATUS_OFFSET 0x34 +#define TIMER1_2_INTERRUPT_MASK_OFFSET 0x38 + +#define TIMER_FREERUN_OFFSET 0x40 +#define TIMER_FREERUN_CONTROL_OFFSET 0x44 + +#define CNS3XXX_HCIE_BASE 0x7D000000 /* HCIE Control */ +#define CNS3XXX_HCIE_BASE_VIRT 0xFFF30000 + +#define CNS3XXX_RAID_BASE 0x7E000000 /* RAID Control */ +#define CNS3XXX_RAID_BASE_VIRT 0xFFF12000 + +#define CNS3XXX_AXI_IXC_BASE 0x7F000000 /* AXI IXC */ +#define CNS3XXX_AXI_IXC_BASE_VIRT 0xFFF13000 + +#define CNS3XXX_CLCD_BASE 0x80000000 /* LCD Control */ +#define CNS3XXX_CLCD_BASE_VIRT 0xFFF14000 + +#define CNS3XXX_USBOTG_BASE 0x81000000 /* USB OTG Control */ +#define CNS3XXX_USBOTG_BASE_VIRT 0xFFF15000 + +#define CNS3XXX_USB_BASE 0x82000000 /* USB Host Control */ + +#define CNS3XXX_SATA2_BASE 0x83000000 /* SATA */ +#define CNS3XXX_SATA2_SIZE SZ_16M +#define CNS3XXX_SATA2_BASE_VIRT 0xFFF17000 + +#define CNS3XXX_CAMERA_BASE 0x84000000 /* Camera Interface */ +#define CNS3XXX_CAMERA_BASE_VIRT 0xFFF18000 + +#define CNS3XXX_SDIO_BASE 0x85000000 /* SDIO */ +#define CNS3XXX_SDIO_BASE_VIRT 0xFFF19000 + +#define CNS3XXX_I2S_TDM_BASE 0x86000000 /* I2S TDM */ +#define CNS3XXX_I2S_TDM_BASE_VIRT 0xFFF1A000 + +#define CNS3XXX_2DG_BASE 0x87000000 /* 2D Graphic Control */ +#define CNS3XXX_2DG_BASE_VIRT 0xFFF1B000 + +#define CNS3XXX_USB_OHCI_BASE 0x88000000 /* USB OHCI */ + +#define CNS3XXX_L2C_BASE 0x92000000 /* L2 Cache Control */ +#define CNS3XXX_L2C_BASE_VIRT 0xFFF27000 + +#define CNS3XXX_PCIE0_MEM_BASE 0xA0000000 /* PCIe Port 0 IO/Memory Space */ +#define CNS3XXX_PCIE0_MEM_BASE_VIRT 0xE0000000 + +#define CNS3XXX_PCIE0_HOST_BASE 0xAB000000 /* PCIe Port 0 RC Base */ +#define CNS3XXX_PCIE0_HOST_BASE_VIRT 0xE1000000 + +#define CNS3XXX_PCIE0_IO_BASE 0xAC000000 /* PCIe Port 0 */ +#define CNS3XXX_PCIE0_IO_BASE_VIRT 0xE2000000 + +#define CNS3XXX_PCIE0_CFG0_BASE 0xAD000000 /* PCIe Port 0 CFG Type 0 */ +#define CNS3XXX_PCIE0_CFG0_BASE_VIRT 0xE3000000 + +#define CNS3XXX_PCIE0_CFG1_BASE 0xAE000000 /* PCIe Port 0 CFG Type 1 */ +#define CNS3XXX_PCIE0_CFG1_BASE_VIRT 0xE4000000 + +#define CNS3XXX_PCIE0_MSG_BASE 0xAF000000 /* PCIe Port 0 Message Space */ +#define CNS3XXX_PCIE0_MSG_BASE_VIRT 0xE5000000 + +#define CNS3XXX_PCIE1_MEM_BASE 0xB0000000 /* PCIe Port 1 IO/Memory Space */ +#define CNS3XXX_PCIE1_MEM_BASE_VIRT 0xE8000000 + +#define CNS3XXX_PCIE1_HOST_BASE 0xBB000000 /* PCIe Port 1 RC Base */ +#define CNS3XXX_PCIE1_HOST_BASE_VIRT 0xE9000000 + +#define CNS3XXX_PCIE1_IO_BASE 0xBC000000 /* PCIe Port 1 */ +#define CNS3XXX_PCIE1_IO_BASE_VIRT 0xEA000000 + +#define CNS3XXX_PCIE1_CFG0_BASE 0xBD000000 /* PCIe Port 1 CFG Type 0 */ +#define CNS3XXX_PCIE1_CFG0_BASE_VIRT 0xEB000000 + +#define CNS3XXX_PCIE1_CFG1_BASE 0xBE000000 /* PCIe Port 1 CFG Type 1 */ +#define CNS3XXX_PCIE1_CFG1_BASE_VIRT 0xEC000000 + +#define CNS3XXX_PCIE1_MSG_BASE 0xBF000000 /* PCIe Port 1 Message Space */ +#define CNS3XXX_PCIE1_MSG_BASE_VIRT 0xED000000 + +/* + * Testchip peripheral and fpga gic regions + */ +#define CNS3XXX_TC11MP_SCU_BASE 0x90000000 /* IRQ, Test chip */ +#define CNS3XXX_TC11MP_SCU_BASE_VIRT 0xFF000000 + +#define CNS3XXX_TC11MP_GIC_CPU_BASE 0x90000100 /* Test chip interrupt controller CPU interface */ +#define CNS3XXX_TC11MP_GIC_CPU_BASE_VIRT 0xFF000100 + +#define CNS3XXX_TC11MP_TWD_BASE 0x90000600 +#define CNS3XXX_TC11MP_TWD_BASE_VIRT 0xFF000600 + +#define CNS3XXX_TC11MP_GIC_DIST_BASE 0x90001000 /* Test chip interrupt controller distributor */ +#define CNS3XXX_TC11MP_GIC_DIST_BASE_VIRT 0xFF001000 + +#define CNS3XXX_TC11MP_L220_BASE 0x92002000 /* L220 registers */ +#define CNS3XXX_TC11MP_L220_BASE_VIRT 0xFF002000 + +/* + * Misc block + */ +#define MISC_MEM_MAP(offs) (void __iomem *)(CNS3XXX_MISC_BASE_VIRT + (offs)) + +#define MISC_MEMORY_REMAP_REG MISC_MEM_MAP(0x00) +#define MISC_CHIP_CONFIG_REG MISC_MEM_MAP(0x04) +#define MISC_DEBUG_PROBE_DATA_REG MISC_MEM_MAP(0x08) +#define MISC_DEBUG_PROBE_SELECTION_REG MISC_MEM_MAP(0x0C) +#define MISC_IO_PIN_FUNC_SELECTION_REG MISC_MEM_MAP(0x10) +#define MISC_GPIOA_PIN_ENABLE_REG MISC_MEM_MAP(0x14) +#define MISC_GPIOB_PIN_ENABLE_REG MISC_MEM_MAP(0x18) +#define MISC_IO_PAD_DRIVE_STRENGTH_CTRL_A MISC_MEM_MAP(0x1C) +#define MISC_IO_PAD_DRIVE_STRENGTH_CTRL_B MISC_MEM_MAP(0x20) +#define MISC_GPIOA_15_0_PULL_CTRL_REG MISC_MEM_MAP(0x24) +#define MISC_GPIOA_16_31_PULL_CTRL_REG MISC_MEM_MAP(0x28) +#define MISC_GPIOB_15_0_PULL_CTRL_REG MISC_MEM_MAP(0x2C) +#define MISC_GPIOB_16_31_PULL_CTRL_REG MISC_MEM_MAP(0x30) +#define MISC_IO_PULL_CTRL_REG MISC_MEM_MAP(0x34) +#define MISC_E_FUSE_31_0_REG MISC_MEM_MAP(0x40) +#define MISC_E_FUSE_63_32_REG MISC_MEM_MAP(0x44) +#define MISC_E_FUSE_95_64_REG MISC_MEM_MAP(0x48) +#define MISC_E_FUSE_127_96_REG MISC_MEM_MAP(0x4C) +#define MISC_SOFTWARE_TEST_1_REG MISC_MEM_MAP(0x50) +#define MISC_SOFTWARE_TEST_2_REG MISC_MEM_MAP(0x54) + +#define MISC_SATA_POWER_MODE MISC_MEM_MAP(0x310) + +#define MISC_USB_CFG_REG MISC_MEM_MAP(0x800) +#define MISC_USB_STS_REG MISC_MEM_MAP(0x804) +#define MISC_USBPHY00_CFG_REG MISC_MEM_MAP(0x808) +#define MISC_USBPHY01_CFG_REG MISC_MEM_MAP(0x80c) +#define MISC_USBPHY10_CFG_REG MISC_MEM_MAP(0x810) +#define MISC_USBPHY11_CFG_REG MISC_MEM_MAP(0x814) + +#define MISC_PCIEPHY_CMCTL(x) MISC_MEM_MAP(0x900 + (x) * 0x004) +#define MISC_PCIEPHY_CTL(x) MISC_MEM_MAP(0x940 + (x) * 0x100) +#define MISC_PCIE_AXIS_AWMISC(x) MISC_MEM_MAP(0x944 + (x) * 0x100) +#define MISC_PCIE_AXIS_ARMISC(x) MISC_MEM_MAP(0x948 + (x) * 0x100) +#define MISC_PCIE_AXIS_RMISC(x) MISC_MEM_MAP(0x94C + (x) * 0x100) +#define MISC_PCIE_AXIS_BMISC(x) MISC_MEM_MAP(0x950 + (x) * 0x100) +#define MISC_PCIE_AXIM_RMISC(x) MISC_MEM_MAP(0x954 + (x) * 0x100) +#define MISC_PCIE_AXIM_BMISC(x) MISC_MEM_MAP(0x958 + (x) * 0x100) +#define MISC_PCIE_CTRL(x) MISC_MEM_MAP(0x95C + (x) * 0x100) +#define MISC_PCIE_PM_DEBUG(x) MISC_MEM_MAP(0x960 + (x) * 0x100) +#define MISC_PCIE_RFC_DEBUG(x) MISC_MEM_MAP(0x964 + (x) * 0x100) +#define MISC_PCIE_CXPL_DEBUGL(x) MISC_MEM_MAP(0x968 + (x) * 0x100) +#define MISC_PCIE_CXPL_DEBUGH(x) MISC_MEM_MAP(0x96C + (x) * 0x100) +#define MISC_PCIE_DIAG_DEBUGH(x) MISC_MEM_MAP(0x970 + (x) * 0x100) +#define MISC_PCIE_W1CLR(x) MISC_MEM_MAP(0x974 + (x) * 0x100) +#define MISC_PCIE_INT_MASK(x) MISC_MEM_MAP(0x978 + (x) * 0x100) +#define MISC_PCIE_INT_STATUS(x) MISC_MEM_MAP(0x97C + (x) * 0x100) + +/* + * Power management and clock control + */ +#define PMU_MEM_MAP(offs) (void __iomem *)(CNS3XXX_PM_BASE_VIRT + (offs)) + +#define PM_CLK_GATE_REG PMU_MEM_MAP(0x000) +#define PM_SOFT_RST_REG PMU_MEM_MAP(0x004) +#define PM_HS_CFG_REG PMU_MEM_MAP(0x008) +#define PM_CACTIVE_STA_REG PMU_MEM_MAP(0x00C) +#define PM_PWR_STA_REG PMU_MEM_MAP(0x010) +#define PM_CLK_CTRL_REG PMU_MEM_MAP(0x014) +#define PM_PLL_LCD_I2S_CTRL_REG PMU_MEM_MAP(0x018) +#define PM_PLL_HM_PD_CTRL_REG PMU_MEM_MAP(0x01C) +#define PM_REGULAT_CTRL_REG PMU_MEM_MAP(0x020) +#define PM_WDT_CTRL_REG PMU_MEM_MAP(0x024) +#define PM_WU_CTRL0_REG PMU_MEM_MAP(0x028) +#define PM_WU_CTRL1_REG PMU_MEM_MAP(0x02C) +#define PM_CSR_REG PMU_MEM_MAP(0x030) + +/* PM_CLK_GATE_REG */ +#define PM_CLK_GATE_REG_OFFSET_SDIO (25) +#define PM_CLK_GATE_REG_OFFSET_GPU (24) +#define PM_CLK_GATE_REG_OFFSET_CIM (23) +#define PM_CLK_GATE_REG_OFFSET_LCDC (22) +#define PM_CLK_GATE_REG_OFFSET_I2S (21) +#define PM_CLK_GATE_REG_OFFSET_RAID (20) +#define PM_CLK_GATE_REG_OFFSET_SATA (19) +#define PM_CLK_GATE_REG_OFFSET_PCIE(x) (17 + (x)) +#define PM_CLK_GATE_REG_OFFSET_USB_HOST (16) +#define PM_CLK_GATE_REG_OFFSET_USB_OTG (15) +#define PM_CLK_GATE_REG_OFFSET_TIMER (14) +#define PM_CLK_GATE_REG_OFFSET_CRYPTO (13) +#define PM_CLK_GATE_REG_OFFSET_HCIE (12) +#define PM_CLK_GATE_REG_OFFSET_SWITCH (11) +#define PM_CLK_GATE_REG_OFFSET_GPIO (10) +#define PM_CLK_GATE_REG_OFFSET_UART3 (9) +#define PM_CLK_GATE_REG_OFFSET_UART2 (8) +#define PM_CLK_GATE_REG_OFFSET_UART1 (7) +#define PM_CLK_GATE_REG_OFFSET_RTC (5) +#define PM_CLK_GATE_REG_OFFSET_GDMA (4) +#define PM_CLK_GATE_REG_OFFSET_SPI_PCM_I2C (3) +#define PM_CLK_GATE_REG_OFFSET_SMC_NFI (1) +#define PM_CLK_GATE_REG_MASK (0x03FFFFBA) + +/* PM_SOFT_RST_REG */ +#define PM_SOFT_RST_REG_OFFST_WARM_RST_FLAG (31) +#define PM_SOFT_RST_REG_OFFST_CPU1 (29) +#define PM_SOFT_RST_REG_OFFST_CPU0 (28) +#define PM_SOFT_RST_REG_OFFST_SDIO (25) +#define PM_SOFT_RST_REG_OFFST_GPU (24) +#define PM_SOFT_RST_REG_OFFST_CIM (23) +#define PM_SOFT_RST_REG_OFFST_LCDC (22) +#define PM_SOFT_RST_REG_OFFST_I2S (21) +#define PM_SOFT_RST_REG_OFFST_RAID (20) +#define PM_SOFT_RST_REG_OFFST_SATA (19) +#define PM_SOFT_RST_REG_OFFST_PCIE(x) (17 + (x)) +#define PM_SOFT_RST_REG_OFFST_USB_HOST (16) +#define PM_SOFT_RST_REG_OFFST_USB_OTG (15) +#define PM_SOFT_RST_REG_OFFST_TIMER (14) +#define PM_SOFT_RST_REG_OFFST_CRYPTO (13) +#define PM_SOFT_RST_REG_OFFST_HCIE (12) +#define PM_SOFT_RST_REG_OFFST_SWITCH (11) +#define PM_SOFT_RST_REG_OFFST_GPIO (10) +#define PM_SOFT_RST_REG_OFFST_UART3 (9) +#define PM_SOFT_RST_REG_OFFST_UART2 (8) +#define PM_SOFT_RST_REG_OFFST_UART1 (7) +#define PM_SOFT_RST_REG_OFFST_RTC (5) +#define PM_SOFT_RST_REG_OFFST_GDMA (4) +#define PM_SOFT_RST_REG_OFFST_SPI_PCM_I2C (3) +#define PM_SOFT_RST_REG_OFFST_DMC (2) +#define PM_SOFT_RST_REG_OFFST_SMC_NFI (1) +#define PM_SOFT_RST_REG_OFFST_GLOBAL (0) +#define PM_SOFT_RST_REG_MASK (0xF3FFFFBF) + +/* PMHS_CFG_REG */ +#define PM_HS_CFG_REG_OFFSET_SDIO (25) +#define PM_HS_CFG_REG_OFFSET_GPU (24) +#define PM_HS_CFG_REG_OFFSET_CIM (23) +#define PM_HS_CFG_REG_OFFSET_LCDC (22) +#define PM_HS_CFG_REG_OFFSET_I2S (21) +#define PM_HS_CFG_REG_OFFSET_RAID (20) +#define PM_HS_CFG_REG_OFFSET_SATA (19) +#define PM_HS_CFG_REG_OFFSET_PCIE1 (18) +#define PM_HS_CFG_REG_OFFSET_PCIE0 (17) +#define PM_HS_CFG_REG_OFFSET_USB_HOST (16) +#define PM_HS_CFG_REG_OFFSET_USB_OTG (15) +#define PM_HS_CFG_REG_OFFSET_TIMER (14) +#define PM_HS_CFG_REG_OFFSET_CRYPTO (13) +#define PM_HS_CFG_REG_OFFSET_HCIE (12) +#define PM_HS_CFG_REG_OFFSET_SWITCH (11) +#define PM_HS_CFG_REG_OFFSET_GPIO (10) +#define PM_HS_CFG_REG_OFFSET_UART3 (9) +#define PM_HS_CFG_REG_OFFSET_UART2 (8) +#define PM_HS_CFG_REG_OFFSET_UART1 (7) +#define PM_HS_CFG_REG_OFFSET_RTC (5) +#define PM_HS_CFG_REG_OFFSET_GDMA (4) +#define PM_HS_CFG_REG_OFFSET_SPI_PCM_I2S (3) +#define PM_HS_CFG_REG_OFFSET_DMC (2) +#define PM_HS_CFG_REG_OFFSET_SMC_NFI (1) +#define PM_HS_CFG_REG_MASK (0x03FFFFBE) +#define PM_HS_CFG_REG_MASK_SUPPORT (0x01100806) + +/* PM_CACTIVE_STA_REG */ +#define PM_CACTIVE_STA_REG_OFFSET_SDIO (25) +#define PM_CACTIVE_STA_REG_OFFSET_GPU (24) +#define PM_CACTIVE_STA_REG_OFFSET_CIM (23) +#define PM_CACTIVE_STA_REG_OFFSET_LCDC (22) +#define PM_CACTIVE_STA_REG_OFFSET_I2S (21) +#define PM_CACTIVE_STA_REG_OFFSET_RAID (20) +#define PM_CACTIVE_STA_REG_OFFSET_SATA (19) +#define PM_CACTIVE_STA_REG_OFFSET_PCIE1 (18) +#define PM_CACTIVE_STA_REG_OFFSET_PCIE0 (17) +#define PM_CACTIVE_STA_REG_OFFSET_USB_HOST (16) +#define PM_CACTIVE_STA_REG_OFFSET_USB_OTG (15) +#define PM_CACTIVE_STA_REG_OFFSET_TIMER (14) +#define PM_CACTIVE_STA_REG_OFFSET_CRYPTO (13) +#define PM_CACTIVE_STA_REG_OFFSET_HCIE (12) +#define PM_CACTIVE_STA_REG_OFFSET_SWITCH (11) +#define PM_CACTIVE_STA_REG_OFFSET_GPIO (10) +#define PM_CACTIVE_STA_REG_OFFSET_UART3 (9) +#define PM_CACTIVE_STA_REG_OFFSET_UART2 (8) +#define PM_CACTIVE_STA_REG_OFFSET_UART1 (7) +#define PM_CACTIVE_STA_REG_OFFSET_RTC (5) +#define PM_CACTIVE_STA_REG_OFFSET_GDMA (4) +#define PM_CACTIVE_STA_REG_OFFSET_SPI_PCM_I2S (3) +#define PM_CACTIVE_STA_REG_OFFSET_DMC (2) +#define PM_CACTIVE_STA_REG_OFFSET_SMC_NFI (1) +#define PM_CACTIVE_STA_REG_MASK (0x03FFFFBE) + +/* PM_PWR_STA_REG */ +#define PM_PWR_STA_REG_REG_OFFSET_SDIO (25) +#define PM_PWR_STA_REG_REG_OFFSET_GPU (24) +#define PM_PWR_STA_REG_REG_OFFSET_CIM (23) +#define PM_PWR_STA_REG_REG_OFFSET_LCDC (22) +#define PM_PWR_STA_REG_REG_OFFSET_I2S (21) +#define PM_PWR_STA_REG_REG_OFFSET_RAID (20) +#define PM_PWR_STA_REG_REG_OFFSET_SATA (19) +#define PM_PWR_STA_REG_REG_OFFSET_PCIE1 (18) +#define PM_PWR_STA_REG_REG_OFFSET_PCIE0 (17) +#define PM_PWR_STA_REG_REG_OFFSET_USB_HOST (16) +#define PM_PWR_STA_REG_REG_OFFSET_USB_OTG (15) +#define PM_PWR_STA_REG_REG_OFFSET_TIMER (14) +#define PM_PWR_STA_REG_REG_OFFSET_CRYPTO (13) +#define PM_PWR_STA_REG_REG_OFFSET_HCIE (12) +#define PM_PWR_STA_REG_REG_OFFSET_SWITCH (11) +#define PM_PWR_STA_REG_REG_OFFSET_GPIO (10) +#define PM_PWR_STA_REG_REG_OFFSET_UART3 (9) +#define PM_PWR_STA_REG_REG_OFFSET_UART2 (8) +#define PM_PWR_STA_REG_REG_OFFSET_UART1 (7) +#define PM_PWR_STA_REG_REG_OFFSET_RTC (5) +#define PM_PWR_STA_REG_REG_OFFSET_GDMA (4) +#define PM_PWR_STA_REG_REG_OFFSET_SPI_PCM_I2S (3) +#define PM_PWR_STA_REG_REG_OFFSET_DMC (2) +#define PM_PWR_STA_REG_REG_OFFSET_SMC_NFI (1) +#define PM_PWR_STA_REG_REG_MASK (0x03FFFFBE) + +/* PM_CLK_CTRL_REG */ +#define PM_CLK_CTRL_REG_OFFSET_I2S_MCLK (31) +#define PM_CLK_CTRL_REG_OFFSET_DDR2_CHG_EN (30) +#define PM_CLK_CTRL_REG_OFFSET_PCIE_REF1_EN (29) +#define PM_CLK_CTRL_REG_OFFSET_PCIE_REF0_EN (28) +#define PM_CLK_CTRL_REG_OFFSET_TIMER_SIM_MODE (27) +#define PM_CLK_CTRL_REG_OFFSET_I2SCLK_DIV (24) +#define PM_CLK_CTRL_REG_OFFSET_I2SCLK_SEL (22) +#define PM_CLK_CTRL_REG_OFFSET_CLKOUT_DIV (20) +#define PM_CLK_CTRL_REG_OFFSET_CLKOUT_SEL (16) +#define PM_CLK_CTRL_REG_OFFSET_MDC_DIV (14) +#define PM_CLK_CTRL_REG_OFFSET_CRYPTO_CLK_SEL (12) +#define PM_CLK_CTRL_REG_OFFSET_CPU_PWR_MODE (9) +#define PM_CLK_CTRL_REG_OFFSET_PLL_DDR2_SEL (7) +#define PM_CLK_CTRL_REG_OFFSET_DIV_IMMEDIATE (6) +#define PM_CLK_CTRL_REG_OFFSET_CPU_CLK_DIV (4) +#define PM_CLK_CTRL_REG_OFFSET_PLL_CPU_SEL (0) + +#define PM_CPU_CLK_DIV(DIV) { \ + PM_CLK_CTRL_REG &= ~((0x3) << PM_CLK_CTRL_REG_OFFSET_CPU_CLK_DIV); \ + PM_CLK_CTRL_REG |= (((DIV)&0x3) << PM_CLK_CTRL_REG_OFFSET_CPU_CLK_DIV); \ +} + +#define PM_PLL_CPU_SEL(CPU) { \ + PM_CLK_CTRL_REG &= ~((0xF) << PM_CLK_CTRL_REG_OFFSET_PLL_CPU_SEL); \ + PM_CLK_CTRL_REG |= (((CPU)&0xF) << PM_CLK_CTRL_REG_OFFSET_PLL_CPU_SEL); \ +} + +/* PM_PLL_LCD_I2S_CTRL_REG */ +#define PM_PLL_LCD_I2S_CTRL_REG_OFFSET_MCLK_SMC_DIV (22) +#define PM_PLL_LCD_I2S_CTRL_REG_OFFSET_R_SEL (17) +#define PM_PLL_LCD_I2S_CTRL_REG_OFFSET_PLL_LCD_P (11) +#define PM_PLL_LCD_I2S_CTRL_REG_OFFSET_PLL_LCD_M (3) +#define PM_PLL_LCD_I2S_CTRL_REG_OFFSET_PLL_LCD_S (0) + +/* PM_PLL_HM_PD_CTRL_REG */ +#define PM_PLL_HM_PD_CTRL_REG_OFFSET_SATA_PHY1 (11) +#define PM_PLL_HM_PD_CTRL_REG_OFFSET_SATA_PHY0 (10) +#define PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_I2SCD (6) +#define PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_I2S (5) +#define PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_LCD (4) +#define PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_USB (3) +#define PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_RGMII (2) +#define PM_PLL_HM_PD_CTRL_REG_MASK (0x00000C7C) + +/* PM_WDT_CTRL_REG */ +#define PM_WDT_CTRL_REG_OFFSET_RESET_CPU_ONLY (0) + +/* PM_CSR_REG - Clock Scaling Register*/ +#define PM_CSR_REG_OFFSET_CSR_EN (30) +#define PM_CSR_REG_OFFSET_CSR_NUM (0) + +#define CNS3XXX_PWR_CLK_EN(BLOCK) (0x1< #include #include -#include +#include "cns3xxx.h" #include "core.h" static struct map_desc cns3xxx_io_desc[] __initdata = { diff --git a/arch/arm/mach-cns3xxx/devices.c b/arch/arm/mach-cns3xxx/devices.c index 1e40c99..7da78a2 100644 --- a/arch/arm/mach-cns3xxx/devices.c +++ b/arch/arm/mach-cns3xxx/devices.c @@ -16,9 +16,8 @@ #include #include #include -#include -#include -#include +#include "cns3xxx.h" +#include "pm.h" #include "core.h" #include "devices.h" diff --git a/arch/arm/mach-cns3xxx/include/mach/cns3xxx.h b/arch/arm/mach-cns3xxx/include/mach/cns3xxx.h deleted file mode 100644 index 191c8e5..0000000 --- a/arch/arm/mach-cns3xxx/include/mach/cns3xxx.h +++ /dev/null @@ -1,632 +0,0 @@ -/* - * Copyright 2008 Cavium Networks - * - * This file is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License, Version 2, as - * published by the Free Software Foundation. - */ - -#ifndef __MACH_BOARD_CNS3XXXH -#define __MACH_BOARD_CNS3XXXH - -/* - * Memory map - */ -#define CNS3XXX_FLASH_BASE 0x10000000 /* Flash/SRAM Memory Bank 0 */ -#define CNS3XXX_FLASH_SIZE SZ_256M - -#define CNS3XXX_DDR2SDRAM_BASE 0x20000000 /* DDR2 SDRAM Memory */ - -#define CNS3XXX_SPI_FLASH_BASE 0x60000000 /* SPI Serial Flash Memory */ - -#define CNS3XXX_SWITCH_BASE 0x70000000 /* Switch and HNAT Control */ -#define CNS3XXX_SWITCH_BASE_VIRT 0xFFF00000 - -#define CNS3XXX_PPE_BASE 0x70001000 /* HANT */ -#define CNS3XXX_PPE_BASE_VIRT 0xFFF50000 - -#define CNS3XXX_EMBEDDED_SRAM_BASE 0x70002000 /* HANT Embedded SRAM */ -#define CNS3XXX_EMBEDDED_SRAM_BASE_VIRT 0xFFF60000 - -#define CNS3XXX_SSP_BASE 0x71000000 /* Synchronous Serial Port - SPI/PCM/I2C */ -#define CNS3XXX_SSP_BASE_VIRT 0xFFF01000 - -#define CNS3XXX_DMC_BASE 0x72000000 /* DMC Control (DDR2 SDRAM) */ -#define CNS3XXX_DMC_BASE_VIRT 0xFFF02000 - -#define CNS3XXX_SMC_BASE 0x73000000 /* SMC Control */ -#define CNS3XXX_SMC_BASE_VIRT 0xFFF03000 - -#define SMC_MEMC_STATUS_OFFSET 0x000 -#define SMC_MEMIF_CFG_OFFSET 0x004 -#define SMC_MEMC_CFG_SET_OFFSET 0x008 -#define SMC_MEMC_CFG_CLR_OFFSET 0x00C -#define SMC_DIRECT_CMD_OFFSET 0x010 -#define SMC_SET_CYCLES_OFFSET 0x014 -#define SMC_SET_OPMODE_OFFSET 0x018 -#define SMC_REFRESH_PERIOD_0_OFFSET 0x020 -#define SMC_REFRESH_PERIOD_1_OFFSET 0x024 -#define SMC_SRAM_CYCLES0_0_OFFSET 0x100 -#define SMC_NAND_CYCLES0_0_OFFSET 0x100 -#define SMC_OPMODE0_0_OFFSET 0x104 -#define SMC_SRAM_CYCLES0_1_OFFSET 0x120 -#define SMC_NAND_CYCLES0_1_OFFSET 0x120 -#define SMC_OPMODE0_1_OFFSET 0x124 -#define SMC_USER_STATUS_OFFSET 0x200 -#define SMC_USER_CONFIG_OFFSET 0x204 -#define SMC_ECC_STATUS_OFFSET 0x300 -#define SMC_ECC_MEMCFG_OFFSET 0x304 -#define SMC_ECC_MEMCOMMAND1_OFFSET 0x308 -#define SMC_ECC_MEMCOMMAND2_OFFSET 0x30C -#define SMC_ECC_ADDR0_OFFSET 0x310 -#define SMC_ECC_ADDR1_OFFSET 0x314 -#define SMC_ECC_VALUE0_OFFSET 0x318 -#define SMC_ECC_VALUE1_OFFSET 0x31C -#define SMC_ECC_VALUE2_OFFSET 0x320 -#define SMC_ECC_VALUE3_OFFSET 0x324 -#define SMC_PERIPH_ID_0_OFFSET 0xFE0 -#define SMC_PERIPH_ID_1_OFFSET 0xFE4 -#define SMC_PERIPH_ID_2_OFFSET 0xFE8 -#define SMC_PERIPH_ID_3_OFFSET 0xFEC -#define SMC_PCELL_ID_0_OFFSET 0xFF0 -#define SMC_PCELL_ID_1_OFFSET 0xFF4 -#define SMC_PCELL_ID_2_OFFSET 0xFF8 -#define SMC_PCELL_ID_3_OFFSET 0xFFC - -#define CNS3XXX_GPIOA_BASE 0x74000000 /* GPIO port A */ -#define CNS3XXX_GPIOA_BASE_VIRT 0xFFF04000 - -#define CNS3XXX_GPIOB_BASE 0x74800000 /* GPIO port B */ -#define CNS3XXX_GPIOB_BASE_VIRT 0xFFF05000 - -#define CNS3XXX_RTC_BASE 0x75000000 /* Real Time Clock */ -#define CNS3XXX_RTC_BASE_VIRT 0xFFF06000 - -#define RTC_SEC_OFFSET 0x00 -#define RTC_MIN_OFFSET 0x04 -#define RTC_HOUR_OFFSET 0x08 -#define RTC_DAY_OFFSET 0x0C -#define RTC_SEC_ALM_OFFSET 0x10 -#define RTC_MIN_ALM_OFFSET 0x14 -#define RTC_HOUR_ALM_OFFSET 0x18 -#define RTC_REC_OFFSET 0x1C -#define RTC_CTRL_OFFSET 0x20 -#define RTC_INTR_STS_OFFSET 0x34 - -#define CNS3XXX_MISC_BASE 0x76000000 /* Misc Control */ -#define CNS3XXX_MISC_BASE_VIRT 0xFFF07000 /* Misc Control */ - -#define CNS3XXX_PM_BASE 0x77000000 /* Power Management Control */ -#define CNS3XXX_PM_BASE_VIRT 0xFFF08000 - -#define PM_CLK_GATE_OFFSET 0x00 -#define PM_SOFT_RST_OFFSET 0x04 -#define PM_HS_CFG_OFFSET 0x08 -#define PM_CACTIVE_STA_OFFSET 0x0C -#define PM_PWR_STA_OFFSET 0x10 -#define PM_SYS_CLK_CTRL_OFFSET 0x14 -#define PM_PLL_LCD_I2S_CTRL_OFFSET 0x18 -#define PM_PLL_HM_PD_OFFSET 0x1C - -#define CNS3XXX_UART0_BASE 0x78000000 /* UART 0 */ -#define CNS3XXX_UART0_BASE_VIRT 0xFFF09000 - -#define CNS3XXX_UART1_BASE 0x78400000 /* UART 1 */ -#define CNS3XXX_UART1_BASE_VIRT 0xFFF0A000 - -#define CNS3XXX_UART2_BASE 0x78800000 /* UART 2 */ -#define CNS3XXX_UART2_BASE_VIRT 0xFFF0B000 - -#define CNS3XXX_DMAC_BASE 0x79000000 /* Generic DMA Control */ -#define CNS3XXX_DMAC_BASE_VIRT 0xFFF0D000 - -#define CNS3XXX_CORESIGHT_BASE 0x7A000000 /* CoreSight */ -#define CNS3XXX_CORESIGHT_BASE_VIRT 0xFFF0E000 - -#define CNS3XXX_CRYPTO_BASE 0x7B000000 /* Crypto */ -#define CNS3XXX_CRYPTO_BASE_VIRT 0xFFF0F000 - -#define CNS3XXX_I2S_BASE 0x7C000000 /* I2S */ -#define CNS3XXX_I2S_BASE_VIRT 0xFFF10000 - -#define CNS3XXX_TIMER1_2_3_BASE 0x7C800000 /* Timer */ -#define CNS3XXX_TIMER1_2_3_BASE_VIRT 0xFFF10800 - -#define TIMER1_COUNTER_OFFSET 0x00 -#define TIMER1_AUTO_RELOAD_OFFSET 0x04 -#define TIMER1_MATCH_V1_OFFSET 0x08 -#define TIMER1_MATCH_V2_OFFSET 0x0C - -#define TIMER2_COUNTER_OFFSET 0x10 -#define TIMER2_AUTO_RELOAD_OFFSET 0x14 -#define TIMER2_MATCH_V1_OFFSET 0x18 -#define TIMER2_MATCH_V2_OFFSET 0x1C - -#define TIMER1_2_CONTROL_OFFSET 0x30 -#define TIMER1_2_INTERRUPT_STATUS_OFFSET 0x34 -#define TIMER1_2_INTERRUPT_MASK_OFFSET 0x38 - -#define TIMER_FREERUN_OFFSET 0x40 -#define TIMER_FREERUN_CONTROL_OFFSET 0x44 - -#define CNS3XXX_HCIE_BASE 0x7D000000 /* HCIE Control */ -#define CNS3XXX_HCIE_BASE_VIRT 0xFFF30000 - -#define CNS3XXX_RAID_BASE 0x7E000000 /* RAID Control */ -#define CNS3XXX_RAID_BASE_VIRT 0xFFF12000 - -#define CNS3XXX_AXI_IXC_BASE 0x7F000000 /* AXI IXC */ -#define CNS3XXX_AXI_IXC_BASE_VIRT 0xFFF13000 - -#define CNS3XXX_CLCD_BASE 0x80000000 /* LCD Control */ -#define CNS3XXX_CLCD_BASE_VIRT 0xFFF14000 - -#define CNS3XXX_USBOTG_BASE 0x81000000 /* USB OTG Control */ -#define CNS3XXX_USBOTG_BASE_VIRT 0xFFF15000 - -#define CNS3XXX_USB_BASE 0x82000000 /* USB Host Control */ - -#define CNS3XXX_SATA2_BASE 0x83000000 /* SATA */ -#define CNS3XXX_SATA2_SIZE SZ_16M -#define CNS3XXX_SATA2_BASE_VIRT 0xFFF17000 - -#define CNS3XXX_CAMERA_BASE 0x84000000 /* Camera Interface */ -#define CNS3XXX_CAMERA_BASE_VIRT 0xFFF18000 - -#define CNS3XXX_SDIO_BASE 0x85000000 /* SDIO */ -#define CNS3XXX_SDIO_BASE_VIRT 0xFFF19000 - -#define CNS3XXX_I2S_TDM_BASE 0x86000000 /* I2S TDM */ -#define CNS3XXX_I2S_TDM_BASE_VIRT 0xFFF1A000 - -#define CNS3XXX_2DG_BASE 0x87000000 /* 2D Graphic Control */ -#define CNS3XXX_2DG_BASE_VIRT 0xFFF1B000 - -#define CNS3XXX_USB_OHCI_BASE 0x88000000 /* USB OHCI */ - -#define CNS3XXX_L2C_BASE 0x92000000 /* L2 Cache Control */ -#define CNS3XXX_L2C_BASE_VIRT 0xFFF27000 - -#define CNS3XXX_PCIE0_MEM_BASE 0xA0000000 /* PCIe Port 0 IO/Memory Space */ -#define CNS3XXX_PCIE0_MEM_BASE_VIRT 0xE0000000 - -#define CNS3XXX_PCIE0_HOST_BASE 0xAB000000 /* PCIe Port 0 RC Base */ -#define CNS3XXX_PCIE0_HOST_BASE_VIRT 0xE1000000 - -#define CNS3XXX_PCIE0_IO_BASE 0xAC000000 /* PCIe Port 0 */ -#define CNS3XXX_PCIE0_IO_BASE_VIRT 0xE2000000 - -#define CNS3XXX_PCIE0_CFG0_BASE 0xAD000000 /* PCIe Port 0 CFG Type 0 */ -#define CNS3XXX_PCIE0_CFG0_BASE_VIRT 0xE3000000 - -#define CNS3XXX_PCIE0_CFG1_BASE 0xAE000000 /* PCIe Port 0 CFG Type 1 */ -#define CNS3XXX_PCIE0_CFG1_BASE_VIRT 0xE4000000 - -#define CNS3XXX_PCIE0_MSG_BASE 0xAF000000 /* PCIe Port 0 Message Space */ -#define CNS3XXX_PCIE0_MSG_BASE_VIRT 0xE5000000 - -#define CNS3XXX_PCIE1_MEM_BASE 0xB0000000 /* PCIe Port 1 IO/Memory Space */ -#define CNS3XXX_PCIE1_MEM_BASE_VIRT 0xE8000000 - -#define CNS3XXX_PCIE1_HOST_BASE 0xBB000000 /* PCIe Port 1 RC Base */ -#define CNS3XXX_PCIE1_HOST_BASE_VIRT 0xE9000000 - -#define CNS3XXX_PCIE1_IO_BASE 0xBC000000 /* PCIe Port 1 */ -#define CNS3XXX_PCIE1_IO_BASE_VIRT 0xEA000000 - -#define CNS3XXX_PCIE1_CFG0_BASE 0xBD000000 /* PCIe Port 1 CFG Type 0 */ -#define CNS3XXX_PCIE1_CFG0_BASE_VIRT 0xEB000000 - -#define CNS3XXX_PCIE1_CFG1_BASE 0xBE000000 /* PCIe Port 1 CFG Type 1 */ -#define CNS3XXX_PCIE1_CFG1_BASE_VIRT 0xEC000000 - -#define CNS3XXX_PCIE1_MSG_BASE 0xBF000000 /* PCIe Port 1 Message Space */ -#define CNS3XXX_PCIE1_MSG_BASE_VIRT 0xED000000 - -/* - * Testchip peripheral and fpga gic regions - */ -#define CNS3XXX_TC11MP_SCU_BASE 0x90000000 /* IRQ, Test chip */ -#define CNS3XXX_TC11MP_SCU_BASE_VIRT 0xFF000000 - -#define CNS3XXX_TC11MP_GIC_CPU_BASE 0x90000100 /* Test chip interrupt controller CPU interface */ -#define CNS3XXX_TC11MP_GIC_CPU_BASE_VIRT 0xFF000100 - -#define CNS3XXX_TC11MP_TWD_BASE 0x90000600 -#define CNS3XXX_TC11MP_TWD_BASE_VIRT 0xFF000600 - -#define CNS3XXX_TC11MP_GIC_DIST_BASE 0x90001000 /* Test chip interrupt controller distributor */ -#define CNS3XXX_TC11MP_GIC_DIST_BASE_VIRT 0xFF001000 - -#define CNS3XXX_TC11MP_L220_BASE 0x92002000 /* L220 registers */ -#define CNS3XXX_TC11MP_L220_BASE_VIRT 0xFF002000 - -/* - * Misc block - */ -#define MISC_MEM_MAP(offs) (void __iomem *)(CNS3XXX_MISC_BASE_VIRT + (offs)) - -#define MISC_MEMORY_REMAP_REG MISC_MEM_MAP(0x00) -#define MISC_CHIP_CONFIG_REG MISC_MEM_MAP(0x04) -#define MISC_DEBUG_PROBE_DATA_REG MISC_MEM_MAP(0x08) -#define MISC_DEBUG_PROBE_SELECTION_REG MISC_MEM_MAP(0x0C) -#define MISC_IO_PIN_FUNC_SELECTION_REG MISC_MEM_MAP(0x10) -#define MISC_GPIOA_PIN_ENABLE_REG MISC_MEM_MAP(0x14) -#define MISC_GPIOB_PIN_ENABLE_REG MISC_MEM_MAP(0x18) -#define MISC_IO_PAD_DRIVE_STRENGTH_CTRL_A MISC_MEM_MAP(0x1C) -#define MISC_IO_PAD_DRIVE_STRENGTH_CTRL_B MISC_MEM_MAP(0x20) -#define MISC_GPIOA_15_0_PULL_CTRL_REG MISC_MEM_MAP(0x24) -#define MISC_GPIOA_16_31_PULL_CTRL_REG MISC_MEM_MAP(0x28) -#define MISC_GPIOB_15_0_PULL_CTRL_REG MISC_MEM_MAP(0x2C) -#define MISC_GPIOB_16_31_PULL_CTRL_REG MISC_MEM_MAP(0x30) -#define MISC_IO_PULL_CTRL_REG MISC_MEM_MAP(0x34) -#define MISC_E_FUSE_31_0_REG MISC_MEM_MAP(0x40) -#define MISC_E_FUSE_63_32_REG MISC_MEM_MAP(0x44) -#define MISC_E_FUSE_95_64_REG MISC_MEM_MAP(0x48) -#define MISC_E_FUSE_127_96_REG MISC_MEM_MAP(0x4C) -#define MISC_SOFTWARE_TEST_1_REG MISC_MEM_MAP(0x50) -#define MISC_SOFTWARE_TEST_2_REG MISC_MEM_MAP(0x54) - -#define MISC_SATA_POWER_MODE MISC_MEM_MAP(0x310) - -#define MISC_USB_CFG_REG MISC_MEM_MAP(0x800) -#define MISC_USB_STS_REG MISC_MEM_MAP(0x804) -#define MISC_USBPHY00_CFG_REG MISC_MEM_MAP(0x808) -#define MISC_USBPHY01_CFG_REG MISC_MEM_MAP(0x80c) -#define MISC_USBPHY10_CFG_REG MISC_MEM_MAP(0x810) -#define MISC_USBPHY11_CFG_REG MISC_MEM_MAP(0x814) - -#define MISC_PCIEPHY_CMCTL(x) MISC_MEM_MAP(0x900 + (x) * 0x004) -#define MISC_PCIEPHY_CTL(x) MISC_MEM_MAP(0x940 + (x) * 0x100) -#define MISC_PCIE_AXIS_AWMISC(x) MISC_MEM_MAP(0x944 + (x) * 0x100) -#define MISC_PCIE_AXIS_ARMISC(x) MISC_MEM_MAP(0x948 + (x) * 0x100) -#define MISC_PCIE_AXIS_RMISC(x) MISC_MEM_MAP(0x94C + (x) * 0x100) -#define MISC_PCIE_AXIS_BMISC(x) MISC_MEM_MAP(0x950 + (x) * 0x100) -#define MISC_PCIE_AXIM_RMISC(x) MISC_MEM_MAP(0x954 + (x) * 0x100) -#define MISC_PCIE_AXIM_BMISC(x) MISC_MEM_MAP(0x958 + (x) * 0x100) -#define MISC_PCIE_CTRL(x) MISC_MEM_MAP(0x95C + (x) * 0x100) -#define MISC_PCIE_PM_DEBUG(x) MISC_MEM_MAP(0x960 + (x) * 0x100) -#define MISC_PCIE_RFC_DEBUG(x) MISC_MEM_MAP(0x964 + (x) * 0x100) -#define MISC_PCIE_CXPL_DEBUGL(x) MISC_MEM_MAP(0x968 + (x) * 0x100) -#define MISC_PCIE_CXPL_DEBUGH(x) MISC_MEM_MAP(0x96C + (x) * 0x100) -#define MISC_PCIE_DIAG_DEBUGH(x) MISC_MEM_MAP(0x970 + (x) * 0x100) -#define MISC_PCIE_W1CLR(x) MISC_MEM_MAP(0x974 + (x) * 0x100) -#define MISC_PCIE_INT_MASK(x) MISC_MEM_MAP(0x978 + (x) * 0x100) -#define MISC_PCIE_INT_STATUS(x) MISC_MEM_MAP(0x97C + (x) * 0x100) - -/* - * Power management and clock control - */ -#define PMU_MEM_MAP(offs) (void __iomem *)(CNS3XXX_PM_BASE_VIRT + (offs)) - -#define PM_CLK_GATE_REG PMU_MEM_MAP(0x000) -#define PM_SOFT_RST_REG PMU_MEM_MAP(0x004) -#define PM_HS_CFG_REG PMU_MEM_MAP(0x008) -#define PM_CACTIVE_STA_REG PMU_MEM_MAP(0x00C) -#define PM_PWR_STA_REG PMU_MEM_MAP(0x010) -#define PM_CLK_CTRL_REG PMU_MEM_MAP(0x014) -#define PM_PLL_LCD_I2S_CTRL_REG PMU_MEM_MAP(0x018) -#define PM_PLL_HM_PD_CTRL_REG PMU_MEM_MAP(0x01C) -#define PM_REGULAT_CTRL_REG PMU_MEM_MAP(0x020) -#define PM_WDT_CTRL_REG PMU_MEM_MAP(0x024) -#define PM_WU_CTRL0_REG PMU_MEM_MAP(0x028) -#define PM_WU_CTRL1_REG PMU_MEM_MAP(0x02C) -#define PM_CSR_REG PMU_MEM_MAP(0x030) - -/* PM_CLK_GATE_REG */ -#define PM_CLK_GATE_REG_OFFSET_SDIO (25) -#define PM_CLK_GATE_REG_OFFSET_GPU (24) -#define PM_CLK_GATE_REG_OFFSET_CIM (23) -#define PM_CLK_GATE_REG_OFFSET_LCDC (22) -#define PM_CLK_GATE_REG_OFFSET_I2S (21) -#define PM_CLK_GATE_REG_OFFSET_RAID (20) -#define PM_CLK_GATE_REG_OFFSET_SATA (19) -#define PM_CLK_GATE_REG_OFFSET_PCIE(x) (17 + (x)) -#define PM_CLK_GATE_REG_OFFSET_USB_HOST (16) -#define PM_CLK_GATE_REG_OFFSET_USB_OTG (15) -#define PM_CLK_GATE_REG_OFFSET_TIMER (14) -#define PM_CLK_GATE_REG_OFFSET_CRYPTO (13) -#define PM_CLK_GATE_REG_OFFSET_HCIE (12) -#define PM_CLK_GATE_REG_OFFSET_SWITCH (11) -#define PM_CLK_GATE_REG_OFFSET_GPIO (10) -#define PM_CLK_GATE_REG_OFFSET_UART3 (9) -#define PM_CLK_GATE_REG_OFFSET_UART2 (8) -#define PM_CLK_GATE_REG_OFFSET_UART1 (7) -#define PM_CLK_GATE_REG_OFFSET_RTC (5) -#define PM_CLK_GATE_REG_OFFSET_GDMA (4) -#define PM_CLK_GATE_REG_OFFSET_SPI_PCM_I2C (3) -#define PM_CLK_GATE_REG_OFFSET_SMC_NFI (1) -#define PM_CLK_GATE_REG_MASK (0x03FFFFBA) - -/* PM_SOFT_RST_REG */ -#define PM_SOFT_RST_REG_OFFST_WARM_RST_FLAG (31) -#define PM_SOFT_RST_REG_OFFST_CPU1 (29) -#define PM_SOFT_RST_REG_OFFST_CPU0 (28) -#define PM_SOFT_RST_REG_OFFST_SDIO (25) -#define PM_SOFT_RST_REG_OFFST_GPU (24) -#define PM_SOFT_RST_REG_OFFST_CIM (23) -#define PM_SOFT_RST_REG_OFFST_LCDC (22) -#define PM_SOFT_RST_REG_OFFST_I2S (21) -#define PM_SOFT_RST_REG_OFFST_RAID (20) -#define PM_SOFT_RST_REG_OFFST_SATA (19) -#define PM_SOFT_RST_REG_OFFST_PCIE(x) (17 + (x)) -#define PM_SOFT_RST_REG_OFFST_USB_HOST (16) -#define PM_SOFT_RST_REG_OFFST_USB_OTG (15) -#define PM_SOFT_RST_REG_OFFST_TIMER (14) -#define PM_SOFT_RST_REG_OFFST_CRYPTO (13) -#define PM_SOFT_RST_REG_OFFST_HCIE (12) -#define PM_SOFT_RST_REG_OFFST_SWITCH (11) -#define PM_SOFT_RST_REG_OFFST_GPIO (10) -#define PM_SOFT_RST_REG_OFFST_UART3 (9) -#define PM_SOFT_RST_REG_OFFST_UART2 (8) -#define PM_SOFT_RST_REG_OFFST_UART1 (7) -#define PM_SOFT_RST_REG_OFFST_RTC (5) -#define PM_SOFT_RST_REG_OFFST_GDMA (4) -#define PM_SOFT_RST_REG_OFFST_SPI_PCM_I2C (3) -#define PM_SOFT_RST_REG_OFFST_DMC (2) -#define PM_SOFT_RST_REG_OFFST_SMC_NFI (1) -#define PM_SOFT_RST_REG_OFFST_GLOBAL (0) -#define PM_SOFT_RST_REG_MASK (0xF3FFFFBF) - -/* PMHS_CFG_REG */ -#define PM_HS_CFG_REG_OFFSET_SDIO (25) -#define PM_HS_CFG_REG_OFFSET_GPU (24) -#define PM_HS_CFG_REG_OFFSET_CIM (23) -#define PM_HS_CFG_REG_OFFSET_LCDC (22) -#define PM_HS_CFG_REG_OFFSET_I2S (21) -#define PM_HS_CFG_REG_OFFSET_RAID (20) -#define PM_HS_CFG_REG_OFFSET_SATA (19) -#define PM_HS_CFG_REG_OFFSET_PCIE1 (18) -#define PM_HS_CFG_REG_OFFSET_PCIE0 (17) -#define PM_HS_CFG_REG_OFFSET_USB_HOST (16) -#define PM_HS_CFG_REG_OFFSET_USB_OTG (15) -#define PM_HS_CFG_REG_OFFSET_TIMER (14) -#define PM_HS_CFG_REG_OFFSET_CRYPTO (13) -#define PM_HS_CFG_REG_OFFSET_HCIE (12) -#define PM_HS_CFG_REG_OFFSET_SWITCH (11) -#define PM_HS_CFG_REG_OFFSET_GPIO (10) -#define PM_HS_CFG_REG_OFFSET_UART3 (9) -#define PM_HS_CFG_REG_OFFSET_UART2 (8) -#define PM_HS_CFG_REG_OFFSET_UART1 (7) -#define PM_HS_CFG_REG_OFFSET_RTC (5) -#define PM_HS_CFG_REG_OFFSET_GDMA (4) -#define PM_HS_CFG_REG_OFFSET_SPI_PCM_I2S (3) -#define PM_HS_CFG_REG_OFFSET_DMC (2) -#define PM_HS_CFG_REG_OFFSET_SMC_NFI (1) -#define PM_HS_CFG_REG_MASK (0x03FFFFBE) -#define PM_HS_CFG_REG_MASK_SUPPORT (0x01100806) - -/* PM_CACTIVE_STA_REG */ -#define PM_CACTIVE_STA_REG_OFFSET_SDIO (25) -#define PM_CACTIVE_STA_REG_OFFSET_GPU (24) -#define PM_CACTIVE_STA_REG_OFFSET_CIM (23) -#define PM_CACTIVE_STA_REG_OFFSET_LCDC (22) -#define PM_CACTIVE_STA_REG_OFFSET_I2S (21) -#define PM_CACTIVE_STA_REG_OFFSET_RAID (20) -#define PM_CACTIVE_STA_REG_OFFSET_SATA (19) -#define PM_CACTIVE_STA_REG_OFFSET_PCIE1 (18) -#define PM_CACTIVE_STA_REG_OFFSET_PCIE0 (17) -#define PM_CACTIVE_STA_REG_OFFSET_USB_HOST (16) -#define PM_CACTIVE_STA_REG_OFFSET_USB_OTG (15) -#define PM_CACTIVE_STA_REG_OFFSET_TIMER (14) -#define PM_CACTIVE_STA_REG_OFFSET_CRYPTO (13) -#define PM_CACTIVE_STA_REG_OFFSET_HCIE (12) -#define PM_CACTIVE_STA_REG_OFFSET_SWITCH (11) -#define PM_CACTIVE_STA_REG_OFFSET_GPIO (10) -#define PM_CACTIVE_STA_REG_OFFSET_UART3 (9) -#define PM_CACTIVE_STA_REG_OFFSET_UART2 (8) -#define PM_CACTIVE_STA_REG_OFFSET_UART1 (7) -#define PM_CACTIVE_STA_REG_OFFSET_RTC (5) -#define PM_CACTIVE_STA_REG_OFFSET_GDMA (4) -#define PM_CACTIVE_STA_REG_OFFSET_SPI_PCM_I2S (3) -#define PM_CACTIVE_STA_REG_OFFSET_DMC (2) -#define PM_CACTIVE_STA_REG_OFFSET_SMC_NFI (1) -#define PM_CACTIVE_STA_REG_MASK (0x03FFFFBE) - -/* PM_PWR_STA_REG */ -#define PM_PWR_STA_REG_REG_OFFSET_SDIO (25) -#define PM_PWR_STA_REG_REG_OFFSET_GPU (24) -#define PM_PWR_STA_REG_REG_OFFSET_CIM (23) -#define PM_PWR_STA_REG_REG_OFFSET_LCDC (22) -#define PM_PWR_STA_REG_REG_OFFSET_I2S (21) -#define PM_PWR_STA_REG_REG_OFFSET_RAID (20) -#define PM_PWR_STA_REG_REG_OFFSET_SATA (19) -#define PM_PWR_STA_REG_REG_OFFSET_PCIE1 (18) -#define PM_PWR_STA_REG_REG_OFFSET_PCIE0 (17) -#define PM_PWR_STA_REG_REG_OFFSET_USB_HOST (16) -#define PM_PWR_STA_REG_REG_OFFSET_USB_OTG (15) -#define PM_PWR_STA_REG_REG_OFFSET_TIMER (14) -#define PM_PWR_STA_REG_REG_OFFSET_CRYPTO (13) -#define PM_PWR_STA_REG_REG_OFFSET_HCIE (12) -#define PM_PWR_STA_REG_REG_OFFSET_SWITCH (11) -#define PM_PWR_STA_REG_REG_OFFSET_GPIO (10) -#define PM_PWR_STA_REG_REG_OFFSET_UART3 (9) -#define PM_PWR_STA_REG_REG_OFFSET_UART2 (8) -#define PM_PWR_STA_REG_REG_OFFSET_UART1 (7) -#define PM_PWR_STA_REG_REG_OFFSET_RTC (5) -#define PM_PWR_STA_REG_REG_OFFSET_GDMA (4) -#define PM_PWR_STA_REG_REG_OFFSET_SPI_PCM_I2S (3) -#define PM_PWR_STA_REG_REG_OFFSET_DMC (2) -#define PM_PWR_STA_REG_REG_OFFSET_SMC_NFI (1) -#define PM_PWR_STA_REG_REG_MASK (0x03FFFFBE) - -/* PM_CLK_CTRL_REG */ -#define PM_CLK_CTRL_REG_OFFSET_I2S_MCLK (31) -#define PM_CLK_CTRL_REG_OFFSET_DDR2_CHG_EN (30) -#define PM_CLK_CTRL_REG_OFFSET_PCIE_REF1_EN (29) -#define PM_CLK_CTRL_REG_OFFSET_PCIE_REF0_EN (28) -#define PM_CLK_CTRL_REG_OFFSET_TIMER_SIM_MODE (27) -#define PM_CLK_CTRL_REG_OFFSET_I2SCLK_DIV (24) -#define PM_CLK_CTRL_REG_OFFSET_I2SCLK_SEL (22) -#define PM_CLK_CTRL_REG_OFFSET_CLKOUT_DIV (20) -#define PM_CLK_CTRL_REG_OFFSET_CLKOUT_SEL (16) -#define PM_CLK_CTRL_REG_OFFSET_MDC_DIV (14) -#define PM_CLK_CTRL_REG_OFFSET_CRYPTO_CLK_SEL (12) -#define PM_CLK_CTRL_REG_OFFSET_CPU_PWR_MODE (9) -#define PM_CLK_CTRL_REG_OFFSET_PLL_DDR2_SEL (7) -#define PM_CLK_CTRL_REG_OFFSET_DIV_IMMEDIATE (6) -#define PM_CLK_CTRL_REG_OFFSET_CPU_CLK_DIV (4) -#define PM_CLK_CTRL_REG_OFFSET_PLL_CPU_SEL (0) - -#define PM_CPU_CLK_DIV(DIV) { \ - PM_CLK_CTRL_REG &= ~((0x3) << PM_CLK_CTRL_REG_OFFSET_CPU_CLK_DIV); \ - PM_CLK_CTRL_REG |= (((DIV)&0x3) << PM_CLK_CTRL_REG_OFFSET_CPU_CLK_DIV); \ -} - -#define PM_PLL_CPU_SEL(CPU) { \ - PM_CLK_CTRL_REG &= ~((0xF) << PM_CLK_CTRL_REG_OFFSET_PLL_CPU_SEL); \ - PM_CLK_CTRL_REG |= (((CPU)&0xF) << PM_CLK_CTRL_REG_OFFSET_PLL_CPU_SEL); \ -} - -/* PM_PLL_LCD_I2S_CTRL_REG */ -#define PM_PLL_LCD_I2S_CTRL_REG_OFFSET_MCLK_SMC_DIV (22) -#define PM_PLL_LCD_I2S_CTRL_REG_OFFSET_R_SEL (17) -#define PM_PLL_LCD_I2S_CTRL_REG_OFFSET_PLL_LCD_P (11) -#define PM_PLL_LCD_I2S_CTRL_REG_OFFSET_PLL_LCD_M (3) -#define PM_PLL_LCD_I2S_CTRL_REG_OFFSET_PLL_LCD_S (0) - -/* PM_PLL_HM_PD_CTRL_REG */ -#define PM_PLL_HM_PD_CTRL_REG_OFFSET_SATA_PHY1 (11) -#define PM_PLL_HM_PD_CTRL_REG_OFFSET_SATA_PHY0 (10) -#define PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_I2SCD (6) -#define PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_I2S (5) -#define PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_LCD (4) -#define PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_USB (3) -#define PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_RGMII (2) -#define PM_PLL_HM_PD_CTRL_REG_MASK (0x00000C7C) - -/* PM_WDT_CTRL_REG */ -#define PM_WDT_CTRL_REG_OFFSET_RESET_CPU_ONLY (0) - -/* PM_CSR_REG - Clock Scaling Register*/ -#define PM_CSR_REG_OFFSET_CSR_EN (30) -#define PM_CSR_REG_OFFSET_CSR_NUM (0) - -#define CNS3XXX_PWR_CLK_EN(BLOCK) (0x1< - -void cns3xxx_pwr_clk_en(unsigned int block); -void cns3xxx_pwr_clk_dis(unsigned int block); -void cns3xxx_pwr_power_up(unsigned int block); -void cns3xxx_pwr_power_down(unsigned int block); - -extern atomic_t usb_pwr_ref; - -#endif /* __CNS3XXX_PM_H */ diff --git a/arch/arm/mach-cns3xxx/include/mach/uncompress.h b/arch/arm/mach-cns3xxx/include/mach/uncompress.h index 7a030b9..e2c642c1c 100644 --- a/arch/arm/mach-cns3xxx/include/mach/uncompress.h +++ b/arch/arm/mach-cns3xxx/include/mach/uncompress.h @@ -8,7 +8,7 @@ */ #include -#include +#include "cns3xxx.h" #define AMBA_UART_DR(base) (*(volatile unsigned char *)((base) + 0x00)) #define AMBA_UART_LCRH(base) (*(volatile unsigned char *)((base) + 0x2c)) diff --git a/arch/arm/mach-cns3xxx/pcie.c b/arch/arm/mach-cns3xxx/pcie.c index 3113283..c7b204b 100644 --- a/arch/arm/mach-cns3xxx/pcie.c +++ b/arch/arm/mach-cns3xxx/pcie.c @@ -20,7 +20,7 @@ #include #include #include -#include +#include "cns3xxx.h" #include "core.h" enum cns3xxx_access_type { diff --git a/arch/arm/mach-cns3xxx/pm.c b/arch/arm/mach-cns3xxx/pm.c index 3645808..79e3d47 100644 --- a/arch/arm/mach-cns3xxx/pm.c +++ b/arch/arm/mach-cns3xxx/pm.c @@ -11,8 +11,8 @@ #include #include #include -#include -#include +#include "cns3xxx.h" +#include "pm.h" #include "core.h" void cns3xxx_pwr_clk_en(unsigned int block) diff --git a/arch/arm/mach-cns3xxx/pm.h b/arch/arm/mach-cns3xxx/pm.h new file mode 100644 index 0000000..c2588cc --- /dev/null +++ b/arch/arm/mach-cns3xxx/pm.h @@ -0,0 +1,23 @@ +/* + * Copyright 2000 Deep Blue Solutions Ltd + * Copyright 2004 ARM Limited + * Copyright 2008 Cavium Networks + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + */ + +#ifndef __CNS3XXX_PM_H +#define __CNS3XXX_PM_H + +#include + +void cns3xxx_pwr_clk_en(unsigned int block); +void cns3xxx_pwr_clk_dis(unsigned int block); +void cns3xxx_pwr_power_up(unsigned int block); +void cns3xxx_pwr_power_down(unsigned int block); + +extern atomic_t usb_pwr_ref; + +#endif /* __CNS3XXX_PM_H */ -- cgit v1.1 From 2f72a682f79d4eb2d96364d1a9abb7bd16c47afb Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Thu, 14 Mar 2013 17:30:53 +0100 Subject: ARM: cns3xxx: enable sparse IRQ support This trivially enables sparse IRQ on cns3xxx by moving the nr_irqs definition from mach/irqs.h into the machine descriptor. These interrupts will still get statically assigned, so nothing changes here. Signed-off-by: Arnd Bergmann --- arch/arm/Kconfig | 1 + arch/arm/mach-cns3xxx/cns3420vb.c | 1 + arch/arm/mach-cns3xxx/include/mach/irqs.h | 24 ------------------------ 3 files changed, 2 insertions(+), 24 deletions(-) delete mode 100644 arch/arm/mach-cns3xxx/include/mach/irqs.h (limited to 'arch/arm') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 5b71469..8bad33e 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -390,6 +390,7 @@ config ARCH_CNS3XXX select MIGHT_HAVE_CACHE_L2X0 select MIGHT_HAVE_PCI select PCI_DOMAINS if PCI + select SPARSE_IRQ help Support for Cavium Networks CNS3XXX platform. diff --git a/arch/arm/mach-cns3xxx/cns3420vb.c b/arch/arm/mach-cns3xxx/cns3420vb.c index d863d87..ce096d6 100644 --- a/arch/arm/mach-cns3xxx/cns3420vb.c +++ b/arch/arm/mach-cns3xxx/cns3420vb.c @@ -246,6 +246,7 @@ static void __init cns3420_map_io(void) MACHINE_START(CNS3420VB, "Cavium Networks CNS3420 Validation Board") .atag_offset = 0x100, + .nr_irqs = NR_IRQS_CNS3XXX, .map_io = cns3420_map_io, .init_irq = cns3xxx_init_irq, .init_time = cns3xxx_timer_init, diff --git a/arch/arm/mach-cns3xxx/include/mach/irqs.h b/arch/arm/mach-cns3xxx/include/mach/irqs.h deleted file mode 100644 index 2ab96f8..0000000 --- a/arch/arm/mach-cns3xxx/include/mach/irqs.h +++ /dev/null @@ -1,24 +0,0 @@ -/* - * Copyright 2000 Deep Blue Solutions Ltd. - * Copyright 2003 ARM Limited - * Copyright 2008 Cavium Networks - * - * This file is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License, Version 2, as - * published by the Free Software Foundation. - */ - -#ifndef __MACH_IRQS_H -#define __MACH_IRQS_H - -#define IRQ_LOCALTIMER 29 -#define IRQ_LOCALWDOG 30 -#define IRQ_TC11MP_GIC_START 32 - -#include - -#ifndef NR_IRQS -#error "NR_IRQS not defined by the board-specific files" -#endif - -#endif -- cgit v1.1 From 29c9b7be7574c486534a79c45982ede00f6a25a9 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Thu, 14 Mar 2013 16:02:59 +0100 Subject: ARM: cns3xxx: move debug_ll code to include/debug/ This is needed in order to keep debug_ll functionality on cns3xxx working when we enable ARCH_MULTIPLATFORM. Signed-off-by: Arnd Bergmann --- arch/arm/Kconfig.debug | 8 ++++++++ arch/arm/configs/cns3420vb_defconfig | 1 + arch/arm/include/debug/cns3xxx.S | 19 +++++++++++++++++++ arch/arm/mach-cns3xxx/include/mach/debug-macro.S | 19 ------------------- 4 files changed, 28 insertions(+), 19 deletions(-) create mode 100644 arch/arm/include/debug/cns3xxx.S delete mode 100644 arch/arm/mach-cns3xxx/include/mach/debug-macro.S (limited to 'arch/arm') diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug index acdddda..52f410d 100644 --- a/arch/arm/Kconfig.debug +++ b/arch/arm/Kconfig.debug @@ -103,6 +103,13 @@ choice Say Y here if you want the debug print routines to direct their output to the second serial port on these devices. + config DEBUG_CNS3XXX + bool "Kernel Kernel low-level debugging on Cavium Networks CNS3xxx" + depends on ARCH_CNS3XXX + help + Say Y here if you want the debug print routines to direct + their output to the CNS3xxx UART0. + config DEBUG_DAVINCI_DA8XX_UART1 bool "Kernel low-level debugging on DaVinci DA8XX using UART1" depends on ARCH_DAVINCI_DA8XX @@ -579,6 +586,7 @@ endchoice config DEBUG_LL_INCLUDE string + default "debug/cns3xxx.S" if DEBUG_CNS3XXX default "debug/icedcc.S" if DEBUG_ICEDCC default "debug/imx.S" if DEBUG_IMX1_UART || \ DEBUG_IMX25_UART || \ diff --git a/arch/arm/configs/cns3420vb_defconfig b/arch/arm/configs/cns3420vb_defconfig index 313627a..b79e984 100644 --- a/arch/arm/configs/cns3420vb_defconfig +++ b/arch/arm/configs/cns3420vb_defconfig @@ -21,6 +21,7 @@ CONFIG_MODVERSIONS=y CONFIG_IOSCHED_CFQ=m CONFIG_ARCH_CNS3XXX=y CONFIG_MACH_CNS3420VB=y +CONFIG_DEBUG_CNS3XXX=y CONFIG_AEABI=y CONFIG_ZBOOT_ROM_TEXT=0x0 CONFIG_ZBOOT_ROM_BSS=0x0 diff --git a/arch/arm/include/debug/cns3xxx.S b/arch/arm/include/debug/cns3xxx.S new file mode 100644 index 0000000..d04c150 --- /dev/null +++ b/arch/arm/include/debug/cns3xxx.S @@ -0,0 +1,19 @@ +/* + * Debugging macro include header + * + * Copyright 1994-1999 Russell King + * Copyright 2008 Cavium Networks + * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + */ + + .macro addruart,rp,rv,tmp + mov \rp, #0x00009000 + orr \rv, \rp, #0xf0000000 @ virtual base + orr \rp, \rp, #0x10000000 + .endm + +#include diff --git a/arch/arm/mach-cns3xxx/include/mach/debug-macro.S b/arch/arm/mach-cns3xxx/include/mach/debug-macro.S deleted file mode 100644 index d04c150..0000000 --- a/arch/arm/mach-cns3xxx/include/mach/debug-macro.S +++ /dev/null @@ -1,19 +0,0 @@ -/* - * Debugging macro include header - * - * Copyright 1994-1999 Russell King - * Copyright 2008 Cavium Networks - * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks - * - * This file is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License, Version 2, as - * published by the Free Software Foundation. - */ - - .macro addruart,rp,rv,tmp - mov \rp, #0x00009000 - orr \rv, \rp, #0xf0000000 @ virtual base - orr \rp, \rp, #0x10000000 - .endm - -#include -- cgit v1.1 From 15bc1fe67f66644c8093cc2d3304217d1c7de797 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Thu, 14 Mar 2013 17:32:59 +0100 Subject: ARM: cns3xxx: enable multiplatform support This moves the cns3xxx configuration option inside of ARCH_MULTIPLATFORM, since there is no reason for not doing it now. We can then also remove the three header files that become obsolete. Signed-off-by: Arnd Bergmann --- arch/arm/Kconfig | 12 ------ arch/arm/configs/cns3420vb_defconfig | 2 + arch/arm/mach-cns3xxx/Kconfig | 11 +++++ arch/arm/mach-cns3xxx/include/mach/timex.h | 12 ------ arch/arm/mach-cns3xxx/include/mach/uncompress.h | 53 ------------------------- 5 files changed, 13 insertions(+), 77 deletions(-) delete mode 100644 arch/arm/mach-cns3xxx/include/mach/timex.h delete mode 100644 arch/arm/mach-cns3xxx/include/mach/uncompress.h (limited to 'arch/arm') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 8bad33e..78ffcc6 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -382,18 +382,6 @@ config ARCH_BCM2835 This enables support for the Broadcom BCM2835 SoC. This SoC is use in the Raspberry Pi, and Roku 2 devices. -config ARCH_CNS3XXX - bool "Cavium Networks CNS3XXX family" - select ARM_GIC - select CPU_V6K - select GENERIC_CLOCKEVENTS - select MIGHT_HAVE_CACHE_L2X0 - select MIGHT_HAVE_PCI - select PCI_DOMAINS if PCI - select SPARSE_IRQ - help - Support for Cavium Networks CNS3XXX platform. - config ARCH_CLPS711X bool "Cirrus Logic CLPS711x/EP721x/EP731x-based" select ARCH_REQUIRE_GPIOLIB diff --git a/arch/arm/configs/cns3420vb_defconfig b/arch/arm/configs/cns3420vb_defconfig index b79e984..b1ff5cd 100644 --- a/arch/arm/configs/cns3420vb_defconfig +++ b/arch/arm/configs/cns3420vb_defconfig @@ -19,6 +19,8 @@ CONFIG_MODULE_FORCE_UNLOAD=y CONFIG_MODVERSIONS=y # CONFIG_BLK_DEV_BSG is not set CONFIG_IOSCHED_CFQ=m +CONFIG_ARCH_MULTI_V6=y +#CONFIG_ARCH_MULTI_V7 is not set CONFIG_ARCH_CNS3XXX=y CONFIG_MACH_CNS3420VB=y CONFIG_DEBUG_CNS3XXX=y diff --git a/arch/arm/mach-cns3xxx/Kconfig b/arch/arm/mach-cns3xxx/Kconfig index 9ebfcc4..5720f3d 100644 --- a/arch/arm/mach-cns3xxx/Kconfig +++ b/arch/arm/mach-cns3xxx/Kconfig @@ -1,3 +1,14 @@ +config ARCH_CNS3XXX + bool "Cavium Networks CNS3XXX family" if ARCH_MULTI_V6 + select ARM_GIC + select CPU_V6K + select GENERIC_CLOCKEVENTS + select MIGHT_HAVE_CACHE_L2X0 + select MIGHT_HAVE_PCI + select PCI_DOMAINS if PCI + help + Support for Cavium Networks CNS3XXX platform. + menu "CNS3XXX platform type" depends on ARCH_CNS3XXX diff --git a/arch/arm/mach-cns3xxx/include/mach/timex.h b/arch/arm/mach-cns3xxx/include/mach/timex.h deleted file mode 100644 index 1fd0421..0000000 --- a/arch/arm/mach-cns3xxx/include/mach/timex.h +++ /dev/null @@ -1,12 +0,0 @@ -/* - * Cavium Networks architecture timex specifications - * - * Copyright 2003 ARM Limited - * Copyright 2008 Cavium Networks - * - * This file is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License, Version 2, as - * published by the Free Software Foundation. - */ - -#define CLOCK_TICK_RATE (50000000 / 16) diff --git a/arch/arm/mach-cns3xxx/include/mach/uncompress.h b/arch/arm/mach-cns3xxx/include/mach/uncompress.h deleted file mode 100644 index e2c642c1c..0000000 --- a/arch/arm/mach-cns3xxx/include/mach/uncompress.h +++ /dev/null @@ -1,53 +0,0 @@ -/* - * Copyright 2003 ARM Limited - * Copyright 2008 Cavium Networks - * - * This file is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License, Version 2, as - * published by the Free Software Foundation. - */ - -#include -#include "cns3xxx.h" - -#define AMBA_UART_DR(base) (*(volatile unsigned char *)((base) + 0x00)) -#define AMBA_UART_LCRH(base) (*(volatile unsigned char *)((base) + 0x2c)) -#define AMBA_UART_CR(base) (*(volatile unsigned char *)((base) + 0x30)) -#define AMBA_UART_FR(base) (*(volatile unsigned char *)((base) + 0x18)) - -/* - * Return the UART base address - */ -static inline unsigned long get_uart_base(void) -{ - if (machine_is_cns3420vb()) - return CNS3XXX_UART0_BASE; - else - return 0; -} - -/* - * This does not append a newline - */ -static inline void putc(int c) -{ - unsigned long base = get_uart_base(); - - while (AMBA_UART_FR(base) & (1 << 5)) - barrier(); - - AMBA_UART_DR(base) = c; -} - -static inline void flush(void) -{ - unsigned long base = get_uart_base(); - - while (AMBA_UART_FR(base) & (1 << 3)) - barrier(); -} - -/* - * nothing to do - */ -#define arch_decomp_setup() -- cgit v1.1 From 415f59142d9d9dd023deaeb3b4dfc1aecdd3983c Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Thu, 14 Mar 2013 22:27:32 +0100 Subject: ARM: cns3xxx: initial DT support This adds very minimal support for booting cns3xxx using a device tree. It should support the same devices that cns3420vb provides but gets them from the DT. All devices that don't have their own binding are probed through auxdata. This is completely untested and likely incomplete. Booting through ATAGS is made optional, so it can be turned off by anybody who has a DTB file. Signed-off-by: Arnd Bergmann --- arch/arm/mach-cns3xxx/Kconfig | 1 + arch/arm/mach-cns3xxx/Makefile | 8 +-- arch/arm/mach-cns3xxx/core.c | 119 +++++++++++++++++++++++++++++++++++++++++ 3 files changed, 125 insertions(+), 3 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-cns3xxx/Kconfig b/arch/arm/mach-cns3xxx/Kconfig index 5720f3d..dbf0df8 100644 --- a/arch/arm/mach-cns3xxx/Kconfig +++ b/arch/arm/mach-cns3xxx/Kconfig @@ -14,6 +14,7 @@ menu "CNS3XXX platform type" config MACH_CNS3420VB bool "Support for CNS3420 Validation Board" + depends on ATAGS help Include support for the Cavium Networks CNS3420 MPCore Platform Baseboard. diff --git a/arch/arm/mach-cns3xxx/Makefile b/arch/arm/mach-cns3xxx/Makefile index 11033f1..a1ff108 100644 --- a/arch/arm/mach-cns3xxx/Makefile +++ b/arch/arm/mach-cns3xxx/Makefile @@ -1,3 +1,5 @@ -obj-$(CONFIG_ARCH_CNS3XXX) += core.o pm.o devices.o -obj-$(CONFIG_PCI) += pcie.o -obj-$(CONFIG_MACH_CNS3420VB) += cns3420vb.o +obj-$(CONFIG_ARCH_CNS3XXX) += cns3xxx.o +cns3xxx-y += core.o pm.o +cns3xxx-$(CONFIG_ATAGS) += devices.o +cns3xxx-$(CONFIG_PCI) += pcie.o +cns3xxx-$(CONFIG_MACH_CNS3420VB) += cns3420vb.o diff --git a/arch/arm/mach-cns3xxx/core.c b/arch/arm/mach-cns3xxx/core.c index 012ffdb..49e657c 100644 --- a/arch/arm/mach-cns3xxx/core.c +++ b/arch/arm/mach-cns3xxx/core.c @@ -13,12 +13,18 @@ #include #include #include +#include +#include +#include +#include +#include #include #include #include #include #include "cns3xxx.h" #include "core.h" +#include "pm.h" static struct map_desc cns3xxx_io_desc[] __initdata = { { @@ -276,3 +282,116 @@ void __init cns3xxx_l2x0_init(void) } #endif /* CONFIG_CACHE_L2X0 */ + +static int csn3xxx_usb_power_on(struct platform_device *pdev) +{ + /* + * EHCI and OHCI share the same clock and power, + * resetting twice would cause the 1st controller been reset. + * Therefore only do power up at the first up device, and + * power down at the last down device. + * + * Set USB AHB INCR length to 16 + */ + if (atomic_inc_return(&usb_pwr_ref) == 1) { + cns3xxx_pwr_power_up(1 << PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_USB); + cns3xxx_pwr_clk_en(1 << PM_CLK_GATE_REG_OFFSET_USB_HOST); + cns3xxx_pwr_soft_rst(1 << PM_SOFT_RST_REG_OFFST_USB_HOST); + __raw_writel((__raw_readl(MISC_CHIP_CONFIG_REG) | (0X2 << 24)), + MISC_CHIP_CONFIG_REG); + } + + return 0; +} + +static void csn3xxx_usb_power_off(struct platform_device *pdev) +{ + /* + * EHCI and OHCI share the same clock and power, + * resetting twice would cause the 1st controller been reset. + * Therefore only do power up at the first up device, and + * power down at the last down device. + */ + if (atomic_dec_return(&usb_pwr_ref) == 0) + cns3xxx_pwr_clk_dis(1 << PM_CLK_GATE_REG_OFFSET_USB_HOST); +} + +static struct usb_ehci_pdata cns3xxx_usb_ehci_pdata = { + .power_on = csn3xxx_usb_power_on, + .power_off = csn3xxx_usb_power_off, +}; + +static struct usb_ohci_pdata cns3xxx_usb_ohci_pdata = { + .num_ports = 1, + .power_on = csn3xxx_usb_power_on, + .power_off = csn3xxx_usb_power_off, +}; + +static struct of_dev_auxdata cns3xxx_auxdata[] __initconst = { + { "intel,usb-ehci", CNS3XXX_USB_BASE, "ehci-platform", &cns3xxx_usb_ehci_pdata }, + { "intel,usb-ohci", CNS3XXX_USB_OHCI_BASE, "ohci-platform", &cns3xxx_usb_ohci_pdata }, + { "cavium,cns3420-ahci", CNS3XXX_SATA2_BASE, "ahci", NULL }, + { "cavium,cns3420-sdhci", CNS3XXX_SDIO_BASE, "ahci", NULL }, + {}, +}; + +static void __init cns3xxx_init(void) +{ + struct device_node *dn; + + cns3xxx_l2x0_init(); + + dn = of_find_compatible_node(NULL, NULL, "cavium,cns3420-ahci"); + if (of_device_is_available(dn)) { + u32 tmp; + + tmp = __raw_readl(MISC_SATA_POWER_MODE); + tmp |= 0x1 << 16; /* Disable SATA PHY 0 from SLUMBER Mode */ + tmp |= 0x1 << 17; /* Disable SATA PHY 1 from SLUMBER Mode */ + __raw_writel(tmp, MISC_SATA_POWER_MODE); + + /* Enable SATA PHY */ + cns3xxx_pwr_power_up(0x1 << PM_PLL_HM_PD_CTRL_REG_OFFSET_SATA_PHY0); + cns3xxx_pwr_power_up(0x1 << PM_PLL_HM_PD_CTRL_REG_OFFSET_SATA_PHY1); + + /* Enable SATA Clock */ + cns3xxx_pwr_clk_en(0x1 << PM_CLK_GATE_REG_OFFSET_SATA); + + /* De-Asscer SATA Reset */ + cns3xxx_pwr_soft_rst(CNS3XXX_PWR_SOFTWARE_RST(SATA)); + } + + dn = of_find_compatible_node(NULL, NULL, "cavium,cns3420-sdhci"); + if (of_device_is_available(dn)) { + u32 __iomem *gpioa = IOMEM(CNS3XXX_MISC_BASE_VIRT + 0x0014); + u32 gpioa_pins = __raw_readl(gpioa); + + /* MMC/SD pins share with GPIOA */ + gpioa_pins |= 0x1fff0004; + __raw_writel(gpioa_pins, gpioa); + + cns3xxx_pwr_clk_en(CNS3XXX_PWR_CLK_EN(SDIO)); + cns3xxx_pwr_soft_rst(CNS3XXX_PWR_SOFTWARE_RST(SDIO)); + } + + pm_power_off = cns3xxx_power_off; + + of_platform_populate(NULL, of_default_bus_match_table, + cns3xxx_auxdata, NULL); +} + +static const char *cns3xxx_dt_compat[] __initdata = { + "cavium,cns3410", + "cavium,cns3420", + NULL, +}; + +DT_MACHINE_START(CNS3XXX_DT, "Cavium Networks CNS3xxx") + .dt_compat = cns3xxx_dt_compat, + .nr_irqs = NR_IRQS_CNS3XXX, + .map_io = cns3xxx_map_io, + .init_irq = cns3xxx_init_irq, + .init_time = cns3xxx_timer_init, + .init_machine = cns3xxx_init, + .restart = cns3xxx_restart, +MACHINE_END -- cgit v1.1 From ae55afce201cb7d1bb05727834ba9d8255c360c9 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Tue, 19 Mar 2013 22:01:25 +0100 Subject: ARM: nomadik: hide MACH_NOMADIK_8815NHK in Kconfig The nomadik multiplatform support made it possible to select MACH_NOMADIK_8815NHK without selecting ARCH_NOMADIK, which leads to build errors when we also select ARMv6/v7 targets. Adding the ifdef here restores the intended behavior. Signed-off-by: Arnd Bergmann --- arch/arm/mach-nomadik/Kconfig | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/mach-nomadik/Kconfig b/arch/arm/mach-nomadik/Kconfig index 954f0e3..3213bad 100644 --- a/arch/arm/mach-nomadik/Kconfig +++ b/arch/arm/mach-nomadik/Kconfig @@ -17,6 +17,7 @@ config ARCH_NOMADIK help Support for the Nomadik platform by ST-Ericsson +if ARCH_NOMADIK menu "Nomadik boards" config MACH_NOMADIK_8815NHK @@ -26,6 +27,7 @@ config MACH_NOMADIK_8815NHK select I2C_ALGOBIT endmenu +endif config NOMADIK_8815 depends on ARCH_NOMADIK -- cgit v1.1 From cde35bd027023b052316c14ae3fc01e2f487a6ab Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Tue, 19 Mar 2013 22:03:13 +0100 Subject: ARM: spear: build hotplug.o for armv7-a The hotplug.c file uses assembly instructions that are only available on ARMv7 but not on ARMv6. This is ok because we know that code will only run on arm ARMv7 SPEARr13xx, but it produces build errors when we also enable one of the ARMv6 targets in a multiplatform configuration. Signed-off-by: Arnd Bergmann --- arch/arm/mach-spear/Makefile | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/mach-spear/Makefile b/arch/arm/mach-spear/Makefile index dc9ce80..af9bffb 100644 --- a/arch/arm/mach-spear/Makefile +++ b/arch/arm/mach-spear/Makefile @@ -22,3 +22,5 @@ obj-$(CONFIG_MACH_SPEAR320) += spear320.o obj-$(CONFIG_ARCH_SPEAR6XX) += spear6xx.o obj-$(CONFIG_ARCH_SPEAR6XX) += pl080.o + +CFLAGS_hotplug.o += -march=armv7-a -- cgit v1.1 From 67d71344fd09223820eb9de39b597ec29f035e89 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Tue, 19 Mar 2013 15:31:08 +0100 Subject: ARM: sirf: fix prima2 interrupt lookup We must not read the interrupts property manually but instead use irq_of_parse_and_map() to guarantee that we get the correct interrupt number once we stop using the legacy IRQ domain. Signed-off-by: Arnd Bergmann Tested-by: Barry Song --- arch/arm/mach-prima2/timer-prima2.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-prima2/timer-prima2.c b/arch/arm/mach-prima2/timer-prima2.c index 6da584f..9829083 100644 --- a/arch/arm/mach-prima2/timer-prima2.c +++ b/arch/arm/mach-prima2/timer-prima2.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #include #include @@ -223,7 +224,6 @@ static struct of_device_id timer_ids[] = { static void __init sirfsoc_of_timer_map(void) { struct device_node *np; - const unsigned int *intspec; np = of_find_matching_node(NULL, timer_ids); if (!np) @@ -233,9 +233,7 @@ static void __init sirfsoc_of_timer_map(void) panic("unable to map timer cpu registers\n"); /* Get the interrupts property */ - intspec = of_get_property(np, "interrupts", NULL); - BUG_ON(!intspec); - sirfsoc_timer_irq.irq = be32_to_cpup(intspec); + sirfsoc_timer_irq.irq = irq_of_parse_and_map(np, 0); of_node_put(np); } -- cgit v1.1 From 60dbd7680f069c07525a825d805fd2644eae92e6 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Tue, 19 Mar 2013 11:21:44 +0100 Subject: ARM: sirf: move irq driver to drivers/irqchip This updates the irqchip drier for prima2 to the current practices by moving it into drivers/irqchip and integrating it into the irqchip_init infrastructure. We also now use a linear irq domain as a preparation for sparse IRQ suport. Signed-off-by: Arnd Bergmann Cc: Thomas Gleixner --- arch/arm/mach-prima2/Makefile | 1 - arch/arm/mach-prima2/common.c | 10 +--- arch/arm/mach-prima2/irq.c | 129 ------------------------------------------ 3 files changed, 2 insertions(+), 138 deletions(-) delete mode 100644 arch/arm/mach-prima2/irq.c (limited to 'arch/arm') diff --git a/arch/arm/mach-prima2/Makefile b/arch/arm/mach-prima2/Makefile index bfe360c..5fdff7e 100644 --- a/arch/arm/mach-prima2/Makefile +++ b/arch/arm/mach-prima2/Makefile @@ -4,7 +4,6 @@ obj-y += rtciobrg.o obj-$(CONFIG_DEBUG_LL) += lluart.o obj-$(CONFIG_CACHE_L2X0) += l2x0.o obj-$(CONFIG_SUSPEND) += pm.o sleep.o -obj-$(CONFIG_SIRF_IRQ) += irq.o obj-$(CONFIG_SMP) += platsmp.o headsmp.o obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o obj-$(CONFIG_ARCH_PRIMA2) += timer-prima2.o diff --git a/arch/arm/mach-prima2/common.c b/arch/arm/mach-prima2/common.c index 72efb4f..15c14df 100644 --- a/arch/arm/mach-prima2/common.c +++ b/arch/arm/mach-prima2/common.c @@ -46,11 +46,8 @@ static const char *atlas6_dt_match[] __initdata = { DT_MACHINE_START(ATLAS6_DT, "Generic ATLAS6 (Flattened Device Tree)") /* Maintainer: Barry Song */ .map_io = sirfsoc_map_io, - .init_irq = sirfsoc_of_irq_init, + .init_irq = irqchip_init, .init_time = sirfsoc_prima2_timer_init, -#ifdef CONFIG_MULTI_IRQ_HANDLER - .handle_irq = sirfsoc_handle_irq, -#endif .init_machine = sirfsoc_mach_init, .init_late = sirfsoc_init_late, .dt_compat = atlas6_dt_match, @@ -67,11 +64,8 @@ static const char *prima2_dt_match[] __initdata = { DT_MACHINE_START(PRIMA2_DT, "Generic PRIMA2 (Flattened Device Tree)") /* Maintainer: Barry Song */ .map_io = sirfsoc_map_io, - .init_irq = sirfsoc_of_irq_init, + .init_irq = irqchip_init, .init_time = sirfsoc_prima2_timer_init, -#ifdef CONFIG_MULTI_IRQ_HANDLER - .handle_irq = sirfsoc_handle_irq, -#endif .dma_zone_size = SZ_256M, .init_machine = sirfsoc_mach_init, .init_late = sirfsoc_init_late, diff --git a/arch/arm/mach-prima2/irq.c b/arch/arm/mach-prima2/irq.c deleted file mode 100644 index 6c0f3e9..0000000 --- a/arch/arm/mach-prima2/irq.c +++ /dev/null @@ -1,129 +0,0 @@ -/* - * interrupt controller support for CSR SiRFprimaII - * - * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company. - * - * Licensed under GPLv2 or later. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#define SIRFSOC_INT_RISC_MASK0 0x0018 -#define SIRFSOC_INT_RISC_MASK1 0x001C -#define SIRFSOC_INT_RISC_LEVEL0 0x0020 -#define SIRFSOC_INT_RISC_LEVEL1 0x0024 -#define SIRFSOC_INIT_IRQ_ID 0x0038 - -void __iomem *sirfsoc_intc_base; - -static __init void -sirfsoc_alloc_gc(void __iomem *base, unsigned int irq_start, unsigned int num) -{ - struct irq_chip_generic *gc; - struct irq_chip_type *ct; - - gc = irq_alloc_generic_chip("SIRFINTC", 1, irq_start, base, handle_level_irq); - ct = gc->chip_types; - - ct->chip.irq_mask = irq_gc_mask_clr_bit; - ct->chip.irq_unmask = irq_gc_mask_set_bit; - ct->regs.mask = SIRFSOC_INT_RISC_MASK0; - - irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE, IRQ_NOREQUEST, 0); -} - -static __init void sirfsoc_irq_init(void) -{ - sirfsoc_alloc_gc(sirfsoc_intc_base, 0, 32); - sirfsoc_alloc_gc(sirfsoc_intc_base + 4, 32, - SIRFSOC_INTENAL_IRQ_END + 1 - 32); - - writel_relaxed(0, sirfsoc_intc_base + SIRFSOC_INT_RISC_LEVEL0); - writel_relaxed(0, sirfsoc_intc_base + SIRFSOC_INT_RISC_LEVEL1); - - writel_relaxed(0, sirfsoc_intc_base + SIRFSOC_INT_RISC_MASK0); - writel_relaxed(0, sirfsoc_intc_base + SIRFSOC_INT_RISC_MASK1); -} - -asmlinkage void __exception_irq_entry sirfsoc_handle_irq(struct pt_regs *regs) -{ - u32 irqstat, irqnr; - - irqstat = readl_relaxed(sirfsoc_intc_base + SIRFSOC_INIT_IRQ_ID); - irqnr = irqstat & 0xff; - - handle_IRQ(irqnr, regs); -} - -static struct of_device_id intc_ids[] = { - { .compatible = "sirf,prima2-intc" }, - {}, -}; - -void __init sirfsoc_of_irq_init(void) -{ - struct device_node *np; - - np = of_find_matching_node(NULL, intc_ids); - if (!np) - return; - - sirfsoc_intc_base = of_iomap(np, 0); - if (!sirfsoc_intc_base) - panic("unable to map intc cpu registers\n"); - - irq_domain_add_legacy(np, SIRFSOC_INTENAL_IRQ_END + 1, 0, 0, - &irq_domain_simple_ops, NULL); - - of_node_put(np); - - sirfsoc_irq_init(); -} - -struct sirfsoc_irq_status { - u32 mask0; - u32 mask1; - u32 level0; - u32 level1; -}; - -static struct sirfsoc_irq_status sirfsoc_irq_st; - -static int sirfsoc_irq_suspend(void) -{ - sirfsoc_irq_st.mask0 = readl_relaxed(sirfsoc_intc_base + SIRFSOC_INT_RISC_MASK0); - sirfsoc_irq_st.mask1 = readl_relaxed(sirfsoc_intc_base + SIRFSOC_INT_RISC_MASK1); - sirfsoc_irq_st.level0 = readl_relaxed(sirfsoc_intc_base + SIRFSOC_INT_RISC_LEVEL0); - sirfsoc_irq_st.level1 = readl_relaxed(sirfsoc_intc_base + SIRFSOC_INT_RISC_LEVEL1); - - return 0; -} - -static void sirfsoc_irq_resume(void) -{ - writel_relaxed(sirfsoc_irq_st.mask0, sirfsoc_intc_base + SIRFSOC_INT_RISC_MASK0); - writel_relaxed(sirfsoc_irq_st.mask1, sirfsoc_intc_base + SIRFSOC_INT_RISC_MASK1); - writel_relaxed(sirfsoc_irq_st.level0, sirfsoc_intc_base + SIRFSOC_INT_RISC_LEVEL0); - writel_relaxed(sirfsoc_irq_st.level1, sirfsoc_intc_base + SIRFSOC_INT_RISC_LEVEL1); -} - -static struct syscore_ops sirfsoc_irq_syscore_ops = { - .suspend = sirfsoc_irq_suspend, - .resume = sirfsoc_irq_resume, -}; - -static int __init sirfsoc_irq_pm_init(void) -{ - register_syscore_ops(&sirfsoc_irq_syscore_ops); - return 0; -} -device_initcall(sirfsoc_irq_pm_init); -- cgit v1.1 From 630be7ea2f2d0c2ee5662308297b77087da2ace2 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Tue, 19 Mar 2013 12:19:01 +0100 Subject: ARM: sirf: enable sparse IRQ Now that both irqchips for sirf are converted to not rely on legacy domains, let's move all of the platform over to sparse IRQ. Signed-off-by: Arnd Bergmann --- arch/arm/Kconfig | 1 + arch/arm/mach-prima2/common.c | 2 ++ arch/arm/mach-prima2/include/mach/irqs.h | 17 ----------------- 3 files changed, 3 insertions(+), 17 deletions(-) delete mode 100644 arch/arm/mach-prima2/include/mach/irqs.h (limited to 'arch/arm') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 5bfd584..c674b32 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -427,6 +427,7 @@ config ARCH_SIRF select PINCTRL select PINCTRL_SIRF select USE_OF + select SPARSE_IRQ help Support for CSR SiRFprimaII/Marco/Polo platforms diff --git a/arch/arm/mach-prima2/common.c b/arch/arm/mach-prima2/common.c index 15c14df..31f43ea 100644 --- a/arch/arm/mach-prima2/common.c +++ b/arch/arm/mach-prima2/common.c @@ -45,6 +45,7 @@ static const char *atlas6_dt_match[] __initdata = { DT_MACHINE_START(ATLAS6_DT, "Generic ATLAS6 (Flattened Device Tree)") /* Maintainer: Barry Song */ + .nr_irqs = 128, .map_io = sirfsoc_map_io, .init_irq = irqchip_init, .init_time = sirfsoc_prima2_timer_init, @@ -63,6 +64,7 @@ static const char *prima2_dt_match[] __initdata = { DT_MACHINE_START(PRIMA2_DT, "Generic PRIMA2 (Flattened Device Tree)") /* Maintainer: Barry Song */ + .nr_irqs = 128, .map_io = sirfsoc_map_io, .init_irq = irqchip_init, .init_time = sirfsoc_prima2_timer_init, diff --git a/arch/arm/mach-prima2/include/mach/irqs.h b/arch/arm/mach-prima2/include/mach/irqs.h deleted file mode 100644 index b778a0f..0000000 --- a/arch/arm/mach-prima2/include/mach/irqs.h +++ /dev/null @@ -1,17 +0,0 @@ -/* - * arch/arm/mach-prima2/include/mach/irqs.h - * - * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company. - * - * Licensed under GPLv2 or later. - */ - -#ifndef __ASM_ARCH_IRQS_H -#define __ASM_ARCH_IRQS_H - -#define SIRFSOC_INTENAL_IRQ_START 0 -#define SIRFSOC_INTENAL_IRQ_END 127 -#define SIRFSOC_GPIO_IRQ_START (SIRFSOC_INTENAL_IRQ_END + 1) -#define NR_IRQS 288 - -#endif -- cgit v1.1 From 67bdb28718ae6dbdfbfa541161529acfa0f3c137 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Tue, 19 Mar 2013 13:52:14 +0100 Subject: ARM: sirf: move debug-macro.S to include/debug/sirf.S The new style ll_debug implementation for multiplatform requires the platform glue to be in include/debug, so let's move it there to separate the debugging logic from the platform code. Signed-off-by: Arnd Bergmann Tested-by: Barry Song --- arch/arm/Kconfig.debug | 1 + arch/arm/include/debug/sirf.S | 42 +++++++++++++++++++++++++ arch/arm/mach-prima2/include/mach/debug-macro.S | 29 ----------------- arch/arm/mach-prima2/lluart.c | 12 ++++++- 4 files changed, 54 insertions(+), 30 deletions(-) create mode 100644 arch/arm/include/debug/sirf.S delete mode 100644 arch/arm/mach-prima2/include/mach/debug-macro.S (limited to 'arch/arm') diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug index acdddda..a69334d 100644 --- a/arch/arm/Kconfig.debug +++ b/arch/arm/Kconfig.debug @@ -592,6 +592,7 @@ config DEBUG_LL_INCLUDE default "debug/mvebu.S" if DEBUG_MVEBU_UART default "debug/omap2plus.S" if DEBUG_OMAP2PLUS_UART default "debug/picoxcell.S" if DEBUG_PICOXCELL_UART + default "debug/sirf.S" if DEBUG_SIRFPRIMA2_UART1 || DEBUG_SIRFMARCO_UART1 default "debug/socfpga.S" if DEBUG_SOCFPGA_UART default "debug/sunxi.S" if DEBUG_SUNXI_UART0 || DEBUG_SUNXI_UART1 default "debug/vexpress.S" if DEBUG_VEXPRESS_UART0_DETECT || \ diff --git a/arch/arm/include/debug/sirf.S b/arch/arm/include/debug/sirf.S new file mode 100644 index 0000000..dbf250c --- /dev/null +++ b/arch/arm/include/debug/sirf.S @@ -0,0 +1,42 @@ +/* + * arch/arm/mach-prima2/include/mach/debug-macro.S + * + * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company. + * + * Licensed under GPLv2 or later. + */ + +#if defined(CONFIG_DEBUG_SIRFPRIMA2_UART1) +#define SIRFSOC_UART1_PA_BASE 0xb0060000 +#elif defined(CONFIG_DEBUG_SIRFMARCO_UART1) +#define SIRFSOC_UART1_PA_BASE 0xcc060000 +#else +#define SIRFSOC_UART1_PA_BASE 0 +#endif + +#define SIRFSOC_UART1_VA_BASE 0xFEC60000 + +#define SIRFSOC_UART_TXFIFO_STATUS 0x0114 +#define SIRFSOC_UART_TXFIFO_DATA 0x0118 + +#define SIRFSOC_UART1_TXFIFO_FULL (1 << 5) +#define SIRFSOC_UART1_TXFIFO_EMPTY (1 << 6) + + .macro addruart, rp, rv, tmp + ldr \rp, =SIRFSOC_UART1_PA_BASE @ physical + ldr \rv, =SIRFSOC_UART1_VA_BASE @ virtual + .endm + + .macro senduart,rd,rx + str \rd, [\rx, #SIRFSOC_UART_TXFIFO_DATA] + .endm + + .macro busyuart,rd,rx + .endm + + .macro waituart,rd,rx +1001: ldr \rd, [\rx, #SIRFSOC_UART_TXFIFO_STATUS] + tst \rd, #SIRFSOC_UART1_TXFIFO_EMPTY + beq 1001b + .endm + diff --git a/arch/arm/mach-prima2/include/mach/debug-macro.S b/arch/arm/mach-prima2/include/mach/debug-macro.S deleted file mode 100644 index cd97492..0000000 --- a/arch/arm/mach-prima2/include/mach/debug-macro.S +++ /dev/null @@ -1,29 +0,0 @@ -/* - * arch/arm/mach-prima2/include/mach/debug-macro.S - * - * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company. - * - * Licensed under GPLv2 or later. - */ - -#include -#include - - .macro addruart, rp, rv, tmp - ldr \rp, =SIRFSOC_UART1_PA_BASE @ physical - ldr \rv, =SIRFSOC_UART1_VA_BASE @ virtual - .endm - - .macro senduart,rd,rx - str \rd, [\rx, #SIRFSOC_UART_TXFIFO_DATA] - .endm - - .macro busyuart,rd,rx - .endm - - .macro waituart,rd,rx -1001: ldr \rd, [\rx, #SIRFSOC_UART_TXFIFO_STATUS] - tst \rd, #SIRFSOC_UART1_TXFIFO_EMPTY - beq 1001b - .endm - diff --git a/arch/arm/mach-prima2/lluart.c b/arch/arm/mach-prima2/lluart.c index a89f9b3..7222481 100644 --- a/arch/arm/mach-prima2/lluart.c +++ b/arch/arm/mach-prima2/lluart.c @@ -10,7 +10,17 @@ #include #include #include -#include + +#if defined(CONFIG_DEBUG_SIRFPRIMA2_UART1) +#define SIRFSOC_UART1_PA_BASE 0xb0060000 +#elif defined(CONFIG_DEBUG_SIRFMARCO_UART1) +#define SIRFSOC_UART1_PA_BASE 0xcc060000 +#else +#define SIRFSOC_UART1_PA_BASE 0 +#endif + +#define SIRFSOC_UART1_VA_BASE SIRFSOC_VA(0x060000) +#define SIRFSOC_UART1_SIZE SZ_4K void __init sirfsoc_map_lluart(void) { -- cgit v1.1 From 275786b71d42bb54c03c15197128d7cb05d4dd8b Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Tue, 19 Mar 2013 15:27:22 +0100 Subject: ARM: sirf: use clocksource_of infrastructure This moves the two sirf clocksource drivers to drivers/clocksource and integrates them into the framework for locating the clock sources automatically. Signed-off-by: Arnd Bergmann Tested-by: Barry Song Cc: John Stultz Cc: Thomas Gleixner --- arch/arm/mach-prima2/Makefile | 2 - arch/arm/mach-prima2/common.c | 14 +- arch/arm/mach-prima2/common.h | 3 - arch/arm/mach-prima2/timer-marco.c | 316 ------------------------------------ arch/arm/mach-prima2/timer-prima2.c | 239 --------------------------- 5 files changed, 11 insertions(+), 563 deletions(-) delete mode 100644 arch/arm/mach-prima2/timer-marco.c delete mode 100644 arch/arm/mach-prima2/timer-prima2.c (limited to 'arch/arm') diff --git a/arch/arm/mach-prima2/Makefile b/arch/arm/mach-prima2/Makefile index 5fdff7e..52ac738 100644 --- a/arch/arm/mach-prima2/Makefile +++ b/arch/arm/mach-prima2/Makefile @@ -6,5 +6,3 @@ obj-$(CONFIG_CACHE_L2X0) += l2x0.o obj-$(CONFIG_SUSPEND) += pm.o sleep.o obj-$(CONFIG_SMP) += platsmp.o headsmp.o obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o -obj-$(CONFIG_ARCH_PRIMA2) += timer-prima2.o -obj-$(CONFIG_ARCH_MARCO) += timer-marco.o diff --git a/arch/arm/mach-prima2/common.c b/arch/arm/mach-prima2/common.c index 31f43ea..4f94cd8 100644 --- a/arch/arm/mach-prima2/common.c +++ b/arch/arm/mach-prima2/common.c @@ -6,6 +6,7 @@ * Licensed under GPLv2 or later. */ +#include #include #include #include @@ -31,6 +32,13 @@ void __init sirfsoc_init_late(void) sirfsoc_pm_init(); } +static __init void sirfsoc_init_time(void) +{ + /* initialize clocking early, we want to set the OS timer */ + sirfsoc_of_clk_init(); + clocksource_of_init(); +} + static __init void sirfsoc_map_io(void) { sirfsoc_map_lluart(); @@ -48,7 +56,7 @@ DT_MACHINE_START(ATLAS6_DT, "Generic ATLAS6 (Flattened Device Tree)") .nr_irqs = 128, .map_io = sirfsoc_map_io, .init_irq = irqchip_init, - .init_time = sirfsoc_prima2_timer_init, + .init_time = sirfsoc_init_time, .init_machine = sirfsoc_mach_init, .init_late = sirfsoc_init_late, .dt_compat = atlas6_dt_match, @@ -67,7 +75,7 @@ DT_MACHINE_START(PRIMA2_DT, "Generic PRIMA2 (Flattened Device Tree)") .nr_irqs = 128, .map_io = sirfsoc_map_io, .init_irq = irqchip_init, - .init_time = sirfsoc_prima2_timer_init, + .init_time = sirfsoc_init_time, .dma_zone_size = SZ_256M, .init_machine = sirfsoc_mach_init, .init_late = sirfsoc_init_late, @@ -87,7 +95,7 @@ DT_MACHINE_START(MARCO_DT, "Generic MARCO (Flattened Device Tree)") .smp = smp_ops(sirfsoc_smp_ops), .map_io = sirfsoc_map_io, .init_irq = irqchip_init, - .init_time = sirfsoc_marco_timer_init, + .init_time = sirfsoc_init_time, .init_machine = sirfsoc_mach_init, .init_late = sirfsoc_init_late, .dt_compat = marco_dt_match, diff --git a/arch/arm/mach-prima2/common.h b/arch/arm/mach-prima2/common.h index b7c26b6..54262cf 100644 --- a/arch/arm/mach-prima2/common.h +++ b/arch/arm/mach-prima2/common.h @@ -13,9 +13,6 @@ #include #include -extern void sirfsoc_prima2_timer_init(void); -extern void sirfsoc_marco_timer_init(void); - extern struct smp_operations sirfsoc_smp_ops; extern void sirfsoc_secondary_startup(void); extern void sirfsoc_cpu_die(unsigned int cpu); diff --git a/arch/arm/mach-prima2/timer-marco.c b/arch/arm/mach-prima2/timer-marco.c deleted file mode 100644 index f4eea2e..0000000 --- a/arch/arm/mach-prima2/timer-marco.c +++ /dev/null @@ -1,316 +0,0 @@ -/* - * System timer for CSR SiRFprimaII - * - * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company. - * - * Licensed under GPLv2 or later. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "common.h" - -#define SIRFSOC_TIMER_32COUNTER_0_CTRL 0x0000 -#define SIRFSOC_TIMER_32COUNTER_1_CTRL 0x0004 -#define SIRFSOC_TIMER_MATCH_0 0x0018 -#define SIRFSOC_TIMER_MATCH_1 0x001c -#define SIRFSOC_TIMER_COUNTER_0 0x0048 -#define SIRFSOC_TIMER_COUNTER_1 0x004c -#define SIRFSOC_TIMER_INTR_STATUS 0x0060 -#define SIRFSOC_TIMER_WATCHDOG_EN 0x0064 -#define SIRFSOC_TIMER_64COUNTER_CTRL 0x0068 -#define SIRFSOC_TIMER_64COUNTER_LO 0x006c -#define SIRFSOC_TIMER_64COUNTER_HI 0x0070 -#define SIRFSOC_TIMER_64COUNTER_LOAD_LO 0x0074 -#define SIRFSOC_TIMER_64COUNTER_LOAD_HI 0x0078 -#define SIRFSOC_TIMER_64COUNTER_RLATCHED_LO 0x007c -#define SIRFSOC_TIMER_64COUNTER_RLATCHED_HI 0x0080 - -#define SIRFSOC_TIMER_REG_CNT 6 - -static const u32 sirfsoc_timer_reg_list[SIRFSOC_TIMER_REG_CNT] = { - SIRFSOC_TIMER_WATCHDOG_EN, - SIRFSOC_TIMER_32COUNTER_0_CTRL, - SIRFSOC_TIMER_32COUNTER_1_CTRL, - SIRFSOC_TIMER_64COUNTER_CTRL, - SIRFSOC_TIMER_64COUNTER_RLATCHED_LO, - SIRFSOC_TIMER_64COUNTER_RLATCHED_HI, -}; - -static u32 sirfsoc_timer_reg_val[SIRFSOC_TIMER_REG_CNT]; - -static void __iomem *sirfsoc_timer_base; -static void __init sirfsoc_of_timer_map(void); - -/* disable count and interrupt */ -static inline void sirfsoc_timer_count_disable(int idx) -{ - writel_relaxed(readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL + 4 * idx) & ~0x7, - sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL + 4 * idx); -} - -/* enable count and interrupt */ -static inline void sirfsoc_timer_count_enable(int idx) -{ - writel_relaxed(readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL + 4 * idx) | 0x7, - sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL + 4 * idx); -} - -/* timer interrupt handler */ -static irqreturn_t sirfsoc_timer_interrupt(int irq, void *dev_id) -{ - struct clock_event_device *ce = dev_id; - int cpu = smp_processor_id(); - - /* clear timer interrupt */ - writel_relaxed(BIT(cpu), sirfsoc_timer_base + SIRFSOC_TIMER_INTR_STATUS); - - if (ce->mode == CLOCK_EVT_MODE_ONESHOT) - sirfsoc_timer_count_disable(cpu); - - ce->event_handler(ce); - - return IRQ_HANDLED; -} - -/* read 64-bit timer counter */ -static cycle_t sirfsoc_timer_read(struct clocksource *cs) -{ - u64 cycles; - - writel_relaxed((readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL) | - BIT(0)) & ~BIT(1), sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL); - - cycles = readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_RLATCHED_HI); - cycles = (cycles << 32) | readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_RLATCHED_LO); - - return cycles; -} - -static int sirfsoc_timer_set_next_event(unsigned long delta, - struct clock_event_device *ce) -{ - int cpu = smp_processor_id(); - - writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_0 + - 4 * cpu); - writel_relaxed(delta, sirfsoc_timer_base + SIRFSOC_TIMER_MATCH_0 + - 4 * cpu); - - /* enable the tick */ - sirfsoc_timer_count_enable(cpu); - - return 0; -} - -static void sirfsoc_timer_set_mode(enum clock_event_mode mode, - struct clock_event_device *ce) -{ - switch (mode) { - case CLOCK_EVT_MODE_ONESHOT: - /* enable in set_next_event */ - break; - default: - break; - } - - sirfsoc_timer_count_disable(smp_processor_id()); -} - -static void sirfsoc_clocksource_suspend(struct clocksource *cs) -{ - int i; - - for (i = 0; i < SIRFSOC_TIMER_REG_CNT; i++) - sirfsoc_timer_reg_val[i] = readl_relaxed(sirfsoc_timer_base + sirfsoc_timer_reg_list[i]); -} - -static void sirfsoc_clocksource_resume(struct clocksource *cs) -{ - int i; - - for (i = 0; i < SIRFSOC_TIMER_REG_CNT - 2; i++) - writel_relaxed(sirfsoc_timer_reg_val[i], sirfsoc_timer_base + sirfsoc_timer_reg_list[i]); - - writel_relaxed(sirfsoc_timer_reg_val[SIRFSOC_TIMER_REG_CNT - 2], - sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_LOAD_LO); - writel_relaxed(sirfsoc_timer_reg_val[SIRFSOC_TIMER_REG_CNT - 1], - sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_LOAD_HI); - - writel_relaxed(readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL) | - BIT(1) | BIT(0), sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL); -} - -static struct clock_event_device sirfsoc_clockevent = { - .name = "sirfsoc_clockevent", - .rating = 200, - .features = CLOCK_EVT_FEAT_ONESHOT, - .set_mode = sirfsoc_timer_set_mode, - .set_next_event = sirfsoc_timer_set_next_event, -}; - -static struct clocksource sirfsoc_clocksource = { - .name = "sirfsoc_clocksource", - .rating = 200, - .mask = CLOCKSOURCE_MASK(64), - .flags = CLOCK_SOURCE_IS_CONTINUOUS, - .read = sirfsoc_timer_read, - .suspend = sirfsoc_clocksource_suspend, - .resume = sirfsoc_clocksource_resume, -}; - -static struct irqaction sirfsoc_timer_irq = { - .name = "sirfsoc_timer0", - .flags = IRQF_TIMER | IRQF_NOBALANCING, - .handler = sirfsoc_timer_interrupt, - .dev_id = &sirfsoc_clockevent, -}; - -#ifdef CONFIG_LOCAL_TIMERS - -static struct irqaction sirfsoc_timer1_irq = { - .name = "sirfsoc_timer1", - .flags = IRQF_TIMER | IRQF_NOBALANCING, - .handler = sirfsoc_timer_interrupt, -}; - -static int __cpuinit sirfsoc_local_timer_setup(struct clock_event_device *ce) -{ - /* Use existing clock_event for cpu 0 */ - if (!smp_processor_id()) - return 0; - - ce->irq = sirfsoc_timer1_irq.irq; - ce->name = "local_timer"; - ce->features = sirfsoc_clockevent.features; - ce->rating = sirfsoc_clockevent.rating; - ce->set_mode = sirfsoc_timer_set_mode; - ce->set_next_event = sirfsoc_timer_set_next_event; - ce->shift = sirfsoc_clockevent.shift; - ce->mult = sirfsoc_clockevent.mult; - ce->max_delta_ns = sirfsoc_clockevent.max_delta_ns; - ce->min_delta_ns = sirfsoc_clockevent.min_delta_ns; - - sirfsoc_timer1_irq.dev_id = ce; - BUG_ON(setup_irq(ce->irq, &sirfsoc_timer1_irq)); - irq_set_affinity(sirfsoc_timer1_irq.irq, cpumask_of(1)); - - clockevents_register_device(ce); - return 0; -} - -static void sirfsoc_local_timer_stop(struct clock_event_device *ce) -{ - sirfsoc_timer_count_disable(1); - - remove_irq(sirfsoc_timer1_irq.irq, &sirfsoc_timer1_irq); -} - -static struct local_timer_ops sirfsoc_local_timer_ops __cpuinitdata = { - .setup = sirfsoc_local_timer_setup, - .stop = sirfsoc_local_timer_stop, -}; -#endif /* CONFIG_LOCAL_TIMERS */ - -static void __init sirfsoc_clockevent_init(void) -{ - clockevents_calc_mult_shift(&sirfsoc_clockevent, CLOCK_TICK_RATE, 60); - - sirfsoc_clockevent.max_delta_ns = - clockevent_delta2ns(-2, &sirfsoc_clockevent); - sirfsoc_clockevent.min_delta_ns = - clockevent_delta2ns(2, &sirfsoc_clockevent); - - sirfsoc_clockevent.cpumask = cpumask_of(0); - clockevents_register_device(&sirfsoc_clockevent); -#ifdef CONFIG_LOCAL_TIMERS - local_timer_register(&sirfsoc_local_timer_ops); -#endif -} - -/* initialize the kernel jiffy timer source */ -void __init sirfsoc_marco_timer_init(void) -{ - unsigned long rate; - u32 timer_div; - struct clk *clk; - - /* initialize clocking early, we want to set the OS timer */ - sirfsoc_of_clk_init(); - - /* timer's input clock is io clock */ - clk = clk_get_sys("io", NULL); - - BUG_ON(IS_ERR(clk)); - rate = clk_get_rate(clk); - - BUG_ON(rate < CLOCK_TICK_RATE); - BUG_ON(rate % CLOCK_TICK_RATE); - - sirfsoc_of_timer_map(); - - /* Initialize the timer dividers */ - timer_div = rate / CLOCK_TICK_RATE - 1; - writel_relaxed(timer_div << 16, sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL); - writel_relaxed(timer_div << 16, sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL); - writel_relaxed(timer_div << 16, sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_1_CTRL); - - /* Initialize timer counters to 0 */ - writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_LOAD_LO); - writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_LOAD_HI); - writel_relaxed(readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL) | - BIT(1) | BIT(0), sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL); - writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_0); - writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_1); - - /* Clear all interrupts */ - writel_relaxed(0xFFFF, sirfsoc_timer_base + SIRFSOC_TIMER_INTR_STATUS); - - BUG_ON(clocksource_register_hz(&sirfsoc_clocksource, CLOCK_TICK_RATE)); - - BUG_ON(setup_irq(sirfsoc_timer_irq.irq, &sirfsoc_timer_irq)); - - sirfsoc_clockevent_init(); -} - -static struct of_device_id timer_ids[] = { - { .compatible = "sirf,marco-tick" }, - {}, -}; - -static void __init sirfsoc_of_timer_map(void) -{ - struct device_node *np; - - np = of_find_matching_node(NULL, timer_ids); - if (!np) - return; - sirfsoc_timer_base = of_iomap(np, 0); - if (!sirfsoc_timer_base) - panic("unable to map timer cpu registers\n"); - - sirfsoc_timer_irq.irq = irq_of_parse_and_map(np, 0); - if (!sirfsoc_timer_irq.irq) - panic("No irq passed for timer0 via DT\n"); - -#ifdef CONFIG_LOCAL_TIMERS - sirfsoc_timer1_irq.irq = irq_of_parse_and_map(np, 1); - if (!sirfsoc_timer1_irq.irq) - panic("No irq passed for timer1 via DT\n"); -#endif - - of_node_put(np); -} diff --git a/arch/arm/mach-prima2/timer-prima2.c b/arch/arm/mach-prima2/timer-prima2.c deleted file mode 100644 index 9829083..0000000 --- a/arch/arm/mach-prima2/timer-prima2.c +++ /dev/null @@ -1,239 +0,0 @@ -/* - * System timer for CSR SiRFprimaII - * - * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company. - * - * Licensed under GPLv2 or later. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "common.h" - -#define SIRFSOC_TIMER_COUNTER_LO 0x0000 -#define SIRFSOC_TIMER_COUNTER_HI 0x0004 -#define SIRFSOC_TIMER_MATCH_0 0x0008 -#define SIRFSOC_TIMER_MATCH_1 0x000C -#define SIRFSOC_TIMER_MATCH_2 0x0010 -#define SIRFSOC_TIMER_MATCH_3 0x0014 -#define SIRFSOC_TIMER_MATCH_4 0x0018 -#define SIRFSOC_TIMER_MATCH_5 0x001C -#define SIRFSOC_TIMER_STATUS 0x0020 -#define SIRFSOC_TIMER_INT_EN 0x0024 -#define SIRFSOC_TIMER_WATCHDOG_EN 0x0028 -#define SIRFSOC_TIMER_DIV 0x002C -#define SIRFSOC_TIMER_LATCH 0x0030 -#define SIRFSOC_TIMER_LATCHED_LO 0x0034 -#define SIRFSOC_TIMER_LATCHED_HI 0x0038 - -#define SIRFSOC_TIMER_WDT_INDEX 5 - -#define SIRFSOC_TIMER_LATCH_BIT BIT(0) - -#define SIRFSOC_TIMER_REG_CNT 11 - -static const u32 sirfsoc_timer_reg_list[SIRFSOC_TIMER_REG_CNT] = { - SIRFSOC_TIMER_MATCH_0, SIRFSOC_TIMER_MATCH_1, SIRFSOC_TIMER_MATCH_2, - SIRFSOC_TIMER_MATCH_3, SIRFSOC_TIMER_MATCH_4, SIRFSOC_TIMER_MATCH_5, - SIRFSOC_TIMER_INT_EN, SIRFSOC_TIMER_WATCHDOG_EN, SIRFSOC_TIMER_DIV, - SIRFSOC_TIMER_LATCHED_LO, SIRFSOC_TIMER_LATCHED_HI, -}; - -static u32 sirfsoc_timer_reg_val[SIRFSOC_TIMER_REG_CNT]; - -static void __iomem *sirfsoc_timer_base; -static void __init sirfsoc_of_timer_map(void); - -/* timer0 interrupt handler */ -static irqreturn_t sirfsoc_timer_interrupt(int irq, void *dev_id) -{ - struct clock_event_device *ce = dev_id; - - WARN_ON(!(readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_STATUS) & BIT(0))); - - /* clear timer0 interrupt */ - writel_relaxed(BIT(0), sirfsoc_timer_base + SIRFSOC_TIMER_STATUS); - - ce->event_handler(ce); - - return IRQ_HANDLED; -} - -/* read 64-bit timer counter */ -static cycle_t sirfsoc_timer_read(struct clocksource *cs) -{ - u64 cycles; - - /* latch the 64-bit timer counter */ - writel_relaxed(SIRFSOC_TIMER_LATCH_BIT, sirfsoc_timer_base + SIRFSOC_TIMER_LATCH); - cycles = readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_LATCHED_HI); - cycles = (cycles << 32) | readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_LATCHED_LO); - - return cycles; -} - -static int sirfsoc_timer_set_next_event(unsigned long delta, - struct clock_event_device *ce) -{ - unsigned long now, next; - - writel_relaxed(SIRFSOC_TIMER_LATCH_BIT, sirfsoc_timer_base + SIRFSOC_TIMER_LATCH); - now = readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_LATCHED_LO); - next = now + delta; - writel_relaxed(next, sirfsoc_timer_base + SIRFSOC_TIMER_MATCH_0); - writel_relaxed(SIRFSOC_TIMER_LATCH_BIT, sirfsoc_timer_base + SIRFSOC_TIMER_LATCH); - now = readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_LATCHED_LO); - - return next - now > delta ? -ETIME : 0; -} - -static void sirfsoc_timer_set_mode(enum clock_event_mode mode, - struct clock_event_device *ce) -{ - u32 val = readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_INT_EN); - switch (mode) { - case CLOCK_EVT_MODE_PERIODIC: - WARN_ON(1); - break; - case CLOCK_EVT_MODE_ONESHOT: - writel_relaxed(val | BIT(0), sirfsoc_timer_base + SIRFSOC_TIMER_INT_EN); - break; - case CLOCK_EVT_MODE_SHUTDOWN: - writel_relaxed(val & ~BIT(0), sirfsoc_timer_base + SIRFSOC_TIMER_INT_EN); - break; - case CLOCK_EVT_MODE_UNUSED: - case CLOCK_EVT_MODE_RESUME: - break; - } -} - -static void sirfsoc_clocksource_suspend(struct clocksource *cs) -{ - int i; - - writel_relaxed(SIRFSOC_TIMER_LATCH_BIT, sirfsoc_timer_base + SIRFSOC_TIMER_LATCH); - - for (i = 0; i < SIRFSOC_TIMER_REG_CNT; i++) - sirfsoc_timer_reg_val[i] = readl_relaxed(sirfsoc_timer_base + sirfsoc_timer_reg_list[i]); -} - -static void sirfsoc_clocksource_resume(struct clocksource *cs) -{ - int i; - - for (i = 0; i < SIRFSOC_TIMER_REG_CNT - 2; i++) - writel_relaxed(sirfsoc_timer_reg_val[i], sirfsoc_timer_base + sirfsoc_timer_reg_list[i]); - - writel_relaxed(sirfsoc_timer_reg_val[SIRFSOC_TIMER_REG_CNT - 2], sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_LO); - writel_relaxed(sirfsoc_timer_reg_val[SIRFSOC_TIMER_REG_CNT - 1], sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_HI); -} - -static struct clock_event_device sirfsoc_clockevent = { - .name = "sirfsoc_clockevent", - .rating = 200, - .features = CLOCK_EVT_FEAT_ONESHOT, - .set_mode = sirfsoc_timer_set_mode, - .set_next_event = sirfsoc_timer_set_next_event, -}; - -static struct clocksource sirfsoc_clocksource = { - .name = "sirfsoc_clocksource", - .rating = 200, - .mask = CLOCKSOURCE_MASK(64), - .flags = CLOCK_SOURCE_IS_CONTINUOUS, - .read = sirfsoc_timer_read, - .suspend = sirfsoc_clocksource_suspend, - .resume = sirfsoc_clocksource_resume, -}; - -static struct irqaction sirfsoc_timer_irq = { - .name = "sirfsoc_timer0", - .flags = IRQF_TIMER, - .irq = 0, - .handler = sirfsoc_timer_interrupt, - .dev_id = &sirfsoc_clockevent, -}; - -/* Overwrite weak default sched_clock with more precise one */ -static u32 notrace sirfsoc_read_sched_clock(void) -{ - return (u32)(sirfsoc_timer_read(NULL) & 0xffffffff); -} - -static void __init sirfsoc_clockevent_init(void) -{ - sirfsoc_clockevent.cpumask = cpumask_of(0); - clockevents_config_and_register(&sirfsoc_clockevent, CLOCK_TICK_RATE, - 2, -2); -} - -/* initialize the kernel jiffy timer source */ -void __init sirfsoc_prima2_timer_init(void) -{ - unsigned long rate; - struct clk *clk; - - /* initialize clocking early, we want to set the OS timer */ - sirfsoc_of_clk_init(); - - /* timer's input clock is io clock */ - clk = clk_get_sys("io", NULL); - - BUG_ON(IS_ERR(clk)); - - rate = clk_get_rate(clk); - - BUG_ON(rate < CLOCK_TICK_RATE); - BUG_ON(rate % CLOCK_TICK_RATE); - - sirfsoc_of_timer_map(); - - writel_relaxed(rate / CLOCK_TICK_RATE / 2 - 1, sirfsoc_timer_base + SIRFSOC_TIMER_DIV); - writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_LO); - writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_HI); - writel_relaxed(BIT(0), sirfsoc_timer_base + SIRFSOC_TIMER_STATUS); - - BUG_ON(clocksource_register_hz(&sirfsoc_clocksource, CLOCK_TICK_RATE)); - - setup_sched_clock(sirfsoc_read_sched_clock, 32, CLOCK_TICK_RATE); - - BUG_ON(setup_irq(sirfsoc_timer_irq.irq, &sirfsoc_timer_irq)); - - sirfsoc_clockevent_init(); -} - -static struct of_device_id timer_ids[] = { - { .compatible = "sirf,prima2-tick" }, - {}, -}; - -static void __init sirfsoc_of_timer_map(void) -{ - struct device_node *np; - - np = of_find_matching_node(NULL, timer_ids); - if (!np) - return; - sirfsoc_timer_base = of_iomap(np, 0); - if (!sirfsoc_timer_base) - panic("unable to map timer cpu registers\n"); - - /* Get the interrupts property */ - sirfsoc_timer_irq.irq = irq_of_parse_and_map(np, 0); - - of_node_put(np); -} -- cgit v1.1 From cf82e0e40525d3525445ada6569525cc44aad46f Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Tue, 19 Mar 2013 17:45:37 +0100 Subject: ARM: sirf: enable multiplatform support All the prerequisites are there now, so we can move sirf into multiplatform. Signed-off-by: Arnd Bergmann --- arch/arm/Kconfig | 17 ---------- arch/arm/mach-prima2/Kconfig | 12 ++++++++ arch/arm/mach-prima2/Makefile | 2 ++ arch/arm/mach-prima2/common.h | 3 ++ arch/arm/mach-prima2/include/mach/clkdev.h | 15 --------- arch/arm/mach-prima2/include/mach/entry-macro.S | 22 ------------- arch/arm/mach-prima2/include/mach/hardware.h | 15 --------- arch/arm/mach-prima2/include/mach/map.h | 18 ----------- arch/arm/mach-prima2/include/mach/timex.h | 14 --------- arch/arm/mach-prima2/include/mach/uart.h | 29 ----------------- arch/arm/mach-prima2/include/mach/uncompress.h | 41 ------------------------- arch/arm/mach-prima2/lluart.c | 2 +- arch/arm/mach-prima2/platsmp.c | 1 - 13 files changed, 18 insertions(+), 173 deletions(-) delete mode 100644 arch/arm/mach-prima2/include/mach/clkdev.h delete mode 100644 arch/arm/mach-prima2/include/mach/entry-macro.S delete mode 100644 arch/arm/mach-prima2/include/mach/hardware.h delete mode 100644 arch/arm/mach-prima2/include/mach/map.h delete mode 100644 arch/arm/mach-prima2/include/mach/timex.h delete mode 100644 arch/arm/mach-prima2/include/mach/uart.h delete mode 100644 arch/arm/mach-prima2/include/mach/uncompress.h (limited to 'arch/arm') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index c674b32..1bcec63 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -49,7 +49,6 @@ config ARM select HAVE_REGS_AND_STACK_ACCESS_API select HAVE_SYSCALL_TRACEPOINTS select HAVE_UID16 - select HAVE_VIRT_TO_BUS select KTIME_SCALAR select PERF_USE_VMALLOC select RTC_LIB @@ -415,22 +414,6 @@ config ARCH_GEMINI help Support for the Cortina Systems Gemini family SoCs -config ARCH_SIRF - bool "CSR SiRF" - select ARCH_REQUIRE_GPIOLIB - select AUTO_ZRELADDR - select COMMON_CLK - select GENERIC_CLOCKEVENTS - select GENERIC_IRQ_CHIP - select MIGHT_HAVE_CACHE_L2X0 - select NO_IOPORT - select PINCTRL - select PINCTRL_SIRF - select USE_OF - select SPARSE_IRQ - help - Support for CSR SiRFprimaII/Marco/Polo platforms - config ARCH_EBSA110 bool "EBSA-110" select ARCH_USES_GETTIMEOFFSET diff --git a/arch/arm/mach-prima2/Kconfig b/arch/arm/mach-prima2/Kconfig index b3be799..587c0bd 100644 --- a/arch/arm/mach-prima2/Kconfig +++ b/arch/arm/mach-prima2/Kconfig @@ -1,3 +1,15 @@ +config ARCH_SIRF + bool "CSR SiRF" if ARCH_MULTI_V7 + select ARCH_REQUIRE_GPIOLIB + select GENERIC_CLOCKEVENTS + select GENERIC_IRQ_CHIP + select MIGHT_HAVE_CACHE_L2X0 + select NO_IOPORT + select PINCTRL + select PINCTRL_SIRF + help + Support for CSR SiRFprimaII/Marco/Polo platforms + if ARCH_SIRF menu "CSR SiRF atlas6/primaII/Marco/Polo Specific Features" diff --git a/arch/arm/mach-prima2/Makefile b/arch/arm/mach-prima2/Makefile index 52ac738..7a6b4a3 100644 --- a/arch/arm/mach-prima2/Makefile +++ b/arch/arm/mach-prima2/Makefile @@ -6,3 +6,5 @@ obj-$(CONFIG_CACHE_L2X0) += l2x0.o obj-$(CONFIG_SUSPEND) += pm.o sleep.o obj-$(CONFIG_SMP) += platsmp.o headsmp.o obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o + +CFLAGS_hotplug.o += -march=armv7-a diff --git a/arch/arm/mach-prima2/common.h b/arch/arm/mach-prima2/common.h index 54262cf..81135cd 100644 --- a/arch/arm/mach-prima2/common.h +++ b/arch/arm/mach-prima2/common.h @@ -13,6 +13,9 @@ #include #include +#define SIRFSOC_VA_BASE _AC(0xFEC00000, UL) +#define SIRFSOC_VA(x) (SIRFSOC_VA_BASE + ((x) & 0x00FFF000)) + extern struct smp_operations sirfsoc_smp_ops; extern void sirfsoc_secondary_startup(void); extern void sirfsoc_cpu_die(unsigned int cpu); diff --git a/arch/arm/mach-prima2/include/mach/clkdev.h b/arch/arm/mach-prima2/include/mach/clkdev.h deleted file mode 100644 index 6693251..0000000 --- a/arch/arm/mach-prima2/include/mach/clkdev.h +++ /dev/null @@ -1,15 +0,0 @@ -/* - * arch/arm/mach-prima2/include/mach/clkdev.h - * - * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company. - * - * Licensed under GPLv2 or later. - */ - -#ifndef __MACH_CLKDEV_H -#define __MACH_CLKDEV_H - -#define __clk_get(clk) ({ 1; }) -#define __clk_put(clk) do { } while (0) - -#endif diff --git a/arch/arm/mach-prima2/include/mach/entry-macro.S b/arch/arm/mach-prima2/include/mach/entry-macro.S deleted file mode 100644 index 86434e7..0000000 --- a/arch/arm/mach-prima2/include/mach/entry-macro.S +++ /dev/null @@ -1,22 +0,0 @@ -/* - * arch/arm/mach-prima2/include/mach/entry-macro.S - * - * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company. - * - * Licensed under GPLv2 or later. - */ - -#include - -#define SIRFSOC_INT_ID 0x38 - - .macro get_irqnr_preamble, base, tmp - ldr \base, =sirfsoc_intc_base - ldr \base, [\base] - .endm - - .macro get_irqnr_and_base, irqnr, irqstat, base, tmp - ldr \irqnr, [\base, #SIRFSOC_INT_ID] @ Get the highest priority irq - cmp \irqnr, #0x40 @ the irq num can't be larger than 0x3f - movges \irqnr, #0 - .endm diff --git a/arch/arm/mach-prima2/include/mach/hardware.h b/arch/arm/mach-prima2/include/mach/hardware.h deleted file mode 100644 index 105b969..0000000 --- a/arch/arm/mach-prima2/include/mach/hardware.h +++ /dev/null @@ -1,15 +0,0 @@ -/* - * arch/arm/mach-prima2/include/mach/hardware.h - * - * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company. - * - * Licensed under GPLv2 or later. - */ - -#ifndef __MACH_HARDWARE_H__ -#define __MACH_HARDWARE_H__ - -#include -#include - -#endif diff --git a/arch/arm/mach-prima2/include/mach/map.h b/arch/arm/mach-prima2/include/mach/map.h deleted file mode 100644 index 6f24353..0000000 --- a/arch/arm/mach-prima2/include/mach/map.h +++ /dev/null @@ -1,18 +0,0 @@ -/* - * memory & I/O static mapping definitions for CSR SiRFprimaII - * - * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company. - * - * Licensed under GPLv2 or later. - */ - -#ifndef __MACH_PRIMA2_MAP_H__ -#define __MACH_PRIMA2_MAP_H__ - -#include - -#define SIRFSOC_VA_BASE _AC(0xFEC00000, UL) - -#define SIRFSOC_VA(x) (SIRFSOC_VA_BASE + ((x) & 0x00FFF000)) - -#endif diff --git a/arch/arm/mach-prima2/include/mach/timex.h b/arch/arm/mach-prima2/include/mach/timex.h deleted file mode 100644 index d6f98a7..0000000 --- a/arch/arm/mach-prima2/include/mach/timex.h +++ /dev/null @@ -1,14 +0,0 @@ -/* - * arch/arm/mach-prima2/include/mach/timex.h - * - * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company. - * - * Licensed under GPLv2 or later. - */ - -#ifndef __MACH_TIMEX_H__ -#define __MACH_TIMEX_H__ - -#define CLOCK_TICK_RATE 1000000 - -#endif diff --git a/arch/arm/mach-prima2/include/mach/uart.h b/arch/arm/mach-prima2/include/mach/uart.h deleted file mode 100644 index c10510d..0000000 --- a/arch/arm/mach-prima2/include/mach/uart.h +++ /dev/null @@ -1,29 +0,0 @@ -/* - * arch/arm/mach-prima2/include/mach/uart.h - * - * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company. - * - * Licensed under GPLv2 or later. - */ - -#ifndef __MACH_PRIMA2_SIRFSOC_UART_H -#define __MACH_PRIMA2_SIRFSOC_UART_H - -/* UART-1: used as serial debug port */ -#if defined(CONFIG_DEBUG_SIRFPRIMA2_UART1) -#define SIRFSOC_UART1_PA_BASE 0xb0060000 -#elif defined(CONFIG_DEBUG_SIRFMARCO_UART1) -#define SIRFSOC_UART1_PA_BASE 0xcc060000 -#else -#define SIRFSOC_UART1_PA_BASE 0 -#endif -#define SIRFSOC_UART1_VA_BASE SIRFSOC_VA(0x060000) -#define SIRFSOC_UART1_SIZE SZ_4K - -#define SIRFSOC_UART_TXFIFO_STATUS 0x0114 -#define SIRFSOC_UART_TXFIFO_DATA 0x0118 - -#define SIRFSOC_UART1_TXFIFO_FULL (1 << 5) -#define SIRFSOC_UART1_TXFIFO_EMPTY (1 << 6) - -#endif diff --git a/arch/arm/mach-prima2/include/mach/uncompress.h b/arch/arm/mach-prima2/include/mach/uncompress.h deleted file mode 100644 index d1513a3..0000000 --- a/arch/arm/mach-prima2/include/mach/uncompress.h +++ /dev/null @@ -1,41 +0,0 @@ -/* - * arch/arm/mach-prima2/include/mach/uncompress.h - * - * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company. - * - * Licensed under GPLv2 or later. - */ - -#ifndef __ASM_ARCH_UNCOMPRESS_H -#define __ASM_ARCH_UNCOMPRESS_H - -#include -#include -#include - -void arch_decomp_setup(void) -{ -} - -static __inline__ void putc(char c) -{ - /* - * during kernel decompression, all mappings are flat: - * virt_addr == phys_addr - */ - if (!SIRFSOC_UART1_PA_BASE) - return; - - while (__raw_readl((void __iomem *)SIRFSOC_UART1_PA_BASE + SIRFSOC_UART_TXFIFO_STATUS) - & SIRFSOC_UART1_TXFIFO_FULL) - barrier(); - - __raw_writel(c, (void __iomem *)SIRFSOC_UART1_PA_BASE + SIRFSOC_UART_TXFIFO_DATA); -} - -static inline void flush(void) -{ -} - -#endif - diff --git a/arch/arm/mach-prima2/lluart.c b/arch/arm/mach-prima2/lluart.c index 7222481..99c0c92 100644 --- a/arch/arm/mach-prima2/lluart.c +++ b/arch/arm/mach-prima2/lluart.c @@ -9,7 +9,7 @@ #include #include #include -#include +#include "common.h" #if defined(CONFIG_DEBUG_SIRFPRIMA2_UART1) #define SIRFSOC_UART1_PA_BASE 0xb0060000 diff --git a/arch/arm/mach-prima2/platsmp.c b/arch/arm/mach-prima2/platsmp.c index 4b78831..d52e322 100644 --- a/arch/arm/mach-prima2/platsmp.c +++ b/arch/arm/mach-prima2/platsmp.c @@ -18,7 +18,6 @@ #include #include #include -#include #include "common.h" -- cgit v1.1 From dbaf6a8d5de7b63f85eea10a47681f920cbf7385 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Tue, 19 Mar 2013 23:08:43 +0100 Subject: ARM: sirf: enable support in multi_v7_defconfig This enables all sirf specific drivers in the defconfig. Signed-off-by: Arnd Bergmann Reviewed-by: Barry Song --- arch/arm/configs/multi_v7_defconfig | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig index e31d442..44ec305 100644 --- a/arch/arm/configs/multi_v7_defconfig +++ b/arch/arm/configs/multi_v7_defconfig @@ -3,6 +3,7 @@ CONFIG_NO_HZ=y CONFIG_HIGH_RES_TIMERS=y CONFIG_ARCH_MVEBU=y CONFIG_MACH_ARMADA_370=y +CONFIG_ARCH_SIRF=y CONFIG_MACH_ARMADA_XP=y CONFIG_ARCH_HIGHBANK=y CONFIG_ARCH_SOCFPGA=y @@ -34,12 +35,16 @@ CONFIG_SERIAL_8250_DW=y CONFIG_SERIAL_AMBA_PL011=y CONFIG_SERIAL_AMBA_PL011_CONSOLE=y CONFIG_SERIAL_OF_PLATFORM=y +CONFIG_SERIAL_SIRFSOC=y +CONFIG_SERIAL_SIRFSOC_CONSOLE=y CONFIG_IPMI_HANDLER=y CONFIG_IPMI_SI=y CONFIG_I2C=y CONFIG_I2C_DESIGNWARE_PLATFORM=y +CONFIG_I2C_SIRF=y CONFIG_SPI=y CONFIG_SPI_PL022=y +CONFIG_SPI_SIRF=y CONFIG_FB=y CONFIG_FB_ARMCLCD=y CONFIG_FRAMEBUFFER_CONSOLE=y @@ -58,3 +63,4 @@ CONFIG_RTC_CLASS=y CONFIG_RTC_DRV_PL031=y CONFIG_DMADEVICES=y CONFIG_PL330_DMA=y +CONFIG_SIRF_DMA=y -- cgit v1.1 From e4bcda28344cc4762c57ad7333f0472a39e83479 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Fri, 29 Mar 2013 17:38:18 -0600 Subject: ARM: tegra: move to This is required so that code such as Tegra's PCIe and clock drivers can still access this header file once Tegra is converted to multiplatform, and no longer exists. Signed-off-by: Stephen Warren --- arch/arm/mach-tegra/board.h | 1 + arch/arm/mach-tegra/common.c | 2 -- arch/arm/mach-tegra/include/mach/powergate.h | 54 ---------------------------- arch/arm/mach-tegra/pcie.c | 3 +- arch/arm/mach-tegra/powergate.c | 3 +- 5 files changed, 3 insertions(+), 60 deletions(-) delete mode 100644 arch/arm/mach-tegra/include/mach/powergate.h (limited to 'arch/arm') diff --git a/arch/arm/mach-tegra/board.h b/arch/arm/mach-tegra/board.h index 60431de..1787327 100644 --- a/arch/arm/mach-tegra/board.h +++ b/arch/arm/mach-tegra/board.h @@ -40,6 +40,7 @@ int tegra_clk_debugfs_init(void); static inline int tegra_clk_debugfs_init(void) { return 0; } #endif +int __init tegra_powergate_init(void); #if defined(CONFIG_ARCH_TEGRA_2x_SOC) && defined(CONFIG_DEBUG_FS) int __init tegra_powergate_debugfs_init(void); #else diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c index f0315c9..7cc7563 100644 --- a/arch/arm/mach-tegra/common.c +++ b/arch/arm/mach-tegra/common.c @@ -27,8 +27,6 @@ #include -#include - #include "board.h" #include "common.h" #include "fuse.h" diff --git a/arch/arm/mach-tegra/include/mach/powergate.h b/arch/arm/mach-tegra/include/mach/powergate.h deleted file mode 100644 index 06763fe..0000000 --- a/arch/arm/mach-tegra/include/mach/powergate.h +++ /dev/null @@ -1,54 +0,0 @@ -/* - * drivers/regulator/tegra-regulator.c - * - * Copyright (c) 2010 Google, Inc - * - * Author: - * Colin Cross - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#ifndef _MACH_TEGRA_POWERGATE_H_ -#define _MACH_TEGRA_POWERGATE_H_ - -struct clk; - -#define TEGRA_POWERGATE_CPU 0 -#define TEGRA_POWERGATE_3D 1 -#define TEGRA_POWERGATE_VENC 2 -#define TEGRA_POWERGATE_PCIE 3 -#define TEGRA_POWERGATE_VDEC 4 -#define TEGRA_POWERGATE_L2 5 -#define TEGRA_POWERGATE_MPE 6 -#define TEGRA_POWERGATE_HEG 7 -#define TEGRA_POWERGATE_SATA 8 -#define TEGRA_POWERGATE_CPU1 9 -#define TEGRA_POWERGATE_CPU2 10 -#define TEGRA_POWERGATE_CPU3 11 -#define TEGRA_POWERGATE_CELP 12 -#define TEGRA_POWERGATE_3D1 13 - -#define TEGRA_POWERGATE_CPU0 TEGRA_POWERGATE_CPU -#define TEGRA_POWERGATE_3D0 TEGRA_POWERGATE_3D - -int __init tegra_powergate_init(void); - -int tegra_cpu_powergate_id(int cpuid); -int tegra_powergate_is_powered(int id); -int tegra_powergate_power_on(int id); -int tegra_powergate_power_off(int id); -int tegra_powergate_remove_clamping(int id); - -/* Must be called with clk disabled, and returns with clk enabled */ -int tegra_powergate_sequence_power_up(int id, struct clk *clk); - -#endif /* _MACH_TEGRA_POWERGATE_H_ */ diff --git a/arch/arm/mach-tegra/pcie.c b/arch/arm/mach-tegra/pcie.c index b60165f..46144a1 100644 --- a/arch/arm/mach-tegra/pcie.c +++ b/arch/arm/mach-tegra/pcie.c @@ -34,12 +34,11 @@ #include #include #include +#include #include #include -#include - #include "board.h" #include "iomap.h" diff --git a/arch/arm/mach-tegra/powergate.c b/arch/arm/mach-tegra/powergate.c index c6bc8f8..585d297 100644 --- a/arch/arm/mach-tegra/powergate.c +++ b/arch/arm/mach-tegra/powergate.c @@ -27,8 +27,7 @@ #include #include #include - -#include +#include #include "fuse.h" #include "iomap.h" -- cgit v1.1 From 9002722560ba86a2f59811e3d11a2575bf47e1f6 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Wed, 26 Sep 2012 13:08:59 -0600 Subject: ARM: tegra: convert to multi-platform This allows Tegra be included in a kernel build that supports multiple SoCs at once, which is useful for distro kernels. This change: * Moves Tegra's Kconfig into its own directory, as seems typical for multi-platform conversions. * Stops selecting some ARM errata that are incompatible with multi- platform. This requires that you use a bootloader that enables the workaround! * Deletes some headers and Makefile.boot that aren't needed now that we support multi-platform. Signed-off-by: Stephen Warren --- arch/arm/Kconfig | 19 --- arch/arm/mach-tegra/Kconfig | 27 ++-- arch/arm/mach-tegra/Makefile.boot | 3 - arch/arm/mach-tegra/include/mach/timex.h | 26 ---- arch/arm/mach-tegra/include/mach/uncompress.h | 175 -------------------------- 5 files changed, 20 insertions(+), 230 deletions(-) delete mode 100644 arch/arm/mach-tegra/Makefile.boot delete mode 100644 arch/arm/mach-tegra/include/mach/timex.h delete mode 100644 arch/arm/mach-tegra/include/mach/uncompress.h (limited to 'arch/arm') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 59b7be7..f6dfe23 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -663,25 +663,6 @@ config ARCH_LPC32XX help Support for the NXP LPC32XX family of processors -config ARCH_TEGRA - bool "NVIDIA Tegra" - select ARCH_HAS_CPUFREQ - select ARCH_REQUIRE_GPIOLIB - select CLKDEV_LOOKUP - select CLKSRC_MMIO - select CLKSRC_OF - select COMMON_CLK - select GENERIC_CLOCKEVENTS - select HAVE_CLK - select HAVE_SMP - select MIGHT_HAVE_CACHE_L2X0 - select SOC_BUS - select SPARSE_IRQ - select USE_OF - help - This enables support for NVIDIA Tegra based systems (Tegra APX, - Tegra 6xx and Tegra 2 series). - config ARCH_PXA bool "PXA2xx/PXA3xx-based" depends on MMU diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig index d1c4893..df99ee9 100644 --- a/arch/arm/mach-tegra/Kconfig +++ b/arch/arm/mach-tegra/Kconfig @@ -1,13 +1,28 @@ -if ARCH_TEGRA +config ARCH_TEGRA + bool "NVIDIA Tegra" if ARCH_MULTI_V7 + select ARCH_HAS_CPUFREQ + select ARCH_REQUIRE_GPIOLIB + select CLKDEV_LOOKUP + select CLKSRC_MMIO + select CLKSRC_OF + select COMMON_CLK + select GENERIC_CLOCKEVENTS + select HAVE_CLK + select HAVE_SMP + select MIGHT_HAVE_CACHE_L2X0 + select SOC_BUS + select SPARSE_IRQ + select USE_OF + help + This enables support for NVIDIA Tegra based systems. -comment "NVIDIA Tegra options" +menu "NVIDIA Tegra options" + depends on ARCH_TEGRA config ARCH_TEGRA_2x_SOC bool "Enable support for Tegra20 family" select ARCH_NEEDS_CPU_IDLE_COUPLED if SMP select ARM_ERRATA_720789 - select ARM_ERRATA_742230 if SMP - select ARM_ERRATA_751472 select ARM_ERRATA_754327 if SMP select ARM_ERRATA_764369 if SMP select ARM_GIC @@ -26,8 +41,6 @@ config ARCH_TEGRA_2x_SOC config ARCH_TEGRA_3x_SOC bool "Enable support for Tegra30 family" - select ARM_ERRATA_743622 - select ARM_ERRATA_751472 select ARM_ERRATA_754322 select ARM_ERRATA_764369 if SMP select ARM_GIC @@ -71,4 +84,4 @@ config TEGRA_AHB config TEGRA_EMC_SCALING_ENABLE bool "Enable scaling the memory frequency" -endif +endmenu diff --git a/arch/arm/mach-tegra/Makefile.boot b/arch/arm/mach-tegra/Makefile.boot deleted file mode 100644 index 2943381..0000000 --- a/arch/arm/mach-tegra/Makefile.boot +++ /dev/null @@ -1,3 +0,0 @@ -zreladdr-$(CONFIG_ARCH_TEGRA_2x_SOC) += 0x00008000 -params_phys-$(CONFIG_ARCH_TEGRA_2x_SOC) := 0x00000100 -initrd_phys-$(CONFIG_ARCH_TEGRA_2x_SOC) := 0x00800000 diff --git a/arch/arm/mach-tegra/include/mach/timex.h b/arch/arm/mach-tegra/include/mach/timex.h deleted file mode 100644 index a44ccbd..0000000 --- a/arch/arm/mach-tegra/include/mach/timex.h +++ /dev/null @@ -1,26 +0,0 @@ -/* - * arch/arm/mach-tegra/include/mach/timex.h - * - * Copyright (C) 2010 Google, Inc. - * - * Author: - * Colin Cross - * Erik Gilling - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#ifndef __MACH_TEGRA_TIMEX_H -#define __MACH_TEGRA_TIMEX_H - -#define CLOCK_TICK_RATE 1000000 - -#endif diff --git a/arch/arm/mach-tegra/include/mach/uncompress.h b/arch/arm/mach-tegra/include/mach/uncompress.h deleted file mode 100644 index 0838641..0000000 --- a/arch/arm/mach-tegra/include/mach/uncompress.h +++ /dev/null @@ -1,175 +0,0 @@ -/* - * arch/arm/mach-tegra/include/mach/uncompress.h - * - * Copyright (C) 2010 Google, Inc. - * Copyright (C) 2011 Google, Inc. - * Copyright (C) 2011-2012 NVIDIA CORPORATION. All Rights Reserved. - * - * Author: - * Colin Cross - * Erik Gilling - * Doug Anderson - * Stephen Warren - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#ifndef __MACH_TEGRA_UNCOMPRESS_H -#define __MACH_TEGRA_UNCOMPRESS_H - -#include -#include - -#include "../../iomap.h" - -#define BIT(x) (1 << (x)) -#define ARRAY_SIZE(arr) (sizeof(arr) / sizeof((arr)[0])) - -#define DEBUG_UART_SHIFT 2 - -volatile u8 *uart; - -static void putc(int c) -{ - if (uart == NULL) - return; - - while (!(uart[UART_LSR << DEBUG_UART_SHIFT] & UART_LSR_THRE)) - barrier(); - uart[UART_TX << DEBUG_UART_SHIFT] = c; -} - -static inline void flush(void) -{ -} - -static const struct { - u32 base; - u32 reset_reg; - u32 clock_reg; - u32 bit; -} uarts[] = { - { - TEGRA_UARTA_BASE, - TEGRA_CLK_RESET_BASE + 0x04, - TEGRA_CLK_RESET_BASE + 0x10, - 6, - }, - { - TEGRA_UARTB_BASE, - TEGRA_CLK_RESET_BASE + 0x04, - TEGRA_CLK_RESET_BASE + 0x10, - 7, - }, - { - TEGRA_UARTC_BASE, - TEGRA_CLK_RESET_BASE + 0x08, - TEGRA_CLK_RESET_BASE + 0x14, - 23, - }, - { - TEGRA_UARTD_BASE, - TEGRA_CLK_RESET_BASE + 0x0c, - TEGRA_CLK_RESET_BASE + 0x18, - 1, - }, - { - TEGRA_UARTE_BASE, - TEGRA_CLK_RESET_BASE + 0x0c, - TEGRA_CLK_RESET_BASE + 0x18, - 2, - }, -}; - -static inline bool uart_clocked(int i) -{ - if (*(u8 *)uarts[i].reset_reg & BIT(uarts[i].bit)) - return false; - - if (!(*(u8 *)uarts[i].clock_reg & BIT(uarts[i].bit))) - return false; - - return true; -} - -#ifdef CONFIG_TEGRA_DEBUG_UART_AUTO_ODMDATA -int auto_odmdata(void) -{ - volatile u32 *pmc = (volatile u32 *)TEGRA_PMC_BASE; - u32 odmdata = pmc[0xa0 / 4]; - - /* - * Bits 19:18 are the console type: 0=default, 1=none, 2==DCC, 3==UART - * Some boards apparently swap the last two values, but we don't have - * any way of catering for that here, so we just accept either. If this - * doesn't make sense for your board, just don't enable this feature. - * - * Bits 17:15 indicate the UART to use, 0/1/2/3/4 are UART A/B/C/D/E. - */ - - switch ((odmdata >> 18) & 3) { - case 2: - case 3: - break; - default: - return -1; - } - - return (odmdata >> 15) & 7; -} -#endif - -/* - * Setup before decompression. This is where we do UART selection for - * earlyprintk and init the uart_base register. - */ -static inline void arch_decomp_setup(void) -{ - int uart_id; - volatile u32 *apb_misc = (volatile u32 *)TEGRA_APB_MISC_BASE; - u32 chip, div; - -#if defined(CONFIG_TEGRA_DEBUG_UART_AUTO_ODMDATA) - uart_id = auto_odmdata(); -#elif defined(CONFIG_TEGRA_DEBUG_UARTA) - uart_id = 0; -#elif defined(CONFIG_TEGRA_DEBUG_UARTB) - uart_id = 1; -#elif defined(CONFIG_TEGRA_DEBUG_UARTC) - uart_id = 2; -#elif defined(CONFIG_TEGRA_DEBUG_UARTD) - uart_id = 3; -#elif defined(CONFIG_TEGRA_DEBUG_UARTE) - uart_id = 4; -#endif - - if (uart_id < 0 || uart_id >= ARRAY_SIZE(uarts) || - !uart_clocked(uart_id)) - uart = NULL; - else - uart = (volatile u8 *)uarts[uart_id].base; - - if (uart == NULL) - return; - - chip = (apb_misc[0x804 / 4] >> 8) & 0xff; - if (chip == 0x20) - div = 0x0075; - else - div = 0x00dd; - - uart[UART_LCR << DEBUG_UART_SHIFT] |= UART_LCR_DLAB; - uart[UART_DLL << DEBUG_UART_SHIFT] = div & 0xff; - uart[UART_DLM << DEBUG_UART_SHIFT] = div >> 8; - uart[UART_LCR << DEBUG_UART_SHIFT] = 3; -} - -#endif -- cgit v1.1 From 806a94f20c8d78c96601878393a49fab577dcf2e Mon Sep 17 00:00:00 2001 From: Tony Prisk Date: Mon, 25 Mar 2013 21:11:40 +1300 Subject: arm: vt8500: Add wm8850 config options to multi_v7_defconfig This patch finally adds the WM8850 SoC to the multi_v7_defconfig. We don't have a seperate defconfig for this SoC as it is only available as a multiplatform option. Signed-off-by: Tony Prisk Signed-off-by: Olof Johansson --- arch/arm/configs/multi_v7_defconfig | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig index e3f2f6a..2e67a27 100644 --- a/arch/arm/configs/multi_v7_defconfig +++ b/arch/arm/configs/multi_v7_defconfig @@ -8,6 +8,7 @@ CONFIG_MACH_ARMADA_XP=y CONFIG_ARCH_HIGHBANK=y CONFIG_ARCH_SOCFPGA=y CONFIG_ARCH_SUNXI=y +CONFIG_ARCH_WM8850=y # CONFIG_ARCH_VEXPRESS_CORTEX_A5_A9_ERRATA is not set CONFIG_ARCH_ZYNQ=y CONFIG_ARM_ERRATA_754322=y @@ -43,6 +44,8 @@ CONFIG_SERIAL_AMBA_PL011_CONSOLE=y CONFIG_SERIAL_OF_PLATFORM=y CONFIG_SERIAL_SIRFSOC=y CONFIG_SERIAL_SIRFSOC_CONSOLE=y +CONFIG_SERIAL_VT8500=y +CONFIG_SERIAL_VT8500_CONSOLE=y CONFIG_IPMI_HANDLER=y CONFIG_IPMI_SI=y CONFIG_I2C=y @@ -54,6 +57,7 @@ CONFIG_SPI_SIRF=y CONFIG_GPIO_PL061=y CONFIG_FB=y CONFIG_FB_ARMCLCD=y +CONFIG_FB_WM8505=y CONFIG_FRAMEBUFFER_CONSOLE=y CONFIG_USB=y CONFIG_USB_ISP1760_HCD=y @@ -63,12 +67,16 @@ CONFIG_MMC_ARMMMCI=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_PLTFM=y CONFIG_MMC_SDHCI_SPEAR=y +CONFIG_MMC_WMT=y CONFIG_EDAC=y CONFIG_EDAC_MM_EDAC=y CONFIG_EDAC_HIGHBANK_MC=y CONFIG_EDAC_HIGHBANK_L2=y CONFIG_RTC_CLASS=y CONFIG_RTC_DRV_PL031=y +CONFIG_RTC_DRV_VT8500=y +CONFIG_PWM=y +CONFIG_PWM_VT8500=y CONFIG_DMADEVICES=y CONFIG_PL330_DMA=y CONFIG_SIRF_DMA=y -- cgit v1.1 From 45680995cd8ccf5eb71a1808eb96408589d37a26 Mon Sep 17 00:00:00 2001 From: Shawn Guo Date: Fri, 29 Mar 2013 14:41:27 +0800 Subject: ARM: mxs: call mxs_pm_init() as a machine_desc hook The device_initcall is not a friend of multiplatform build. Call mxs_pm_init() as a machine_desc hook instead of device_initcall. Signed-off-by: Shawn Guo --- arch/arm/mach-mxs/mach-mxs.c | 3 +++ arch/arm/mach-mxs/pm.c | 4 +--- arch/arm/mach-mxs/pm.h | 14 ++++++++++++++ 3 files changed, 18 insertions(+), 3 deletions(-) create mode 100644 arch/arm/mach-mxs/pm.h (limited to 'arch/arm') diff --git a/arch/arm/mach-mxs/mach-mxs.c b/arch/arm/mach-mxs/mach-mxs.c index 16870bf..b5c1bdd 100644 --- a/arch/arm/mach-mxs/mach-mxs.c +++ b/arch/arm/mach-mxs/mach-mxs.c @@ -32,6 +32,8 @@ #include #include +#include "pm.h" + /* MXS DIGCTL SAIF CLKMUX */ #define MXS_DIGCTL_SAIF_CLKMUX_DIRECT 0x0 #define MXS_DIGCTL_SAIF_CLKMUX_CROSSINPUT 0x1 @@ -607,6 +609,7 @@ DT_MACHINE_START(MXS, "Freescale MXS (Device Tree)") .handle_irq = icoll_handle_irq, .init_time = mxs_timer_init, .init_machine = mxs_machine_init, + .init_late = mxs_pm_init, .dt_compat = mxs_dt_compat, .restart = mxs_restart, MACHINE_END diff --git a/arch/arm/mach-mxs/pm.c b/arch/arm/mach-mxs/pm.c index a9b4bbc..b2494d2 100644 --- a/arch/arm/mach-mxs/pm.c +++ b/arch/arm/mach-mxs/pm.c @@ -34,9 +34,7 @@ static struct platform_suspend_ops mxs_suspend_ops = { .valid = suspend_valid_only_mem, }; -static int __init mxs_pm_init(void) +void __init mxs_pm_init(void) { suspend_set_ops(&mxs_suspend_ops); - return 0; } -device_initcall(mxs_pm_init); diff --git a/arch/arm/mach-mxs/pm.h b/arch/arm/mach-mxs/pm.h new file mode 100644 index 0000000..f57e7cd --- /dev/null +++ b/arch/arm/mach-mxs/pm.h @@ -0,0 +1,14 @@ +/* + * Copyright (C) 2013 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ARCH_MXS_PM_H +#define __ARCH_MXS_PM_H + +void mxs_pm_init(void); + +#endif -- cgit v1.1 From e91411b44d54db96c3d2d365b195b112e513d4ba Mon Sep 17 00:00:00 2001 From: Shawn Guo Date: Fri, 29 Mar 2013 14:30:07 +0800 Subject: ARM: mxs: rename debug-macro.S for multiplatform build Rename arch/arm/mach-mxs/include/mach/debug-macro.S to arch/arm/include/debug/mxs.S for multiplatform build. Signed-off-by: Shawn Guo --- arch/arm/Kconfig.debug | 1 + arch/arm/include/debug/mxs.S | 27 +++++++++++++++++++++++++++ arch/arm/mach-mxs/include/mach/debug-macro.S | 27 --------------------------- 3 files changed, 28 insertions(+), 27 deletions(-) create mode 100644 arch/arm/include/debug/mxs.S delete mode 100644 arch/arm/mach-mxs/include/mach/debug-macro.S (limited to 'arch/arm') diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug index 9b31f43..057601e 100644 --- a/arch/arm/Kconfig.debug +++ b/arch/arm/Kconfig.debug @@ -591,6 +591,7 @@ config DEBUG_LL_INCLUDE DEBUG_IMX6Q_UART default "debug/highbank.S" if DEBUG_HIGHBANK_UART default "debug/mvebu.S" if DEBUG_MVEBU_UART + default "debug/mxs.S" if DEBUG_IMX23_UART || DEBUG_IMX28_UART default "debug/omap2plus.S" if DEBUG_OMAP2PLUS_UART default "debug/picoxcell.S" if DEBUG_PICOXCELL_UART default "debug/socfpga.S" if DEBUG_SOCFPGA_UART diff --git a/arch/arm/include/debug/mxs.S b/arch/arm/include/debug/mxs.S new file mode 100644 index 0000000..d869515 --- /dev/null +++ b/arch/arm/include/debug/mxs.S @@ -0,0 +1,27 @@ +/* arch/arm/mach-mxs/include/mach/debug-macro.S + * + * Debugging macro include header + * + * Copyright (C) 1994-1999 Russell King + * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#ifdef CONFIG_DEBUG_IMX23_UART +#define UART_PADDR 0x80070000 +#elif defined (CONFIG_DEBUG_IMX28_UART) +#define UART_PADDR 0x80074000 +#endif + +#define UART_VADDR 0xfe100000 + + .macro addruart, rp, rv, tmp + ldr \rp, =UART_PADDR @ physical + ldr \rv, =UART_VADDR @ virtual + .endm + +#include diff --git a/arch/arm/mach-mxs/include/mach/debug-macro.S b/arch/arm/mach-mxs/include/mach/debug-macro.S deleted file mode 100644 index d869515..0000000 --- a/arch/arm/mach-mxs/include/mach/debug-macro.S +++ /dev/null @@ -1,27 +0,0 @@ -/* arch/arm/mach-mxs/include/mach/debug-macro.S - * - * Debugging macro include header - * - * Copyright (C) 1994-1999 Russell King - * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - */ - -#ifdef CONFIG_DEBUG_IMX23_UART -#define UART_PADDR 0x80070000 -#elif defined (CONFIG_DEBUG_IMX28_UART) -#define UART_PADDR 0x80074000 -#endif - -#define UART_VADDR 0xfe100000 - - .macro addruart, rp, rv, tmp - ldr \rp, =UART_PADDR @ physical - ldr \rv, =UART_VADDR @ virtual - .endm - -#include -- cgit v1.1 From d696e3f6585ddeb7bddbf0783b649fa669459a5c Mon Sep 17 00:00:00 2001 From: Shawn Guo Date: Fri, 29 Mar 2013 16:25:43 +0800 Subject: ARM: mxs: enable multiplatform build Remove files that are not needed by multiplatform build, and make necessary changes on Kconfig to enable multiplatform build. Signed-off-by: Shawn Guo --- arch/arm/Kconfig | 17 ------- arch/arm/configs/mxs_defconfig | 2 +- arch/arm/mach-mxs/Kconfig | 22 +++++---- arch/arm/mach-mxs/Makefile | 2 +- arch/arm/mach-mxs/Makefile.boot | 1 - arch/arm/mach-mxs/include/mach/timex.h | 21 -------- arch/arm/mach-mxs/include/mach/uncompress.h | 76 ----------------------------- 7 files changed, 14 insertions(+), 127 deletions(-) delete mode 100644 arch/arm/mach-mxs/Makefile.boot delete mode 100644 arch/arm/mach-mxs/include/mach/timex.h delete mode 100644 arch/arm/mach-mxs/include/mach/uncompress.h (limited to 'arch/arm') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 2e4386c..31ca652 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -468,23 +468,6 @@ config ARCH_FOOTBRIDGE Support for systems based on the DC21285 companion chip ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder. -config ARCH_MXS - bool "Freescale MXS-based" - select ARCH_REQUIRE_GPIOLIB - select CLKDEV_LOOKUP - select CLKSRC_MMIO - select CLKSRC_OF - select COMMON_CLK - select GENERIC_CLOCKEVENTS - select HAVE_CLK_PREPARE - select MULTI_IRQ_HANDLER - select PINCTRL - select SPARSE_IRQ - select STMP_DEVICE - select USE_OF - help - Support for Freescale MXS-based family of processors - config ARCH_NETX bool "Hilscher NetX based" select ARM_VIC diff --git a/arch/arm/configs/mxs_defconfig b/arch/arm/configs/mxs_defconfig index 6a99e30..023c4e1 100644 --- a/arch/arm/configs/mxs_defconfig +++ b/arch/arm/configs/mxs_defconfig @@ -22,8 +22,8 @@ CONFIG_MODVERSIONS=y CONFIG_BLK_DEV_INTEGRITY=y # CONFIG_IOSCHED_DEADLINE is not set # CONFIG_IOSCHED_CFQ is not set +# CONFIG_ARCH_MULTI_V7 is not set CONFIG_ARCH_MXS=y -CONFIG_MACH_MXS_DT=y # CONFIG_ARM_THUMB is not set CONFIG_PREEMPT_VOLUNTARY=y CONFIG_AEABI=y diff --git a/arch/arm/mach-mxs/Kconfig b/arch/arm/mach-mxs/Kconfig index ecc4319..02e6935 100644 --- a/arch/arm/mach-mxs/Kconfig +++ b/arch/arm/mach-mxs/Kconfig @@ -1,5 +1,3 @@ -if ARCH_MXS - config SOC_IMX23 bool select ARM_AMBA @@ -15,14 +13,18 @@ config SOC_IMX28 select HAVE_PWM select PINCTRL_IMX28 -comment "MXS platforms:" - -config MACH_MXS_DT - bool "Support MXS platforms from device tree" +config ARCH_MXS + bool "Freescale MXS (i.MX23, i.MX28) support" + depends on ARCH_MULTI_V5 + select ARCH_REQUIRE_GPIOLIB + select CLKDEV_LOOKUP + select CLKSRC_MMIO + select CLKSRC_OF + select GENERIC_CLOCKEVENTS + select HAVE_CLK_PREPARE + select PINCTRL select SOC_IMX23 select SOC_IMX28 + select STMP_DEVICE help - Include support for Freescale MXS platforms(i.MX23 and i.MX28) - using the device tree for discovery - -endif + Support for Freescale MXS-based family of processors diff --git a/arch/arm/mach-mxs/Makefile b/arch/arm/mach-mxs/Makefile index 80db726..cc2bf67 100644 --- a/arch/arm/mach-mxs/Makefile +++ b/arch/arm/mach-mxs/Makefile @@ -1,2 +1,2 @@ obj-$(CONFIG_PM) += pm.o -obj-$(CONFIG_MACH_MXS_DT) += mach-mxs.o +obj-$(CONFIG_ARCH_MXS) += mach-mxs.o diff --git a/arch/arm/mach-mxs/Makefile.boot b/arch/arm/mach-mxs/Makefile.boot deleted file mode 100644 index 07b11fe..0000000 --- a/arch/arm/mach-mxs/Makefile.boot +++ /dev/null @@ -1 +0,0 @@ -zreladdr-y += 0x40008000 diff --git a/arch/arm/mach-mxs/include/mach/timex.h b/arch/arm/mach-mxs/include/mach/timex.h deleted file mode 100644 index 734ce89..0000000 --- a/arch/arm/mach-mxs/include/mach/timex.h +++ /dev/null @@ -1,21 +0,0 @@ -/* - * Copyright (C) 1999 ARM Limited - * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __MACH_MXS_TIMEX_H__ -#define __MACH_MXS_TIMEX_H__ - -#define CLOCK_TICK_RATE 32000 /* 32K */ - -#endif /* __MACH_MXS_TIMEX_H__ */ diff --git a/arch/arm/mach-mxs/include/mach/uncompress.h b/arch/arm/mach-mxs/include/mach/uncompress.h deleted file mode 100644 index 533f518..0000000 --- a/arch/arm/mach-mxs/include/mach/uncompress.h +++ /dev/null @@ -1,76 +0,0 @@ -/* - * arch/arm/mach-mxs/include/mach/uncompress.h - * - * Copyright (C) 1999 ARM Limited - * Copyright (C) Shane Nay (shane@minirl.com) - * Copyright 2010 Freescale Semiconductor, Inc. All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ -#ifndef __MACH_MXS_UNCOMPRESS_H__ -#define __MACH_MXS_UNCOMPRESS_H__ - -unsigned long mxs_duart_base; - -#define MXS_DUART(x) (*(volatile unsigned long *)(mxs_duart_base + (x))) - -#define MXS_DUART_DR 0x00 -#define MXS_DUART_FR 0x18 -#define MXS_DUART_FR_TXFE (1 << 7) -#define MXS_DUART_CR 0x30 -#define MXS_DUART_CR_UARTEN (1 << 0) - -/* - * The following code assumes the serial port has already been - * initialized by the bootloader. If it's not, the output is - * simply discarded. - */ - -static void putc(int ch) -{ - if (!mxs_duart_base) - return; - if (!(MXS_DUART(MXS_DUART_CR) & MXS_DUART_CR_UARTEN)) - return; - - while (!(MXS_DUART(MXS_DUART_FR) & MXS_DUART_FR_TXFE)) - barrier(); - - MXS_DUART(MXS_DUART_DR) = ch; -} - -static inline void flush(void) -{ -} - -#define MX23_DUART_BASE_ADDR 0x80070000 -#define MX28_DUART_BASE_ADDR 0x80074000 -#define MXS_DIGCTL_CHIPID 0x8001c310 - -static inline void __arch_decomp_setup(unsigned long arch_id) -{ - u16 chipid = (*(volatile unsigned long *) MXS_DIGCTL_CHIPID) >> 16; - - switch (chipid) { - case 0x3780: - mxs_duart_base = MX23_DUART_BASE_ADDR; - break; - case 0x2800: - mxs_duart_base = MX28_DUART_BASE_ADDR; - break; - default: - break; - } -} - -#define arch_decomp_setup() __arch_decomp_setup(arch_id) - -#endif /* __MACH_MXS_UNCOMPRESS_H__ */ -- cgit v1.1 From 9a47a8dccf8866b497bd80809da1c665e7b07c2c Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Thu, 21 Mar 2013 12:27:25 +0100 Subject: mfd: prcmu: pass a base and size with the early initcall This patch will make an early remapping of the PRCMU, to be used when setting up the clocks, that will call down into parts of the PRCMU driver before it is probed. Going forward this will be removed like this: - The mailbox subsystem need to be merged. http://marc.info/?l=linux-kernel&m=136314559201983&w=2 - At this point the PRCMU clock code can be moved over to the ux500 clock driver in drivers/clk/ux500/* and maintained there in a decentralized manner. - This early initcall and PRCMU base parameters become part of the ux500_clk_init() call instead. Cc: Suman Anna Cc: Loic Pallardy Acked-by: Samuel Ortiz Acked-by: Arnd Bergmann Acked-by: Ulf Hansson Signed-off-by: Linus Walleij --- arch/arm/mach-ux500/cpu.c | 15 +++++++++------ 1 file changed, 9 insertions(+), 6 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-ux500/cpu.c b/arch/arm/mach-ux500/cpu.c index 537870d..6d3b57d 100644 --- a/arch/arm/mach-ux500/cpu.c +++ b/arch/arm/mach-ux500/cpu.c @@ -8,7 +8,7 @@ #include #include -#include +#include #include #include #include @@ -68,13 +68,16 @@ void __init ux500_init_irq(void) * Init clocks here so that they are available for system timer * initialization. */ - if (cpu_is_u8500_family() || cpu_is_u9540()) - db8500_prcmu_early_init(); - - if (cpu_is_u8500_family() || cpu_is_u9540()) + if (cpu_is_u8500_family()) { + prcmu_early_init(U8500_PRCMU_BASE, SZ_8K - 1); + u8500_clk_init(); + } else if (cpu_is_u9540()) { + prcmu_early_init(U8500_PRCMU_BASE, SZ_8K - 1); u8500_clk_init(); - else if (cpu_is_u8540()) + } else if (cpu_is_u8540()) { + prcmu_early_init(U8500_PRCMU_BASE, SZ_8K + SZ_4K - 1); u8540_clk_init(); + } } void __init ux500_init_late(void) -- cgit v1.1 From b047d98127ccbf9fe83b6192a3562b3ead0b2415 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Tue, 19 Mar 2013 14:21:47 +0100 Subject: mfd: db8500-prcmu: get base address from resource We cannot use a global variable stored in to find the base address of the PRCMU. The real resource is already there from the board, so use this to look up the base address instead. Currently the patch is kept minimal so as not to interfere with other work being done on refactoring this driver, but at a later point the defines using (prcmu_base + 0xnnn) need to be replaced by pure offset defined for (0xnnn) and the base inlined with the readl()/writel() and similar codepaths. Acked-by: Samuel Ortiz Signed-off-by: Linus Walleij --- arch/arm/mach-ux500/cpu-db8500.c | 2 -- arch/arm/mach-ux500/cpu.c | 2 -- arch/arm/mach-ux500/include/mach/hardware.h | 2 -- 3 files changed, 6 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-ux500/cpu-db8500.c b/arch/arm/mach-ux500/cpu-db8500.c index 19235cf..8c58dff 100644 --- a/arch/arm/mach-ux500/cpu-db8500.c +++ b/arch/arm/mach-ux500/cpu-db8500.c @@ -94,8 +94,6 @@ void __init u8500_map_io(void) iotable_init(u9540_io_desc, ARRAY_SIZE(u9540_io_desc)); else iotable_init(u8500_io_desc, ARRAY_SIZE(u8500_io_desc)); - - _PRCMU_BASE = __io_address(U8500_PRCMU_BASE); } static struct resource db8500_pmu_resources[] = { diff --git a/arch/arm/mach-ux500/cpu.c b/arch/arm/mach-ux500/cpu.c index 6d3b57d..6f8e152 100644 --- a/arch/arm/mach-ux500/cpu.c +++ b/arch/arm/mach-ux500/cpu.c @@ -30,8 +30,6 @@ #include "board-mop500.h" #include "id.h" -void __iomem *_PRCMU_BASE; - /* * FIXME: Should we set up the GPIO domain here? * diff --git a/arch/arm/mach-ux500/include/mach/hardware.h b/arch/arm/mach-ux500/include/mach/hardware.h index 5201dda..4eece2af 100644 --- a/arch/arm/mach-ux500/include/mach/hardware.h +++ b/arch/arm/mach-ux500/include/mach/hardware.h @@ -39,8 +39,6 @@ #ifndef __ASSEMBLY__ -extern void __iomem *_PRCMU_BASE; - #define ARRAY_AND_SIZE(x) (x), ARRAY_SIZE(x) #endif /* __ASSEMBLY__ */ -- cgit v1.1 From 1e22a8c614a5d8c29d0882de21ce327673b71fca Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Tue, 19 Mar 2013 15:36:12 +0100 Subject: ARM: ux500: move PM-related PRCMU functions to machine We are trying to decompose and decentralize the code in the DB8500 PRCMU out into subdrivers. The code moved in this patch concerns a group of functions used for decoupling and recoupling the IRQs from the GIC. During sleep and idle the Ux500 system will transfer all IRQ handling to the PRCMU using these functions. Basically we are left with the two alternatives of code placement as: - arch/arm/mach-ux500/pm.c - this because the code is closely related to the GIC, and takes ownership of some of the registers from the PRCMU related to this PM functionality. - drivers/mfd/db8500-prcmu-pm.c - because the code is affecting stuff in the PRCMU register range. But then this code needs to remap and handle GIC registers. This patch implementation is taking the first approach. Currently the cpuidle driver is the only piece of code using this set of functions, but it will later also be used by the suspend/resume code which is currently under review. The header file is moved to: The function prototypes need to be placed in a globally visible header since the CPUidle code is planned to move out to drivers/cpuidle. Acked-by: Samuel Ortiz Acked-by: Rickard Andersson Acked-by: Daniel Lezcano Signed-off-by: Linus Walleij --- arch/arm/mach-ux500/Makefile | 2 +- arch/arm/mach-ux500/cpu.c | 4 + arch/arm/mach-ux500/cpuidle.c | 3 +- arch/arm/mach-ux500/pm.c | 167 ++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 174 insertions(+), 2 deletions(-) create mode 100644 arch/arm/mach-ux500/pm.c (limited to 'arch/arm') diff --git a/arch/arm/mach-ux500/Makefile b/arch/arm/mach-ux500/Makefile index f24710d..580a4db 100644 --- a/arch/arm/mach-ux500/Makefile +++ b/arch/arm/mach-ux500/Makefile @@ -3,7 +3,7 @@ # obj-y := cpu.o devices.o devices-common.o \ - id.o usb.o timer.o + id.o usb.o timer.o pm.o obj-$(CONFIG_CPU_IDLE) += cpuidle.o obj-$(CONFIG_CACHE_L2X0) += cache-l2x0.o obj-$(CONFIG_UX500_SOC_DB8500) += cpu-db8500.o devices-db8500.o diff --git a/arch/arm/mach-ux500/cpu.c b/arch/arm/mach-ux500/cpu.c index 6f8e152..2c5c48b 100644 --- a/arch/arm/mach-ux500/cpu.c +++ b/arch/arm/mach-ux500/cpu.c @@ -20,6 +20,7 @@ #include #include #include +#include #include @@ -68,12 +69,15 @@ void __init ux500_init_irq(void) */ if (cpu_is_u8500_family()) { prcmu_early_init(U8500_PRCMU_BASE, SZ_8K - 1); + ux500_pm_init(U8500_PRCMU_BASE, SZ_8K - 1); u8500_clk_init(); } else if (cpu_is_u9540()) { prcmu_early_init(U8500_PRCMU_BASE, SZ_8K - 1); + ux500_pm_init(U8500_PRCMU_BASE, SZ_8K - 1); u8500_clk_init(); } else if (cpu_is_u8540()) { prcmu_early_init(U8500_PRCMU_BASE, SZ_8K + SZ_4K - 1); + ux500_pm_init(U8500_PRCMU_BASE, SZ_8K + SZ_4K - 1); u8540_clk_init(); } } diff --git a/arch/arm/mach-ux500/cpuidle.c b/arch/arm/mach-ux500/cpuidle.c index ce91493..1e5bb66 100644 --- a/arch/arm/mach-ux500/cpuidle.c +++ b/arch/arm/mach-ux500/cpuidle.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #include @@ -130,7 +131,7 @@ int __init ux500_idle_init(void) int ret, cpu; struct cpuidle_device *device; - /* Configure wake up reasons */ + /* Configure wake up reasons */ prcmu_enable_wakeups(PRCMU_WAKEUP(ARM) | PRCMU_WAKEUP(RTC) | PRCMU_WAKEUP(ABB)); diff --git a/arch/arm/mach-ux500/pm.c b/arch/arm/mach-ux500/pm.c new file mode 100644 index 0000000..6949a13 --- /dev/null +++ b/arch/arm/mach-ux500/pm.c @@ -0,0 +1,167 @@ +/* + * Copyright (C) ST-Ericsson SA 2010-2013 + * Author: Rickard Andersson for + * ST-Ericsson. + * Author: Daniel Lezcano for Linaro. + * License terms: GNU General Public License (GPL) version 2 + * + */ + +#include +#include +#include +#include +#include + +#include + +/* ARM WFI Standby signal register */ +#define PRCM_ARM_WFI_STANDBY (prcmu_base + 0x130) +#define PRCM_ARM_WFI_STANDBY_WFI0 0x08 +#define PRCM_ARM_WFI_STANDBY_WFI1 0x10 +#define PRCM_IOCR (prcmu_base + 0x310) +#define PRCM_IOCR_IOFORCE 0x1 + +/* Dual A9 core interrupt management unit registers */ +#define PRCM_A9_MASK_REQ (prcmu_base + 0x328) +#define PRCM_A9_MASK_REQ_PRCM_A9_MASK_REQ 0x1 + +#define PRCM_A9_MASK_ACK (prcmu_base + 0x32c) +#define PRCM_ARMITMSK31TO0 (prcmu_base + 0x11c) +#define PRCM_ARMITMSK63TO32 (prcmu_base + 0x120) +#define PRCM_ARMITMSK95TO64 (prcmu_base + 0x124) +#define PRCM_ARMITMSK127TO96 (prcmu_base + 0x128) +#define PRCM_POWER_STATE_VAL (prcmu_base + 0x25C) +#define PRCM_ARMITVAL31TO0 (prcmu_base + 0x260) +#define PRCM_ARMITVAL63TO32 (prcmu_base + 0x264) +#define PRCM_ARMITVAL95TO64 (prcmu_base + 0x268) +#define PRCM_ARMITVAL127TO96 (prcmu_base + 0x26C) + +static void __iomem *prcmu_base; + +/* This function decouple the gic from the prcmu */ +int prcmu_gic_decouple(void) +{ + u32 val = readl(PRCM_A9_MASK_REQ); + + /* Set bit 0 register value to 1 */ + writel(val | PRCM_A9_MASK_REQ_PRCM_A9_MASK_REQ, + PRCM_A9_MASK_REQ); + + /* Make sure the register is updated */ + readl(PRCM_A9_MASK_REQ); + + /* Wait a few cycles for the gic mask completion */ + udelay(1); + + return 0; +} + +/* This function recouple the gic with the prcmu */ +int prcmu_gic_recouple(void) +{ + u32 val = readl(PRCM_A9_MASK_REQ); + + /* Set bit 0 register value to 0 */ + writel(val & ~PRCM_A9_MASK_REQ_PRCM_A9_MASK_REQ, PRCM_A9_MASK_REQ); + + return 0; +} + +#define PRCMU_GIC_NUMBER_REGS 5 + +/* + * This function checks if there are pending irq on the gic. It only + * makes sense if the gic has been decoupled before with the + * db8500_prcmu_gic_decouple function. Disabling an interrupt only + * disables the forwarding of the interrupt to any CPU interface. It + * does not prevent the interrupt from changing state, for example + * becoming pending, or active and pending if it is already + * active. Hence, we have to check the interrupt is pending *and* is + * active. + */ +bool prcmu_gic_pending_irq(void) +{ + u32 pr; /* Pending register */ + u32 er; /* Enable register */ + void __iomem *dist_base = __io_address(U8500_GIC_DIST_BASE); + int i; + + /* 5 registers. STI & PPI not skipped */ + for (i = 0; i < PRCMU_GIC_NUMBER_REGS; i++) { + + pr = readl_relaxed(dist_base + GIC_DIST_PENDING_SET + i * 4); + er = readl_relaxed(dist_base + GIC_DIST_ENABLE_SET + i * 4); + + if (pr & er) + return true; /* There is a pending interrupt */ + } + + return false; +} + +/* + * This function checks if there are pending interrupt on the + * prcmu which has been delegated to monitor the irqs with the + * db8500_prcmu_copy_gic_settings function. + */ +bool prcmu_pending_irq(void) +{ + u32 it, im; + int i; + + for (i = 0; i < PRCMU_GIC_NUMBER_REGS - 1; i++) { + it = readl(PRCM_ARMITVAL31TO0 + i * 4); + im = readl(PRCM_ARMITMSK31TO0 + i * 4); + if (it & im) + return true; /* There is a pending interrupt */ + } + + return false; +} + +/* + * This function checks if the specified cpu is in in WFI. It's usage + * makes sense only if the gic is decoupled with the db8500_prcmu_gic_decouple + * function. Of course passing smp_processor_id() to this function will + * always return false... + */ +bool prcmu_is_cpu_in_wfi(int cpu) +{ + return readl(PRCM_ARM_WFI_STANDBY) & cpu ? PRCM_ARM_WFI_STANDBY_WFI1 : + PRCM_ARM_WFI_STANDBY_WFI0; +} + +/* + * This function copies the gic SPI settings to the prcmu in order to + * monitor them and abort/finish the retention/off sequence or state. + */ +int prcmu_copy_gic_settings(void) +{ + u32 er; /* Enable register */ + void __iomem *dist_base = __io_address(U8500_GIC_DIST_BASE); + int i; + + /* We skip the STI and PPI */ + for (i = 0; i < PRCMU_GIC_NUMBER_REGS - 1; i++) { + er = readl_relaxed(dist_base + + GIC_DIST_ENABLE_SET + (i + 1) * 4); + writel(er, PRCM_ARMITMSK31TO0 + i * 4); + } + + return 0; +} + +void __init ux500_pm_init(u32 phy_base, u32 size) +{ + prcmu_base = ioremap(phy_base, size); + if (!prcmu_base) { + pr_err("could not remap PRCMU for PM functions\n"); + return; + } + /* + * On watchdog reboot the GIC is in some cases decoupled. + * This will make sure that the GIC is correctly configured. + */ + prcmu_gic_recouple(); +} -- cgit v1.1 From 55b175d7e6327939df82592ef279c534da323354 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Thu, 21 Mar 2013 22:51:07 +0100 Subject: ARM: ux500: split out prcmu initialization This untangles the final bits of the prcmu code from the platform code: * The IRQ_PRCMU_* definitions move from irqs-db8500.h into prcmu.c because they are only of local significance. * u8500_thsens_device goes into the prcmu, because it uses a PRCMU IRQ that the platform does not see. * IRQ_DB8500_AB8500 and IRQ_PRCMU_BASE go into the platform data because the PRCMU does not see it. Acked-by: Samuel Ortiz Signed-off-by: Arnd Bergmann [Fixed a oneliner bug] Signed-off-by: Linus Walleij --- arch/arm/mach-ux500/board-mop500.c | 58 -------------------------- arch/arm/mach-ux500/devices-db8500.c | 2 + arch/arm/mach-ux500/include/mach/irqs-db8500.h | 25 ----------- 3 files changed, 2 insertions(+), 83 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c index b034578..fe3d72c 100644 --- a/arch/arm/mach-ux500/board-mop500.c +++ b/arch/arm/mach-ux500/board-mop500.c @@ -206,63 +206,6 @@ struct ab8500_platform_data ab8500_platdata = { .codec = &ab8500_codec_pdata, }; -/* - * Thermal Sensor - */ - -static struct resource db8500_thsens_resources[] = { - { - .name = "IRQ_HOTMON_LOW", - .start = IRQ_PRCMU_HOTMON_LOW, - .end = IRQ_PRCMU_HOTMON_LOW, - .flags = IORESOURCE_IRQ, - }, - { - .name = "IRQ_HOTMON_HIGH", - .start = IRQ_PRCMU_HOTMON_HIGH, - .end = IRQ_PRCMU_HOTMON_HIGH, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct db8500_thsens_platform_data db8500_thsens_data = { - .trip_points[0] = { - .temp = 70000, - .type = THERMAL_TRIP_ACTIVE, - .cdev_name = { - [0] = "thermal-cpufreq-0", - }, - }, - .trip_points[1] = { - .temp = 75000, - .type = THERMAL_TRIP_ACTIVE, - .cdev_name = { - [0] = "thermal-cpufreq-0", - }, - }, - .trip_points[2] = { - .temp = 80000, - .type = THERMAL_TRIP_ACTIVE, - .cdev_name = { - [0] = "thermal-cpufreq-0", - }, - }, - .trip_points[3] = { - .temp = 85000, - .type = THERMAL_TRIP_CRITICAL, - }, - .num_trips = 4, -}; - -static struct platform_device u8500_thsens_device = { - .name = "db8500-thermal", - .resource = db8500_thsens_resources, - .num_resources = ARRAY_SIZE(db8500_thsens_resources), - .dev = { - .platform_data = &db8500_thsens_data, - }, -}; - static struct platform_device u8500_cpufreq_cooling_device = { .name = "db8500-cpufreq-cooling", }; @@ -622,7 +565,6 @@ static struct platform_device *snowball_platform_devs[] __initdata = { &snowball_key_dev, &snowball_sbnet_dev, &snowball_gpio_en_3v3_regulator_dev, - &u8500_thsens_device, &u8500_cpufreq_cooling_device, }; diff --git a/arch/arm/mach-ux500/devices-db8500.c b/arch/arm/mach-ux500/devices-db8500.c index f3d9419..df4d7de 100644 --- a/arch/arm/mach-ux500/devices-db8500.c +++ b/arch/arm/mach-ux500/devices-db8500.c @@ -199,6 +199,8 @@ struct platform_device u8500_ske_keypad_device = { struct prcmu_pdata db8500_prcmu_pdata = { .ab_platdata = &ab8500_platdata, + .ab_irq = IRQ_DB8500_AB8500, + .irq_base = IRQ_PRCMU_BASE, .version_offset = DB8500_PRCMU_FW_VERSION_OFFSET, .legacy_offset = DB8500_PRCMU_LEGACY_OFFSET, }; diff --git a/arch/arm/mach-ux500/include/mach/irqs-db8500.h b/arch/arm/mach-ux500/include/mach/irqs-db8500.h index 68bc149..f3a9d59 100644 --- a/arch/arm/mach-ux500/include/mach/irqs-db8500.h +++ b/arch/arm/mach-ux500/include/mach/irqs-db8500.h @@ -109,31 +109,6 @@ /* Virtual interrupts corresponding to the PRCMU wakeups. */ #define IRQ_PRCMU_BASE IRQ_SOC_START -#define NUM_PRCMU_WAKEUPS (IRQ_PRCMU_END - IRQ_PRCMU_BASE) - -#define IRQ_PRCMU_RTC (IRQ_PRCMU_BASE) -#define IRQ_PRCMU_RTT0 (IRQ_PRCMU_BASE + 1) -#define IRQ_PRCMU_RTT1 (IRQ_PRCMU_BASE + 2) -#define IRQ_PRCMU_HSI0 (IRQ_PRCMU_BASE + 3) -#define IRQ_PRCMU_HSI1 (IRQ_PRCMU_BASE + 4) -#define IRQ_PRCMU_CA_WAKE (IRQ_PRCMU_BASE + 5) -#define IRQ_PRCMU_USB (IRQ_PRCMU_BASE + 6) -#define IRQ_PRCMU_ABB (IRQ_PRCMU_BASE + 7) -#define IRQ_PRCMU_ABB_FIFO (IRQ_PRCMU_BASE + 8) -#define IRQ_PRCMU_ARM (IRQ_PRCMU_BASE + 9) -#define IRQ_PRCMU_MODEM_SW_RESET_REQ (IRQ_PRCMU_BASE + 10) -#define IRQ_PRCMU_GPIO0 (IRQ_PRCMU_BASE + 11) -#define IRQ_PRCMU_GPIO1 (IRQ_PRCMU_BASE + 12) -#define IRQ_PRCMU_GPIO2 (IRQ_PRCMU_BASE + 13) -#define IRQ_PRCMU_GPIO3 (IRQ_PRCMU_BASE + 14) -#define IRQ_PRCMU_GPIO4 (IRQ_PRCMU_BASE + 15) -#define IRQ_PRCMU_GPIO5 (IRQ_PRCMU_BASE + 16) -#define IRQ_PRCMU_GPIO6 (IRQ_PRCMU_BASE + 17) -#define IRQ_PRCMU_GPIO7 (IRQ_PRCMU_BASE + 18) -#define IRQ_PRCMU_GPIO8 (IRQ_PRCMU_BASE + 19) -#define IRQ_PRCMU_CA_SLEEP (IRQ_PRCMU_BASE + 20) -#define IRQ_PRCMU_HOTMON_LOW (IRQ_PRCMU_BASE + 21) -#define IRQ_PRCMU_HOTMON_HIGH (IRQ_PRCMU_BASE + 22) #define IRQ_PRCMU_END (IRQ_PRCMU_BASE + 23) /* -- cgit v1.1 From f87b95dd2e4a8832b1d6034f15a5324db42608a0 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Tue, 19 Mar 2013 11:01:36 +0100 Subject: ARM: ux500: move debugmacro to debug includes This moves the Ux500 debug macro to the debug headers to make way for multiplatform support. Acked-by: Arnd Bergmann Signed-off-by: Linus Walleij --- arch/arm/Kconfig.debug | 8 ++++++ arch/arm/include/debug/ux500.S | 39 ++++++++++++++++++++++++++ arch/arm/mach-ux500/include/mach/debug-macro.S | 39 -------------------------- 3 files changed, 47 insertions(+), 39 deletions(-) create mode 100644 arch/arm/include/debug/ux500.S delete mode 100644 arch/arm/mach-ux500/include/mach/debug-macro.S (limited to 'arch/arm') diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug index ecfcdba..2ac4a20 100644 --- a/arch/arm/Kconfig.debug +++ b/arch/arm/Kconfig.debug @@ -414,6 +414,13 @@ choice Say Y here if you want the debug print routines to direct their output to the uart1 port on SiRFmarco devices. + config DEBUG_UX500_UART + depends on ARCH_U8500 + bool "Use Ux500 UART for low-level debug" + help + Say Y here if you want kernel low-level debugging support + on Ux500 based platforms. + config DEBUG_VEXPRESS_UART0_DETECT bool "Autodetect UART0 on Versatile Express Cortex-A core tiles" depends on ARCH_VEXPRESS && CPU_CP15_MMU @@ -598,6 +605,7 @@ config DEBUG_LL_INCLUDE DEBUG_VEXPRESS_UART0_CA9 || DEBUG_VEXPRESS_UART0_RS1 default "debug/vt8500.S" if DEBUG_VT8500_UART0 default "debug/tegra.S" if DEBUG_TEGRA_UART + default "debug/ux500.S" if DEBUG_UX500_UART default "debug/zynq.S" if DEBUG_ZYNQ_UART0 || DEBUG_ZYNQ_UART1 default "mach/debug-macro.S" diff --git a/arch/arm/include/debug/ux500.S b/arch/arm/include/debug/ux500.S new file mode 100644 index 0000000..6703522 --- /dev/null +++ b/arch/arm/include/debug/ux500.S @@ -0,0 +1,39 @@ +/* + * Debugging macro include header + * + * Copyright (C) 2009 ST-Ericsson + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ +#include + +#if CONFIG_UX500_DEBUG_UART > 2 +#error Invalid Ux500 debug UART +#endif + +/* + * DEBUG_LL only works if only one SOC is built in. We don't use #else below + * in order to get "__UX500_UART redefined" warnings if more than one SOC is + * built, so that there's some hint during the build that something is wrong. + */ + +#ifdef CONFIG_UX500_SOC_DB8500 +#define __UX500_UART(n) U8500_UART##n##_BASE +#endif + +#ifndef __UX500_UART +#error Unknown SOC +#endif + +#define UX500_UART(n) __UX500_UART(n) +#define UART_BASE UX500_UART(CONFIG_UX500_DEBUG_UART) + + .macro addruart, rp, rv, tmp + ldr \rp, =UART_BASE @ no, physical address + ldr \rv, =IO_ADDRESS(UART_BASE) @ yes, virtual address + .endm + +#include diff --git a/arch/arm/mach-ux500/include/mach/debug-macro.S b/arch/arm/mach-ux500/include/mach/debug-macro.S deleted file mode 100644 index 6703522..0000000 --- a/arch/arm/mach-ux500/include/mach/debug-macro.S +++ /dev/null @@ -1,39 +0,0 @@ -/* - * Debugging macro include header - * - * Copyright (C) 2009 ST-Ericsson - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - */ -#include - -#if CONFIG_UX500_DEBUG_UART > 2 -#error Invalid Ux500 debug UART -#endif - -/* - * DEBUG_LL only works if only one SOC is built in. We don't use #else below - * in order to get "__UX500_UART redefined" warnings if more than one SOC is - * built, so that there's some hint during the build that something is wrong. - */ - -#ifdef CONFIG_UX500_SOC_DB8500 -#define __UX500_UART(n) U8500_UART##n##_BASE -#endif - -#ifndef __UX500_UART -#error Unknown SOC -#endif - -#define UX500_UART(n) __UX500_UART(n) -#define UART_BASE UX500_UART(CONFIG_UX500_DEBUG_UART) - - .macro addruart, rp, rv, tmp - ldr \rp, =UART_BASE @ no, physical address - ldr \rv, =IO_ADDRESS(UART_BASE) @ yes, virtual address - .endm - -#include -- cgit v1.1 From 9bed3e05e94fbdfc986fba4be7fa5e83db909874 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Fri, 5 Apr 2013 16:07:31 +0200 Subject: ARM: ux500: make debug macro stand-alone This pushes the knowledge of physical addresses down into the debug macro so we can get rid of the dependency. Signed-off-by: Linus Walleij --- arch/arm/include/debug/ux500.S | 23 ++++++++++++++++------- 1 file changed, 16 insertions(+), 7 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/include/debug/ux500.S b/arch/arm/include/debug/ux500.S index 6703522..2848857 100644 --- a/arch/arm/include/debug/ux500.S +++ b/arch/arm/include/debug/ux500.S @@ -8,7 +8,7 @@ * published by the Free Software Foundation. * */ -#include + #if CONFIG_UX500_DEBUG_UART > 2 #error Invalid Ux500 debug UART @@ -21,19 +21,28 @@ */ #ifdef CONFIG_UX500_SOC_DB8500 -#define __UX500_UART(n) U8500_UART##n##_BASE +#define U8500_UART0_PHYS_BASE (0x80120000) +#define U8500_UART1_PHYS_BASE (0x80121000) +#define U8500_UART2_PHYS_BASE (0x80007000) +#define U8500_UART0_VIRT_BASE (0xa8120000) +#define U8500_UART1_VIRT_BASE (0xa8121000) +#define U8500_UART2_VIRT_BASE (0xa8007000) +#define __UX500_PHYS_UART(n) U8500_UART##n##_PHYS_BASE +#define __UX500_VIRT_UART(n) U8500_UART##n##_VIRT_BASE #endif -#ifndef __UX500_UART +#if !defined(__UX500_PHYS_UART) || !defined(__UX500_VIRT_UART) #error Unknown SOC #endif -#define UX500_UART(n) __UX500_UART(n) -#define UART_BASE UX500_UART(CONFIG_UX500_DEBUG_UART) +#define UX500_PHYS_UART(n) __UX500_PHYS_UART(n) +#define UX500_VIRT_UART(n) __UX500_VIRT_UART(n) +#define UART_PHYS_BASE UX500_PHYS_UART(CONFIG_UX500_DEBUG_UART) +#define UART_VIRT_BASE UX500_VIRT_UART(CONFIG_UX500_DEBUG_UART) .macro addruart, rp, rv, tmp - ldr \rp, =UART_BASE @ no, physical address - ldr \rv, =IO_ADDRESS(UART_BASE) @ yes, virtual address + ldr \rp, =UART_PHYS_BASE @ no, physical address + ldr \rv, =UART_VIRT_BASE @ yes, virtual address .endm #include -- cgit v1.1 From 9b819060d349e2247c471d8f055c91a597560da0 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Tue, 19 Mar 2013 11:21:56 +0100 Subject: clk: ux500: pass clock base adresses in init call The ux500 clock driver was including which will not work when building for multiplatform support since is going away. Pass the base adresses in the init call instead. Cc: Ulf Hansson Cc: Mike Turquette Acked-by: Arnd Bergmann Acked-by: Ulf Hansson Acked-by: Mike Turquette Signed-off-by: Linus Walleij --- arch/arm/mach-ux500/cpu.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-ux500/cpu.c b/arch/arm/mach-ux500/cpu.c index 2c5c48b..ee69439d 100644 --- a/arch/arm/mach-ux500/cpu.c +++ b/arch/arm/mach-ux500/cpu.c @@ -70,11 +70,15 @@ void __init ux500_init_irq(void) if (cpu_is_u8500_family()) { prcmu_early_init(U8500_PRCMU_BASE, SZ_8K - 1); ux500_pm_init(U8500_PRCMU_BASE, SZ_8K - 1); - u8500_clk_init(); + u8500_clk_init(U8500_CLKRST1_BASE, U8500_CLKRST2_BASE, + U8500_CLKRST3_BASE, U8500_CLKRST5_BASE, + U8500_CLKRST6_BASE); } else if (cpu_is_u9540()) { prcmu_early_init(U8500_PRCMU_BASE, SZ_8K - 1); ux500_pm_init(U8500_PRCMU_BASE, SZ_8K - 1); - u8500_clk_init(); + u8500_clk_init(U8500_CLKRST1_BASE, U8500_CLKRST2_BASE, + U8500_CLKRST3_BASE, U8500_CLKRST5_BASE, + U8500_CLKRST6_BASE); } else if (cpu_is_u8540()) { prcmu_early_init(U8500_PRCMU_BASE, SZ_8K + SZ_4K - 1); ux500_pm_init(U8500_PRCMU_BASE, SZ_8K + SZ_4K - 1); -- cgit v1.1 From ab0fc6ce4825311e1842bb3c46611d0f02d189df Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Thu, 21 Mar 2013 22:51:06 +0100 Subject: ARM: ux500: move mach/msp.h to This header file only contains platform data structure definitions, so it's straightforward to move. Signed-off-by: Arnd Bergmann [Delete one include rather than move it] Signed-off-by: Linus Walleij --- arch/arm/mach-ux500/board-mop500-audio.c | 2 +- arch/arm/mach-ux500/board-mop500.h | 2 +- arch/arm/mach-ux500/include/mach/msp.h | 27 --------------------------- 3 files changed, 2 insertions(+), 29 deletions(-) delete mode 100644 arch/arm/mach-ux500/include/mach/msp.h (limited to 'arch/arm') diff --git a/arch/arm/mach-ux500/board-mop500-audio.c b/arch/arm/mach-ux500/board-mop500-audio.c index 7209db7..43bbee1 100644 --- a/arch/arm/mach-ux500/board-mop500-audio.c +++ b/arch/arm/mach-ux500/board-mop500-audio.c @@ -13,7 +13,7 @@ #include #include #include -#include +#include #include "ste-dma40-db8500.h" #include "board-mop500.h" diff --git a/arch/arm/mach-ux500/board-mop500.h b/arch/arm/mach-ux500/board-mop500.h index eaa605f..eb81caf1 100644 --- a/arch/arm/mach-ux500/board-mop500.h +++ b/arch/arm/mach-ux500/board-mop500.h @@ -9,7 +9,7 @@ /* For NOMADIK_NR_GPIO */ #include -#include +#include #include /* Snowball specific GPIO assignments, this board has no GPIO expander */ diff --git a/arch/arm/mach-ux500/include/mach/msp.h b/arch/arm/mach-ux500/include/mach/msp.h deleted file mode 100644 index 9991aea..0000000 --- a/arch/arm/mach-ux500/include/mach/msp.h +++ /dev/null @@ -1,27 +0,0 @@ -/* - * Copyright (C) ST-Ericsson SA 2010 - * - * Author: Rabin Vincent for ST-Ericsson - * License terms: GNU General Public License (GPL), version 2. - */ - -#ifndef __MSP_H -#define __MSP_H - -#include - -enum msp_i2s_id { - MSP_I2S_0 = 0, - MSP_I2S_1, - MSP_I2S_2, - MSP_I2S_3, -}; - -/* Platform data structure for a MSP I2S-device */ -struct msp_i2s_platform_data { - enum msp_i2s_id id; - struct stedma40_chan_cfg *msp_i2s_dma_rx; - struct stedma40_chan_cfg *msp_i2s_dma_tx; -}; - -#endif -- cgit v1.1 From e5a1f68203e4dab8fdbb4c7d20977e6a5dbc7a49 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Thu, 21 Mar 2013 22:51:10 +0100 Subject: staging: ste_rmi4: kill platform_data hack There is only one instance of the platform data for synaptics_i2c_rmi4 in the mainline kernel, so there is no point of pretending its variable here. The only member that has a dependency on the platform is actually the interrupt number, and there is a field in the i2c_client structure that gets initialized from the board info, so we can trivially move the board_into into the platform without knowledge of the platform_data structure. Signed-off-by: Arnd Bergmann Acked-by: Greg Kroah-Hartman Signed-off-by: Linus Walleij --- arch/arm/mach-ux500/board-mop500-u8500uib.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-ux500/board-mop500-u8500uib.c b/arch/arm/mach-ux500/board-mop500-u8500uib.c index ead91c9..0b5e14a 100644 --- a/arch/arm/mach-ux500/board-mop500-u8500uib.c +++ b/arch/arm/mach-ux500/board-mop500-u8500uib.c @@ -16,8 +16,11 @@ #include "board-mop500.h" -/* Dummy data that can be overridden by staging driver */ -struct i2c_board_info __initdata __weak mop500_i2c3_devices_u8500[] = { +static struct i2c_board_info __initdata mop500_i2c3_devices_u8500[] = { + { + I2C_BOARD_INFO("synaptics_rmi4_i2c", 0x4B), + .irq = NOMADIK_GPIO_TO_IRQ(84), + }, }; /* -- cgit v1.1 From 174e7796624d2749359c3fdc673c1232b060d7f6 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Tue, 19 Mar 2013 15:41:55 +0100 Subject: ARM: ux500: get rid of This removes and from the Ux500, merging them into the local include "db8500-regs.h" in mach-ux500. There is some impact outside the ux500 machine, but most of it is dealt with in earlier patches. Contains portions of a clean-up patch from Arnd Bergmann. Cc: Samuel Ortiz Cc: Ulf Hansson Acked-by: Mike Turquette Signed-off-by: Arnd Bergmann Signed-off-by: Linus Walleij --- arch/arm/mach-ux500/board-mop500-audio.c | 1 - arch/arm/mach-ux500/board-mop500-pins.c | 2 - arch/arm/mach-ux500/board-mop500-sdi.c | 2 +- arch/arm/mach-ux500/board-mop500-uib.c | 1 - arch/arm/mach-ux500/board-mop500.c | 2 +- arch/arm/mach-ux500/cache-l2x0.c | 2 +- arch/arm/mach-ux500/cpu-db8500.c | 4 +- arch/arm/mach-ux500/cpu.c | 2 +- arch/arm/mach-ux500/cpuidle.c | 2 + arch/arm/mach-ux500/db8500-regs.h | 201 +++++++++++++++++++++++++ arch/arm/mach-ux500/devices-common.c | 1 - arch/arm/mach-ux500/devices-db8500.c | 2 +- arch/arm/mach-ux500/devices-db8500.h | 1 + arch/arm/mach-ux500/devices.c | 3 +- arch/arm/mach-ux500/id.c | 2 +- arch/arm/mach-ux500/include/mach/db8500-regs.h | 173 --------------------- arch/arm/mach-ux500/include/mach/hardware.h | 45 ------ arch/arm/mach-ux500/include/mach/irqs.h | 2 - arch/arm/mach-ux500/include/mach/uncompress.h | 3 +- arch/arm/mach-ux500/platsmp.c | 2 +- arch/arm/mach-ux500/pm.c | 2 +- arch/arm/mach-ux500/timer.c | 2 +- arch/arm/mach-ux500/usb.c | 2 +- 23 files changed, 219 insertions(+), 240 deletions(-) create mode 100644 arch/arm/mach-ux500/db8500-regs.h delete mode 100644 arch/arm/mach-ux500/include/mach/db8500-regs.h delete mode 100644 arch/arm/mach-ux500/include/mach/hardware.h (limited to 'arch/arm') diff --git a/arch/arm/mach-ux500/board-mop500-audio.c b/arch/arm/mach-ux500/board-mop500-audio.c index 43bbee1..96e62ef 100644 --- a/arch/arm/mach-ux500/board-mop500-audio.c +++ b/arch/arm/mach-ux500/board-mop500-audio.c @@ -11,7 +11,6 @@ #include #include -#include #include #include diff --git a/arch/arm/mach-ux500/board-mop500-pins.c b/arch/arm/mach-ux500/board-mop500-pins.c index 0a3f30d..f3976f9 100644 --- a/arch/arm/mach-ux500/board-mop500-pins.c +++ b/arch/arm/mach-ux500/board-mop500-pins.c @@ -13,8 +13,6 @@ #include -#include - #include "pins-db8500.h" #include "board-mop500.h" diff --git a/arch/arm/mach-ux500/board-mop500-sdi.c b/arch/arm/mach-ux500/board-mop500-sdi.c index 051b62c..0ada767 100644 --- a/arch/arm/mach-ux500/board-mop500-sdi.c +++ b/arch/arm/mach-ux500/board-mop500-sdi.c @@ -15,8 +15,8 @@ #include #include -#include +#include "db8500-regs.h" #include "devices-db8500.h" #include "board-mop500.h" #include "ste-dma40-db8500.h" diff --git a/arch/arm/mach-ux500/board-mop500-uib.c b/arch/arm/mach-ux500/board-mop500-uib.c index 7037d36..bdaa422 100644 --- a/arch/arm/mach-ux500/board-mop500-uib.c +++ b/arch/arm/mach-ux500/board-mop500-uib.c @@ -11,7 +11,6 @@ #include #include -#include #include "board-mop500.h" #include "id.h" diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c index fe3d72c..e1b38ef 100644 --- a/arch/arm/mach-ux500/board-mop500.c +++ b/arch/arm/mach-ux500/board-mop500.c @@ -41,13 +41,13 @@ #include #include -#include #include #include #include #include #include "ste-dma40-db8500.h" +#include "db8500-regs.h" #include "devices-db8500.h" #include "board-mop500.h" #include "board-mop500-regulators.h" diff --git a/arch/arm/mach-ux500/cache-l2x0.c b/arch/arm/mach-ux500/cache-l2x0.c index 1c1609d..e12cc92 100644 --- a/arch/arm/mach-ux500/cache-l2x0.c +++ b/arch/arm/mach-ux500/cache-l2x0.c @@ -9,8 +9,8 @@ #include #include -#include +#include "db8500-regs.h" #include "id.h" static void __iomem *l2x0_base; diff --git a/arch/arm/mach-ux500/cpu-db8500.c b/arch/arm/mach-ux500/cpu-db8500.c index 8c58dff..d726c06 100644 --- a/arch/arm/mach-ux500/cpu-db8500.c +++ b/arch/arm/mach-ux500/cpu-db8500.c @@ -28,15 +28,13 @@ #include #include -#include #include #include -#include #include #include "devices-db8500.h" #include "ste-dma40-db8500.h" - +#include "db8500-regs.h" #include "board-mop500.h" #include "id.h" diff --git a/arch/arm/mach-ux500/cpu.c b/arch/arm/mach-ux500/cpu.c index ee69439d..aa14c5f 100644 --- a/arch/arm/mach-ux500/cpu.c +++ b/arch/arm/mach-ux500/cpu.c @@ -24,11 +24,11 @@ #include -#include #include #include #include "board-mop500.h" +#include "db8500-regs.h" #include "id.h" /* diff --git a/arch/arm/mach-ux500/cpuidle.c b/arch/arm/mach-ux500/cpuidle.c index 1e5bb66..654115a 100644 --- a/arch/arm/mach-ux500/cpuidle.c +++ b/arch/arm/mach-ux500/cpuidle.c @@ -21,6 +21,8 @@ #include #include +#include "db8500-regs.h" + static atomic_t master = ATOMIC_INIT(0); static DEFINE_SPINLOCK(master_lock); static DEFINE_PER_CPU(struct cpuidle_device, ux500_cpuidle_device); diff --git a/arch/arm/mach-ux500/db8500-regs.h b/arch/arm/mach-ux500/db8500-regs.h new file mode 100644 index 0000000..b2d7a0b --- /dev/null +++ b/arch/arm/mach-ux500/db8500-regs.h @@ -0,0 +1,201 @@ +/* + * Copyright (C) ST-Ericsson SA 2010 + * + * License terms: GNU General Public License (GPL) version 2 + */ + +#ifndef __MACH_DB8500_REGS_H +#define __MACH_DB8500_REGS_H + +/* Base address and bank offsets for ESRAM */ +#define U8500_ESRAM_BASE 0x40000000 +#define U8500_ESRAM_BANK_SIZE 0x00020000 +#define U8500_ESRAM_BANK0 U8500_ESRAM_BASE +#define U8500_ESRAM_BANK1 (U8500_ESRAM_BASE + U8500_ESRAM_BANK_SIZE) +#define U8500_ESRAM_BANK2 (U8500_ESRAM_BANK1 + U8500_ESRAM_BANK_SIZE) +#define U8500_ESRAM_BANK3 (U8500_ESRAM_BANK2 + U8500_ESRAM_BANK_SIZE) +#define U8500_ESRAM_BANK4 (U8500_ESRAM_BANK3 + U8500_ESRAM_BANK_SIZE) +/* + * on V1 DMA uses 4KB for logical parameters position is right after the 64KB + * reserved for security + */ +#define U8500_ESRAM_DMA_LCPA_OFFSET 0x10000 + +#define U8500_DMA_LCPA_BASE (U8500_ESRAM_BANK0 + U8500_ESRAM_DMA_LCPA_OFFSET) + +/* This address fulfills the 256k alignment requirement of the lcla base */ +#define U8500_DMA_LCLA_BASE U8500_ESRAM_BANK4 + +#define U8500_PER3_BASE 0x80000000 +#define U8500_STM_BASE 0x80100000 +#define U8500_STM_REG_BASE (U8500_STM_BASE + 0xF000) +#define U8500_PER2_BASE 0x80110000 +#define U8500_PER1_BASE 0x80120000 +#define U8500_B2R2_BASE 0x80130000 +#define U8500_HSEM_BASE 0x80140000 +#define U8500_PER4_BASE 0x80150000 +#define U8500_TPIU_BASE 0x80190000 +#define U8500_ICN_BASE 0x81000000 + +#define U8500_BOOT_ROM_BASE 0x90000000 +/* ASIC ID is at 0xbf4 offset within this region */ +#define U8500_ASIC_ID_BASE 0x9001D000 + +#define U9540_BOOT_ROM_BASE 0xFFFE0000 +/* ASIC ID is at 0xbf4 offset within this region */ +#define U9540_ASIC_ID_BASE 0xFFFFD000 + +#define U8500_PER6_BASE 0xa03c0000 +#define U8500_PER7_BASE 0xa03d0000 +#define U8500_PER5_BASE 0xa03e0000 + +#define U8500_SVA_BASE 0xa0100000 +#define U8500_SIA_BASE 0xa0200000 + +#define U8500_SGA_BASE 0xa0300000 +#define U8500_MCDE_BASE 0xa0350000 +#define U8500_DMA_BASE 0x801C0000 /* v1 */ + +#define U8500_SBAG_BASE 0xa0390000 + +#define U8500_SCU_BASE 0xa0410000 +#define U8500_GIC_CPU_BASE 0xa0410100 +#define U8500_TWD_BASE 0xa0410600 +#define U8500_GIC_DIST_BASE 0xa0411000 +#define U8500_L2CC_BASE 0xa0412000 + +#define U8500_MODEM_I2C 0xb7e02000 + +#define U8500_GPIO0_BASE (U8500_PER1_BASE + 0xE000) +#define U8500_GPIO1_BASE (U8500_PER3_BASE + 0xE000) +#define U8500_GPIO2_BASE (U8500_PER2_BASE + 0xE000) +#define U8500_GPIO3_BASE (U8500_PER5_BASE + 0x1E000) + +#define U8500_UART0_BASE (U8500_PER1_BASE + 0x0000) +#define U8500_UART1_BASE (U8500_PER1_BASE + 0x1000) + +/* per6 base addresses */ +#define U8500_RNG_BASE (U8500_PER6_BASE + 0x0000) +#define U8500_HASH0_BASE (U8500_PER6_BASE + 0x1000) +#define U8500_HASH1_BASE (U8500_PER6_BASE + 0x2000) +#define U8500_PKA_BASE (U8500_PER6_BASE + 0x4000) +#define U8500_PKAM_BASE (U8500_PER6_BASE + 0x5100) +#define U8500_MTU0_BASE (U8500_PER6_BASE + 0x6000) /* v1 */ +#define U8500_MTU1_BASE (U8500_PER6_BASE + 0x7000) /* v1 */ +#define U8500_CR_BASE (U8500_PER6_BASE + 0x8000) /* v1 */ +#define U8500_CRYP0_BASE (U8500_PER6_BASE + 0xa000) +#define U8500_CRYP1_BASE (U8500_PER6_BASE + 0xb000) +#define U8500_CLKRST6_BASE (U8500_PER6_BASE + 0xf000) + +/* per5 base addresses */ +#define U8500_USBOTG_BASE (U8500_PER5_BASE + 0x00000) +#define U8500_CLKRST5_BASE (U8500_PER5_BASE + 0x1f000) + +/* per4 base addresses */ +#define U8500_BACKUPRAM0_BASE (U8500_PER4_BASE + 0x00000) +#define U8500_BACKUPRAM1_BASE (U8500_PER4_BASE + 0x01000) +#define U8500_RTT0_BASE (U8500_PER4_BASE + 0x02000) +#define U8500_RTT1_BASE (U8500_PER4_BASE + 0x03000) +#define U8500_RTC_BASE (U8500_PER4_BASE + 0x04000) +#define U8500_SCR_BASE (U8500_PER4_BASE + 0x05000) +#define U8500_DMC_BASE (U8500_PER4_BASE + 0x06000) +#define U8500_PRCMU_BASE (U8500_PER4_BASE + 0x07000) +#define U9540_DMC1_BASE (U8500_PER4_BASE + 0x0A000) +#define U8500_PRCMU_TCDM_BASE (U8500_PER4_BASE + 0x68000) +#define U9540_PRCMU_TCDM_BASE (U8500_PER4_BASE + 0x6A000) +#define U8500_PRCMU_TCPM_BASE (U8500_PER4_BASE + 0x60000) +#define U8500_PRCMU_TIMER_3_BASE (U8500_PER4_BASE + 0x07338) +#define U8500_PRCMU_TIMER_4_BASE (U8500_PER4_BASE + 0x07450) + +/* per3 base addresses */ +#define U8500_FSMC_BASE (U8500_PER3_BASE + 0x0000) +#define U8500_SSP0_BASE (U8500_PER3_BASE + 0x2000) +#define U8500_SSP1_BASE (U8500_PER3_BASE + 0x3000) +#define U8500_I2C0_BASE (U8500_PER3_BASE + 0x4000) +#define U8500_SDI2_BASE (U8500_PER3_BASE + 0x5000) +#define U8500_SKE_BASE (U8500_PER3_BASE + 0x6000) +#define U8500_UART2_BASE (U8500_PER3_BASE + 0x7000) +#define U8500_SDI5_BASE (U8500_PER3_BASE + 0x8000) +#define U8500_CLKRST3_BASE (U8500_PER3_BASE + 0xf000) + +/* per2 base addresses */ +#define U8500_I2C3_BASE (U8500_PER2_BASE + 0x0000) +#define U8500_SPI2_BASE (U8500_PER2_BASE + 0x1000) +#define U8500_SPI1_BASE (U8500_PER2_BASE + 0x2000) +#define U8500_PWL_BASE (U8500_PER2_BASE + 0x3000) +#define U8500_SDI4_BASE (U8500_PER2_BASE + 0x4000) +#define U8500_MSP2_BASE (U8500_PER2_BASE + 0x7000) +#define U8500_SDI1_BASE (U8500_PER2_BASE + 0x8000) +#define U8500_SDI3_BASE (U8500_PER2_BASE + 0x9000) +#define U8500_SPI0_BASE (U8500_PER2_BASE + 0xa000) +#define U8500_HSIR_BASE (U8500_PER2_BASE + 0xb000) +#define U8500_HSIT_BASE (U8500_PER2_BASE + 0xc000) +#define U8500_CLKRST2_BASE (U8500_PER2_BASE + 0xf000) + +/* per1 base addresses */ +#define U8500_I2C1_BASE (U8500_PER1_BASE + 0x2000) +#define U8500_MSP0_BASE (U8500_PER1_BASE + 0x3000) +#define U8500_MSP1_BASE (U8500_PER1_BASE + 0x4000) +#define U8500_MSP3_BASE (U8500_PER1_BASE + 0x5000) +#define U8500_SDI0_BASE (U8500_PER1_BASE + 0x6000) +#define U8500_I2C2_BASE (U8500_PER1_BASE + 0x8000) +#define U8500_SPI3_BASE (U8500_PER1_BASE + 0x9000) +#define U8500_I2C4_BASE (U8500_PER1_BASE + 0xa000) +#define U8500_SLIM0_BASE (U8500_PER1_BASE + 0xb000) +#define U8500_CLKRST1_BASE (U8500_PER1_BASE + 0xf000) + +#define U8500_SHRM_GOP_INTERRUPT_BASE 0xB7C00040 + +#define U8500_GPIOBANK0_BASE U8500_GPIO0_BASE +#define U8500_GPIOBANK1_BASE (U8500_GPIO0_BASE + 0x80) +#define U8500_GPIOBANK2_BASE U8500_GPIO1_BASE +#define U8500_GPIOBANK3_BASE (U8500_GPIO1_BASE + 0x80) +#define U8500_GPIOBANK4_BASE (U8500_GPIO1_BASE + 0x100) +#define U8500_GPIOBANK5_BASE (U8500_GPIO1_BASE + 0x180) +#define U8500_GPIOBANK6_BASE U8500_GPIO2_BASE +#define U8500_GPIOBANK7_BASE (U8500_GPIO2_BASE + 0x80) +#define U8500_GPIOBANK8_BASE U8500_GPIO3_BASE + +#define U8500_MCDE_SIZE 0x1000 +#define U8500_DSI_LINK_SIZE 0x1000 +#define U8500_DSI_LINK1_BASE (U8500_MCDE_BASE + U8500_MCDE_SIZE) +#define U8500_DSI_LINK2_BASE (U8500_DSI_LINK1_BASE + U8500_DSI_LINK_SIZE) +#define U8500_DSI_LINK3_BASE (U8500_DSI_LINK2_BASE + U8500_DSI_LINK_SIZE) +#define U8500_DSI_LINK_COUNT 0x3 + +/* Modem and APE physical addresses */ +#define U8500_MODEM_BASE 0xe000000 +#define U8500_APE_BASE 0x6000000 + +/* SoC identification number information */ +#define U8500_BB_UID_BASE (U8500_BACKUPRAM1_BASE + 0xFC0) + +/* Offsets to specific addresses in some IP blocks for DMA */ +#define MSP_TX_RX_REG_OFFSET 0 +#define CRYP1_RX_REG_OFFSET 0x10 +#define CRYP1_TX_REG_OFFSET 0x8 +#define HASH1_TX_REG_OFFSET 0x4 + +/* + * Macros to get at IO space when running virtually + * We dont map all the peripherals, let ioremap do + * this for us. We map only very basic peripherals here. + */ +#define U8500_IO_VIRTUAL 0xf0000000 +#define U8500_IO_PHYSICAL 0xa0000000 +/* This is where we map in the ROM to check ASIC IDs */ +#define UX500_VIRT_ROM 0xf0000000 + +/* This macro is used in assembly, so no cast */ +#define IO_ADDRESS(x) \ + (((x) & 0x0fffffff) + (((x) >> 4) & 0x0f000000) + U8500_IO_VIRTUAL) + +/* typesafe io address */ +#define __io_address(n) IOMEM(IO_ADDRESS(n)) + +/* Used by some plat-nomadik code */ +#define io_p2v(n) __io_address(n) + +#define ARRAY_AND_SIZE(x) (x), ARRAY_SIZE(x) + +#endif diff --git a/arch/arm/mach-ux500/devices-common.c b/arch/arm/mach-ux500/devices-common.c index 16b5f71..94868b7 100644 --- a/arch/arm/mach-ux500/devices-common.c +++ b/arch/arm/mach-ux500/devices-common.c @@ -13,7 +13,6 @@ #include #include -#include #include #include "devices-common.h" diff --git a/arch/arm/mach-ux500/devices-db8500.c b/arch/arm/mach-ux500/devices-db8500.c index df4d7de..4c0ef14 100644 --- a/arch/arm/mach-ux500/devices-db8500.c +++ b/arch/arm/mach-ux500/devices-db8500.c @@ -15,10 +15,10 @@ #include #include -#include #include #include +#include "db8500-regs.h" #include "devices-db8500.h" #include "ste-dma40-db8500.h" diff --git a/arch/arm/mach-ux500/devices-db8500.h b/arch/arm/mach-ux500/devices-db8500.h index dbcb35c..c9db210 100644 --- a/arch/arm/mach-ux500/devices-db8500.h +++ b/arch/arm/mach-ux500/devices-db8500.h @@ -10,6 +10,7 @@ #include #include +#include "db8500-regs.h" #include "devices-common.h" struct ske_keypad_platform_data; diff --git a/arch/arm/mach-ux500/devices.c b/arch/arm/mach-ux500/devices.c index ea0a2f9..f63a512 100644 --- a/arch/arm/mach-ux500/devices.c +++ b/arch/arm/mach-ux500/devices.c @@ -11,9 +11,10 @@ #include #include -#include #include +#include "db8500-regs.h" + void __init amba_add_devices(struct amba_device *devs[], int num) { int i; diff --git a/arch/arm/mach-ux500/id.c b/arch/arm/mach-ux500/id.c index 9f95184..a847cf2 100644 --- a/arch/arm/mach-ux500/id.c +++ b/arch/arm/mach-ux500/id.c @@ -14,9 +14,9 @@ #include #include -#include #include +#include "db8500-regs.h" #include "id.h" struct dbx500_asic_id dbx500_id; diff --git a/arch/arm/mach-ux500/include/mach/db8500-regs.h b/arch/arm/mach-ux500/include/mach/db8500-regs.h deleted file mode 100644 index 1530d49..0000000 --- a/arch/arm/mach-ux500/include/mach/db8500-regs.h +++ /dev/null @@ -1,173 +0,0 @@ -/* - * Copyright (C) ST-Ericsson SA 2010 - * - * License terms: GNU General Public License (GPL) version 2 - */ - -#ifndef __MACH_DB8500_REGS_H -#define __MACH_DB8500_REGS_H - -/* Base address and bank offsets for ESRAM */ -#define U8500_ESRAM_BASE 0x40000000 -#define U8500_ESRAM_BANK_SIZE 0x00020000 -#define U8500_ESRAM_BANK0 U8500_ESRAM_BASE -#define U8500_ESRAM_BANK1 (U8500_ESRAM_BASE + U8500_ESRAM_BANK_SIZE) -#define U8500_ESRAM_BANK2 (U8500_ESRAM_BANK1 + U8500_ESRAM_BANK_SIZE) -#define U8500_ESRAM_BANK3 (U8500_ESRAM_BANK2 + U8500_ESRAM_BANK_SIZE) -#define U8500_ESRAM_BANK4 (U8500_ESRAM_BANK3 + U8500_ESRAM_BANK_SIZE) -/* - * on V1 DMA uses 4KB for logical parameters position is right after the 64KB - * reserved for security - */ -#define U8500_ESRAM_DMA_LCPA_OFFSET 0x10000 - -#define U8500_DMA_LCPA_BASE (U8500_ESRAM_BANK0 + U8500_ESRAM_DMA_LCPA_OFFSET) - -/* This address fulfills the 256k alignment requirement of the lcla base */ -#define U8500_DMA_LCLA_BASE U8500_ESRAM_BANK4 - -#define U8500_PER3_BASE 0x80000000 -#define U8500_STM_BASE 0x80100000 -#define U8500_STM_REG_BASE (U8500_STM_BASE + 0xF000) -#define U8500_PER2_BASE 0x80110000 -#define U8500_PER1_BASE 0x80120000 -#define U8500_B2R2_BASE 0x80130000 -#define U8500_HSEM_BASE 0x80140000 -#define U8500_PER4_BASE 0x80150000 -#define U8500_TPIU_BASE 0x80190000 -#define U8500_ICN_BASE 0x81000000 - -#define U8500_BOOT_ROM_BASE 0x90000000 -/* ASIC ID is at 0xbf4 offset within this region */ -#define U8500_ASIC_ID_BASE 0x9001D000 - -#define U9540_BOOT_ROM_BASE 0xFFFE0000 -/* ASIC ID is at 0xbf4 offset within this region */ -#define U9540_ASIC_ID_BASE 0xFFFFD000 - -#define U8500_PER6_BASE 0xa03c0000 -#define U8500_PER7_BASE 0xa03d0000 -#define U8500_PER5_BASE 0xa03e0000 - -#define U8500_SVA_BASE 0xa0100000 -#define U8500_SIA_BASE 0xa0200000 - -#define U8500_SGA_BASE 0xa0300000 -#define U8500_MCDE_BASE 0xa0350000 -#define U8500_DMA_BASE 0x801C0000 /* v1 */ - -#define U8500_SBAG_BASE 0xa0390000 - -#define U8500_SCU_BASE 0xa0410000 -#define U8500_GIC_CPU_BASE 0xa0410100 -#define U8500_TWD_BASE 0xa0410600 -#define U8500_GIC_DIST_BASE 0xa0411000 -#define U8500_L2CC_BASE 0xa0412000 - -#define U8500_MODEM_I2C 0xb7e02000 - -#define U8500_GPIO0_BASE (U8500_PER1_BASE + 0xE000) -#define U8500_GPIO1_BASE (U8500_PER3_BASE + 0xE000) -#define U8500_GPIO2_BASE (U8500_PER2_BASE + 0xE000) -#define U8500_GPIO3_BASE (U8500_PER5_BASE + 0x1E000) - -#define U8500_UART0_BASE (U8500_PER1_BASE + 0x0000) -#define U8500_UART1_BASE (U8500_PER1_BASE + 0x1000) - -/* per6 base addresses */ -#define U8500_RNG_BASE (U8500_PER6_BASE + 0x0000) -#define U8500_HASH0_BASE (U8500_PER6_BASE + 0x1000) -#define U8500_HASH1_BASE (U8500_PER6_BASE + 0x2000) -#define U8500_PKA_BASE (U8500_PER6_BASE + 0x4000) -#define U8500_PKAM_BASE (U8500_PER6_BASE + 0x5100) -#define U8500_MTU0_BASE (U8500_PER6_BASE + 0x6000) /* v1 */ -#define U8500_MTU1_BASE (U8500_PER6_BASE + 0x7000) /* v1 */ -#define U8500_CR_BASE (U8500_PER6_BASE + 0x8000) /* v1 */ -#define U8500_CRYP0_BASE (U8500_PER6_BASE + 0xa000) -#define U8500_CRYP1_BASE (U8500_PER6_BASE + 0xb000) -#define U8500_CLKRST6_BASE (U8500_PER6_BASE + 0xf000) - -/* per5 base addresses */ -#define U8500_USBOTG_BASE (U8500_PER5_BASE + 0x00000) -#define U8500_CLKRST5_BASE (U8500_PER5_BASE + 0x1f000) - -/* per4 base addresses */ -#define U8500_BACKUPRAM0_BASE (U8500_PER4_BASE + 0x00000) -#define U8500_BACKUPRAM1_BASE (U8500_PER4_BASE + 0x01000) -#define U8500_RTT0_BASE (U8500_PER4_BASE + 0x02000) -#define U8500_RTT1_BASE (U8500_PER4_BASE + 0x03000) -#define U8500_RTC_BASE (U8500_PER4_BASE + 0x04000) -#define U8500_SCR_BASE (U8500_PER4_BASE + 0x05000) -#define U8500_DMC_BASE (U8500_PER4_BASE + 0x06000) -#define U8500_PRCMU_BASE (U8500_PER4_BASE + 0x07000) -#define U9540_DMC1_BASE (U8500_PER4_BASE + 0x0A000) -#define U8500_PRCMU_TCDM_BASE (U8500_PER4_BASE + 0x68000) -#define U9540_PRCMU_TCDM_BASE (U8500_PER4_BASE + 0x6A000) -#define U8500_PRCMU_TCPM_BASE (U8500_PER4_BASE + 0x60000) -#define U8500_PRCMU_TIMER_3_BASE (U8500_PER4_BASE + 0x07338) -#define U8500_PRCMU_TIMER_4_BASE (U8500_PER4_BASE + 0x07450) - -/* per3 base addresses */ -#define U8500_FSMC_BASE (U8500_PER3_BASE + 0x0000) -#define U8500_SSP0_BASE (U8500_PER3_BASE + 0x2000) -#define U8500_SSP1_BASE (U8500_PER3_BASE + 0x3000) -#define U8500_I2C0_BASE (U8500_PER3_BASE + 0x4000) -#define U8500_SDI2_BASE (U8500_PER3_BASE + 0x5000) -#define U8500_SKE_BASE (U8500_PER3_BASE + 0x6000) -#define U8500_UART2_BASE (U8500_PER3_BASE + 0x7000) -#define U8500_SDI5_BASE (U8500_PER3_BASE + 0x8000) -#define U8500_CLKRST3_BASE (U8500_PER3_BASE + 0xf000) - -/* per2 base addresses */ -#define U8500_I2C3_BASE (U8500_PER2_BASE + 0x0000) -#define U8500_SPI2_BASE (U8500_PER2_BASE + 0x1000) -#define U8500_SPI1_BASE (U8500_PER2_BASE + 0x2000) -#define U8500_PWL_BASE (U8500_PER2_BASE + 0x3000) -#define U8500_SDI4_BASE (U8500_PER2_BASE + 0x4000) -#define U8500_MSP2_BASE (U8500_PER2_BASE + 0x7000) -#define U8500_SDI1_BASE (U8500_PER2_BASE + 0x8000) -#define U8500_SDI3_BASE (U8500_PER2_BASE + 0x9000) -#define U8500_SPI0_BASE (U8500_PER2_BASE + 0xa000) -#define U8500_HSIR_BASE (U8500_PER2_BASE + 0xb000) -#define U8500_HSIT_BASE (U8500_PER2_BASE + 0xc000) -#define U8500_CLKRST2_BASE (U8500_PER2_BASE + 0xf000) - -/* per1 base addresses */ -#define U8500_I2C1_BASE (U8500_PER1_BASE + 0x2000) -#define U8500_MSP0_BASE (U8500_PER1_BASE + 0x3000) -#define U8500_MSP1_BASE (U8500_PER1_BASE + 0x4000) -#define U8500_MSP3_BASE (U8500_PER1_BASE + 0x5000) -#define U8500_SDI0_BASE (U8500_PER1_BASE + 0x6000) -#define U8500_I2C2_BASE (U8500_PER1_BASE + 0x8000) -#define U8500_SPI3_BASE (U8500_PER1_BASE + 0x9000) -#define U8500_I2C4_BASE (U8500_PER1_BASE + 0xa000) -#define U8500_SLIM0_BASE (U8500_PER1_BASE + 0xb000) -#define U8500_CLKRST1_BASE (U8500_PER1_BASE + 0xf000) - -#define U8500_SHRM_GOP_INTERRUPT_BASE 0xB7C00040 - -#define U8500_GPIOBANK0_BASE U8500_GPIO0_BASE -#define U8500_GPIOBANK1_BASE (U8500_GPIO0_BASE + 0x80) -#define U8500_GPIOBANK2_BASE U8500_GPIO1_BASE -#define U8500_GPIOBANK3_BASE (U8500_GPIO1_BASE + 0x80) -#define U8500_GPIOBANK4_BASE (U8500_GPIO1_BASE + 0x100) -#define U8500_GPIOBANK5_BASE (U8500_GPIO1_BASE + 0x180) -#define U8500_GPIOBANK6_BASE U8500_GPIO2_BASE -#define U8500_GPIOBANK7_BASE (U8500_GPIO2_BASE + 0x80) -#define U8500_GPIOBANK8_BASE U8500_GPIO3_BASE - -#define U8500_MCDE_SIZE 0x1000 -#define U8500_DSI_LINK_SIZE 0x1000 -#define U8500_DSI_LINK1_BASE (U8500_MCDE_BASE + U8500_MCDE_SIZE) -#define U8500_DSI_LINK2_BASE (U8500_DSI_LINK1_BASE + U8500_DSI_LINK_SIZE) -#define U8500_DSI_LINK3_BASE (U8500_DSI_LINK2_BASE + U8500_DSI_LINK_SIZE) -#define U8500_DSI_LINK_COUNT 0x3 - -/* Modem and APE physical addresses */ -#define U8500_MODEM_BASE 0xe000000 -#define U8500_APE_BASE 0x6000000 - -/* SoC identification number information */ -#define U8500_BB_UID_BASE (U8500_BACKUPRAM1_BASE + 0xFC0) - -#endif diff --git a/arch/arm/mach-ux500/include/mach/hardware.h b/arch/arm/mach-ux500/include/mach/hardware.h deleted file mode 100644 index 4eece2af..0000000 --- a/arch/arm/mach-ux500/include/mach/hardware.h +++ /dev/null @@ -1,45 +0,0 @@ -/* - * Copyright (C) 2009 ST-Ericsson. - * - * U8500 hardware definitions - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ -#ifndef __MACH_HARDWARE_H -#define __MACH_HARDWARE_H - -/* - * Macros to get at IO space when running virtually - * We dont map all the peripherals, let ioremap do - * this for us. We map only very basic peripherals here. - */ -#define U8500_IO_VIRTUAL 0xf0000000 -#define U8500_IO_PHYSICAL 0xa0000000 -/* This is where we map in the ROM to check ASIC IDs */ -#define UX500_VIRT_ROM 0xf0000000 - -/* This macro is used in assembly, so no cast */ -#define IO_ADDRESS(x) \ - (((x) & 0x0fffffff) + (((x) >> 4) & 0x0f000000) + U8500_IO_VIRTUAL) - -/* typesafe io address */ -#define __io_address(n) IOMEM(IO_ADDRESS(n)) - -/* Used by some plat-nomadik code */ -#define io_p2v(n) __io_address(n) - -#include - -#define MSP_TX_RX_REG_OFFSET 0 -#define CRYP1_RX_REG_OFFSET 0x10 -#define CRYP1_TX_REG_OFFSET 0x8 -#define HASH1_TX_REG_OFFSET 0x4 - -#ifndef __ASSEMBLY__ - -#define ARRAY_AND_SIZE(x) (x), ARRAY_SIZE(x) - -#endif /* __ASSEMBLY__ */ -#endif /* __MACH_HARDWARE_H */ diff --git a/arch/arm/mach-ux500/include/mach/irqs.h b/arch/arm/mach-ux500/include/mach/irqs.h index fc77b42..829947d 100644 --- a/arch/arm/mach-ux500/include/mach/irqs.h +++ b/arch/arm/mach-ux500/include/mach/irqs.h @@ -10,8 +10,6 @@ #ifndef ASM_ARCH_IRQS_H #define ASM_ARCH_IRQS_H -#include - #define IRQ_LOCALTIMER 29 #define IRQ_LOCALWDOG 30 diff --git a/arch/arm/mach-ux500/include/mach/uncompress.h b/arch/arm/mach-ux500/include/mach/uncompress.h index 36969d5..533a004 100644 --- a/arch/arm/mach-ux500/include/mach/uncompress.h +++ b/arch/arm/mach-ux500/include/mach/uncompress.h @@ -22,7 +22,8 @@ #include #include #include -#include +/* TODO: This goes away in multiplatform boot, this file gets deleted */ +#include "../../db8500-regs.h" void __iomem *ux500_uart_base; diff --git a/arch/arm/mach-ux500/platsmp.c b/arch/arm/mach-ux500/platsmp.c index 18f7af3..8a9c070 100644 --- a/arch/arm/mach-ux500/platsmp.c +++ b/arch/arm/mach-ux500/platsmp.c @@ -22,9 +22,9 @@ #include #include -#include #include +#include "db8500-regs.h" #include "id.h" /* This is called from headsmp.S to wakeup the secondary core */ diff --git a/arch/arm/mach-ux500/pm.c b/arch/arm/mach-ux500/pm.c index 6949a13..1a468f0 100644 --- a/arch/arm/mach-ux500/pm.c +++ b/arch/arm/mach-ux500/pm.c @@ -13,7 +13,7 @@ #include #include -#include +#include "db8500-regs.h" /* ARM WFI Standby signal register */ #define PRCM_ARM_WFI_STANDBY (prcmu_base + 0x130) diff --git a/arch/arm/mach-ux500/timer.c b/arch/arm/mach-ux500/timer.c index a6af0b8..5b91fac 100644 --- a/arch/arm/mach-ux500/timer.c +++ b/arch/arm/mach-ux500/timer.c @@ -14,9 +14,9 @@ #include #include -#include #include +#include "db8500-regs.h" #include "id.h" #ifdef CONFIG_HAVE_ARM_TWD diff --git a/arch/arm/mach-ux500/usb.c b/arch/arm/mach-ux500/usb.c index 78ac65f..2dfc72f 100644 --- a/arch/arm/mach-ux500/usb.c +++ b/arch/arm/mach-ux500/usb.c @@ -10,7 +10,7 @@ #include #include -#include +#include "db8500-regs.h" #define MUSB_DMA40_RX_CH { \ .mode = STEDMA40_MODE_LOGICAL, \ -- cgit v1.1 From eba52748bee971207ddc44b926c12282d0741e2e Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Thu, 21 Mar 2013 22:51:08 +0100 Subject: ARM: ux500: make irqs.h local to platform With the PRCMU out of the way, nothing outside of mach-ux500 uses mach/irqs.h any more, so we can make it a local header file, including the two sub-headers. Signed-off-by: Arnd Bergmann Signed-off-by: Linus Walleij --- arch/arm/mach-ux500/board-mop500-audio.c | 2 +- arch/arm/mach-ux500/board-mop500-u8500uib.c | 2 +- arch/arm/mach-ux500/board-mop500.c | 2 +- arch/arm/mach-ux500/board-mop500.h | 2 +- arch/arm/mach-ux500/cpu-db8500.c | 2 +- arch/arm/mach-ux500/devices-common.c | 2 +- arch/arm/mach-ux500/devices-db8500.c | 2 +- arch/arm/mach-ux500/devices-db8500.h | 2 +- .../mach-ux500/include/mach/irqs-board-mop500.h | 55 --------- arch/arm/mach-ux500/include/mach/irqs-db8500.h | 125 --------------------- arch/arm/mach-ux500/include/mach/irqs.h | 49 -------- arch/arm/mach-ux500/irqs-board-mop500.h | 55 +++++++++ arch/arm/mach-ux500/irqs-db8500.h | 125 +++++++++++++++++++++ arch/arm/mach-ux500/irqs.h | 49 ++++++++ arch/arm/mach-ux500/timer.c | 2 +- 15 files changed, 238 insertions(+), 238 deletions(-) delete mode 100644 arch/arm/mach-ux500/include/mach/irqs-board-mop500.h delete mode 100644 arch/arm/mach-ux500/include/mach/irqs-db8500.h delete mode 100644 arch/arm/mach-ux500/include/mach/irqs.h create mode 100644 arch/arm/mach-ux500/irqs-board-mop500.h create mode 100644 arch/arm/mach-ux500/irqs-db8500.h create mode 100644 arch/arm/mach-ux500/irqs.h (limited to 'arch/arm') diff --git a/arch/arm/mach-ux500/board-mop500-audio.c b/arch/arm/mach-ux500/board-mop500-audio.c index 96e62ef..def0637 100644 --- a/arch/arm/mach-ux500/board-mop500-audio.c +++ b/arch/arm/mach-ux500/board-mop500-audio.c @@ -11,7 +11,7 @@ #include #include -#include +#include "irqs.h" #include #include "ste-dma40-db8500.h" diff --git a/arch/arm/mach-ux500/board-mop500-u8500uib.c b/arch/arm/mach-ux500/board-mop500-u8500uib.c index 0b5e14a..d397c19 100644 --- a/arch/arm/mach-ux500/board-mop500-u8500uib.c +++ b/arch/arm/mach-ux500/board-mop500-u8500uib.c @@ -12,7 +12,7 @@ #include #include -#include +#include "irqs.h" #include "board-mop500.h" diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c index e1b38ef..6e8ee11 100644 --- a/arch/arm/mach-ux500/board-mop500.c +++ b/arch/arm/mach-ux500/board-mop500.c @@ -43,7 +43,7 @@ #include #include -#include +#include "irqs.h" #include #include "ste-dma40-db8500.h" diff --git a/arch/arm/mach-ux500/board-mop500.h b/arch/arm/mach-ux500/board-mop500.h index eb81caf1..16bf1ac 100644 --- a/arch/arm/mach-ux500/board-mop500.h +++ b/arch/arm/mach-ux500/board-mop500.h @@ -8,7 +8,7 @@ #define __BOARD_MOP500_H /* For NOMADIK_NR_GPIO */ -#include +#include "irqs.h" #include #include diff --git a/arch/arm/mach-ux500/cpu-db8500.c b/arch/arm/mach-ux500/cpu-db8500.c index d726c06..e11f87d 100644 --- a/arch/arm/mach-ux500/cpu-db8500.c +++ b/arch/arm/mach-ux500/cpu-db8500.c @@ -30,7 +30,7 @@ #include #include -#include +#include "irqs.h" #include "devices-db8500.h" #include "ste-dma40-db8500.h" diff --git a/arch/arm/mach-ux500/devices-common.c b/arch/arm/mach-ux500/devices-common.c index 94868b7..f71b3d7 100644 --- a/arch/arm/mach-ux500/devices-common.c +++ b/arch/arm/mach-ux500/devices-common.c @@ -13,7 +13,7 @@ #include #include -#include +#include "irqs.h" #include "devices-common.h" diff --git a/arch/arm/mach-ux500/devices-db8500.c b/arch/arm/mach-ux500/devices-db8500.c index 4c0ef14..45ec955 100644 --- a/arch/arm/mach-ux500/devices-db8500.c +++ b/arch/arm/mach-ux500/devices-db8500.c @@ -16,7 +16,7 @@ #include #include -#include +#include "irqs.h" #include "db8500-regs.h" #include "devices-db8500.h" diff --git a/arch/arm/mach-ux500/devices-db8500.h b/arch/arm/mach-ux500/devices-db8500.h index c9db210..3219983 100644 --- a/arch/arm/mach-ux500/devices-db8500.h +++ b/arch/arm/mach-ux500/devices-db8500.h @@ -9,7 +9,7 @@ #define __DEVICES_DB8500_H #include -#include +#include "irqs.h" #include "db8500-regs.h" #include "devices-common.h" diff --git a/arch/arm/mach-ux500/include/mach/irqs-board-mop500.h b/arch/arm/mach-ux500/include/mach/irqs-board-mop500.h deleted file mode 100644 index d526dd8..0000000 --- a/arch/arm/mach-ux500/include/mach/irqs-board-mop500.h +++ /dev/null @@ -1,55 +0,0 @@ -/* - * Copyright (C) ST-Ericsson SA 2010 - * - * Author: Rabin Vincent - * License terms: GNU General Public License (GPL) version 2 - */ - -#ifndef __MACH_IRQS_BOARD_MOP500_H -#define __MACH_IRQS_BOARD_MOP500_H - -/* Number of AB8500 irqs is taken from header file */ -#include - -#define MOP500_AB8500_IRQ_BASE IRQ_BOARD_START -#define MOP500_AB8500_IRQ_END (MOP500_AB8500_IRQ_BASE \ - + AB8500_MAX_NR_IRQS) - -/* TC35892 */ -#define TC35892_NR_INTERNAL_IRQS 8 -#define TC35892_INT_GPIO(x) (TC35892_NR_INTERNAL_IRQS + (x)) -#define TC35892_NR_GPIOS 24 -#define TC35892_NR_IRQS TC35892_INT_GPIO(TC35892_NR_GPIOS) - -#define MOP500_EGPIO_NR_IRQS TC35892_NR_IRQS - -#define MOP500_EGPIO_IRQ_BASE MOP500_AB8500_IRQ_END -#define MOP500_EGPIO_IRQ_END (MOP500_EGPIO_IRQ_BASE \ - + MOP500_EGPIO_NR_IRQS) -/* STMPE1601 irqs */ -#define STMPE_NR_INTERNAL_IRQS 9 -#define STMPE_INT_GPIO(x) (STMPE_NR_INTERNAL_IRQS + (x)) -#define STMPE_NR_GPIOS 24 -#define STMPE_NR_IRQS STMPE_INT_GPIO(STMPE_NR_GPIOS) - -#define MOP500_STMPE1601_IRQBASE MOP500_EGPIO_IRQ_END -#define MOP500_STMPE1601_IRQ(x) (MOP500_STMPE1601_IRQBASE + (x)) - -#define MOP500_STMPE1601_IRQ_END \ - MOP500_STMPE1601_IRQ(STMPE_NR_INTERNAL_IRQS) - -#define MOP500_NR_IRQS MOP500_STMPE1601_IRQ_END - -#define MOP500_IRQ_END MOP500_NR_IRQS - -/* - * We may have several boards, but only one will run at a - * time, so the one with most IRQs will bump this ahead, - * but the IRQ_BOARD_START remains the same for either board. - */ -#if MOP500_IRQ_END > IRQ_BOARD_END -#undef IRQ_BOARD_END -#define IRQ_BOARD_END MOP500_IRQ_END -#endif - -#endif diff --git a/arch/arm/mach-ux500/include/mach/irqs-db8500.h b/arch/arm/mach-ux500/include/mach/irqs-db8500.h deleted file mode 100644 index f3a9d59..0000000 --- a/arch/arm/mach-ux500/include/mach/irqs-db8500.h +++ /dev/null @@ -1,125 +0,0 @@ -/* - * Copyright (C) ST-Ericsson SA 2010 - * - * Author: Rabin Vincent - * License terms: GNU General Public License (GPL) version 2 - */ - -#ifndef __MACH_IRQS_DB8500_H -#define __MACH_IRQS_DB8500_H - -#define IRQ_DB8500_MTU0 (IRQ_SHPI_START + 4) -#define IRQ_DB8500_SPI2 (IRQ_SHPI_START + 6) -#define IRQ_DB8500_PMU (IRQ_SHPI_START + 7) -#define IRQ_DB8500_SPI0 (IRQ_SHPI_START + 8) -#define IRQ_DB8500_RTT (IRQ_SHPI_START + 9) -#define IRQ_DB8500_PKA (IRQ_SHPI_START + 10) -#define IRQ_DB8500_UART0 (IRQ_SHPI_START + 11) -#define IRQ_DB8500_I2C3 (IRQ_SHPI_START + 12) -#define IRQ_DB8500_L2CC (IRQ_SHPI_START + 13) -#define IRQ_DB8500_SSP0 (IRQ_SHPI_START + 14) -#define IRQ_DB8500_CRYP1 (IRQ_SHPI_START + 15) -#define IRQ_DB8500_MSP1_RX (IRQ_SHPI_START + 16) -#define IRQ_DB8500_MTU1 (IRQ_SHPI_START + 17) -#define IRQ_DB8500_RTC (IRQ_SHPI_START + 18) -#define IRQ_DB8500_UART1 (IRQ_SHPI_START + 19) -#define IRQ_DB8500_USB_WAKEUP (IRQ_SHPI_START + 20) -#define IRQ_DB8500_I2C0 (IRQ_SHPI_START + 21) -#define IRQ_DB8500_I2C1 (IRQ_SHPI_START + 22) -#define IRQ_DB8500_USBOTG (IRQ_SHPI_START + 23) -#define IRQ_DB8500_DMA_SECURE (IRQ_SHPI_START + 24) -#define IRQ_DB8500_DMA (IRQ_SHPI_START + 25) -#define IRQ_DB8500_UART2 (IRQ_SHPI_START + 26) -#define IRQ_DB8500_ICN_PMU1 (IRQ_SHPI_START + 27) -#define IRQ_DB8500_ICN_PMU2 (IRQ_SHPI_START + 28) -#define IRQ_DB8500_HSIR_EXCEP (IRQ_SHPI_START + 29) -#define IRQ_DB8500_MSP0 (IRQ_SHPI_START + 31) -#define IRQ_DB8500_HSIR_CH0_OVRRUN (IRQ_SHPI_START + 32) -#define IRQ_DB8500_HSIR_CH1_OVRRUN (IRQ_SHPI_START + 33) -#define IRQ_DB8500_HSIR_CH2_OVRRUN (IRQ_SHPI_START + 34) -#define IRQ_DB8500_HSIR_CH3_OVRRUN (IRQ_SHPI_START + 35) -#define IRQ_DB8500_HSIR_CH4_OVRRUN (IRQ_SHPI_START + 36) -#define IRQ_DB8500_HSIR_CH5_OVRRUN (IRQ_SHPI_START + 37) -#define IRQ_DB8500_HSIR_CH6_OVRRUN (IRQ_SHPI_START + 38) -#define IRQ_DB8500_HSIR_CH7_OVRRUN (IRQ_SHPI_START + 39) -#define IRQ_DB8500_AB8500 (IRQ_SHPI_START + 40) -#define IRQ_DB8500_SDMMC2 (IRQ_SHPI_START + 41) -#define IRQ_DB8500_SIA (IRQ_SHPI_START + 42) -#define IRQ_DB8500_SIA2 (IRQ_SHPI_START + 43) -#define IRQ_DB8500_SVA (IRQ_SHPI_START + 44) -#define IRQ_DB8500_SVA2 (IRQ_SHPI_START + 45) -#define IRQ_DB8500_PRCMU0 (IRQ_SHPI_START + 46) -#define IRQ_DB8500_PRCMU1 (IRQ_SHPI_START + 47) -#define IRQ_DB8500_DISP (IRQ_SHPI_START + 48) -#define IRQ_DB8500_SPI3 (IRQ_SHPI_START + 49) -#define IRQ_DB8500_SDMMC1 (IRQ_SHPI_START + 50) -#define IRQ_DB8500_I2C4 (IRQ_SHPI_START + 51) -#define IRQ_DB8500_SSP1 (IRQ_SHPI_START + 52) -#define IRQ_DB8500_SKE (IRQ_SHPI_START + 53) -#define IRQ_DB8500_KB (IRQ_SHPI_START + 54) -#define IRQ_DB8500_I2C2 (IRQ_SHPI_START + 55) -#define IRQ_DB8500_B2R2 (IRQ_SHPI_START + 56) -#define IRQ_DB8500_CRYP0 (IRQ_SHPI_START + 57) -#define IRQ_DB8500_SDMMC3 (IRQ_SHPI_START + 59) -#define IRQ_DB8500_SDMMC0 (IRQ_SHPI_START + 60) -#define IRQ_DB8500_HSEM (IRQ_SHPI_START + 61) -#define IRQ_DB8500_MSP1 (IRQ_SHPI_START + 62) -#define IRQ_DB8500_SBAG (IRQ_SHPI_START + 63) -#define IRQ_DB8500_SPI1 (IRQ_SHPI_START + 96) -#define IRQ_DB8500_SRPTIMER (IRQ_SHPI_START + 97) -#define IRQ_DB8500_MSP2 (IRQ_SHPI_START + 98) -#define IRQ_DB8500_SDMMC4 (IRQ_SHPI_START + 99) -#define IRQ_DB8500_SDMMC5 (IRQ_SHPI_START + 100) -#define IRQ_DB8500_HSIRD0 (IRQ_SHPI_START + 104) -#define IRQ_DB8500_HSIRD1 (IRQ_SHPI_START + 105) -#define IRQ_DB8500_HSITD0 (IRQ_SHPI_START + 106) -#define IRQ_DB8500_HSITD1 (IRQ_SHPI_START + 107) -#define IRQ_DB8500_CTI0 (IRQ_SHPI_START + 108) -#define IRQ_DB8500_CTI1 (IRQ_SHPI_START + 109) -#define IRQ_DB8500_ICN_ERR (IRQ_SHPI_START + 110) -#define IRQ_DB8500_MALI_PPMMU (IRQ_SHPI_START + 112) -#define IRQ_DB8500_MALI_PP (IRQ_SHPI_START + 113) -#define IRQ_DB8500_MALI_GPMMU (IRQ_SHPI_START + 114) -#define IRQ_DB8500_MALI_GP (IRQ_SHPI_START + 115) -#define IRQ_DB8500_MALI (IRQ_SHPI_START + 116) -#define IRQ_DB8500_PRCMU_SEM (IRQ_SHPI_START + 118) -#define IRQ_DB8500_GPIO0 (IRQ_SHPI_START + 119) -#define IRQ_DB8500_GPIO1 (IRQ_SHPI_START + 120) -#define IRQ_DB8500_GPIO2 (IRQ_SHPI_START + 121) -#define IRQ_DB8500_GPIO3 (IRQ_SHPI_START + 122) -#define IRQ_DB8500_GPIO4 (IRQ_SHPI_START + 123) -#define IRQ_DB8500_GPIO5 (IRQ_SHPI_START + 124) -#define IRQ_DB8500_GPIO6 (IRQ_SHPI_START + 125) -#define IRQ_DB8500_GPIO7 (IRQ_SHPI_START + 126) -#define IRQ_DB8500_GPIO8 (IRQ_SHPI_START + 127) - -#define IRQ_CA_WAKE_REQ_ED (IRQ_SHPI_START + 71) -#define IRQ_AC_READ_NOTIFICATION_0_ED (IRQ_SHPI_START + 66) -#define IRQ_AC_READ_NOTIFICATION_1_ED (IRQ_SHPI_START + 64) -#define IRQ_CA_MSG_PEND_NOTIFICATION_0_ED (IRQ_SHPI_START + 67) -#define IRQ_CA_MSG_PEND_NOTIFICATION_1_ED (IRQ_SHPI_START + 65) - -#define IRQ_CA_WAKE_REQ_V1 (IRQ_SHPI_START + 83) -#define IRQ_AC_READ_NOTIFICATION_0_V1 (IRQ_SHPI_START + 78) -#define IRQ_AC_READ_NOTIFICATION_1_V1 (IRQ_SHPI_START + 76) -#define IRQ_CA_MSG_PEND_NOTIFICATION_0_V1 (IRQ_SHPI_START + 79) -#define IRQ_CA_MSG_PEND_NOTIFICATION_1_V1 (IRQ_SHPI_START + 77) - -#ifdef CONFIG_UX500_SOC_DB8500 - -/* Virtual interrupts corresponding to the PRCMU wakeups. */ -#define IRQ_PRCMU_BASE IRQ_SOC_START -#define IRQ_PRCMU_END (IRQ_PRCMU_BASE + 23) - -/* - * We may have several SoCs, but only one will run at a - * time, so the one with most IRQs will bump this ahead, - * but the IRQ_SOC_START remains the same for either SoC. - */ -#if IRQ_SOC_END < IRQ_PRCMU_END -#undef IRQ_SOC_END -#define IRQ_SOC_END IRQ_PRCMU_END -#endif - -#endif /* CONFIG_UX500_SOC_DB8500 */ -#endif diff --git a/arch/arm/mach-ux500/include/mach/irqs.h b/arch/arm/mach-ux500/include/mach/irqs.h deleted file mode 100644 index 829947d..0000000 --- a/arch/arm/mach-ux500/include/mach/irqs.h +++ /dev/null @@ -1,49 +0,0 @@ -/* - * Copyright (C) 2008 STMicroelectronics - * Copyright (C) 2009 ST-Ericsson. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ -#ifndef ASM_ARCH_IRQS_H -#define ASM_ARCH_IRQS_H - -#define IRQ_LOCALTIMER 29 -#define IRQ_LOCALWDOG 30 - -/* Shared Peripheral Interrupt (SHPI) */ -#define IRQ_SHPI_START 32 - -/* - * MTU0 preserved for now until plat-nomadik is taught not to use it. Don't - * add any other IRQs here, use the irqs-dbx500.h files. - */ -#define IRQ_MTU0 (IRQ_SHPI_START + 4) - -#define DBX500_NR_INTERNAL_IRQS 166 - -/* After chip-specific IRQ numbers we have the GPIO ones */ -#define NOMADIK_NR_GPIO 288 -#define NOMADIK_GPIO_TO_IRQ(gpio) ((gpio) + DBX500_NR_INTERNAL_IRQS) -#define NOMADIK_IRQ_TO_GPIO(irq) ((irq) - DBX500_NR_INTERNAL_IRQS) -#define IRQ_GPIO_END NOMADIK_GPIO_TO_IRQ(NOMADIK_NR_GPIO) - -#define IRQ_SOC_START IRQ_GPIO_END -/* This will be overridden by SoC-specific irq headers */ -#define IRQ_SOC_END IRQ_SOC_START - -#include - -#define IRQ_BOARD_START IRQ_SOC_END -/* This will be overridden by board-specific irq headers */ -#define IRQ_BOARD_END IRQ_BOARD_START - -#ifdef CONFIG_MACH_MOP500 -#include -#endif - -#define UX500_NR_IRQS IRQ_BOARD_END - -#endif /* ASM_ARCH_IRQS_H */ diff --git a/arch/arm/mach-ux500/irqs-board-mop500.h b/arch/arm/mach-ux500/irqs-board-mop500.h new file mode 100644 index 0000000..d526dd8 --- /dev/null +++ b/arch/arm/mach-ux500/irqs-board-mop500.h @@ -0,0 +1,55 @@ +/* + * Copyright (C) ST-Ericsson SA 2010 + * + * Author: Rabin Vincent + * License terms: GNU General Public License (GPL) version 2 + */ + +#ifndef __MACH_IRQS_BOARD_MOP500_H +#define __MACH_IRQS_BOARD_MOP500_H + +/* Number of AB8500 irqs is taken from header file */ +#include + +#define MOP500_AB8500_IRQ_BASE IRQ_BOARD_START +#define MOP500_AB8500_IRQ_END (MOP500_AB8500_IRQ_BASE \ + + AB8500_MAX_NR_IRQS) + +/* TC35892 */ +#define TC35892_NR_INTERNAL_IRQS 8 +#define TC35892_INT_GPIO(x) (TC35892_NR_INTERNAL_IRQS + (x)) +#define TC35892_NR_GPIOS 24 +#define TC35892_NR_IRQS TC35892_INT_GPIO(TC35892_NR_GPIOS) + +#define MOP500_EGPIO_NR_IRQS TC35892_NR_IRQS + +#define MOP500_EGPIO_IRQ_BASE MOP500_AB8500_IRQ_END +#define MOP500_EGPIO_IRQ_END (MOP500_EGPIO_IRQ_BASE \ + + MOP500_EGPIO_NR_IRQS) +/* STMPE1601 irqs */ +#define STMPE_NR_INTERNAL_IRQS 9 +#define STMPE_INT_GPIO(x) (STMPE_NR_INTERNAL_IRQS + (x)) +#define STMPE_NR_GPIOS 24 +#define STMPE_NR_IRQS STMPE_INT_GPIO(STMPE_NR_GPIOS) + +#define MOP500_STMPE1601_IRQBASE MOP500_EGPIO_IRQ_END +#define MOP500_STMPE1601_IRQ(x) (MOP500_STMPE1601_IRQBASE + (x)) + +#define MOP500_STMPE1601_IRQ_END \ + MOP500_STMPE1601_IRQ(STMPE_NR_INTERNAL_IRQS) + +#define MOP500_NR_IRQS MOP500_STMPE1601_IRQ_END + +#define MOP500_IRQ_END MOP500_NR_IRQS + +/* + * We may have several boards, but only one will run at a + * time, so the one with most IRQs will bump this ahead, + * but the IRQ_BOARD_START remains the same for either board. + */ +#if MOP500_IRQ_END > IRQ_BOARD_END +#undef IRQ_BOARD_END +#define IRQ_BOARD_END MOP500_IRQ_END +#endif + +#endif diff --git a/arch/arm/mach-ux500/irqs-db8500.h b/arch/arm/mach-ux500/irqs-db8500.h new file mode 100644 index 0000000..f3a9d59 --- /dev/null +++ b/arch/arm/mach-ux500/irqs-db8500.h @@ -0,0 +1,125 @@ +/* + * Copyright (C) ST-Ericsson SA 2010 + * + * Author: Rabin Vincent + * License terms: GNU General Public License (GPL) version 2 + */ + +#ifndef __MACH_IRQS_DB8500_H +#define __MACH_IRQS_DB8500_H + +#define IRQ_DB8500_MTU0 (IRQ_SHPI_START + 4) +#define IRQ_DB8500_SPI2 (IRQ_SHPI_START + 6) +#define IRQ_DB8500_PMU (IRQ_SHPI_START + 7) +#define IRQ_DB8500_SPI0 (IRQ_SHPI_START + 8) +#define IRQ_DB8500_RTT (IRQ_SHPI_START + 9) +#define IRQ_DB8500_PKA (IRQ_SHPI_START + 10) +#define IRQ_DB8500_UART0 (IRQ_SHPI_START + 11) +#define IRQ_DB8500_I2C3 (IRQ_SHPI_START + 12) +#define IRQ_DB8500_L2CC (IRQ_SHPI_START + 13) +#define IRQ_DB8500_SSP0 (IRQ_SHPI_START + 14) +#define IRQ_DB8500_CRYP1 (IRQ_SHPI_START + 15) +#define IRQ_DB8500_MSP1_RX (IRQ_SHPI_START + 16) +#define IRQ_DB8500_MTU1 (IRQ_SHPI_START + 17) +#define IRQ_DB8500_RTC (IRQ_SHPI_START + 18) +#define IRQ_DB8500_UART1 (IRQ_SHPI_START + 19) +#define IRQ_DB8500_USB_WAKEUP (IRQ_SHPI_START + 20) +#define IRQ_DB8500_I2C0 (IRQ_SHPI_START + 21) +#define IRQ_DB8500_I2C1 (IRQ_SHPI_START + 22) +#define IRQ_DB8500_USBOTG (IRQ_SHPI_START + 23) +#define IRQ_DB8500_DMA_SECURE (IRQ_SHPI_START + 24) +#define IRQ_DB8500_DMA (IRQ_SHPI_START + 25) +#define IRQ_DB8500_UART2 (IRQ_SHPI_START + 26) +#define IRQ_DB8500_ICN_PMU1 (IRQ_SHPI_START + 27) +#define IRQ_DB8500_ICN_PMU2 (IRQ_SHPI_START + 28) +#define IRQ_DB8500_HSIR_EXCEP (IRQ_SHPI_START + 29) +#define IRQ_DB8500_MSP0 (IRQ_SHPI_START + 31) +#define IRQ_DB8500_HSIR_CH0_OVRRUN (IRQ_SHPI_START + 32) +#define IRQ_DB8500_HSIR_CH1_OVRRUN (IRQ_SHPI_START + 33) +#define IRQ_DB8500_HSIR_CH2_OVRRUN (IRQ_SHPI_START + 34) +#define IRQ_DB8500_HSIR_CH3_OVRRUN (IRQ_SHPI_START + 35) +#define IRQ_DB8500_HSIR_CH4_OVRRUN (IRQ_SHPI_START + 36) +#define IRQ_DB8500_HSIR_CH5_OVRRUN (IRQ_SHPI_START + 37) +#define IRQ_DB8500_HSIR_CH6_OVRRUN (IRQ_SHPI_START + 38) +#define IRQ_DB8500_HSIR_CH7_OVRRUN (IRQ_SHPI_START + 39) +#define IRQ_DB8500_AB8500 (IRQ_SHPI_START + 40) +#define IRQ_DB8500_SDMMC2 (IRQ_SHPI_START + 41) +#define IRQ_DB8500_SIA (IRQ_SHPI_START + 42) +#define IRQ_DB8500_SIA2 (IRQ_SHPI_START + 43) +#define IRQ_DB8500_SVA (IRQ_SHPI_START + 44) +#define IRQ_DB8500_SVA2 (IRQ_SHPI_START + 45) +#define IRQ_DB8500_PRCMU0 (IRQ_SHPI_START + 46) +#define IRQ_DB8500_PRCMU1 (IRQ_SHPI_START + 47) +#define IRQ_DB8500_DISP (IRQ_SHPI_START + 48) +#define IRQ_DB8500_SPI3 (IRQ_SHPI_START + 49) +#define IRQ_DB8500_SDMMC1 (IRQ_SHPI_START + 50) +#define IRQ_DB8500_I2C4 (IRQ_SHPI_START + 51) +#define IRQ_DB8500_SSP1 (IRQ_SHPI_START + 52) +#define IRQ_DB8500_SKE (IRQ_SHPI_START + 53) +#define IRQ_DB8500_KB (IRQ_SHPI_START + 54) +#define IRQ_DB8500_I2C2 (IRQ_SHPI_START + 55) +#define IRQ_DB8500_B2R2 (IRQ_SHPI_START + 56) +#define IRQ_DB8500_CRYP0 (IRQ_SHPI_START + 57) +#define IRQ_DB8500_SDMMC3 (IRQ_SHPI_START + 59) +#define IRQ_DB8500_SDMMC0 (IRQ_SHPI_START + 60) +#define IRQ_DB8500_HSEM (IRQ_SHPI_START + 61) +#define IRQ_DB8500_MSP1 (IRQ_SHPI_START + 62) +#define IRQ_DB8500_SBAG (IRQ_SHPI_START + 63) +#define IRQ_DB8500_SPI1 (IRQ_SHPI_START + 96) +#define IRQ_DB8500_SRPTIMER (IRQ_SHPI_START + 97) +#define IRQ_DB8500_MSP2 (IRQ_SHPI_START + 98) +#define IRQ_DB8500_SDMMC4 (IRQ_SHPI_START + 99) +#define IRQ_DB8500_SDMMC5 (IRQ_SHPI_START + 100) +#define IRQ_DB8500_HSIRD0 (IRQ_SHPI_START + 104) +#define IRQ_DB8500_HSIRD1 (IRQ_SHPI_START + 105) +#define IRQ_DB8500_HSITD0 (IRQ_SHPI_START + 106) +#define IRQ_DB8500_HSITD1 (IRQ_SHPI_START + 107) +#define IRQ_DB8500_CTI0 (IRQ_SHPI_START + 108) +#define IRQ_DB8500_CTI1 (IRQ_SHPI_START + 109) +#define IRQ_DB8500_ICN_ERR (IRQ_SHPI_START + 110) +#define IRQ_DB8500_MALI_PPMMU (IRQ_SHPI_START + 112) +#define IRQ_DB8500_MALI_PP (IRQ_SHPI_START + 113) +#define IRQ_DB8500_MALI_GPMMU (IRQ_SHPI_START + 114) +#define IRQ_DB8500_MALI_GP (IRQ_SHPI_START + 115) +#define IRQ_DB8500_MALI (IRQ_SHPI_START + 116) +#define IRQ_DB8500_PRCMU_SEM (IRQ_SHPI_START + 118) +#define IRQ_DB8500_GPIO0 (IRQ_SHPI_START + 119) +#define IRQ_DB8500_GPIO1 (IRQ_SHPI_START + 120) +#define IRQ_DB8500_GPIO2 (IRQ_SHPI_START + 121) +#define IRQ_DB8500_GPIO3 (IRQ_SHPI_START + 122) +#define IRQ_DB8500_GPIO4 (IRQ_SHPI_START + 123) +#define IRQ_DB8500_GPIO5 (IRQ_SHPI_START + 124) +#define IRQ_DB8500_GPIO6 (IRQ_SHPI_START + 125) +#define IRQ_DB8500_GPIO7 (IRQ_SHPI_START + 126) +#define IRQ_DB8500_GPIO8 (IRQ_SHPI_START + 127) + +#define IRQ_CA_WAKE_REQ_ED (IRQ_SHPI_START + 71) +#define IRQ_AC_READ_NOTIFICATION_0_ED (IRQ_SHPI_START + 66) +#define IRQ_AC_READ_NOTIFICATION_1_ED (IRQ_SHPI_START + 64) +#define IRQ_CA_MSG_PEND_NOTIFICATION_0_ED (IRQ_SHPI_START + 67) +#define IRQ_CA_MSG_PEND_NOTIFICATION_1_ED (IRQ_SHPI_START + 65) + +#define IRQ_CA_WAKE_REQ_V1 (IRQ_SHPI_START + 83) +#define IRQ_AC_READ_NOTIFICATION_0_V1 (IRQ_SHPI_START + 78) +#define IRQ_AC_READ_NOTIFICATION_1_V1 (IRQ_SHPI_START + 76) +#define IRQ_CA_MSG_PEND_NOTIFICATION_0_V1 (IRQ_SHPI_START + 79) +#define IRQ_CA_MSG_PEND_NOTIFICATION_1_V1 (IRQ_SHPI_START + 77) + +#ifdef CONFIG_UX500_SOC_DB8500 + +/* Virtual interrupts corresponding to the PRCMU wakeups. */ +#define IRQ_PRCMU_BASE IRQ_SOC_START +#define IRQ_PRCMU_END (IRQ_PRCMU_BASE + 23) + +/* + * We may have several SoCs, but only one will run at a + * time, so the one with most IRQs will bump this ahead, + * but the IRQ_SOC_START remains the same for either SoC. + */ +#if IRQ_SOC_END < IRQ_PRCMU_END +#undef IRQ_SOC_END +#define IRQ_SOC_END IRQ_PRCMU_END +#endif + +#endif /* CONFIG_UX500_SOC_DB8500 */ +#endif diff --git a/arch/arm/mach-ux500/irqs.h b/arch/arm/mach-ux500/irqs.h new file mode 100644 index 0000000..15b2af6 --- /dev/null +++ b/arch/arm/mach-ux500/irqs.h @@ -0,0 +1,49 @@ +/* + * Copyright (C) 2008 STMicroelectronics + * Copyright (C) 2009 ST-Ericsson. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ +#ifndef ASM_ARCH_IRQS_H +#define ASM_ARCH_IRQS_H + +#define IRQ_LOCALTIMER 29 +#define IRQ_LOCALWDOG 30 + +/* Shared Peripheral Interrupt (SHPI) */ +#define IRQ_SHPI_START 32 + +/* + * MTU0 preserved for now until plat-nomadik is taught not to use it. Don't + * add any other IRQs here, use the irqs-dbx500.h files. + */ +#define IRQ_MTU0 (IRQ_SHPI_START + 4) + +#define DBX500_NR_INTERNAL_IRQS 166 + +/* After chip-specific IRQ numbers we have the GPIO ones */ +#define NOMADIK_NR_GPIO 288 +#define NOMADIK_GPIO_TO_IRQ(gpio) ((gpio) + DBX500_NR_INTERNAL_IRQS) +#define NOMADIK_IRQ_TO_GPIO(irq) ((irq) - DBX500_NR_INTERNAL_IRQS) +#define IRQ_GPIO_END NOMADIK_GPIO_TO_IRQ(NOMADIK_NR_GPIO) + +#define IRQ_SOC_START IRQ_GPIO_END +/* This will be overridden by SoC-specific irq headers */ +#define IRQ_SOC_END IRQ_SOC_START + +#include "irqs-db8500.h" + +#define IRQ_BOARD_START IRQ_SOC_END +/* This will be overridden by board-specific irq headers */ +#define IRQ_BOARD_END IRQ_BOARD_START + +#ifdef CONFIG_MACH_MOP500 +#include "irqs-board-mop500.h" +#endif + +#define UX500_NR_IRQS IRQ_BOARD_END + +#endif /* ASM_ARCH_IRQS_H */ diff --git a/arch/arm/mach-ux500/timer.c b/arch/arm/mach-ux500/timer.c index 5b91fac..2dbbaef 100644 --- a/arch/arm/mach-ux500/timer.c +++ b/arch/arm/mach-ux500/timer.c @@ -14,7 +14,7 @@ #include #include -#include +#include "irqs.h" #include "db8500-regs.h" #include "id.h" -- cgit v1.1 From e657bcf6db84864079b31909e911a69c813aa0c0 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Thu, 21 Mar 2013 22:51:12 +0100 Subject: ARM: ux500: make remaining headers local mach/setup.h and mach/devices.h are only needed from inside of mach-ux500 now, so we can simply move them out of the include/mach directory. Signed-off-by: Arnd Bergmann Signed-off-by: Linus Walleij --- arch/arm/mach-ux500/board-mop500-audio.c | 2 +- arch/arm/mach-ux500/board-mop500-sdi.c | 2 +- arch/arm/mach-ux500/board-mop500.c | 4 +-- arch/arm/mach-ux500/cpu-db8500.c | 4 +-- arch/arm/mach-ux500/cpu.c | 4 +-- arch/arm/mach-ux500/devices-db8500.c | 2 +- arch/arm/mach-ux500/devices.c | 2 +- arch/arm/mach-ux500/devices.h | 23 ++++++++++++++ arch/arm/mach-ux500/hotplug.c | 2 +- arch/arm/mach-ux500/id.c | 2 +- arch/arm/mach-ux500/include/mach/devices.h | 23 -------------- arch/arm/mach-ux500/include/mach/setup.h | 50 ------------------------------ arch/arm/mach-ux500/platsmp.c | 2 +- arch/arm/mach-ux500/setup.h | 50 ++++++++++++++++++++++++++++++ arch/arm/mach-ux500/timer.c | 2 +- 15 files changed, 87 insertions(+), 87 deletions(-) create mode 100644 arch/arm/mach-ux500/devices.h delete mode 100644 arch/arm/mach-ux500/include/mach/devices.h delete mode 100644 arch/arm/mach-ux500/include/mach/setup.h create mode 100644 arch/arm/mach-ux500/setup.h (limited to 'arch/arm') diff --git a/arch/arm/mach-ux500/board-mop500-audio.c b/arch/arm/mach-ux500/board-mop500-audio.c index def0637..aba9e56 100644 --- a/arch/arm/mach-ux500/board-mop500-audio.c +++ b/arch/arm/mach-ux500/board-mop500-audio.c @@ -10,7 +10,7 @@ #include #include -#include +#include "devices.h" #include "irqs.h" #include diff --git a/arch/arm/mach-ux500/board-mop500-sdi.c b/arch/arm/mach-ux500/board-mop500-sdi.c index 0ada767..f76be4a 100644 --- a/arch/arm/mach-ux500/board-mop500-sdi.c +++ b/arch/arm/mach-ux500/board-mop500-sdi.c @@ -14,7 +14,7 @@ #include #include -#include +#include "devices.h" #include "db8500-regs.h" #include "devices-db8500.h" diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c index 6e8ee11..0d59e1a 100644 --- a/arch/arm/mach-ux500/board-mop500.c +++ b/arch/arm/mach-ux500/board-mop500.c @@ -41,8 +41,8 @@ #include #include -#include -#include +#include "setup.h" +#include "devices.h" #include "irqs.h" #include diff --git a/arch/arm/mach-ux500/cpu-db8500.c b/arch/arm/mach-ux500/cpu-db8500.c index e11f87d..7a66a81 100644 --- a/arch/arm/mach-ux500/cpu-db8500.c +++ b/arch/arm/mach-ux500/cpu-db8500.c @@ -28,8 +28,8 @@ #include #include -#include -#include +#include "setup.h" +#include "devices.h" #include "irqs.h" #include "devices-db8500.h" diff --git a/arch/arm/mach-ux500/cpu.c b/arch/arm/mach-ux500/cpu.c index aa14c5f..915e263 100644 --- a/arch/arm/mach-ux500/cpu.c +++ b/arch/arm/mach-ux500/cpu.c @@ -24,8 +24,8 @@ #include -#include -#include +#include "setup.h" +#include "devices.h" #include "board-mop500.h" #include "db8500-regs.h" diff --git a/arch/arm/mach-ux500/devices-db8500.c b/arch/arm/mach-ux500/devices-db8500.c index 45ec955..1cf94ce 100644 --- a/arch/arm/mach-ux500/devices-db8500.c +++ b/arch/arm/mach-ux500/devices-db8500.c @@ -15,7 +15,7 @@ #include #include -#include +#include "setup.h" #include "irqs.h" #include "db8500-regs.h" diff --git a/arch/arm/mach-ux500/devices.c b/arch/arm/mach-ux500/devices.c index f63a512..0f9e52b 100644 --- a/arch/arm/mach-ux500/devices.c +++ b/arch/arm/mach-ux500/devices.c @@ -11,7 +11,7 @@ #include #include -#include +#include "setup.h" #include "db8500-regs.h" diff --git a/arch/arm/mach-ux500/devices.h b/arch/arm/mach-ux500/devices.h new file mode 100644 index 0000000..cbc6f1e --- /dev/null +++ b/arch/arm/mach-ux500/devices.h @@ -0,0 +1,23 @@ +/* + * Copyright (C) ST-Ericsson SA 2010 + * + * License terms: GNU General Public License (GPL) version 2 + */ + +#ifndef __ASM_ARCH_DEVICES_H__ +#define __ASM_ARCH_DEVICES_H__ + +struct platform_device; +struct amba_device; + +extern struct platform_device u8500_gpio_devs[]; + +extern struct amba_device ux500_pl031_device; + +extern struct platform_device ux500_hash1_device; +extern struct platform_device ux500_cryp1_device; + +extern struct platform_device u8500_dma40_device; +extern struct platform_device ux500_ske_keypad_device; + +#endif diff --git a/arch/arm/mach-ux500/hotplug.c b/arch/arm/mach-ux500/hotplug.c index 2f6af25..87abcf2 100644 --- a/arch/arm/mach-ux500/hotplug.c +++ b/arch/arm/mach-ux500/hotplug.c @@ -15,7 +15,7 @@ #include #include -#include +#include "setup.h" /* * platform-specific code to shutdown a CPU diff --git a/arch/arm/mach-ux500/id.c b/arch/arm/mach-ux500/id.c index a847cf2..0d33d1a 100644 --- a/arch/arm/mach-ux500/id.c +++ b/arch/arm/mach-ux500/id.c @@ -14,7 +14,7 @@ #include #include -#include +#include "setup.h" #include "db8500-regs.h" #include "id.h" diff --git a/arch/arm/mach-ux500/include/mach/devices.h b/arch/arm/mach-ux500/include/mach/devices.h deleted file mode 100644 index cbc6f1e..0000000 --- a/arch/arm/mach-ux500/include/mach/devices.h +++ /dev/null @@ -1,23 +0,0 @@ -/* - * Copyright (C) ST-Ericsson SA 2010 - * - * License terms: GNU General Public License (GPL) version 2 - */ - -#ifndef __ASM_ARCH_DEVICES_H__ -#define __ASM_ARCH_DEVICES_H__ - -struct platform_device; -struct amba_device; - -extern struct platform_device u8500_gpio_devs[]; - -extern struct amba_device ux500_pl031_device; - -extern struct platform_device ux500_hash1_device; -extern struct platform_device ux500_cryp1_device; - -extern struct platform_device u8500_dma40_device; -extern struct platform_device ux500_ske_keypad_device; - -#endif diff --git a/arch/arm/mach-ux500/include/mach/setup.h b/arch/arm/mach-ux500/include/mach/setup.h deleted file mode 100644 index bddce2b..0000000 --- a/arch/arm/mach-ux500/include/mach/setup.h +++ /dev/null @@ -1,50 +0,0 @@ -/* - * Copyright (C) 2009 ST-Ericsson. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * These symbols are needed for board-specific files to call their - * own cpu-specific files - */ -#ifndef __ASM_ARCH_SETUP_H -#define __ASM_ARCH_SETUP_H - -#include -#include -#include - -void __init ux500_map_io(void); -extern void __init u8500_map_io(void); - -extern struct device * __init u8500_init_devices(struct ab8500_platform_data *ab8500); - -extern void __init ux500_init_irq(void); -extern void __init ux500_init_late(void); - -extern struct device *ux500_soc_device_init(const char *soc_id); - -struct amba_device; -extern void __init amba_add_devices(struct amba_device *devs[], int num); - -extern void ux500_timer_init(void); - -#define __IO_DEV_DESC(x, sz) { \ - .virtual = IO_ADDRESS(x), \ - .pfn = __phys_to_pfn(x), \ - .length = sz, \ - .type = MT_DEVICE, \ -} - -#define __MEM_DEV_DESC(x, sz) { \ - .virtual = IO_ADDRESS(x), \ - .pfn = __phys_to_pfn(x), \ - .length = sz, \ - .type = MT_MEMORY, \ -} - -extern struct smp_operations ux500_smp_ops; -extern void ux500_cpu_die(unsigned int cpu); - -#endif /* __ASM_ARCH_SETUP_H */ diff --git a/arch/arm/mach-ux500/platsmp.c b/arch/arm/mach-ux500/platsmp.c index 8a9c070..12ad8ad 100644 --- a/arch/arm/mach-ux500/platsmp.c +++ b/arch/arm/mach-ux500/platsmp.c @@ -22,7 +22,7 @@ #include #include -#include +#include "setup.h" #include "db8500-regs.h" #include "id.h" diff --git a/arch/arm/mach-ux500/setup.h b/arch/arm/mach-ux500/setup.h new file mode 100644 index 0000000..bddce2b --- /dev/null +++ b/arch/arm/mach-ux500/setup.h @@ -0,0 +1,50 @@ +/* + * Copyright (C) 2009 ST-Ericsson. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * These symbols are needed for board-specific files to call their + * own cpu-specific files + */ +#ifndef __ASM_ARCH_SETUP_H +#define __ASM_ARCH_SETUP_H + +#include +#include +#include + +void __init ux500_map_io(void); +extern void __init u8500_map_io(void); + +extern struct device * __init u8500_init_devices(struct ab8500_platform_data *ab8500); + +extern void __init ux500_init_irq(void); +extern void __init ux500_init_late(void); + +extern struct device *ux500_soc_device_init(const char *soc_id); + +struct amba_device; +extern void __init amba_add_devices(struct amba_device *devs[], int num); + +extern void ux500_timer_init(void); + +#define __IO_DEV_DESC(x, sz) { \ + .virtual = IO_ADDRESS(x), \ + .pfn = __phys_to_pfn(x), \ + .length = sz, \ + .type = MT_DEVICE, \ +} + +#define __MEM_DEV_DESC(x, sz) { \ + .virtual = IO_ADDRESS(x), \ + .pfn = __phys_to_pfn(x), \ + .length = sz, \ + .type = MT_MEMORY, \ +} + +extern struct smp_operations ux500_smp_ops; +extern void ux500_cpu_die(unsigned int cpu); + +#endif /* __ASM_ARCH_SETUP_H */ diff --git a/arch/arm/mach-ux500/timer.c b/arch/arm/mach-ux500/timer.c index 2dbbaef..290b9c5 100644 --- a/arch/arm/mach-ux500/timer.c +++ b/arch/arm/mach-ux500/timer.c @@ -13,7 +13,7 @@ #include -#include +#include "setup.h" #include "irqs.h" #include "db8500-regs.h" -- cgit v1.1 From 7f01e5a7e6a0e99dd9fe9277595953832da8491e Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Thu, 21 Mar 2013 22:51:13 +0100 Subject: ARM: ux500: move to multiplatform Nothing is holding us up any more, and we can make ux500 coexist with the rest of the platforms. The timex.h and uncompress.h headers are no longer needed now. Signed-off-by: Arnd Bergmann Signed-off-by: Linus Walleij --- arch/arm/Kconfig | 15 ------- arch/arm/mach-ux500/Kconfig | 14 +++++++ arch/arm/mach-ux500/include/mach/timex.h | 6 --- arch/arm/mach-ux500/include/mach/uncompress.h | 58 --------------------------- 4 files changed, 14 insertions(+), 79 deletions(-) delete mode 100644 arch/arm/mach-ux500/include/mach/timex.h delete mode 100644 arch/arm/mach-ux500/include/mach/uncompress.h (limited to 'arch/arm') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 2c3bdce..6ece86a 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -900,21 +900,6 @@ config ARCH_U300 help Support for ST-Ericsson U300 series mobile platforms. -config ARCH_U8500 - bool "ST-Ericsson U8500 Series" - depends on MMU - select ARCH_HAS_CPUFREQ - select ARCH_REQUIRE_GPIOLIB - select ARM_AMBA - select CLKDEV_LOOKUP - select CPU_V7 - select GENERIC_CLOCKEVENTS - select HAVE_SMP - select MIGHT_HAVE_CACHE_L2X0 - select SPARSE_IRQ - help - Support for ST-Ericsson's Ux500 architecture - config ARCH_NOMADIK bool "STMicroelectronics Nomadik" select ARCH_REQUIRE_GPIOLIB diff --git a/arch/arm/mach-ux500/Kconfig b/arch/arm/mach-ux500/Kconfig index 3e5bbd0..eeea3bf 100644 --- a/arch/arm/mach-ux500/Kconfig +++ b/arch/arm/mach-ux500/Kconfig @@ -1,3 +1,17 @@ +config ARCH_U8500 + bool "ST-Ericsson U8500 Series" if ARCH_MULTI_V7 + depends on MMU + select ARCH_HAS_CPUFREQ + select ARCH_REQUIRE_GPIOLIB + select ARM_AMBA + select CLKDEV_LOOKUP + select CPU_V7 + select GENERIC_CLOCKEVENTS + select HAVE_SMP + select MIGHT_HAVE_CACHE_L2X0 + help + Support for ST-Ericsson's Ux500 architecture + if ARCH_U8500 config UX500_SOC_COMMON diff --git a/arch/arm/mach-ux500/include/mach/timex.h b/arch/arm/mach-ux500/include/mach/timex.h deleted file mode 100644 index d0942c1..0000000 --- a/arch/arm/mach-ux500/include/mach/timex.h +++ /dev/null @@ -1,6 +0,0 @@ -#ifndef __ASM_ARCH_TIMEX_H -#define __ASM_ARCH_TIMEX_H - -#define CLOCK_TICK_RATE 110000000 - -#endif diff --git a/arch/arm/mach-ux500/include/mach/uncompress.h b/arch/arm/mach-ux500/include/mach/uncompress.h deleted file mode 100644 index 533a004..0000000 --- a/arch/arm/mach-ux500/include/mach/uncompress.h +++ /dev/null @@ -1,58 +0,0 @@ -/* - * Copyright (C) 2009 ST-Ericsson - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#ifndef __ASM_ARCH_UNCOMPRESS_H -#define __ASM_ARCH_UNCOMPRESS_H - -#include -#include -#include -#include -/* TODO: This goes away in multiplatform boot, this file gets deleted */ -#include "../../db8500-regs.h" - -void __iomem *ux500_uart_base; - -static void putc(const char c) -{ - /* Do nothing if the UART is not enabled. */ - if (!(__raw_readb(ux500_uart_base + UART011_CR) & 0x1)) - return; - - if (c == '\n') - putc('\r'); - - while (__raw_readb(ux500_uart_base + UART01x_FR) & (1 << 5)) - barrier(); - __raw_writeb(c, ux500_uart_base + UART01x_DR); -} - -static void flush(void) -{ - if (!(__raw_readb(ux500_uart_base + UART011_CR) & 0x1)) - return; - while (__raw_readb(ux500_uart_base + UART01x_FR) & (1 << 3)) - barrier(); -} - -static inline void arch_decomp_setup(void) -{ - /* Use machine_is_foo() macro if you need to switch base someday */ - ux500_uart_base = (void __iomem *)U8500_UART2_BASE; -} - -#endif /* __ASM_ARCH_UNCOMPRESS_H */ -- cgit v1.1 From f6f1bdac9d3006e246e82672322dcd7e7e0863fd Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Thu, 21 Mar 2013 22:51:14 +0100 Subject: ARM: ux500: build hotplug.o for ARMv7-a If we try to build this file in a multiplatform configuration with ARMv6 enabled, gas complains about the dsb operation being undefined. Adding -march=armv7-a is safe because that code is only ever run on ux500, which is Cortex-A9. Signed-off-by: Arnd Bergmann Signed-off-by: Linus Walleij --- arch/arm/mach-ux500/Makefile | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/mach-ux500/Makefile b/arch/arm/mach-ux500/Makefile index 580a4db..bf9b6be 100644 --- a/arch/arm/mach-ux500/Makefile +++ b/arch/arm/mach-ux500/Makefile @@ -15,3 +15,5 @@ obj-$(CONFIG_MACH_MOP500) += board-mop500.o board-mop500-sdi.o \ board-mop500-audio.o obj-$(CONFIG_SMP) += platsmp.o headsmp.o obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o + +CFLAGS_hotplug.o += -march=armv7-a -- cgit v1.1 From 4c3ffffdbca2e6f6f5125fa7b149d87a13f92c94 Mon Sep 17 00:00:00 2001 From: Stephen Boyd Date: Wed, 27 Feb 2013 15:28:14 -0800 Subject: ARM: Push selects for TWD/SCU into machine entries The TWD and SCU configs are selected by default as long as MSM_SCORPIONMP is false and/or MCT is false. Implementing the logic this way certainly saves lines in the Kconfig but it precludes those machines which select MSM_SCORPIONMP or MCT from participating in the single zImage effort because when those machines are combined with other SMP capable machines the TWD and SCU are no longer selected by default. Push the select out to the machine entries so that we can compile these machines together and still select the appropriate configs. Cc: Barry Song Acked-by: David Brown Cc: Kukjin Kim Cc: Linus Walleij Acked-by: Pawel Moll Cc: Rob Herring Cc: Russell King Acked-by: Santosh Shilimkar Cc: Sascha Hauer Cc: Shiraz Hashim Acked-by: Simon Horman Cc: Srinidhi Kasagar Cc: Stephen Warren Cc: Tony Lindgren Acked-by: Viresh Kumar Signed-off-by: Stephen Boyd Signed-off-by: Arnd Bergmann --- arch/arm/Kconfig | 4 ++-- arch/arm/mach-exynos/Kconfig | 2 ++ arch/arm/mach-highbank/Kconfig | 1 + arch/arm/mach-imx/Kconfig | 3 ++- arch/arm/mach-msm/Kconfig | 7 ++----- arch/arm/mach-omap2/Kconfig | 2 ++ arch/arm/mach-prima2/Kconfig | 1 + arch/arm/mach-realview/Kconfig | 8 ++++++++ arch/arm/mach-spear/Kconfig | 2 ++ arch/arm/mach-tegra/Kconfig | 2 ++ arch/arm/mach-ux500/Kconfig | 2 ++ arch/arm/mach-vexpress/Kconfig | 2 ++ arch/arm/mach-zynq/Kconfig | 2 ++ 13 files changed, 30 insertions(+), 8 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 3a6333e..88b662d 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -637,6 +637,8 @@ config ARCH_SHMOBILE bool "Renesas SH-Mobile / R-Mobile" select CLKDEV_LOOKUP select GENERIC_CLOCKEVENTS + select HAVE_ARM_SCU if SMP + select HAVE_ARM_TWD if LOCAL_TIMERS select HAVE_CLK select HAVE_MACH_CLKDEV select HAVE_SMP @@ -1400,7 +1402,6 @@ config SMP depends on GENERIC_CLOCKEVENTS depends on HAVE_SMP depends on MMU - select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP select USE_GENERIC_SMP_HELPERS help This enables support for systems with more than one CPU. If you have @@ -1525,7 +1526,6 @@ config LOCAL_TIMERS bool "Use local timer interrupts" depends on SMP default y - select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT) help Enable support for local timers on SMP platforms, rather then the legacy IPI broadcast method. Local timers allows the system diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig index 70f94c8..54cf73e 100644 --- a/arch/arm/mach-exynos/Kconfig +++ b/arch/arm/mach-exynos/Kconfig @@ -14,6 +14,7 @@ menu "SAMSUNG EXYNOS SoCs Support" config ARCH_EXYNOS4 bool "SAMSUNG EXYNOS4" default y + select HAVE_ARM_SCU if SMP select HAVE_SMP select MIGHT_HAVE_CACHE_L2X0 help @@ -21,6 +22,7 @@ config ARCH_EXYNOS4 config ARCH_EXYNOS5 bool "SAMSUNG EXYNOS5" + select HAVE_ARM_SCU if SMP select HAVE_SMP help Samsung EXYNOS5 (Cortex-A15) SoC based systems diff --git a/arch/arm/mach-highbank/Kconfig b/arch/arm/mach-highbank/Kconfig index 44b12f9..cd9fcb1 100644 --- a/arch/arm/mach-highbank/Kconfig +++ b/arch/arm/mach-highbank/Kconfig @@ -12,6 +12,7 @@ config ARCH_HIGHBANK select CPU_V7 select GENERIC_CLOCKEVENTS select HAVE_ARM_SCU + select HAVE_ARM_TWD if LOCAL_TIMERS select HAVE_SMP select MAILBOX select PL320_MBOX diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index 4c9c6f9..2cc0dbd 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig @@ -811,7 +811,8 @@ config SOC_IMX6Q select ARM_GIC select COMMON_CLK select CPU_V7 - select HAVE_ARM_SCU + select HAVE_ARM_SCU if SMP + select HAVE_ARM_TWD if LOCAL_TIMERS select HAVE_CAN_FLEXCAN if CAN select HAVE_IMX_GPC select HAVE_IMX_MMDC diff --git a/arch/arm/mach-msm/Kconfig b/arch/arm/mach-msm/Kconfig index b619085..fceb093 100644 --- a/arch/arm/mach-msm/Kconfig +++ b/arch/arm/mach-msm/Kconfig @@ -44,10 +44,10 @@ endchoice config ARCH_MSM8X60 bool "MSM8X60" - select ARCH_MSM_SCORPIONMP select ARM_GIC select CPU_V7 select GPIO_MSM_V2 + select HAVE_SMP select MSM_GPIOMUX select MSM_SCM if SMP select MSM_V2_TLMM @@ -55,9 +55,9 @@ config ARCH_MSM8X60 config ARCH_MSM8960 bool "MSM8960" - select ARCH_MSM_SCORPIONMP select ARM_GIC select CPU_V7 + select HAVE_SMP select MSM_GPIOMUX select MSM_SCM if SMP select MSM_V2_TLMM @@ -68,9 +68,6 @@ config MSM_HAS_DEBUG_UART_HS config MSM_SOC_REV_A bool -config ARCH_MSM_SCORPIONMP - bool - select HAVE_SMP config ARCH_MSM_ARM11 bool diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig index 8111cd9..e6724a7 100644 --- a/arch/arm/mach-omap2/Kconfig +++ b/arch/arm/mach-omap2/Kconfig @@ -87,6 +87,8 @@ config ARCH_OMAP4 select ARM_GIC select CACHE_L2X0 select CPU_V7 + select HAVE_ARM_SCU if SMP + select HAVE_ARM_TWD if LOCAL_TIMERS select HAVE_SMP select LOCAL_TIMERS if SMP select OMAP_INTERCONNECT diff --git a/arch/arm/mach-prima2/Kconfig b/arch/arm/mach-prima2/Kconfig index 587c0bd..80ca974 100644 --- a/arch/arm/mach-prima2/Kconfig +++ b/arch/arm/mach-prima2/Kconfig @@ -36,6 +36,7 @@ config ARCH_MARCO default y select ARM_GIC select CPU_V7 + select HAVE_ARM_SCU if SMP select HAVE_SMP select SMP_ON_UP help diff --git a/arch/arm/mach-realview/Kconfig b/arch/arm/mach-realview/Kconfig index 14c1d47..d210c0f 100644 --- a/arch/arm/mach-realview/Kconfig +++ b/arch/arm/mach-realview/Kconfig @@ -12,6 +12,8 @@ config REALVIEW_EB_A9MP bool "Support Multicore Cortex-A9 Tile" depends on MACH_REALVIEW_EB select CPU_V7 + select HAVE_ARM_SCU if SMP + select HAVE_ARM_TWD if LOCAL_TIMERS select HAVE_SMP select MIGHT_HAVE_CACHE_L2X0 help @@ -23,6 +25,8 @@ config REALVIEW_EB_ARM11MP depends on MACH_REALVIEW_EB select ARCH_HAS_BARRIERS if SMP select CPU_V6K + select HAVE_ARM_SCU if SMP + select HAVE_ARM_TWD if LOCAL_TIMERS select HAVE_SMP select MIGHT_HAVE_CACHE_L2X0 help @@ -43,6 +47,8 @@ config MACH_REALVIEW_PB11MP select ARCH_HAS_BARRIERS if SMP select ARM_GIC select CPU_V6K + select HAVE_ARM_SCU if SMP + select HAVE_ARM_TWD if LOCAL_TIMERS select HAVE_PATA_PLATFORM select HAVE_SMP select MIGHT_HAVE_CACHE_L2X0 @@ -85,6 +91,8 @@ config MACH_REALVIEW_PBX bool "Support RealView(R) Platform Baseboard Explore" select ARCH_SPARSEMEM_ENABLE if CPU_V7 && !REALVIEW_HIGH_PHYS_OFFSET select ARM_GIC + select HAVE_ARM_SCU if SMP + select HAVE_ARM_TWD if LOCAL_TIMERS select HAVE_PATA_PLATFORM select HAVE_SMP select MIGHT_HAVE_CACHE_L2X0 diff --git a/arch/arm/mach-spear/Kconfig b/arch/arm/mach-spear/Kconfig index 4c52ee2..716522a 100644 --- a/arch/arm/mach-spear/Kconfig +++ b/arch/arm/mach-spear/Kconfig @@ -22,6 +22,8 @@ config ARCH_SPEAR13XX select ARM_GIC select CPU_V7 select GPIO_SPEAR_SPICS + select HAVE_ARM_SCU if SMP + select HAVE_ARM_TWD if LOCAL_TIMERS select HAVE_SMP select MIGHT_HAVE_CACHE_L2X0 select PINCTRL diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig index df99ee9..597e76b 100644 --- a/arch/arm/mach-tegra/Kconfig +++ b/arch/arm/mach-tegra/Kconfig @@ -7,6 +7,8 @@ config ARCH_TEGRA select CLKSRC_OF select COMMON_CLK select GENERIC_CLOCKEVENTS + select HAVE_ARM_SCU if SMP + select HAVE_ARM_TWD if LOCAL_TIMERS select HAVE_CLK select HAVE_SMP select MIGHT_HAVE_CACHE_L2X0 diff --git a/arch/arm/mach-ux500/Kconfig b/arch/arm/mach-ux500/Kconfig index eeea3bf..f66d7de 100644 --- a/arch/arm/mach-ux500/Kconfig +++ b/arch/arm/mach-ux500/Kconfig @@ -7,6 +7,8 @@ config ARCH_U8500 select CLKDEV_LOOKUP select CPU_V7 select GENERIC_CLOCKEVENTS + select HAVE_ARM_SCU if SMP + select HAVE_ARM_TWD if LOCAL_TIMERS select HAVE_SMP select MIGHT_HAVE_CACHE_L2X0 help diff --git a/arch/arm/mach-vexpress/Kconfig b/arch/arm/mach-vexpress/Kconfig index 52d315b..5e3a2d3 100644 --- a/arch/arm/mach-vexpress/Kconfig +++ b/arch/arm/mach-vexpress/Kconfig @@ -9,6 +9,8 @@ config ARCH_VEXPRESS select COMMON_CLK_VERSATILE select CPU_V7 select GENERIC_CLOCKEVENTS + select HAVE_ARM_SCU if SMP + select HAVE_ARM_TWD if LOCAL_TIMERS select HAVE_CLK select HAVE_PATA_PLATFORM select HAVE_SMP diff --git a/arch/arm/mach-zynq/Kconfig b/arch/arm/mach-zynq/Kconfig index adb6c0e..138b589 100644 --- a/arch/arm/mach-zynq/Kconfig +++ b/arch/arm/mach-zynq/Kconfig @@ -5,6 +5,8 @@ config ARCH_ZYNQ select COMMON_CLK select CPU_V7 select GENERIC_CLOCKEVENTS + select HAVE_ARM_SCU if SMP + select HAVE_ARM_TWD if LOCAL_TIMERS select ICST select MIGHT_HAVE_CACHE_L2X0 select USE_OF -- cgit v1.1 From 408e713545ca0bebe6034935c65e7e95c70d253b Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Tue, 9 Apr 2013 21:58:38 +0200 Subject: ARM: tegra: build assembly files with -march=armv7-a The tegra assembly files are written for ARMv7 and are not compatible with ARMv6, which leads to build warnings when compiling a dual ARMv6/v7 kernel. Since this code is only ever run on Tegra ARMv7 hardware, we can tell the assembler which architecture level to use. Signed-off-by: Arnd Bergmann --- arch/arm/mach-tegra/Makefile | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile index e40326d..bfc5b07 100644 --- a/arch/arm/mach-tegra/Makefile +++ b/arch/arm/mach-tegra/Makefile @@ -1,3 +1,5 @@ +asflags-y += -march=armv7-a + obj-y += common.o obj-y += io.o obj-y += irq.o -- cgit v1.1 From b4cf27f7735f9e5d80f3e79fcf355ced15461219 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Thu, 11 Apr 2013 23:13:27 +0200 Subject: ARM: exynos: introduce EXYNOS_ATAGS symbol As a preparation for multiplatform support, this introduces a new Kconfig symbol to split the ATAGS based EXYNOS platforms from the DT based ones. Turning off CONFIG_EXYNOS_ATAGS disables all platforms that are not yet converted to DT, and we can have code that relies on DT checking for this symbol being disabled. Signed-off-by: Arnd Bergmann --- arch/arm/mach-exynos/Kconfig | 15 +++++++++++++++ 1 file changed, 15 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig index 70f94c8..d8c251b 100644 --- a/arch/arm/mach-exynos/Kconfig +++ b/arch/arm/mach-exynos/Kconfig @@ -85,6 +85,19 @@ config EXYNOS4_MCT help Use MCT (Multi Core Timer) as kernel timers +config EXYNOS_ATAGS + bool "ATAGS based boot for EXYNOS (deprecated)" + depends on !ARCH_MULTIPLATFORM + depends on ATAGS + default y + help + The EXYNOS platform is moving towards being completely probed + through device tree. This enables support for board files using + the traditional ATAGS boot format. + Note that this option is not available for multiplatform builds. + +if EXYNOS_ATAGS + config EXYNOS_DEV_DMA bool help @@ -400,6 +413,8 @@ config MACH_SMDK4412 Machine support for Samsung SMDK4412 endif +endif + comment "Flattened Device Tree based board for EXYNOS SoCs" config MACH_EXYNOS4_DT -- cgit v1.1 From 7ba8022fc3a1d2434c1f038f022c5d69026319ca Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Tue, 5 Mar 2013 11:28:29 +0100 Subject: ARM: exynos: prepare for sparse IRQ When we enable CONFIG_SPARSE_IRQ, we have to set the value of NR_IRQS in the machine_desc for legacy IRQ domains, and any file referring to the number of interrupts or a specific number must include the mach/irqs.h header file explicitly. Signed-off-by: Arnd Bergmann --- arch/arm/mach-exynos/dev-uart.c | 1 + arch/arm/mach-exynos/include/mach/irqs.h | 5 ++++- arch/arm/mach-exynos/mach-armlex4210.c | 1 + arch/arm/mach-exynos/mach-nuri.c | 1 + arch/arm/mach-exynos/mach-origen.c | 1 + arch/arm/mach-exynos/mach-smdk4x12.c | 1 + arch/arm/mach-exynos/mach-smdkv310.c | 1 + arch/arm/plat-samsung/irq-vic-timer.c | 1 + arch/arm/plat-samsung/pm.c | 1 + arch/arm/plat-samsung/s5p-irq.c | 1 + 10 files changed, 13 insertions(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-exynos/dev-uart.c b/arch/arm/mach-exynos/dev-uart.c index 7c42f4b..c48aff0 100644 --- a/arch/arm/mach-exynos/dev-uart.c +++ b/arch/arm/mach-exynos/dev-uart.c @@ -20,6 +20,7 @@ #include #include #include +#include #include diff --git a/arch/arm/mach-exynos/include/mach/irqs.h b/arch/arm/mach-exynos/include/mach/irqs.h index 1f4dc35..8bd5dde 100644 --- a/arch/arm/mach-exynos/include/mach/irqs.h +++ b/arch/arm/mach-exynos/include/mach/irqs.h @@ -466,7 +466,10 @@ #define IRQ_TIMER_BASE (IRQ_GPIO_END + 64) /* Set the default NR_IRQS */ +#define EXYNOS_NR_IRQS (IRQ_TIMER_BASE + IRQ_TIMER_COUNT) -#define NR_IRQS (IRQ_TIMER_BASE + IRQ_TIMER_COUNT) +#ifndef CONFIG_SPARSE_IRQ +#define NR_IRQS EXYNOS_NR_IRQS +#endif #endif /* __ASM_ARCH_IRQS_H */ diff --git a/arch/arm/mach-exynos/mach-armlex4210.c b/arch/arm/mach-exynos/mach-armlex4210.c index 685f291..2126f35 100644 --- a/arch/arm/mach-exynos/mach-armlex4210.c +++ b/arch/arm/mach-exynos/mach-armlex4210.c @@ -25,6 +25,7 @@ #include #include +#include #include #include "common.h" diff --git a/arch/arm/mach-exynos/mach-nuri.c b/arch/arm/mach-exynos/mach-nuri.c index 1ea7973..ab920e3 100644 --- a/arch/arm/mach-exynos/mach-nuri.c +++ b/arch/arm/mach-exynos/mach-nuri.c @@ -53,6 +53,7 @@ #include #include +#include #include #include "common.h" diff --git a/arch/arm/mach-exynos/mach-origen.c b/arch/arm/mach-exynos/mach-origen.c index 579d2d1..f23ce401 100644 --- a/arch/arm/mach-exynos/mach-origen.c +++ b/arch/arm/mach-exynos/mach-origen.c @@ -46,6 +46,7 @@ #include #include +#include #include #include "common.h" diff --git a/arch/arm/mach-exynos/mach-smdk4x12.c b/arch/arm/mach-exynos/mach-smdk4x12.c index fe61496..5df9123 100644 --- a/arch/arm/mach-exynos/mach-smdk4x12.c +++ b/arch/arm/mach-exynos/mach-smdk4x12.c @@ -39,6 +39,7 @@ #include #include +#include #include #include diff --git a/arch/arm/mach-exynos/mach-smdkv310.c b/arch/arm/mach-exynos/mach-smdkv310.c index d716729..9a1d359 100644 --- a/arch/arm/mach-exynos/mach-smdkv310.c +++ b/arch/arm/mach-exynos/mach-smdkv310.c @@ -43,6 +43,7 @@ #include #include +#include #include #include diff --git a/arch/arm/plat-samsung/irq-vic-timer.c b/arch/arm/plat-samsung/irq-vic-timer.c index f980cf3..1113066 100644 --- a/arch/arm/plat-samsung/irq-vic-timer.c +++ b/arch/arm/plat-samsung/irq-vic-timer.c @@ -19,6 +19,7 @@ #include #include +#include #include #include #include diff --git a/arch/arm/plat-samsung/pm.c b/arch/arm/plat-samsung/pm.c index 002b147..53210ec 100644 --- a/arch/arm/plat-samsung/pm.c +++ b/arch/arm/plat-samsung/pm.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include diff --git a/arch/arm/plat-samsung/s5p-irq.c b/arch/arm/plat-samsung/s5p-irq.c index 103e371..ff1a760 100644 --- a/arch/arm/plat-samsung/s5p-irq.c +++ b/arch/arm/plat-samsung/s5p-irq.c @@ -15,6 +15,7 @@ #include #include +#include #include #include #include -- cgit v1.1 From a2e407104769d64e01556d4c335bb6478e1e7f3c Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Mon, 4 Mar 2013 18:03:10 +0100 Subject: ARM: exynos: move debug-macro.S to include/debug/ The move is necessary to support early debug output on exynos with multiplatform configurations. This implies also moving the plat/debug-macro.S file, but we are leaving the remaining users of that file in place, to avoid adding large numbers of extra configuration options to Kconfig.debug Signed-off-by: Arnd Bergmann --- arch/arm/Kconfig.debug | 8 +++ arch/arm/include/debug/exynos.S | 39 +++++++++++ arch/arm/include/debug/samsung.S | 87 ++++++++++++++++++++++++ arch/arm/mach-exynos/include/mach/debug-macro.S | 39 ----------- arch/arm/mach-s3c24xx/include/mach/debug-macro.S | 2 +- arch/arm/mach-s3c64xx/include/mach/debug-macro.S | 2 +- arch/arm/mach-s5p64x0/include/mach/debug-macro.S | 2 +- arch/arm/mach-s5pc100/include/mach/debug-macro.S | 2 +- arch/arm/mach-s5pv210/include/mach/debug-macro.S | 2 +- arch/arm/plat-samsung/include/plat/debug-macro.S | 87 ------------------------ 10 files changed, 139 insertions(+), 131 deletions(-) create mode 100644 arch/arm/include/debug/exynos.S create mode 100644 arch/arm/include/debug/samsung.S delete mode 100644 arch/arm/mach-exynos/include/mach/debug-macro.S delete mode 100644 arch/arm/plat-samsung/include/plat/debug-macro.S (limited to 'arch/arm') diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug index 9b31f43..59ce26a 100644 --- a/arch/arm/Kconfig.debug +++ b/arch/arm/Kconfig.debug @@ -330,6 +330,7 @@ choice config DEBUG_S3C_UART0 depends on PLAT_SAMSUNG + select DEBUG_EXYNOS_UART if ARCH_EXYNOS bool "Use S3C UART 0 for low-level debug" help Say Y here if you want the debug print routines to direct @@ -341,6 +342,7 @@ choice config DEBUG_S3C_UART1 depends on PLAT_SAMSUNG + select DEBUG_EXYNOS_UART if ARCH_EXYNOS bool "Use S3C UART 1 for low-level debug" help Say Y here if you want the debug print routines to direct @@ -352,6 +354,7 @@ choice config DEBUG_S3C_UART2 depends on PLAT_SAMSUNG + select DEBUG_EXYNOS_UART if ARCH_EXYNOS bool "Use S3C UART 2 for low-level debug" help Say Y here if you want the debug print routines to direct @@ -363,6 +366,7 @@ choice config DEBUG_S3C_UART3 depends on PLAT_SAMSUNG && ARCH_EXYNOS + select DEBUG_EXYNOS_UART bool "Use S3C UART 3 for low-level debug" help Say Y here if you want the debug print routines to direct @@ -485,6 +489,9 @@ choice endchoice +config DEBUG_EXYNOS_UART + bool + config DEBUG_IMX_UART_PORT int "i.MX Debug UART Port Selection" if DEBUG_IMX1_UART || \ DEBUG_IMX25_UART || \ @@ -580,6 +587,7 @@ endchoice config DEBUG_LL_INCLUDE string + default "debug/exynos.S" if DEBUG_EXYNOS_UART default "debug/icedcc.S" if DEBUG_ICEDCC default "debug/imx.S" if DEBUG_IMX1_UART || \ DEBUG_IMX25_UART || \ diff --git a/arch/arm/include/debug/exynos.S b/arch/arm/include/debug/exynos.S new file mode 100644 index 0000000..b17fdb7 --- /dev/null +++ b/arch/arm/include/debug/exynos.S @@ -0,0 +1,39 @@ +/* + * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +/* pull in the relevant register and map files. */ + +#define S3C_ADDR_BASE 0xF6000000 +#define S3C_VA_UART S3C_ADDR_BASE + 0x01000000 +#define EXYNOS4_PA_UART 0x13800000 +#define EXYNOS5_PA_UART 0x12C00000 + + /* note, for the boot process to work we have to keep the UART + * virtual address aligned to an 1MiB boundary for the L1 + * mapping the head code makes. We keep the UART virtual address + * aligned and add in the offset when we load the value here. + */ + + .macro addruart, rp, rv, tmp + mrc p15, 0, \tmp, c0, c0, 0 + and \tmp, \tmp, #0xf0 + teq \tmp, #0xf0 @@ A15 + ldreq \rp, =EXYNOS5_PA_UART + movne \rp, #EXYNOS4_PA_UART @@ EXYNOS4 + ldr \rv, =S3C_VA_UART +#if CONFIG_DEBUG_S3C_UART != 0 + add \rp, \rp, #(0x10000 * CONFIG_DEBUG_S3C_UART) + add \rv, \rv, #(0x10000 * CONFIG_DEBUG_S3C_UART) +#endif + .endm + +#define fifo_full fifo_full_s5pv210 +#define fifo_level fifo_level_s5pv210 + +#include diff --git a/arch/arm/include/debug/samsung.S b/arch/arm/include/debug/samsung.S new file mode 100644 index 0000000..f3a9cff --- /dev/null +++ b/arch/arm/include/debug/samsung.S @@ -0,0 +1,87 @@ +/* arch/arm/plat-samsung/include/plat/debug-macro.S + * + * Copyright 2005, 2007 Simtec Electronics + * http://armlinux.simtec.co.uk/ + * Ben Dooks + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include + +/* The S5PV210/S5PC110 implementations are as belows. */ + + .macro fifo_level_s5pv210 rd, rx + ldr \rd, [\rx, # S3C2410_UFSTAT] + and \rd, \rd, #S5PV210_UFSTAT_TXMASK + .endm + + .macro fifo_full_s5pv210 rd, rx + ldr \rd, [\rx, # S3C2410_UFSTAT] + tst \rd, #S5PV210_UFSTAT_TXFULL + .endm + +/* The S3C2440 implementations are used by default as they are the + * most widely re-used */ + + .macro fifo_level_s3c2440 rd, rx + ldr \rd, [\rx, # S3C2410_UFSTAT] + and \rd, \rd, #S3C2440_UFSTAT_TXMASK + .endm + +#ifndef fifo_level +#define fifo_level fifo_level_s3c2440 +#endif + + .macro fifo_full_s3c2440 rd, rx + ldr \rd, [\rx, # S3C2410_UFSTAT] + tst \rd, #S3C2440_UFSTAT_TXFULL + .endm + +#ifndef fifo_full +#define fifo_full fifo_full_s3c2440 +#endif + + .macro senduart,rd,rx + strb \rd, [\rx, # S3C2410_UTXH] + .endm + + .macro busyuart, rd, rx + ldr \rd, [\rx, # S3C2410_UFCON] + tst \rd, #S3C2410_UFCON_FIFOMODE @ fifo enabled? + beq 1001f @ + @ FIFO enabled... +1003: + fifo_full \rd, \rx + bne 1003b + b 1002f + +1001: + @ busy waiting for non fifo + ldr \rd, [\rx, # S3C2410_UTRSTAT] + tst \rd, #S3C2410_UTRSTAT_TXFE + beq 1001b + +1002: @ exit busyuart + .endm + + .macro waituart,rd,rx + ldr \rd, [\rx, # S3C2410_UFCON] + tst \rd, #S3C2410_UFCON_FIFOMODE @ fifo enabled? + beq 1001f @ + @ FIFO enabled... +1003: + fifo_level \rd, \rx + teq \rd, #0 + bne 1003b + b 1002f +1001: + @ idle waiting for non fifo + ldr \rd, [\rx, # S3C2410_UTRSTAT] + tst \rd, #S3C2410_UTRSTAT_TXFE + beq 1001b + +1002: @ exit busyuart + .endm diff --git a/arch/arm/mach-exynos/include/mach/debug-macro.S b/arch/arm/mach-exynos/include/mach/debug-macro.S deleted file mode 100644 index e0c86ea..0000000 --- a/arch/arm/mach-exynos/include/mach/debug-macro.S +++ /dev/null @@ -1,39 +0,0 @@ -/* linux/arch/arm/mach-exynos4/include/mach/debug-macro.S - * - * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * Based on arch/arm/mach-s3c6400/include/mach/debug-macro.S - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -/* pull in the relevant register and map files. */ - -#include - - /* note, for the boot process to work we have to keep the UART - * virtual address aligned to an 1MiB boundary for the L1 - * mapping the head code makes. We keep the UART virtual address - * aligned and add in the offset when we load the value here. - */ - - .macro addruart, rp, rv, tmp - mrc p15, 0, \tmp, c0, c0, 0 - and \tmp, \tmp, #0xf0 - teq \tmp, #0xf0 @@ A15 - ldreq \rp, =EXYNOS5_PA_UART - movne \rp, #EXYNOS4_PA_UART @@ EXYNOS4 - ldr \rv, =S3C_VA_UART -#if CONFIG_DEBUG_S3C_UART != 0 - add \rp, \rp, #(0x10000 * CONFIG_DEBUG_S3C_UART) - add \rv, \rv, #(0x10000 * CONFIG_DEBUG_S3C_UART) -#endif - .endm - -#define fifo_full fifo_full_s5pv210 -#define fifo_level fifo_level_s5pv210 - -#include diff --git a/arch/arm/mach-s3c24xx/include/mach/debug-macro.S b/arch/arm/mach-s3c24xx/include/mach/debug-macro.S index 13ed33c..2558952 100644 --- a/arch/arm/mach-s3c24xx/include/mach/debug-macro.S +++ b/arch/arm/mach-s3c24xx/include/mach/debug-macro.S @@ -98,4 +98,4 @@ /* include the reset of the code which will do the work */ -#include +#include diff --git a/arch/arm/mach-s3c64xx/include/mach/debug-macro.S b/arch/arm/mach-s3c64xx/include/mach/debug-macro.S index c0c076a..dd9ccca 100644 --- a/arch/arm/mach-s3c64xx/include/mach/debug-macro.S +++ b/arch/arm/mach-s3c64xx/include/mach/debug-macro.S @@ -35,4 +35,4 @@ * will be fine with us. */ -#include +#include diff --git a/arch/arm/mach-s5p64x0/include/mach/debug-macro.S b/arch/arm/mach-s5p64x0/include/mach/debug-macro.S index e80ba3c..5e2916f 100644 --- a/arch/arm/mach-s5p64x0/include/mach/debug-macro.S +++ b/arch/arm/mach-s5p64x0/include/mach/debug-macro.S @@ -30,4 +30,4 @@ #endif .endm -#include +#include diff --git a/arch/arm/mach-s5pc100/include/mach/debug-macro.S b/arch/arm/mach-s5pc100/include/mach/debug-macro.S index 694f759..66cb7f1 100644 --- a/arch/arm/mach-s5pc100/include/mach/debug-macro.S +++ b/arch/arm/mach-s5pc100/include/mach/debug-macro.S @@ -36,4 +36,4 @@ * will be fine with us. */ -#include +#include diff --git a/arch/arm/mach-s5pv210/include/mach/debug-macro.S b/arch/arm/mach-s5pv210/include/mach/debug-macro.S index 79e5559..80c2199 100644 --- a/arch/arm/mach-s5pv210/include/mach/debug-macro.S +++ b/arch/arm/mach-s5pv210/include/mach/debug-macro.S @@ -38,4 +38,4 @@ * will be fine with us. */ -#include +#include diff --git a/arch/arm/plat-samsung/include/plat/debug-macro.S b/arch/arm/plat-samsung/include/plat/debug-macro.S deleted file mode 100644 index f3a9cff..0000000 --- a/arch/arm/plat-samsung/include/plat/debug-macro.S +++ /dev/null @@ -1,87 +0,0 @@ -/* arch/arm/plat-samsung/include/plat/debug-macro.S - * - * Copyright 2005, 2007 Simtec Electronics - * http://armlinux.simtec.co.uk/ - * Ben Dooks - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include - -/* The S5PV210/S5PC110 implementations are as belows. */ - - .macro fifo_level_s5pv210 rd, rx - ldr \rd, [\rx, # S3C2410_UFSTAT] - and \rd, \rd, #S5PV210_UFSTAT_TXMASK - .endm - - .macro fifo_full_s5pv210 rd, rx - ldr \rd, [\rx, # S3C2410_UFSTAT] - tst \rd, #S5PV210_UFSTAT_TXFULL - .endm - -/* The S3C2440 implementations are used by default as they are the - * most widely re-used */ - - .macro fifo_level_s3c2440 rd, rx - ldr \rd, [\rx, # S3C2410_UFSTAT] - and \rd, \rd, #S3C2440_UFSTAT_TXMASK - .endm - -#ifndef fifo_level -#define fifo_level fifo_level_s3c2440 -#endif - - .macro fifo_full_s3c2440 rd, rx - ldr \rd, [\rx, # S3C2410_UFSTAT] - tst \rd, #S3C2440_UFSTAT_TXFULL - .endm - -#ifndef fifo_full -#define fifo_full fifo_full_s3c2440 -#endif - - .macro senduart,rd,rx - strb \rd, [\rx, # S3C2410_UTXH] - .endm - - .macro busyuart, rd, rx - ldr \rd, [\rx, # S3C2410_UFCON] - tst \rd, #S3C2410_UFCON_FIFOMODE @ fifo enabled? - beq 1001f @ - @ FIFO enabled... -1003: - fifo_full \rd, \rx - bne 1003b - b 1002f - -1001: - @ busy waiting for non fifo - ldr \rd, [\rx, # S3C2410_UTRSTAT] - tst \rd, #S3C2410_UTRSTAT_TXFE - beq 1001b - -1002: @ exit busyuart - .endm - - .macro waituart,rd,rx - ldr \rd, [\rx, # S3C2410_UFCON] - tst \rd, #S3C2410_UFCON_FIFOMODE @ fifo enabled? - beq 1001f @ - @ FIFO enabled... -1003: - fifo_level \rd, \rx - teq \rd, #0 - bne 1003b - b 1002f -1001: - @ idle waiting for non fifo - ldr \rd, [\rx, # S3C2410_UTRSTAT] - tst \rd, #S3C2410_UTRSTAT_TXFE - beq 1001b - -1002: @ exit busyuart - .endm -- cgit v1.1 From f76da510d61a8793c990bee9acc10744ee2b2a8c Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Wed, 10 Apr 2013 14:49:03 +0200 Subject: ARM: samsung: move mfc device definition to s5p-dev-mfc.c For a DT-only build we don't want to compile devs.c, but we do need the mfc device, which is also referenced by the DT based platforms, so move it all into one place. Signed-off-by: Arnd Bergmann --- arch/arm/plat-samsung/devs.c | 45 ------------------------------------- arch/arm/plat-samsung/s5p-dev-mfc.c | 42 +++++++++++++++++++++++++++++++++- 2 files changed, 41 insertions(+), 46 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/plat-samsung/devs.c b/arch/arm/plat-samsung/devs.c index 51afedd..de9ad27 100644 --- a/arch/arm/plat-samsung/devs.c +++ b/arch/arm/plat-samsung/devs.c @@ -878,51 +878,6 @@ void __init s3c24xx_fb_set_platdata(struct s3c2410fb_mach_info *pd) } #endif /* CONFIG_PLAT_S3C24XX */ -/* MFC */ - -#ifdef CONFIG_S5P_DEV_MFC -static struct resource s5p_mfc_resource[] = { - [0] = DEFINE_RES_MEM(S5P_PA_MFC, SZ_64K), - [1] = DEFINE_RES_IRQ(IRQ_MFC), -}; - -struct platform_device s5p_device_mfc = { - .name = "s5p-mfc", - .id = -1, - .num_resources = ARRAY_SIZE(s5p_mfc_resource), - .resource = s5p_mfc_resource, -}; - -/* - * MFC hardware has 2 memory interfaces which are modelled as two separate - * platform devices to let dma-mapping distinguish between them. - * - * MFC parent device (s5p_device_mfc) must be registered before memory - * interface specific devices (s5p_device_mfc_l and s5p_device_mfc_r). - */ - -struct platform_device s5p_device_mfc_l = { - .name = "s5p-mfc-l", - .id = -1, - .dev = { - .parent = &s5p_device_mfc.dev, - .dma_mask = &samsung_device_dma_mask, - .coherent_dma_mask = DMA_BIT_MASK(32), - }, -}; - -struct platform_device s5p_device_mfc_r = { - .name = "s5p-mfc-r", - .id = -1, - .dev = { - .parent = &s5p_device_mfc.dev, - .dma_mask = &samsung_device_dma_mask, - .coherent_dma_mask = DMA_BIT_MASK(32), - }, -}; - -#endif /* CONFIG_S5P_DEV_MFC */ - /* MIPI CSIS */ #ifdef CONFIG_S5P_DEV_CSIS0 diff --git a/arch/arm/plat-samsung/s5p-dev-mfc.c b/arch/arm/plat-samsung/s5p-dev-mfc.c index 5ec104b..a93fb6f 100644 --- a/arch/arm/plat-samsung/s5p-dev-mfc.c +++ b/arch/arm/plat-samsung/s5p-dev-mfc.c @@ -18,10 +18,50 @@ #include #include +#include #include -#include #include +static struct resource s5p_mfc_resource[] = { + [0] = DEFINE_RES_MEM(S5P_PA_MFC, SZ_64K), + [1] = DEFINE_RES_IRQ(IRQ_MFC), +}; + +struct platform_device s5p_device_mfc = { + .name = "s5p-mfc", + .id = -1, + .num_resources = ARRAY_SIZE(s5p_mfc_resource), + .resource = s5p_mfc_resource, +}; + +/* + * MFC hardware has 2 memory interfaces which are modelled as two separate + * platform devices to let dma-mapping distinguish between them. + * + * MFC parent device (s5p_device_mfc) must be registered before memory + * interface specific devices (s5p_device_mfc_l and s5p_device_mfc_r). + */ + +struct platform_device s5p_device_mfc_l = { + .name = "s5p-mfc-l", + .id = -1, + .dev = { + .parent = &s5p_device_mfc.dev, + .dma_mask = &s5p_device_mfc_l.dev.coherent_dma_mask, + .coherent_dma_mask = DMA_BIT_MASK(32), + }, +}; + +struct platform_device s5p_device_mfc_r = { + .name = "s5p-mfc-r", + .id = -1, + .dev = { + .parent = &s5p_device_mfc.dev, + .dma_mask = &s5p_device_mfc_r.dev.coherent_dma_mask, + .coherent_dma_mask = DMA_BIT_MASK(32), + }, +}; + struct s5p_mfc_reserved_mem { phys_addr_t base; unsigned long size; -- cgit v1.1 From cc014f3e29e15140e35e14fa194034baee92df2a Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Mon, 4 Mar 2013 18:28:21 +0100 Subject: mmc: sdhci-s3c: remove platform dependencies plat/regs-sdhci.h is not used anywhere but in the sdhci-s3c driver, so it can become a local file there and all other inclusions removed. plat/sdhci.h is used only to define the platform devices, and with the exception of the platform_data structure not needed by the driver, so we can split out the platform_data definition instead and leave the rest to platform code. Signed-off-by: Arnd Bergmann Acked-by: Chris Ball --- arch/arm/mach-exynos/setup-sdhci-gpio.c | 2 +- arch/arm/mach-s5pc100/setup-sdhci-gpio.c | 1 - arch/arm/mach-s5pv210/setup-sdhci-gpio.c | 1 - arch/arm/plat-samsung/include/plat/regs-sdhci.h | 87 ------------------------- arch/arm/plat-samsung/include/plat/sdhci.h | 56 +--------------- 5 files changed, 2 insertions(+), 145 deletions(-) delete mode 100644 arch/arm/plat-samsung/include/plat/regs-sdhci.h (limited to 'arch/arm') diff --git a/arch/arm/mach-exynos/setup-sdhci-gpio.c b/arch/arm/mach-exynos/setup-sdhci-gpio.c index e8d08bf..d5b98c8 100644 --- a/arch/arm/mach-exynos/setup-sdhci-gpio.c +++ b/arch/arm/mach-exynos/setup-sdhci-gpio.c @@ -19,8 +19,8 @@ #include #include +#include #include -#include #include void exynos4_setup_sdhci0_cfg_gpio(struct platform_device *dev, int width) diff --git a/arch/arm/mach-s5pc100/setup-sdhci-gpio.c b/arch/arm/mach-s5pc100/setup-sdhci-gpio.c index 03c02d0..6010c03 100644 --- a/arch/arm/mach-s5pc100/setup-sdhci-gpio.c +++ b/arch/arm/mach-s5pc100/setup-sdhci-gpio.c @@ -19,7 +19,6 @@ #include #include -#include #include void s5pc100_setup_sdhci0_cfg_gpio(struct platform_device *dev, int width) diff --git a/arch/arm/mach-s5pv210/setup-sdhci-gpio.c b/arch/arm/mach-s5pv210/setup-sdhci-gpio.c index 3e3ac05..0512ada 100644 --- a/arch/arm/mach-s5pv210/setup-sdhci-gpio.c +++ b/arch/arm/mach-s5pv210/setup-sdhci-gpio.c @@ -20,7 +20,6 @@ #include #include -#include #include void s5pv210_setup_sdhci0_cfg_gpio(struct platform_device *dev, int width) diff --git a/arch/arm/plat-samsung/include/plat/regs-sdhci.h b/arch/arm/plat-samsung/include/plat/regs-sdhci.h deleted file mode 100644 index e34049ad..0000000 --- a/arch/arm/plat-samsung/include/plat/regs-sdhci.h +++ /dev/null @@ -1,87 +0,0 @@ -/* linux/arch/arm/plat-s3c/include/plat/regs-sdhci.h - * - * Copyright 2008 Openmoko, Inc. - * Copyright 2008 Simtec Electronics - * http://armlinux.simtec.co.uk/ - * Ben Dooks - * - * S3C Platform - SDHCI (HSMMC) register definitions - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#ifndef __PLAT_S3C_SDHCI_REGS_H -#define __PLAT_S3C_SDHCI_REGS_H __FILE__ - -#define S3C_SDHCI_CONTROL2 (0x80) -#define S3C_SDHCI_CONTROL3 (0x84) -#define S3C64XX_SDHCI_CONTROL4 (0x8C) - -#define S3C64XX_SDHCI_CTRL2_ENSTAASYNCCLR (1 << 31) -#define S3C64XX_SDHCI_CTRL2_ENCMDCNFMSK (1 << 30) -#define S3C_SDHCI_CTRL2_CDINVRXD3 (1 << 29) -#define S3C_SDHCI_CTRL2_SLCARDOUT (1 << 28) - -#define S3C_SDHCI_CTRL2_FLTCLKSEL_MASK (0xf << 24) -#define S3C_SDHCI_CTRL2_FLTCLKSEL_SHIFT (24) -#define S3C_SDHCI_CTRL2_FLTCLKSEL(_x) ((_x) << 24) - -#define S3C_SDHCI_CTRL2_LVLDAT_MASK (0xff << 16) -#define S3C_SDHCI_CTRL2_LVLDAT_SHIFT (16) -#define S3C_SDHCI_CTRL2_LVLDAT(_x) ((_x) << 16) - -#define S3C_SDHCI_CTRL2_ENFBCLKTX (1 << 15) -#define S3C_SDHCI_CTRL2_ENFBCLKRX (1 << 14) -#define S3C_SDHCI_CTRL2_SDCDSEL (1 << 13) -#define S3C_SDHCI_CTRL2_SDSIGPC (1 << 12) -#define S3C_SDHCI_CTRL2_ENBUSYCHKTXSTART (1 << 11) - -#define S3C_SDHCI_CTRL2_DFCNT_MASK (0x3 << 9) -#define S3C_SDHCI_CTRL2_DFCNT_SHIFT (9) -#define S3C_SDHCI_CTRL2_DFCNT_NONE (0x0 << 9) -#define S3C_SDHCI_CTRL2_DFCNT_4SDCLK (0x1 << 9) -#define S3C_SDHCI_CTRL2_DFCNT_16SDCLK (0x2 << 9) -#define S3C_SDHCI_CTRL2_DFCNT_64SDCLK (0x3 << 9) - -#define S3C_SDHCI_CTRL2_ENCLKOUTHOLD (1 << 8) -#define S3C_SDHCI_CTRL2_RWAITMODE (1 << 7) -#define S3C_SDHCI_CTRL2_DISBUFRD (1 << 6) -#define S3C_SDHCI_CTRL2_SELBASECLK_MASK (0x3 << 4) -#define S3C_SDHCI_CTRL2_SELBASECLK_SHIFT (4) -#define S3C_SDHCI_CTRL2_PWRSYNC (1 << 3) -#define S3C_SDHCI_CTRL2_ENCLKOUTMSKCON (1 << 1) -#define S3C_SDHCI_CTRL2_HWINITFIN (1 << 0) - -#define S3C_SDHCI_CTRL3_FCSEL3 (1 << 31) -#define S3C_SDHCI_CTRL3_FCSEL2 (1 << 23) -#define S3C_SDHCI_CTRL3_FCSEL1 (1 << 15) -#define S3C_SDHCI_CTRL3_FCSEL0 (1 << 7) - -#define S3C_SDHCI_CTRL3_FIA3_MASK (0x7f << 24) -#define S3C_SDHCI_CTRL3_FIA3_SHIFT (24) -#define S3C_SDHCI_CTRL3_FIA3(_x) ((_x) << 24) - -#define S3C_SDHCI_CTRL3_FIA2_MASK (0x7f << 16) -#define S3C_SDHCI_CTRL3_FIA2_SHIFT (16) -#define S3C_SDHCI_CTRL3_FIA2(_x) ((_x) << 16) - -#define S3C_SDHCI_CTRL3_FIA1_MASK (0x7f << 8) -#define S3C_SDHCI_CTRL3_FIA1_SHIFT (8) -#define S3C_SDHCI_CTRL3_FIA1(_x) ((_x) << 8) - -#define S3C_SDHCI_CTRL3_FIA0_MASK (0x7f << 0) -#define S3C_SDHCI_CTRL3_FIA0_SHIFT (0) -#define S3C_SDHCI_CTRL3_FIA0(_x) ((_x) << 0) - -#define S3C64XX_SDHCI_CONTROL4_DRIVE_MASK (0x3 << 16) -#define S3C64XX_SDHCI_CONTROL4_DRIVE_SHIFT (16) -#define S3C64XX_SDHCI_CONTROL4_DRIVE_2mA (0x0 << 16) -#define S3C64XX_SDHCI_CONTROL4_DRIVE_4mA (0x1 << 16) -#define S3C64XX_SDHCI_CONTROL4_DRIVE_7mA (0x2 << 16) -#define S3C64XX_SDHCI_CONTROL4_DRIVE_9mA (0x3 << 16) - -#define S3C64XX_SDHCI_CONTROL4_BUSY (1) - -#endif /* __PLAT_S3C_SDHCI_REGS_H */ diff --git a/arch/arm/plat-samsung/include/plat/sdhci.h b/arch/arm/plat-samsung/include/plat/sdhci.h index 9b87f38..1e0aab0 100644 --- a/arch/arm/plat-samsung/include/plat/sdhci.h +++ b/arch/arm/plat-samsung/include/plat/sdhci.h @@ -18,62 +18,9 @@ #ifndef __PLAT_S3C_SDHCI_H #define __PLAT_S3C_SDHCI_H __FILE__ +#include #include -struct platform_device; -struct mmc_host; -struct mmc_card; -struct mmc_ios; - -enum cd_types { - S3C_SDHCI_CD_INTERNAL, /* use mmc internal CD line */ - S3C_SDHCI_CD_EXTERNAL, /* use external callback */ - S3C_SDHCI_CD_GPIO, /* use external gpio pin for CD line */ - S3C_SDHCI_CD_NONE, /* no CD line, use polling to detect card */ - S3C_SDHCI_CD_PERMANENT, /* no CD line, card permanently wired to host */ -}; - -/** - * struct s3c_sdhci_platdata() - Platform device data for Samsung SDHCI - * @max_width: The maximum number of data bits supported. - * @host_caps: Standard MMC host capabilities bit field. - * @host_caps2: The second standard MMC host capabilities bit field. - * @cd_type: Type of Card Detection method (see cd_types enum above) - * @ext_cd_init: Initialize external card detect subsystem. Called on - * sdhci-s3c driver probe when cd_type == S3C_SDHCI_CD_EXTERNAL. - * notify_func argument is a callback to the sdhci-s3c driver - * that triggers the card detection event. Callback arguments: - * dev is pointer to platform device of the host controller, - * state is new state of the card (0 - removed, 1 - inserted). - * @ext_cd_cleanup: Cleanup external card detect subsystem. Called on - * sdhci-s3c driver remove when cd_type == S3C_SDHCI_CD_EXTERNAL. - * notify_func argument is the same callback as for ext_cd_init. - * @ext_cd_gpio: gpio pin used for external CD line, valid only if - * cd_type == S3C_SDHCI_CD_GPIO - * @ext_cd_gpio_invert: invert values for external CD gpio line - * @cfg_gpio: Configure the GPIO for a specific card bit-width - * - * Initialisation data specific to either the machine or the platform - * for the device driver to use or call-back when configuring gpio or - * card speed information. -*/ -struct s3c_sdhci_platdata { - unsigned int max_width; - unsigned int host_caps; - unsigned int host_caps2; - unsigned int pm_caps; - enum cd_types cd_type; - - int ext_cd_gpio; - bool ext_cd_gpio_invert; - int (*ext_cd_init)(void (*notify_func)(struct platform_device *, - int state)); - int (*ext_cd_cleanup)(void (*notify_func)(struct platform_device *, - int state)); - - void (*cfg_gpio)(struct platform_device *dev, int width); -}; - /* s3c_sdhci_set_platdata() - common helper for setting SDHCI platform data * @pd: The default platform data for this device. * @set: Pointer to the platform data to fill in. @@ -378,5 +325,4 @@ static inline void s3c_sdhci_setname(int id, char *name) break; } } - #endif /* __PLAT_S3C_SDHCI_H */ -- cgit v1.1 From 93115b7fa8f4090ecbf247b29992a9454d4f9c22 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Tue, 5 Mar 2013 12:14:17 +0100 Subject: mtd: onenand/samsung: make regs-onenand.h file local Nothing uses the NAND register definitions other than the actual driver, so we can move the header file into the same local directory, which lets us build it in a multiplatform configuration. Signed-off-by: Arnd Bergmann Acked-by: Kyungmin Park Cc: linux-mtd@lists.infradead.org Cc: David Woodhouse --- arch/arm/plat-samsung/include/plat/regs-onenand.h | 63 ----------------------- 1 file changed, 63 deletions(-) delete mode 100644 arch/arm/plat-samsung/include/plat/regs-onenand.h (limited to 'arch/arm') diff --git a/arch/arm/plat-samsung/include/plat/regs-onenand.h b/arch/arm/plat-samsung/include/plat/regs-onenand.h deleted file mode 100644 index 930ea8b..0000000 --- a/arch/arm/plat-samsung/include/plat/regs-onenand.h +++ /dev/null @@ -1,63 +0,0 @@ -/* - * linux/arch/arm/plat-s3c/include/plat/regs-onenand.h - * - * Copyright (C) 2008-2010 Samsung Electronics - * Kyungmin Park - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#ifndef __SAMSUNG_ONENAND_H__ -#define __SAMSUNG_ONENAND_H__ - -#include - -/* - * OneNAND Controller - */ -#define MEM_CFG_OFFSET 0x0000 -#define BURST_LEN_OFFSET 0x0010 -#define MEM_RESET_OFFSET 0x0020 -#define INT_ERR_STAT_OFFSET 0x0030 -#define INT_ERR_MASK_OFFSET 0x0040 -#define INT_ERR_ACK_OFFSET 0x0050 -#define ECC_ERR_STAT_OFFSET 0x0060 -#define MANUFACT_ID_OFFSET 0x0070 -#define DEVICE_ID_OFFSET 0x0080 -#define DATA_BUF_SIZE_OFFSET 0x0090 -#define BOOT_BUF_SIZE_OFFSET 0x00A0 -#define BUF_AMOUNT_OFFSET 0x00B0 -#define TECH_OFFSET 0x00C0 -#define FBA_WIDTH_OFFSET 0x00D0 -#define FPA_WIDTH_OFFSET 0x00E0 -#define FSA_WIDTH_OFFSET 0x00F0 -#define TRANS_SPARE_OFFSET 0x0140 -#define DBS_DFS_WIDTH_OFFSET 0x0160 -#define INT_PIN_ENABLE_OFFSET 0x01A0 -#define ACC_CLOCK_OFFSET 0x01C0 -#define FLASH_VER_ID_OFFSET 0x01F0 -#define FLASH_AUX_CNTRL_OFFSET 0x0300 /* s3c64xx only */ - -#define ONENAND_MEM_RESET_HOT 0x3 -#define ONENAND_MEM_RESET_COLD 0x2 -#define ONENAND_MEM_RESET_WARM 0x1 - -#define CACHE_OP_ERR (1 << 13) -#define RST_CMP (1 << 12) -#define RDY_ACT (1 << 11) -#define INT_ACT (1 << 10) -#define UNSUP_CMD (1 << 9) -#define LOCKED_BLK (1 << 8) -#define BLK_RW_CMP (1 << 7) -#define ERS_CMP (1 << 6) -#define PGM_CMP (1 << 5) -#define LOAD_CMP (1 << 4) -#define ERS_FAIL (1 << 3) -#define PGM_FAIL (1 << 2) -#define INT_TO (1 << 1) -#define LD_FAIL_ECC_ERR (1 << 0) - -#define TSRF (1 << 0) - -#endif -- cgit v1.1 From b9d7c5d3f48fb9582458ce014baa66c1e16d9be6 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Tue, 5 Mar 2013 12:04:37 +0100 Subject: rtc: s3c: make header file local Nothing outside of the rtc driver includes plat/regs-rtc.h, so we can simply move the file into the same directory, which allows us to build the file as platform-independent code. Signed-off-by: Arnd Bergmann Cc: rtc-linux@googlegroups.com Cc: Alessandro Zummo --- arch/arm/plat-samsung/include/plat/regs-rtc.h | 71 --------------------------- 1 file changed, 71 deletions(-) delete mode 100644 arch/arm/plat-samsung/include/plat/regs-rtc.h (limited to 'arch/arm') diff --git a/arch/arm/plat-samsung/include/plat/regs-rtc.h b/arch/arm/plat-samsung/include/plat/regs-rtc.h deleted file mode 100644 index 0f8263e..0000000 --- a/arch/arm/plat-samsung/include/plat/regs-rtc.h +++ /dev/null @@ -1,71 +0,0 @@ -/* arch/arm/mach-s3c2410/include/mach/regs-rtc.h - * - * Copyright (c) 2003 Simtec Electronics - * http://www.simtec.co.uk/products/SWLINUX/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * S3C2410 Internal RTC register definition -*/ - -#ifndef __ASM_ARCH_REGS_RTC_H -#define __ASM_ARCH_REGS_RTC_H __FILE__ - -#define S3C2410_RTCREG(x) (x) -#define S3C2410_INTP S3C2410_RTCREG(0x30) -#define S3C2410_INTP_ALM (1 << 1) -#define S3C2410_INTP_TIC (1 << 0) - -#define S3C2410_RTCCON S3C2410_RTCREG(0x40) -#define S3C2410_RTCCON_RTCEN (1 << 0) -#define S3C2410_RTCCON_CNTSEL (1 << 2) -#define S3C2410_RTCCON_CLKRST (1 << 3) -#define S3C2443_RTCCON_TICSEL (1 << 4) -#define S3C64XX_RTCCON_TICEN (1 << 8) - -#define S3C2410_TICNT S3C2410_RTCREG(0x44) -#define S3C2410_TICNT_ENABLE (1 << 7) - -/* S3C2443: tick count is 15 bit wide - * TICNT[6:0] contains upper 7 bits - * TICNT1[7:0] contains lower 8 bits - */ -#define S3C2443_TICNT_PART(x) ((x & 0x7f00) >> 8) -#define S3C2443_TICNT1 S3C2410_RTCREG(0x4C) -#define S3C2443_TICNT1_PART(x) (x & 0xff) - -/* S3C2416: tick count is 32 bit wide - * TICNT[6:0] contains bits [14:8] - * TICNT1[7:0] contains lower 8 bits - * TICNT2[16:0] contains upper 17 bits - */ -#define S3C2416_TICNT2 S3C2410_RTCREG(0x48) -#define S3C2416_TICNT2_PART(x) ((x & 0xffff8000) >> 15) - -#define S3C2410_RTCALM S3C2410_RTCREG(0x50) -#define S3C2410_RTCALM_ALMEN (1 << 6) -#define S3C2410_RTCALM_YEAREN (1 << 5) -#define S3C2410_RTCALM_MONEN (1 << 4) -#define S3C2410_RTCALM_DAYEN (1 << 3) -#define S3C2410_RTCALM_HOUREN (1 << 2) -#define S3C2410_RTCALM_MINEN (1 << 1) -#define S3C2410_RTCALM_SECEN (1 << 0) - -#define S3C2410_ALMSEC S3C2410_RTCREG(0x54) -#define S3C2410_ALMMIN S3C2410_RTCREG(0x58) -#define S3C2410_ALMHOUR S3C2410_RTCREG(0x5c) - -#define S3C2410_ALMDATE S3C2410_RTCREG(0x60) -#define S3C2410_ALMMON S3C2410_RTCREG(0x64) -#define S3C2410_ALMYEAR S3C2410_RTCREG(0x68) - -#define S3C2410_RTCSEC S3C2410_RTCREG(0x70) -#define S3C2410_RTCMIN S3C2410_RTCREG(0x74) -#define S3C2410_RTCHOUR S3C2410_RTCREG(0x78) -#define S3C2410_RTCDATE S3C2410_RTCREG(0x7c) -#define S3C2410_RTCMON S3C2410_RTCREG(0x84) -#define S3C2410_RTCYEAR S3C2410_RTCREG(0x88) - -#endif /* __ASM_ARCH_REGS_RTC_H */ -- cgit v1.1 From bd51de53e1be9896d815bbea30560262216d4616 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Wed, 10 Apr 2013 14:57:15 +0200 Subject: ARM: exynos: enable multiplatform support This makes it possible to enable the exynos platform as part of a multiplatform kernel, in addition to keeping the single-platform exynos support. The multiplatform variant has a number of limitations at the moment: * It only supports DT-enabled machines. This is not a problem in the long run, as non-DT machines for exynos are going away. The main problem here is that the gpio code and the exynos_eint irqchip are not multiplatform capable but still required for ATAGS based boot. * The watchdog driver is still missing a conversion. * sparsemem and memory_holes are currently not supported in multiplatform. The the multiplatform aware ARCH_EXYNOS Kconfig symbol is disabled for now, as dependent patches are still pending in other subsystem trees. We will enable it once everything comes together. Signed-off-by: Arnd Bergmann --- arch/arm/Kconfig | 9 +-------- arch/arm/configs/exynos4_defconfig | 2 +- arch/arm/mach-exynos/Kconfig | 25 +++++++++++++++++++++---- arch/arm/mach-exynos/Makefile | 5 +++-- arch/arm/mach-exynos/common.c | 6 ++++++ arch/arm/plat-samsung/Kconfig | 7 ++++++- arch/arm/plat-samsung/Makefile | 8 ++++++-- arch/arm/plat-samsung/include/plat/pm.h | 5 +++++ 8 files changed, 49 insertions(+), 18 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 13b7394..b375a94 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -853,18 +853,11 @@ config ARCH_S5PV210 help Samsung S5PV210/S5PC110 series based systems -config ARCH_EXYNOS +config ARCH_EXYNOS_SINGLE bool "Samsung EXYNOS" - select ARCH_HAS_CPUFREQ select ARCH_HAS_HOLES_MEMORYMODEL select ARCH_SPARSEMEM_ENABLE - select CLKDEV_LOOKUP - select CPU_V7 - select GENERIC_CLOCKEVENTS - select HAVE_CLK - select HAVE_S3C2410_I2C if I2C select HAVE_S3C2410_WATCHDOG if WATCHDOG - select HAVE_S3C_RTC if RTC_CLASS select NEED_MACH_GPIO_H select NEED_MACH_MEMORY_H help diff --git a/arch/arm/configs/exynos4_defconfig b/arch/arm/configs/exynos4_defconfig index bffe68e..ae90a0f 100644 --- a/arch/arm/configs/exynos4_defconfig +++ b/arch/arm/configs/exynos4_defconfig @@ -4,7 +4,7 @@ CONFIG_KALLSYMS_ALL=y CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y # CONFIG_BLK_DEV_BSG is not set -CONFIG_ARCH_EXYNOS=y +CONFIG_ARCH_EXYNOS_SINGLE=y CONFIG_S3C_LOWLEVEL_UART_PORT=1 CONFIG_MACH_SMDKC210=y CONFIG_MACH_ARMLEX4210=y diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig index d8c251b..1d69c62 100644 --- a/arch/arm/mach-exynos/Kconfig +++ b/arch/arm/mach-exynos/Kconfig @@ -7,6 +7,20 @@ # Configuration options for the EXYNOS4 +config ARCH_EXYNOS + # TODO: make this visible after all drivers are converted + bool "Samsung EXYNOS" if ARCH_MULTI_V7 && BROKEN + default ARCH_EXYNOS_SINGLE + select ARCH_HAS_CPUFREQ + select CLKDEV_LOOKUP + select CPU_V7 + select GENERIC_CLOCKEVENTS + select HAVE_CLK + select HAVE_S3C2410_I2C if I2C + select HAVE_S3C_RTC if RTC_CLASS + help + Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5) + if ARCH_EXYNOS menu "SAMSUNG EXYNOS SoCs Support" @@ -19,6 +33,9 @@ config ARCH_EXYNOS4 help Samsung EXYNOS4 SoCs based systems +config ARCH_EXYNOS4_SINGLE + def_bool ARCH_EXYNOS4 && ARCH_EXYNOS_SINGLE + config ARCH_EXYNOS5 bool "SAMSUNG EXYNOS5" select HAVE_SMP @@ -35,7 +52,7 @@ config CPU_EXYNOS4210 select PM_GENERIC_DOMAINS select S5P_PM if PM select S5P_SLEEP if PM - select SAMSUNG_DMADEV + select SAMSUNG_DMADEV if ARCH_EXYNOS_SINGLE help Enable EXYNOS4210 CPU support @@ -45,7 +62,7 @@ config SOC_EXYNOS4212 depends on ARCH_EXYNOS4 select S5P_PM if PM select S5P_SLEEP if PM - select SAMSUNG_DMADEV + select SAMSUNG_DMADEV if ARCH_EXYNOS_SINGLE help Enable EXYNOS4212 SoC support @@ -53,7 +70,7 @@ config SOC_EXYNOS4412 bool "SAMSUNG EXYNOS4412" default y depends on ARCH_EXYNOS4 - select SAMSUNG_DMADEV + select SAMSUNG_DMADEV if ARCH_EXYNOS_SINGLE help Enable EXYNOS4412 SoC support @@ -64,7 +81,7 @@ config SOC_EXYNOS5250 select S5P_PM if PM select S5P_SLEEP if PM select S5P_DEV_MFC - select SAMSUNG_DMADEV + select SAMSUNG_DMADEV if ARCH_EXYNOS_SINGLE help Enable EXYNOS5250 SoC support diff --git a/arch/arm/mach-exynos/Makefile b/arch/arm/mach-exynos/Makefile index 435757e..57e9124 100644 --- a/arch/arm/mach-exynos/Makefile +++ b/arch/arm/mach-exynos/Makefile @@ -4,6 +4,7 @@ # http://www.samsung.com/ # # Licensed under GPLv2 +ccflags-$(CONFIG_ARCH_MULTIPLATFORM) += -I$(srctree)/$(src)/include -I$(srctree)/arch/arm/plat-samsung/include obj-y := obj-m := @@ -48,12 +49,12 @@ obj-$(CONFIG_MACH_EXYNOS5_DT) += mach-exynos5-dt.o # device support obj-y += dev-uart.o -obj-$(CONFIG_ARCH_EXYNOS4) += dev-audio.o +obj-$(CONFIG_ARCH_EXYNOS4_SINGLE) += dev-audio.o obj-$(CONFIG_EXYNOS4_DEV_AHCI) += dev-ahci.o obj-$(CONFIG_EXYNOS_DEV_DMA) += dma.o obj-$(CONFIG_EXYNOS4_DEV_USB_OHCI) += dev-ohci.o -obj-$(CONFIG_ARCH_EXYNOS) += setup-i2c0.o +obj-$(CONFIG_ARCH_EXYNOS_SINGLE) += setup-i2c0.o obj-$(CONFIG_EXYNOS4_SETUP_FIMC) += setup-fimc.o obj-$(CONFIG_EXYNOS4_SETUP_FIMD0) += setup-fimd0.o obj-$(CONFIG_EXYNOS4_SETUP_I2C1) += setup-i2c1.o diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c index d63d399..83bd3f0 100644 --- a/arch/arm/mach-exynos/common.c +++ b/arch/arm/mach-exynos/common.c @@ -368,6 +368,9 @@ static void __init exynos4_map_io(void) else iotable_init(exynos4_iodesc1, ARRAY_SIZE(exynos4_iodesc1)); + if (!IS_ENABLED(CONFIG_EXYNOS_ATAGS)) + return + /* initialize device information early */ exynos4_default_sdhci0(); exynos4_default_sdhci1(); @@ -570,6 +573,8 @@ static void __init exynos4_init_uarts(struct s3c2410_uartcfg *cfg, int no) s3c24xx_init_uartdevs("exynos4210-uart", exynos4_uart_resources, cfg, no); } + +#ifdef CONFIG_EXYNOS_ATAGS static void __iomem *exynos_eint_base; static DEFINE_SPINLOCK(eint_lock); @@ -875,3 +880,4 @@ static int __init exynos_init_irq_eint(void) return 0; } arch_initcall(exynos_init_irq_eint); +#endif diff --git a/arch/arm/plat-samsung/Kconfig b/arch/arm/plat-samsung/Kconfig index a9d52167..8aae681 100644 --- a/arch/arm/plat-samsung/Kconfig +++ b/arch/arm/plat-samsung/Kconfig @@ -13,6 +13,10 @@ config PLAT_SAMSUNG help Base platform code for all Samsung SoC based systems +config PLAT_SAMSUNG_SINGLE + def_bool PLAT_SAMSUNG && !ARCH_MULTIPLATFORM + + config PLAT_S5P bool depends on (ARCH_S5P64X0 || ARCH_S5PC100 || ARCH_S5PV210 || ARCH_EXYNOS) @@ -23,7 +27,7 @@ config PLAT_S5P select GIC_NON_BANKED if ARCH_EXYNOS4 select NO_IOPORT select PLAT_SAMSUNG - select S3C_GPIO_TRACK + select S3C_GPIO_TRACK if PLAT_SAMSUNG_SINGLE select S5P_GPIO_DRVSTR select SAMSUNG_CLKSRC select SAMSUNG_GPIOLIB_4BIT @@ -178,6 +182,7 @@ config S5P_DEV_UART config S3C_ADC bool "ADC common driver support" + depends on PLAT_SAMSUNG_SINGLE help Core support for the ADC block found in the Samsung SoC systems for drivers such as the touchscreen and hwmon to use to share diff --git a/arch/arm/plat-samsung/Makefile b/arch/arm/plat-samsung/Makefile index 3a7c64d..cf684b2 100644 --- a/arch/arm/plat-samsung/Makefile +++ b/arch/arm/plat-samsung/Makefile @@ -4,6 +4,9 @@ # # Licensed under GPLv2 +ccflags-$(CONFIG_ARCH_MULTI_V7) += -I$(srctree)/$(src)/include +ccflags-$(CONFIG_ARCH_EXYNOS) += -I$(srctree)/arch/arm/mach-exynos/include + obj-y := obj-m := obj-n := dummy.o @@ -34,7 +37,7 @@ obj-$(CONFIG_S3C_ADC) += adc.o obj-y += platformdata.o -obj-y += devs.o +obj-$(CONFIG_PLAT_SAMSUNG_SINGLE) += devs.o obj-y += dev-uart.o obj-$(CONFIG_S5P_DEV_MFC) += s5p-dev-mfc.o obj-$(CONFIG_S5P_DEV_UART) += s5p-dev-uart.o @@ -51,9 +54,10 @@ obj-$(CONFIG_S3C_DMA) += dma.o s3c-dma-ops.o obj-$(CONFIG_SAMSUNG_DMADEV) += dma-ops.o # PM support - obj-$(CONFIG_PM) += pm.o +ifdef CONFIG_PLAT_SAMSUNG_SINGLE obj-$(CONFIG_PM) += pm-gpio.o +endif obj-$(CONFIG_SAMSUNG_PM_CHECK) += pm-check.o obj-$(CONFIG_SAMSUNG_WAKEMASK) += wakeup-mask.o diff --git a/arch/arm/plat-samsung/include/plat/pm.h b/arch/arm/plat-samsung/include/plat/pm.h index f6fcade..266a4e3 100644 --- a/arch/arm/plat-samsung/include/plat/pm.h +++ b/arch/arm/plat-samsung/include/plat/pm.h @@ -166,6 +166,7 @@ extern void s3c_pm_check_store(void); */ extern void s3c_pm_configure_extint(void); +#ifdef CONFIG_PLAT_SAMSUNG_SINGLE /** * samsung_pm_restore_gpios() - restore the state of the gpios after sleep. * @@ -181,6 +182,10 @@ extern void samsung_pm_restore_gpios(void); * Save the GPIO states for resotration on resume. See samsung_pm_restore_gpios(). */ extern void samsung_pm_save_gpios(void); +#else +#define samsung_pm_restore_gpios() do { } while(0) +#define samsung_pm_save_gpios() do { } while(0) +#endif extern void s3c_pm_save_core(void); extern void s3c_pm_restore_core(void); -- cgit v1.1 From f19814721e24cac152348872ff38f38a3b45852a Mon Sep 17 00:00:00 2001 From: Paul Bolle Date: Tue, 5 Mar 2013 10:13:39 +0100 Subject: ARM: SPEAr13xx: Fix typo "ARCH_HAVE_CPUFREQ" Do what commit f12a500e4adcc0961803e54b5ed1e74275d399f1 ("ARM: SPEAr13xx: Enable CONFIG_ARCH_HAS_CPUFREQ") wanted to do. [arnd: fix botched merge from changing the Kconfig file] Signed-off-by: Paul Bolle Acked-by: Viresh Kumar Signed-off-by: Arnd Bergmann --- arch/arm/mach-spear/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-spear/Kconfig b/arch/arm/mach-spear/Kconfig index 716522a..442917e 100644 --- a/arch/arm/mach-spear/Kconfig +++ b/arch/arm/mach-spear/Kconfig @@ -18,7 +18,7 @@ if PLAT_SPEAR config ARCH_SPEAR13XX bool "ST SPEAr13xx" depends on ARCH_MULTI_V7 || PLAT_SPEAR_SINGLE - select ARCH_HAVE_CPUFREQ + select ARCH_HAS_CPUFREQ select ARM_GIC select CPU_V7 select GPIO_SPEAR_SPICS -- cgit v1.1 From 4923ee444a39c8b75027ed01a7812e940194dbec Mon Sep 17 00:00:00 2001 From: Olof Johansson Date: Fri, 26 Apr 2013 11:32:02 -0700 Subject: Revert "ARM: exynos: enable multiplatform support" This reverts commit bd51de53e1be9896d815bbea30560262216d4616. Turns out that multiplatform breaks some uses cases, such as when you have an existing defconfig, since it adds the new EXYNOS_SINGLE config option as a dependecy. As a result, nearly all exynos config options will be disabled by default. Reverting instead of rebasing since this branch is pulled in as a dependency elsewhere. Signed-off-by: Olof Johansson --- arch/arm/Kconfig | 9 ++++++++- arch/arm/configs/exynos4_defconfig | 2 +- arch/arm/mach-exynos/Kconfig | 25 ++++--------------------- arch/arm/mach-exynos/Makefile | 5 ++--- arch/arm/mach-exynos/common.c | 6 ------ arch/arm/plat-samsung/Kconfig | 7 +------ arch/arm/plat-samsung/Makefile | 8 ++------ arch/arm/plat-samsung/include/plat/pm.h | 5 ----- 8 files changed, 18 insertions(+), 49 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index b375a94..13b7394 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -853,11 +853,18 @@ config ARCH_S5PV210 help Samsung S5PV210/S5PC110 series based systems -config ARCH_EXYNOS_SINGLE +config ARCH_EXYNOS bool "Samsung EXYNOS" + select ARCH_HAS_CPUFREQ select ARCH_HAS_HOLES_MEMORYMODEL select ARCH_SPARSEMEM_ENABLE + select CLKDEV_LOOKUP + select CPU_V7 + select GENERIC_CLOCKEVENTS + select HAVE_CLK + select HAVE_S3C2410_I2C if I2C select HAVE_S3C2410_WATCHDOG if WATCHDOG + select HAVE_S3C_RTC if RTC_CLASS select NEED_MACH_GPIO_H select NEED_MACH_MEMORY_H help diff --git a/arch/arm/configs/exynos4_defconfig b/arch/arm/configs/exynos4_defconfig index ae90a0f..bffe68e 100644 --- a/arch/arm/configs/exynos4_defconfig +++ b/arch/arm/configs/exynos4_defconfig @@ -4,7 +4,7 @@ CONFIG_KALLSYMS_ALL=y CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y # CONFIG_BLK_DEV_BSG is not set -CONFIG_ARCH_EXYNOS_SINGLE=y +CONFIG_ARCH_EXYNOS=y CONFIG_S3C_LOWLEVEL_UART_PORT=1 CONFIG_MACH_SMDKC210=y CONFIG_MACH_ARMLEX4210=y diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig index 1d69c62..d8c251b 100644 --- a/arch/arm/mach-exynos/Kconfig +++ b/arch/arm/mach-exynos/Kconfig @@ -7,20 +7,6 @@ # Configuration options for the EXYNOS4 -config ARCH_EXYNOS - # TODO: make this visible after all drivers are converted - bool "Samsung EXYNOS" if ARCH_MULTI_V7 && BROKEN - default ARCH_EXYNOS_SINGLE - select ARCH_HAS_CPUFREQ - select CLKDEV_LOOKUP - select CPU_V7 - select GENERIC_CLOCKEVENTS - select HAVE_CLK - select HAVE_S3C2410_I2C if I2C - select HAVE_S3C_RTC if RTC_CLASS - help - Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5) - if ARCH_EXYNOS menu "SAMSUNG EXYNOS SoCs Support" @@ -33,9 +19,6 @@ config ARCH_EXYNOS4 help Samsung EXYNOS4 SoCs based systems -config ARCH_EXYNOS4_SINGLE - def_bool ARCH_EXYNOS4 && ARCH_EXYNOS_SINGLE - config ARCH_EXYNOS5 bool "SAMSUNG EXYNOS5" select HAVE_SMP @@ -52,7 +35,7 @@ config CPU_EXYNOS4210 select PM_GENERIC_DOMAINS select S5P_PM if PM select S5P_SLEEP if PM - select SAMSUNG_DMADEV if ARCH_EXYNOS_SINGLE + select SAMSUNG_DMADEV help Enable EXYNOS4210 CPU support @@ -62,7 +45,7 @@ config SOC_EXYNOS4212 depends on ARCH_EXYNOS4 select S5P_PM if PM select S5P_SLEEP if PM - select SAMSUNG_DMADEV if ARCH_EXYNOS_SINGLE + select SAMSUNG_DMADEV help Enable EXYNOS4212 SoC support @@ -70,7 +53,7 @@ config SOC_EXYNOS4412 bool "SAMSUNG EXYNOS4412" default y depends on ARCH_EXYNOS4 - select SAMSUNG_DMADEV if ARCH_EXYNOS_SINGLE + select SAMSUNG_DMADEV help Enable EXYNOS4412 SoC support @@ -81,7 +64,7 @@ config SOC_EXYNOS5250 select S5P_PM if PM select S5P_SLEEP if PM select S5P_DEV_MFC - select SAMSUNG_DMADEV if ARCH_EXYNOS_SINGLE + select SAMSUNG_DMADEV help Enable EXYNOS5250 SoC support diff --git a/arch/arm/mach-exynos/Makefile b/arch/arm/mach-exynos/Makefile index 57e9124..435757e 100644 --- a/arch/arm/mach-exynos/Makefile +++ b/arch/arm/mach-exynos/Makefile @@ -4,7 +4,6 @@ # http://www.samsung.com/ # # Licensed under GPLv2 -ccflags-$(CONFIG_ARCH_MULTIPLATFORM) += -I$(srctree)/$(src)/include -I$(srctree)/arch/arm/plat-samsung/include obj-y := obj-m := @@ -49,12 +48,12 @@ obj-$(CONFIG_MACH_EXYNOS5_DT) += mach-exynos5-dt.o # device support obj-y += dev-uart.o -obj-$(CONFIG_ARCH_EXYNOS4_SINGLE) += dev-audio.o +obj-$(CONFIG_ARCH_EXYNOS4) += dev-audio.o obj-$(CONFIG_EXYNOS4_DEV_AHCI) += dev-ahci.o obj-$(CONFIG_EXYNOS_DEV_DMA) += dma.o obj-$(CONFIG_EXYNOS4_DEV_USB_OHCI) += dev-ohci.o -obj-$(CONFIG_ARCH_EXYNOS_SINGLE) += setup-i2c0.o +obj-$(CONFIG_ARCH_EXYNOS) += setup-i2c0.o obj-$(CONFIG_EXYNOS4_SETUP_FIMC) += setup-fimc.o obj-$(CONFIG_EXYNOS4_SETUP_FIMD0) += setup-fimd0.o obj-$(CONFIG_EXYNOS4_SETUP_I2C1) += setup-i2c1.o diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c index 83bd3f0..d63d399 100644 --- a/arch/arm/mach-exynos/common.c +++ b/arch/arm/mach-exynos/common.c @@ -368,9 +368,6 @@ static void __init exynos4_map_io(void) else iotable_init(exynos4_iodesc1, ARRAY_SIZE(exynos4_iodesc1)); - if (!IS_ENABLED(CONFIG_EXYNOS_ATAGS)) - return - /* initialize device information early */ exynos4_default_sdhci0(); exynos4_default_sdhci1(); @@ -573,8 +570,6 @@ static void __init exynos4_init_uarts(struct s3c2410_uartcfg *cfg, int no) s3c24xx_init_uartdevs("exynos4210-uart", exynos4_uart_resources, cfg, no); } - -#ifdef CONFIG_EXYNOS_ATAGS static void __iomem *exynos_eint_base; static DEFINE_SPINLOCK(eint_lock); @@ -880,4 +875,3 @@ static int __init exynos_init_irq_eint(void) return 0; } arch_initcall(exynos_init_irq_eint); -#endif diff --git a/arch/arm/plat-samsung/Kconfig b/arch/arm/plat-samsung/Kconfig index 8aae681..a9d52167 100644 --- a/arch/arm/plat-samsung/Kconfig +++ b/arch/arm/plat-samsung/Kconfig @@ -13,10 +13,6 @@ config PLAT_SAMSUNG help Base platform code for all Samsung SoC based systems -config PLAT_SAMSUNG_SINGLE - def_bool PLAT_SAMSUNG && !ARCH_MULTIPLATFORM - - config PLAT_S5P bool depends on (ARCH_S5P64X0 || ARCH_S5PC100 || ARCH_S5PV210 || ARCH_EXYNOS) @@ -27,7 +23,7 @@ config PLAT_S5P select GIC_NON_BANKED if ARCH_EXYNOS4 select NO_IOPORT select PLAT_SAMSUNG - select S3C_GPIO_TRACK if PLAT_SAMSUNG_SINGLE + select S3C_GPIO_TRACK select S5P_GPIO_DRVSTR select SAMSUNG_CLKSRC select SAMSUNG_GPIOLIB_4BIT @@ -182,7 +178,6 @@ config S5P_DEV_UART config S3C_ADC bool "ADC common driver support" - depends on PLAT_SAMSUNG_SINGLE help Core support for the ADC block found in the Samsung SoC systems for drivers such as the touchscreen and hwmon to use to share diff --git a/arch/arm/plat-samsung/Makefile b/arch/arm/plat-samsung/Makefile index cf684b2..3a7c64d 100644 --- a/arch/arm/plat-samsung/Makefile +++ b/arch/arm/plat-samsung/Makefile @@ -4,9 +4,6 @@ # # Licensed under GPLv2 -ccflags-$(CONFIG_ARCH_MULTI_V7) += -I$(srctree)/$(src)/include -ccflags-$(CONFIG_ARCH_EXYNOS) += -I$(srctree)/arch/arm/mach-exynos/include - obj-y := obj-m := obj-n := dummy.o @@ -37,7 +34,7 @@ obj-$(CONFIG_S3C_ADC) += adc.o obj-y += platformdata.o -obj-$(CONFIG_PLAT_SAMSUNG_SINGLE) += devs.o +obj-y += devs.o obj-y += dev-uart.o obj-$(CONFIG_S5P_DEV_MFC) += s5p-dev-mfc.o obj-$(CONFIG_S5P_DEV_UART) += s5p-dev-uart.o @@ -54,10 +51,9 @@ obj-$(CONFIG_S3C_DMA) += dma.o s3c-dma-ops.o obj-$(CONFIG_SAMSUNG_DMADEV) += dma-ops.o # PM support + obj-$(CONFIG_PM) += pm.o -ifdef CONFIG_PLAT_SAMSUNG_SINGLE obj-$(CONFIG_PM) += pm-gpio.o -endif obj-$(CONFIG_SAMSUNG_PM_CHECK) += pm-check.o obj-$(CONFIG_SAMSUNG_WAKEMASK) += wakeup-mask.o diff --git a/arch/arm/plat-samsung/include/plat/pm.h b/arch/arm/plat-samsung/include/plat/pm.h index 266a4e3..f6fcade 100644 --- a/arch/arm/plat-samsung/include/plat/pm.h +++ b/arch/arm/plat-samsung/include/plat/pm.h @@ -166,7 +166,6 @@ extern void s3c_pm_check_store(void); */ extern void s3c_pm_configure_extint(void); -#ifdef CONFIG_PLAT_SAMSUNG_SINGLE /** * samsung_pm_restore_gpios() - restore the state of the gpios after sleep. * @@ -182,10 +181,6 @@ extern void samsung_pm_restore_gpios(void); * Save the GPIO states for resotration on resume. See samsung_pm_restore_gpios(). */ extern void samsung_pm_save_gpios(void); -#else -#define samsung_pm_restore_gpios() do { } while(0) -#define samsung_pm_save_gpios() do { } while(0) -#endif extern void s3c_pm_save_core(void); extern void s3c_pm_restore_core(void); -- cgit v1.1 From ea7113f70d6f91dee0d7afd8580c8cac06b6d222 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Sat, 20 Apr 2013 16:09:17 +0200 Subject: clocksource: nomadik-mtu: fix up clocksource/timer The Nomadik clocksource driver has had a bad define making it impossible to use it for sched_clock() for a while. Fix this and also enable it for the Nomadik. Signed-off-by: Linus Walleij Signed-off-by: Olof Johansson --- arch/arm/mach-nomadik/Kconfig | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm') diff --git a/arch/arm/mach-nomadik/Kconfig b/arch/arm/mach-nomadik/Kconfig index 3213bad..9b9d105 100644 --- a/arch/arm/mach-nomadik/Kconfig +++ b/arch/arm/mach-nomadik/Kconfig @@ -5,6 +5,7 @@ config ARCH_NOMADIK select ARM_AMBA select ARM_VIC select CLKSRC_NOMADIK_MTU + select CLKSRC_NOMADIK_MTU_SCHED_CLOCK select COMMON_CLK select CPU_ARM926T select GENERIC_CLOCKEVENTS -- cgit v1.1