From 74dc3cd32e062b664e78c2e61331b4e0caac7822 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Date: Wed, 1 Mar 2017 15:26:42 +0100 Subject: ARM: dts: aspeed: add SPI controller bindings MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Let's define the SPI controllers in the Aspeed SoCs AST2500 and AST2400 and also enable these, as well as the chips, on the associated platforms. Signed-off-by: Cédric Le Goater Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-ast2500-evb.dts | 20 +++++++++ arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts | 16 +++++++ arch/arm/boot/dts/aspeed-g4.dtsi | 29 ++++++++++++ arch/arm/boot/dts/aspeed-g5.dtsi | 63 +++++++++++++++++++++++++++ 4 files changed, 128 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/aspeed-ast2500-evb.dts b/arch/arm/boot/dts/aspeed-ast2500-evb.dts index d967603..8f82e8a 100644 --- a/arch/arm/boot/dts/aspeed-ast2500-evb.dts +++ b/arch/arm/boot/dts/aspeed-ast2500-evb.dts @@ -20,6 +20,26 @@ }; }; +&fmc { + status = "okay"; + flash@0 { + status = "okay"; + label = "bmc"; + }; +}; + +&spi1 { + status = "okay"; + flash@0 { + status = "okay"; + label = "pnor"; + }; +}; + +&spi2 { + status = "okay"; +}; + &uart5 { status = "okay"; }; diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts b/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts index 1d2fc1e..aab1889 100644 --- a/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts +++ b/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts @@ -31,6 +31,22 @@ }; }; +&fmc { + status = "okay"; + flash@0 { + status = "okay"; + label = "bmc"; + }; +}; + +&spi { + status = "okay"; + flash@0 { + status = "okay"; + label = "pnor"; + }; +}; + &uart5 { status = "okay"; }; diff --git a/arch/arm/boot/dts/aspeed-g4.dtsi b/arch/arm/boot/dts/aspeed-g4.dtsi index 0b4932c..7ef6442 100644 --- a/arch/arm/boot/dts/aspeed-g4.dtsi +++ b/arch/arm/boot/dts/aspeed-g4.dtsi @@ -33,6 +33,35 @@ #size-cells = <1>; ranges; + fmc: flash-controller@1e620000 { + reg = < 0x1e620000 0x94 + 0x20000000 0x02000000 >; + #address-cells = <1>; + #size-cells = <0>; + compatible = "aspeed,ast2400-fmc"; + status = "disabled"; + interrupts = <19>; + flash@0 { + reg = < 0 >; + compatible = "jedec,spi-nor"; + status = "disabled"; + }; + }; + + spi: flash-controller@1e630000 { + reg = < 0x1e630000 0x18 + 0x30000000 0x02000000 >; + #address-cells = <1>; + #size-cells = <0>; + compatible = "aspeed,ast2400-spi"; + status = "disabled"; + flash@0 { + reg = < 0 >; + compatible = "jedec,spi-nor"; + status = "disabled"; + }; + }; + vic: interrupt-controller@1e6c0080 { compatible = "aspeed,ast2400-vic"; interrupt-controller; diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi index b664fe3..8970f3c 100644 --- a/arch/arm/boot/dts/aspeed-g5.dtsi +++ b/arch/arm/boot/dts/aspeed-g5.dtsi @@ -24,6 +24,69 @@ #size-cells = <1>; ranges; + fmc: flash-controller@1e620000 { + reg = < 0x1e620000 0xc4 + 0x20000000 0x10000000 >; + #address-cells = <1>; + #size-cells = <0>; + compatible = "aspeed,ast2500-fmc"; + status = "disabled"; + interrupts = <19>; + flash@0 { + reg = < 0 >; + compatible = "jedec,spi-nor"; + status = "disabled"; + }; + flash@1 { + reg = < 1 >; + compatible = "jedec,spi-nor"; + status = "disabled"; + }; + flash@2 { + reg = < 2 >; + compatible = "jedec,spi-nor"; + status = "disabled"; + }; + }; + + spi1: flash-controller@1e630000 { + reg = < 0x1e630000 0xc4 + 0x30000000 0x08000000 >; + #address-cells = <1>; + #size-cells = <0>; + compatible = "aspeed,ast2500-spi"; + status = "disabled"; + flash@0 { + reg = < 0 >; + compatible = "jedec,spi-nor"; + status = "disabled"; + }; + flash@1 { + reg = < 1 >; + compatible = "jedec,spi-nor"; + status = "disabled"; + }; + }; + + spi2: flash-controller@1e631000 { + reg = < 0x1e631000 0xc4 + 0x38000000 0x08000000 >; + #address-cells = <1>; + #size-cells = <0>; + compatible = "aspeed,ast2500-spi"; + status = "disabled"; + flash@0 { + reg = < 0 >; + compatible = "jedec,spi-nor"; + status = "disabled"; + }; + flash@1 { + reg = < 1 >; + compatible = "jedec,spi-nor"; + status = "disabled"; + }; + }; + vic: interrupt-controller@1e6c0080 { compatible = "aspeed,ast2400-vic"; interrupt-controller; -- cgit v1.1 From 8b9102da97293073f065fe5dfd49d21580b84e2b Mon Sep 17 00:00:00 2001 From: Joel Stanley Date: Fri, 31 Mar 2017 13:05:10 +1030 Subject: ARM: dts: aspeed: Make G5 clocks fixed MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit We do not yet have a clk driver upstream. So that users can boot the unmodified upstream kernel, add fixed-clock and clock-frequency properties to all of the clocks. The values are taken from the ast2500evb. This is the only upstream dts. It also happens to match all of the systems I have seen so far. Acked-by: Cédric Le Goater Acked-by: Andrew Jeffery Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-g5.dtsi | 72 ++++++++++++++++++++++------------------ 1 file changed, 40 insertions(+), 32 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi index 8970f3c..9e0b86e 100644 --- a/arch/arm/boot/dts/aspeed-g5.dtsi +++ b/arch/arm/boot/dts/aspeed-g5.dtsi @@ -117,15 +117,49 @@ #size-cells = <1>; ranges; - clk_clkin: clk_clkin@1e6e2070 { - #clock-cells = <0>; - compatible = "aspeed,g5-clkin-clock"; - reg = <0x1e6e2070 0x04>; - }; - syscon: syscon@1e6e2000 { compatible = "aspeed,g5-scu", "syscon", "simple-mfd"; reg = <0x1e6e2000 0x1a8>; + #address-cells = <1>; + #size-cells = <0>; + + clk_clkin: clk_clkin@70 { + #clock-cells = <0>; + compatible = "aspeed,g5-clkin-clock", "fixed-clock"; + reg = <0x70>; + clock-frequency = <24000000>; + }; + + clk_hpll: clk_hpll@24 { + #clock-cells = <0>; + compatible = "aspeed,g5-hpll-clock", "fixed-clock"; + reg = <0x24>; + clocks = <&clk_clkin>; + clock-frequency = <792000000>; + }; + + clk_ahb: clk_ahb@70 { + #clock-cells = <0>; + compatible = "aspeed,g5-ahb-clock", "fixed-clock"; + reg = <0x70>; + clocks = <&clk_hpll>; + clock-frequency = <198000000>; + }; + + clk_apb: clk_apb@08 { + #clock-cells = <0>; + compatible = "aspeed,g5-apb-clock", "fixed-clock"; + reg = <0x08>; + clocks = <&clk_hpll>; + clock-frequency = <24750000>; + }; + + clk_uart: clk_uart@2c { + #clock-cells = <0>; + compatible = "aspeed,uart-clock", "fixed-clock"; + reg = <0x2c>; + clock-frequency = <24000000>; + }; pinctrl: pinctrl { compatible = "aspeed,g5-pinctrl"; @@ -937,33 +971,7 @@ }; }; - }; - - clk_hpll: clk_hpll@1e6e2024 { - #clock-cells = <0>; - compatible = "aspeed,g5-hpll-clock"; - reg = <0x1e6e2024 0x4>; - clocks = <&clk_clkin>; - }; - - clk_ahb: clk_ahb@1e6e2070 { - #clock-cells = <0>; - compatible = "aspeed,g5-ahb-clock"; - reg = <0x1e6e2070 0x4>; - clocks = <&clk_hpll>; - }; - - clk_apb: clk_apb@1e6e2008 { - #clock-cells = <0>; - compatible = "aspeed,g5-apb-clock"; - reg = <0x1e6e2008 0x4>; - clocks = <&clk_hpll>; - }; - clk_uart: clk_uart@1e6e2008 { - #clock-cells = <0>; - compatible = "aspeed,uart-clock"; - reg = <0x1e6e202c 0x4>; }; gfx: display@1e6e6000 { -- cgit v1.1 From 491bdcfa8c41995419a6719f83016d7a43008f38 Mon Sep 17 00:00:00 2001 From: Joel Stanley Date: Thu, 6 Apr 2017 11:11:43 +0930 Subject: ARM: dts: aspeed: Make G4 clocks fixed MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit We do not yet have a clk driver upstream. So that users can boot the unmodified upstream kernel, add fixed-clock and clock-frequency properties to all of the clocks. The values are taken from the Palmetto system. This is the only upstream dts. It also happens to match all of the systems seen so far. Acked-by: Cédric Le Goater Acked-by: Andrew Jeffery Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-g4.dtsi | 68 +++++++++++++++++++++++----------------- 1 file changed, 39 insertions(+), 29 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/aspeed-g4.dtsi b/arch/arm/boot/dts/aspeed-g4.dtsi index 7ef6442..4e3f055 100644 --- a/arch/arm/boot/dts/aspeed-g4.dtsi +++ b/arch/arm/boot/dts/aspeed-g4.dtsi @@ -18,15 +18,6 @@ }; }; - clocks { - clk_clkin: clk_clkin { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <48000000>; - }; - - }; - ahb { compatible = "simple-bus"; #address-cells = <1>; @@ -92,16 +83,48 @@ #size-cells = <1>; ranges; - clk_hpll: clk_hpll@1e6e2070 { - #clock-cells = <0>; - compatible = "aspeed,g4-hpll-clock"; - reg = <0x1e6e2070 0x4>; - clocks = <&clk_clkin>; - }; - syscon: syscon@1e6e2000 { compatible = "aspeed,g4-scu", "syscon", "simple-mfd"; reg = <0x1e6e2000 0x1a8>; + #address-cells = <1>; + #size-cells = <0>; + + clk_clkin: clk_clkin { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <48000000>; + }; + + clk_hpll: clk_hpll@70 { + #clock-cells = <0>; + compatible = "aspeed,g4-hpll-clock", "fixed-clock"; + reg = <0x70>; + clocks = <&clk_clkin>; + clock-frequency = <384000000>; + }; + + clk_ahb: clk_ahb@70 { + #clock-cells = <0>; + compatible = "aspeed,g4-ahb-clock", "fixed-clock"; + reg = <0x70>; + clocks = <&clk_hpll>; + clock-frequency = <192000000>; + }; + + clk_apb: clk_apb@08 { + #clock-cells = <0>; + compatible = "aspeed,g4-apb-clock", "fixed-clock"; + reg = <0x08>; + clocks = <&clk_hpll>; + clock-frequency = <48000000>; + }; + + clk_uart: clk_uart@2c{ + #clock-cells = <0>; + compatible = "aspeed,g4-uart-clock", "fixed-clock"; + reg = <0x2c>; + clock-frequency = <24000000>; + }; pinctrl: pinctrl { compatible = "aspeed,g4-pinctrl"; @@ -849,19 +872,6 @@ }; }; - clk_apb: clk_apb@1e6e2008 { - #clock-cells = <0>; - compatible = "aspeed,g4-apb-clock"; - reg = <0x1e6e2008 0x4>; - clocks = <&clk_hpll>; - }; - - clk_uart: clk_uart@1e6e2008 { - #clock-cells = <0>; - compatible = "aspeed,uart-clock"; - reg = <0x1e6e202c 0x4>; - }; - sram@1e720000 { compatible = "mmio-sram"; reg = <0x1e720000 0x8000>; // 32K -- cgit v1.1 From 1142aea9ff9d9f86fc88e6637f7c6edd25adc39c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Date: Wed, 22 Mar 2017 17:04:43 +0100 Subject: ARM: dts: aspeed: Add SPI controller bindings to Romulus MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Romulus systems have one MX25L25635 (32768 Kbytes) flash module for the BMC firmware and other MT25QL512A (65536 Kbytes) for the host. Signed-off-by: Cédric Le Goater Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts b/arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts index 7a3b2b5..7a02044 100644 --- a/arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts +++ b/arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts @@ -31,6 +31,25 @@ }; }; +&fmc { + status = "okay"; + flash@0 { + status = "okay"; + label = "bmc"; + }; +}; + +&spi1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi1_default>; + + flash@0 { + status = "okay"; + label = "pnor"; + }; +}; + &uart5 { status = "okay"; }; -- cgit v1.1 From 63c6527b7f6802fbc6f537a53d0e1a0d1435191d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Date: Thu, 6 Apr 2017 19:02:33 +0200 Subject: ARM: dts: aspeed: Add a fastread property MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit All chips on OpenPOWER platforms support the fastread SPI command. Signed-off-by: Cédric Le Goater Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-ast2500-evb.dts | 2 ++ arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts | 2 ++ arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts | 2 ++ 3 files changed, 6 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/aspeed-ast2500-evb.dts b/arch/arm/boot/dts/aspeed-ast2500-evb.dts index 8f82e8a..7c90dac 100644 --- a/arch/arm/boot/dts/aspeed-ast2500-evb.dts +++ b/arch/arm/boot/dts/aspeed-ast2500-evb.dts @@ -24,6 +24,7 @@ status = "okay"; flash@0 { status = "okay"; + m25p,fast-read; label = "bmc"; }; }; @@ -32,6 +33,7 @@ status = "okay"; flash@0 { status = "okay"; + m25p,fast-read; label = "pnor"; }; }; diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts b/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts index aab1889..1125517 100644 --- a/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts +++ b/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts @@ -35,6 +35,7 @@ status = "okay"; flash@0 { status = "okay"; + m25p,fast-read; label = "bmc"; }; }; @@ -43,6 +44,7 @@ status = "okay"; flash@0 { status = "okay"; + m25p,fast-read; label = "pnor"; }; }; diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts b/arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts index 7a02044..5a08961 100644 --- a/arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts +++ b/arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts @@ -35,6 +35,7 @@ status = "okay"; flash@0 { status = "okay"; + m25p,fast-read; label = "bmc"; }; }; @@ -46,6 +47,7 @@ flash@0 { status = "okay"; + m25p,fast-read; label = "pnor"; }; }; -- cgit v1.1 From 23491da8f5bcc6e7914654746fbe3dfeb5820e17 Mon Sep 17 00:00:00 2001 From: Joel Stanley Date: Fri, 7 Apr 2017 12:14:19 +0930 Subject: ARM: dts: aspeed: Update watchdog compatible strings The string was changed when upstreaming the driver. Put the correct string for generation 4 and 5 systems, as well as fix the reg length for ast2500 systems. Acked-by: Andrew Jeffery Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-g4.dtsi | 4 ++-- arch/arm/boot/dts/aspeed-g5.dtsi | 12 ++++++------ 2 files changed, 8 insertions(+), 8 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/aspeed-g4.dtsi b/arch/arm/boot/dts/aspeed-g4.dtsi index 4e3f055..857cc0c 100644 --- a/arch/arm/boot/dts/aspeed-g4.dtsi +++ b/arch/arm/boot/dts/aspeed-g4.dtsi @@ -898,13 +898,13 @@ }; wdt1: wdt@1e785000 { - compatible = "aspeed,wdt"; + compatible = "aspeed,ast2400-wdt"; reg = <0x1e785000 0x1c>; interrupts = <27>; }; wdt2: wdt@1e785020 { - compatible = "aspeed,wdt"; + compatible = "aspeed,ast2400-wdt"; reg = <0x1e785020 0x1c>; interrupts = <27>; clocks = <&clk_apb>; diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi index 9e0b86e..f7a81c9 100644 --- a/arch/arm/boot/dts/aspeed-g5.dtsi +++ b/arch/arm/boot/dts/aspeed-g5.dtsi @@ -1007,21 +1007,21 @@ wdt1: wdt@1e785000 { - compatible = "aspeed,wdt"; - reg = <0x1e785000 0x1c>; + compatible = "aspeed,ast2500-wdt"; + reg = <0x1e785000 0x20>; interrupts = <27>; }; wdt2: wdt@1e785020 { - compatible = "aspeed,wdt"; - reg = <0x1e785020 0x1c>; + compatible = "aspeed,ast2500-wdt"; + reg = <0x1e785020 0x20>; interrupts = <27>; status = "disabled"; }; wdt3: wdt@1e785040 { - compatible = "aspeed,wdt"; - reg = <0x1e785074 0x1c>; + compatible = "aspeed,ast2500-wdt"; + reg = <0x1e785040 0x20>; status = "disabled"; }; -- cgit v1.1 From 71b8b86c75f7eea71ba0aa49490d59fd48ff7661 Mon Sep 17 00:00:00 2001 From: Lei YU Date: Thu, 23 Mar 2017 14:42:48 +0800 Subject: ARM: dts: aspeed: romulus: Add UART1 Romulus has a RS-232 connection on the back of chassis, add UART1 to use this connection. Signed-off-by: Lei YU Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts | 15 +++++++++++++++ 1 file changed, 15 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts b/arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts index 5a08961..1190fec1 100644 --- a/arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts +++ b/arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts @@ -52,6 +52,21 @@ }; }; +&uart1 { + /* Rear RS-232 connector */ + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_txd1_default + &pinctrl_rxd1_default + &pinctrl_nrts1_default + &pinctrl_ndtr1_default + &pinctrl_ndsr1_default + &pinctrl_ncts1_default + &pinctrl_ndcd1_default + &pinctrl_nri1_default>; +}; + &uart5 { status = "okay"; }; -- cgit v1.1 From 78a2569fa60497347babeddb24a367946e258283 Mon Sep 17 00:00:00 2001 From: Rick Altherr Date: Wed, 29 Mar 2017 18:08:46 -0700 Subject: arm: dts: aspeed: Describe ADCs for AST2400/AST2500 Signed-off-by: Rick Altherr Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-g4.dtsi | 8 ++++++++ arch/arm/boot/dts/aspeed-g5.dtsi | 9 ++++++++- 2 files changed, 16 insertions(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/aspeed-g4.dtsi b/arch/arm/boot/dts/aspeed-g4.dtsi index 857cc0c..914f6e7 100644 --- a/arch/arm/boot/dts/aspeed-g4.dtsi +++ b/arch/arm/boot/dts/aspeed-g4.dtsi @@ -971,6 +971,14 @@ no-loopback-test; status = "disabled"; }; + + adc: adc@1e6e9000 { + compatible = "aspeed,ast2400-adc"; + reg = <0x1e6e9000 0xb0>; + clocks = <&clk_apb>; + #io-channel-cells = <1>; + status = "disabled"; + }; }; }; }; diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi index f7a81c9..20e2af0 100644 --- a/arch/arm/boot/dts/aspeed-g5.dtsi +++ b/arch/arm/boot/dts/aspeed-g5.dtsi @@ -384,7 +384,6 @@ function = "LAD0"; groups = "LAD0"; }; - pinctrl_lad1_default: lad1_default { function = "LAD1"; groups = "LAD1"; @@ -1115,6 +1114,14 @@ no-loopback-test; status = "disabled"; }; + + adc: adc@1e6e9000 { + compatible = "aspeed,ast2500-adc"; + reg = <0x1e6e9000 0xb0>; + clocks = <&clk_apb>; + #io-channel-cells = <1>; + status = "disabled"; + }; }; }; }; -- cgit v1.1