From 7ec892ef5f1bd707e2d5ab128069cb6af75c7f07 Mon Sep 17 00:00:00 2001 From: Vivek Gautam Date: Wed, 10 Apr 2013 19:30:38 +0900 Subject: ARM: dts: Enabling samsung-usb2phy driver for exynos5250 Adding usbphy node for Exynos5250 along with the necessary device data to be parsed. Signed-off-by: Vivek Gautam Signed-off-by: Kukjin Kim --- arch/arm/boot/dts/exynos5250.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi index 98dfc3e..0673524 100644 --- a/arch/arm/boot/dts/exynos5250.dtsi +++ b/arch/arm/boot/dts/exynos5250.dtsi @@ -497,6 +497,21 @@ clock-names = "usbhost"; }; + usbphy@12130000 { + compatible = "samsung,exynos5250-usb2phy"; + reg = <0x12130000 0x100>; + clocks = <&clock 1>, <&clock 285>; + clock-names = "ext_xtal", "usbhost"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + usbphy-sys { + reg = <0x10040704 0x8>, + <0x10050230 0x4>; + }; + }; + amba { #address-cells = <1>; #size-cells = <1>; -- cgit v1.1 From 68a433f18c0574b50c5952978ca95b0db7347174 Mon Sep 17 00:00:00 2001 From: Tomasz Figa Date: Sat, 25 May 2013 06:27:29 +0900 Subject: ARM: EXYNOS: Fix support of Exynos4210 rev0 SoC This patch extends exynos_init_time() function to handle Exynos4210 rev0 SoC, which differs in availability of system timers and needs different clocksource initialization. This makes it possible to use exynos_init_time() function as init_time callback for all Exynos-based boards, including Universal_C210, which originally had to use samsung_timer_init(). Signed-off-by: Tomasz Figa Signed-off-by: Kyungmin Park Signed-off-by: Kukjin Kim --- arch/arm/mach-exynos/Kconfig | 3 ++- arch/arm/mach-exynos/common.c | 30 +++++++++++++++++++++++++++++- arch/arm/mach-exynos/common.h | 2 ++ arch/arm/mach-exynos/mach-universal_c210.c | 5 ++--- 4 files changed, 35 insertions(+), 5 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig index d19edff..ff18fc2 100644 --- a/arch/arm/mach-exynos/Kconfig +++ b/arch/arm/mach-exynos/Kconfig @@ -250,6 +250,7 @@ config MACH_ARMLEX4210 config MACH_UNIVERSAL_C210 bool "Mobile UNIVERSAL_C210 Board" select CLKSRC_MMIO + select CLKSRC_SAMSUNG_PWM select CPU_EXYNOS4210 select EXYNOS4_SETUP_FIMC select EXYNOS4_SETUP_FIMD0 @@ -281,7 +282,6 @@ config MACH_UNIVERSAL_C210 select S5P_DEV_TV select S5P_GPIO_INT select S5P_SETUP_MIPIPHY - select SAMSUNG_HRT help Machine support for Samsung Mobile Universal S5PC210 Reference Board. @@ -410,6 +410,7 @@ config MACH_EXYNOS4_DT depends on ARCH_EXYNOS4 select ARM_AMBA select CLKSRC_OF + select CLKSRC_SAMSUNG_PWM if CPU_EXYNOS4210 select CPU_EXYNOS4210 select KEYBOARD_SAMSUNG if INPUT_KEYBOARD select PINCTRL diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c index 745e304..a2d2012 100644 --- a/arch/arm/mach-exynos/common.c +++ b/arch/arm/mach-exynos/common.c @@ -10,12 +10,14 @@ */ #include +#include #include #include #include #include #include #include +#include #include #include #include @@ -302,6 +304,13 @@ static struct map_desc exynos5440_iodesc0[] __initdata = { }, }; +static struct samsung_pwm_variant exynos4_pwm_variant = { + .bits = 32, + .div_base = 0, + .has_tint_cstat = true, + .tclk_mask = 0, +}; + void exynos4_restart(char mode, const char *cmd) { __raw_writel(0x1, S5P_SWRESET); @@ -442,8 +451,20 @@ static void __init exynos5440_map_io(void) iotable_init(exynos5440_iodesc0, ARRAY_SIZE(exynos5440_iodesc0)); } +void __init exynos_set_timer_source(u8 channels) +{ + exynos4_pwm_variant.output_mask = BIT(SAMSUNG_PWM_NUM) - 1; + exynos4_pwm_variant.output_mask &= ~channels; +} + void __init exynos_init_time(void) { + unsigned int timer_irqs[SAMSUNG_PWM_NUM] = { + EXYNOS4_IRQ_TIMER0_VIC, EXYNOS4_IRQ_TIMER1_VIC, + EXYNOS4_IRQ_TIMER2_VIC, EXYNOS4_IRQ_TIMER3_VIC, + EXYNOS4_IRQ_TIMER4_VIC, + }; + if (of_have_populated_dt()) { #ifdef CONFIG_OF of_clk_init(NULL); @@ -455,7 +476,14 @@ void __init exynos_init_time(void) exynos4_clk_init(NULL, !soc_is_exynos4210(), S5P_VA_CMU, readl(S5P_VA_CHIPID + 8) & 1); exynos4_clk_register_fixed_ext(xxti_f, xusbxti_f); #endif - mct_init(S5P_VA_SYSTIMER, EXYNOS4_IRQ_MCT_G0, EXYNOS4_IRQ_MCT_L0, EXYNOS4_IRQ_MCT_L1); +#ifdef CONFIG_CLKSRC_SAMSUNG_PWM + if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_0) + samsung_pwm_clocksource_init(S3C_VA_TIMER, + timer_irqs, &exynos4_pwm_variant); + else +#endif + mct_init(S5P_VA_SYSTIMER, EXYNOS4_IRQ_MCT_G0, + EXYNOS4_IRQ_MCT_L0, EXYNOS4_IRQ_MCT_L1); } } diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h index 60dd35c..11fc1e2 100644 --- a/arch/arm/mach-exynos/common.h +++ b/arch/arm/mach-exynos/common.h @@ -32,6 +32,8 @@ void exynos4_clk_register_fixed_ext(unsigned long, unsigned long); void exynos_firmware_init(void); +void exynos_set_timer_source(u8 channels); + #ifdef CONFIG_PM_GENERIC_DOMAINS int exynos_pm_late_initcall(void); #else diff --git a/arch/arm/mach-exynos/mach-universal_c210.c b/arch/arm/mach-exynos/mach-universal_c210.c index 327d50d..74ddb2b 100644 --- a/arch/arm/mach-exynos/mach-universal_c210.c +++ b/arch/arm/mach-exynos/mach-universal_c210.c @@ -41,7 +41,6 @@ #include #include #include -#include #include #include @@ -1094,7 +1093,7 @@ static void __init universal_map_io(void) { exynos_init_io(NULL, 0); s3c24xx_init_uarts(universal_uartcfgs, ARRAY_SIZE(universal_uartcfgs)); - samsung_set_timer_source(SAMSUNG_PWM2, SAMSUNG_PWM4); + exynos_set_timer_source(BIT(2) | BIT(4)); xxti_f = 0; xusbxti_f = 24000000; } @@ -1154,7 +1153,7 @@ MACHINE_START(UNIVERSAL_C210, "UNIVERSAL_C210") .map_io = universal_map_io, .init_machine = universal_machine_init, .init_late = exynos_init_late, - .init_time = samsung_timer_init, + .init_time = exynos_init_time, .reserve = &universal_reserve, .restart = exynos4_restart, MACHINE_END -- cgit v1.1 From 1ba830c9997214a7fbe4d91cf238793764620e3b Mon Sep 17 00:00:00 2001 From: Jungseok Lee Date: Sat, 25 May 2013 06:33:03 +0900 Subject: ARM: EXYNOS: fix software reset logic for EXYNOS5440 SOC This patch fixes software reset logic. Software reset applies only to powered-on domains in SOC because software reset to all domains causes reboot failure. Signed-off-by: Jungseok Lee Signed-off-by: Kukjin Kim --- arch/arm/mach-exynos/common.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c index a2d2012..027c9e7 100644 --- a/arch/arm/mach-exynos/common.c +++ b/arch/arm/mach-exynos/common.c @@ -326,9 +326,16 @@ void exynos5_restart(char mode, const char *cmd) val = 0x1; addr = EXYNOS_SWRESET; } else if (of_machine_is_compatible("samsung,exynos5440")) { + u32 status; np = of_find_compatible_node(NULL, NULL, "samsung,exynos5440-clock"); + + addr = of_iomap(np, 0) + 0xbc; + status = __raw_readl(addr); + addr = of_iomap(np, 0) + 0xcc; - val = (0xfff << 20) | (0x1 << 16); + val = __raw_readl(addr); + + val = (val & 0xffff0000) | (status & 0xffff); } else { pr_err("%s: cannot support non-DT\n", __func__); return; -- cgit v1.1 From 15f504f0c2038b9a0f1569c9ce34def61f0c65be Mon Sep 17 00:00:00 2001 From: Tomasz Figa Date: Sat, 25 May 2013 06:49:43 +0900 Subject: ARM: SAMSUNG: Add names to fimd0 IRQ resources Since commit 1977e6d8 (drm/exynos: change the method for getting the interrupt) the Exynos DRM FIMD driver requires IRQ resources to be named. This patch fixes probe failure in non-DT cases by adding appropriate resource names to fimd0 platform device. Signed-off-by: Tomasz Figa Signed-off-by: Kyungmin Park Signed-off-by: Kukjin Kim --- arch/arm/plat-samsung/devs.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/plat-samsung/devs.c b/arch/arm/plat-samsung/devs.c index 30c2fe2..0f9c3f4 100644 --- a/arch/arm/plat-samsung/devs.c +++ b/arch/arm/plat-samsung/devs.c @@ -311,9 +311,9 @@ struct platform_device s5p_device_jpeg = { #ifdef CONFIG_S5P_DEV_FIMD0 static struct resource s5p_fimd0_resource[] = { [0] = DEFINE_RES_MEM(S5P_PA_FIMD0, SZ_32K), - [1] = DEFINE_RES_IRQ(IRQ_FIMD0_VSYNC), - [2] = DEFINE_RES_IRQ(IRQ_FIMD0_FIFO), - [3] = DEFINE_RES_IRQ(IRQ_FIMD0_SYSTEM), + [1] = DEFINE_RES_IRQ_NAMED(IRQ_FIMD0_VSYNC, "vsync"), + [2] = DEFINE_RES_IRQ_NAMED(IRQ_FIMD0_FIFO, "fifo"), + [3] = DEFINE_RES_IRQ_NAMED(IRQ_FIMD0_SYSTEM, "lcd_sys"), }; struct platform_device s5p_device_fimd0 = { -- cgit v1.1 From b134dc3feaa5136b376c7d2658bbe156bea19e63 Mon Sep 17 00:00:00 2001 From: Tomasz Figa Date: Fri, 17 May 2013 18:24:28 +0200 Subject: ARM: EXYNOS: Fix EINT wake-up mask configuration when pinctrl is used On DT-enabled systems pinctrl-exynos driver is responsible for handling of wake-up EINT interrupts. This patch adjusts wake-up mask configuration code to take wake-up mask value from pinctrl-exynos driver on DT-enabled systems. Signed-off-by: Tomasz Figa Signed-off-by: Kyungmin Park Tested-by: Doug Anderson Signed-off-by: Linus Walleij --- arch/arm/mach-exynos/include/mach/pm-core.h | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-exynos/include/mach/pm-core.h b/arch/arm/mach-exynos/include/mach/pm-core.h index 7dbbfec..296090e 100644 --- a/arch/arm/mach-exynos/include/mach/pm-core.h +++ b/arch/arm/mach-exynos/include/mach/pm-core.h @@ -18,8 +18,15 @@ #ifndef __ASM_ARCH_PM_CORE_H #define __ASM_ARCH_PM_CORE_H __FILE__ +#include #include +#ifdef CONFIG_PINCTRL_EXYNOS +extern u32 exynos_get_eint_wake_mask(void); +#else +static inline u32 exynos_get_eint_wake_mask(void) { return 0xffffffff; } +#endif + static inline void s3c_pm_debug_init_uart(void) { /* nothing here yet */ @@ -27,7 +34,12 @@ static inline void s3c_pm_debug_init_uart(void) static inline void s3c_pm_arch_prepare_irqs(void) { - __raw_writel(s3c_irqwake_eintmask, S5P_EINT_WAKEUP_MASK); + u32 eintmask = s3c_irqwake_eintmask; + + if (of_have_populated_dt()) + eintmask = exynos_get_eint_wake_mask(); + + __raw_writel(eintmask, S5P_EINT_WAKEUP_MASK); __raw_writel(s3c_irqwake_intmask & ~(1 << 31), S5P_WAKEUP_MASK); } -- cgit v1.1 From da9d0fbf5e9aa47492a19588bd0efd18d6d172e0 Mon Sep 17 00:00:00 2001 From: Olof Johansson Date: Thu, 9 May 2013 13:58:19 -0700 Subject: ARM: exynos: defconfig update This turns on a number of configs that are useful on the Chromebook, but also good to have on in general: * USB host and MMC drivers(!) * I2C GPIO arbitration driver * CYAPA trackpad driver * simplefb * CROS EC and keyboard drivers * S5M8767 driver * MAX77686 drivers * MAX8997 driver * DEVTMPFS + mount * DM_CRYPT (as module) * CRYPTOLOOP * HIGHMEM * PRINTK timestamps This also turns off DEBUG_LL, and switches the hardcoded Samsung lowlevel uart to uart 3 (which is only used to show the "uncompressing kernel" message at boot, it seems). Signed-off-by: Olof Johansson Reviewed-by: Doug Anderson Tested-by: Tushar Behera Acked-by: Kukjin Kim --- arch/arm/configs/exynos_defconfig | 54 +++++++++++++++++++++++++++++++++------ 1 file changed, 46 insertions(+), 8 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/configs/exynos_defconfig b/arch/arm/configs/exynos_defconfig index e40b435d..227abf9 100644 --- a/arch/arm/configs/exynos_defconfig +++ b/arch/arm/configs/exynos_defconfig @@ -1,4 +1,4 @@ -CONFIG_EXPERIMENTAL=y +CONFIG_SYSVIPC=y CONFIG_NO_HZ=y CONFIG_HIGH_RES_TIMERS=y CONFIG_BLK_DEV_INITRD=y @@ -7,17 +7,18 @@ CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y # CONFIG_BLK_DEV_BSG is not set CONFIG_PARTITION_ADVANCED=y -CONFIG_EFI_PARTITION=y CONFIG_ARCH_EXYNOS=y -CONFIG_S3C_LOWLEVEL_UART_PORT=1 +CONFIG_S3C_LOWLEVEL_UART_PORT=3 CONFIG_S3C24XX_PWM=y CONFIG_ARCH_EXYNOS5=y CONFIG_MACH_EXYNOS4_DT=y -CONFIG_MACH_EXYNOS5_DT=y CONFIG_SMP=y CONFIG_NR_CPUS=2 CONFIG_PREEMPT=y CONFIG_AEABI=y +CONFIG_HIGHMEM=y +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZBOOT_ROM_BSS=0x0 CONFIG_ARM_APPENDED_DTB=y CONFIG_ARM_ATAG_DTB_COMPAT=y CONFIG_CMDLINE="root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M console=ttySAC1,115200 init=/linuxrc mem=256M" @@ -30,35 +31,58 @@ CONFIG_NET_KEY=y CONFIG_INET=y CONFIG_RFKILL_REGULATOR=y CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y CONFIG_PROC_DEVICETREE=y CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_CRYPTOLOOP=y CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM_SIZE=8192 CONFIG_SCSI=y CONFIG_BLK_DEV_SD=y CONFIG_CHR_DEV_SG=y +CONFIG_MD=y +CONFIG_BLK_DEV_DM=y +CONFIG_DM_CRYPT=m CONFIG_NETDEVICES=y CONFIG_SMSC911X=y CONFIG_USB_USBNET=y CONFIG_USB_NET_SMSC75XX=y CONFIG_USB_NET_SMSC95XX=y CONFIG_INPUT_EVDEV=y -# CONFIG_INPUT_KEYBOARD is not set -# CONFIG_INPUT_MOUSE is not set +CONFIG_KEYBOARD_CROS_EC=y +# CONFIG_MOUSE_PS2 is not set +CONFIG_MOUSE_CYAPA=y CONFIG_INPUT_TOUCHSCREEN=y CONFIG_SERIAL_8250=y CONFIG_SERIAL_SAMSUNG=y CONFIG_SERIAL_SAMSUNG_CONSOLE=y CONFIG_SERIAL_OF_PLATFORM=y CONFIG_HW_RANDOM=y +CONFIG_TCG_TPM=y +CONFIG_TCG_TIS_I2C_INFINEON=y CONFIG_I2C=y +CONFIG_I2C_MUX=y +CONFIG_I2C_ARB_GPIO_CHALLENGE=y +CONFIG_I2C_S3C2410=y +CONFIG_DEBUG_GPIO=y # CONFIG_HWMON is not set +CONFIG_MFD_CROS_EC=y +CONFIG_MFD_CROS_EC_I2C=y +CONFIG_MFD_MAX77686=y +CONFIG_MFD_MAX8997=y +CONFIG_MFD_SEC_CORE=y CONFIG_MFD_TPS65090=y CONFIG_REGULATOR=y CONFIG_REGULATOR_FIXED_VOLTAGE=y CONFIG_REGULATOR_GPIO=y +CONFIG_REGULATOR_MAX8997=y +CONFIG_REGULATOR_MAX77686=y +CONFIG_REGULATOR_S5M8767=y CONFIG_REGULATOR_TPS65090=y CONFIG_FB=y +CONFIG_FB_MODE_HELPERS=y +CONFIG_FB_SIMPLE=y CONFIG_EXYNOS_VIDEO=y CONFIG_EXYNOS_MIPI_DSI=y CONFIG_EXYNOS_DP=y @@ -67,6 +91,20 @@ CONFIG_FONTS=y CONFIG_FONT_7x14=y CONFIG_LOGO=y CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_S5P=y +CONFIG_USB_STORAGE=y +CONFIG_USB_DWC3=y +CONFIG_USB_PHY=y +CONFIG_SAMSUNG_USB2PHY=y +CONFIG_SAMSUNG_USB3PHY=y +CONFIG_MMC=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_S3C=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_IDMAC=y +CONFIG_MMC_DW_EXYNOS=y +CONFIG_COMMON_CLK_MAX77686=y CONFIG_EXT2_FS=y CONFIG_EXT3_FS=y CONFIG_EXT4_FS=y @@ -79,6 +117,7 @@ CONFIG_ROMFS_FS=y CONFIG_NLS_CODEPAGE_437=y CONFIG_NLS_ASCII=y CONFIG_NLS_ISO8859_1=y +CONFIG_PRINTK_TIME=y CONFIG_MAGIC_SYSRQ=y CONFIG_DEBUG_KERNEL=y CONFIG_DETECT_HUNG_TASK=y @@ -87,6 +126,5 @@ CONFIG_DEBUG_SPINLOCK=y CONFIG_DEBUG_MUTEXES=y CONFIG_DEBUG_INFO=y CONFIG_DEBUG_USER=y -CONFIG_DEBUG_LL=y -CONFIG_EARLY_PRINTK=y +CONFIG_CRYPTO_SHA256=y CONFIG_CRC_CCITT=y -- cgit v1.1 From 00dddcaa51f997cdc6dbae3303a31024e29a0fc0 Mon Sep 17 00:00:00 2001 From: Lars Poeschel Date: Tue, 28 May 2013 10:24:57 +0200 Subject: ARM: dts: AM33xx: Fix properties on gpmc node The gpmc driver is actually looking for "gpmc,num-cs" and "gpmc,num-waitpins" properties in DT. The binding doc also states this. Correct the properties in the dts to provide the right values for the gpmc driver. Signed-off-by: Lars Poeschel Acked-by: Peter Korsgaard Acked-by: Pekon Gupta Signed-off-by: Benoit Cousson --- arch/arm/boot/dts/am33xx.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi index 1460d9b..8e1248f 100644 --- a/arch/arm/boot/dts/am33xx.dtsi +++ b/arch/arm/boot/dts/am33xx.dtsi @@ -409,8 +409,8 @@ ti,hwmods = "gpmc"; reg = <0x50000000 0x2000>; interrupts = <100>; - num-cs = <7>; - num-waitpins = <2>; + gpmc,num-cs = <7>; + gpmc,num-waitpins = <2>; #address-cells = <2>; #size-cells = <1>; status = "disabled"; -- cgit v1.1 From 1e68f43b7dcf0e5eee10baeb3cbe4e1ca59db9fd Mon Sep 17 00:00:00 2001 From: Kevin Hilman Date: Fri, 24 May 2013 17:24:21 -0700 Subject: ARM: dts: omap4-panda|sdp: Fix mux for twl6030 IRQ pin and msecure line Earlier commits ensured proper muxing of pins related to proper TWL6030 behavior: see commit 265a2bc8 (ARM: OMAP3: TWL4030: ensure sys_nirq1 is mux'd and wakeup enabled) and commit 1ef43369 (ARM: OMAP4: TWL: mux sys_drm_msecure as output for PMIC). However these only fixed legacy boot and not DT boot. For DT boot, the default mux values need to be set properly in DT. Special thanks to Nishanth Menon for the review and catching some major flaws in earlier versions. Tested on OMAP4430/Panda and OMAP4460/Panda-ES. Cc: Nishanth Menon Cc: Tony Lindgren Signed-off-by: Kevin Hilman Acked-by: Grygorii Strashko [benoit.cousson@linaro.org: Slightly change the subject to align board name with file name] Signed-off-by: Benoit Cousson --- arch/arm/boot/dts/omap4-panda-common.dtsi | 20 ++++++++++++++++++++ arch/arm/boot/dts/omap4-sdp.dts | 20 ++++++++++++++++++++ 2 files changed, 40 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/omap4-panda-common.dtsi b/arch/arm/boot/dts/omap4-panda-common.dtsi index 03bd60d..eeb734e 100644 --- a/arch/arm/boot/dts/omap4-panda-common.dtsi +++ b/arch/arm/boot/dts/omap4-panda-common.dtsi @@ -56,9 +56,23 @@ }; }; +&omap4_pmx_wkup { + pinctrl-names = "default"; + pinctrl-0 = < + &twl6030_wkup_pins + >; + + twl6030_wkup_pins: pinmux_twl6030_wkup_pins { + pinctrl-single,pins = < + 0x14 0x2 /* fref_clk0_out.sys_drm_msecure OUTPUT | MODE2 */ + >; + }; +}; + &omap4_pmx_core { pinctrl-names = "default"; pinctrl-0 = < + &twl6030_pins &twl6040_pins &mcpdm_pins &mcbsp1_pins @@ -66,6 +80,12 @@ &tpd12s015_pins >; + twl6030_pins: pinmux_twl6030_pins { + pinctrl-single,pins = < + 0x15e 0x4118 /* sys_nirq1.sys_nirq1 OMAP_WAKEUP_EN | INPUT_PULLUP | MODE0 */ + >; + }; + twl6040_pins: pinmux_twl6040_pins { pinctrl-single,pins = < 0xe0 0x3 /* hdq_sio.gpio_127 OUTPUT | MODE3 */ diff --git a/arch/arm/boot/dts/omap4-sdp.dts b/arch/arm/boot/dts/omap4-sdp.dts index a35d9cd..98505a2 100644 --- a/arch/arm/boot/dts/omap4-sdp.dts +++ b/arch/arm/boot/dts/omap4-sdp.dts @@ -142,9 +142,23 @@ }; }; +&omap4_pmx_wkup { + pinctrl-names = "default"; + pinctrl-0 = < + &twl6030_wkup_pins + >; + + twl6030_wkup_pins: pinmux_twl6030_wkup_pins { + pinctrl-single,pins = < + 0x14 0x2 /* fref_clk0_out.sys_drm_msecure OUTPUT | MODE2 */ + >; + }; +}; + &omap4_pmx_core { pinctrl-names = "default"; pinctrl-0 = < + &twl6030_pins &twl6040_pins &mcpdm_pins &dmic_pins @@ -179,6 +193,12 @@ >; }; + twl6030_pins: pinmux_twl6030_pins { + pinctrl-single,pins = < + 0x15e 0x4118 /* sys_nirq1.sys_nirq1 OMAP_WAKEUP_EN | INPUT_PULLUP | MODE0 */ + >; + }; + twl6040_pins: pinmux_twl6040_pins { pinctrl-single,pins = < 0xe0 0x3 /* hdq_sio.gpio_127 OUTPUT | MODE3 */ -- cgit v1.1 From 8341613afbc8d65bca8c81158edfb49f36b7ad92 Mon Sep 17 00:00:00 2001 From: Suman Anna Date: Wed, 17 Apr 2013 18:23:15 -0500 Subject: ARM: dts: OMAP5: Fix missing PWM capability to timer nodes OMAP5 has 6 timers (GPTimers 5, 6, 8 to 11) that are capable of PWM. The PWM capability property is missing from the node definitions of couple of timers. Add ti,timer-pwm attribute for timer 5, 6, 8 and 11. Signed-off-by: Suman Anna [benoit.cousson@linaro.org: Update changelog and subject to highlight the fix] Signed-off-by: Benoit Cousson --- arch/arm/boot/dts/omap5.dtsi | 3 +++ 1 file changed, 3 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi index 3dd7ff8..635cae2 100644 --- a/arch/arm/boot/dts/omap5.dtsi +++ b/arch/arm/boot/dts/omap5.dtsi @@ -538,6 +538,7 @@ interrupts = <0 41 0x4>; ti,hwmods = "timer5"; ti,timer-dsp; + ti,timer-pwm; }; timer6: timer@4013a000 { @@ -574,6 +575,7 @@ reg = <0x4803e000 0x80>; interrupts = <0 45 0x4>; ti,hwmods = "timer9"; + ti,timer-pwm; }; timer10: timer@48086000 { @@ -581,6 +583,7 @@ reg = <0x48086000 0x80>; interrupts = <0 46 0x4>; ti,hwmods = "timer10"; + ti,timer-pwm; }; timer11: timer@48088000 { -- cgit v1.1