From da4a686a2cfb077a8bfc1697f597e7f86235b822 Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Wed, 6 Feb 2013 21:17:47 -0600 Subject: ARM: smp_twd: convert to use CLKSRC_OF init Now that we have OF based init with CLKSRC_OF, convert smp_twd init function to use it and covert all callers of twd_local_timer_of_register. Signed-off-by: Rob Herring Cc: Shawn Guo Cc: Sascha Hauer Cc: Russell King Cc: Viresh Kumar Cc: Shiraz Hashim Cc: Srinidhi Kasagar Cc: John Stultz Cc: Thomas Gleixner Cc: linux-omap@vger.kernel.org Cc: spear-devel@list.st.com Reviewed-by: Stephen Warren Acked-by: Santosh Shilimkar Acked-by: Tony Lindgren Acked-by: Linus Walleij --- arch/arm/Kconfig | 1 + arch/arm/include/asm/smp_twd.h | 8 -------- arch/arm/kernel/smp_twd.c | 17 ++++------------- arch/arm/mach-highbank/highbank.c | 5 ++--- arch/arm/mach-imx/mach-imx6q.c | 5 ++--- arch/arm/mach-omap2/timer.c | 2 +- arch/arm/mach-spear13xx/spear13xx.c | 4 ++-- arch/arm/mach-ux500/timer.c | 3 ++- arch/arm/mach-vexpress/v2m.c | 6 +++--- 9 files changed, 17 insertions(+), 34 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 5b71469..5bfd584 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1597,6 +1597,7 @@ config HAVE_ARM_ARCH_TIMER config HAVE_ARM_TWD bool depends on SMP + select CLKSRC_OF if OF help This options enables support for the ARM timer and watchdog unit diff --git a/arch/arm/include/asm/smp_twd.h b/arch/arm/include/asm/smp_twd.h index 0f01f46..7b2899c 100644 --- a/arch/arm/include/asm/smp_twd.h +++ b/arch/arm/include/asm/smp_twd.h @@ -34,12 +34,4 @@ struct twd_local_timer name __initdata = { \ int twd_local_timer_register(struct twd_local_timer *); -#ifdef CONFIG_HAVE_ARM_TWD -void twd_local_timer_of_register(void); -#else -static inline void twd_local_timer_of_register(void) -{ -} -#endif - #endif diff --git a/arch/arm/kernel/smp_twd.c b/arch/arm/kernel/smp_twd.c index 3f25650..90525d9 100644 --- a/arch/arm/kernel/smp_twd.c +++ b/arch/arm/kernel/smp_twd.c @@ -362,25 +362,13 @@ int __init twd_local_timer_register(struct twd_local_timer *tlt) } #ifdef CONFIG_OF -const static struct of_device_id twd_of_match[] __initconst = { - { .compatible = "arm,cortex-a9-twd-timer", }, - { .compatible = "arm,cortex-a5-twd-timer", }, - { .compatible = "arm,arm11mp-twd-timer", }, - { }, -}; - -void __init twd_local_timer_of_register(void) +static void __init twd_local_timer_of_register(struct device_node *np) { - struct device_node *np; int err; if (!is_smp() || !setup_max_cpus) return; - np = of_find_matching_node(NULL, twd_of_match); - if (!np) - return; - twd_ppi = irq_of_parse_and_map(np, 0); if (!twd_ppi) { err = -EINVAL; @@ -398,4 +386,7 @@ void __init twd_local_timer_of_register(void) out: WARN(err, "twd_local_timer_of_register failed (%d)\n", err); } +CLOCKSOURCE_OF_DECLARE(arm_twd_a9, "arm,cortex-a9-twd-timer", twd_local_timer_of_register); +CLOCKSOURCE_OF_DECLARE(arm_twd_a5, "arm,cortex-a5-twd-timer", twd_local_timer_of_register); +CLOCKSOURCE_OF_DECLARE(arm_twd_11mp, "arm,arm11mp-twd-timer", twd_local_timer_of_register); #endif diff --git a/arch/arm/mach-highbank/highbank.c b/arch/arm/mach-highbank/highbank.c index a4f9f50..76c1170 100644 --- a/arch/arm/mach-highbank/highbank.c +++ b/arch/arm/mach-highbank/highbank.c @@ -32,7 +32,6 @@ #include #include #include -#include #include #include #include @@ -119,10 +118,10 @@ static void __init highbank_timer_init(void) sp804_clocksource_and_sched_clock_init(timer_base + 0x20, "timer1"); sp804_clockevents_init(timer_base, irq, "timer0"); - twd_local_timer_of_register(); - arch_timer_of_register(); arch_timer_sched_clock_init(); + + clocksource_of_init(); } static void highbank_power_off(void) diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c index 9ffd103..b59ddcb 100644 --- a/arch/arm/mach-imx/mach-imx6q.c +++ b/arch/arm/mach-imx/mach-imx6q.c @@ -12,6 +12,7 @@ #include #include +#include #include #include #include @@ -28,11 +29,9 @@ #include #include #include -#include #include #include #include -#include #include #include "common.h" @@ -292,7 +291,7 @@ static void __init imx6q_init_irq(void) static void __init imx6q_timer_init(void) { mx6q_clocks_init(); - twd_local_timer_of_register(); + clocksource_of_init(); imx_print_silicon_rev("i.MX6Q", imx6q_revision()); } diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c index 2bdd4cf..4fd8025 100644 --- a/arch/arm/mach-omap2/timer.c +++ b/arch/arm/mach-omap2/timer.c @@ -597,7 +597,7 @@ void __init omap4_local_timer_init(void) int err; if (of_have_populated_dt()) { - twd_local_timer_of_register(); + clocksource_of_init(); return; } diff --git a/arch/arm/mach-spear13xx/spear13xx.c b/arch/arm/mach-spear13xx/spear13xx.c index c7d2b4a..25a1019 100644 --- a/arch/arm/mach-spear13xx/spear13xx.c +++ b/arch/arm/mach-spear13xx/spear13xx.c @@ -15,12 +15,12 @@ #include #include +#include #include #include #include #include #include -#include #include #include #include @@ -179,5 +179,5 @@ void __init spear13xx_timer_init(void) clk_put(pclk); spear_setup_of_timer(); - twd_local_timer_of_register(); + clocksource_of_init(); } diff --git a/arch/arm/mach-ux500/timer.c b/arch/arm/mach-ux500/timer.c index a6af0b8..d07bbe7 100644 --- a/arch/arm/mach-ux500/timer.c +++ b/arch/arm/mach-ux500/timer.c @@ -7,6 +7,7 @@ #include #include #include +#include #include #include #include @@ -32,7 +33,7 @@ static void __init ux500_twd_init(void) twd_local_timer = &u8500_twd_local_timer; if (of_have_populated_dt()) - twd_local_timer_of_register(); + clocksource_of_init(); else { err = twd_local_timer_register(twd_local_timer); if (err) diff --git a/arch/arm/mach-vexpress/v2m.c b/arch/arm/mach-vexpress/v2m.c index 915683c..d0ad789 100644 --- a/arch/arm/mach-vexpress/v2m.c +++ b/arch/arm/mach-vexpress/v2m.c @@ -5,6 +5,7 @@ #include #include #include +#include #include #include #include @@ -25,7 +26,6 @@ #include #include #include -#include #include #include #include @@ -435,6 +435,7 @@ static void __init v2m_dt_timer_init(void) vexpress_clk_of_init(); + clocksource_of_init(); do { node = of_find_compatible_node(node, NULL, "arm,sp804"); } while (node && vexpress_get_site_by_node(node) != VEXPRESS_SITE_MB); @@ -445,8 +446,7 @@ static void __init v2m_dt_timer_init(void) irq_of_parse_and_map(node, 0)); } - if (arch_timer_of_register() != 0) - twd_local_timer_of_register(); + arch_timer_of_register(); if (arch_timer_sched_clock_init() != 0) versatile_sched_clock_init(vexpress_get_24mhz_clock_base(), -- cgit v1.1 From d4fe49e54527f6f4c3b0ab2ca2bad68e27bf0d00 Mon Sep 17 00:00:00 2001 From: Barry Song Date: Mon, 18 Mar 2013 15:04:38 +0800 Subject: arm: prima2: add new SiRFatlas6 machine in common board SiRFatlas6's machine definition is almost seem with SiRFprimaII except that prima2 has a 256MB DMA zone. This patch adds SiRFatlas6 machine in common board files, and also adds atlas6 arch node in Kconfig. Signed-off-by: Barry Song Signed-off-by: Arnd Bergmann --- arch/arm/mach-prima2/Kconfig | 10 +++++++++- arch/arm/mach-prima2/common.c | 21 +++++++++++++++++++++ 2 files changed, 30 insertions(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-prima2/Kconfig b/arch/arm/mach-prima2/Kconfig index 4f7379f..b3be799 100644 --- a/arch/arm/mach-prima2/Kconfig +++ b/arch/arm/mach-prima2/Kconfig @@ -1,6 +1,14 @@ if ARCH_SIRF -menu "CSR SiRF primaII/Marco/Polo Specific Features" +menu "CSR SiRF atlas6/primaII/Marco/Polo Specific Features" + +config ARCH_ATLAS6 + bool "CSR SiRFSoC ATLAS6 ARM Cortex A9 Platform" + default y + select CPU_V7 + select SIRF_IRQ + help + Support for CSR SiRFSoC ARM Cortex A9 Platform config ARCH_PRIMA2 bool "CSR SiRFSoC PRIMA2 ARM Cortex A9 Platform" diff --git a/arch/arm/mach-prima2/common.c b/arch/arm/mach-prima2/common.c index 2d57aa4..72efb4f 100644 --- a/arch/arm/mach-prima2/common.c +++ b/arch/arm/mach-prima2/common.c @@ -37,6 +37,27 @@ static __init void sirfsoc_map_io(void) sirfsoc_map_scu(); } +#ifdef CONFIG_ARCH_ATLAS6 +static const char *atlas6_dt_match[] __initdata = { + "sirf,atlas6", + NULL +}; + +DT_MACHINE_START(ATLAS6_DT, "Generic ATLAS6 (Flattened Device Tree)") + /* Maintainer: Barry Song */ + .map_io = sirfsoc_map_io, + .init_irq = sirfsoc_of_irq_init, + .init_time = sirfsoc_prima2_timer_init, +#ifdef CONFIG_MULTI_IRQ_HANDLER + .handle_irq = sirfsoc_handle_irq, +#endif + .init_machine = sirfsoc_mach_init, + .init_late = sirfsoc_init_late, + .dt_compat = atlas6_dt_match, + .restart = sirfsoc_restart, +MACHINE_END +#endif + #ifdef CONFIG_ARCH_PRIMA2 static const char *prima2_dt_match[] __initdata = { "sirf,prima2", -- cgit v1.1 From 5fa2f9af76f780a54f59579e1e71f1e85a9b6c64 Mon Sep 17 00:00:00 2001 From: Barry Song Date: Mon, 18 Mar 2013 15:04:39 +0800 Subject: ARM/dts: prima2: add .dtsi for atlas6 and .dts for atla6-evb board atlas6.dtsi is basically a copy of prima2.dtsi as most components are compatible with prima2 except that: 1. node of l2 cache is deleted 2. node multimedia engine is deleted 3. node of sata is deleted 4. node of sdmmc4 is deleted 5. powervr is moved to "powervr,sgx510" 6. pinctrl is moved to atlas6 as pinmux layout has big changes in atlas6 7. clock is moved to atlas6 as clock layout has changes in atlas6 Signed-off-by: Barry Song Signed-off-by: Jiansong Chen --- arch/arm/boot/dts/atlas6-evb.dts | 78 +++++ arch/arm/boot/dts/atlas6.dtsi | 668 +++++++++++++++++++++++++++++++++++++++ 2 files changed, 746 insertions(+) create mode 100644 arch/arm/boot/dts/atlas6-evb.dts create mode 100644 arch/arm/boot/dts/atlas6.dtsi (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/atlas6-evb.dts b/arch/arm/boot/dts/atlas6-evb.dts new file mode 100644 index 0000000..ab042ca --- /dev/null +++ b/arch/arm/boot/dts/atlas6-evb.dts @@ -0,0 +1,78 @@ +/* + * DTS file for CSR SiRFatlas6 Evaluation Board + * + * Copyright (c) 2012 Cambridge Silicon Radio Limited, a CSR plc group company. + * + * Licensed under GPLv2 or later. + */ + +/dts-v1/; + +/include/ "atlas6.dtsi" + +/ { + model = "CSR SiRFatlas6 Evaluation Board"; + compatible = "sirf,atlas6-cb", "sirf,atlas6"; + + memory { + reg = <0x00000000 0x20000000>; + }; + + axi { + peri-iobg { + uart@b0060000 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins_a>; + }; + spi@b00d0000 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&spi0_pins_a>; + spi@0 { + compatible = "spidev"; + reg = <0>; + spi-max-frequency = <1000000>; + }; + }; + spi@b0170000 { + pinctrl-names = "default"; + pinctrl-0 = <&spi1_pins_a>; + }; + i2c0: i2c@b00e0000 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins_a>; + lcd@40 { + compatible = "sirf,lcd"; + reg = <0x40>; + }; + }; + + }; + disp-iobg { + lcd@90010000 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&lcd_24pins_a>; + }; + }; + }; + display: display@0 { + panels { + panel0: panel@0 { + panel-name = "Innolux TFT"; + hactive = <800>; + vactive = <480>; + left_margin = <20>; + right_margin = <234>; + upper_margin = <3>; + lower_margin = <41>; + hsync_len = <3>; + vsync_len = <2>; + pixclock = <33264000>; + sync = <3>; + timing = <0x88>; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/atlas6.dtsi b/arch/arm/boot/dts/atlas6.dtsi new file mode 100644 index 0000000..7d1a279 --- /dev/null +++ b/arch/arm/boot/dts/atlas6.dtsi @@ -0,0 +1,668 @@ +/* + * DTS file for CSR SiRFatlas6 SoC + * + * Copyright (c) 2012 Cambridge Silicon Radio Limited, a CSR plc group company. + * + * Licensed under GPLv2 or later. + */ + +/include/ "skeleton.dtsi" +/ { + compatible = "sirf,atlas6"; + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&intc>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + reg = <0x0>; + d-cache-line-size = <32>; + i-cache-line-size = <32>; + d-cache-size = <32768>; + i-cache-size = <32768>; + /* from bootloader */ + timebase-frequency = <0>; + bus-frequency = <0>; + clock-frequency = <0>; + }; + }; + + axi { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x40000000 0x40000000 0x80000000>; + + intc: interrupt-controller@80020000 { + #interrupt-cells = <1>; + interrupt-controller; + compatible = "sirf,prima2-intc"; + reg = <0x80020000 0x1000>; + }; + + sys-iobg { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x88000000 0x88000000 0x40000>; + + clks: clock-controller@88000000 { + compatible = "sirf,atlas6-clkc"; + reg = <0x88000000 0x1000>; + interrupts = <3>; + #clock-cells = <1>; + }; + + reset-controller@88010000 { + compatible = "sirf,prima2-rstc"; + reg = <0x88010000 0x1000>; + }; + + rsc-controller@88020000 { + compatible = "sirf,prima2-rsc"; + reg = <0x88020000 0x1000>; + }; + }; + + mem-iobg { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x90000000 0x90000000 0x10000>; + + memory-controller@90000000 { + compatible = "sirf,prima2-memc"; + reg = <0x90000000 0x10000>; + interrupts = <27>; + clocks = <&clks 5>; + }; + }; + + disp-iobg { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x90010000 0x90010000 0x30000>; + + lcd@90010000 { + compatible = "sirf,prima2-lcd"; + reg = <0x90010000 0x20000>; + interrupts = <30>; + clocks = <&clks 34>; + display=<&display>; + /* later transfer to pwm */ + bl-gpio = <&gpio 7 0>; + default-panel = <&panel0>; + }; + + vpp@90020000 { + compatible = "sirf,prima2-vpp"; + reg = <0x90020000 0x10000>; + interrupts = <31>; + clocks = <&clks 35>; + }; + }; + + graphics-iobg { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x98000000 0x98000000 0x8000000>; + + graphics@98000000 { + compatible = "powervr,sgx510"; + reg = <0x98000000 0x8000000>; + interrupts = <6>; + clocks = <&clks 32>; + }; + }; + + dsp-iobg { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0xa8000000 0xa8000000 0x2000000>; + + dspif@a8000000 { + compatible = "sirf,prima2-dspif"; + reg = <0xa8000000 0x10000>; + interrupts = <9>; + }; + + gps@a8010000 { + compatible = "sirf,prima2-gps"; + reg = <0xa8010000 0x10000>; + interrupts = <7>; + clocks = <&clks 9>; + }; + + dsp@a9000000 { + compatible = "sirf,prima2-dsp"; + reg = <0xa9000000 0x1000000>; + interrupts = <8>; + clocks = <&clks 8>; + }; + }; + + peri-iobg { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0xb0000000 0xb0000000 0x180000>, + <0x56000000 0x56000000 0x1b00000>; + + timer@b0020000 { + compatible = "sirf,prima2-tick"; + reg = <0xb0020000 0x1000>; + interrupts = <0>; + }; + + nand@b0030000 { + compatible = "sirf,prima2-nand"; + reg = <0xb0030000 0x10000>; + interrupts = <41>; + clocks = <&clks 26>; + }; + + audio@b0040000 { + compatible = "sirf,prima2-audio"; + reg = <0xb0040000 0x10000>; + interrupts = <35>; + clocks = <&clks 27>; + }; + + uart0: uart@b0050000 { + cell-index = <0>; + compatible = "sirf,prima2-uart"; + reg = <0xb0050000 0x1000>; + interrupts = <17>; + fifosize = <128>; + clocks = <&clks 13>; + }; + + uart1: uart@b0060000 { + cell-index = <1>; + compatible = "sirf,prima2-uart"; + reg = <0xb0060000 0x1000>; + interrupts = <18>; + fifosize = <32>; + clocks = <&clks 14>; + }; + + uart2: uart@b0070000 { + cell-index = <2>; + compatible = "sirf,prima2-uart"; + reg = <0xb0070000 0x1000>; + interrupts = <19>; + fifosize = <128>; + clocks = <&clks 15>; + }; + + usp0: usp@b0080000 { + cell-index = <0>; + compatible = "sirf,prima2-usp"; + reg = <0xb0080000 0x10000>; + interrupts = <20>; + clocks = <&clks 28>; + }; + + usp1: usp@b0090000 { + cell-index = <1>; + compatible = "sirf,prima2-usp"; + reg = <0xb0090000 0x10000>; + interrupts = <21>; + clocks = <&clks 29>; + }; + + dmac0: dma-controller@b00b0000 { + cell-index = <0>; + compatible = "sirf,prima2-dmac"; + reg = <0xb00b0000 0x10000>; + interrupts = <12>; + clocks = <&clks 24>; + }; + + dmac1: dma-controller@b0160000 { + cell-index = <1>; + compatible = "sirf,prima2-dmac"; + reg = <0xb0160000 0x10000>; + interrupts = <13>; + clocks = <&clks 25>; + }; + + vip@b00C0000 { + compatible = "sirf,prima2-vip"; + reg = <0xb00C0000 0x10000>; + clocks = <&clks 31>; + }; + + spi0: spi@b00d0000 { + cell-index = <0>; + compatible = "sirf,prima2-spi"; + reg = <0xb00d0000 0x10000>; + interrupts = <15>; + sirf,spi-num-chipselects = <1>; + cs-gpios = <&gpio 0 0>; + sirf,spi-dma-rx-channel = <25>; + sirf,spi-dma-tx-channel = <20>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clks 19>; + status = "disabled"; + }; + + spi1: spi@b0170000 { + cell-index = <1>; + compatible = "sirf,prima2-spi"; + reg = <0xb0170000 0x10000>; + interrupts = <16>; + clocks = <&clks 20>; + status = "disabled"; + }; + + i2c0: i2c@b00e0000 { + cell-index = <0>; + compatible = "sirf,prima2-i2c"; + reg = <0xb00e0000 0x10000>; + interrupts = <24>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clks 17>; + }; + + i2c1: i2c@b00f0000 { + cell-index = <1>; + compatible = "sirf,prima2-i2c"; + reg = <0xb00f0000 0x10000>; + interrupts = <25>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clks 18>; + }; + + tsc@b0110000 { + compatible = "sirf,prima2-tsc"; + reg = <0xb0110000 0x10000>; + interrupts = <33>; + clocks = <&clks 16>; + }; + + gpio: pinctrl@b0120000 { + #gpio-cells = <2>; + #interrupt-cells = <2>; + compatible = "sirf,atlas6-pinctrl"; + reg = <0xb0120000 0x10000>; + interrupts = <43 44 45 46 47>; + gpio-controller; + interrupt-controller; + + lcd_16pins_a: lcd0@0 { + lcd { + sirf,pins = "lcd_16bitsgrp"; + sirf,function = "lcd_16bits"; + }; + }; + lcd_18pins_a: lcd0@1 { + lcd { + sirf,pins = "lcd_18bitsgrp"; + sirf,function = "lcd_18bits"; + }; + }; + lcd_24pins_a: lcd0@2 { + lcd { + sirf,pins = "lcd_24bitsgrp"; + sirf,function = "lcd_24bits"; + }; + }; + lcdrom_pins_a: lcdrom0@0 { + lcd { + sirf,pins = "lcdromgrp"; + sirf,function = "lcdrom"; + }; + }; + uart0_pins_a: uart0@0 { + uart { + sirf,pins = "uart0grp"; + sirf,function = "uart0"; + }; + }; + uart1_pins_a: uart1@0 { + uart { + sirf,pins = "uart1grp"; + sirf,function = "uart1"; + }; + }; + uart2_pins_a: uart2@0 { + uart { + sirf,pins = "uart2grp"; + sirf,function = "uart2"; + }; + }; + uart2_noflow_pins_a: uart2@1 { + uart { + sirf,pins = "uart2_nostreamctrlgrp"; + sirf,function = "uart2_nostreamctrl"; + }; + }; + spi0_pins_a: spi0@0 { + spi { + sirf,pins = "spi0grp"; + sirf,function = "spi0"; + }; + }; + spi1_pins_a: spi1@0 { + spi { + sirf,pins = "spi1grp"; + sirf,function = "spi1"; + }; + }; + i2c0_pins_a: i2c0@0 { + i2c { + sirf,pins = "i2c0grp"; + sirf,function = "i2c0"; + }; + }; + i2c1_pins_a: i2c1@0 { + i2c { + sirf,pins = "i2c1grp"; + sirf,function = "i2c1"; + }; + }; + pwm0_pins_a: pwm0@0 { + pwm { + sirf,pins = "pwm0grp"; + sirf,function = "pwm0"; + }; + }; + pwm1_pins_a: pwm1@0 { + pwm { + sirf,pins = "pwm1grp"; + sirf,function = "pwm1"; + }; + }; + pwm2_pins_a: pwm2@0 { + pwm { + sirf,pins = "pwm2grp"; + sirf,function = "pwm2"; + }; + }; + pwm3_pins_a: pwm3@0 { + pwm { + sirf,pins = "pwm3grp"; + sirf,function = "pwm3"; + }; + }; + pwm4_pins_a: pwm4@0 { + pwm { + sirf,pins = "pwm4grp"; + sirf,function = "pwm4"; + }; + }; + gps_pins_a: gps@0 { + gps { + sirf,pins = "gpsgrp"; + sirf,function = "gps"; + }; + }; + vip_pins_a: vip@0 { + vip { + sirf,pins = "vipgrp"; + sirf,function = "vip"; + }; + }; + sdmmc0_pins_a: sdmmc0@0 { + sdmmc0 { + sirf,pins = "sdmmc0grp"; + sirf,function = "sdmmc0"; + }; + }; + sdmmc1_pins_a: sdmmc1@0 { + sdmmc1 { + sirf,pins = "sdmmc1grp"; + sirf,function = "sdmmc1"; + }; + }; + sdmmc2_pins_a: sdmmc2@0 { + sdmmc2 { + sirf,pins = "sdmmc2grp"; + sirf,function = "sdmmc2"; + }; + }; + sdmmc2_nowp_pins_a: sdmmc2_nowp@0 { + sdmmc2_nowp { + sirf,pins = "sdmmc2_nowpgrp"; + sirf,function = "sdmmc2_nowp"; + }; + }; + sdmmc3_pins_a: sdmmc3@0 { + sdmmc3 { + sirf,pins = "sdmmc3grp"; + sirf,function = "sdmmc3"; + }; + }; + sdmmc5_pins_a: sdmmc5@0 { + sdmmc5 { + sirf,pins = "sdmmc5grp"; + sirf,function = "sdmmc5"; + }; + }; + i2s_pins_a: i2s@0 { + i2s { + sirf,pins = "i2sgrp"; + sirf,function = "i2s"; + }; + }; + i2s_no_din_pins_a: i2s_no_din@0 { + i2s_no_din { + sirf,pins = "i2s_no_dingrp"; + sirf,function = "i2s_no_din"; + }; + }; + i2s_6chn_pins_a: i2s_6chn@0 { + i2s_6chn { + sirf,pins = "i2s_6chngrp"; + sirf,function = "i2s_6chn"; + }; + }; + ac97_pins_a: ac97@0 { + ac97 { + sirf,pins = "ac97grp"; + sirf,function = "ac97"; + }; + }; + nand_pins_a: nand@0 { + nand { + sirf,pins = "nandgrp"; + sirf,function = "nand"; + }; + }; + usp0_pins_a: usp0@0 { + usp0 { + sirf,pins = "usp0grp"; + sirf,function = "usp0"; + }; + }; + usp1_pins_a: usp1@0 { + usp1 { + sirf,pins = "usp1grp"; + sirf,function = "usp1"; + }; + }; + usb0_upli_drvbus_pins_a: usb0_upli_drvbus@0 { + usb0_upli_drvbus { + sirf,pins = "usb0_upli_drvbusgrp"; + sirf,function = "usb0_upli_drvbus"; + }; + }; + usb1_utmi_drvbus_pins_a: usb1_utmi_drvbus@0 { + usb1_utmi_drvbus { + sirf,pins = "usb1_utmi_drvbusgrp"; + sirf,function = "usb1_utmi_drvbus"; + }; + }; + warm_rst_pins_a: warm_rst@0 { + warm_rst { + sirf,pins = "warm_rstgrp"; + sirf,function = "warm_rst"; + }; + }; + pulse_count_pins_a: pulse_count@0 { + pulse_count { + sirf,pins = "pulse_countgrp"; + sirf,function = "pulse_count"; + }; + }; + cko0_rst_pins_a: cko0_rst@0 { + cko0_rst { + sirf,pins = "cko0_rstgrp"; + sirf,function = "cko0_rst"; + }; + }; + cko1_rst_pins_a: cko1_rst@0 { + cko1_rst { + sirf,pins = "cko1_rstgrp"; + sirf,function = "cko1_rst"; + }; + }; + }; + + pwm@b0130000 { + compatible = "sirf,prima2-pwm"; + reg = <0xb0130000 0x10000>; + clocks = <&clks 21>; + }; + + efusesys@b0140000 { + compatible = "sirf,prima2-efuse"; + reg = <0xb0140000 0x10000>; + clocks = <&clks 22>; + }; + + pulsec@b0150000 { + compatible = "sirf,prima2-pulsec"; + reg = <0xb0150000 0x10000>; + interrupts = <48>; + clocks = <&clks 23>; + }; + + pci-iobg { + compatible = "sirf,prima2-pciiobg", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x56000000 0x56000000 0x1b00000>; + + sd0: sdhci@56000000 { + cell-index = <0>; + compatible = "sirf,prima2-sdhc"; + reg = <0x56000000 0x100000>; + interrupts = <38>; + bus-width = <8>; + clocks = <&clks 36>; + }; + + sd1: sdhci@56100000 { + cell-index = <1>; + compatible = "sirf,prima2-sdhc"; + reg = <0x56100000 0x100000>; + interrupts = <38>; + status = "disabled"; + clocks = <&clks 36>; + }; + + sd2: sdhci@56200000 { + cell-index = <2>; + compatible = "sirf,prima2-sdhc"; + reg = <0x56200000 0x100000>; + interrupts = <23>; + status = "disabled"; + clocks = <&clks 37>; + }; + + sd3: sdhci@56300000 { + cell-index = <3>; + compatible = "sirf,prima2-sdhc"; + reg = <0x56300000 0x100000>; + interrupts = <23>; + status = "disabled"; + clocks = <&clks 37>; + }; + + sd5: sdhci@56500000 { + cell-index = <5>; + compatible = "sirf,prima2-sdhc"; + reg = <0x56500000 0x100000>; + interrupts = <39>; + status = "disabled"; + clocks = <&clks 38>; + }; + + pci-copy@57900000 { + compatible = "sirf,prima2-pcicp"; + reg = <0x57900000 0x100000>; + interrupts = <40>; + }; + + rom-interface@57a00000 { + compatible = "sirf,prima2-romif"; + reg = <0x57a00000 0x100000>; + }; + }; + }; + + rtc-iobg { + compatible = "sirf,prima2-rtciobg", "sirf-prima2-rtciobg-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x80030000 0x10000>; + + gpsrtc@1000 { + compatible = "sirf,prima2-gpsrtc"; + reg = <0x1000 0x1000>; + interrupts = <55 56 57>; + }; + + sysrtc@2000 { + compatible = "sirf,prima2-sysrtc"; + reg = <0x2000 0x1000>; + interrupts = <52 53 54>; + }; + + pwrc@3000 { + compatible = "sirf,prima2-pwrc"; + reg = <0x3000 0x1000>; + interrupts = <32>; + }; + }; + + uus-iobg { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0xb8000000 0xb8000000 0x40000>; + + usb0: usb@b00e0000 { + compatible = "chipidea,ci13611a-prima2"; + reg = <0xb8000000 0x10000>; + interrupts = <10>; + clocks = <&clks 40>; + }; + + usb1: usb@b00f0000 { + compatible = "chipidea,ci13611a-prima2"; + reg = <0xb8010000 0x10000>; + interrupts = <11>; + clocks = <&clks 41>; + }; + + security@b00f0000 { + compatible = "sirf,prima2-security"; + reg = <0xb8030000 0x10000>; + interrupts = <42>; + clocks = <&clks 7>; + }; + }; + }; +}; -- cgit v1.1 From 67d71344fd09223820eb9de39b597ec29f035e89 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Tue, 19 Mar 2013 15:31:08 +0100 Subject: ARM: sirf: fix prima2 interrupt lookup We must not read the interrupts property manually but instead use irq_of_parse_and_map() to guarantee that we get the correct interrupt number once we stop using the legacy IRQ domain. Signed-off-by: Arnd Bergmann Tested-by: Barry Song --- arch/arm/mach-prima2/timer-prima2.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-prima2/timer-prima2.c b/arch/arm/mach-prima2/timer-prima2.c index 6da584f..9829083 100644 --- a/arch/arm/mach-prima2/timer-prima2.c +++ b/arch/arm/mach-prima2/timer-prima2.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #include #include @@ -223,7 +224,6 @@ static struct of_device_id timer_ids[] = { static void __init sirfsoc_of_timer_map(void) { struct device_node *np; - const unsigned int *intspec; np = of_find_matching_node(NULL, timer_ids); if (!np) @@ -233,9 +233,7 @@ static void __init sirfsoc_of_timer_map(void) panic("unable to map timer cpu registers\n"); /* Get the interrupts property */ - intspec = of_get_property(np, "interrupts", NULL); - BUG_ON(!intspec); - sirfsoc_timer_irq.irq = be32_to_cpup(intspec); + sirfsoc_timer_irq.irq = irq_of_parse_and_map(np, 0); of_node_put(np); } -- cgit v1.1 From 60dbd7680f069c07525a825d805fd2644eae92e6 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Tue, 19 Mar 2013 11:21:44 +0100 Subject: ARM: sirf: move irq driver to drivers/irqchip This updates the irqchip drier for prima2 to the current practices by moving it into drivers/irqchip and integrating it into the irqchip_init infrastructure. We also now use a linear irq domain as a preparation for sparse IRQ suport. Signed-off-by: Arnd Bergmann Cc: Thomas Gleixner --- arch/arm/mach-prima2/Makefile | 1 - arch/arm/mach-prima2/common.c | 10 +--- arch/arm/mach-prima2/irq.c | 129 ------------------------------------------ 3 files changed, 2 insertions(+), 138 deletions(-) delete mode 100644 arch/arm/mach-prima2/irq.c (limited to 'arch/arm') diff --git a/arch/arm/mach-prima2/Makefile b/arch/arm/mach-prima2/Makefile index bfe360c..5fdff7e 100644 --- a/arch/arm/mach-prima2/Makefile +++ b/arch/arm/mach-prima2/Makefile @@ -4,7 +4,6 @@ obj-y += rtciobrg.o obj-$(CONFIG_DEBUG_LL) += lluart.o obj-$(CONFIG_CACHE_L2X0) += l2x0.o obj-$(CONFIG_SUSPEND) += pm.o sleep.o -obj-$(CONFIG_SIRF_IRQ) += irq.o obj-$(CONFIG_SMP) += platsmp.o headsmp.o obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o obj-$(CONFIG_ARCH_PRIMA2) += timer-prima2.o diff --git a/arch/arm/mach-prima2/common.c b/arch/arm/mach-prima2/common.c index 72efb4f..15c14df 100644 --- a/arch/arm/mach-prima2/common.c +++ b/arch/arm/mach-prima2/common.c @@ -46,11 +46,8 @@ static const char *atlas6_dt_match[] __initdata = { DT_MACHINE_START(ATLAS6_DT, "Generic ATLAS6 (Flattened Device Tree)") /* Maintainer: Barry Song */ .map_io = sirfsoc_map_io, - .init_irq = sirfsoc_of_irq_init, + .init_irq = irqchip_init, .init_time = sirfsoc_prima2_timer_init, -#ifdef CONFIG_MULTI_IRQ_HANDLER - .handle_irq = sirfsoc_handle_irq, -#endif .init_machine = sirfsoc_mach_init, .init_late = sirfsoc_init_late, .dt_compat = atlas6_dt_match, @@ -67,11 +64,8 @@ static const char *prima2_dt_match[] __initdata = { DT_MACHINE_START(PRIMA2_DT, "Generic PRIMA2 (Flattened Device Tree)") /* Maintainer: Barry Song */ .map_io = sirfsoc_map_io, - .init_irq = sirfsoc_of_irq_init, + .init_irq = irqchip_init, .init_time = sirfsoc_prima2_timer_init, -#ifdef CONFIG_MULTI_IRQ_HANDLER - .handle_irq = sirfsoc_handle_irq, -#endif .dma_zone_size = SZ_256M, .init_machine = sirfsoc_mach_init, .init_late = sirfsoc_init_late, diff --git a/arch/arm/mach-prima2/irq.c b/arch/arm/mach-prima2/irq.c deleted file mode 100644 index 6c0f3e9..0000000 --- a/arch/arm/mach-prima2/irq.c +++ /dev/null @@ -1,129 +0,0 @@ -/* - * interrupt controller support for CSR SiRFprimaII - * - * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company. - * - * Licensed under GPLv2 or later. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#define SIRFSOC_INT_RISC_MASK0 0x0018 -#define SIRFSOC_INT_RISC_MASK1 0x001C -#define SIRFSOC_INT_RISC_LEVEL0 0x0020 -#define SIRFSOC_INT_RISC_LEVEL1 0x0024 -#define SIRFSOC_INIT_IRQ_ID 0x0038 - -void __iomem *sirfsoc_intc_base; - -static __init void -sirfsoc_alloc_gc(void __iomem *base, unsigned int irq_start, unsigned int num) -{ - struct irq_chip_generic *gc; - struct irq_chip_type *ct; - - gc = irq_alloc_generic_chip("SIRFINTC", 1, irq_start, base, handle_level_irq); - ct = gc->chip_types; - - ct->chip.irq_mask = irq_gc_mask_clr_bit; - ct->chip.irq_unmask = irq_gc_mask_set_bit; - ct->regs.mask = SIRFSOC_INT_RISC_MASK0; - - irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE, IRQ_NOREQUEST, 0); -} - -static __init void sirfsoc_irq_init(void) -{ - sirfsoc_alloc_gc(sirfsoc_intc_base, 0, 32); - sirfsoc_alloc_gc(sirfsoc_intc_base + 4, 32, - SIRFSOC_INTENAL_IRQ_END + 1 - 32); - - writel_relaxed(0, sirfsoc_intc_base + SIRFSOC_INT_RISC_LEVEL0); - writel_relaxed(0, sirfsoc_intc_base + SIRFSOC_INT_RISC_LEVEL1); - - writel_relaxed(0, sirfsoc_intc_base + SIRFSOC_INT_RISC_MASK0); - writel_relaxed(0, sirfsoc_intc_base + SIRFSOC_INT_RISC_MASK1); -} - -asmlinkage void __exception_irq_entry sirfsoc_handle_irq(struct pt_regs *regs) -{ - u32 irqstat, irqnr; - - irqstat = readl_relaxed(sirfsoc_intc_base + SIRFSOC_INIT_IRQ_ID); - irqnr = irqstat & 0xff; - - handle_IRQ(irqnr, regs); -} - -static struct of_device_id intc_ids[] = { - { .compatible = "sirf,prima2-intc" }, - {}, -}; - -void __init sirfsoc_of_irq_init(void) -{ - struct device_node *np; - - np = of_find_matching_node(NULL, intc_ids); - if (!np) - return; - - sirfsoc_intc_base = of_iomap(np, 0); - if (!sirfsoc_intc_base) - panic("unable to map intc cpu registers\n"); - - irq_domain_add_legacy(np, SIRFSOC_INTENAL_IRQ_END + 1, 0, 0, - &irq_domain_simple_ops, NULL); - - of_node_put(np); - - sirfsoc_irq_init(); -} - -struct sirfsoc_irq_status { - u32 mask0; - u32 mask1; - u32 level0; - u32 level1; -}; - -static struct sirfsoc_irq_status sirfsoc_irq_st; - -static int sirfsoc_irq_suspend(void) -{ - sirfsoc_irq_st.mask0 = readl_relaxed(sirfsoc_intc_base + SIRFSOC_INT_RISC_MASK0); - sirfsoc_irq_st.mask1 = readl_relaxed(sirfsoc_intc_base + SIRFSOC_INT_RISC_MASK1); - sirfsoc_irq_st.level0 = readl_relaxed(sirfsoc_intc_base + SIRFSOC_INT_RISC_LEVEL0); - sirfsoc_irq_st.level1 = readl_relaxed(sirfsoc_intc_base + SIRFSOC_INT_RISC_LEVEL1); - - return 0; -} - -static void sirfsoc_irq_resume(void) -{ - writel_relaxed(sirfsoc_irq_st.mask0, sirfsoc_intc_base + SIRFSOC_INT_RISC_MASK0); - writel_relaxed(sirfsoc_irq_st.mask1, sirfsoc_intc_base + SIRFSOC_INT_RISC_MASK1); - writel_relaxed(sirfsoc_irq_st.level0, sirfsoc_intc_base + SIRFSOC_INT_RISC_LEVEL0); - writel_relaxed(sirfsoc_irq_st.level1, sirfsoc_intc_base + SIRFSOC_INT_RISC_LEVEL1); -} - -static struct syscore_ops sirfsoc_irq_syscore_ops = { - .suspend = sirfsoc_irq_suspend, - .resume = sirfsoc_irq_resume, -}; - -static int __init sirfsoc_irq_pm_init(void) -{ - register_syscore_ops(&sirfsoc_irq_syscore_ops); - return 0; -} -device_initcall(sirfsoc_irq_pm_init); -- cgit v1.1 From 630be7ea2f2d0c2ee5662308297b77087da2ace2 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Tue, 19 Mar 2013 12:19:01 +0100 Subject: ARM: sirf: enable sparse IRQ Now that both irqchips for sirf are converted to not rely on legacy domains, let's move all of the platform over to sparse IRQ. Signed-off-by: Arnd Bergmann --- arch/arm/Kconfig | 1 + arch/arm/mach-prima2/common.c | 2 ++ arch/arm/mach-prima2/include/mach/irqs.h | 17 ----------------- 3 files changed, 3 insertions(+), 17 deletions(-) delete mode 100644 arch/arm/mach-prima2/include/mach/irqs.h (limited to 'arch/arm') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 5bfd584..c674b32 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -427,6 +427,7 @@ config ARCH_SIRF select PINCTRL select PINCTRL_SIRF select USE_OF + select SPARSE_IRQ help Support for CSR SiRFprimaII/Marco/Polo platforms diff --git a/arch/arm/mach-prima2/common.c b/arch/arm/mach-prima2/common.c index 15c14df..31f43ea 100644 --- a/arch/arm/mach-prima2/common.c +++ b/arch/arm/mach-prima2/common.c @@ -45,6 +45,7 @@ static const char *atlas6_dt_match[] __initdata = { DT_MACHINE_START(ATLAS6_DT, "Generic ATLAS6 (Flattened Device Tree)") /* Maintainer: Barry Song */ + .nr_irqs = 128, .map_io = sirfsoc_map_io, .init_irq = irqchip_init, .init_time = sirfsoc_prima2_timer_init, @@ -63,6 +64,7 @@ static const char *prima2_dt_match[] __initdata = { DT_MACHINE_START(PRIMA2_DT, "Generic PRIMA2 (Flattened Device Tree)") /* Maintainer: Barry Song */ + .nr_irqs = 128, .map_io = sirfsoc_map_io, .init_irq = irqchip_init, .init_time = sirfsoc_prima2_timer_init, diff --git a/arch/arm/mach-prima2/include/mach/irqs.h b/arch/arm/mach-prima2/include/mach/irqs.h deleted file mode 100644 index b778a0f..0000000 --- a/arch/arm/mach-prima2/include/mach/irqs.h +++ /dev/null @@ -1,17 +0,0 @@ -/* - * arch/arm/mach-prima2/include/mach/irqs.h - * - * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company. - * - * Licensed under GPLv2 or later. - */ - -#ifndef __ASM_ARCH_IRQS_H -#define __ASM_ARCH_IRQS_H - -#define SIRFSOC_INTENAL_IRQ_START 0 -#define SIRFSOC_INTENAL_IRQ_END 127 -#define SIRFSOC_GPIO_IRQ_START (SIRFSOC_INTENAL_IRQ_END + 1) -#define NR_IRQS 288 - -#endif -- cgit v1.1 From 67bdb28718ae6dbdfbfa541161529acfa0f3c137 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Tue, 19 Mar 2013 13:52:14 +0100 Subject: ARM: sirf: move debug-macro.S to include/debug/sirf.S The new style ll_debug implementation for multiplatform requires the platform glue to be in include/debug, so let's move it there to separate the debugging logic from the platform code. Signed-off-by: Arnd Bergmann Tested-by: Barry Song --- arch/arm/Kconfig.debug | 1 + arch/arm/include/debug/sirf.S | 42 +++++++++++++++++++++++++ arch/arm/mach-prima2/include/mach/debug-macro.S | 29 ----------------- arch/arm/mach-prima2/lluart.c | 12 ++++++- 4 files changed, 54 insertions(+), 30 deletions(-) create mode 100644 arch/arm/include/debug/sirf.S delete mode 100644 arch/arm/mach-prima2/include/mach/debug-macro.S (limited to 'arch/arm') diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug index acdddda..a69334d 100644 --- a/arch/arm/Kconfig.debug +++ b/arch/arm/Kconfig.debug @@ -592,6 +592,7 @@ config DEBUG_LL_INCLUDE default "debug/mvebu.S" if DEBUG_MVEBU_UART default "debug/omap2plus.S" if DEBUG_OMAP2PLUS_UART default "debug/picoxcell.S" if DEBUG_PICOXCELL_UART + default "debug/sirf.S" if DEBUG_SIRFPRIMA2_UART1 || DEBUG_SIRFMARCO_UART1 default "debug/socfpga.S" if DEBUG_SOCFPGA_UART default "debug/sunxi.S" if DEBUG_SUNXI_UART0 || DEBUG_SUNXI_UART1 default "debug/vexpress.S" if DEBUG_VEXPRESS_UART0_DETECT || \ diff --git a/arch/arm/include/debug/sirf.S b/arch/arm/include/debug/sirf.S new file mode 100644 index 0000000..dbf250c --- /dev/null +++ b/arch/arm/include/debug/sirf.S @@ -0,0 +1,42 @@ +/* + * arch/arm/mach-prima2/include/mach/debug-macro.S + * + * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company. + * + * Licensed under GPLv2 or later. + */ + +#if defined(CONFIG_DEBUG_SIRFPRIMA2_UART1) +#define SIRFSOC_UART1_PA_BASE 0xb0060000 +#elif defined(CONFIG_DEBUG_SIRFMARCO_UART1) +#define SIRFSOC_UART1_PA_BASE 0xcc060000 +#else +#define SIRFSOC_UART1_PA_BASE 0 +#endif + +#define SIRFSOC_UART1_VA_BASE 0xFEC60000 + +#define SIRFSOC_UART_TXFIFO_STATUS 0x0114 +#define SIRFSOC_UART_TXFIFO_DATA 0x0118 + +#define SIRFSOC_UART1_TXFIFO_FULL (1 << 5) +#define SIRFSOC_UART1_TXFIFO_EMPTY (1 << 6) + + .macro addruart, rp, rv, tmp + ldr \rp, =SIRFSOC_UART1_PA_BASE @ physical + ldr \rv, =SIRFSOC_UART1_VA_BASE @ virtual + .endm + + .macro senduart,rd,rx + str \rd, [\rx, #SIRFSOC_UART_TXFIFO_DATA] + .endm + + .macro busyuart,rd,rx + .endm + + .macro waituart,rd,rx +1001: ldr \rd, [\rx, #SIRFSOC_UART_TXFIFO_STATUS] + tst \rd, #SIRFSOC_UART1_TXFIFO_EMPTY + beq 1001b + .endm + diff --git a/arch/arm/mach-prima2/include/mach/debug-macro.S b/arch/arm/mach-prima2/include/mach/debug-macro.S deleted file mode 100644 index cd97492..0000000 --- a/arch/arm/mach-prima2/include/mach/debug-macro.S +++ /dev/null @@ -1,29 +0,0 @@ -/* - * arch/arm/mach-prima2/include/mach/debug-macro.S - * - * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company. - * - * Licensed under GPLv2 or later. - */ - -#include -#include - - .macro addruart, rp, rv, tmp - ldr \rp, =SIRFSOC_UART1_PA_BASE @ physical - ldr \rv, =SIRFSOC_UART1_VA_BASE @ virtual - .endm - - .macro senduart,rd,rx - str \rd, [\rx, #SIRFSOC_UART_TXFIFO_DATA] - .endm - - .macro busyuart,rd,rx - .endm - - .macro waituart,rd,rx -1001: ldr \rd, [\rx, #SIRFSOC_UART_TXFIFO_STATUS] - tst \rd, #SIRFSOC_UART1_TXFIFO_EMPTY - beq 1001b - .endm - diff --git a/arch/arm/mach-prima2/lluart.c b/arch/arm/mach-prima2/lluart.c index a89f9b3..7222481 100644 --- a/arch/arm/mach-prima2/lluart.c +++ b/arch/arm/mach-prima2/lluart.c @@ -10,7 +10,17 @@ #include #include #include -#include + +#if defined(CONFIG_DEBUG_SIRFPRIMA2_UART1) +#define SIRFSOC_UART1_PA_BASE 0xb0060000 +#elif defined(CONFIG_DEBUG_SIRFMARCO_UART1) +#define SIRFSOC_UART1_PA_BASE 0xcc060000 +#else +#define SIRFSOC_UART1_PA_BASE 0 +#endif + +#define SIRFSOC_UART1_VA_BASE SIRFSOC_VA(0x060000) +#define SIRFSOC_UART1_SIZE SZ_4K void __init sirfsoc_map_lluart(void) { -- cgit v1.1 From 275786b71d42bb54c03c15197128d7cb05d4dd8b Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Tue, 19 Mar 2013 15:27:22 +0100 Subject: ARM: sirf: use clocksource_of infrastructure This moves the two sirf clocksource drivers to drivers/clocksource and integrates them into the framework for locating the clock sources automatically. Signed-off-by: Arnd Bergmann Tested-by: Barry Song Cc: John Stultz Cc: Thomas Gleixner --- arch/arm/mach-prima2/Makefile | 2 - arch/arm/mach-prima2/common.c | 14 +- arch/arm/mach-prima2/common.h | 3 - arch/arm/mach-prima2/timer-marco.c | 316 ------------------------------------ arch/arm/mach-prima2/timer-prima2.c | 239 --------------------------- 5 files changed, 11 insertions(+), 563 deletions(-) delete mode 100644 arch/arm/mach-prima2/timer-marco.c delete mode 100644 arch/arm/mach-prima2/timer-prima2.c (limited to 'arch/arm') diff --git a/arch/arm/mach-prima2/Makefile b/arch/arm/mach-prima2/Makefile index 5fdff7e..52ac738 100644 --- a/arch/arm/mach-prima2/Makefile +++ b/arch/arm/mach-prima2/Makefile @@ -6,5 +6,3 @@ obj-$(CONFIG_CACHE_L2X0) += l2x0.o obj-$(CONFIG_SUSPEND) += pm.o sleep.o obj-$(CONFIG_SMP) += platsmp.o headsmp.o obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o -obj-$(CONFIG_ARCH_PRIMA2) += timer-prima2.o -obj-$(CONFIG_ARCH_MARCO) += timer-marco.o diff --git a/arch/arm/mach-prima2/common.c b/arch/arm/mach-prima2/common.c index 31f43ea..4f94cd8 100644 --- a/arch/arm/mach-prima2/common.c +++ b/arch/arm/mach-prima2/common.c @@ -6,6 +6,7 @@ * Licensed under GPLv2 or later. */ +#include #include #include #include @@ -31,6 +32,13 @@ void __init sirfsoc_init_late(void) sirfsoc_pm_init(); } +static __init void sirfsoc_init_time(void) +{ + /* initialize clocking early, we want to set the OS timer */ + sirfsoc_of_clk_init(); + clocksource_of_init(); +} + static __init void sirfsoc_map_io(void) { sirfsoc_map_lluart(); @@ -48,7 +56,7 @@ DT_MACHINE_START(ATLAS6_DT, "Generic ATLAS6 (Flattened Device Tree)") .nr_irqs = 128, .map_io = sirfsoc_map_io, .init_irq = irqchip_init, - .init_time = sirfsoc_prima2_timer_init, + .init_time = sirfsoc_init_time, .init_machine = sirfsoc_mach_init, .init_late = sirfsoc_init_late, .dt_compat = atlas6_dt_match, @@ -67,7 +75,7 @@ DT_MACHINE_START(PRIMA2_DT, "Generic PRIMA2 (Flattened Device Tree)") .nr_irqs = 128, .map_io = sirfsoc_map_io, .init_irq = irqchip_init, - .init_time = sirfsoc_prima2_timer_init, + .init_time = sirfsoc_init_time, .dma_zone_size = SZ_256M, .init_machine = sirfsoc_mach_init, .init_late = sirfsoc_init_late, @@ -87,7 +95,7 @@ DT_MACHINE_START(MARCO_DT, "Generic MARCO (Flattened Device Tree)") .smp = smp_ops(sirfsoc_smp_ops), .map_io = sirfsoc_map_io, .init_irq = irqchip_init, - .init_time = sirfsoc_marco_timer_init, + .init_time = sirfsoc_init_time, .init_machine = sirfsoc_mach_init, .init_late = sirfsoc_init_late, .dt_compat = marco_dt_match, diff --git a/arch/arm/mach-prima2/common.h b/arch/arm/mach-prima2/common.h index b7c26b6..54262cf 100644 --- a/arch/arm/mach-prima2/common.h +++ b/arch/arm/mach-prima2/common.h @@ -13,9 +13,6 @@ #include #include -extern void sirfsoc_prima2_timer_init(void); -extern void sirfsoc_marco_timer_init(void); - extern struct smp_operations sirfsoc_smp_ops; extern void sirfsoc_secondary_startup(void); extern void sirfsoc_cpu_die(unsigned int cpu); diff --git a/arch/arm/mach-prima2/timer-marco.c b/arch/arm/mach-prima2/timer-marco.c deleted file mode 100644 index f4eea2e..0000000 --- a/arch/arm/mach-prima2/timer-marco.c +++ /dev/null @@ -1,316 +0,0 @@ -/* - * System timer for CSR SiRFprimaII - * - * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company. - * - * Licensed under GPLv2 or later. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "common.h" - -#define SIRFSOC_TIMER_32COUNTER_0_CTRL 0x0000 -#define SIRFSOC_TIMER_32COUNTER_1_CTRL 0x0004 -#define SIRFSOC_TIMER_MATCH_0 0x0018 -#define SIRFSOC_TIMER_MATCH_1 0x001c -#define SIRFSOC_TIMER_COUNTER_0 0x0048 -#define SIRFSOC_TIMER_COUNTER_1 0x004c -#define SIRFSOC_TIMER_INTR_STATUS 0x0060 -#define SIRFSOC_TIMER_WATCHDOG_EN 0x0064 -#define SIRFSOC_TIMER_64COUNTER_CTRL 0x0068 -#define SIRFSOC_TIMER_64COUNTER_LO 0x006c -#define SIRFSOC_TIMER_64COUNTER_HI 0x0070 -#define SIRFSOC_TIMER_64COUNTER_LOAD_LO 0x0074 -#define SIRFSOC_TIMER_64COUNTER_LOAD_HI 0x0078 -#define SIRFSOC_TIMER_64COUNTER_RLATCHED_LO 0x007c -#define SIRFSOC_TIMER_64COUNTER_RLATCHED_HI 0x0080 - -#define SIRFSOC_TIMER_REG_CNT 6 - -static const u32 sirfsoc_timer_reg_list[SIRFSOC_TIMER_REG_CNT] = { - SIRFSOC_TIMER_WATCHDOG_EN, - SIRFSOC_TIMER_32COUNTER_0_CTRL, - SIRFSOC_TIMER_32COUNTER_1_CTRL, - SIRFSOC_TIMER_64COUNTER_CTRL, - SIRFSOC_TIMER_64COUNTER_RLATCHED_LO, - SIRFSOC_TIMER_64COUNTER_RLATCHED_HI, -}; - -static u32 sirfsoc_timer_reg_val[SIRFSOC_TIMER_REG_CNT]; - -static void __iomem *sirfsoc_timer_base; -static void __init sirfsoc_of_timer_map(void); - -/* disable count and interrupt */ -static inline void sirfsoc_timer_count_disable(int idx) -{ - writel_relaxed(readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL + 4 * idx) & ~0x7, - sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL + 4 * idx); -} - -/* enable count and interrupt */ -static inline void sirfsoc_timer_count_enable(int idx) -{ - writel_relaxed(readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL + 4 * idx) | 0x7, - sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL + 4 * idx); -} - -/* timer interrupt handler */ -static irqreturn_t sirfsoc_timer_interrupt(int irq, void *dev_id) -{ - struct clock_event_device *ce = dev_id; - int cpu = smp_processor_id(); - - /* clear timer interrupt */ - writel_relaxed(BIT(cpu), sirfsoc_timer_base + SIRFSOC_TIMER_INTR_STATUS); - - if (ce->mode == CLOCK_EVT_MODE_ONESHOT) - sirfsoc_timer_count_disable(cpu); - - ce->event_handler(ce); - - return IRQ_HANDLED; -} - -/* read 64-bit timer counter */ -static cycle_t sirfsoc_timer_read(struct clocksource *cs) -{ - u64 cycles; - - writel_relaxed((readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL) | - BIT(0)) & ~BIT(1), sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL); - - cycles = readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_RLATCHED_HI); - cycles = (cycles << 32) | readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_RLATCHED_LO); - - return cycles; -} - -static int sirfsoc_timer_set_next_event(unsigned long delta, - struct clock_event_device *ce) -{ - int cpu = smp_processor_id(); - - writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_0 + - 4 * cpu); - writel_relaxed(delta, sirfsoc_timer_base + SIRFSOC_TIMER_MATCH_0 + - 4 * cpu); - - /* enable the tick */ - sirfsoc_timer_count_enable(cpu); - - return 0; -} - -static void sirfsoc_timer_set_mode(enum clock_event_mode mode, - struct clock_event_device *ce) -{ - switch (mode) { - case CLOCK_EVT_MODE_ONESHOT: - /* enable in set_next_event */ - break; - default: - break; - } - - sirfsoc_timer_count_disable(smp_processor_id()); -} - -static void sirfsoc_clocksource_suspend(struct clocksource *cs) -{ - int i; - - for (i = 0; i < SIRFSOC_TIMER_REG_CNT; i++) - sirfsoc_timer_reg_val[i] = readl_relaxed(sirfsoc_timer_base + sirfsoc_timer_reg_list[i]); -} - -static void sirfsoc_clocksource_resume(struct clocksource *cs) -{ - int i; - - for (i = 0; i < SIRFSOC_TIMER_REG_CNT - 2; i++) - writel_relaxed(sirfsoc_timer_reg_val[i], sirfsoc_timer_base + sirfsoc_timer_reg_list[i]); - - writel_relaxed(sirfsoc_timer_reg_val[SIRFSOC_TIMER_REG_CNT - 2], - sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_LOAD_LO); - writel_relaxed(sirfsoc_timer_reg_val[SIRFSOC_TIMER_REG_CNT - 1], - sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_LOAD_HI); - - writel_relaxed(readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL) | - BIT(1) | BIT(0), sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL); -} - -static struct clock_event_device sirfsoc_clockevent = { - .name = "sirfsoc_clockevent", - .rating = 200, - .features = CLOCK_EVT_FEAT_ONESHOT, - .set_mode = sirfsoc_timer_set_mode, - .set_next_event = sirfsoc_timer_set_next_event, -}; - -static struct clocksource sirfsoc_clocksource = { - .name = "sirfsoc_clocksource", - .rating = 200, - .mask = CLOCKSOURCE_MASK(64), - .flags = CLOCK_SOURCE_IS_CONTINUOUS, - .read = sirfsoc_timer_read, - .suspend = sirfsoc_clocksource_suspend, - .resume = sirfsoc_clocksource_resume, -}; - -static struct irqaction sirfsoc_timer_irq = { - .name = "sirfsoc_timer0", - .flags = IRQF_TIMER | IRQF_NOBALANCING, - .handler = sirfsoc_timer_interrupt, - .dev_id = &sirfsoc_clockevent, -}; - -#ifdef CONFIG_LOCAL_TIMERS - -static struct irqaction sirfsoc_timer1_irq = { - .name = "sirfsoc_timer1", - .flags = IRQF_TIMER | IRQF_NOBALANCING, - .handler = sirfsoc_timer_interrupt, -}; - -static int __cpuinit sirfsoc_local_timer_setup(struct clock_event_device *ce) -{ - /* Use existing clock_event for cpu 0 */ - if (!smp_processor_id()) - return 0; - - ce->irq = sirfsoc_timer1_irq.irq; - ce->name = "local_timer"; - ce->features = sirfsoc_clockevent.features; - ce->rating = sirfsoc_clockevent.rating; - ce->set_mode = sirfsoc_timer_set_mode; - ce->set_next_event = sirfsoc_timer_set_next_event; - ce->shift = sirfsoc_clockevent.shift; - ce->mult = sirfsoc_clockevent.mult; - ce->max_delta_ns = sirfsoc_clockevent.max_delta_ns; - ce->min_delta_ns = sirfsoc_clockevent.min_delta_ns; - - sirfsoc_timer1_irq.dev_id = ce; - BUG_ON(setup_irq(ce->irq, &sirfsoc_timer1_irq)); - irq_set_affinity(sirfsoc_timer1_irq.irq, cpumask_of(1)); - - clockevents_register_device(ce); - return 0; -} - -static void sirfsoc_local_timer_stop(struct clock_event_device *ce) -{ - sirfsoc_timer_count_disable(1); - - remove_irq(sirfsoc_timer1_irq.irq, &sirfsoc_timer1_irq); -} - -static struct local_timer_ops sirfsoc_local_timer_ops __cpuinitdata = { - .setup = sirfsoc_local_timer_setup, - .stop = sirfsoc_local_timer_stop, -}; -#endif /* CONFIG_LOCAL_TIMERS */ - -static void __init sirfsoc_clockevent_init(void) -{ - clockevents_calc_mult_shift(&sirfsoc_clockevent, CLOCK_TICK_RATE, 60); - - sirfsoc_clockevent.max_delta_ns = - clockevent_delta2ns(-2, &sirfsoc_clockevent); - sirfsoc_clockevent.min_delta_ns = - clockevent_delta2ns(2, &sirfsoc_clockevent); - - sirfsoc_clockevent.cpumask = cpumask_of(0); - clockevents_register_device(&sirfsoc_clockevent); -#ifdef CONFIG_LOCAL_TIMERS - local_timer_register(&sirfsoc_local_timer_ops); -#endif -} - -/* initialize the kernel jiffy timer source */ -void __init sirfsoc_marco_timer_init(void) -{ - unsigned long rate; - u32 timer_div; - struct clk *clk; - - /* initialize clocking early, we want to set the OS timer */ - sirfsoc_of_clk_init(); - - /* timer's input clock is io clock */ - clk = clk_get_sys("io", NULL); - - BUG_ON(IS_ERR(clk)); - rate = clk_get_rate(clk); - - BUG_ON(rate < CLOCK_TICK_RATE); - BUG_ON(rate % CLOCK_TICK_RATE); - - sirfsoc_of_timer_map(); - - /* Initialize the timer dividers */ - timer_div = rate / CLOCK_TICK_RATE - 1; - writel_relaxed(timer_div << 16, sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL); - writel_relaxed(timer_div << 16, sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL); - writel_relaxed(timer_div << 16, sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_1_CTRL); - - /* Initialize timer counters to 0 */ - writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_LOAD_LO); - writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_LOAD_HI); - writel_relaxed(readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL) | - BIT(1) | BIT(0), sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL); - writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_0); - writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_1); - - /* Clear all interrupts */ - writel_relaxed(0xFFFF, sirfsoc_timer_base + SIRFSOC_TIMER_INTR_STATUS); - - BUG_ON(clocksource_register_hz(&sirfsoc_clocksource, CLOCK_TICK_RATE)); - - BUG_ON(setup_irq(sirfsoc_timer_irq.irq, &sirfsoc_timer_irq)); - - sirfsoc_clockevent_init(); -} - -static struct of_device_id timer_ids[] = { - { .compatible = "sirf,marco-tick" }, - {}, -}; - -static void __init sirfsoc_of_timer_map(void) -{ - struct device_node *np; - - np = of_find_matching_node(NULL, timer_ids); - if (!np) - return; - sirfsoc_timer_base = of_iomap(np, 0); - if (!sirfsoc_timer_base) - panic("unable to map timer cpu registers\n"); - - sirfsoc_timer_irq.irq = irq_of_parse_and_map(np, 0); - if (!sirfsoc_timer_irq.irq) - panic("No irq passed for timer0 via DT\n"); - -#ifdef CONFIG_LOCAL_TIMERS - sirfsoc_timer1_irq.irq = irq_of_parse_and_map(np, 1); - if (!sirfsoc_timer1_irq.irq) - panic("No irq passed for timer1 via DT\n"); -#endif - - of_node_put(np); -} diff --git a/arch/arm/mach-prima2/timer-prima2.c b/arch/arm/mach-prima2/timer-prima2.c deleted file mode 100644 index 9829083..0000000 --- a/arch/arm/mach-prima2/timer-prima2.c +++ /dev/null @@ -1,239 +0,0 @@ -/* - * System timer for CSR SiRFprimaII - * - * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company. - * - * Licensed under GPLv2 or later. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "common.h" - -#define SIRFSOC_TIMER_COUNTER_LO 0x0000 -#define SIRFSOC_TIMER_COUNTER_HI 0x0004 -#define SIRFSOC_TIMER_MATCH_0 0x0008 -#define SIRFSOC_TIMER_MATCH_1 0x000C -#define SIRFSOC_TIMER_MATCH_2 0x0010 -#define SIRFSOC_TIMER_MATCH_3 0x0014 -#define SIRFSOC_TIMER_MATCH_4 0x0018 -#define SIRFSOC_TIMER_MATCH_5 0x001C -#define SIRFSOC_TIMER_STATUS 0x0020 -#define SIRFSOC_TIMER_INT_EN 0x0024 -#define SIRFSOC_TIMER_WATCHDOG_EN 0x0028 -#define SIRFSOC_TIMER_DIV 0x002C -#define SIRFSOC_TIMER_LATCH 0x0030 -#define SIRFSOC_TIMER_LATCHED_LO 0x0034 -#define SIRFSOC_TIMER_LATCHED_HI 0x0038 - -#define SIRFSOC_TIMER_WDT_INDEX 5 - -#define SIRFSOC_TIMER_LATCH_BIT BIT(0) - -#define SIRFSOC_TIMER_REG_CNT 11 - -static const u32 sirfsoc_timer_reg_list[SIRFSOC_TIMER_REG_CNT] = { - SIRFSOC_TIMER_MATCH_0, SIRFSOC_TIMER_MATCH_1, SIRFSOC_TIMER_MATCH_2, - SIRFSOC_TIMER_MATCH_3, SIRFSOC_TIMER_MATCH_4, SIRFSOC_TIMER_MATCH_5, - SIRFSOC_TIMER_INT_EN, SIRFSOC_TIMER_WATCHDOG_EN, SIRFSOC_TIMER_DIV, - SIRFSOC_TIMER_LATCHED_LO, SIRFSOC_TIMER_LATCHED_HI, -}; - -static u32 sirfsoc_timer_reg_val[SIRFSOC_TIMER_REG_CNT]; - -static void __iomem *sirfsoc_timer_base; -static void __init sirfsoc_of_timer_map(void); - -/* timer0 interrupt handler */ -static irqreturn_t sirfsoc_timer_interrupt(int irq, void *dev_id) -{ - struct clock_event_device *ce = dev_id; - - WARN_ON(!(readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_STATUS) & BIT(0))); - - /* clear timer0 interrupt */ - writel_relaxed(BIT(0), sirfsoc_timer_base + SIRFSOC_TIMER_STATUS); - - ce->event_handler(ce); - - return IRQ_HANDLED; -} - -/* read 64-bit timer counter */ -static cycle_t sirfsoc_timer_read(struct clocksource *cs) -{ - u64 cycles; - - /* latch the 64-bit timer counter */ - writel_relaxed(SIRFSOC_TIMER_LATCH_BIT, sirfsoc_timer_base + SIRFSOC_TIMER_LATCH); - cycles = readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_LATCHED_HI); - cycles = (cycles << 32) | readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_LATCHED_LO); - - return cycles; -} - -static int sirfsoc_timer_set_next_event(unsigned long delta, - struct clock_event_device *ce) -{ - unsigned long now, next; - - writel_relaxed(SIRFSOC_TIMER_LATCH_BIT, sirfsoc_timer_base + SIRFSOC_TIMER_LATCH); - now = readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_LATCHED_LO); - next = now + delta; - writel_relaxed(next, sirfsoc_timer_base + SIRFSOC_TIMER_MATCH_0); - writel_relaxed(SIRFSOC_TIMER_LATCH_BIT, sirfsoc_timer_base + SIRFSOC_TIMER_LATCH); - now = readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_LATCHED_LO); - - return next - now > delta ? -ETIME : 0; -} - -static void sirfsoc_timer_set_mode(enum clock_event_mode mode, - struct clock_event_device *ce) -{ - u32 val = readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_INT_EN); - switch (mode) { - case CLOCK_EVT_MODE_PERIODIC: - WARN_ON(1); - break; - case CLOCK_EVT_MODE_ONESHOT: - writel_relaxed(val | BIT(0), sirfsoc_timer_base + SIRFSOC_TIMER_INT_EN); - break; - case CLOCK_EVT_MODE_SHUTDOWN: - writel_relaxed(val & ~BIT(0), sirfsoc_timer_base + SIRFSOC_TIMER_INT_EN); - break; - case CLOCK_EVT_MODE_UNUSED: - case CLOCK_EVT_MODE_RESUME: - break; - } -} - -static void sirfsoc_clocksource_suspend(struct clocksource *cs) -{ - int i; - - writel_relaxed(SIRFSOC_TIMER_LATCH_BIT, sirfsoc_timer_base + SIRFSOC_TIMER_LATCH); - - for (i = 0; i < SIRFSOC_TIMER_REG_CNT; i++) - sirfsoc_timer_reg_val[i] = readl_relaxed(sirfsoc_timer_base + sirfsoc_timer_reg_list[i]); -} - -static void sirfsoc_clocksource_resume(struct clocksource *cs) -{ - int i; - - for (i = 0; i < SIRFSOC_TIMER_REG_CNT - 2; i++) - writel_relaxed(sirfsoc_timer_reg_val[i], sirfsoc_timer_base + sirfsoc_timer_reg_list[i]); - - writel_relaxed(sirfsoc_timer_reg_val[SIRFSOC_TIMER_REG_CNT - 2], sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_LO); - writel_relaxed(sirfsoc_timer_reg_val[SIRFSOC_TIMER_REG_CNT - 1], sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_HI); -} - -static struct clock_event_device sirfsoc_clockevent = { - .name = "sirfsoc_clockevent", - .rating = 200, - .features = CLOCK_EVT_FEAT_ONESHOT, - .set_mode = sirfsoc_timer_set_mode, - .set_next_event = sirfsoc_timer_set_next_event, -}; - -static struct clocksource sirfsoc_clocksource = { - .name = "sirfsoc_clocksource", - .rating = 200, - .mask = CLOCKSOURCE_MASK(64), - .flags = CLOCK_SOURCE_IS_CONTINUOUS, - .read = sirfsoc_timer_read, - .suspend = sirfsoc_clocksource_suspend, - .resume = sirfsoc_clocksource_resume, -}; - -static struct irqaction sirfsoc_timer_irq = { - .name = "sirfsoc_timer0", - .flags = IRQF_TIMER, - .irq = 0, - .handler = sirfsoc_timer_interrupt, - .dev_id = &sirfsoc_clockevent, -}; - -/* Overwrite weak default sched_clock with more precise one */ -static u32 notrace sirfsoc_read_sched_clock(void) -{ - return (u32)(sirfsoc_timer_read(NULL) & 0xffffffff); -} - -static void __init sirfsoc_clockevent_init(void) -{ - sirfsoc_clockevent.cpumask = cpumask_of(0); - clockevents_config_and_register(&sirfsoc_clockevent, CLOCK_TICK_RATE, - 2, -2); -} - -/* initialize the kernel jiffy timer source */ -void __init sirfsoc_prima2_timer_init(void) -{ - unsigned long rate; - struct clk *clk; - - /* initialize clocking early, we want to set the OS timer */ - sirfsoc_of_clk_init(); - - /* timer's input clock is io clock */ - clk = clk_get_sys("io", NULL); - - BUG_ON(IS_ERR(clk)); - - rate = clk_get_rate(clk); - - BUG_ON(rate < CLOCK_TICK_RATE); - BUG_ON(rate % CLOCK_TICK_RATE); - - sirfsoc_of_timer_map(); - - writel_relaxed(rate / CLOCK_TICK_RATE / 2 - 1, sirfsoc_timer_base + SIRFSOC_TIMER_DIV); - writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_LO); - writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_HI); - writel_relaxed(BIT(0), sirfsoc_timer_base + SIRFSOC_TIMER_STATUS); - - BUG_ON(clocksource_register_hz(&sirfsoc_clocksource, CLOCK_TICK_RATE)); - - setup_sched_clock(sirfsoc_read_sched_clock, 32, CLOCK_TICK_RATE); - - BUG_ON(setup_irq(sirfsoc_timer_irq.irq, &sirfsoc_timer_irq)); - - sirfsoc_clockevent_init(); -} - -static struct of_device_id timer_ids[] = { - { .compatible = "sirf,prima2-tick" }, - {}, -}; - -static void __init sirfsoc_of_timer_map(void) -{ - struct device_node *np; - - np = of_find_matching_node(NULL, timer_ids); - if (!np) - return; - sirfsoc_timer_base = of_iomap(np, 0); - if (!sirfsoc_timer_base) - panic("unable to map timer cpu registers\n"); - - /* Get the interrupts property */ - sirfsoc_timer_irq.irq = irq_of_parse_and_map(np, 0); - - of_node_put(np); -} -- cgit v1.1 From cf82e0e40525d3525445ada6569525cc44aad46f Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Tue, 19 Mar 2013 17:45:37 +0100 Subject: ARM: sirf: enable multiplatform support All the prerequisites are there now, so we can move sirf into multiplatform. Signed-off-by: Arnd Bergmann --- arch/arm/Kconfig | 17 ---------- arch/arm/mach-prima2/Kconfig | 12 ++++++++ arch/arm/mach-prima2/Makefile | 2 ++ arch/arm/mach-prima2/common.h | 3 ++ arch/arm/mach-prima2/include/mach/clkdev.h | 15 --------- arch/arm/mach-prima2/include/mach/entry-macro.S | 22 ------------- arch/arm/mach-prima2/include/mach/hardware.h | 15 --------- arch/arm/mach-prima2/include/mach/map.h | 18 ----------- arch/arm/mach-prima2/include/mach/timex.h | 14 --------- arch/arm/mach-prima2/include/mach/uart.h | 29 ----------------- arch/arm/mach-prima2/include/mach/uncompress.h | 41 ------------------------- arch/arm/mach-prima2/lluart.c | 2 +- arch/arm/mach-prima2/platsmp.c | 1 - 13 files changed, 18 insertions(+), 173 deletions(-) delete mode 100644 arch/arm/mach-prima2/include/mach/clkdev.h delete mode 100644 arch/arm/mach-prima2/include/mach/entry-macro.S delete mode 100644 arch/arm/mach-prima2/include/mach/hardware.h delete mode 100644 arch/arm/mach-prima2/include/mach/map.h delete mode 100644 arch/arm/mach-prima2/include/mach/timex.h delete mode 100644 arch/arm/mach-prima2/include/mach/uart.h delete mode 100644 arch/arm/mach-prima2/include/mach/uncompress.h (limited to 'arch/arm') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index c674b32..1bcec63 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -49,7 +49,6 @@ config ARM select HAVE_REGS_AND_STACK_ACCESS_API select HAVE_SYSCALL_TRACEPOINTS select HAVE_UID16 - select HAVE_VIRT_TO_BUS select KTIME_SCALAR select PERF_USE_VMALLOC select RTC_LIB @@ -415,22 +414,6 @@ config ARCH_GEMINI help Support for the Cortina Systems Gemini family SoCs -config ARCH_SIRF - bool "CSR SiRF" - select ARCH_REQUIRE_GPIOLIB - select AUTO_ZRELADDR - select COMMON_CLK - select GENERIC_CLOCKEVENTS - select GENERIC_IRQ_CHIP - select MIGHT_HAVE_CACHE_L2X0 - select NO_IOPORT - select PINCTRL - select PINCTRL_SIRF - select USE_OF - select SPARSE_IRQ - help - Support for CSR SiRFprimaII/Marco/Polo platforms - config ARCH_EBSA110 bool "EBSA-110" select ARCH_USES_GETTIMEOFFSET diff --git a/arch/arm/mach-prima2/Kconfig b/arch/arm/mach-prima2/Kconfig index b3be799..587c0bd 100644 --- a/arch/arm/mach-prima2/Kconfig +++ b/arch/arm/mach-prima2/Kconfig @@ -1,3 +1,15 @@ +config ARCH_SIRF + bool "CSR SiRF" if ARCH_MULTI_V7 + select ARCH_REQUIRE_GPIOLIB + select GENERIC_CLOCKEVENTS + select GENERIC_IRQ_CHIP + select MIGHT_HAVE_CACHE_L2X0 + select NO_IOPORT + select PINCTRL + select PINCTRL_SIRF + help + Support for CSR SiRFprimaII/Marco/Polo platforms + if ARCH_SIRF menu "CSR SiRF atlas6/primaII/Marco/Polo Specific Features" diff --git a/arch/arm/mach-prima2/Makefile b/arch/arm/mach-prima2/Makefile index 52ac738..7a6b4a3 100644 --- a/arch/arm/mach-prima2/Makefile +++ b/arch/arm/mach-prima2/Makefile @@ -6,3 +6,5 @@ obj-$(CONFIG_CACHE_L2X0) += l2x0.o obj-$(CONFIG_SUSPEND) += pm.o sleep.o obj-$(CONFIG_SMP) += platsmp.o headsmp.o obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o + +CFLAGS_hotplug.o += -march=armv7-a diff --git a/arch/arm/mach-prima2/common.h b/arch/arm/mach-prima2/common.h index 54262cf..81135cd 100644 --- a/arch/arm/mach-prima2/common.h +++ b/arch/arm/mach-prima2/common.h @@ -13,6 +13,9 @@ #include #include +#define SIRFSOC_VA_BASE _AC(0xFEC00000, UL) +#define SIRFSOC_VA(x) (SIRFSOC_VA_BASE + ((x) & 0x00FFF000)) + extern struct smp_operations sirfsoc_smp_ops; extern void sirfsoc_secondary_startup(void); extern void sirfsoc_cpu_die(unsigned int cpu); diff --git a/arch/arm/mach-prima2/include/mach/clkdev.h b/arch/arm/mach-prima2/include/mach/clkdev.h deleted file mode 100644 index 6693251..0000000 --- a/arch/arm/mach-prima2/include/mach/clkdev.h +++ /dev/null @@ -1,15 +0,0 @@ -/* - * arch/arm/mach-prima2/include/mach/clkdev.h - * - * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company. - * - * Licensed under GPLv2 or later. - */ - -#ifndef __MACH_CLKDEV_H -#define __MACH_CLKDEV_H - -#define __clk_get(clk) ({ 1; }) -#define __clk_put(clk) do { } while (0) - -#endif diff --git a/arch/arm/mach-prima2/include/mach/entry-macro.S b/arch/arm/mach-prima2/include/mach/entry-macro.S deleted file mode 100644 index 86434e7..0000000 --- a/arch/arm/mach-prima2/include/mach/entry-macro.S +++ /dev/null @@ -1,22 +0,0 @@ -/* - * arch/arm/mach-prima2/include/mach/entry-macro.S - * - * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company. - * - * Licensed under GPLv2 or later. - */ - -#include - -#define SIRFSOC_INT_ID 0x38 - - .macro get_irqnr_preamble, base, tmp - ldr \base, =sirfsoc_intc_base - ldr \base, [\base] - .endm - - .macro get_irqnr_and_base, irqnr, irqstat, base, tmp - ldr \irqnr, [\base, #SIRFSOC_INT_ID] @ Get the highest priority irq - cmp \irqnr, #0x40 @ the irq num can't be larger than 0x3f - movges \irqnr, #0 - .endm diff --git a/arch/arm/mach-prima2/include/mach/hardware.h b/arch/arm/mach-prima2/include/mach/hardware.h deleted file mode 100644 index 105b969..0000000 --- a/arch/arm/mach-prima2/include/mach/hardware.h +++ /dev/null @@ -1,15 +0,0 @@ -/* - * arch/arm/mach-prima2/include/mach/hardware.h - * - * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company. - * - * Licensed under GPLv2 or later. - */ - -#ifndef __MACH_HARDWARE_H__ -#define __MACH_HARDWARE_H__ - -#include -#include - -#endif diff --git a/arch/arm/mach-prima2/include/mach/map.h b/arch/arm/mach-prima2/include/mach/map.h deleted file mode 100644 index 6f24353..0000000 --- a/arch/arm/mach-prima2/include/mach/map.h +++ /dev/null @@ -1,18 +0,0 @@ -/* - * memory & I/O static mapping definitions for CSR SiRFprimaII - * - * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company. - * - * Licensed under GPLv2 or later. - */ - -#ifndef __MACH_PRIMA2_MAP_H__ -#define __MACH_PRIMA2_MAP_H__ - -#include - -#define SIRFSOC_VA_BASE _AC(0xFEC00000, UL) - -#define SIRFSOC_VA(x) (SIRFSOC_VA_BASE + ((x) & 0x00FFF000)) - -#endif diff --git a/arch/arm/mach-prima2/include/mach/timex.h b/arch/arm/mach-prima2/include/mach/timex.h deleted file mode 100644 index d6f98a7..0000000 --- a/arch/arm/mach-prima2/include/mach/timex.h +++ /dev/null @@ -1,14 +0,0 @@ -/* - * arch/arm/mach-prima2/include/mach/timex.h - * - * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company. - * - * Licensed under GPLv2 or later. - */ - -#ifndef __MACH_TIMEX_H__ -#define __MACH_TIMEX_H__ - -#define CLOCK_TICK_RATE 1000000 - -#endif diff --git a/arch/arm/mach-prima2/include/mach/uart.h b/arch/arm/mach-prima2/include/mach/uart.h deleted file mode 100644 index c10510d..0000000 --- a/arch/arm/mach-prima2/include/mach/uart.h +++ /dev/null @@ -1,29 +0,0 @@ -/* - * arch/arm/mach-prima2/include/mach/uart.h - * - * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company. - * - * Licensed under GPLv2 or later. - */ - -#ifndef __MACH_PRIMA2_SIRFSOC_UART_H -#define __MACH_PRIMA2_SIRFSOC_UART_H - -/* UART-1: used as serial debug port */ -#if defined(CONFIG_DEBUG_SIRFPRIMA2_UART1) -#define SIRFSOC_UART1_PA_BASE 0xb0060000 -#elif defined(CONFIG_DEBUG_SIRFMARCO_UART1) -#define SIRFSOC_UART1_PA_BASE 0xcc060000 -#else -#define SIRFSOC_UART1_PA_BASE 0 -#endif -#define SIRFSOC_UART1_VA_BASE SIRFSOC_VA(0x060000) -#define SIRFSOC_UART1_SIZE SZ_4K - -#define SIRFSOC_UART_TXFIFO_STATUS 0x0114 -#define SIRFSOC_UART_TXFIFO_DATA 0x0118 - -#define SIRFSOC_UART1_TXFIFO_FULL (1 << 5) -#define SIRFSOC_UART1_TXFIFO_EMPTY (1 << 6) - -#endif diff --git a/arch/arm/mach-prima2/include/mach/uncompress.h b/arch/arm/mach-prima2/include/mach/uncompress.h deleted file mode 100644 index d1513a3..0000000 --- a/arch/arm/mach-prima2/include/mach/uncompress.h +++ /dev/null @@ -1,41 +0,0 @@ -/* - * arch/arm/mach-prima2/include/mach/uncompress.h - * - * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company. - * - * Licensed under GPLv2 or later. - */ - -#ifndef __ASM_ARCH_UNCOMPRESS_H -#define __ASM_ARCH_UNCOMPRESS_H - -#include -#include -#include - -void arch_decomp_setup(void) -{ -} - -static __inline__ void putc(char c) -{ - /* - * during kernel decompression, all mappings are flat: - * virt_addr == phys_addr - */ - if (!SIRFSOC_UART1_PA_BASE) - return; - - while (__raw_readl((void __iomem *)SIRFSOC_UART1_PA_BASE + SIRFSOC_UART_TXFIFO_STATUS) - & SIRFSOC_UART1_TXFIFO_FULL) - barrier(); - - __raw_writel(c, (void __iomem *)SIRFSOC_UART1_PA_BASE + SIRFSOC_UART_TXFIFO_DATA); -} - -static inline void flush(void) -{ -} - -#endif - diff --git a/arch/arm/mach-prima2/lluart.c b/arch/arm/mach-prima2/lluart.c index 7222481..99c0c92 100644 --- a/arch/arm/mach-prima2/lluart.c +++ b/arch/arm/mach-prima2/lluart.c @@ -9,7 +9,7 @@ #include #include #include -#include +#include "common.h" #if defined(CONFIG_DEBUG_SIRFPRIMA2_UART1) #define SIRFSOC_UART1_PA_BASE 0xb0060000 diff --git a/arch/arm/mach-prima2/platsmp.c b/arch/arm/mach-prima2/platsmp.c index 4b78831..d52e322 100644 --- a/arch/arm/mach-prima2/platsmp.c +++ b/arch/arm/mach-prima2/platsmp.c @@ -18,7 +18,6 @@ #include #include #include -#include #include "common.h" -- cgit v1.1 From dbaf6a8d5de7b63f85eea10a47681f920cbf7385 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Tue, 19 Mar 2013 23:08:43 +0100 Subject: ARM: sirf: enable support in multi_v7_defconfig This enables all sirf specific drivers in the defconfig. Signed-off-by: Arnd Bergmann Reviewed-by: Barry Song --- arch/arm/configs/multi_v7_defconfig | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig index e31d442..44ec305 100644 --- a/arch/arm/configs/multi_v7_defconfig +++ b/arch/arm/configs/multi_v7_defconfig @@ -3,6 +3,7 @@ CONFIG_NO_HZ=y CONFIG_HIGH_RES_TIMERS=y CONFIG_ARCH_MVEBU=y CONFIG_MACH_ARMADA_370=y +CONFIG_ARCH_SIRF=y CONFIG_MACH_ARMADA_XP=y CONFIG_ARCH_HIGHBANK=y CONFIG_ARCH_SOCFPGA=y @@ -34,12 +35,16 @@ CONFIG_SERIAL_8250_DW=y CONFIG_SERIAL_AMBA_PL011=y CONFIG_SERIAL_AMBA_PL011_CONSOLE=y CONFIG_SERIAL_OF_PLATFORM=y +CONFIG_SERIAL_SIRFSOC=y +CONFIG_SERIAL_SIRFSOC_CONSOLE=y CONFIG_IPMI_HANDLER=y CONFIG_IPMI_SI=y CONFIG_I2C=y CONFIG_I2C_DESIGNWARE_PLATFORM=y +CONFIG_I2C_SIRF=y CONFIG_SPI=y CONFIG_SPI_PL022=y +CONFIG_SPI_SIRF=y CONFIG_FB=y CONFIG_FB_ARMCLCD=y CONFIG_FRAMEBUFFER_CONSOLE=y @@ -58,3 +63,4 @@ CONFIG_RTC_CLASS=y CONFIG_RTC_DRV_PL031=y CONFIG_DMADEVICES=y CONFIG_PL330_DMA=y +CONFIG_SIRF_DMA=y -- cgit v1.1