From 4e09f4a6b620d6617f2ce7ee858c6d98176d156e Mon Sep 17 00:00:00 2001 From: Andrzej Hajda Date: Mon, 23 Jan 2017 11:05:49 +0100 Subject: arm64: dts: exynos: configure TV path clocks for Ultra HD modes Ultra HD modes requires clock ticking at increased rate. Signed-off-by: Andrzej Hajda Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi b/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi index a5c8669..13a0950 100644 --- a/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi @@ -217,6 +217,18 @@ assigned-clock-parents = <&cmu_top CLK_FOUT_AUD_PLL>; }; +&cmu_disp { + assigned-clocks = <&cmu_mif CLK_MOUT_SCLK_DECON_TV_ECLK_A>, + <&cmu_mif CLK_DIV_SCLK_DECON_TV_ECLK>, + <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK_USER>, + <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK>; + assigned-clock-parents = <&cmu_mif CLK_MOUT_BUS_PLL_DIV2>, + <0>, + <&cmu_mif CLK_SCLK_DECON_TV_ECLK_DISP>, + <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK_USER>; + assigned-clock-rates = <0>, <400000000>; +}; + &cmu_fsys { assigned-clocks = <&cmu_top CLK_MOUT_SCLK_USBDRD30>, <&cmu_top CLK_MOUT_SCLK_USBHOST30>, -- cgit v1.1