From f0a78909bd6fc48c50d6557bac95a589d2f987d4 Mon Sep 17 00:00:00 2001 From: Duc Dang Date: Mon, 20 Jun 2016 18:26:35 -0700 Subject: arm64: dts: apm: Fix timer interrupt polarity for X-Gene 2 SoC Correct X-Gene 2 timer interrupt polarity as low-level triggered. Signed-off-by: Duc Dang --- arch/arm64/boot/dts/apm/apm-shadowcat.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'arch/arm64/boot/dts/apm') diff --git a/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi b/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi index e5ced2a..21028b1 100644 --- a/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi +++ b/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi @@ -198,10 +198,10 @@ timer { compatible = "arm,armv8-timer"; - interrupts = <1 0 0xff04>, /* Secure Phys IRQ */ - <1 13 0xff04>, /* Non-secure Phys IRQ */ - <1 14 0xff04>, /* Virt IRQ */ - <1 15 0xff04>; /* Hyp IRQ */ + interrupts = <1 0 0xff08>, /* Secure Phys IRQ */ + <1 13 0xff08>, /* Non-secure Phys IRQ */ + <1 14 0xff08>, /* Virt IRQ */ + <1 15 0xff08>; /* Hyp IRQ */ clock-frequency = <50000000>; }; -- cgit v1.1