From 98f420b23a62e0c9df78c5851860d47bf1bc87dd Mon Sep 17 00:00:00 2001 From: dmitry pervushin Date: Sun, 31 May 2009 13:32:11 +0100 Subject: [ARM] 5532/1: Freescale STMP: register definitions [3/3] Replace HW_zzz register access macros by regular __raw_readl/__raw_writel calls Signed-off-by: dmitry pervushin Signed-off-by: Russell King --- arch/arm/plat-stmp3xxx/include/mach/dma.h | 16 +- arch/arm/plat-stmp3xxx/include/mach/pinmux.h | 7 +- arch/arm/plat-stmp3xxx/include/mach/platform.h | 21 +++ .../arm/plat-stmp3xxx/include/mach/stmp3xxx_regs.h | 195 --------------------- arch/arm/plat-stmp3xxx/include/mach/system.h | 8 +- 5 files changed, 36 insertions(+), 211 deletions(-) delete mode 100644 arch/arm/plat-stmp3xxx/include/mach/stmp3xxx_regs.h (limited to 'arch/arm/plat-stmp3xxx/include') diff --git a/arch/arm/plat-stmp3xxx/include/mach/dma.h b/arch/arm/plat-stmp3xxx/include/mach/dma.h index 1e305b2..7c58557 100644 --- a/arch/arm/plat-stmp3xxx/include/mach/dma.h +++ b/arch/arm/plat-stmp3xxx/include/mach/dma.h @@ -25,16 +25,14 @@ #define MAX_PIO_WORDS (15) #endif -#define STMP3XXX_BUS_APBH 0 -#define STMP3XXX_BUS_APBX 1 +#define STMP3XXX_BUS_APBH 0 +#define STMP3XXX_BUS_APBX 1 #define STMP3XXX_DMA_MAX_CHANNEL 16 - - -#define STMP3xxx_DMA(channel, bus) ((bus) * 16 + (channel)) - -#define MAX_DMA_ADDRESS 0xffffffff - -#define MAX_DMA_CHANNELS 32 +#define STMP3XXX_DMA_BUS(dma) ((dma) / 16) +#define STMP3XXX_DMA_CHANNEL(dma) ((dma) % 16) +#define STMP3XXX_DMA(channel, bus) ((bus) * 16 + (channel)) +#define MAX_DMA_ADDRESS 0xffffffff +#define MAX_DMA_CHANNELS 32 struct stmp3xxx_dma_command { u32 next; diff --git a/arch/arm/plat-stmp3xxx/include/mach/pinmux.h b/arch/arm/plat-stmp3xxx/include/mach/pinmux.h index 526c068..cc5af82 100644 --- a/arch/arm/plat-stmp3xxx/include/mach/pinmux.h +++ b/arch/arm/plat-stmp3xxx/include/mach/pinmux.h @@ -146,10 +146,9 @@ struct stmp3xxx_pinmux_bank { u8 strengths[HW_DRIVE_PINDRV_NUM]; /* GPIO things */ - void __iomem *hw_gpio_read, - *hw_gpio_set, - *hw_gpio_clr, - *hw_gpio_doe; + void __iomem *hw_gpio_in, + *hw_gpio_out, + *hw_gpio_doe; int irq, virq; }; diff --git a/arch/arm/plat-stmp3xxx/include/mach/platform.h b/arch/arm/plat-stmp3xxx/include/mach/platform.h index 525c413..7007dda 100644 --- a/arch/arm/plat-stmp3xxx/include/mach/platform.h +++ b/arch/arm/plat-stmp3xxx/include/mach/platform.h @@ -14,6 +14,9 @@ #ifndef __ASM_PLAT_PLATFORM_H #define __ASM_PLAT_PLATFORM_H +#ifndef __ASSEMBLER__ +#include +#endif #include /* Virtual address where registers are mapped */ @@ -44,4 +47,22 @@ #define IRQ_PRIORITY_REG_WR HW_ICOLL_INTERRUPTn_WR #endif +#define HW_STMP3XXX_SET 0x04 +#define HW_STMP3XXX_CLR 0x08 +#define HW_STMP3XXX_TOG 0x0c + +#ifndef __ASSEMBLER__ +static inline void stmp3xxx_clearl(u32 v, void __iomem *r) +{ + __raw_writel(v, r + HW_STMP3XXX_CLR); +} + +static inline void stmp3xxx_setl(u32 v, void __iomem *r) +{ + __raw_writel(v, r + HW_STMP3XXX_SET); +} +#endif + +#define BF(value, field) (((value) << BP_##field) & BM_##field) + #endif /* __ASM_ARCH_PLATFORM_H */ diff --git a/arch/arm/plat-stmp3xxx/include/mach/stmp3xxx_regs.h b/arch/arm/plat-stmp3xxx/include/mach/stmp3xxx_regs.h deleted file mode 100644 index 47797b2..0000000 --- a/arch/arm/plat-stmp3xxx/include/mach/stmp3xxx_regs.h +++ /dev/null @@ -1,195 +0,0 @@ -/* - * Freescale STMP37XX/STMP378X SoC register access interfaces - * - * The SoC registers may be accessed via: - * - * - single 32 bit address, or - * - four 32 bit addresses - general purpose, set, clear and toggle bits - * - * Multiple IP blocks (e.g. SSP, UART) provide identical register sets per - * each module - * - * Embedded Alley Solutions, Inc - * - * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - */ - -/* - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ -#ifndef __ASM_PLAT_STMP3XXX_REGS_H -#define __ASM_PLAT_STMP3XXX_REGS_H - -#ifndef __ASSEMBLER__ -#include -#endif - -#include "platform.h" - -#define REGS_BASE STMP3XXX_REGS_BASE - -#define HW_STMP3xxx_SET 0x04 -#define HW_STMP3xxx_CLR 0x08 -#define HW_STMP3xxx_TOG 0x0c - -#ifndef __ASSEMBLER__ -#define HW_REGISTER_FUNCS(id, base, offset, regset, rd, wr) \ - static const u32 id##_OFFSET = offset; \ - static inline u32 id##_RD_NB(const void __iomem *regbase) { \ - if (!rd) \ - printk(KERN_ERR"%s: cannot READ at %p+%x\n", \ - #id, regbase, offset); \ - return __raw_readl(regbase + offset); \ - } \ - static inline void id##_WR_NB(void __iomem *regbase, u32 v) { \ - if (!wr) \ - printk(KERN_ERR"%s: cannot WRITE at %p+%x\n", \ - #id, regbase, offset); \ - __raw_writel(v, regbase + offset); \ - } \ - static inline void id##_SET_NB(void __iomem *regbase, u32 v) { \ - if (!wr) \ - printk(KERN_ERR"%s: cannot SET at %p+%x\n", \ - #id, regbase, offset); \ - if (regset) \ - __raw_writel(v, regbase + \ - offset + HW_STMP3xxx_SET); \ - else \ - __raw_writel(v | __raw_readl(regbase + offset), \ - regbase + offset); \ - } \ - static inline void id##_CLR_NB(void __iomem *regbase, u32 v) { \ - if (!wr) \ - printk(KERN_ERR"%s: cannot CLR at %p+%x\n", \ - #id, regbase, offset); \ - if (regset) \ - __raw_writel(v, regbase + \ - offset + HW_STMP3xxx_CLR); \ - else \ - __raw_writel( \ - ~v & __raw_readl(regbase + offset), \ - regbase + offset); \ - } \ - static inline void id##_TOG_NB(void __iomem *regbase, u32 v) { \ - if (!wr) \ - printk(KERN_ERR"%s: cannot TOG at %p+%x\n", \ - #id, regbase, offset); \ - if (regset) \ - __raw_writel(v, regbase + \ - offset + HW_STMP3xxx_TOG); \ - else \ - __raw_writel(v ^ __raw_readl(regbase + offset), \ - regbase + offset); \ - } \ - static inline u32 id##_RD(void) { return id##_RD_NB(base); } \ - static inline void id##_WR(u32 v) { id##_WR_NB(base, v); } \ - static inline void id##_SET(u32 v) { id##_SET_NB(base, v); } \ - static inline void id##_CLR(u32 v) { id##_CLR_NB(base, v); } \ - static inline void id##_TOG(u32 v) { id##_TOG_NB(base, v); } - -#define HW_REGISTER_FUNCS_INDEXED(id, base, offset, regset, rd, wr, step)\ - static inline u32 id##_OFFSET(int i) { \ - return offset + i * step; \ - } \ - static inline u32 id##_RD_NB(const void __iomem *regbase, int i) {\ - if (!rd) \ - printk(KERN_ERR"%s(%d): can't READ at %p+%x\n", \ - #id, i, regbase, offset + i * step); \ - return __raw_readl(regbase + offset + i * step); \ - } \ - static inline void id##_WR_NB(void __iomem *regbase, int i, u32 v) {\ - if (!wr) \ - printk(KERN_ERR"%s(%d): can't WRITE at %p+%x\n",\ - #id, i, regbase, offset + i * step); \ - __raw_writel(v, regbase + offset + i * step); \ - } \ - static inline void id##_SET_NB(void __iomem *regbase, int i, u32 v) {\ - if (!wr) \ - printk(KERN_ERR"%s(%d): can't SET at %p+%x\n", \ - #id, i, regbase, offset + i * step); \ - if (regset) \ - __raw_writel(v, regbase + offset + \ - i * step + HW_STMP3xxx_SET); \ - else \ - __raw_writel(v | __raw_readl(regbase + \ - offset + i * step), \ - regbase + offset + i * step); \ - } \ - static inline void id##_CLR_NB(void __iomem *regbase, int i, u32 v) {\ - if (!wr) \ - printk(KERN_ERR"%s(%d): cannot CLR at %p+%x\n", \ - #id, i, regbase, offset + i * step); \ - if (regset) \ - __raw_writel(v, regbase + offset + \ - i * step + HW_STMP3xxx_CLR); \ - else \ - __raw_writel(~v & __raw_readl(regbase + \ - offset + i * step), \ - regbase + offset + i * step); \ - } \ - static inline void id##_TOG_NB(void __iomem *regbase, int i, u32 v) {\ - if (!wr) \ - printk(KERN_ERR"%s(%d): cannot TOG at %p+%x\n", \ - #id, i, regbase, offset + i * step); \ - if (regset) \ - __raw_writel(v, regbase + offset + \ - i * step + HW_STMP3xxx_TOG); \ - else \ - __raw_writel(v ^ __raw_readl(regbase + offset \ - + i * step), \ - regbase + offset + i * step); \ - } \ - static inline u32 id##_RD(int i) \ - { \ - return id##_RD_NB(base, i); \ - } \ - static inline void id##_WR(int i, u32 v) \ - { \ - id##_WR_NB(base, i, v); \ - } \ - static inline void id##_SET(int i, u32 v) \ - { \ - id##_SET_NB(base, i, v); \ - } \ - static inline void id##_CLR(int i, u32 v) \ - { \ - id##_CLR_NB(base, i, v); \ - } \ - static inline void id##_TOG(int i, u32 v) \ - { \ - id##_TOG_NB(base, i, v); \ - } - -#define HW_REGISTER_WO(id, base, offset)\ - HW_REGISTER_FUNCS(id, base, offset, 1, 0, 1) -#define HW_REGISTER_RO(id, base, offset)\ - HW_REGISTER_FUNCS(id, base, offset, 1, 1, 0) -#define HW_REGISTER(id, base, offset) \ - HW_REGISTER_FUNCS(id, base, offset, 1, 1, 1) -#define HW_REGISTER_0(id, base, offset) \ - HW_REGISTER_FUNCS(id, base, offset, 0, 1, 1) -#define HW_REGISTER_INDEXED(id, base, offset, step) \ - HW_REGISTER_FUNCS_INDEXED(id, base, offset, 1, 1, 1, step) -#define HW_REGISTER_RO_INDEXED(id, base, offset, step) \ - HW_REGISTER_FUNCS_INDEXED(id, base, offset, 1, 1, 0, step) -#define HW_REGISTER_0_INDEXED(id, base, offset, step) \ - HW_REGISTER_FUNCS_INDEXED(id, base, offset, 0, 1, 1, step) -#else /* __ASSEMBLER__ */ -#define HW_REGISTER_FUNCS(id, base, offset, regset, rd, wr) -#define HW_REGISTER_FUNCS_INDEXED(id, base, offset, regset, rd, wr, step) -#define HW_REGISTER_WO(id, base, offset) -#define HW_REGISTER_RO(id, base, offset) -#define HW_REGISTER(id, base, offset) -#define HW_REGISTER_0(id, base, offset) -#define HW_REGISTER_INDEXED(id, base, offset, step) -#define HW_REGISTER_RO_INDEXED(id, base, offset, step) -#define HW_REGISTER_0_INDEXED(id, base, offset, step) -#endif /* __ASSEMBLER__ */ - -#endif /* __ASM_PLAT_STMP3XXX_REGS_H */ diff --git a/arch/arm/plat-stmp3xxx/include/mach/system.h b/arch/arm/plat-stmp3xxx/include/mach/system.h index dac48d2..28a9888 100644 --- a/arch/arm/plat-stmp3xxx/include/mach/system.h +++ b/arch/arm/plat-stmp3xxx/include/mach/system.h @@ -17,6 +17,7 @@ #define __ASM_ARCH_SYSTEM_H #include +#include #include #include @@ -33,13 +34,14 @@ static inline void arch_idle(void) static inline void arch_reset(char mode, const char *cmd) { /* Set BATTCHRG to default value */ - HW_POWER_CHARGE_WR(0x00010000); + __raw_writel(0x00010000, REGS_POWER_BASE + HW_POWER_CHARGE); /* Set MINPWR to default value */ - HW_POWER_MINPWR_WR(0); + __raw_writel(0, REGS_POWER_BASE + HW_POWER_MINPWR); /* Reset digital side of chip (but not power or RTC) */ - HW_CLKCTRL_RESET_WR(BM_CLKCTRL_RESET_DIG); + __raw_writel(BM_CLKCTRL_RESET_DIG, + REGS_CLKCTRL_BASE + HW_CLKCTRL_RESET); /* Should not return */ } -- cgit v1.1