From f348a2a2817e9d24b1edd4befc9659ec83501ca5 Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Thu, 3 Jul 2008 11:24:25 +0100 Subject: [ARM] S3C24XX: Add gpiolib support Add support for gpilib on all S3C24XX platforms. Signed-off-by: Ben Dooks --- arch/arm/plat-s3c24xx/Kconfig | 1 + arch/arm/plat-s3c24xx/Makefile | 1 + arch/arm/plat-s3c24xx/gpiolib.c | 259 ++++++++++++++++++++++++++++++++++++++++ 3 files changed, 261 insertions(+) create mode 100644 arch/arm/plat-s3c24xx/gpiolib.c (limited to 'arch/arm/plat-s3c24xx') diff --git a/arch/arm/plat-s3c24xx/Kconfig b/arch/arm/plat-s3c24xx/Kconfig index b66fb3c..1521f1c 100644 --- a/arch/arm/plat-s3c24xx/Kconfig +++ b/arch/arm/plat-s3c24xx/Kconfig @@ -9,6 +9,7 @@ config PLAT_S3C24XX depends on ARCH_S3C2410 default y if ARCH_S3C2410 select NO_IOPORT + select HAVE_GPIO_LIB help Base platform code for any Samsung S3C24XX device diff --git a/arch/arm/plat-s3c24xx/Makefile b/arch/arm/plat-s3c24xx/Makefile index 131d202..b91e625 100644 --- a/arch/arm/plat-s3c24xx/Makefile +++ b/arch/arm/plat-s3c24xx/Makefile @@ -16,6 +16,7 @@ obj-y += cpu.o obj-y += irq.o obj-y += devs.o obj-y += gpio.o +obj-y += gpiolib.o obj-y += time.o obj-y += clock.o diff --git a/arch/arm/plat-s3c24xx/gpiolib.c b/arch/arm/plat-s3c24xx/gpiolib.c new file mode 100644 index 0000000..825d8d0 --- /dev/null +++ b/arch/arm/plat-s3c24xx/gpiolib.c @@ -0,0 +1,259 @@ +/* linux/arch/arm/plat-s3c24xx/gpiolib.c + * + * Copyright (c) 2008 Simtec Electronics + * http://armlinux.simtec.co.uk/ + * Ben Dooks + * + * S3C24XX GPIOlib support + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License. +*/ + +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include + +struct s3c24xx_gpio_chip { + struct gpio_chip chip; + void __iomem *base; +}; + +static inline struct s3c24xx_gpio_chip *to_s3c_chip(struct gpio_chip *gpc) +{ + return container_of(gpc, struct s3c24xx_gpio_chip, chip); +} + +/* these routines are exported for use by other parts of the platform + * and system support, but are not intended to be used directly by the + * drivers themsevles. + */ + +int s3c24xx_gpiolib_input(struct gpio_chip *chip, unsigned offset) +{ + struct s3c24xx_gpio_chip *ourchip = to_s3c_chip(chip); + void __iomem *base = ourchip->base; + unsigned long flags; + unsigned long con; + + local_irq_save(flags); + + con = __raw_readl(base + 0x00); + con &= ~(3 << (offset * 2)); + con |= (S3C2410_GPIO_OUTPUT & 0xf) << (offset * 2); + + __raw_writel(con, base + 0x00); + + local_irq_restore(flags); + return 0; +} + +int s3c24xx_gpiolib_output(struct gpio_chip *chip, + unsigned offset, int value) +{ + struct s3c24xx_gpio_chip *ourchip = to_s3c_chip(chip); + void __iomem *base = ourchip->base; + unsigned long flags; + unsigned long dat; + unsigned long con; + + local_irq_save(flags); + + dat = __raw_readl(base + 0x04); + dat &= ~(1 << offset); + if (value) + dat |= 1 << offset; + __raw_writel(dat, base + 0x04); + + con = __raw_readl(base + 0x00); + con &= ~(3 << (offset * 2)); + con |= (S3C2410_GPIO_OUTPUT & 0xf) << (offset * 2); + + __raw_writel(con, base + 0x00); + __raw_writel(dat, base + 0x04); + + local_irq_restore(flags); + return 0; +} + +void s3c24xx_gpiolib_set(struct gpio_chip *chip, unsigned offset, int value) +{ + struct s3c24xx_gpio_chip *ourchip = to_s3c_chip(chip); + void __iomem *base = ourchip->base; + unsigned long flags; + unsigned long dat; + + local_irq_save(flags); + + dat = __raw_readl(base + 0x04); + dat &= ~(1 << offset); + if (value) + dat |= 1 << offset; + __raw_writel(dat, base + 0x04); + + local_irq_restore(flags); +} + +int s3c24xx_gpiolib_get(struct gpio_chip *chip, unsigned offset) +{ + struct s3c24xx_gpio_chip *ourchip = to_s3c_chip(chip); + unsigned long val; + + val = __raw_readl(ourchip->base + 0x04); + val >>= offset; + val &= 1; + + return val; +} + +static int s3c24xx_gpiolib_banka_input(struct gpio_chip *chip, unsigned offset) +{ + return -EINVAL; +} + +static int s3c24xx_gpiolib_banka_output(struct gpio_chip *chip, + unsigned offset, int value) +{ + struct s3c24xx_gpio_chip *ourchip = to_s3c_chip(chip); + void __iomem *base = ourchip->base; + unsigned long flags; + unsigned long dat; + unsigned long con; + + local_irq_save(flags); + + con = __raw_readl(base + 0x00); + dat = __raw_readl(base + 0x04); + + dat &= ~(1 << offset); + if (value) + dat |= 1 << offset; + + __raw_writel(dat, base + 0x04); + + con &= ~(1 << offset); + + __raw_writel(con, base + 0x00); + __raw_writel(dat, base + 0x04); + + local_irq_restore(flags); + return 0; +} + + +struct s3c24xx_gpio_chip gpios[] = { + [0] = { + .base = S3C24XX_GPIO_BASE(S3C2410_GPA0), + .chip = { + .base = S3C2410_GPA0, + .owner = THIS_MODULE, + .label = "GPIOA", + .ngpio = 24, + .direction_input = s3c24xx_gpiolib_banka_input, + .direction_output = s3c24xx_gpiolib_banka_output, + .set = s3c24xx_gpiolib_set, + .get = s3c24xx_gpiolib_get, + }, + }, + [1] = { + .base = S3C24XX_GPIO_BASE(S3C2410_GPB0), + .chip = { + .base = S3C2410_GPB0, + .owner = THIS_MODULE, + .label = "GPIOB", + .ngpio = 16, + .direction_input = s3c24xx_gpiolib_input, + .direction_output = s3c24xx_gpiolib_output, + .set = s3c24xx_gpiolib_set, + .get = s3c24xx_gpiolib_get, + }, + }, + [2] = { + .base = S3C24XX_GPIO_BASE(S3C2410_GPC0), + .chip = { + .base = S3C2410_GPC0, + .owner = THIS_MODULE, + .label = "GPIOC", + .ngpio = 16, + .direction_input = s3c24xx_gpiolib_input, + .direction_output = s3c24xx_gpiolib_output, + .set = s3c24xx_gpiolib_set, + .get = s3c24xx_gpiolib_get, + }, + }, + [3] = { + .base = S3C24XX_GPIO_BASE(S3C2410_GPD0), + .chip = { + .base = S3C2410_GPD0, + .owner = THIS_MODULE, + .label = "GPIOD", + .ngpio = 16, + .direction_input = s3c24xx_gpiolib_input, + .direction_output = s3c24xx_gpiolib_output, + .set = s3c24xx_gpiolib_set, + .get = s3c24xx_gpiolib_get, + }, + }, + [4] = { + .base = S3C24XX_GPIO_BASE(S3C2410_GPE0), + .chip = { + .base = S3C2410_GPE0, + .label = "GPIOE", + .owner = THIS_MODULE, + .ngpio = 16, + .direction_input = s3c24xx_gpiolib_input, + .direction_output = s3c24xx_gpiolib_output, + .set = s3c24xx_gpiolib_set, + .get = s3c24xx_gpiolib_get, + }, + }, + [5] = { + .base = S3C24XX_GPIO_BASE(S3C2410_GPF0), + .chip = { + .base = S3C2410_GPF0, + .owner = THIS_MODULE, + .label = "GPIOF", + .ngpio = 8, + .direction_input = s3c24xx_gpiolib_input, + .direction_output = s3c24xx_gpiolib_output, + .set = s3c24xx_gpiolib_set, + .get = s3c24xx_gpiolib_get, + }, + }, + [6] = { + .base = S3C24XX_GPIO_BASE(S3C2410_GPG0), + .chip = { + .base = S3C2410_GPG0, + .owner = THIS_MODULE, + .label = "GPIOG", + .ngpio = 10, + .direction_input = s3c24xx_gpiolib_input, + .direction_output = s3c24xx_gpiolib_output, + .set = s3c24xx_gpiolib_set, + .get = s3c24xx_gpiolib_get, + }, + }, +}; + +static __init int s3c24xx_gpiolib_init(void) +{ + struct s3c24xx_gpio_chip *chip = gpios; + int gpn; + + for (gpn = 0; gpn < ARRAY_SIZE(gpios); gpn++, chip++) + gpiochip_add(&chip->chip); + + return 0; +} + +arch_initcall(s3c24xx_gpiolib_init); -- cgit v1.1