From 8ea0de4b8831513924e3ec6a17bb721fabf97055 Mon Sep 17 00:00:00 2001 From: Nicolas Pitre Date: Thu, 28 Apr 2011 17:00:17 -0400 Subject: ARM: zImage: remove the static qualifier from global data variables To be able to relocate the .bss section at run time independently from the rest of the code, we must make sure that no GOTOFF relocations are used with .bss symbols. This usually means that no global variables can be marked static unless they're also const. Let's remove the static qualifier from current offenders, or turn them into const variables when possible. Next commit will ensure the build fails if one of those is reintroduced due to otherwise enforced coding standards for the kernel. Signed-off-by: Nicolas Pitre Tested-by: Tony Lindgren --- arch/arm/plat-mxc/include/mach/uncompress.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm/plat-mxc') diff --git a/arch/arm/plat-mxc/include/mach/uncompress.h b/arch/arm/plat-mxc/include/mach/uncompress.h index 4864b0a..d85e2d1 100644 --- a/arch/arm/plat-mxc/include/mach/uncompress.h +++ b/arch/arm/plat-mxc/include/mach/uncompress.h @@ -21,7 +21,7 @@ #include -static unsigned long uart_base; +unsigned long uart_base; #define UART(x) (*(volatile unsigned long *)(uart_base + (x))) -- cgit v1.1 From 2d95378b043f082192a11f8476e3f63291c3477b Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Fri, 25 Mar 2011 12:52:47 -0300 Subject: ARM: mx53: Print silicon revision on boot MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Having the silicon revision to appear on the boot log is a useful information. MX31, MX35 and MX51 already show the silicon revision on boot. Add support for displaying such information for MX53 as well. Tested on a mx53loco board, where it shows: CPU identified as i.MX53, silicon rev 2.0 Signed-off-by: Fabio Estevam LAKML-Reference: 1301068367-18937-1-git-send-email-fabio.estevam@freescale.com Signed-off-by: Uwe Kleine-König Signed-off-by: Sascha Hauer --- arch/arm/plat-mxc/include/mach/common.h | 1 + arch/arm/plat-mxc/include/mach/mx53.h | 13 ------------- 2 files changed, 1 insertion(+), 13 deletions(-) (limited to 'arch/arm/plat-mxc') diff --git a/arch/arm/plat-mxc/include/mach/common.h b/arch/arm/plat-mxc/include/mach/common.h index a22ebe1..bfa1ffc 100644 --- a/arch/arm/plat-mxc/include/mach/common.h +++ b/arch/arm/plat-mxc/include/mach/common.h @@ -68,4 +68,5 @@ extern void mxc91231_arch_reset(int, const char *); extern void mxc91231_prepare_idle(void); extern void mx51_efikamx_reset(void); extern int mx53_revision(void); +extern int mx53_display_revision(void); #endif diff --git a/arch/arm/plat-mxc/include/mach/mx53.h b/arch/arm/plat-mxc/include/mach/mx53.h index ace1786..9d2a1ef 100644 --- a/arch/arm/plat-mxc/include/mach/mx53.h +++ b/arch/arm/plat-mxc/include/mach/mx53.h @@ -337,17 +337,4 @@ #define MX53_INT_GPIO7_LOW 107 #define MX53_INT_GPIO7_HIGH 108 -/* silicon revisions specific to i.MX53 */ -#define MX53_CHIP_REV_1_0 0x10 -#define MX53_CHIP_REV_1_1 0x11 -#define MX53_CHIP_REV_1_2 0x12 -#define MX53_CHIP_REV_1_3 0x13 -#define MX53_CHIP_REV_2_0 0x20 -#define MX53_CHIP_REV_2_1 0x21 -#define MX53_CHIP_REV_2_2 0x22 -#define MX53_CHIP_REV_2_3 0x23 -#define MX53_CHIP_REV_3_0 0x30 -#define MX53_CHIP_REV_3_1 0x31 -#define MX53_CHIP_REV_3_2 0x32 - #endif /* ifndef __MACH_MX53_H__ */ -- cgit v1.1 From 986e5f08de25050e893411aef56776d84d3530b6 Mon Sep 17 00:00:00 2001 From: Wolfram Sang Date: Thu, 10 Mar 2011 20:55:04 +0100 Subject: ARM: mx27: fix gpt4/5 base address MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Reported-by: Igor Trevisan Signed-off-by: Wolfram Sang LAKML-Reference: 1299786904-5494-1-git-send-email-w.sang@pengutronix.de Signed-off-by: Uwe Kleine-König Signed-off-by: Sascha Hauer --- arch/arm/plat-mxc/include/mach/mx27.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm/plat-mxc') diff --git a/arch/arm/plat-mxc/include/mach/mx27.h b/arch/arm/plat-mxc/include/mach/mx27.h index cbc43ad..1dc1c52 100644 --- a/arch/arm/plat-mxc/include/mach/mx27.h +++ b/arch/arm/plat-mxc/include/mach/mx27.h @@ -60,8 +60,8 @@ #define MX27_AUDMUX_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x16000) #define MX27_CSPI3_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x17000) #define MX27_MSHC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x18000) -#define MX27_GPT5_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x19000) -#define MX27_GPT4_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x1a000) +#define MX27_GPT4_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x19000) +#define MX27_GPT5_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x1a000) #define MX27_UART5_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x1b000) #define MX27_UART6_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x1c000) #define MX27_I2C2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x1d000) -- cgit v1.1 From fdaf0ef72a1d0ef58d56923773491f24e2c3ae6a Mon Sep 17 00:00:00 2001 From: Baruch Siach Date: Mon, 14 Mar 2011 11:40:21 +0200 Subject: ARM: imx/mx25: add NAND chip select pins to iomux MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Baruch Siach LAKML-Reference: cae1d71db47204ee2654eca7391cb656ed53566b.1300095569.git.baruch@tkos.co.il Signed-off-by: Uwe Kleine-König Signed-off-by: Sascha Hauer --- arch/arm/plat-mxc/include/mach/iomux-mx25.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'arch/arm/plat-mxc') diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx25.h b/arch/arm/plat-mxc/include/mach/iomux-mx25.h index d7f52c9..2e5244d 100644 --- a/arch/arm/plat-mxc/include/mach/iomux-mx25.h +++ b/arch/arm/plat-mxc/include/mach/iomux-mx25.h @@ -89,13 +89,16 @@ #define MX25_PAD_CS0__GPIO_4_2 IOMUX_PAD(0x000, 0x04c, 0x05, 0, 0, NO_PAD_CTRL) #define MX25_PAD_CS1__CS1 IOMUX_PAD(0x000, 0x050, 0x00, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CS1__NF_CE3 IOMUX_PAD(0x000, 0x050, 0x01, 0, 0, NO_PAD_CTRL) #define MX25_PAD_CS1__GPIO_4_3 IOMUX_PAD(0x000, 0x050, 0x05, 0, 0, NO_PAD_CTRL) #define MX25_PAD_CS4__CS4 IOMUX_PAD(0x264, 0x054, 0x10, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CS4__NF_CE1 IOMUX_PAD(0x264, 0x054, 0x01, 0, 0, NO_PAD_CTRL) #define MX25_PAD_CS4__UART5_CTS IOMUX_PAD(0x264, 0x054, 0x13, 0, 0, NO_PAD_CTRL) #define MX25_PAD_CS4__GPIO_3_20 IOMUX_PAD(0x264, 0x054, 0x15, 0, 0, NO_PAD_CTRL) #define MX25_PAD_CS5__CS5 IOMUX_PAD(0x268, 0x058, 0x10, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CS5__NF_CE2 IOMUX_PAD(0x268, 0x058, 0x01, 0, 0, NO_PAD_CTRL) #define MX25_PAD_CS5__UART5_RTS IOMUX_PAD(0x268, 0x058, 0x13, 0x574, 0, NO_PAD_CTRL) #define MX25_PAD_CS5__GPIO_3_21 IOMUX_PAD(0x268, 0x058, 0x15, 0, 0, NO_PAD_CTRL) -- cgit v1.1 From 83422671c3e93b8ef77805fbad74173a1636d5f1 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Tue, 1 Mar 2011 11:04:34 +0100 Subject: ARM: mx3: dynamically allocate "mxc_rtc" devices MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit LAKML-Reference: 1299271882-2130-2-git-send-email-u.kleine-koenig@pengutronix.de Signed-off-by: Uwe Kleine-König Signed-off-by: Sascha Hauer --- arch/arm/plat-mxc/devices/Kconfig | 3 ++ arch/arm/plat-mxc/devices/Makefile | 1 + arch/arm/plat-mxc/devices/platform-mxc_rtc.c | 40 +++++++++++++++++++++++++ arch/arm/plat-mxc/include/mach/devices-common.h | 9 ++++++ 4 files changed, 53 insertions(+) create mode 100644 arch/arm/plat-mxc/devices/platform-mxc_rtc.c (limited to 'arch/arm/plat-mxc') diff --git a/arch/arm/plat-mxc/devices/Kconfig b/arch/arm/plat-mxc/devices/Kconfig index b9ab1d5..0e8d7ab 100644 --- a/arch/arm/plat-mxc/devices/Kconfig +++ b/arch/arm/plat-mxc/devices/Kconfig @@ -63,6 +63,9 @@ config IMX_HAVE_PLATFORM_MXC_RNGA bool select ARCH_HAS_RNGA +config IMX_HAVE_PLATFORM_MXC_RTC + bool + config IMX_HAVE_PLATFORM_MXC_W1 bool diff --git a/arch/arm/plat-mxc/devices/Makefile b/arch/arm/plat-mxc/devices/Makefile index 75cd2ec..ca227eae 100644 --- a/arch/arm/plat-mxc/devices/Makefile +++ b/arch/arm/plat-mxc/devices/Makefile @@ -19,6 +19,7 @@ obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_MMC) += platform-mxc-mmc.o obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_NAND) += platform-mxc_nand.o obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_PWM) += platform-mxc_pwm.o obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_RNGA) += platform-mxc_rnga.o +obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_RTC) += platform-mxc_rtc.o obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_W1) += platform-mxc_w1.o obj-$(CONFIG_IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX) += platform-sdhci-esdhc-imx.o obj-$(CONFIG_IMX_HAVE_PLATFORM_SPI_IMX) += platform-spi_imx.o diff --git a/arch/arm/plat-mxc/devices/platform-mxc_rtc.c b/arch/arm/plat-mxc/devices/platform-mxc_rtc.c new file mode 100644 index 0000000..16d0ec4 --- /dev/null +++ b/arch/arm/plat-mxc/devices/platform-mxc_rtc.c @@ -0,0 +1,40 @@ +/* + * Copyright (C) 2010-2011 Pengutronix + * Uwe Kleine-Koenig + * + * This program is free software; you can redistribute it and/or modify it under + * the terms of the GNU General Public License version 2 as published by the + * Free Software Foundation. + */ +#include +#include + +#define imx_mxc_rtc_data_entry_single(soc) \ + { \ + .iobase = soc ## _RTC_BASE_ADDR, \ + .irq = soc ## _INT_RTC, \ + } + +#ifdef CONFIG_SOC_IMX31 +const struct imx_mxc_rtc_data imx31_mxc_rtc_data __initconst = + imx_mxc_rtc_data_entry_single(MX31); +#endif /* ifdef CONFIG_SOC_IMX31 */ + +struct platform_device *__init imx_add_mxc_rtc( + const struct imx_mxc_rtc_data *data) +{ + struct resource res[] = { + { + .start = data->iobase, + .end = data->iobase + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, { + .start = data->irq, + .end = data->irq, + .flags = IORESOURCE_IRQ, + }, + }; + + return imx_add_platform_device("mxc_rtc", -1, + res, ARRAY_SIZE(res), NULL, 0); +} diff --git a/arch/arm/plat-mxc/include/mach/devices-common.h b/arch/arm/plat-mxc/include/mach/devices-common.h index 8658c9c..b0bc198 100644 --- a/arch/arm/plat-mxc/include/mach/devices-common.h +++ b/arch/arm/plat-mxc/include/mach/devices-common.h @@ -237,6 +237,15 @@ struct imx_mxc_pwm_data { struct platform_device *__init imx_add_mxc_pwm( const struct imx_mxc_pwm_data *data); +/* mxc_rtc */ +struct imx_mxc_rtc_data { + resource_size_t iobase; + resource_size_t irq; +}; +struct platform_device *__init imx_add_mxc_rtc( + const struct imx_mxc_rtc_data *data); + +/* mxc_w1 */ struct imx_mxc_w1_data { resource_size_t iobase; }; -- cgit v1.1 From afa77ef30ead4865ce2c0c1c55054d45521ce1c7 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Thu, 3 Mar 2011 21:32:02 +0100 Subject: ARM: mx3: dynamically allocate "ipu-core" devices MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit ... together with the related devices "mx3_camera" and "mx3_sdc_fb". "mx3_camera" doesn't fit the scheme of the other devices that just are allocated and registered in a single function because it needs additional care to get some dmaable memory. So currently imx31_alloc_mx3_camera duplicates most of imx_add_platform_device_dmamask, but I'm not sure it's worth to split the latter to be able to reuse more code. This gets rid of mach-mx3/devices.[ch] and so several files need to be adapted not to #include devices.h anymore. LAKML-Reference: 1299271882-2130-5-git-send-email-u.kleine-koenig@pengutronix.de Signed-off-by: Uwe Kleine-König Signed-off-by: Sascha Hauer --- arch/arm/plat-mxc/devices/Kconfig | 3 + arch/arm/plat-mxc/devices/Makefile | 1 + arch/arm/plat-mxc/devices/platform-ipu-core.c | 129 ++++++++++++++++++++++++ arch/arm/plat-mxc/include/mach/devices-common.h | 18 ++++ 4 files changed, 151 insertions(+) create mode 100644 arch/arm/plat-mxc/devices/platform-ipu-core.c (limited to 'arch/arm/plat-mxc') diff --git a/arch/arm/plat-mxc/devices/Kconfig b/arch/arm/plat-mxc/devices/Kconfig index 0e8d7ab..a860b16 100644 --- a/arch/arm/plat-mxc/devices/Kconfig +++ b/arch/arm/plat-mxc/devices/Kconfig @@ -41,6 +41,9 @@ config IMX_HAVE_PLATFORM_IMX_UART config IMX_HAVE_PLATFORM_IMX_UDC bool +config IMX_HAVE_PLATFORM_IPU_CORE + bool + config IMX_HAVE_PLATFORM_MX1_CAMERA bool diff --git a/arch/arm/plat-mxc/devices/Makefile b/arch/arm/plat-mxc/devices/Makefile index ca227eae..ad2922a 100644 --- a/arch/arm/plat-mxc/devices/Makefile +++ b/arch/arm/plat-mxc/devices/Makefile @@ -12,6 +12,7 @@ obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_KEYPAD) += platform-imx-keypad.o obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_SSI) += platform-imx-ssi.o obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_UART) += platform-imx-uart.o obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_UDC) += platform-imx_udc.o +obj-$(CONFIG_IMX_HAVE_PLATFORM_IPU_CORE) += platform-ipu-core.o obj-$(CONFIG_IMX_HAVE_PLATFORM_MX1_CAMERA) += platform-mx1-camera.o obj-$(CONFIG_IMX_HAVE_PLATFORM_MX2_CAMERA) += platform-mx2-camera.o obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_EHCI) += platform-mxc-ehci.o diff --git a/arch/arm/plat-mxc/devices/platform-ipu-core.c b/arch/arm/plat-mxc/devices/platform-ipu-core.c new file mode 100644 index 0000000..edf6503 --- /dev/null +++ b/arch/arm/plat-mxc/devices/platform-ipu-core.c @@ -0,0 +1,129 @@ +/* + * Copyright (C) 2011 Pengutronix + * Uwe Kleine-Koenig + * + * This program is free software; you can redistribute it and/or modify it under + * the terms of the GNU General Public License version 2 as published by the + * Free Software Foundation. + */ +#include +#include + +#define imx_ipu_core_entry_single(soc) \ +{ \ + .iobase = soc ## _IPU_CTRL_BASE_ADDR, \ + .synirq = soc ## _INT_IPU_SYN, \ + .errirq = soc ## _INT_IPU_ERR, \ +} + +#ifdef CONFIG_SOC_IMX31 +const struct imx_ipu_core_data imx31_ipu_core_data __initconst = + imx_ipu_core_entry_single(MX31); +#endif + +#ifdef CONFIG_SOC_IMX35 +const struct imx_ipu_core_data imx35_ipu_core_data __initconst = + imx_ipu_core_entry_single(MX35); +#endif + +static struct platform_device *imx_ipu_coredev __initdata; + +struct platform_device *__init imx_add_ipu_core( + const struct imx_ipu_core_data *data, + const struct ipu_platform_data *pdata) +{ + /* The resource order is important! */ + struct resource res[] = { + { + .start = data->iobase, + .end = data->iobase + 0x5f, + .flags = IORESOURCE_MEM, + }, { + .start = data->iobase + 0x88, + .end = data->iobase + 0xb3, + .flags = IORESOURCE_MEM, + }, { + .start = data->synirq, + .end = data->synirq, + .flags = IORESOURCE_IRQ, + }, { + .start = data->errirq, + .end = data->errirq, + .flags = IORESOURCE_IRQ, + }, + }; + + return imx_ipu_coredev = imx_add_platform_device("ipu-core", -1, + res, ARRAY_SIZE(res), pdata, sizeof(*pdata)); +} + +struct platform_device *__init imx_alloc_mx3_camera( + const struct imx_ipu_core_data *data, + const struct mx3_camera_pdata *pdata) +{ + struct resource res[] = { + { + .start = data->iobase + 0x60, + .end = data->iobase + 0x87, + .flags = IORESOURCE_MEM, + }, + }; + int ret = -ENOMEM; + struct platform_device *pdev; + + if (IS_ERR_OR_NULL(imx_ipu_coredev)) + return ERR_PTR(-ENODEV); + + pdev = platform_device_alloc("mx3-camera", 0); + if (!pdev) + goto err; + + pdev->dev.dma_mask = kmalloc(sizeof(*pdev->dev.dma_mask), GFP_KERNEL); + if (!pdev->dev.dma_mask) + goto err; + + *pdev->dev.dma_mask = DMA_BIT_MASK(32); + pdev->dev.coherent_dma_mask = DMA_BIT_MASK(32); + + ret = platform_device_add_resources(pdev, res, ARRAY_SIZE(res)); + if (ret) + goto err; + + if (pdata) { + struct mx3_camera_pdata *copied_pdata; + + ret = platform_device_add_data(pdev, pdata, sizeof(*pdata)); + if (ret) { +err: + kfree(pdev->dev.dma_mask); + platform_device_put(pdev); + return ERR_PTR(-ENODEV); + } + copied_pdata = dev_get_platdata(&pdev->dev); + copied_pdata->dma_dev = &imx_ipu_coredev->dev; + } + + return pdev; +} + +struct platform_device *__init imx_add_mx3_sdc_fb( + const struct imx_ipu_core_data *data, + struct mx3fb_platform_data *pdata) +{ + struct resource res[] = { + { + .start = data->iobase + 0xb4, + .end = data->iobase + 0x1bf, + .flags = IORESOURCE_MEM, + }, + }; + + if (IS_ERR_OR_NULL(imx_ipu_coredev)) + return ERR_PTR(-ENODEV); + + pdata->dma_dev = &imx_ipu_coredev->dev; + + return imx_add_platform_device_dmamask("mx3_sdc_fb", -1, + res, ARRAY_SIZE(res), pdata, sizeof(*pdata), + DMA_BIT_MASK(32)); +} diff --git a/arch/arm/plat-mxc/include/mach/devices-common.h b/arch/arm/plat-mxc/include/mach/devices-common.h index b0bc198..fa84773 100644 --- a/arch/arm/plat-mxc/include/mach/devices-common.h +++ b/arch/arm/plat-mxc/include/mach/devices-common.h @@ -166,6 +166,24 @@ struct platform_device *__init imx_add_imx_udc( const struct imx_imx_udc_data *data, const struct imxusb_platform_data *pdata); +#include +#include +#include +struct imx_ipu_core_data { + resource_size_t iobase; + resource_size_t synirq; + resource_size_t errirq; +}; +struct platform_device *__init imx_add_ipu_core( + const struct imx_ipu_core_data *data, + const struct ipu_platform_data *pdata); +struct platform_device *__init imx_alloc_mx3_camera( + const struct imx_ipu_core_data *data, + const struct mx3_camera_pdata *pdata); +struct platform_device *__init imx_add_mx3_sdc_fb( + const struct imx_ipu_core_data *data, + struct mx3fb_platform_data *pdata); + #include struct imx_mx1_camera_data { resource_size_t iobase; -- cgit v1.1 From 18879e13b11b8c173a773edb258da51abc0bd2cd Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Mon, 6 Dec 2010 10:03:18 +0100 Subject: ARM: imx51: use platform id 2 for imx51-cspi MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The platform id is used to determine the spi bus number, so it should better be different to the ids used for imx51-ecspi. Otherwise it's not possible to use both devices "imx51-cspi.0" and "imx51-ecspi.0". Alternative approaches are to use dynamic bus numbering as offered by the spi framework or let the machine code set the bus number. The downside of both possibilities is that the bus number isn't fixed for the same busses on different machines using i.MX51. LAKML-Reference: 1302100716-21034-1-git-send-email-u.kleine-koenig@pengutronix.de Signed-off-by: Uwe Kleine-König Signed-off-by: Sascha Hauer --- arch/arm/plat-mxc/devices/platform-spi_imx.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm/plat-mxc') diff --git a/arch/arm/plat-mxc/devices/platform-spi_imx.c b/arch/arm/plat-mxc/devices/platform-spi_imx.c index f4a60ab..f97eb36 100644 --- a/arch/arm/plat-mxc/devices/platform-spi_imx.c +++ b/arch/arm/plat-mxc/devices/platform-spi_imx.c @@ -80,7 +80,7 @@ const struct imx_spi_imx_data imx35_cspi_data[] __initconst = { #ifdef CONFIG_SOC_IMX51 const struct imx_spi_imx_data imx51_cspi_data __initconst = - imx_spi_imx_data_entry_single(MX51, CSPI, "imx51-cspi", 0, , SZ_4K); + imx_spi_imx_data_entry_single(MX51, CSPI, "imx51-cspi", 2, , SZ_4K); const struct imx_spi_imx_data imx51_ecspi_data[] __initconst = { #define imx51_ecspi_data_entry(_id, _hwid) \ -- cgit v1.1 From f142b6196891660b329408e71573f97475823667 Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Thu, 3 Mar 2011 15:12:44 +0100 Subject: video i.MX: remove mx1 compile time dependencies MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit remove usage of CONFIG_ARCH_MX1. It's mostly unused anyway, replace it with cpu_is_mx1() where necessary. Also, depend on IMX_HAVE_PLATFORM_IMX_FB instead of the architectures directly. LAKML-Reference: 20110303141244.GQ29521@pengutronix.de Acked-by: Paul Mundt Signed-off-by: Uwe Kleine-König Signed-off-by: Sascha Hauer --- arch/arm/plat-mxc/devices/Kconfig | 1 - 1 file changed, 1 deletion(-) (limited to 'arch/arm/plat-mxc') diff --git a/arch/arm/plat-mxc/devices/Kconfig b/arch/arm/plat-mxc/devices/Kconfig index a860b16..bd294ad 100644 --- a/arch/arm/plat-mxc/devices/Kconfig +++ b/arch/arm/plat-mxc/devices/Kconfig @@ -24,7 +24,6 @@ config IMX_HAVE_PLATFORM_IMXDI_RTC config IMX_HAVE_PLATFORM_IMX_FB bool - select HAVE_FB_IMX config IMX_HAVE_PLATFORM_IMX_I2C bool -- cgit v1.1 From 13cf8df97d075cf61445c689a30c8b0ce70b415f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Thu, 7 Apr 2011 11:13:25 +0200 Subject: ARM: remove support for mxc91231 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Since support for mxc91231 was introduced 2009 it only saw patches that were part of (mxc or arm) global cleanups. The only supported machine only had 4 devices (2x UART, sdhc, watchdog). Cc: Dmitriy Taychenachev LAKML-Reference: 1302211482-17926-1-git-send-email-u.kleine-koenig@pengutronix.de Signed-off-by: Uwe Kleine-König Signed-off-by: Sascha Hauer --- arch/arm/plat-mxc/Kconfig | 8 - arch/arm/plat-mxc/include/mach/common.h | 7 - arch/arm/plat-mxc/include/mach/debug-macro.S | 7 - arch/arm/plat-mxc/include/mach/hardware.h | 13 -- arch/arm/plat-mxc/include/mach/iomux-mxc91231.h | 283 ------------------------ arch/arm/plat-mxc/include/mach/irqs.h | 2 - arch/arm/plat-mxc/include/mach/memory.h | 3 - arch/arm/plat-mxc/include/mach/mxc.h | 15 +- arch/arm/plat-mxc/include/mach/mxc91231.h | 256 --------------------- arch/arm/plat-mxc/include/mach/system.h | 6 - arch/arm/plat-mxc/include/mach/timex.h | 2 - arch/arm/plat-mxc/system.c | 6 - arch/arm/plat-mxc/time.c | 2 +- 13 files changed, 2 insertions(+), 608 deletions(-) delete mode 100644 arch/arm/plat-mxc/include/mach/iomux-mxc91231.h delete mode 100644 arch/arm/plat-mxc/include/mach/mxc91231.h (limited to 'arch/arm/plat-mxc') diff --git a/arch/arm/plat-mxc/Kconfig b/arch/arm/plat-mxc/Kconfig index b0cb425..debd7be 100644 --- a/arch/arm/plat-mxc/Kconfig +++ b/arch/arm/plat-mxc/Kconfig @@ -30,13 +30,6 @@ config ARCH_MX3 help This enables support for systems based on the Freescale i.MX3 family -config ARCH_MXC91231 - bool "MXC91231-based" - select CPU_V6 - select MXC_AVIC - help - This enables support for systems based on the Freescale MXC91231 family - config ARCH_MX5 bool "MX5-based" select CPU_V7 @@ -48,7 +41,6 @@ endchoice source "arch/arm/mach-imx/Kconfig" source "arch/arm/mach-mx3/Kconfig" -source "arch/arm/mach-mxc91231/Kconfig" source "arch/arm/mach-mx5/Kconfig" endmenu diff --git a/arch/arm/plat-mxc/include/mach/common.h b/arch/arm/plat-mxc/include/mach/common.h index bfa1ffc..da79918 100644 --- a/arch/arm/plat-mxc/include/mach/common.h +++ b/arch/arm/plat-mxc/include/mach/common.h @@ -23,7 +23,6 @@ extern void mx35_map_io(void); extern void mx50_map_io(void); extern void mx51_map_io(void); extern void mx53_map_io(void); -extern void mxc91231_map_io(void); extern void imx1_init_early(void); extern void imx21_init_early(void); extern void imx25_init_early(void); @@ -33,7 +32,6 @@ extern void imx35_init_early(void); extern void imx50_init_early(void); extern void imx51_init_early(void); extern void imx53_init_early(void); -extern void mxc91231_init_early(void); extern void mxc_init_irq(void __iomem *); extern void tzic_init_irq(void __iomem *); extern void mx1_init_irq(void); @@ -45,7 +43,6 @@ extern void mx35_init_irq(void); extern void mx50_init_irq(void); extern void mx51_init_irq(void); extern void mx53_init_irq(void); -extern void mxc91231_init_irq(void); extern void epit_timer_init(struct clk *timer_clk, void __iomem *base, int irq); extern void mxc_timer_init(struct clk *timer_clk, void __iomem *, int); extern int mx1_clocks_init(unsigned long fref); @@ -58,14 +55,10 @@ extern int mx51_clocks_init(unsigned long ckil, unsigned long osc, unsigned long ckih1, unsigned long ckih2); extern int mx53_clocks_init(unsigned long ckil, unsigned long osc, unsigned long ckih1, unsigned long ckih2); -extern int mxc91231_clocks_init(unsigned long fref); extern int mxc_register_gpios(void); extern int mxc_register_device(struct platform_device *pdev, void *data); extern void mxc_set_cpu_type(unsigned int type); extern void mxc_arch_reset_init(void __iomem *); -extern void mxc91231_power_off(void); -extern void mxc91231_arch_reset(int, const char *); -extern void mxc91231_prepare_idle(void); extern void mx51_efikamx_reset(void); extern int mx53_revision(void); extern int mx53_display_revision(void); diff --git a/arch/arm/plat-mxc/include/mach/debug-macro.S b/arch/arm/plat-mxc/include/mach/debug-macro.S index 3b3a37c..8e8d175 100644 --- a/arch/arm/plat-mxc/include/mach/debug-macro.S +++ b/arch/arm/plat-mxc/include/mach/debug-macro.S @@ -44,13 +44,6 @@ #define UART_PADDR MX51_UART1_BASE_ADDR #endif -#ifdef CONFIG_ARCH_MXC91231 -#ifdef UART_PADDR -#error "CONFIG_DEBUG_LL is incompatible with multiple archs" -#endif -#define UART_PADDR MXC91231_UART2_BASE_ADDR -#endif - #define UART_VADDR IMX_IO_ADDRESS(UART_PADDR) .macro addruart, rp, rv diff --git a/arch/arm/plat-mxc/include/mach/hardware.h b/arch/arm/plat-mxc/include/mach/hardware.h index 26bb1ba..a881db5 100644 --- a/arch/arm/plat-mxc/include/mach/hardware.h +++ b/arch/arm/plat-mxc/include/mach/hardware.h @@ -86,15 +86,6 @@ * SPBA0 0x70000000+0x100000 -> 0xf5400000+0x100000 * AIPS1 0x73f00000+0x100000 -> 0xf5700000+0x100000 * AIPS2 0x83f00000+0x100000 -> 0xf4300000+0x100000 - * mxc91231: - * L2CC 0x30000000+0x010000 -> 0xf4400000+0x010000 - * X_MEMC 0xb8000000+0x010000 -> 0xf4c00000+0x010000 - * ROMP 0x60000000+0x010000 -> 0xf5000000+0x010000 - * AVIC 0x68000000+0x010000 -> 0xf5800000+0x010000 - * AIPS1 0x43f00000+0x100000 -> 0xf5300000+0x100000 - * SPBA0 0x50000000+0x100000 -> 0xf5400000+0x100000 - * SPBA1 0x52000000+0x100000 -> 0xf5600000+0x100000 - * AIPS2 0x53f00000+0x100000 -> 0xf5700000+0x100000 */ #define IMX_IO_P2V(x) ( \ 0xf4000000 + \ @@ -134,10 +125,6 @@ # include #endif -#ifdef CONFIG_ARCH_MXC91231 -# include -#endif - #include #define imx_map_entry(soc, name, _type) { \ diff --git a/arch/arm/plat-mxc/include/mach/iomux-mxc91231.h b/arch/arm/plat-mxc/include/mach/iomux-mxc91231.h deleted file mode 100644 index bf28df0..0000000 --- a/arch/arm/plat-mxc/include/mach/iomux-mxc91231.h +++ /dev/null @@ -1,283 +0,0 @@ -/* - * Copyright 2004-2006 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright (C) 2008 by Sascha Hauer - * Copyright (C) 2009 by Dmitriy Taychenachev - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __MACH_IOMUX_MXC91231_H__ -#define __MACH_IOMUX_MXC91231_H__ - -/* - * various IOMUX output functions - */ - -#define IOMUX_OCONFIG_GPIO (0 << 4) /* used as GPIO */ -#define IOMUX_OCONFIG_FUNC (1 << 4) /* used as function */ -#define IOMUX_OCONFIG_ALT1 (2 << 4) /* used as alternate function 1 */ -#define IOMUX_OCONFIG_ALT2 (3 << 4) /* used as alternate function 2 */ -#define IOMUX_OCONFIG_ALT3 (4 << 4) /* used as alternate function 3 */ -#define IOMUX_OCONFIG_ALT4 (5 << 4) /* used as alternate function 4 */ -#define IOMUX_OCONFIG_ALT5 (6 << 4) /* used as alternate function 5 */ -#define IOMUX_OCONFIG_ALT6 (7 << 4) /* used as alternate function 6 */ -#define IOMUX_ICONFIG_NONE 0 /* not configured for input */ -#define IOMUX_ICONFIG_GPIO 1 /* used as GPIO */ -#define IOMUX_ICONFIG_FUNC 2 /* used as function */ -#define IOMUX_ICONFIG_ALT1 4 /* used as alternate function 1 */ -#define IOMUX_ICONFIG_ALT2 8 /* used as alternate function 2 */ - -#define IOMUX_CONFIG_GPIO (IOMUX_OCONFIG_GPIO | IOMUX_ICONFIG_GPIO) -#define IOMUX_CONFIG_FUNC (IOMUX_OCONFIG_FUNC | IOMUX_ICONFIG_FUNC) -#define IOMUX_CONFIG_ALT1 (IOMUX_OCONFIG_ALT1 | IOMUX_ICONFIG_ALT1) -#define IOMUX_CONFIG_ALT2 (IOMUX_OCONFIG_ALT2 | IOMUX_ICONFIG_ALT2) - -/* - * setups a single pin: - * - reserves the pin so that it is not claimed by another driver - * - setups the iomux according to the configuration - * - if the pin is configured as a GPIO, we claim it through kernel gpiolib - */ -int mxc_iomux_alloc_pin(unsigned int pin_mode, const char *label); -/* - * setups mutliple pins - * convenient way to call the above function with tables - */ -int mxc_iomux_setup_multiple_pins(const unsigned int *pin_list, unsigned count, - const char *label); - -/* - * releases a single pin: - * - make it available for a future use by another driver - * - frees the GPIO if the pin was configured as GPIO - * - DOES NOT reconfigure the IOMUX in its reset state - */ -void mxc_iomux_release_pin(unsigned int pin_mode); -/* - * releases multiple pins - * convenvient way to call the above function with tables - */ -void mxc_iomux_release_multiple_pins(const unsigned int *pin_list, int count); - -#define MUX_SIDE_AP (0) -#define MUX_SIDE_SP (1) - -#define MUX_SIDE_SHIFT (26) -#define MUX_SIDE_MASK (0x1 << MUX_SIDE_SHIFT) - -#define MUX_GPIO_PORT_SHIFT (23) -#define MUX_GPIO_PORT_MASK (0x7 << MUX_GPIO_PORT_SHIFT) - -#define MUX_GPIO_PIN_SHIFT (20) -#define MUX_GPIO_PIN_MASK (0x1f << MUX_GPIO_PIN_SHIFT) - -#define MUX_REG_SHIFT (15) -#define MUX_REG_MASK (0x1f << MUX_REG_SHIFT) - -#define MUX_FIELD_SHIFT (13) -#define MUX_FIELD_MASK (0x3 << MUX_FIELD_SHIFT) - -#define MUX_PADGRP_SHIFT (8) -#define MUX_PADGRP_MASK (0x1f << MUX_PADGRP_SHIFT) - -#define MUX_PIN_MASK (0xffffff << 8) - -#define GPIO_PORT_MAX (3) - -#define IOMUX_PIN(side, gport, gpin, ctlreg, ctlfield, padgrp) \ - (((side) << MUX_SIDE_SHIFT) | \ - (gport << MUX_GPIO_PORT_SHIFT) | \ - ((gpin) << MUX_GPIO_PIN_SHIFT) | \ - ((ctlreg) << MUX_REG_SHIFT) | \ - ((ctlfield) << MUX_FIELD_SHIFT) | \ - ((padgrp) << MUX_PADGRP_SHIFT)) - -#define MUX_MODE_OUT_SHIFT (4) -#define MUX_MODE_IN_SHIFT (0) -#define MUX_MODE_SHIFT (0) -#define MUX_MODE_MASK (0xff << MUX_MODE_SHIFT) - -#define IOMUX_MODE(pin, mode) \ - (pin | (mode << MUX_MODE_SHIFT)) - -enum iomux_pins { - /* AP Side pins */ - MXC91231_PIN_AP_CLE = IOMUX_PIN(0, 0, 0, 0, 0, 24), - MXC91231_PIN_AP_ALE = IOMUX_PIN(0, 0, 1, 0, 1, 24), - MXC91231_PIN_AP_CE_B = IOMUX_PIN(0, 0, 2, 0, 2, 24), - MXC91231_PIN_AP_RE_B = IOMUX_PIN(0, 0, 3, 0, 3, 24), - MXC91231_PIN_AP_WE_B = IOMUX_PIN(0, 0, 4, 1, 0, 24), - MXC91231_PIN_AP_WP_B = IOMUX_PIN(0, 0, 5, 1, 1, 24), - MXC91231_PIN_AP_BSY_B = IOMUX_PIN(0, 0, 6, 1, 2, 24), - MXC91231_PIN_AP_U1_TXD = IOMUX_PIN(0, 0, 7, 1, 3, 28), - MXC91231_PIN_AP_U1_RXD = IOMUX_PIN(0, 0, 8, 2, 0, 28), - MXC91231_PIN_AP_U1_RTS_B = IOMUX_PIN(0, 0, 9, 2, 1, 28), - MXC91231_PIN_AP_U1_CTS_B = IOMUX_PIN(0, 0, 10, 2, 2, 28), - MXC91231_PIN_AP_AD1_TXD = IOMUX_PIN(0, 0, 11, 2, 3, 9), - MXC91231_PIN_AP_AD1_RXD = IOMUX_PIN(0, 0, 12, 3, 0, 9), - MXC91231_PIN_AP_AD1_TXC = IOMUX_PIN(0, 0, 13, 3, 1, 9), - MXC91231_PIN_AP_AD1_TXFS = IOMUX_PIN(0, 0, 14, 3, 2, 9), - MXC91231_PIN_AP_AD2_TXD = IOMUX_PIN(0, 0, 15, 3, 3, 9), - MXC91231_PIN_AP_AD2_RXD = IOMUX_PIN(0, 0, 16, 4, 0, 9), - MXC91231_PIN_AP_AD2_TXC = IOMUX_PIN(0, 0, 17, 4, 1, 9), - MXC91231_PIN_AP_AD2_TXFS = IOMUX_PIN(0, 0, 18, 4, 2, 9), - MXC91231_PIN_AP_OWDAT = IOMUX_PIN(0, 0, 19, 4, 3, 28), - MXC91231_PIN_AP_IPU_LD17 = IOMUX_PIN(0, 0, 20, 5, 0, 28), - MXC91231_PIN_AP_IPU_D3_VSYNC = IOMUX_PIN(0, 0, 21, 5, 1, 28), - MXC91231_PIN_AP_IPU_D3_HSYNC = IOMUX_PIN(0, 0, 22, 5, 2, 28), - MXC91231_PIN_AP_IPU_D3_CLK = IOMUX_PIN(0, 0, 23, 5, 3, 28), - MXC91231_PIN_AP_IPU_D3_DRDY = IOMUX_PIN(0, 0, 24, 6, 0, 28), - MXC91231_PIN_AP_IPU_D3_CONTR = IOMUX_PIN(0, 0, 25, 6, 1, 28), - MXC91231_PIN_AP_IPU_D0_CS = IOMUX_PIN(0, 0, 26, 6, 2, 28), - MXC91231_PIN_AP_IPU_LD16 = IOMUX_PIN(0, 0, 27, 6, 3, 28), - MXC91231_PIN_AP_IPU_D2_CS = IOMUX_PIN(0, 0, 28, 7, 0, 28), - MXC91231_PIN_AP_IPU_PAR_RS = IOMUX_PIN(0, 0, 29, 7, 1, 28), - MXC91231_PIN_AP_IPU_D3_PS = IOMUX_PIN(0, 0, 30, 7, 2, 28), - MXC91231_PIN_AP_IPU_D3_CLS = IOMUX_PIN(0, 0, 31, 7, 3, 28), - MXC91231_PIN_AP_IPU_RD = IOMUX_PIN(0, 1, 0, 8, 0, 28), - MXC91231_PIN_AP_IPU_WR = IOMUX_PIN(0, 1, 1, 8, 1, 28), - MXC91231_PIN_AP_IPU_LD0 = IOMUX_PIN(0, 7, 0, 8, 2, 28), - MXC91231_PIN_AP_IPU_LD1 = IOMUX_PIN(0, 7, 0, 8, 3, 28), - MXC91231_PIN_AP_IPU_LD2 = IOMUX_PIN(0, 7, 0, 9, 0, 28), - MXC91231_PIN_AP_IPU_LD3 = IOMUX_PIN(0, 1, 2, 9, 1, 28), - MXC91231_PIN_AP_IPU_LD4 = IOMUX_PIN(0, 1, 3, 9, 2, 28), - MXC91231_PIN_AP_IPU_LD5 = IOMUX_PIN(0, 1, 4, 9, 3, 28), - MXC91231_PIN_AP_IPU_LD6 = IOMUX_PIN(0, 1, 5, 10, 0, 28), - MXC91231_PIN_AP_IPU_LD7 = IOMUX_PIN(0, 1, 6, 10, 1, 28), - MXC91231_PIN_AP_IPU_LD8 = IOMUX_PIN(0, 1, 7, 10, 2, 28), - MXC91231_PIN_AP_IPU_LD9 = IOMUX_PIN(0, 1, 8, 10, 3, 28), - MXC91231_PIN_AP_IPU_LD10 = IOMUX_PIN(0, 1, 9, 11, 0, 28), - MXC91231_PIN_AP_IPU_LD11 = IOMUX_PIN(0, 1, 10, 11, 1, 28), - MXC91231_PIN_AP_IPU_LD12 = IOMUX_PIN(0, 1, 11, 11, 2, 28), - MXC91231_PIN_AP_IPU_LD13 = IOMUX_PIN(0, 1, 12, 11, 3, 28), - MXC91231_PIN_AP_IPU_LD14 = IOMUX_PIN(0, 1, 13, 12, 0, 28), - MXC91231_PIN_AP_IPU_LD15 = IOMUX_PIN(0, 1, 14, 12, 1, 28), - MXC91231_PIN_AP_KPROW4 = IOMUX_PIN(0, 7, 0, 12, 2, 10), - MXC91231_PIN_AP_KPROW5 = IOMUX_PIN(0, 1, 16, 12, 3, 10), - MXC91231_PIN_AP_GPIO_AP_B17 = IOMUX_PIN(0, 1, 17, 13, 0, 10), - MXC91231_PIN_AP_GPIO_AP_B18 = IOMUX_PIN(0, 1, 18, 13, 1, 10), - MXC91231_PIN_AP_KPCOL3 = IOMUX_PIN(0, 1, 19, 13, 2, 11), - MXC91231_PIN_AP_KPCOL4 = IOMUX_PIN(0, 1, 20, 13, 3, 11), - MXC91231_PIN_AP_KPCOL5 = IOMUX_PIN(0, 1, 21, 14, 0, 11), - MXC91231_PIN_AP_GPIO_AP_B22 = IOMUX_PIN(0, 1, 22, 14, 1, 11), - MXC91231_PIN_AP_GPIO_AP_B23 = IOMUX_PIN(0, 1, 23, 14, 2, 11), - MXC91231_PIN_AP_CSI_D0 = IOMUX_PIN(0, 1, 24, 14, 3, 21), - MXC91231_PIN_AP_CSI_D1 = IOMUX_PIN(0, 1, 25, 15, 0, 21), - MXC91231_PIN_AP_CSI_D2 = IOMUX_PIN(0, 1, 26, 15, 1, 21), - MXC91231_PIN_AP_CSI_D3 = IOMUX_PIN(0, 1, 27, 15, 2, 21), - MXC91231_PIN_AP_CSI_D4 = IOMUX_PIN(0, 1, 28, 15, 3, 21), - MXC91231_PIN_AP_CSI_D5 = IOMUX_PIN(0, 1, 29, 16, 0, 21), - MXC91231_PIN_AP_CSI_D6 = IOMUX_PIN(0, 1, 30, 16, 1, 21), - MXC91231_PIN_AP_CSI_D7 = IOMUX_PIN(0, 1, 31, 16, 2, 21), - MXC91231_PIN_AP_CSI_D8 = IOMUX_PIN(0, 2, 0, 16, 3, 21), - MXC91231_PIN_AP_CSI_D9 = IOMUX_PIN(0, 2, 1, 17, 0, 21), - MXC91231_PIN_AP_CSI_MCLK = IOMUX_PIN(0, 2, 2, 17, 1, 21), - MXC91231_PIN_AP_CSI_VSYNC = IOMUX_PIN(0, 2, 3, 17, 2, 21), - MXC91231_PIN_AP_CSI_HSYNC = IOMUX_PIN(0, 2, 4, 17, 3, 21), - MXC91231_PIN_AP_CSI_PIXCLK = IOMUX_PIN(0, 2, 5, 18, 0, 21), - MXC91231_PIN_AP_I2CLK = IOMUX_PIN(0, 2, 6, 18, 1, 12), - MXC91231_PIN_AP_I2DAT = IOMUX_PIN(0, 2, 7, 18, 2, 12), - MXC91231_PIN_AP_GPIO_AP_C8 = IOMUX_PIN(0, 2, 8, 18, 3, 9), - MXC91231_PIN_AP_GPIO_AP_C9 = IOMUX_PIN(0, 2, 9, 19, 0, 9), - MXC91231_PIN_AP_GPIO_AP_C10 = IOMUX_PIN(0, 2, 10, 19, 1, 9), - MXC91231_PIN_AP_GPIO_AP_C11 = IOMUX_PIN(0, 2, 11, 19, 2, 9), - MXC91231_PIN_AP_GPIO_AP_C12 = IOMUX_PIN(0, 2, 12, 19, 3, 9), - MXC91231_PIN_AP_GPIO_AP_C13 = IOMUX_PIN(0, 2, 13, 20, 0, 28), - MXC91231_PIN_AP_GPIO_AP_C14 = IOMUX_PIN(0, 2, 14, 20, 1, 28), - MXC91231_PIN_AP_GPIO_AP_C15 = IOMUX_PIN(0, 2, 15, 20, 2, 9), - MXC91231_PIN_AP_GPIO_AP_C16 = IOMUX_PIN(0, 2, 16, 20, 3, 9), - MXC91231_PIN_AP_GPIO_AP_C17 = IOMUX_PIN(0, 2, 17, 21, 0, 9), - MXC91231_PIN_AP_ED_INT0 = IOMUX_PIN(0, 2, 18, 21, 1, 22), - MXC91231_PIN_AP_ED_INT1 = IOMUX_PIN(0, 2, 19, 21, 2, 22), - MXC91231_PIN_AP_ED_INT2 = IOMUX_PIN(0, 2, 20, 21, 3, 22), - MXC91231_PIN_AP_ED_INT3 = IOMUX_PIN(0, 2, 21, 22, 0, 22), - MXC91231_PIN_AP_ED_INT4 = IOMUX_PIN(0, 2, 22, 22, 1, 23), - MXC91231_PIN_AP_ED_INT5 = IOMUX_PIN(0, 2, 23, 22, 2, 23), - MXC91231_PIN_AP_ED_INT6 = IOMUX_PIN(0, 2, 24, 22, 3, 23), - MXC91231_PIN_AP_ED_INT7 = IOMUX_PIN(0, 2, 25, 23, 0, 23), - MXC91231_PIN_AP_U2_DSR_B = IOMUX_PIN(0, 2, 26, 23, 1, 28), - MXC91231_PIN_AP_U2_RI_B = IOMUX_PIN(0, 2, 27, 23, 2, 28), - MXC91231_PIN_AP_U2_CTS_B = IOMUX_PIN(0, 2, 28, 23, 3, 28), - MXC91231_PIN_AP_U2_DTR_B = IOMUX_PIN(0, 2, 29, 24, 0, 28), - MXC91231_PIN_AP_KPROW0 = IOMUX_PIN(0, 7, 0, 24, 1, 10), - MXC91231_PIN_AP_KPROW1 = IOMUX_PIN(0, 1, 15, 24, 2, 10), - MXC91231_PIN_AP_KPROW2 = IOMUX_PIN(0, 7, 0, 24, 3, 10), - MXC91231_PIN_AP_KPROW3 = IOMUX_PIN(0, 7, 0, 25, 0, 10), - MXC91231_PIN_AP_KPCOL0 = IOMUX_PIN(0, 7, 0, 25, 1, 11), - MXC91231_PIN_AP_KPCOL1 = IOMUX_PIN(0, 7, 0, 25, 2, 11), - MXC91231_PIN_AP_KPCOL2 = IOMUX_PIN(0, 7, 0, 25, 3, 11), - - /* Shared pins */ - MXC91231_PIN_SP_U3_TXD = IOMUX_PIN(1, 3, 0, 0, 0, 28), - MXC91231_PIN_SP_U3_RXD = IOMUX_PIN(1, 3, 1, 0, 1, 28), - MXC91231_PIN_SP_U3_RTS_B = IOMUX_PIN(1, 3, 2, 0, 2, 28), - MXC91231_PIN_SP_U3_CTS_B = IOMUX_PIN(1, 3, 3, 0, 3, 28), - MXC91231_PIN_SP_USB_TXOE_B = IOMUX_PIN(1, 3, 4, 1, 0, 28), - MXC91231_PIN_SP_USB_DAT_VP = IOMUX_PIN(1, 3, 5, 1, 1, 28), - MXC91231_PIN_SP_USB_SE0_VM = IOMUX_PIN(1, 3, 6, 1, 2, 28), - MXC91231_PIN_SP_USB_RXD = IOMUX_PIN(1, 3, 7, 1, 3, 28), - MXC91231_PIN_SP_UH2_TXOE_B = IOMUX_PIN(1, 3, 8, 2, 0, 28), - MXC91231_PIN_SP_UH2_SPEED = IOMUX_PIN(1, 3, 9, 2, 1, 28), - MXC91231_PIN_SP_UH2_SUSPEN = IOMUX_PIN(1, 3, 10, 2, 2, 28), - MXC91231_PIN_SP_UH2_TXDP = IOMUX_PIN(1, 3, 11, 2, 3, 28), - MXC91231_PIN_SP_UH2_RXDP = IOMUX_PIN(1, 3, 12, 3, 0, 28), - MXC91231_PIN_SP_UH2_RXDM = IOMUX_PIN(1, 3, 13, 3, 1, 28), - MXC91231_PIN_SP_UH2_OVR = IOMUX_PIN(1, 3, 14, 3, 2, 28), - MXC91231_PIN_SP_UH2_PWR = IOMUX_PIN(1, 3, 15, 3, 3, 28), - MXC91231_PIN_SP_SD1_DAT0 = IOMUX_PIN(1, 3, 16, 4, 0, 25), - MXC91231_PIN_SP_SD1_DAT1 = IOMUX_PIN(1, 3, 17, 4, 1, 25), - MXC91231_PIN_SP_SD1_DAT2 = IOMUX_PIN(1, 3, 18, 4, 2, 25), - MXC91231_PIN_SP_SD1_DAT3 = IOMUX_PIN(1, 3, 19, 4, 3, 25), - MXC91231_PIN_SP_SD1_CMD = IOMUX_PIN(1, 3, 20, 5, 0, 25), - MXC91231_PIN_SP_SD1_CLK = IOMUX_PIN(1, 3, 21, 5, 1, 25), - MXC91231_PIN_SP_SD2_DAT0 = IOMUX_PIN(1, 3, 22, 5, 2, 26), - MXC91231_PIN_SP_SD2_DAT1 = IOMUX_PIN(1, 3, 23, 5, 3, 26), - MXC91231_PIN_SP_SD2_DAT2 = IOMUX_PIN(1, 3, 24, 6, 0, 26), - MXC91231_PIN_SP_SD2_DAT3 = IOMUX_PIN(1, 3, 25, 6, 1, 26), - MXC91231_PIN_SP_GPIO_SP_A26 = IOMUX_PIN(1, 3, 26, 6, 2, 28), - MXC91231_PIN_SP_SPI1_CLK = IOMUX_PIN(1, 3, 27, 6, 3, 13), - MXC91231_PIN_SP_SPI1_MOSI = IOMUX_PIN(1, 3, 28, 7, 0, 13), - MXC91231_PIN_SP_SPI1_MISO = IOMUX_PIN(1, 3, 29, 7, 1, 13), - MXC91231_PIN_SP_SPI1_SS0 = IOMUX_PIN(1, 3, 30, 7, 2, 13), - MXC91231_PIN_SP_SPI1_SS1 = IOMUX_PIN(1, 3, 31, 7, 3, 13), - MXC91231_PIN_SP_SD2_CMD = IOMUX_PIN(1, 7, 0, 8, 0, 26), - MXC91231_PIN_SP_SD2_CLK = IOMUX_PIN(1, 7, 0, 8, 1, 26), - MXC91231_PIN_SP_SIM1_RST_B = IOMUX_PIN(1, 2, 30, 8, 2, 28), - MXC91231_PIN_SP_SIM1_SVEN = IOMUX_PIN(1, 7, 0, 8, 3, 28), - MXC91231_PIN_SP_SIM1_CLK = IOMUX_PIN(1, 7, 0, 9, 0, 28), - MXC91231_PIN_SP_SIM1_TRXD = IOMUX_PIN(1, 7, 0, 9, 1, 28), - MXC91231_PIN_SP_SIM1_PD = IOMUX_PIN(1, 2, 31, 9, 2, 28), - MXC91231_PIN_SP_UH2_TXDM = IOMUX_PIN(1, 7, 0, 9, 3, 28), - MXC91231_PIN_SP_UH2_RXD = IOMUX_PIN(1, 7, 0, 10, 0, 28), -}; - -#define PIN_AP_MAX (104) -#define PIN_SP_MAX (41) - -#define PIN_MAX (PIN_AP_MAX + PIN_SP_MAX) - -/* - * Convenience values for use with mxc_iomux_mode() - * - * Format here is MXC91231_PIN_(pin name)__(function) - */ - -#define MXC91231_PIN_SP_USB_DAT_VP__USB_DAT_VP \ - IOMUX_MODE(MXC91231_PIN_SP_USB_DAT_VP, IOMUX_CONFIG_FUNC) -#define MXC91231_PIN_SP_USB_SE0_VM__USB_SE0_VM \ - IOMUX_MODE(MXC91231_PIN_SP_USB_SE0_VM, IOMUX_CONFIG_FUNC) -#define MXC91231_PIN_SP_USB_DAT_VP__RXD2 \ - IOMUX_MODE(MXC91231_PIN_SP_USB_DAT_VP, IOMUX_CONFIG_ALT1) -#define MXC91231_PIN_SP_USB_SE0_VM__TXD2 \ - IOMUX_MODE(MXC91231_PIN_SP_USB_SE0_VM, IOMUX_CONFIG_ALT1) - - -#endif /* __MACH_IOMUX_MXC91231_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/irqs.h b/arch/arm/plat-mxc/include/mach/irqs.h index a3d930d3..35c89bc 100644 --- a/arch/arm/plat-mxc/include/mach/irqs.h +++ b/arch/arm/plat-mxc/include/mach/irqs.h @@ -35,8 +35,6 @@ #define MXC_GPIO_IRQS (32 * 4) #elif defined CONFIG_SOC_IMX51 #define MXC_GPIO_IRQS (32 * 4) -#elif defined CONFIG_ARCH_MXC91231 -#define MXC_GPIO_IRQS (32 * 4) #elif defined CONFIG_ARCH_MX3 #define MXC_GPIO_IRQS (32 * 3) #endif diff --git a/arch/arm/plat-mxc/include/mach/memory.h b/arch/arm/plat-mxc/include/mach/memory.h index 5d51cbb..11be5cd 100644 --- a/arch/arm/plat-mxc/include/mach/memory.h +++ b/arch/arm/plat-mxc/include/mach/memory.h @@ -19,7 +19,6 @@ #define MX50_PHYS_OFFSET UL(0x70000000) #define MX51_PHYS_OFFSET UL(0x90000000) #define MX53_PHYS_OFFSET UL(0x70000000) -#define MXC91231_PHYS_OFFSET UL(0x90000000) #if !defined(CONFIG_RUNTIME_PHYS_OFFSET) # if defined CONFIG_ARCH_MX1 @@ -32,8 +31,6 @@ # define PLAT_PHYS_OFFSET MX27_PHYS_OFFSET # elif defined CONFIG_ARCH_MX3 # define PLAT_PHYS_OFFSET MX3x_PHYS_OFFSET -# elif defined CONFIG_ARCH_MXC91231 -# define PLAT_PHYS_OFFSET MXC91231_PHYS_OFFSET # elif defined CONFIG_ARCH_MX50 # define PLAT_PHYS_OFFSET MX50_PHYS_OFFSET # elif defined CONFIG_ARCH_MX51 diff --git a/arch/arm/plat-mxc/include/mach/mxc.h b/arch/arm/plat-mxc/include/mach/mxc.h index 1aea818..0aba8b1 100644 --- a/arch/arm/plat-mxc/include/mach/mxc.h +++ b/arch/arm/plat-mxc/include/mach/mxc.h @@ -35,7 +35,6 @@ #define MXC_CPU_MX50 50 #define MXC_CPU_MX51 51 #define MXC_CPU_MX53 53 -#define MXC_CPU_MXC91231 91231 #define IMX_CHIP_REVISION_1_0 0x10 #define IMX_CHIP_REVISION_1_1 0x11 @@ -177,18 +176,6 @@ extern unsigned int __mxc_cpu_type; # define cpu_is_mx53() (0) #endif -#ifdef CONFIG_ARCH_MXC91231 -# ifdef mxc_cpu_type -# undef mxc_cpu_type -# define mxc_cpu_type __mxc_cpu_type -# else -# define mxc_cpu_type MXC_CPU_MXC91231 -# endif -# define cpu_is_mxc91231() (mxc_cpu_type == MXC_CPU_MXC91231) -#else -# define cpu_is_mxc91231() (0) -#endif - #ifndef __ASSEMBLY__ struct cpu_op { @@ -214,7 +201,7 @@ extern struct cpu_op *(*get_cpu_op)(int *op); #define CSCR_A(n) (IO_ADDRESS(WEIM_BASE_ADDR + n * 0x10 + 0x8)) #endif -#define cpu_is_mx3() (cpu_is_mx31() || cpu_is_mx35() || cpu_is_mxc91231()) +#define cpu_is_mx3() (cpu_is_mx31() || cpu_is_mx35()) #define cpu_is_mx2() (cpu_is_mx21() || cpu_is_mx27()) #endif /* __ASM_ARCH_MXC_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/mxc91231.h b/arch/arm/plat-mxc/include/mach/mxc91231.h deleted file mode 100644 index 765190f..0000000 --- a/arch/arm/plat-mxc/include/mach/mxc91231.h +++ /dev/null @@ -1,256 +0,0 @@ -/* - * Copyright 2004-2006 Freescale Semiconductor, Inc. All Rights Reserved. - * - Platform specific register memory map - * - * Copyright 2005-2007 Motorola, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ -#ifndef __MACH_MXC91231_H__ -#define __MACH_MXC91231_H__ - -/* - * L2CC - */ -#define MXC91231_L2CC_BASE_ADDR 0x30000000 -#define MXC91231_L2CC_SIZE SZ_64K - -/* - * AIPS 1 - */ -#define MXC91231_AIPS1_BASE_ADDR 0x43F00000 -#define MXC91231_AIPS1_SIZE SZ_1M - -#define MXC91231_AIPS1_CTRL_BASE_ADDR MXC91231_AIPS1_BASE_ADDR -#define MXC91231_MAX_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0x04000) -#define MXC91231_EVTMON_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0x08000) -#define MXC91231_CLKCTL_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0x0C000) -#define MXC91231_ETB_SLOT4_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0x10000) -#define MXC91231_ETB_SLOT5_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0x14000) -#define MXC91231_ECT_CTIO_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0x18000) -#define MXC91231_I2C_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0x80000) -#define MXC91231_MU_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0x88000) -#define MXC91231_UART1_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0x90000) -#define MXC91231_UART2_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0x94000) -#define MXC91231_DSM_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0x98000) -#define MXC91231_OWIRE_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0x9C000) -#define MXC91231_SSI1_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0xA0000) -#define MXC91231_KPP_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0xA8000) -#define MXC91231_IOMUX_AP_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0xAC000) -#define MXC91231_CTI_AP_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0xB8000) - -/* - * AIPS 2 - */ -#define MXC91231_AIPS2_BASE_ADDR 0x53F00000 -#define MXC91231_AIPS2_SIZE SZ_1M - -#define MXC91231_GEMK_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0x8C000) -#define MXC91231_GPT1_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0x90000) -#define MXC91231_EPIT1_AP_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0x94000) -#define MXC91231_SCC_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0xAC000) -#define MXC91231_RNGA_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0xB0000) -#define MXC91231_IPU_CTRL_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0xC0000) -#define MXC91231_AUDMUX_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0xC4000) -#define MXC91231_EDIO_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0xC8000) -#define MXC91231_GPIO1_AP_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0xCC000) -#define MXC91231_GPIO2_AP_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0xD0000) -#define MXC91231_SDMA_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0xD4000) -#define MXC91231_RTC_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0xD8000) -#define MXC91231_WDOG1_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0xDC000) -#define MXC91231_PWM_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0xE0000) -#define MXC91231_GPIO3_AP_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0xE4000) -#define MXC91231_WDOG2_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0xE8000) -#define MXC91231_RTIC_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0xEC000) -#define MXC91231_LPMC_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0xF0000) - -/* - * SPBA global module 0 - */ -#define MXC91231_SPBA0_BASE_ADDR 0x50000000 -#define MXC91231_SPBA0_SIZE SZ_1M - -#define MXC91231_MMC_SDHC1_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x04000) -#define MXC91231_MMC_SDHC2_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x08000) -#define MXC91231_UART3_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x0C000) -#define MXC91231_CSPI2_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x10000) -#define MXC91231_SSI2_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x14000) -#define MXC91231_SIM_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x18000) -#define MXC91231_IIM_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x1C000) -#define MXC91231_CTI_SDMA_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x20000) -#define MXC91231_USBOTG_CTRL_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x24000) -#define MXC91231_USBOTG_DATA_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x28000) -#define MXC91231_CSPI1_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x30000) -#define MXC91231_SPBA_CTRL_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x3C000) -#define MXC91231_IOMUX_COM_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x40000) -#define MXC91231_CRM_COM_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x44000) -#define MXC91231_CRM_AP_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x48000) -#define MXC91231_PLL0_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x4C000) -#define MXC91231_PLL1_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x50000) -#define MXC91231_PLL2_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x54000) -#define MXC91231_GPIO4_SH_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x58000) -#define MXC91231_HAC_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x5C000) -#define MXC91231_SAHARA_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x5C000) -#define MXC91231_PLL3_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x60000) - -/* - * SPBA global module 1 - */ -#define MXC91231_SPBA1_BASE_ADDR 0x52000000 -#define MXC91231_SPBA1_SIZE SZ_1M - -#define MXC91231_MQSPI_BASE_ADDR (MXC91231_SPBA1_BASE_ADDR + 0x34000) -#define MXC91231_EL1T_BASE_ADDR (MXC91231_SPBA1_BASE_ADDR + 0x38000) - -/*! - * Defines for SPBA modules - */ -#define MXC91231_SPBA_SDHC1 0x04 -#define MXC91231_SPBA_SDHC2 0x08 -#define MXC91231_SPBA_UART3 0x0C -#define MXC91231_SPBA_CSPI2 0x10 -#define MXC91231_SPBA_SSI2 0x14 -#define MXC91231_SPBA_SIM 0x18 -#define MXC91231_SPBA_IIM 0x1C -#define MXC91231_SPBA_CTI_SDMA 0x20 -#define MXC91231_SPBA_USBOTG_CTRL_REGS 0x24 -#define MXC91231_SPBA_USBOTG_DATA_REGS 0x28 -#define MXC91231_SPBA_CSPI1 0x30 -#define MXC91231_SPBA_MQSPI 0x34 -#define MXC91231_SPBA_EL1T 0x38 -#define MXC91231_SPBA_IOMUX 0x40 -#define MXC91231_SPBA_CRM_COM 0x44 -#define MXC91231_SPBA_CRM_AP 0x48 -#define MXC91231_SPBA_PLL0 0x4C -#define MXC91231_SPBA_PLL1 0x50 -#define MXC91231_SPBA_PLL2 0x54 -#define MXC91231_SPBA_GPIO4 0x58 -#define MXC91231_SPBA_SAHARA 0x5C - -/* - * ROMP and AVIC - */ -#define MXC91231_ROMP_BASE_ADDR 0x60000000 -#define MXC91231_ROMP_SIZE SZ_64K - -#define MXC91231_AVIC_BASE_ADDR 0x68000000 -#define MXC91231_AVIC_SIZE SZ_64K - -/* - * NAND, SDRAM, WEIM, M3IF, EMI controllers - */ -#define MXC91231_X_MEMC_BASE_ADDR 0xB8000000 -#define MXC91231_X_MEMC_SIZE SZ_64K - -#define MXC91231_NFC_BASE_ADDR (MXC91231_X_MEMC_BASE_ADDR + 0x0000) -#define MXC91231_ESDCTL_BASE_ADDR (MXC91231_X_MEMC_BASE_ADDR + 0x1000) -#define MXC91231_WEIM_BASE_ADDR (MXC91231_X_MEMC_BASE_ADDR + 0x2000) -#define MXC91231_M3IF_BASE_ADDR (MXC91231_X_MEMC_BASE_ADDR + 0x3000) -#define MXC91231_EMI_CTL_BASE_ADDR (MXC91231_X_MEMC_BASE_ADDR + 0x4000) - -/* - * Memory regions and CS - * CPLD is connected on CS4 - * CS5 is TP1021 or it is not connected - * */ -#define MXC91231_FB_RAM_BASE_ADDR 0x78000000 -#define MXC91231_FB_RAM_SIZE SZ_256K -#define MXC91231_CSD0_BASE_ADDR 0x80000000 -#define MXC91231_CSD1_BASE_ADDR 0x90000000 -#define MXC91231_CS0_BASE_ADDR 0xA0000000 -#define MXC91231_CS1_BASE_ADDR 0xA8000000 -#define MXC91231_CS2_BASE_ADDR 0xB0000000 -#define MXC91231_CS3_BASE_ADDR 0xB2000000 -#define MXC91231_CS4_BASE_ADDR 0xB4000000 -#define MXC91231_CS5_BASE_ADDR 0xB6000000 - -/* - * This macro defines the physical to virtual address mapping for all the - * peripheral modules. It is used by passing in the physical address as x - * and returning the virtual address. - */ -#define MXC91231_IO_P2V(x) IMX_IO_P2V(x) -#define MXC91231_IO_ADDRESS(x) IOMEM(MXC91231_IO_P2V(x)) - -/* - * Interrupt numbers - */ -#define MXC91231_INT_GPIO3 0 -#define MXC91231_INT_EL1T_CI 1 -#define MXC91231_INT_EL1T_RFCI 2 -#define MXC91231_INT_EL1T_RFI 3 -#define MXC91231_INT_EL1T_MCU 4 -#define MXC91231_INT_EL1T_IPI 5 -#define MXC91231_INT_MU_GEN 6 -#define MXC91231_INT_GPIO4 7 -#define MXC91231_INT_MMC_SDHC2 8 -#define MXC91231_INT_MMC_SDHC1 9 -#define MXC91231_INT_I2C 10 -#define MXC91231_INT_SSI2 11 -#define MXC91231_INT_SSI1 12 -#define MXC91231_INT_CSPI2 13 -#define MXC91231_INT_CSPI1 14 -#define MXC91231_INT_RTIC 15 -#define MXC91231_INT_SAHARA 15 -#define MXC91231_INT_HAC 15 -#define MXC91231_INT_UART3_RX 16 -#define MXC91231_INT_UART3_TX 17 -#define MXC91231_INT_UART3_MINT 18 -#define MXC91231_INT_ECT 19 -#define MXC91231_INT_SIM_IPB 20 -#define MXC91231_INT_SIM_DATA 21 -#define MXC91231_INT_RNGA 22 -#define MXC91231_INT_DSM_AP 23 -#define MXC91231_INT_KPP 24 -#define MXC91231_INT_RTC 25 -#define MXC91231_INT_PWM 26 -#define MXC91231_INT_GEMK_AP 27 -#define MXC91231_INT_EPIT 28 -#define MXC91231_INT_GPT 29 -#define MXC91231_INT_UART2_RX 30 -#define MXC91231_INT_UART2_TX 31 -#define MXC91231_INT_UART2_MINT 32 -#define MXC91231_INT_NANDFC 33 -#define MXC91231_INT_SDMA 34 -#define MXC91231_INT_USB_WAKEUP 35 -#define MXC91231_INT_USB_SOF 36 -#define MXC91231_INT_PMU_EVTMON 37 -#define MXC91231_INT_USB_FUNC 38 -#define MXC91231_INT_USB_DMA 39 -#define MXC91231_INT_USB_CTRL 40 -#define MXC91231_INT_IPU_ERR 41 -#define MXC91231_INT_IPU_SYN 42 -#define MXC91231_INT_UART1_RX 43 -#define MXC91231_INT_UART1_TX 44 -#define MXC91231_INT_UART1_MINT 45 -#define MXC91231_INT_IIM 46 -#define MXC91231_INT_MU_RX_OR 47 -#define MXC91231_INT_MU_TX_OR 48 -#define MXC91231_INT_SCC_SCM 49 -#define MXC91231_INT_SCC_SMN 50 -#define MXC91231_INT_GPIO2 51 -#define MXC91231_INT_GPIO1 52 -#define MXC91231_INT_MQSPI1 53 -#define MXC91231_INT_MQSPI2 54 -#define MXC91231_INT_WDOG2 55 -#define MXC91231_INT_EXT_INT7 56 -#define MXC91231_INT_EXT_INT6 57 -#define MXC91231_INT_EXT_INT5 58 -#define MXC91231_INT_EXT_INT4 59 -#define MXC91231_INT_EXT_INT3 60 -#define MXC91231_INT_EXT_INT2 61 -#define MXC91231_INT_EXT_INT1 62 -#define MXC91231_INT_EXT_INT0 63 - -#define MXC91231_MAX_INT_LINES 63 -#define MXC91231_MAX_EXT_LINES 8 - -#endif /* __MACH_MXC91231_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/system.h b/arch/arm/plat-mxc/include/mach/system.h index 0417da9..51f02a9 100644 --- a/arch/arm/plat-mxc/include/mach/system.h +++ b/arch/arm/plat-mxc/include/mach/system.h @@ -24,12 +24,6 @@ extern void mx5_cpu_lp_set(enum mxc_cpu_pwr_mode mode); static inline void arch_idle(void) { -#ifdef CONFIG_ARCH_MXC91231 - if (cpu_is_mxc91231()) { - /* Need this to set DSM low-power mode */ - mxc91231_prepare_idle(); - } -#endif /* fix i.MX31 errata TLSbo65953 and i.MX35 errata ENGcm09472 */ if (cpu_is_mx31() || cpu_is_mx35()) { unsigned long reg = 0; diff --git a/arch/arm/plat-mxc/include/mach/timex.h b/arch/arm/plat-mxc/include/mach/timex.h index 2d96246..d61d5c7 100644 --- a/arch/arm/plat-mxc/include/mach/timex.h +++ b/arch/arm/plat-mxc/include/mach/timex.h @@ -26,8 +26,6 @@ #define CLOCK_TICK_RATE 16000000 #elif defined CONFIG_ARCH_MX5 #define CLOCK_TICK_RATE 8000000 -#elif defined CONFIG_ARCH_MXC91231 -#define CLOCK_TICK_RATE 13000000 #endif #endif /* __ASM_ARCH_MXC_TIMEX_H__ */ diff --git a/arch/arm/plat-mxc/system.c b/arch/arm/plat-mxc/system.c index 3455fc0..8024f2a 100644 --- a/arch/arm/plat-mxc/system.c +++ b/arch/arm/plat-mxc/system.c @@ -37,12 +37,6 @@ void arch_reset(char mode, const char *cmd) { unsigned int wcr_enable; -#ifdef CONFIG_ARCH_MXC91231 - if (cpu_is_mxc91231()) { - mxc91231_arch_reset(mode, cmd); - return; - } -#endif #ifdef CONFIG_MACH_MX51_EFIKAMX if (machine_is_mx51_efikamx()) { mx51_efikamx_reset(); diff --git a/arch/arm/plat-mxc/time.c b/arch/arm/plat-mxc/time.c index 2237ff8..40f32e7 100644 --- a/arch/arm/plat-mxc/time.c +++ b/arch/arm/plat-mxc/time.c @@ -54,7 +54,7 @@ #define MX2_TSTAT_CAPT (1 << 1) #define MX2_TSTAT_COMP (1 << 0) -/* MX31, MX35, MX25, MXC91231, MX5 */ +/* MX31, MX35, MX25, MX5 */ #define V2_TCTL_WAITEN (1 << 3) /* Wait enable mode */ #define V2_TCTL_CLK_IPG (1 << 6) #define V2_TCTL_FRR (1 << 9) -- cgit v1.1 From 91350f6677f988b2342b214338520d1c3ed1ea0e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Tue, 22 Mar 2011 11:54:35 +0100 Subject: ARM: mxc: don't use the symbols in the CPU family choice to select others MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The symbols in this choice should only be used to select between the available machines that can be built into a single kernel. As these sets (will) differ e.g. depending on ARM_PATCH_PHYS_VIRT and AUTO_ZRELADDR letting them select other symbols makes the logic more complex and needs to duplicate some things. So let the machines select the corresponding symbols (indirectly via SOC_XYZ). LAKML-Reference: 1302464943-20721-2-git-send-email-u.kleine-koenig@pengutronix.de Signed-off-by: Uwe Kleine-König Signed-off-by: Sascha Hauer --- arch/arm/plat-mxc/Kconfig | 4 ---- 1 file changed, 4 deletions(-) (limited to 'arch/arm/plat-mxc') diff --git a/arch/arm/plat-mxc/Kconfig b/arch/arm/plat-mxc/Kconfig index debd7be..8b7ab8c 100644 --- a/arch/arm/plat-mxc/Kconfig +++ b/arch/arm/plat-mxc/Kconfig @@ -10,7 +10,6 @@ choice config ARCH_MX1 bool "MX1-based" - select SOC_IMX1 help This enables support for systems based on the Freescale i.MX1 family @@ -26,14 +25,11 @@ config ARCH_MX25 config ARCH_MX3 bool "MX3-based" - select CPU_V6 help This enables support for systems based on the Freescale i.MX3 family config ARCH_MX5 bool "MX5-based" - select CPU_V7 - select ARM_L1_CACHE_SHIFT_6 help This enables support for systems based on the Freescale i.MX51 family -- cgit v1.1 From 7db4d88206e20b8d91e8e7bba3b79805a1b1a98d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Fri, 8 Apr 2011 11:06:43 +0200 Subject: ARM: mxc: don't allow to compile together i.MX51 and i.MX53 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The two SoCs have different PHYS_OFFSETs so it's not (yet) possible to compile a single (working) kernel for these. LAKML-Reference: 1302464943-20721-4-git-send-email-u.kleine-koenig@pengutronix.de Signed-off-by: Uwe Kleine-König Signed-off-by: Sascha Hauer --- arch/arm/plat-mxc/Kconfig | 19 +++++++++++++++++-- 1 file changed, 17 insertions(+), 2 deletions(-) (limited to 'arch/arm/plat-mxc') diff --git a/arch/arm/plat-mxc/Kconfig b/arch/arm/plat-mxc/Kconfig index 8b7ab8c..d9b9aad 100644 --- a/arch/arm/plat-mxc/Kconfig +++ b/arch/arm/plat-mxc/Kconfig @@ -4,6 +4,12 @@ source "arch/arm/plat-mxc/devices/Kconfig" menu "Freescale MXC Implementations" +config ARCH_MX50_SUPPORTED + bool + +config ARCH_MX53_SUPPORTED + bool + choice prompt "Freescale CPU family:" default ARCH_MX3 @@ -28,8 +34,17 @@ config ARCH_MX3 help This enables support for systems based on the Freescale i.MX3 family -config ARCH_MX5 - bool "MX5-based" +config ARCH_MX503 + bool "i.MX50 + i.MX53" + select ARCH_MX50_SUPPORTED + select ARCH_MX53_SUPPORTED + help + This enables support for machines using Freescale's i.MX50 and i.MX51 + processors. + +config ARCH_MX51 + bool "i.MX51" + select ARCH_MX51_SUPPORTED help This enables support for systems based on the Freescale i.MX51 family -- cgit v1.1 From d286a43aa248cb657e0876b5aa4fe0034170d05c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Sat, 2 Apr 2011 00:15:49 +0200 Subject: ARM: mx3: make ioremap quirk ready for multi-SoC kernels MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit To be able to compile e.g. i.MX31 and i.MX51 in a single kernel image the ioremap quirk needs a runtime check. While touching this code make the comment more understandable by adding a sentence from the commit log that introduced it (eadefef ([ARM] MX3: Use ioremap wrapper to map SoC devices nonshared)). As mach/io.h now uses cpu_is_ some header reshuffling in mach/hardware.h was necessary. (mach/mx27.h and mach/mx31.h #include which #includes . So mach/mxc.h which provides the cpu_is_ macros needs to be included before mach/mx27.h and mach/mx31.h.) LAKML-Reference: 1302464943-20721-5-git-send-email-u.kleine-koenig@pengutronix.de Signed-off-by: Uwe Kleine-König Signed-off-by: Sascha Hauer --- arch/arm/plat-mxc/include/mach/hardware.h | 4 ++-- arch/arm/plat-mxc/include/mach/io.h | 23 +++++++++++++++-------- 2 files changed, 17 insertions(+), 10 deletions(-) (limited to 'arch/arm/plat-mxc') diff --git a/arch/arm/plat-mxc/include/mach/hardware.h b/arch/arm/plat-mxc/include/mach/hardware.h index a881db5..67d3e2b 100644 --- a/arch/arm/plat-mxc/include/mach/hardware.h +++ b/arch/arm/plat-mxc/include/mach/hardware.h @@ -95,6 +95,8 @@ #define IMX_IO_ADDRESS(x) IOMEM(IMX_IO_P2V(x)) +#include + #ifdef CONFIG_ARCH_MX5 #include #include @@ -125,8 +127,6 @@ # include #endif -#include - #define imx_map_entry(soc, name, _type) { \ .virtual = soc ## _IO_P2V(soc ## _ ## name ## _BASE_ADDR), \ .pfn = __phys_to_pfn(soc ## _ ## name ## _BASE_ADDR), \ diff --git a/arch/arm/plat-mxc/include/mach/io.h b/arch/arm/plat-mxc/include/mach/io.h index b4f2de7..4347a87 100644 --- a/arch/arm/plat-mxc/include/mach/io.h +++ b/arch/arm/plat-mxc/include/mach/io.h @@ -14,19 +14,26 @@ /* Allow IO space to be anywhere in the memory */ #define IO_SPACE_LIMIT 0xffffffff -#ifdef CONFIG_ARCH_MX3 -#define __arch_ioremap __mx3_ioremap +#if defined(CONFIG_SOC_IMX31) || defined(CONFIG_SOC_IMX35) +#include + +#define __arch_ioremap __imx_ioremap #define __arch_iounmap __iounmap +#define addr_in_module(addr, mod) \ + ((unsigned long)(addr) - mod ## _BASE_ADDR < mod ## _SIZE) + static inline void __iomem * -__mx3_ioremap(unsigned long phys_addr, size_t size, unsigned int mtype) +__imx_ioremap(unsigned long phys_addr, size_t size, unsigned int mtype) { - if (mtype == MT_DEVICE) { - /* Access all peripherals below 0x80000000 as nonshared device - * but leave l2cc alone. + if (mtype == MT_DEVICE && (cpu_is_mx31() || cpu_is_mx35())) { + /* + * Access all peripherals below 0x80000000 as nonshared device + * on mx3, but leave l2cc alone. Otherwise cache corruptions + * can occur. */ - if ((phys_addr < 0x80000000) && ((phys_addr < 0x30000000) || - (phys_addr >= 0x30000000 + SZ_1M))) + if (phys_addr < 0x80000000 && + !addr_in_module(phys_addr, MX3x_L2CC)) mtype = MT_DEVICE_NONSHARED; } -- cgit v1.1 From 7f5e6b089de8a588f649d77f661ff41f2c7679ae Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Sat, 2 Apr 2011 00:16:21 +0200 Subject: ARM: imx: remove some deprecated and unused #defines MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit LAKML-Reference: 1302464943-20721-6-git-send-email-u.kleine-koenig@pengutronix.de Signed-off-by: Uwe Kleine-König Signed-off-by: Sascha Hauer --- arch/arm/plat-mxc/include/mach/mxc.h | 7 ------- 1 file changed, 7 deletions(-) (limited to 'arch/arm/plat-mxc') diff --git a/arch/arm/plat-mxc/include/mach/mxc.h b/arch/arm/plat-mxc/include/mach/mxc.h index 0aba8b1..4ac53ce 100644 --- a/arch/arm/plat-mxc/include/mach/mxc.h +++ b/arch/arm/plat-mxc/include/mach/mxc.h @@ -194,13 +194,6 @@ enum mxc_cpu_pwr_mode { extern struct cpu_op *(*get_cpu_op)(int *op); #endif -#if defined(CONFIG_ARCH_MX3) || defined(CONFIG_ARCH_MX2) -/* These are deprecated, use mx[23][157]_setup_weimcs instead. */ -#define CSCR_U(n) (IO_ADDRESS(WEIM_BASE_ADDR + n * 0x10)) -#define CSCR_L(n) (IO_ADDRESS(WEIM_BASE_ADDR + n * 0x10 + 0x4)) -#define CSCR_A(n) (IO_ADDRESS(WEIM_BASE_ADDR + n * 0x10 + 0x8)) -#endif - #define cpu_is_mx3() (cpu_is_mx31() || cpu_is_mx35()) #define cpu_is_mx2() (cpu_is_mx21() || cpu_is_mx27()) -- cgit v1.1 From 27ad4bf72a27c80c121b2349174e6b41b2e3afd8 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Thu, 17 Mar 2011 09:40:29 +0100 Subject: ARM: imx: move mx3 support to mach-imx MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Fixing a few "please, no space before tabs" and "empty line at end of file" warnings on the way. LAKML-Reference: 1299271882-2130-6-git-send-email-u.kleine-koenig@pengutronix.de Signed-off-by: Uwe Kleine-König Signed-off-by: Sascha Hauer --- arch/arm/plat-mxc/Kconfig | 1 - 1 file changed, 1 deletion(-) (limited to 'arch/arm/plat-mxc') diff --git a/arch/arm/plat-mxc/Kconfig b/arch/arm/plat-mxc/Kconfig index d9b9aad..a5353fc 100644 --- a/arch/arm/plat-mxc/Kconfig +++ b/arch/arm/plat-mxc/Kconfig @@ -51,7 +51,6 @@ config ARCH_MX51 endchoice source "arch/arm/mach-imx/Kconfig" -source "arch/arm/mach-mx3/Kconfig" source "arch/arm/mach-mx5/Kconfig" endmenu -- cgit v1.1