From f5d7a13b18706c3328c6aac3bf782a13cabf255a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Mon, 25 Oct 2010 11:40:30 +0200 Subject: ARM: imx: refactor the io mapping macro MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This makes it more assembler friendly and allows it to be used in situation that need an unsigned long and not a pointer. Also the naming is clearer. IOMEM is introduced without IMX_ prefix as it is used this way in more than one ARM subarch and it might become globally available soon. Signed-off-by: Uwe Kleine-König --- arch/arm/plat-mxc/include/mach/hardware.h | 13 +++++++++---- arch/arm/plat-mxc/include/mach/mx1.h | 5 +++-- arch/arm/plat-mxc/include/mach/mx21.h | 9 +++++---- arch/arm/plat-mxc/include/mach/mx25.h | 9 +++++---- arch/arm/plat-mxc/include/mach/mx27.h | 9 +++++---- arch/arm/plat-mxc/include/mach/mx31.h | 13 +++++++------ arch/arm/plat-mxc/include/mach/mx35.h | 13 +++++++------ arch/arm/plat-mxc/include/mach/mx51.h | 13 +++++++------ arch/arm/plat-mxc/include/mach/mxc91231.h | 19 ++++++++++--------- 9 files changed, 58 insertions(+), 45 deletions(-) (limited to 'arch/arm/plat-mxc') diff --git a/arch/arm/plat-mxc/include/mach/hardware.h b/arch/arm/plat-mxc/include/mach/hardware.h index ebadf4a..4bbe506 100644 --- a/arch/arm/plat-mxc/include/mach/hardware.h +++ b/arch/arm/plat-mxc/include/mach/hardware.h @@ -22,10 +22,15 @@ #include -#define IMX_IO_ADDRESS(addr, module) \ - ((void __force __iomem *) \ - (((unsigned long)((addr) - (module ## _BASE_ADDR)) < module ## _SIZE) ?\ - (addr) - (module ## _BASE_ADDR) + (module ## _BASE_ADDR_VIRT) : 0)) +#ifdef __ASSEMBLER__ +#define IOMEM(addr) (addr) +#else +#define IOMEM(addr) ((void __force __iomem *)(addr)) +#endif + +#define IMX_IO_P2V_MODULE(addr, module) \ + (((addr) - module ## _BASE_ADDR) < module ## _SIZE ? \ + (addr) - (module ## _BASE_ADDR) + (module ## _BASE_ADDR_VIRT) : 0) #ifdef CONFIG_ARCH_MX5 #include diff --git a/arch/arm/plat-mxc/include/mach/mx1.h b/arch/arm/plat-mxc/include/mach/mx1.h index 641b246..b41c288 100644 --- a/arch/arm/plat-mxc/include/mach/mx1.h +++ b/arch/arm/plat-mxc/include/mach/mx1.h @@ -73,8 +73,9 @@ #define MX1_CSI_BASE_ADDR (0x24000 + MX1_IO_BASE_ADDR) /* macro to get at IO space when running virtually */ -#define MX1_IO_ADDRESS(x) ( \ - IMX_IO_ADDRESS(x, MX1_IO)) +#define MX1_IO_P2V(x) ( \ + IMX_IO_P2V_MODULE(x, MX1_IO)) +#define MX1_IO_ADDRESS(x) IOMEM(MX1_IO_P2V(x)) /* fixed interrput numbers */ #define MX1_INT_SOFTINT 0 diff --git a/arch/arm/plat-mxc/include/mach/mx21.h b/arch/arm/plat-mxc/include/mach/mx21.h index 8bc5972..aed0277 100644 --- a/arch/arm/plat-mxc/include/mach/mx21.h +++ b/arch/arm/plat-mxc/include/mach/mx21.h @@ -92,10 +92,11 @@ #define MX21_IRAM_BASE_ADDR 0xffffe800 /* internal ram */ -#define MX21_IO_ADDRESS(x) ( \ - IMX_IO_ADDRESS(x, MX21_AIPI) ?: \ - IMX_IO_ADDRESS(x, MX21_SAHB1) ?: \ - IMX_IO_ADDRESS(x, MX21_X_MEMC)) +#define MX21_IO_P2V(x) ( \ + IMX_IO_P2V_MODULE(x, MX21_AIPI) ?: \ + IMX_IO_P2V_MODULE(x, MX21_SAHB1) ?: \ + IMX_IO_P2V_MODULE(x, MX21_X_MEMC)) +#define MX21_IO_ADDRESS(x) IOMEM(MX21_IO_P2V(x)) /* fixed interrupt numbers */ #define MX21_INT_CSPI3 6 diff --git a/arch/arm/plat-mxc/include/mach/mx25.h b/arch/arm/plat-mxc/include/mach/mx25.h index cf46a45..6f9e1d4 100644 --- a/arch/arm/plat-mxc/include/mach/mx25.h +++ b/arch/arm/plat-mxc/include/mach/mx25.h @@ -28,10 +28,11 @@ #define MX25_GPIO3_BASE_ADDR_VIRT (MX25_AIPS2_BASE_ADDR_VIRT + 0xa4000) #define MX25_GPIO4_BASE_ADDR_VIRT (MX25_AIPS2_BASE_ADDR_VIRT + 0x9c000) -#define MX25_IO_ADDRESS(x) ( \ - IMX_IO_ADDRESS(x, MX25_AIPS1) ?: \ - IMX_IO_ADDRESS(x, MX25_AIPS2) ?: \ - IMX_IO_ADDRESS(x, MX25_AVIC)) +#define MX25_IO_P2V(x) ( \ + IMX_IO_P2V_MODULE(x, MX25_AIPS1) ?: \ + IMX_IO_P2V_MODULE(x, MX25_AIPS2) ?: \ + IMX_IO_P2V_MODULE(x, MX25_AVIC)) +#define MX25_IO_ADDRESS(x) IOMEM(MX25_IO_P2V(x)) #define MX25_AIPS1_IO_ADDRESS(x) \ (((x) - MX25_AIPS1_BASE_ADDR) + MX25_AIPS1_BASE_ADDR_VIRT) diff --git a/arch/arm/plat-mxc/include/mach/mx27.h b/arch/arm/plat-mxc/include/mach/mx27.h index 2237ba2..c769cc8 100644 --- a/arch/arm/plat-mxc/include/mach/mx27.h +++ b/arch/arm/plat-mxc/include/mach/mx27.h @@ -123,10 +123,11 @@ /* IRAM */ #define MX27_IRAM_BASE_ADDR 0xffff4c00 /* internal ram */ -#define MX27_IO_ADDRESS(x) ( \ - IMX_IO_ADDRESS(x, MX27_AIPI) ?: \ - IMX_IO_ADDRESS(x, MX27_SAHB1) ?: \ - IMX_IO_ADDRESS(x, MX27_X_MEMC)) +#define MX27_IO_P2V(x) ( \ + IMX_IO_P2V_MODULE(x, MX27_AIPI) ?: \ + IMX_IO_P2V_MODULE(x, MX27_SAHB1) ?: \ + IMX_IO_P2V_MODULE(x, MX27_X_MEMC)) +#define MX27_IO_ADDRESS(x) IOMEM(MX27_IO_P2V(x)) #ifndef __ASSEMBLER__ static inline void mx27_setup_weimcs(size_t cs, diff --git a/arch/arm/plat-mxc/include/mach/mx31.h b/arch/arm/plat-mxc/include/mach/mx31.h index 61cfe82..eb4a28d 100644 --- a/arch/arm/plat-mxc/include/mach/mx31.h +++ b/arch/arm/plat-mxc/include/mach/mx31.h @@ -121,12 +121,13 @@ #define MX31_PCMCIA_MEM_BASE_ADDR 0xbc000000 -#define MX31_IO_ADDRESS(x) ( \ - IMX_IO_ADDRESS(x, MX31_AIPS1) ?: \ - IMX_IO_ADDRESS(x, MX31_AIPS2) ?: \ - IMX_IO_ADDRESS(x, MX31_AVIC) ?: \ - IMX_IO_ADDRESS(x, MX31_X_MEMC) ?: \ - IMX_IO_ADDRESS(x, MX31_SPBA0)) +#define MX31_IO_P2V(x) ( \ + IMX_IO_P2V_MODULE(x, MX31_AIPS1) ?: \ + IMX_IO_P2V_MODULE(x, MX31_AIPS2) ?: \ + IMX_IO_P2V_MODULE(x, MX31_AVIC) ?: \ + IMX_IO_P2V_MODULE(x, MX31_X_MEMC) ?: \ + IMX_IO_P2V_MODULE(x, MX31_SPBA0)) +#define MX31_IO_ADDRESS(x) IOMEM(MX31_IO_P2V(x)) #ifndef __ASSEMBLER__ static inline void mx31_setup_weimcs(size_t cs, diff --git a/arch/arm/plat-mxc/include/mach/mx35.h b/arch/arm/plat-mxc/include/mach/mx35.h index 6267cff..ce1a24b 100644 --- a/arch/arm/plat-mxc/include/mach/mx35.h +++ b/arch/arm/plat-mxc/include/mach/mx35.h @@ -114,12 +114,13 @@ #define MX35_NFC_BASE_ADDR 0xbb000000 #define MX35_PCMCIA_MEM_BASE_ADDR 0xbc000000 -#define MX35_IO_ADDRESS(x) ( \ - IMX_IO_ADDRESS(x, MX35_AIPS1) ?: \ - IMX_IO_ADDRESS(x, MX35_AIPS2) ?: \ - IMX_IO_ADDRESS(x, MX35_AVIC) ?: \ - IMX_IO_ADDRESS(x, MX35_X_MEMC) ?: \ - IMX_IO_ADDRESS(x, MX35_SPBA0)) +#define MX35_IO_P2V(x) ( \ + IMX_IO_P2V_MODULE(x, MX35_AIPS1) ?: \ + IMX_IO_P2V_MODULE(x, MX35_AIPS2) ?: \ + IMX_IO_P2V_MODULE(x, MX35_AVIC) ?: \ + IMX_IO_P2V_MODULE(x, MX35_X_MEMC) ?: \ + IMX_IO_P2V_MODULE(x, MX35_SPBA0)) +#define MX35_IO_ADDRESS(x) IOMEM(MX35_IO_P2V(x)) /* * Interrupt numbers diff --git a/arch/arm/plat-mxc/include/mach/mx51.h b/arch/arm/plat-mxc/include/mach/mx51.h index 2af7a10..e93cf5b 100644 --- a/arch/arm/plat-mxc/include/mach/mx51.h +++ b/arch/arm/plat-mxc/include/mach/mx51.h @@ -163,12 +163,13 @@ #define MX51_GPU2D_BASE_ADDR 0xd0000000 #define MX51_TZIC_BASE_ADDR 0xe0000000 -#define MX51_IO_ADDRESS(x) ( \ - IMX_IO_ADDRESS(x, MX51_IRAM) ?: \ - IMX_IO_ADDRESS(x, MX51_DEBUG) ?: \ - IMX_IO_ADDRESS(x, MX51_SPBA0) ?: \ - IMX_IO_ADDRESS(x, MX51_AIPS1) ?: \ - IMX_IO_ADDRESS(x, MX51_AIPS2)) +#define MX51_IO_P2V(x) ( \ + IMX_IO_P2V_MODULE(x, MX51_IRAM) ?: \ + IMX_IO_P2V_MODULE(x, MX51_DEBUG) ?: \ + IMX_IO_P2V_MODULE(x, MX51_SPBA0) ?: \ + IMX_IO_P2V_MODULE(x, MX51_AIPS1) ?: \ + IMX_IO_P2V_MODULE(x, MX51_AIPS2)) +#define MX51_IO_ADDRESS(x) IOMEM(MX51_IO_P2V(x)) /* This is currently used in , but should go away */ #define MX51_AIPS1_IO_ADDRESS(x) \ diff --git a/arch/arm/plat-mxc/include/mach/mxc91231.h b/arch/arm/plat-mxc/include/mach/mxc91231.h index 0ca3101..49e5e25 100644 --- a/arch/arm/plat-mxc/include/mach/mxc91231.h +++ b/arch/arm/plat-mxc/include/mach/mxc91231.h @@ -187,15 +187,16 @@ * it returns 0. */ -#define MXC91231_IO_ADDRESS(x) ( \ - IMX_IO_ADDRESS(x, MXC91231_L2CC) ?: \ - IMX_IO_ADDRESS(x, MXC91231_X_MEMC) ?: \ - IMX_IO_ADDRESS(x, MXC91231_ROMP) ?: \ - IMX_IO_ADDRESS(x, MXC91231_AVIC) ?: \ - IMX_IO_ADDRESS(x, MXC91231_AIPS1) ?: \ - IMX_IO_ADDRESS(x, MXC91231_SPBA0) ?: \ - IMX_IO_ADDRESS(x, MXC91231_SPBA1) ?: \ - IMX_IO_ADDRESS(x, MXC91231_AIPS2)) +#define MXC91231_IO_P2V(x) ( \ + IMX_IO_P2V_MODULE(x, MXC91231_L2CC) ?: \ + IMX_IO_P2V_MODULE(x, MXC91231_X_MEMC) ?: \ + IMX_IO_P2V_MODULE(x, MXC91231_ROMP) ?: \ + IMX_IO_P2V_MODULE(x, MXC91231_AVIC) ?: \ + IMX_IO_P2V_MODULE(x, MXC91231_AIPS1) ?: \ + IMX_IO_P2V_MODULE(x, MXC91231_SPBA0) ?: \ + IMX_IO_P2V_MODULE(x, MXC91231_SPBA1) ?: \ + IMX_IO_P2V_MODULE(x, MXC91231_AIPS2)) +#define MXC91231_IO_ADDRESS(x) IOMEM(MXC91231_IO_P2V(x)) /* * Interrupt numbers -- cgit v1.1 From 08ff97b5214143c3bd47add6ec49097cb848120a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Mon, 25 Oct 2010 15:38:09 +0200 Subject: ARM: imx: use MXxy_IO_P2V macros to setup static mappings MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This makes less code rely on the virtual constants. To further simplify code and reduce the needed boilerplate when defining the static mappings a new helper macro is defined in mach/hardware.h. Signed-off-by: Uwe Kleine-König --- arch/arm/plat-mxc/include/mach/hardware.h | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'arch/arm/plat-mxc') diff --git a/arch/arm/plat-mxc/include/mach/hardware.h b/arch/arm/plat-mxc/include/mach/hardware.h index 4bbe506..409cec6 100644 --- a/arch/arm/plat-mxc/include/mach/hardware.h +++ b/arch/arm/plat-mxc/include/mach/hardware.h @@ -66,4 +66,11 @@ #include +#define imx_map_entry(soc, name, _type) { \ + .virtual = soc ## _IO_P2V(soc ## _ ## name ## _BASE_ADDR), \ + .pfn = __phys_to_pfn(soc ## _ ## name ## _BASE_ADDR), \ + .length = soc ## _ ## name ## _SIZE, \ + .type = _type, \ +} + #endif /* __ASM_ARCH_MXC_HARDWARE_H__ */ -- cgit v1.1 From cf3a6aba2f8402d4e45f7f263a0e69f779cd1bdc Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Mon, 25 Oct 2010 15:54:58 +0200 Subject: ARM: imx: remove last explicit users of virtual base address defines MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This allows changing the mapping without the need to adapt all users. While at it remove some unneeded casts to void __iomem *, this is already taken care for in the IO_ADDRESS macros Signed-off-by: Uwe Kleine-König --- arch/arm/plat-mxc/include/mach/mx25.h | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) (limited to 'arch/arm/plat-mxc') diff --git a/arch/arm/plat-mxc/include/mach/mx25.h b/arch/arm/plat-mxc/include/mach/mx25.h index 6f9e1d4..08b5a3a 100644 --- a/arch/arm/plat-mxc/include/mach/mx25.h +++ b/arch/arm/plat-mxc/include/mach/mx25.h @@ -21,13 +21,12 @@ #define MX25_CRM_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0x80000) #define MX25_GPT1_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0x90000) +#define MX25_GPIO4_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0x9c000) +#define MX25_GPIO3_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xa4000) +#define MX25_GPIO1_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xcc000) +#define MX25_GPIO2_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xd0000) #define MX25_WDOG_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xdc000) -#define MX25_GPIO1_BASE_ADDR_VIRT (MX25_AIPS2_BASE_ADDR_VIRT + 0xcc000) -#define MX25_GPIO2_BASE_ADDR_VIRT (MX25_AIPS2_BASE_ADDR_VIRT + 0xd0000) -#define MX25_GPIO3_BASE_ADDR_VIRT (MX25_AIPS2_BASE_ADDR_VIRT + 0xa4000) -#define MX25_GPIO4_BASE_ADDR_VIRT (MX25_AIPS2_BASE_ADDR_VIRT + 0x9c000) - #define MX25_IO_P2V(x) ( \ IMX_IO_P2V_MODULE(x, MX25_AIPS1) ?: \ IMX_IO_P2V_MODULE(x, MX25_AIPS2) ?: \ -- cgit v1.1 From a99631489bbd1b4647b82d0822b6a3942e2dd731 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Mon, 25 Oct 2010 15:44:25 +0200 Subject: ARM: imx: change static io mapping to use a function MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Now only the virtual addresses [0xf4000000, 0xf5ffffff] are used for static per-SoC mappings. The few mappings of whole chip selects are moved accordingly. The now wrong defines for virtual base addresses are removed. Signed-off-by: Uwe Kleine-König --- arch/arm/plat-mxc/include/mach/hardware.h | 67 +++++++++++++++++++++++++++++++ arch/arm/plat-mxc/include/mach/mx1.h | 5 +-- arch/arm/plat-mxc/include/mach/mx21.h | 9 +---- arch/arm/plat-mxc/include/mach/mx25.h | 13 ++---- arch/arm/plat-mxc/include/mach/mx27.h | 9 +---- arch/arm/plat-mxc/include/mach/mx2x.h | 36 +---------------- arch/arm/plat-mxc/include/mach/mx31.h | 16 ++------ arch/arm/plat-mxc/include/mach/mx35.h | 17 ++------ arch/arm/plat-mxc/include/mach/mx3x.h | 65 ++---------------------------- arch/arm/plat-mxc/include/mach/mx51.h | 38 +----------------- arch/arm/plat-mxc/include/mach/mxc91231.h | 22 +--------- 11 files changed, 89 insertions(+), 208 deletions(-) (limited to 'arch/arm/plat-mxc') diff --git a/arch/arm/plat-mxc/include/mach/hardware.h b/arch/arm/plat-mxc/include/mach/hardware.h index 409cec6..dde777c 100644 --- a/arch/arm/plat-mxc/include/mach/hardware.h +++ b/arch/arm/plat-mxc/include/mach/hardware.h @@ -32,6 +32,73 @@ (((addr) - module ## _BASE_ADDR) < module ## _SIZE ? \ (addr) - (module ## _BASE_ADDR) + (module ## _BASE_ADDR_VIRT) : 0) +/* + * This is rather complicated for humans and ugly to verify, but for a machine + * it's OK. Still more as it is usually only applied to constants. The upsides + * on using this approach are: + * + * - same mapping on all i.MX machines + * - works for assembler, too + * - no need to nurture #defines for virtual addresses + * + * The downside it, it's hard to verify (but I have a script for that). + * + * Obviously this needs to be injective for each SoC. In general it maps the + * whole address space to [0xf4000000, 0xf5ffffff]. So [0xf6000000,0xfeffffff] + * is free for per-machine use (e.g. KZM_ARM11_01 uses 64MiB there). + * + * It applies the following mappings for the different SoCs: + * + * mx1: + * IO 0x00200000+0x100000 -> 0xf4000000+0x100000 + * mx21: + * AIPI 0x10000000+0x100000 -> 0xf4400000+0x100000 + * SAHB1 0x80000000+0x100000 -> 0xf4000000+0x100000 + * X_MEMC 0xdf000000+0x004000 -> 0xf5f00000+0x004000 + * mx25: + * AIPS1 0x43f00000+0x100000 -> 0xf5300000+0x100000 + * AIPS2 0x53f00000+0x100000 -> 0xf5700000+0x100000 + * AVIC 0x68000000+0x100000 -> 0xf5800000+0x100000 + * mx27: + * AIPI 0x10000000+0x100000 -> 0xf4400000+0x100000 + * SAHB1 0x80000000+0x100000 -> 0xf4000000+0x100000 + * X_MEMC 0xd8000000+0x100000 -> 0xf5c00000+0x100000 + * mx31: + * AIPS1 0x43f00000+0x100000 -> 0xf5300000+0x100000 + * AIPS2 0x53f00000+0x100000 -> 0xf5700000+0x100000 + * AVIC 0x68000000+0x100000 -> 0xf5800000+0x100000 + * X_MEMC 0xb8000000+0x010000 -> 0xf4c00000+0x010000 + * SPBA0 0x50000000+0x100000 -> 0xf5400000+0x100000 + * mx35: + * AIPS1 0x43f00000+0x100000 -> 0xf5300000+0x100000 + * AIPS2 0x53f00000+0x100000 -> 0xf5700000+0x100000 + * AVIC 0x68000000+0x100000 -> 0xf5800000+0x100000 + * X_MEMC 0xb8000000+0x010000 -> 0xf4c00000+0x010000 + * SPBA0 0x50000000+0x100000 -> 0xf5400000+0x100000 + * mx51: + * IRAM 0x1ffe0000+0x020000 -> 0xf4fe0000+0x020000 + * DEBUG 0x60000000+0x100000 -> 0xf5000000+0x100000 + * SPBA0 0x70000000+0x100000 -> 0xf5400000+0x100000 + * AIPS1 0x73f00000+0x100000 -> 0xf5700000+0x100000 + * AIPS2 0x83f00000+0x100000 -> 0xf4300000+0x100000 + * mxc91231: + * L2CC 0x30000000+0x010000 -> 0xf4400000+0x010000 + * X_MEMC 0xb8000000+0x010000 -> 0xf4c00000+0x010000 + * ROMP 0x60000000+0x010000 -> 0xf5000000+0x010000 + * AVIC 0x68000000+0x010000 -> 0xf5800000+0x010000 + * AIPS1 0x43f00000+0x100000 -> 0xf5300000+0x100000 + * SPBA0 0x50000000+0x100000 -> 0xf5400000+0x100000 + * SPBA1 0x52000000+0x100000 -> 0xf5600000+0x100000 + * AIPS2 0x53f00000+0x100000 -> 0xf5700000+0x100000 + */ +#define IMX_IO_P2V(x) ( \ + 0xf4000000 + \ + (((x) & 0x50000000) >> 6) + \ + (((x) & 0x0b000000) >> 4) + \ + (((x) & 0x000fffff))) + +#define IMX_IO_ADDRESS(x) IOMEM(IMX_IO_P2V(x)) + #ifdef CONFIG_ARCH_MX5 #include #endif diff --git a/arch/arm/plat-mxc/include/mach/mx1.h b/arch/arm/plat-mxc/include/mach/mx1.h index b41c288..b786ae7 100644 --- a/arch/arm/plat-mxc/include/mach/mx1.h +++ b/arch/arm/plat-mxc/include/mach/mx1.h @@ -19,7 +19,6 @@ */ #define MX1_IO_BASE_ADDR 0x00200000 #define MX1_IO_SIZE SZ_1M -#define MX1_IO_BASE_ADDR_VIRT VMALLOC_END #define MX1_CS0_PHYS 0x10000000 #define MX1_CS0_SIZE 0x02000000 @@ -73,8 +72,7 @@ #define MX1_CSI_BASE_ADDR (0x24000 + MX1_IO_BASE_ADDR) /* macro to get at IO space when running virtually */ -#define MX1_IO_P2V(x) ( \ - IMX_IO_P2V_MODULE(x, MX1_IO)) +#define MX1_IO_P2V(x) IMX_IO_P2V(x) #define MX1_IO_ADDRESS(x) IOMEM(MX1_IO_P2V(x)) /* fixed interrput numbers */ @@ -171,7 +169,6 @@ /* these should go away */ #define IMX_IO_PHYS MX1_IO_BASE_ADDR #define IMX_IO_SIZE MX1_IO_SIZE -#define IMX_IO_BASE MX1_IO_BASE_ADDR_VIRT #define IMX_CS0_PHYS MX1_CS0_PHYS #define IMX_CS0_SIZE MX1_CS0_SIZE #define IMX_CS1_PHYS MX1_CS1_PHYS diff --git a/arch/arm/plat-mxc/include/mach/mx21.h b/arch/arm/plat-mxc/include/mach/mx21.h index aed0277..b417e32 100644 --- a/arch/arm/plat-mxc/include/mach/mx21.h +++ b/arch/arm/plat-mxc/include/mach/mx21.h @@ -26,7 +26,6 @@ #define __MACH_MX21_H__ #define MX21_AIPI_BASE_ADDR 0x10000000 -#define MX21_AIPI_BASE_ADDR_VIRT 0xf4000000 #define MX21_AIPI_SIZE SZ_1M #define MX21_DMA_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x01000) #define MX21_WDOG_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x02000) @@ -64,7 +63,6 @@ #define MX21_AVIC_BASE_ADDR 0x10040000 #define MX21_SAHB1_BASE_ADDR 0x80000000 -#define MX21_SAHB1_BASE_ADDR_VIRT 0xf4100000 #define MX21_SAHB1_SIZE SZ_1M #define MX21_CSI_BASE_ADDR (MX2x_SAHB1_BASE_ADDR + 0x0000) @@ -82,7 +80,6 @@ /* NAND, SDRAM, WEIM etc controllers */ #define MX21_X_MEMC_BASE_ADDR 0xdf000000 -#define MX21_X_MEMC_BASE_ADDR_VIRT 0xf4200000 #define MX21_X_MEMC_SIZE SZ_256K #define MX21_SDRAMC_BASE_ADDR (MX21_X_MEMC_BASE_ADDR + 0x0000) @@ -92,10 +89,7 @@ #define MX21_IRAM_BASE_ADDR 0xffffe800 /* internal ram */ -#define MX21_IO_P2V(x) ( \ - IMX_IO_P2V_MODULE(x, MX21_AIPI) ?: \ - IMX_IO_P2V_MODULE(x, MX21_SAHB1) ?: \ - IMX_IO_P2V_MODULE(x, MX21_X_MEMC)) +#define MX21_IO_P2V(x) IMX_IO_P2V(x) #define MX21_IO_ADDRESS(x) IOMEM(MX21_IO_P2V(x)) /* fixed interrupt numbers */ @@ -197,7 +191,6 @@ #define PCMCIA_MEM_BASE_ADDR MX21_PCMCIA_MEM_BASE_ADDR #define CS5_BASE_ADDR MX21_CS5_BASE_ADDR #define X_MEMC_BASE_ADDR MX21_X_MEMC_BASE_ADDR -#define X_MEMC_BASE_ADDR_VIRT MX21_X_MEMC_BASE_ADDR_VIRT #define X_MEMC_SIZE MX21_X_MEMC_SIZE #define SDRAMC_BASE_ADDR MX21_SDRAMC_BASE_ADDR #define EIM_BASE_ADDR MX21_EIM_BASE_ADDR diff --git a/arch/arm/plat-mxc/include/mach/mx25.h b/arch/arm/plat-mxc/include/mach/mx25.h index 08b5a3a..aac6a9c 100644 --- a/arch/arm/plat-mxc/include/mach/mx25.h +++ b/arch/arm/plat-mxc/include/mach/mx25.h @@ -2,13 +2,11 @@ #define __MACH_MX25_H__ #define MX25_AIPS1_BASE_ADDR 0x43f00000 -#define MX25_AIPS1_BASE_ADDR_VIRT 0xfc000000 +#define MX25_AIPS1_BASE_ADDR_VIRT 0xf5300000 #define MX25_AIPS1_SIZE SZ_1M #define MX25_AIPS2_BASE_ADDR 0x53f00000 -#define MX25_AIPS2_BASE_ADDR_VIRT 0xfc200000 #define MX25_AIPS2_SIZE SZ_1M #define MX25_AVIC_BASE_ADDR 0x68000000 -#define MX25_AVIC_BASE_ADDR_VIRT 0xfc400000 #define MX25_AVIC_SIZE SZ_1M #define MX25_I2C1_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0x80000) @@ -27,12 +25,6 @@ #define MX25_GPIO2_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xd0000) #define MX25_WDOG_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xdc000) -#define MX25_IO_P2V(x) ( \ - IMX_IO_P2V_MODULE(x, MX25_AIPS1) ?: \ - IMX_IO_P2V_MODULE(x, MX25_AIPS2) ?: \ - IMX_IO_P2V_MODULE(x, MX25_AVIC)) -#define MX25_IO_ADDRESS(x) IOMEM(MX25_IO_P2V(x)) - #define MX25_AIPS1_IO_ADDRESS(x) \ (((x) - MX25_AIPS1_BASE_ADDR) + MX25_AIPS1_BASE_ADDR_VIRT) @@ -58,6 +50,9 @@ #define MX25_OTG_BASE_ADDR 0x53ff4000 #define MX25_CSI_BASE_ADDR 0x53ff8000 +#define MX25_IO_P2V(x) IMX_IO_P2V(x) +#define MX25_IO_ADDRESS(x) IOMEM(MX25_IO_P2V(x)) + #define MX25_INT_CSPI3 0 #define MX25_INT_I2C1 3 #define MX25_INT_I2C2 4 diff --git a/arch/arm/plat-mxc/include/mach/mx27.h b/arch/arm/plat-mxc/include/mach/mx27.h index c769cc8..e817289 100644 --- a/arch/arm/plat-mxc/include/mach/mx27.h +++ b/arch/arm/plat-mxc/include/mach/mx27.h @@ -29,7 +29,6 @@ #endif #define MX27_AIPI_BASE_ADDR 0x10000000 -#define MX27_AIPI_BASE_ADDR_VIRT 0xf4000000 #define MX27_AIPI_SIZE SZ_1M #define MX27_DMA_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x01000) #define MX27_WDOG_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x02000) @@ -87,7 +86,6 @@ #define MX27_ROMP_BASE_ADDR 0x10041000 #define MX27_SAHB1_BASE_ADDR 0x80000000 -#define MX27_SAHB1_BASE_ADDR_VIRT 0xf4100000 #define MX27_SAHB1_SIZE SZ_1M #define MX27_CSI_BASE_ADDR (MX27_SAHB1_BASE_ADDR + 0x0000) #define MX27_ATA_BASE_ADDR (MX27_SAHB1_BASE_ADDR + 0x1000) @@ -105,7 +103,6 @@ /* NAND, SDRAM, WEIM, M3IF, EMI controllers */ #define MX27_X_MEMC_BASE_ADDR 0xd8000000 -#define MX27_X_MEMC_BASE_ADDR_VIRT 0xf4200000 #define MX27_X_MEMC_SIZE SZ_1M #define MX27_NFC_BASE_ADDR (MX27_X_MEMC_BASE_ADDR) #define MX27_SDRAMC_BASE_ADDR (MX27_X_MEMC_BASE_ADDR + 0x1000) @@ -123,10 +120,7 @@ /* IRAM */ #define MX27_IRAM_BASE_ADDR 0xffff4c00 /* internal ram */ -#define MX27_IO_P2V(x) ( \ - IMX_IO_P2V_MODULE(x, MX27_AIPI) ?: \ - IMX_IO_P2V_MODULE(x, MX27_SAHB1) ?: \ - IMX_IO_P2V_MODULE(x, MX27_X_MEMC)) +#define MX27_IO_P2V(x) IMX_IO_P2V(x) #define MX27_IO_ADDRESS(x) IOMEM(MX27_IO_P2V(x)) #ifndef __ASSEMBLER__ @@ -280,7 +274,6 @@ extern int mx27_revision(void); #define CS4_BASE_ADDR MX27_CS4_BASE_ADDR #define CS5_BASE_ADDR MX27_CS5_BASE_ADDR #define X_MEMC_BASE_ADDR MX27_X_MEMC_BASE_ADDR -#define X_MEMC_BASE_ADDR_VIRT MX27_X_MEMC_BASE_ADDR_VIRT #define X_MEMC_SIZE MX27_X_MEMC_SIZE #define NFC_BASE_ADDR MX27_NFC_BASE_ADDR #define SDRAMC_BASE_ADDR MX27_SDRAMC_BASE_ADDR diff --git a/arch/arm/plat-mxc/include/mach/mx2x.h b/arch/arm/plat-mxc/include/mach/mx2x.h index afb895a..46eeeb2 100644 --- a/arch/arm/plat-mxc/include/mach/mx2x.h +++ b/arch/arm/plat-mxc/include/mach/mx2x.h @@ -27,7 +27,7 @@ /* Register offsets */ #define MX2x_AIPI_BASE_ADDR 0x10000000 -#define MX2x_AIPI_BASE_ADDR_VIRT 0xf4000000 +#define MX2x_AIPI_BASE_ADDR_VIRT 0xf4400000 #define MX2x_AIPI_SIZE SZ_1M #define MX2x_DMA_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x01000) #define MX2x_WDOG_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x02000) @@ -65,43 +65,12 @@ #define MX2x_AVIC_BASE_ADDR 0x10040000 #define MX2x_SAHB1_BASE_ADDR 0x80000000 -#define MX2x_SAHB1_BASE_ADDR_VIRT 0xf4100000 #define MX2x_SAHB1_SIZE SZ_1M #define MX2x_CSI_BASE_ADDR (MX2x_SAHB1_BASE_ADDR + 0x0000) -/* - * This macro defines the physical to virtual address mapping for all the - * peripheral modules. It is used by passing in the physical address as x - * and returning the virtual address. If the physical address is not mapped, - * it returns 0xDEADBEEF - */ -#define IO_ADDRESS(x) \ - (void __force __iomem *) \ - (((x >= AIPI_BASE_ADDR) && (x < (AIPI_BASE_ADDR + AIPI_SIZE))) ? \ - AIPI_IO_ADDRESS(x) : \ - ((x >= SAHB1_BASE_ADDR) && (x < (SAHB1_BASE_ADDR + SAHB1_SIZE))) ? \ - SAHB1_IO_ADDRESS(x) : \ - ((x >= X_MEMC_BASE_ADDR) && (x < (X_MEMC_BASE_ADDR + X_MEMC_SIZE))) ? \ - X_MEMC_IO_ADDRESS(x) : 0xDEADBEEF) - -/* define the address mapping macros: in physical address order */ -#define AIPI_IO_ADDRESS(x) \ +#define AIPI_IO_ADDRESS(x) \ (((x) - AIPI_BASE_ADDR) + AIPI_BASE_ADDR_VIRT) -#define AVIC_IO_ADDRESS(x) AIPI_IO_ADDRESS(x) - -#define SAHB1_IO_ADDRESS(x) \ - (((x) - SAHB1_BASE_ADDR) + SAHB1_BASE_ADDR_VIRT) - -#define CS4_IO_ADDRESS(x) \ - (((x) - CS4_BASE_ADDR) + CS4_BASE_ADDR_VIRT) - -#define X_MEMC_IO_ADDRESS(x) \ - (((x) - X_MEMC_BASE_ADDR) + X_MEMC_BASE_ADDR_VIRT) - -#define PCMCIA_IO_ADDRESS(x) \ - (((x) - X_MEMC_BASE_ADDR) + X_MEMC_BASE_ADDR_VIRT) - /* fixed interrupt numbers */ #define MX2x_INT_CSPI3 6 #define MX2x_INT_GPIO 8 @@ -215,7 +184,6 @@ #define MAX_BASE_ADDR MX2x_MAX_BASE_ADDR #define AVIC_BASE_ADDR MX2x_AVIC_BASE_ADDR #define SAHB1_BASE_ADDR MX2x_SAHB1_BASE_ADDR -#define SAHB1_BASE_ADDR_VIRT MX2x_SAHB1_BASE_ADDR_VIRT #define SAHB1_SIZE MX2x_SAHB1_SIZE #define CSI_BASE_ADDR MX2x_CSI_BASE_ADDR #define MXC_INT_CSPI3 MX2x_INT_CSPI3 diff --git a/arch/arm/plat-mxc/include/mach/mx31.h b/arch/arm/plat-mxc/include/mach/mx31.h index eb4a28d..9ed9975 100644 --- a/arch/arm/plat-mxc/include/mach/mx31.h +++ b/arch/arm/plat-mxc/include/mach/mx31.h @@ -15,7 +15,6 @@ #define MX31_L2CC_SIZE SZ_1M #define MX31_AIPS1_BASE_ADDR 0x43f00000 -#define MX31_AIPS1_BASE_ADDR_VIRT 0xfc000000 #define MX31_AIPS1_SIZE SZ_1M #define MX31_MAX_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x04000) #define MX31_EVTMON_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x08000) @@ -41,7 +40,6 @@ #define MX31_ECT_IP2_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xbc000) #define MX31_SPBA0_BASE_ADDR 0x50000000 -#define MX31_SPBA0_BASE_ADDR_VIRT 0xfc100000 #define MX31_SPBA0_SIZE SZ_1M #define MX31_MMC_SDHC1_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x04000) #define MX31_MMC_SDHC2_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x08000) @@ -55,7 +53,6 @@ #define MX31_SPBA_CTRL_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x3c000) #define MX31_AIPS2_BASE_ADDR 0x53f00000 -#define MX31_AIPS2_BASE_ADDR_VIRT 0xfc200000 #define MX31_AIPS2_SIZE SZ_1M #define MX31_CCM_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0x80000) #define MX31_CSPI3_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0x84000) @@ -84,7 +81,6 @@ #define MX31_ROMP_SIZE SZ_1M #define MX31_AVIC_BASE_ADDR 0x68000000 -#define MX31_AVIC_BASE_ADDR_VIRT 0xfc400000 #define MX31_AVIC_SIZE SZ_1M #define MX31_IPU_MEM_BASE_ADDR 0x70000000 @@ -97,15 +93,14 @@ #define MX31_CS3_BASE_ADDR 0xb2000000 #define MX31_CS4_BASE_ADDR 0xb4000000 -#define MX31_CS4_BASE_ADDR_VIRT 0xf4000000 +#define MX31_CS4_BASE_ADDR_VIRT 0xf6000000 #define MX31_CS4_SIZE SZ_32M #define MX31_CS5_BASE_ADDR 0xb6000000 -#define MX31_CS5_BASE_ADDR_VIRT 0xf6000000 +#define MX31_CS5_BASE_ADDR_VIRT 0xf8000000 #define MX31_CS5_SIZE SZ_32M #define MX31_X_MEMC_BASE_ADDR 0xb8000000 -#define MX31_X_MEMC_BASE_ADDR_VIRT 0xfc320000 #define MX31_X_MEMC_SIZE SZ_64K #define MX31_NFC_BASE_ADDR (MX31_X_MEMC_BASE_ADDR + 0x0000) #define MX31_ESDCTL_BASE_ADDR (MX31_X_MEMC_BASE_ADDR + 0x1000) @@ -121,12 +116,7 @@ #define MX31_PCMCIA_MEM_BASE_ADDR 0xbc000000 -#define MX31_IO_P2V(x) ( \ - IMX_IO_P2V_MODULE(x, MX31_AIPS1) ?: \ - IMX_IO_P2V_MODULE(x, MX31_AIPS2) ?: \ - IMX_IO_P2V_MODULE(x, MX31_AVIC) ?: \ - IMX_IO_P2V_MODULE(x, MX31_X_MEMC) ?: \ - IMX_IO_P2V_MODULE(x, MX31_SPBA0)) +#define MX31_IO_P2V(x) IMX_IO_P2V(x) #define MX31_IO_ADDRESS(x) IOMEM(MX31_IO_P2V(x)) #ifndef __ASSEMBLER__ diff --git a/arch/arm/plat-mxc/include/mach/mx35.h b/arch/arm/plat-mxc/include/mach/mx35.h index ce1a24b..3678ca3 100644 --- a/arch/arm/plat-mxc/include/mach/mx35.h +++ b/arch/arm/plat-mxc/include/mach/mx35.h @@ -11,7 +11,6 @@ #define MX35_L2CC_SIZE SZ_1M #define MX35_AIPS1_BASE_ADDR 0x43f00000 -#define MX35_AIPS1_BASE_ADDR_VIRT 0xfc000000 #define MX35_AIPS1_SIZE SZ_1M #define MX35_MAX_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x04000) #define MX35_EVTMON_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x08000) @@ -33,7 +32,6 @@ #define MX35_ECT_IP2_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0xbc000) #define MX35_SPBA0_BASE_ADDR 0x50000000 -#define MX35_SPBA0_BASE_ADDR_VIRT 0xfc100000 #define MX35_SPBA0_SIZE SZ_1M #define MX35_UART3_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x0c000) #define MX35_CSPI2_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x10000) @@ -44,7 +42,6 @@ #define MX35_SPBA_CTRL_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x3c000) #define MX35_AIPS2_BASE_ADDR 0x53f00000 -#define MX35_AIPS2_BASE_ADDR_VIRT 0xfc200000 #define MX35_AIPS2_SIZE SZ_1M #define MX35_CCM_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0x80000) #define MX35_GPT1_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0x90000) @@ -72,11 +69,9 @@ #define MX35_OTG_BASE_ADDR 0x53ff4000 #define MX35_ROMP_BASE_ADDR 0x60000000 -#define MX35_ROMP_BASE_ADDR_VIRT 0xfc500000 #define MX35_ROMP_SIZE SZ_1M #define MX35_AVIC_BASE_ADDR 0x68000000 -#define MX35_AVIC_BASE_ADDR_VIRT 0xfc400000 #define MX35_AVIC_SIZE SZ_1M /* @@ -92,18 +87,17 @@ #define MX35_CS3_BASE_ADDR 0xb2000000 #define MX35_CS4_BASE_ADDR 0xb4000000 -#define MX35_CS4_BASE_ADDR_VIRT 0xf4000000 +#define MX35_CS4_BASE_ADDR_VIRT 0xf6000000 #define MX35_CS4_SIZE SZ_32M #define MX35_CS5_BASE_ADDR 0xb6000000 -#define MX35_CS5_BASE_ADDR_VIRT 0xf6000000 +#define MX35_CS5_BASE_ADDR_VIRT 0xf8000000 #define MX35_CS5_SIZE SZ_32M /* * NAND, SDRAM, WEIM, M3IF, EMI controllers */ #define MX35_X_MEMC_BASE_ADDR 0xb8000000 -#define MX35_X_MEMC_BASE_ADDR_VIRT 0xfc320000 #define MX35_X_MEMC_SIZE SZ_64K #define MX35_ESDCTL_BASE_ADDR (MX35_X_MEMC_BASE_ADDR + 0x1000) #define MX35_WEIM_BASE_ADDR (MX35_X_MEMC_BASE_ADDR + 0x2000) @@ -114,12 +108,7 @@ #define MX35_NFC_BASE_ADDR 0xbb000000 #define MX35_PCMCIA_MEM_BASE_ADDR 0xbc000000 -#define MX35_IO_P2V(x) ( \ - IMX_IO_P2V_MODULE(x, MX35_AIPS1) ?: \ - IMX_IO_P2V_MODULE(x, MX35_AIPS2) ?: \ - IMX_IO_P2V_MODULE(x, MX35_AVIC) ?: \ - IMX_IO_P2V_MODULE(x, MX35_X_MEMC) ?: \ - IMX_IO_P2V_MODULE(x, MX35_SPBA0)) +#define MX35_IO_P2V(x) IMX_IO_P2V(x) #define MX35_IO_ADDRESS(x) IOMEM(MX35_IO_P2V(x)) /* diff --git a/arch/arm/plat-mxc/include/mach/mx3x.h b/arch/arm/plat-mxc/include/mach/mx3x.h index d1bd26d..da22cd4 100644 --- a/arch/arm/plat-mxc/include/mach/mx3x.h +++ b/arch/arm/plat-mxc/include/mach/mx3x.h @@ -44,7 +44,7 @@ * AIPS 1 */ #define MX3x_AIPS1_BASE_ADDR 0x43f00000 -#define MX3x_AIPS1_BASE_ADDR_VIRT 0xfc000000 +#define MX3x_AIPS1_BASE_ADDR_VIRT 0xf5300000 #define MX3x_AIPS1_SIZE SZ_1M #define MX3x_MAX_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x04000) #define MX3x_EVTMON_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x08000) @@ -69,7 +69,6 @@ * SPBA global module enabled #0 */ #define MX3x_SPBA0_BASE_ADDR 0x50000000 -#define MX3x_SPBA0_BASE_ADDR_VIRT 0xfc100000 #define MX3x_SPBA0_SIZE SZ_1M #define MX3x_UART3_BASE_ADDR (MX3x_SPBA0_BASE_ADDR + 0x0c000) #define MX3x_CSPI2_BASE_ADDR (MX3x_SPBA0_BASE_ADDR + 0x10000) @@ -82,7 +81,6 @@ * AIPS 2 */ #define MX3x_AIPS2_BASE_ADDR 0x53f00000 -#define MX3x_AIPS2_BASE_ADDR_VIRT 0xfc200000 #define MX3x_AIPS2_SIZE SZ_1M #define MX3x_CCM_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0x80000) #define MX3x_GPT1_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0x90000) @@ -105,11 +103,9 @@ * ROMP and AVIC */ #define MX3x_ROMP_BASE_ADDR 0x60000000 -#define MX3x_ROMP_BASE_ADDR_VIRT 0xfc500000 #define MX3x_ROMP_SIZE SZ_1M #define MX3x_AVIC_BASE_ADDR 0x68000000 -#define MX3x_AVIC_BASE_ADDR_VIRT 0xfc400000 #define MX3x_AVIC_SIZE SZ_1M /* @@ -125,18 +121,17 @@ #define MX3x_CS3_BASE_ADDR 0xb2000000 #define MX3x_CS4_BASE_ADDR 0xb4000000 -#define MX3x_CS4_BASE_ADDR_VIRT 0xf4000000 +#define MX3x_CS4_BASE_ADDR_VIRT 0xf6000000 #define MX3x_CS4_SIZE SZ_32M #define MX3x_CS5_BASE_ADDR 0xb6000000 -#define MX3x_CS5_BASE_ADDR_VIRT 0xf6000000 +#define MX3x_CS5_BASE_ADDR_VIRT 0xf8000000 #define MX3x_CS5_SIZE SZ_32M /* * NAND, SDRAM, WEIM, M3IF, EMI controllers */ #define MX3x_X_MEMC_BASE_ADDR 0xb8000000 -#define MX3x_X_MEMC_BASE_ADDR_VIRT 0xfc320000 #define MX3x_X_MEMC_SIZE SZ_64K #define MX3x_ESDCTL_BASE_ADDR (MX3x_X_MEMC_BASE_ADDR + 0x1000) #define MX3x_WEIM_BASE_ADDR (MX3x_X_MEMC_BASE_ADDR + 0x2000) @@ -146,56 +141,9 @@ #define MX3x_PCMCIA_MEM_BASE_ADDR 0xbc000000 -/*! - * This macro defines the physical to virtual address mapping for all the - * peripheral modules. It is used by passing in the physical address as x - * and returning the virtual address. If the physical address is not mapped, - * it returns 0xDEADBEEF - */ -#define IO_ADDRESS(x) \ - (void __force __iomem *) \ - (((x >= AIPS1_BASE_ADDR) && (x < (AIPS1_BASE_ADDR + AIPS1_SIZE))) ? AIPS1_IO_ADDRESS(x):\ - ((x >= SPBA0_BASE_ADDR) && (x < (SPBA0_BASE_ADDR + SPBA0_SIZE))) ? SPBA0_IO_ADDRESS(x):\ - ((x >= AIPS2_BASE_ADDR) && (x < (AIPS2_BASE_ADDR + AIPS2_SIZE))) ? AIPS2_IO_ADDRESS(x):\ - ((x >= ROMP_BASE_ADDR) && (x < (ROMP_BASE_ADDR + ROMP_SIZE))) ? ROMP_IO_ADDRESS(x):\ - ((x >= AVIC_BASE_ADDR) && (x < (AVIC_BASE_ADDR + AVIC_SIZE))) ? AVIC_IO_ADDRESS(x):\ - ((x >= CS4_BASE_ADDR) && (x < (CS4_BASE_ADDR + CS4_SIZE))) ? CS4_IO_ADDRESS(x):\ - ((x >= X_MEMC_BASE_ADDR) && (x < (X_MEMC_BASE_ADDR + X_MEMC_SIZE))) ? X_MEMC_IO_ADDRESS(x):\ - 0xDEADBEEF) - -/* - * define the address mapping macros: in physical address order - */ -#define L2CC_IO_ADDRESS(x) \ - (((x) - L2CC_BASE_ADDR) + L2CC_BASE_ADDR_VIRT) - #define AIPS1_IO_ADDRESS(x) \ (((x) - AIPS1_BASE_ADDR) + AIPS1_BASE_ADDR_VIRT) -#define SPBA0_IO_ADDRESS(x) \ - (((x) - SPBA0_BASE_ADDR) + SPBA0_BASE_ADDR_VIRT) - -#define AIPS2_IO_ADDRESS(x) \ - (((x) - AIPS2_BASE_ADDR) + AIPS2_BASE_ADDR_VIRT) - -#define ROMP_IO_ADDRESS(x) \ - (((x) - ROMP_BASE_ADDR) + ROMP_BASE_ADDR_VIRT) - -#define AVIC_IO_ADDRESS(x) \ - (((x) - AVIC_BASE_ADDR) + AVIC_BASE_ADDR_VIRT) - -#define CS4_IO_ADDRESS(x) \ - (((x) - CS4_BASE_ADDR) + CS4_BASE_ADDR_VIRT) - -#define CS5_IO_ADDRESS(x) \ - (((x) - CS5_BASE_ADDR) + CS5_BASE_ADDR_VIRT) - -#define X_MEMC_IO_ADDRESS(x) \ - (((x) - X_MEMC_BASE_ADDR) + X_MEMC_BASE_ADDR_VIRT) - -#define PCMCIA_IO_ADDRESS(x) \ - (((x) - X_MEMC_BASE_ADDR) + X_MEMC_BASE_ADDR_VIRT) - /* * Interrupt numbers */ @@ -303,7 +251,6 @@ static inline int mx35_revision(void) #define ECT_IP1_BASE_ADDR MX3x_ECT_IP1_BASE_ADDR #define ECT_IP2_BASE_ADDR MX3x_ECT_IP2_BASE_ADDR #define SPBA0_BASE_ADDR MX3x_SPBA0_BASE_ADDR -#define SPBA0_BASE_ADDR_VIRT MX3x_SPBA0_BASE_ADDR_VIRT #define SPBA0_SIZE MX3x_SPBA0_SIZE #define UART3_BASE_ADDR MX3x_UART3_BASE_ADDR #define CSPI2_BASE_ADDR MX3x_CSPI2_BASE_ADDR @@ -312,7 +259,6 @@ static inline int mx35_revision(void) #define MSHC1_BASE_ADDR MX3x_MSHC1_BASE_ADDR #define SPBA_CTRL_BASE_ADDR MX3x_SPBA_CTRL_BASE_ADDR #define AIPS2_BASE_ADDR MX3x_AIPS2_BASE_ADDR -#define AIPS2_BASE_ADDR_VIRT MX3x_AIPS2_BASE_ADDR_VIRT #define AIPS2_SIZE MX3x_AIPS2_SIZE #define CCM_BASE_ADDR MX3x_CCM_BASE_ADDR #define GPT1_BASE_ADDR MX3x_GPT1_BASE_ADDR @@ -331,10 +277,8 @@ static inline int mx35_revision(void) #define PWM_BASE_ADDR MX3x_PWM_BASE_ADDR #define RTIC_BASE_ADDR MX3x_RTIC_BASE_ADDR #define ROMP_BASE_ADDR MX3x_ROMP_BASE_ADDR -#define ROMP_BASE_ADDR_VIRT MX3x_ROMP_BASE_ADDR_VIRT #define ROMP_SIZE MX3x_ROMP_SIZE #define AVIC_BASE_ADDR MX3x_AVIC_BASE_ADDR -#define AVIC_BASE_ADDR_VIRT MX3x_AVIC_BASE_ADDR_VIRT #define AVIC_SIZE MX3x_AVIC_SIZE #define IPU_MEM_BASE_ADDR MX3x_IPU_MEM_BASE_ADDR #define CSD0_BASE_ADDR MX3x_CSD0_BASE_ADDR @@ -344,13 +288,10 @@ static inline int mx35_revision(void) #define CS2_BASE_ADDR MX3x_CS2_BASE_ADDR #define CS3_BASE_ADDR MX3x_CS3_BASE_ADDR #define CS4_BASE_ADDR MX3x_CS4_BASE_ADDR -#define CS4_BASE_ADDR_VIRT MX3x_CS4_BASE_ADDR_VIRT #define CS4_SIZE MX3x_CS4_SIZE #define CS5_BASE_ADDR MX3x_CS5_BASE_ADDR -#define CS5_BASE_ADDR_VIRT MX3x_CS5_BASE_ADDR_VIRT #define CS5_SIZE MX3x_CS5_SIZE #define X_MEMC_BASE_ADDR MX3x_X_MEMC_BASE_ADDR -#define X_MEMC_BASE_ADDR_VIRT MX3x_X_MEMC_BASE_ADDR_VIRT #define X_MEMC_SIZE MX3x_X_MEMC_SIZE #define ESDCTL_BASE_ADDR MX3x_ESDCTL_BASE_ADDR #define WEIM_BASE_ADDR MX3x_WEIM_BASE_ADDR diff --git a/arch/arm/plat-mxc/include/mach/mx51.h b/arch/arm/plat-mxc/include/mach/mx51.h index e93cf5b..1b8715f 100644 --- a/arch/arm/plat-mxc/include/mach/mx51.h +++ b/arch/arm/plat-mxc/include/mach/mx51.h @@ -2,31 +2,6 @@ #define __MACH_MX51_H__ /* - * MX51 memory map: - * - * - * Virt Phys Size What - * --------------------------------------------------------------------------- - * fa3e0000 1ffe0000 128K IRAM (SCCv2 RAM) - * 30000000 256M GPU - * 40000000 512M IPU - * fa200000 60000000 1M DEBUG - * fb100000 70000000 1M SPBA 0 - * fb000000 73f00000 1M AIPS 1 - * fb200000 83f00000 1M AIPS 2 - * 8fffc000 16K TZIC (interrupt controller) - * 90000000 256M CSD0 SDRAM/DDR - * a0000000 256M CSD1 SDRAM/DDR - * b0000000 128M CS0 Flash - * b8000000 128M CS1 Flash - * c0000000 128M CS2 Flash - * c8000000 64M CS3 Flash - * cc000000 32M CS4 SRAM - * ce000000 32M CS5 SRAM - * cfff0000 64K NFC (NAND Flash AXI) - */ - -/* * IROM */ #define MX51_IROM_BASE_ADDR 0x0 @@ -36,7 +11,6 @@ * IRAM */ #define MX51_IRAM_BASE_ADDR 0x1ffe0000 /* internal ram */ -#define MX51_IRAM_BASE_ADDR_VIRT 0xfa3e0000 #define MX51_IRAM_PARTITIONS 16 #define MX51_IRAM_SIZE (MX51_IRAM_PARTITIONS * SZ_8K) /* 128KB */ @@ -45,7 +19,6 @@ #define MX51_IPU_CTRL_BASE_ADDR 0x40000000 #define MX51_DEBUG_BASE_ADDR 0x60000000 -#define MX51_DEBUG_BASE_ADDR_VIRT 0xfa200000 #define MX51_DEBUG_SIZE SZ_1M #define MX51_ETB_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x01000) @@ -61,7 +34,6 @@ * SPBA global module enabled #0 */ #define MX51_SPBA0_BASE_ADDR 0x70000000 -#define MX51_SPBA0_BASE_ADDR_VIRT 0xfb100000 #define MX51_SPBA0_SIZE SZ_1M #define MX51_ESDHC1_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x04000) @@ -81,7 +53,7 @@ * AIPS 1 */ #define MX51_AIPS1_BASE_ADDR 0x73f00000 -#define MX51_AIPS1_BASE_ADDR_VIRT 0xfb000000 +#define MX51_AIPS1_BASE_ADDR_VIRT 0xf5700000 #define MX51_AIPS1_SIZE SZ_1M #define MX51_OTG_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x80000) @@ -109,7 +81,6 @@ * AIPS 2 */ #define MX51_AIPS2_BASE_ADDR 0x83f00000 -#define MX51_AIPS2_BASE_ADDR_VIRT 0xfb200000 #define MX51_AIPS2_SIZE SZ_1M #define MX51_PLL1_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x80000) @@ -163,12 +134,7 @@ #define MX51_GPU2D_BASE_ADDR 0xd0000000 #define MX51_TZIC_BASE_ADDR 0xe0000000 -#define MX51_IO_P2V(x) ( \ - IMX_IO_P2V_MODULE(x, MX51_IRAM) ?: \ - IMX_IO_P2V_MODULE(x, MX51_DEBUG) ?: \ - IMX_IO_P2V_MODULE(x, MX51_SPBA0) ?: \ - IMX_IO_P2V_MODULE(x, MX51_AIPS1) ?: \ - IMX_IO_P2V_MODULE(x, MX51_AIPS2)) +#define MX51_IO_P2V(x) IMX_IO_P2V(x) #define MX51_IO_ADDRESS(x) IOMEM(MX51_IO_P2V(x)) /* This is currently used in , but should go away */ diff --git a/arch/arm/plat-mxc/include/mach/mxc91231.h b/arch/arm/plat-mxc/include/mach/mxc91231.h index 49e5e25..765190f 100644 --- a/arch/arm/plat-mxc/include/mach/mxc91231.h +++ b/arch/arm/plat-mxc/include/mach/mxc91231.h @@ -21,14 +21,12 @@ * L2CC */ #define MXC91231_L2CC_BASE_ADDR 0x30000000 -#define MXC91231_L2CC_BASE_ADDR_VIRT 0xF9000000 #define MXC91231_L2CC_SIZE SZ_64K /* * AIPS 1 */ #define MXC91231_AIPS1_BASE_ADDR 0x43F00000 -#define MXC91231_AIPS1_BASE_ADDR_VIRT 0xFC000000 #define MXC91231_AIPS1_SIZE SZ_1M #define MXC91231_AIPS1_CTRL_BASE_ADDR MXC91231_AIPS1_BASE_ADDR @@ -53,7 +51,6 @@ * AIPS 2 */ #define MXC91231_AIPS2_BASE_ADDR 0x53F00000 -#define MXC91231_AIPS2_BASE_ADDR_VIRT 0xFC100000 #define MXC91231_AIPS2_SIZE SZ_1M #define MXC91231_GEMK_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0x8C000) @@ -79,7 +76,6 @@ * SPBA global module 0 */ #define MXC91231_SPBA0_BASE_ADDR 0x50000000 -#define MXC91231_SPBA0_BASE_ADDR_VIRT 0xFC200000 #define MXC91231_SPBA0_SIZE SZ_1M #define MXC91231_MMC_SDHC1_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x04000) @@ -109,7 +105,6 @@ * SPBA global module 1 */ #define MXC91231_SPBA1_BASE_ADDR 0x52000000 -#define MXC91231_SPBA1_BASE_ADDR_VIRT 0xFC300000 #define MXC91231_SPBA1_SIZE SZ_1M #define MXC91231_MQSPI_BASE_ADDR (MXC91231_SPBA1_BASE_ADDR + 0x34000) @@ -144,18 +139,15 @@ * ROMP and AVIC */ #define MXC91231_ROMP_BASE_ADDR 0x60000000 -#define MXC91231_ROMP_BASE_ADDR_VIRT 0xFC400000 #define MXC91231_ROMP_SIZE SZ_64K #define MXC91231_AVIC_BASE_ADDR 0x68000000 -#define MXC91231_AVIC_BASE_ADDR_VIRT 0xFC410000 #define MXC91231_AVIC_SIZE SZ_64K /* * NAND, SDRAM, WEIM, M3IF, EMI controllers */ #define MXC91231_X_MEMC_BASE_ADDR 0xB8000000 -#define MXC91231_X_MEMC_BASE_ADDR_VIRT 0xFC420000 #define MXC91231_X_MEMC_SIZE SZ_64K #define MXC91231_NFC_BASE_ADDR (MXC91231_X_MEMC_BASE_ADDR + 0x0000) @@ -183,19 +175,9 @@ /* * This macro defines the physical to virtual address mapping for all the * peripheral modules. It is used by passing in the physical address as x - * and returning the virtual address. If the physical address is not mapped, - * it returns 0. + * and returning the virtual address. */ - -#define MXC91231_IO_P2V(x) ( \ - IMX_IO_P2V_MODULE(x, MXC91231_L2CC) ?: \ - IMX_IO_P2V_MODULE(x, MXC91231_X_MEMC) ?: \ - IMX_IO_P2V_MODULE(x, MXC91231_ROMP) ?: \ - IMX_IO_P2V_MODULE(x, MXC91231_AVIC) ?: \ - IMX_IO_P2V_MODULE(x, MXC91231_AIPS1) ?: \ - IMX_IO_P2V_MODULE(x, MXC91231_SPBA0) ?: \ - IMX_IO_P2V_MODULE(x, MXC91231_SPBA1) ?: \ - IMX_IO_P2V_MODULE(x, MXC91231_AIPS2)) +#define MXC91231_IO_P2V(x) IMX_IO_P2V(x) #define MXC91231_IO_ADDRESS(x) IOMEM(MXC91231_IO_P2V(x)) /* -- cgit v1.1 From ac401427c05a6a371950a1cdfaec75f72bffb9b5 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Tue, 26 Oct 2010 09:42:54 +0200 Subject: ARM: imx/debug-macro: rework using the new io mapping macro MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This gets rid of the last user of IMX_NEEDS_DEPRECATED_SYMBOLS. Signed-off-by: Uwe Kleine-König --- arch/arm/plat-mxc/include/mach/debug-macro.S | 23 +++++++---------------- arch/arm/plat-mxc/include/mach/mx25.h | 4 ---- arch/arm/plat-mxc/include/mach/mx2x.h | 5 ----- arch/arm/plat-mxc/include/mach/mx3x.h | 5 ----- arch/arm/plat-mxc/include/mach/mx51.h | 5 ----- 5 files changed, 7 insertions(+), 35 deletions(-) (limited to 'arch/arm/plat-mxc') diff --git a/arch/arm/plat-mxc/include/mach/debug-macro.S b/arch/arm/plat-mxc/include/mach/debug-macro.S index d56213f..3b3a37c 100644 --- a/arch/arm/plat-mxc/include/mach/debug-macro.S +++ b/arch/arm/plat-mxc/include/mach/debug-macro.S @@ -10,58 +10,49 @@ * published by the Free Software Foundation. * */ -#define IMX_NEEDS_DEPRECATED_SYMBOLS +#include #ifdef CONFIG_ARCH_MX1 -#include -#define UART_PADDR UART1_BASE_ADDR -#define UART_VADDR IO_ADDRESS(UART1_BASE_ADDR) +#define UART_PADDR MX1_UART1_BASE_ADDR #endif #ifdef CONFIG_ARCH_MX25 #ifdef UART_PADDR #error "CONFIG_DEBUG_LL is incompatible with multiple archs" #endif -#include #define UART_PADDR MX25_UART1_BASE_ADDR -#define UART_VADDR MX25_AIPS1_IO_ADDRESS(MX25_UART1_BASE_ADDR) #endif #ifdef CONFIG_ARCH_MX2 #ifdef UART_PADDR #error "CONFIG_DEBUG_LL is incompatible with multiple archs" #endif -#include -#define UART_PADDR UART1_BASE_ADDR -#define UART_VADDR AIPI_IO_ADDRESS(UART1_BASE_ADDR) +#define UART_PADDR MX2x_UART1_BASE_ADDR #endif #ifdef CONFIG_ARCH_MX3 #ifdef UART_PADDR #error "CONFIG_DEBUG_LL is incompatible with multiple archs" #endif -#include -#define UART_PADDR UART1_BASE_ADDR -#define UART_VADDR AIPS1_IO_ADDRESS(UART1_BASE_ADDR) +#define UART_PADDR MX3x_UART1_BASE_ADDR #endif #ifdef CONFIG_ARCH_MX5 #ifdef UART_PADDR #error "CONFIG_DEBUG_LL is incompatible with multiple archs" #endif -#include #define UART_PADDR MX51_UART1_BASE_ADDR -#define UART_VADDR MX51_AIPS1_IO_ADDRESS(MX51_UART1_BASE_ADDR) #endif #ifdef CONFIG_ARCH_MXC91231 #ifdef UART_PADDR #error "CONFIG_DEBUG_LL is incompatible with multiple archs" #endif -#include #define UART_PADDR MXC91231_UART2_BASE_ADDR -#define UART_VADDR MXC91231_IO_ADDRESS(MXC91231_UART2_BASE_ADDR) #endif + +#define UART_VADDR IMX_IO_ADDRESS(UART_PADDR) + .macro addruart, rp, rv ldr \rp, =UART_PADDR @ physical ldr \rv, =UART_VADDR @ virtual diff --git a/arch/arm/plat-mxc/include/mach/mx25.h b/arch/arm/plat-mxc/include/mach/mx25.h index aac6a9c..a2404b0 100644 --- a/arch/arm/plat-mxc/include/mach/mx25.h +++ b/arch/arm/plat-mxc/include/mach/mx25.h @@ -2,7 +2,6 @@ #define __MACH_MX25_H__ #define MX25_AIPS1_BASE_ADDR 0x43f00000 -#define MX25_AIPS1_BASE_ADDR_VIRT 0xf5300000 #define MX25_AIPS1_SIZE SZ_1M #define MX25_AIPS2_BASE_ADDR 0x53f00000 #define MX25_AIPS2_SIZE SZ_1M @@ -25,9 +24,6 @@ #define MX25_GPIO2_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xd0000) #define MX25_WDOG_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xdc000) -#define MX25_AIPS1_IO_ADDRESS(x) \ - (((x) - MX25_AIPS1_BASE_ADDR) + MX25_AIPS1_BASE_ADDR_VIRT) - #define MX25_UART1_BASE_ADDR 0x43f90000 #define MX25_UART2_BASE_ADDR 0x43f94000 #define MX25_AUDMUX_BASE_ADDR 0x43fb0000 diff --git a/arch/arm/plat-mxc/include/mach/mx2x.h b/arch/arm/plat-mxc/include/mach/mx2x.h index 46eeeb2..a056948 100644 --- a/arch/arm/plat-mxc/include/mach/mx2x.h +++ b/arch/arm/plat-mxc/include/mach/mx2x.h @@ -27,7 +27,6 @@ /* Register offsets */ #define MX2x_AIPI_BASE_ADDR 0x10000000 -#define MX2x_AIPI_BASE_ADDR_VIRT 0xf4400000 #define MX2x_AIPI_SIZE SZ_1M #define MX2x_DMA_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x01000) #define MX2x_WDOG_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x02000) @@ -68,9 +67,6 @@ #define MX2x_SAHB1_SIZE SZ_1M #define MX2x_CSI_BASE_ADDR (MX2x_SAHB1_BASE_ADDR + 0x0000) -#define AIPI_IO_ADDRESS(x) \ - (((x) - AIPI_BASE_ADDR) + AIPI_BASE_ADDR_VIRT) - /* fixed interrupt numbers */ #define MX2x_INT_CSPI3 6 #define MX2x_INT_GPIO 8 @@ -148,7 +144,6 @@ #ifdef IMX_NEEDS_DEPRECATED_SYMBOLS /* these should go away */ #define AIPI_BASE_ADDR MX2x_AIPI_BASE_ADDR -#define AIPI_BASE_ADDR_VIRT MX2x_AIPI_BASE_ADDR_VIRT #define AIPI_SIZE MX2x_AIPI_SIZE #define DMA_BASE_ADDR MX2x_DMA_BASE_ADDR #define WDOG_BASE_ADDR MX2x_WDOG_BASE_ADDR diff --git a/arch/arm/plat-mxc/include/mach/mx3x.h b/arch/arm/plat-mxc/include/mach/mx3x.h index da22cd4..3d6cc45 100644 --- a/arch/arm/plat-mxc/include/mach/mx3x.h +++ b/arch/arm/plat-mxc/include/mach/mx3x.h @@ -44,7 +44,6 @@ * AIPS 1 */ #define MX3x_AIPS1_BASE_ADDR 0x43f00000 -#define MX3x_AIPS1_BASE_ADDR_VIRT 0xf5300000 #define MX3x_AIPS1_SIZE SZ_1M #define MX3x_MAX_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x04000) #define MX3x_EVTMON_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x08000) @@ -141,9 +140,6 @@ #define MX3x_PCMCIA_MEM_BASE_ADDR 0xbc000000 -#define AIPS1_IO_ADDRESS(x) \ - (((x) - AIPS1_BASE_ADDR) + AIPS1_BASE_ADDR_VIRT) - /* * Interrupt numbers */ @@ -230,7 +226,6 @@ static inline int mx35_revision(void) #define L2CC_BASE_ADDR MX3x_L2CC_BASE_ADDR #define L2CC_SIZE MX3x_L2CC_SIZE #define AIPS1_BASE_ADDR MX3x_AIPS1_BASE_ADDR -#define AIPS1_BASE_ADDR_VIRT MX3x_AIPS1_BASE_ADDR_VIRT #define AIPS1_SIZE MX3x_AIPS1_SIZE #define MAX_BASE_ADDR MX3x_MAX_BASE_ADDR #define EVTMON_BASE_ADDR MX3x_EVTMON_BASE_ADDR diff --git a/arch/arm/plat-mxc/include/mach/mx51.h b/arch/arm/plat-mxc/include/mach/mx51.h index 1b8715f..636347c 100644 --- a/arch/arm/plat-mxc/include/mach/mx51.h +++ b/arch/arm/plat-mxc/include/mach/mx51.h @@ -53,7 +53,6 @@ * AIPS 1 */ #define MX51_AIPS1_BASE_ADDR 0x73f00000 -#define MX51_AIPS1_BASE_ADDR_VIRT 0xf5700000 #define MX51_AIPS1_SIZE SZ_1M #define MX51_OTG_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x80000) @@ -137,10 +136,6 @@ #define MX51_IO_P2V(x) IMX_IO_P2V(x) #define MX51_IO_ADDRESS(x) IOMEM(MX51_IO_P2V(x)) -/* This is currently used in , but should go away */ -#define MX51_AIPS1_IO_ADDRESS(x) \ - (((x) - MX51_AIPS1_BASE_ADDR) + MX51_AIPS1_BASE_ADDR_VIRT) - /* * defines for SPBA modules */ -- cgit v1.1 From d96801b2ca47cfeddadede7a1998e1fe0eab095c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Fri, 22 Oct 2010 09:20:52 +0200 Subject: ARM: imx: remove deprecated symbols as all users are gone now MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Uwe Kleine-König --- arch/arm/plat-mxc/include/mach/mx1.h | 127 ---------------------------------- arch/arm/plat-mxc/include/mach/mx21.h | 34 --------- arch/arm/plat-mxc/include/mach/mx27.h | 69 ------------------ arch/arm/plat-mxc/include/mach/mx2x.h | 112 ------------------------------ arch/arm/plat-mxc/include/mach/mx31.h | 32 --------- arch/arm/plat-mxc/include/mach/mx35.h | 16 ----- arch/arm/plat-mxc/include/mach/mx3x.h | 114 ------------------------------ 7 files changed, 504 deletions(-) (limited to 'arch/arm/plat-mxc') diff --git a/arch/arm/plat-mxc/include/mach/mx1.h b/arch/arm/plat-mxc/include/mach/mx1.h index b786ae7..b6771f4 100644 --- a/arch/arm/plat-mxc/include/mach/mx1.h +++ b/arch/arm/plat-mxc/include/mach/mx1.h @@ -165,131 +165,4 @@ */ #define USBD_INT0 MX1_USBD_INT0 -#ifdef IMX_NEEDS_DEPRECATED_SYMBOLS -/* these should go away */ -#define IMX_IO_PHYS MX1_IO_BASE_ADDR -#define IMX_IO_SIZE MX1_IO_SIZE -#define IMX_CS0_PHYS MX1_CS0_PHYS -#define IMX_CS0_SIZE MX1_CS0_SIZE -#define IMX_CS1_PHYS MX1_CS1_PHYS -#define IMX_CS1_SIZE MX1_CS1_SIZE -#define IMX_CS2_PHYS MX1_CS2_PHYS -#define IMX_CS2_SIZE MX1_CS2_SIZE -#define IMX_CS3_PHYS MX1_CS3_PHYS -#define IMX_CS3_SIZE MX1_CS3_SIZE -#define IMX_CS4_PHYS MX1_CS4_PHYS -#define IMX_CS4_SIZE MX1_CS4_SIZE -#define IMX_CS5_PHYS MX1_CS5_PHYS -#define IMX_CS5_SIZE MX1_CS5_SIZE -#define AIPI1_BASE_ADDR MX1_AIPI1_BASE_ADDR -#define WDT_BASE_ADDR MX1_WDT_BASE_ADDR -#define TIM1_BASE_ADDR MX1_TIM1_BASE_ADDR -#define TIM2_BASE_ADDR MX1_TIM2_BASE_ADDR -#define RTC_BASE_ADDR MX1_RTC_BASE_ADDR -#define LCDC_BASE_ADDR MX1_LCDC_BASE_ADDR -#define UART1_BASE_ADDR MX1_UART1_BASE_ADDR -#define UART2_BASE_ADDR MX1_UART2_BASE_ADDR -#define PWM_BASE_ADDR MX1_PWM_BASE_ADDR -#define DMA_BASE_ADDR MX1_DMA_BASE_ADDR -#define AIPI2_BASE_ADDR MX1_AIPI2_BASE_ADDR -#define SIM_BASE_ADDR MX1_SIM_BASE_ADDR -#define USBD_BASE_ADDR MX1_USBD_BASE_ADDR -#define SPI1_BASE_ADDR MX1_SPI1_BASE_ADDR -#define MMC_BASE_ADDR MX1_MMC_BASE_ADDR -#define ASP_BASE_ADDR MX1_ASP_BASE_ADDR -#define BTA_BASE_ADDR MX1_BTA_BASE_ADDR -#define I2C_BASE_ADDR MX1_I2C_BASE_ADDR -#define SSI_BASE_ADDR MX1_SSI_BASE_ADDR -#define SPI2_BASE_ADDR MX1_SPI2_BASE_ADDR -#define MSHC_BASE_ADDR MX1_MSHC_BASE_ADDR -#define CCM_BASE_ADDR MX1_CCM_BASE_ADDR -#define SCM_BASE_ADDR MX1_SCM_BASE_ADDR -#define GPIO_BASE_ADDR MX1_GPIO_BASE_ADDR -#define EIM_BASE_ADDR MX1_EIM_BASE_ADDR -#define SDRAMC_BASE_ADDR MX1_SDRAMC_BASE_ADDR -#define MMA_BASE_ADDR MX1_MMA_BASE_ADDR -#define AVIC_BASE_ADDR MX1_AVIC_BASE_ADDR -#define CSI_BASE_ADDR MX1_CSI_BASE_ADDR -#define IO_ADDRESS(x) MX1_IO_ADDRESS(x) -#define AVIC_IO_ADDRESS(x) IO_ADDRESS(x) -#define INT_SOFTINT MX1_INT_SOFTINT -#define CSI_INT MX1_CSI_INT -#define DSPA_MAC_INT MX1_DSPA_MAC_INT -#define DSPA_INT MX1_DSPA_INT -#define COMP_INT MX1_COMP_INT -#define MSHC_XINT MX1_MSHC_XINT -#define GPIO_INT_PORTA MX1_GPIO_INT_PORTA -#define GPIO_INT_PORTB MX1_GPIO_INT_PORTB -#define GPIO_INT_PORTC MX1_GPIO_INT_PORTC -#define LCDC_INT MX1_LCDC_INT -#define SIM_INT MX1_SIM_INT -#define SIM_DATA_INT MX1_SIM_DATA_INT -#define RTC_INT MX1_RTC_INT -#define RTC_SAMINT MX1_RTC_SAMINT -#define UART2_MINT_PFERR MX1_UART2_MINT_PFERR -#define UART2_MINT_RTS MX1_UART2_MINT_RTS -#define UART2_MINT_DTR MX1_UART2_MINT_DTR -#define UART2_MINT_UARTC MX1_UART2_MINT_UARTC -#define UART2_MINT_TX MX1_UART2_MINT_TX -#define UART2_MINT_RX MX1_UART2_MINT_RX -#define UART1_MINT_PFERR MX1_UART1_MINT_PFERR -#define UART1_MINT_RTS MX1_UART1_MINT_RTS -#define UART1_MINT_DTR MX1_UART1_MINT_DTR -#define UART1_MINT_UARTC MX1_UART1_MINT_UARTC -#define UART1_MINT_TX MX1_UART1_MINT_TX -#define UART1_MINT_RX MX1_UART1_MINT_RX -#define VOICE_DAC_INT MX1_VOICE_DAC_INT -#define VOICE_ADC_INT MX1_VOICE_ADC_INT -#define PEN_DATA_INT MX1_PEN_DATA_INT -#define PWM_INT MX1_PWM_INT -#define SDHC_INT MX1_SDHC_INT -#define I2C_INT MX1_INT_I2C -#define CSPI_INT MX1_CSPI_INT -#define SSI_TX_INT MX1_SSI_TX_INT -#define SSI_TX_ERR_INT MX1_SSI_TX_ERR_INT -#define SSI_RX_INT MX1_SSI_RX_INT -#define SSI_RX_ERR_INT MX1_SSI_RX_ERR_INT -#define TOUCH_INT MX1_TOUCH_INT -#define USBD_INT1 MX1_USBD_INT1 -#define USBD_INT2 MX1_USBD_INT2 -#define USBD_INT3 MX1_USBD_INT3 -#define USBD_INT4 MX1_USBD_INT4 -#define USBD_INT5 MX1_USBD_INT5 -#define USBD_INT6 MX1_USBD_INT6 -#define BTSYS_INT MX1_BTSYS_INT -#define BTTIM_INT MX1_BTTIM_INT -#define BTWUI_INT MX1_BTWUI_INT -#define TIM2_INT MX1_TIM2_INT -#define TIM1_INT MX1_TIM1_INT -#define DMA_ERR MX1_DMA_ERR -#define DMA_INT MX1_DMA_INT -#define GPIO_INT_PORTD MX1_GPIO_INT_PORTD -#define WDT_INT MX1_WDT_INT -#define DMA_REQ_UART3_T MX1_DMA_REQ_UART3_T -#define DMA_REQ_UART3_R MX1_DMA_REQ_UART3_R -#define DMA_REQ_SSI2_T MX1_DMA_REQ_SSI2_T -#define DMA_REQ_SSI2_R MX1_DMA_REQ_SSI2_R -#define DMA_REQ_CSI_STAT MX1_DMA_REQ_CSI_STAT -#define DMA_REQ_CSI_R MX1_DMA_REQ_CSI_R -#define DMA_REQ_MSHC MX1_DMA_REQ_MSHC -#define DMA_REQ_DSPA_DCT_DOUT MX1_DMA_REQ_DSPA_DCT_DOUT -#define DMA_REQ_DSPA_DCT_DIN MX1_DMA_REQ_DSPA_DCT_DIN -#define DMA_REQ_DSPA_MAC MX1_DMA_REQ_DSPA_MAC -#define DMA_REQ_EXT MX1_DMA_REQ_EXT -#define DMA_REQ_SDHC MX1_DMA_REQ_SDHC -#define DMA_REQ_SPI1_R MX1_DMA_REQ_SPI1_R -#define DMA_REQ_SPI1_T MX1_DMA_REQ_SPI1_T -#define DMA_REQ_SSI_T MX1_DMA_REQ_SSI_T -#define DMA_REQ_SSI_R MX1_DMA_REQ_SSI_R -#define DMA_REQ_ASP_DAC MX1_DMA_REQ_ASP_DAC -#define DMA_REQ_ASP_ADC MX1_DMA_REQ_ASP_ADC -#define DMA_REQ_USP_EP(x) MX1_DMA_REQ_USP_EP(x) -#define DMA_REQ_SPI2_R MX1_DMA_REQ_SPI2_R -#define DMA_REQ_SPI2_T MX1_DMA_REQ_SPI2_T -#define DMA_REQ_UART2_T MX1_DMA_REQ_UART2_T -#define DMA_REQ_UART2_R MX1_DMA_REQ_UART2_R -#define DMA_REQ_UART1_T MX1_DMA_REQ_UART1_T -#define DMA_REQ_UART1_R MX1_DMA_REQ_UART1_R -#endif /* ifdef IMX_NEEDS_DEPRECATED_SYMBOLS */ - #endif /* ifndef __MACH_MX1_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/mx21.h b/arch/arm/plat-mxc/include/mach/mx21.h index b417e32..a82f590 100644 --- a/arch/arm/plat-mxc/include/mach/mx21.h +++ b/arch/arm/plat-mxc/include/mach/mx21.h @@ -179,38 +179,4 @@ #define MX21_DMA_REQ_CSI_STAT 30 #define MX21_DMA_REQ_CSI_RX 31 -#ifdef IMX_NEEDS_DEPRECATED_SYMBOLS -/* these should go away */ -#define SDRAM_BASE_ADDR MX21_SDRAM_BASE_ADDR -#define CSD1_BASE_ADDR MX21_CSD1_BASE_ADDR -#define CS0_BASE_ADDR MX21_CS0_BASE_ADDR -#define CS1_BASE_ADDR MX21_CS1_BASE_ADDR -#define CS2_BASE_ADDR MX21_CS2_BASE_ADDR -#define CS3_BASE_ADDR MX21_CS3_BASE_ADDR -#define CS4_BASE_ADDR MX21_CS4_BASE_ADDR -#define PCMCIA_MEM_BASE_ADDR MX21_PCMCIA_MEM_BASE_ADDR -#define CS5_BASE_ADDR MX21_CS5_BASE_ADDR -#define X_MEMC_BASE_ADDR MX21_X_MEMC_BASE_ADDR -#define X_MEMC_SIZE MX21_X_MEMC_SIZE -#define SDRAMC_BASE_ADDR MX21_SDRAMC_BASE_ADDR -#define EIM_BASE_ADDR MX21_EIM_BASE_ADDR -#define PCMCIA_CTL_BASE_ADDR MX21_PCMCIA_CTL_BASE_ADDR -#define NFC_BASE_ADDR MX21_NFC_BASE_ADDR -#define IRAM_BASE_ADDR MX21_IRAM_BASE_ADDR -#define MXC_INT_FIRI MX21_INT_FIRI -#define MXC_INT_BMI MX21_INT_BMI -#define MXC_INT_EMMAENC MX21_INT_EMMAENC -#define MXC_INT_EMMADEC MX21_INT_EMMADEC -#define MXC_INT_USBWKUP MX21_INT_USBWKUP -#define MXC_INT_USBDMA MX21_INT_USBDMA -#define MXC_INT_USBHOST MX21_INT_USBHOST -#define MXC_INT_USBFUNC MX21_INT_USBFUNC -#define MXC_INT_USBMNP MX21_INT_USBMNP -#define MXC_INT_USBCTRL MX21_INT_USBCTRL -#define MXC_INT_USBCTRL MX21_INT_USBCTRL -#define DMA_REQ_FIRI_RX MX21_DMA_REQ_FIRI_RX -#define DMA_REQ_BMI_TX MX21_DMA_REQ_BMI_TX -#define DMA_REQ_BMI_RX MX21_DMA_REQ_BMI_RX -#endif - #endif /* ifndef __MACH_MX21_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/mx27.h b/arch/arm/plat-mxc/include/mach/mx27.h index e817289..3116b3b 100644 --- a/arch/arm/plat-mxc/include/mach/mx27.h +++ b/arch/arm/plat-mxc/include/mach/mx27.h @@ -244,73 +244,4 @@ static inline void mx27_setup_weimcs(size_t cs, extern int mx27_revision(void); #endif -#ifdef IMX_NEEDS_DEPRECATED_SYMBOLS -/* these should go away */ -#define MSHC_BASE_ADDR MX27_MSHC_BASE_ADDR -#define GPT5_BASE_ADDR MX27_GPT5_BASE_ADDR -#define GPT4_BASE_ADDR MX27_GPT4_BASE_ADDR -#define UART5_BASE_ADDR MX27_UART5_BASE_ADDR -#define UART6_BASE_ADDR MX27_UART6_BASE_ADDR -#define I2C2_BASE_ADDR MX27_I2C2_BASE_ADDR -#define SDHC3_BASE_ADDR MX27_SDHC3_BASE_ADDR -#define GPT6_BASE_ADDR MX27_GPT6_BASE_ADDR -#define VPU_BASE_ADDR MX27_VPU_BASE_ADDR -#define OTG_BASE_ADDR MX27_OTG_BASE_ADDR -#define SAHARA_BASE_ADDR MX27_SAHARA_BASE_ADDR -#define IIM_BASE_ADDR MX27_IIM_BASE_ADDR -#define RTIC_BASE_ADDR MX27_RTIC_BASE_ADDR -#define FEC_BASE_ADDR MX27_FEC_BASE_ADDR -#define SCC_BASE_ADDR MX27_SCC_BASE_ADDR -#define ETB_BASE_ADDR MX27_ETB_BASE_ADDR -#define ETB_RAM_BASE_ADDR MX27_ETB_RAM_BASE_ADDR -#define ROMP_BASE_ADDR MX27_ROMP_BASE_ADDR -#define ATA_BASE_ADDR MX27_ATA_BASE_ADDR -#define SDRAM_BASE_ADDR MX27_SDRAM_BASE_ADDR -#define CSD1_BASE_ADDR MX27_CSD1_BASE_ADDR -#define CS0_BASE_ADDR MX27_CS0_BASE_ADDR -#define CS1_BASE_ADDR MX27_CS1_BASE_ADDR -#define CS2_BASE_ADDR MX27_CS2_BASE_ADDR -#define CS3_BASE_ADDR MX27_CS3_BASE_ADDR -#define CS4_BASE_ADDR MX27_CS4_BASE_ADDR -#define CS5_BASE_ADDR MX27_CS5_BASE_ADDR -#define X_MEMC_BASE_ADDR MX27_X_MEMC_BASE_ADDR -#define X_MEMC_SIZE MX27_X_MEMC_SIZE -#define NFC_BASE_ADDR MX27_NFC_BASE_ADDR -#define SDRAMC_BASE_ADDR MX27_SDRAMC_BASE_ADDR -#define WEIM_BASE_ADDR MX27_WEIM_BASE_ADDR -#define M3IF_BASE_ADDR MX27_M3IF_BASE_ADDR -#define PCMCIA_CTL_BASE_ADDR MX27_PCMCIA_CTL_BASE_ADDR -#define PCMCIA_MEM_BASE_ADDR MX27_PCMCIA_MEM_BASE_ADDR -#define IRAM_BASE_ADDR MX27_IRAM_BASE_ADDR -#define MXC_INT_I2C2 MX27_INT_I2C2 -#define MXC_INT_GPT6 MX27_INT_GPT6 -#define MXC_INT_GPT5 MX27_INT_GPT5 -#define MXC_INT_GPT4 MX27_INT_GPT4 -#define MXC_INT_RTIC MX27_INT_RTIC -#define MXC_INT_SDHC MX27_INT_SDHC -#define MXC_INT_SDHC3 MX27_INT_SDHC3 -#define MXC_INT_ATA MX27_INT_ATA -#define MXC_INT_UART6 MX27_INT_UART6 -#define MXC_INT_UART5 MX27_INT_UART5 -#define MXC_INT_FEC MX27_INT_FEC -#define MXC_INT_VPU MX27_INT_VPU -#define MXC_INT_USB1 MX27_INT_USB1 -#define MXC_INT_USB2 MX27_INT_USB2 -#define MXC_INT_USB3 MX27_INT_USB3 -#define MXC_INT_SCC_SMN MX27_INT_SCC_SMN -#define MXC_INT_SCC_SCM MX27_INT_SCC_SCM -#define MXC_INT_SAHARA MX27_INT_SAHARA -#define MXC_INT_IIM MX27_INT_IIM -#define MXC_INT_CCM MX27_INT_CCM -#define DMA_REQ_MSHC MX27_DMA_REQ_MSHC -#define DMA_REQ_ATA_TX MX27_DMA_REQ_ATA_TX -#define DMA_REQ_ATA_RCV MX27_DMA_REQ_ATA_RCV -#define DMA_REQ_UART5_TX MX27_DMA_REQ_UART5_TX -#define DMA_REQ_UART5_RX MX27_DMA_REQ_UART5_RX -#define DMA_REQ_UART6_TX MX27_DMA_REQ_UART6_TX -#define DMA_REQ_UART6_RX MX27_DMA_REQ_UART6_RX -#define DMA_REQ_SDHC3 MX27_DMA_REQ_SDHC3 -#define DMA_REQ_NFC MX27_DMA_REQ_NFC -#endif - #endif /* ifndef __MACH_MX27_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/mx2x.h b/arch/arm/plat-mxc/include/mach/mx2x.h index a056948..6d07839 100644 --- a/arch/arm/plat-mxc/include/mach/mx2x.h +++ b/arch/arm/plat-mxc/include/mach/mx2x.h @@ -141,116 +141,4 @@ #define MX2x_DMA_REQ_CSI_STAT 30 #define MX2x_DMA_REQ_CSI_RX 31 -#ifdef IMX_NEEDS_DEPRECATED_SYMBOLS -/* these should go away */ -#define AIPI_BASE_ADDR MX2x_AIPI_BASE_ADDR -#define AIPI_SIZE MX2x_AIPI_SIZE -#define DMA_BASE_ADDR MX2x_DMA_BASE_ADDR -#define WDOG_BASE_ADDR MX2x_WDOG_BASE_ADDR -#define GPT1_BASE_ADDR MX2x_GPT1_BASE_ADDR -#define GPT2_BASE_ADDR MX2x_GPT2_BASE_ADDR -#define GPT3_BASE_ADDR MX2x_GPT3_BASE_ADDR -#define PWM_BASE_ADDR MX2x_PWM_BASE_ADDR -#define RTC_BASE_ADDR MX2x_RTC_BASE_ADDR -#define KPP_BASE_ADDR MX2x_KPP_BASE_ADDR -#define OWIRE_BASE_ADDR MX2x_OWIRE_BASE_ADDR -#define UART1_BASE_ADDR MX2x_UART1_BASE_ADDR -#define UART2_BASE_ADDR MX2x_UART2_BASE_ADDR -#define UART3_BASE_ADDR MX2x_UART3_BASE_ADDR -#define UART4_BASE_ADDR MX2x_UART4_BASE_ADDR -#define CSPI1_BASE_ADDR MX2x_CSPI1_BASE_ADDR -#define CSPI2_BASE_ADDR MX2x_CSPI2_BASE_ADDR -#define SSI1_BASE_ADDR MX2x_SSI1_BASE_ADDR -#define SSI2_BASE_ADDR MX2x_SSI2_BASE_ADDR -#define I2C_BASE_ADDR MX2x_I2C_BASE_ADDR -#define SDHC1_BASE_ADDR MX2x_SDHC1_BASE_ADDR -#define SDHC2_BASE_ADDR MX2x_SDHC2_BASE_ADDR -#define GPIO_BASE_ADDR MX2x_GPIO_BASE_ADDR -#define AUDMUX_BASE_ADDR MX2x_AUDMUX_BASE_ADDR -#define CSPI3_BASE_ADDR MX2x_CSPI3_BASE_ADDR -#define LCDC_BASE_ADDR MX2x_LCDC_BASE_ADDR -#define SLCDC_BASE_ADDR MX2x_SLCDC_BASE_ADDR -#define USBOTG_BASE_ADDR MX2x_USBOTG_BASE_ADDR -#define EMMA_PP_BASE_ADDR MX2x_EMMA_PP_BASE_ADDR -#define EMMA_PRP_BASE_ADDR MX2x_EMMA_PRP_BASE_ADDR -#define CCM_BASE_ADDR MX2x_CCM_BASE_ADDR -#define SYSCTRL_BASE_ADDR MX2x_SYSCTRL_BASE_ADDR -#define JAM_BASE_ADDR MX2x_JAM_BASE_ADDR -#define MAX_BASE_ADDR MX2x_MAX_BASE_ADDR -#define AVIC_BASE_ADDR MX2x_AVIC_BASE_ADDR -#define SAHB1_BASE_ADDR MX2x_SAHB1_BASE_ADDR -#define SAHB1_SIZE MX2x_SAHB1_SIZE -#define CSI_BASE_ADDR MX2x_CSI_BASE_ADDR -#define MXC_INT_CSPI3 MX2x_INT_CSPI3 -#define MXC_INT_GPIO MX2x_INT_GPIO -#define MXC_INT_SDHC2 MX2x_INT_SDHC2 -#define MXC_INT_SDHC1 MX2x_INT_SDHC1 -#define MXC_INT_I2C MX2x_INT_I2C -#define MXC_INT_SSI2 MX2x_INT_SSI2 -#define MXC_INT_SSI1 MX2x_INT_SSI1 -#define MXC_INT_CSPI2 MX2x_INT_CSPI2 -#define MXC_INT_CSPI1 MX2x_INT_CSPI1 -#define MXC_INT_UART4 MX2x_INT_UART4 -#define MXC_INT_UART3 MX2x_INT_UART3 -#define MXC_INT_UART2 MX2x_INT_UART2 -#define MXC_INT_UART1 MX2x_INT_UART1 -#define MXC_INT_KPP MX2x_INT_KPP -#define MXC_INT_RTC MX2x_INT_RTC -#define MXC_INT_PWM MX2x_INT_PWM -#define MXC_INT_GPT3 MX2x_INT_GPT3 -#define MXC_INT_GPT2 MX2x_INT_GPT2 -#define MXC_INT_GPT1 MX2x_INT_GPT1 -#define MXC_INT_WDOG MX2x_INT_WDOG -#define MXC_INT_PCMCIA MX2x_INT_PCMCIA -#define MXC_INT_NANDFC MX2x_INT_NANDFC -#define MXC_INT_CSI MX2x_INT_CSI -#define MXC_INT_DMACH0 MX2x_INT_DMACH0 -#define MXC_INT_DMACH1 MX2x_INT_DMACH1 -#define MXC_INT_DMACH2 MX2x_INT_DMACH2 -#define MXC_INT_DMACH3 MX2x_INT_DMACH3 -#define MXC_INT_DMACH4 MX2x_INT_DMACH4 -#define MXC_INT_DMACH5 MX2x_INT_DMACH5 -#define MXC_INT_DMACH6 MX2x_INT_DMACH6 -#define MXC_INT_DMACH7 MX2x_INT_DMACH7 -#define MXC_INT_DMACH8 MX2x_INT_DMACH8 -#define MXC_INT_DMACH9 MX2x_INT_DMACH9 -#define MXC_INT_DMACH10 MX2x_INT_DMACH10 -#define MXC_INT_DMACH11 MX2x_INT_DMACH11 -#define MXC_INT_DMACH12 MX2x_INT_DMACH12 -#define MXC_INT_DMACH13 MX2x_INT_DMACH13 -#define MXC_INT_DMACH14 MX2x_INT_DMACH14 -#define MXC_INT_DMACH15 MX2x_INT_DMACH15 -#define MXC_INT_EMMAPRP MX2x_INT_EMMAPRP -#define MXC_INT_EMMAPP MX2x_INT_EMMAPP -#define MXC_INT_SLCDC MX2x_INT_SLCDC -#define MXC_INT_LCDC MX2x_INT_LCDC -#define DMA_REQ_CSPI3_RX MX2x_DMA_REQ_CSPI3_RX -#define DMA_REQ_CSPI3_TX MX2x_DMA_REQ_CSPI3_TX -#define DMA_REQ_EXT MX2x_DMA_REQ_EXT -#define DMA_REQ_SDHC2 MX2x_DMA_REQ_SDHC2 -#define DMA_REQ_SDHC1 MX2x_DMA_REQ_SDHC1 -#define DMA_REQ_SSI2_RX0 MX2x_DMA_REQ_SSI2_RX0 -#define DMA_REQ_SSI2_TX0 MX2x_DMA_REQ_SSI2_TX0 -#define DMA_REQ_SSI2_RX1 MX2x_DMA_REQ_SSI2_RX1 -#define DMA_REQ_SSI2_TX1 MX2x_DMA_REQ_SSI2_TX1 -#define DMA_REQ_SSI1_RX0 MX2x_DMA_REQ_SSI1_RX0 -#define DMA_REQ_SSI1_TX0 MX2x_DMA_REQ_SSI1_TX0 -#define DMA_REQ_SSI1_RX1 MX2x_DMA_REQ_SSI1_RX1 -#define DMA_REQ_SSI1_TX1 MX2x_DMA_REQ_SSI1_TX1 -#define DMA_REQ_CSPI2_RX MX2x_DMA_REQ_CSPI2_RX -#define DMA_REQ_CSPI2_TX MX2x_DMA_REQ_CSPI2_TX -#define DMA_REQ_CSPI1_RX MX2x_DMA_REQ_CSPI1_RX -#define DMA_REQ_CSPI1_TX MX2x_DMA_REQ_CSPI1_TX -#define DMA_REQ_UART4_RX MX2x_DMA_REQ_UART4_RX -#define DMA_REQ_UART4_TX MX2x_DMA_REQ_UART4_TX -#define DMA_REQ_UART3_RX MX2x_DMA_REQ_UART3_RX -#define DMA_REQ_UART3_TX MX2x_DMA_REQ_UART3_TX -#define DMA_REQ_UART2_RX MX2x_DMA_REQ_UART2_RX -#define DMA_REQ_UART2_TX MX2x_DMA_REQ_UART2_TX -#define DMA_REQ_UART1_RX MX2x_DMA_REQ_UART1_RX -#define DMA_REQ_UART1_TX MX2x_DMA_REQ_UART1_TX -#define DMA_REQ_CSI_STAT MX2x_DMA_REQ_CSI_STAT -#define DMA_REQ_CSI_RX MX2x_DMA_REQ_CSI_RX -#endif - #endif /* ifndef __MACH_MX2x_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/mx31.h b/arch/arm/plat-mxc/include/mach/mx31.h index 9ed9975..6d4b98f 100644 --- a/arch/arm/plat-mxc/include/mach/mx31.h +++ b/arch/arm/plat-mxc/include/mach/mx31.h @@ -215,36 +215,4 @@ static inline void mx31_setup_weimcs(size_t cs, #define MX31_SYSTEM_REV_MIN MX31_CHIP_REV_1_0 #define MX31_SYSTEM_REV_NUM 3 -#ifdef IMX_NEEDS_DEPRECATED_SYMBOLS -/* these should go away */ -#define ATA_BASE_ADDR MX31_ATA_BASE_ADDR -#define UART4_BASE_ADDR MX31_UART4_BASE_ADDR -#define UART5_BASE_ADDR MX31_UART5_BASE_ADDR -#define MMC_SDHC1_BASE_ADDR MX31_MMC_SDHC1_BASE_ADDR -#define MMC_SDHC2_BASE_ADDR MX31_MMC_SDHC2_BASE_ADDR -#define SIM1_BASE_ADDR MX31_SIM1_BASE_ADDR -#define IIM_BASE_ADDR MX31_IIM_BASE_ADDR -#define CSPI3_BASE_ADDR MX31_CSPI3_BASE_ADDR -#define FIRI_BASE_ADDR MX31_FIRI_BASE_ADDR -#define SCM_BASE_ADDR MX31_SCM_BASE_ADDR -#define SMN_BASE_ADDR MX31_SMN_BASE_ADDR -#define MPEG4_ENC_BASE_ADDR MX31_MPEG4_ENC_BASE_ADDR -#define MXC_INT_MPEG4_ENCODER MX31_INT_MPEG4_ENCODER -#define MXC_INT_FIRI MX31_INT_FIRI -#define MXC_INT_MBX MX31_INT_MBX -#define MXC_INT_CSPI3 MX31_INT_CSPI3 -#define MXC_INT_SIM2 MX31_INT_SIM2 -#define MXC_INT_SIM1 MX31_INT_SIM1 -#define MXC_INT_CCM_DVFS MX31_INT_CCM_DVFS -#define MXC_INT_USB1 MX31_INT_USB1 -#define MXC_INT_USB2 MX31_INT_USB2 -#define MXC_INT_USB3 MX31_INT_USB3 -#define MXC_INT_USB4 MX31_INT_USB4 -#define MXC_INT_MSHC2 MX31_INT_MSHC2 -#define MXC_INT_UART4 MX31_INT_UART4 -#define MXC_INT_UART5 MX31_INT_UART5 -#define MXC_INT_CCM MX31_INT_CCM -#define MXC_INT_PCMCIA MX31_INT_PCMCIA -#endif - #endif /* ifndef __MACH_MX31_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/mx35.h b/arch/arm/plat-mxc/include/mach/mx35.h index 3678ca3..9067225 100644 --- a/arch/arm/plat-mxc/include/mach/mx35.h +++ b/arch/arm/plat-mxc/include/mach/mx35.h @@ -183,20 +183,4 @@ #define MX35_SYSTEM_REV_MIN MX3x_CHIP_REV_1_0 #define MX35_SYSTEM_REV_NUM 3 -#ifdef IMX_NEEDS_DEPRECATED_SYMBOLS -/* these should go away */ -#define MXC_FEC_BASE_ADDR MX35_FEC_BASE_ADDR -#define MXC_INT_OWIRE MX35_INT_OWIRE -#define MXC_INT_GPU2D MX35_INT_GPU2D -#define MXC_INT_ASRC MX35_INT_ASRC -#define MXC_INT_USBHS MX35_INT_USBHS -#define MXC_INT_USBOTG MX35_INT_USBOTG -#define MXC_INT_ESAI MX35_INT_ESAI -#define MXC_INT_CAN1 MX35_INT_CAN1 -#define MXC_INT_CAN2 MX35_INT_CAN2 -#define MXC_INT_MLB MX35_INT_MLB -#define MXC_INT_SPDIF MX35_INT_SPDIF -#define MXC_INT_FEC MX35_INT_FEC -#endif - #endif /* ifndef __MACH_MX35_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/mx3x.h b/arch/arm/plat-mxc/include/mach/mx3x.h index 3d6cc45..8c7f34e 100644 --- a/arch/arm/plat-mxc/include/mach/mx3x.h +++ b/arch/arm/plat-mxc/include/mach/mx3x.h @@ -221,118 +221,4 @@ static inline int mx35_revision(void) } #endif -#ifdef IMX_NEEDS_DEPRECATED_SYMBOLS -/* these should go away */ -#define L2CC_BASE_ADDR MX3x_L2CC_BASE_ADDR -#define L2CC_SIZE MX3x_L2CC_SIZE -#define AIPS1_BASE_ADDR MX3x_AIPS1_BASE_ADDR -#define AIPS1_SIZE MX3x_AIPS1_SIZE -#define MAX_BASE_ADDR MX3x_MAX_BASE_ADDR -#define EVTMON_BASE_ADDR MX3x_EVTMON_BASE_ADDR -#define CLKCTL_BASE_ADDR MX3x_CLKCTL_BASE_ADDR -#define ETB_SLOT4_BASE_ADDR MX3x_ETB_SLOT4_BASE_ADDR -#define ETB_SLOT5_BASE_ADDR MX3x_ETB_SLOT5_BASE_ADDR -#define ECT_CTIO_BASE_ADDR MX3x_ECT_CTIO_BASE_ADDR -#define I2C_BASE_ADDR MX3x_I2C_BASE_ADDR -#define I2C3_BASE_ADDR MX3x_I2C3_BASE_ADDR -#define UART1_BASE_ADDR MX3x_UART1_BASE_ADDR -#define UART2_BASE_ADDR MX3x_UART2_BASE_ADDR -#define I2C2_BASE_ADDR MX3x_I2C2_BASE_ADDR -#define OWIRE_BASE_ADDR MX3x_OWIRE_BASE_ADDR -#define SSI1_BASE_ADDR MX3x_SSI1_BASE_ADDR -#define CSPI1_BASE_ADDR MX3x_CSPI1_BASE_ADDR -#define KPP_BASE_ADDR MX3x_KPP_BASE_ADDR -#define IOMUXC_BASE_ADDR MX3x_IOMUXC_BASE_ADDR -#define ECT_IP1_BASE_ADDR MX3x_ECT_IP1_BASE_ADDR -#define ECT_IP2_BASE_ADDR MX3x_ECT_IP2_BASE_ADDR -#define SPBA0_BASE_ADDR MX3x_SPBA0_BASE_ADDR -#define SPBA0_SIZE MX3x_SPBA0_SIZE -#define UART3_BASE_ADDR MX3x_UART3_BASE_ADDR -#define CSPI2_BASE_ADDR MX3x_CSPI2_BASE_ADDR -#define SSI2_BASE_ADDR MX3x_SSI2_BASE_ADDR -#define ATA_DMA_BASE_ADDR MX3x_ATA_DMA_BASE_ADDR -#define MSHC1_BASE_ADDR MX3x_MSHC1_BASE_ADDR -#define SPBA_CTRL_BASE_ADDR MX3x_SPBA_CTRL_BASE_ADDR -#define AIPS2_BASE_ADDR MX3x_AIPS2_BASE_ADDR -#define AIPS2_SIZE MX3x_AIPS2_SIZE -#define CCM_BASE_ADDR MX3x_CCM_BASE_ADDR -#define GPT1_BASE_ADDR MX3x_GPT1_BASE_ADDR -#define EPIT1_BASE_ADDR MX3x_EPIT1_BASE_ADDR -#define EPIT2_BASE_ADDR MX3x_EPIT2_BASE_ADDR -#define GPIO3_BASE_ADDR MX3x_GPIO3_BASE_ADDR -#define SCC_BASE_ADDR MX3x_SCC_BASE_ADDR -#define RNGA_BASE_ADDR MX3x_RNGA_BASE_ADDR -#define IPU_CTRL_BASE_ADDR MX3x_IPU_CTRL_BASE_ADDR -#define AUDMUX_BASE_ADDR MX3x_AUDMUX_BASE_ADDR -#define GPIO1_BASE_ADDR MX3x_GPIO1_BASE_ADDR -#define GPIO2_BASE_ADDR MX3x_GPIO2_BASE_ADDR -#define SDMA_BASE_ADDR MX3x_SDMA_BASE_ADDR -#define RTC_BASE_ADDR MX3x_RTC_BASE_ADDR -#define WDOG_BASE_ADDR MX3x_WDOG_BASE_ADDR -#define PWM_BASE_ADDR MX3x_PWM_BASE_ADDR -#define RTIC_BASE_ADDR MX3x_RTIC_BASE_ADDR -#define ROMP_BASE_ADDR MX3x_ROMP_BASE_ADDR -#define ROMP_SIZE MX3x_ROMP_SIZE -#define AVIC_BASE_ADDR MX3x_AVIC_BASE_ADDR -#define AVIC_SIZE MX3x_AVIC_SIZE -#define IPU_MEM_BASE_ADDR MX3x_IPU_MEM_BASE_ADDR -#define CSD0_BASE_ADDR MX3x_CSD0_BASE_ADDR -#define CSD1_BASE_ADDR MX3x_CSD1_BASE_ADDR -#define CS0_BASE_ADDR MX3x_CS0_BASE_ADDR -#define CS1_BASE_ADDR MX3x_CS1_BASE_ADDR -#define CS2_BASE_ADDR MX3x_CS2_BASE_ADDR -#define CS3_BASE_ADDR MX3x_CS3_BASE_ADDR -#define CS4_BASE_ADDR MX3x_CS4_BASE_ADDR -#define CS4_SIZE MX3x_CS4_SIZE -#define CS5_BASE_ADDR MX3x_CS5_BASE_ADDR -#define CS5_SIZE MX3x_CS5_SIZE -#define X_MEMC_BASE_ADDR MX3x_X_MEMC_BASE_ADDR -#define X_MEMC_SIZE MX3x_X_MEMC_SIZE -#define ESDCTL_BASE_ADDR MX3x_ESDCTL_BASE_ADDR -#define WEIM_BASE_ADDR MX3x_WEIM_BASE_ADDR -#define M3IF_BASE_ADDR MX3x_M3IF_BASE_ADDR -#define EMI_CTL_BASE_ADDR MX3x_EMI_CTL_BASE_ADDR -#define PCMCIA_CTL_BASE_ADDR MX3x_PCMCIA_CTL_BASE_ADDR -#define PCMCIA_MEM_BASE_ADDR MX3x_PCMCIA_MEM_BASE_ADDR -#define MXC_INT_I2C3 MX3x_INT_I2C3 -#define MXC_INT_I2C2 MX3x_INT_I2C2 -#define MXC_INT_RTIC MX3x_INT_RTIC -#define MXC_INT_I2C MX3x_INT_I2C -#define MXC_INT_CSPI2 MX3x_INT_CSPI2 -#define MXC_INT_CSPI1 MX3x_INT_CSPI1 -#define MXC_INT_ATA MX3x_INT_ATA -#define MXC_INT_UART3 MX3x_INT_UART3 -#define MXC_INT_IIM MX3x_INT_IIM -#define MXC_INT_RNGA MX3x_INT_RNGA -#define MXC_INT_EVTMON MX3x_INT_EVTMON -#define MXC_INT_KPP MX3x_INT_KPP -#define MXC_INT_RTC MX3x_INT_RTC -#define MXC_INT_PWM MX3x_INT_PWM -#define MXC_INT_EPIT2 MX3x_INT_EPIT2 -#define MXC_INT_EPIT1 MX3x_INT_EPIT1 -#define MXC_INT_GPT MX3x_INT_GPT -#define MXC_INT_POWER_FAIL MX3x_INT_POWER_FAIL -#define MXC_INT_UART2 MX3x_INT_UART2 -#define MXC_INT_NANDFC MX3x_INT_NANDFC -#define MXC_INT_SDMA MX3x_INT_SDMA -#define MXC_INT_MSHC1 MX3x_INT_MSHC1 -#define MXC_INT_IPU_ERR MX3x_INT_IPU_ERR -#define MXC_INT_IPU_SYN MX3x_INT_IPU_SYN -#define MXC_INT_UART1 MX3x_INT_UART1 -#define MXC_INT_ECT MX3x_INT_ECT -#define MXC_INT_SCC_SCM MX3x_INT_SCC_SCM -#define MXC_INT_SCC_SMN MX3x_INT_SCC_SMN -#define MXC_INT_GPIO2 MX3x_INT_GPIO2 -#define MXC_INT_GPIO1 MX3x_INT_GPIO1 -#define MXC_INT_WDOG MX3x_INT_WDOG -#define MXC_INT_GPIO3 MX3x_INT_GPIO3 -#define MXC_INT_EXT_POWER MX3x_INT_EXT_POWER -#define MXC_INT_EXT_TEMPER MX3x_INT_EXT_TEMPER -#define MXC_INT_EXT_SENSOR60 MX3x_INT_EXT_SENSOR60 -#define MXC_INT_EXT_SENSOR61 MX3x_INT_EXT_SENSOR61 -#define MXC_INT_EXT_WDOG MX3x_INT_EXT_WDOG -#define MXC_INT_EXT_TV MX3x_INT_EXT_TV -#define PROD_SIGNATURE MX3x_PROD_SIGNATURE -#endif - #endif /* ifndef __MACH_MX3x_H__ */ -- cgit v1.1 From ae71a5622253708aa08df231e6415fe7a1e96b10 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Fri, 29 Oct 2010 10:56:07 +0200 Subject: ARM: imx: dynamically allocate mxc_w1 devices MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Currently there is no platform data used in the driver. In case this changes NULL is passed unused to the soc specific functions. Signed-off-by: Uwe Kleine-König --- arch/arm/plat-mxc/devices/Kconfig | 3 ++ arch/arm/plat-mxc/devices/Makefile | 1 + arch/arm/plat-mxc/devices/platform-mxc_w1.c | 50 +++++++++++++++++++++++++ arch/arm/plat-mxc/include/mach/devices-common.h | 6 +++ 4 files changed, 60 insertions(+) create mode 100644 arch/arm/plat-mxc/devices/platform-mxc_w1.c (limited to 'arch/arm/plat-mxc') diff --git a/arch/arm/plat-mxc/devices/Kconfig b/arch/arm/plat-mxc/devices/Kconfig index 9aa6f3e..fb66467 100644 --- a/arch/arm/plat-mxc/devices/Kconfig +++ b/arch/arm/plat-mxc/devices/Kconfig @@ -25,5 +25,8 @@ config IMX_HAVE_PLATFORM_IMX_UART config IMX_HAVE_PLATFORM_MXC_NAND bool +config IMX_HAVE_PLATFORM_MXC_W1 + bool + config IMX_HAVE_PLATFORM_SPI_IMX bool diff --git a/arch/arm/plat-mxc/devices/Makefile b/arch/arm/plat-mxc/devices/Makefile index 45aefeb..1d7d392 100644 --- a/arch/arm/plat-mxc/devices/Makefile +++ b/arch/arm/plat-mxc/devices/Makefile @@ -7,4 +7,5 @@ obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_I2C) += platform-imx-i2c.o obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_SSI) += platform-imx-ssi.o obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_UART) += platform-imx-uart.o obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_NAND) += platform-mxc_nand.o +obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_W1) += platform-mxc_w1.o obj-$(CONFIG_IMX_HAVE_PLATFORM_SPI_IMX) += platform-spi_imx.o diff --git a/arch/arm/plat-mxc/devices/platform-mxc_w1.c b/arch/arm/plat-mxc/devices/platform-mxc_w1.c new file mode 100644 index 0000000..1355237 --- /dev/null +++ b/arch/arm/plat-mxc/devices/platform-mxc_w1.c @@ -0,0 +1,50 @@ +/* + * Copyright (C) 2010 Pengutronix + * Uwe Kleine-Koenig + * + * This program is free software; you can redistribute it and/or modify it under + * the terms of the GNU General Public License version 2 as published by the + * Free Software Foundation. + */ +#include +#include + +#define imx_mxc_w1_data_entry_single(soc) \ + { \ + .iobase = soc ## _OWIRE_BASE_ADDR, \ + } + +#ifdef CONFIG_SOC_IMX21 +const struct imx_mxc_w1_data imx21_mxc_w1_data __initconst = + imx_mxc_w1_data_entry_single(MX21); +#endif /* ifdef CONFIG_SOC_IMX21 */ + +#ifdef CONFIG_SOC_IMX27 +const struct imx_mxc_w1_data imx27_mxc_w1_data __initconst = + imx_mxc_w1_data_entry_single(MX27); +#endif /* ifdef CONFIG_SOC_IMX27 */ + +#ifdef CONFIG_ARCH_MX31 +const struct imx_mxc_w1_data imx31_mxc_w1_data __initconst = + imx_mxc_w1_data_entry_single(MX31); +#endif /* ifdef CONFIG_ARCH_MX31 */ + +#ifdef CONFIG_ARCH_MX35 +const struct imx_mxc_w1_data imx35_mxc_w1_data __initconst = + imx_mxc_w1_data_entry_single(MX35); +#endif /* ifdef CONFIG_ARCH_MX35 */ + +struct platform_device *__init imx_add_mxc_w1( + const struct imx_mxc_w1_data *data) +{ + struct resource res[] = { + { + .start = data->iobase, + .end = data->iobase + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + }; + + return imx_add_platform_device("mxc_w1", 0, + res, ARRAY_SIZE(res), NULL, 0); +} diff --git a/arch/arm/plat-mxc/include/mach/devices-common.h b/arch/arm/plat-mxc/include/mach/devices-common.h index 8c6896f..431e0ef 100644 --- a/arch/arm/plat-mxc/include/mach/devices-common.h +++ b/arch/arm/plat-mxc/include/mach/devices-common.h @@ -99,6 +99,12 @@ struct platform_device *__init imx_add_mxc_nand( const struct imx_mxc_nand_data *data, const struct mxc_nand_platform_data *pdata); +struct imx_mxc_w1_data { + resource_size_t iobase; +}; +struct platform_device *__init imx_add_mxc_w1( + const struct imx_mxc_w1_data *data); + #include struct imx_spi_imx_data { const char *devid; -- cgit v1.1 From e08300043ee4e2df10be551b76e126d6c02f26cc Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Tue, 2 Nov 2010 10:03:51 +0100 Subject: ARM: imx: dynamically allocate imx_udc device MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This is only available for mx1 machines with no in-tree user. Signed-off-by: Uwe Kleine-König --- arch/arm/plat-mxc/devices/Kconfig | 3 + arch/arm/plat-mxc/devices/Makefile | 1 + arch/arm/plat-mxc/devices/platform-imx_udc.c | 75 +++++++++++++++++++++++++ arch/arm/plat-mxc/include/mach/devices-common.h | 16 ++++++ arch/arm/plat-mxc/include/mach/mx1.h | 16 +++--- 5 files changed, 103 insertions(+), 8 deletions(-) create mode 100644 arch/arm/plat-mxc/devices/platform-imx_udc.c (limited to 'arch/arm/plat-mxc') diff --git a/arch/arm/plat-mxc/devices/Kconfig b/arch/arm/plat-mxc/devices/Kconfig index fb66467..2703f5a 100644 --- a/arch/arm/plat-mxc/devices/Kconfig +++ b/arch/arm/plat-mxc/devices/Kconfig @@ -22,6 +22,9 @@ config IMX_HAVE_PLATFORM_IMX_SSI config IMX_HAVE_PLATFORM_IMX_UART bool +config IMX_HAVE_PLATFORM_IMX_UDC + bool + config IMX_HAVE_PLATFORM_MXC_NAND bool diff --git a/arch/arm/plat-mxc/devices/Makefile b/arch/arm/plat-mxc/devices/Makefile index 1d7d392..7c3eaf1 100644 --- a/arch/arm/plat-mxc/devices/Makefile +++ b/arch/arm/plat-mxc/devices/Makefile @@ -6,6 +6,7 @@ obj-y += platform-imx-dma.o obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_I2C) += platform-imx-i2c.o obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_SSI) += platform-imx-ssi.o obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_UART) += platform-imx-uart.o +obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_UDC) += platform-imx_udc.o obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_NAND) += platform-mxc_nand.o obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_W1) += platform-mxc_w1.o obj-$(CONFIG_IMX_HAVE_PLATFORM_SPI_IMX) += platform-spi_imx.o diff --git a/arch/arm/plat-mxc/devices/platform-imx_udc.c b/arch/arm/plat-mxc/devices/platform-imx_udc.c new file mode 100644 index 0000000..6fd675d --- /dev/null +++ b/arch/arm/plat-mxc/devices/platform-imx_udc.c @@ -0,0 +1,75 @@ +/* + * Copyright (C) 2010 Pengutronix + * Uwe Kleine-Koenig + * + * This program is free software; you can redistribute it and/or modify it under + * the terms of the GNU General Public License version 2 as published by the + * Free Software Foundation. + */ +#include +#include + +#define imx_imx_udc_data_entry_single(soc, _size) \ + { \ + .iobase = soc ## _USBD_BASE_ADDR, \ + .iosize = _size, \ + .irq0 = soc ## _INT_USBD0, \ + .irq1 = soc ## _INT_USBD1, \ + .irq2 = soc ## _INT_USBD2, \ + .irq3 = soc ## _INT_USBD3, \ + .irq4 = soc ## _INT_USBD4, \ + .irq5 = soc ## _INT_USBD5, \ + .irq6 = soc ## _INT_USBD6, \ + } + +#define imx_imx_udc_data_entry(soc, _size) \ + [_id] = imx_imx_udc_data_entry_single(soc, _size) + +#ifdef CONFIG_SOC_IMX1 +const struct imx_imx_udc_data imx1_imx_udc_data __initconst = + imx_imx_udc_data_entry_single(MX1, SZ_4K); +#endif /* ifdef CONFIG_SOC_IMX1 */ + +struct platform_device *__init imx_add_imx_udc( + const struct imx_imx_udc_data *data, + const struct imxusb_platform_data *pdata) +{ + struct resource res[] = { + { + .start = data->iobase, + .end = data->iobase + data->iosize - 1, + .flags = IORESOURCE_MEM, + }, { + .start = data->irq0, + .end = data->irq0, + .flags = IORESOURCE_IRQ, + }, { + .start = data->irq1, + .end = data->irq1, + .flags = IORESOURCE_IRQ, + }, { + .start = data->irq2, + .end = data->irq2, + .flags = IORESOURCE_IRQ, + }, { + .start = data->irq3, + .end = data->irq3, + .flags = IORESOURCE_IRQ, + }, { + .start = data->irq4, + .end = data->irq4, + .flags = IORESOURCE_IRQ, + }, { + .start = data->irq5, + .end = data->irq5, + .flags = IORESOURCE_IRQ, + }, { + .start = data->irq6, + .end = data->irq6, + .flags = IORESOURCE_IRQ, + }, + }; + + return imx_add_platform_device("imx_udc", 0, + res, ARRAY_SIZE(res), pdata, sizeof(*pdata)); +} diff --git a/arch/arm/plat-mxc/include/mach/devices-common.h b/arch/arm/plat-mxc/include/mach/devices-common.h index 431e0ef..4eb45fa 100644 --- a/arch/arm/plat-mxc/include/mach/devices-common.h +++ b/arch/arm/plat-mxc/include/mach/devices-common.h @@ -82,6 +82,22 @@ struct platform_device *__init imx_add_imx_uart_1irq( const struct imx_imx_uart_1irq_data *data, const struct imxuart_platform_data *pdata); +#include +struct imx_imx_udc_data { + resource_size_t iobase; + resource_size_t iosize; + resource_size_t irq0; + resource_size_t irq1; + resource_size_t irq2; + resource_size_t irq3; + resource_size_t irq4; + resource_size_t irq5; + resource_size_t irq6; +}; +struct platform_device *__init imx_add_imx_udc( + const struct imx_imx_udc_data *data, + const struct imxusb_platform_data *pdata); + #include struct imx_mxc_nand_data { /* diff --git a/arch/arm/plat-mxc/include/mach/mx1.h b/arch/arm/plat-mxc/include/mach/mx1.h index b6771f4..2cd3fcd 100644 --- a/arch/arm/plat-mxc/include/mach/mx1.h +++ b/arch/arm/plat-mxc/include/mach/mx1.h @@ -114,13 +114,13 @@ #define MX1_SSI_RX_INT 44 #define MX1_SSI_RX_ERR_INT 45 #define MX1_TOUCH_INT 46 -#define MX1_USBD_INT0 47 -#define MX1_USBD_INT1 48 -#define MX1_USBD_INT2 49 -#define MX1_USBD_INT3 50 -#define MX1_USBD_INT4 51 -#define MX1_USBD_INT5 52 -#define MX1_USBD_INT6 53 +#define MX1_INT_USBD0 47 +#define MX1_INT_USBD1 48 +#define MX1_INT_USBD2 49 +#define MX1_INT_USBD3 50 +#define MX1_INT_USBD4 51 +#define MX1_INT_USBD5 52 +#define MX1_INT_USBD6 53 #define MX1_BTSYS_INT 55 #define MX1_BTTIM_INT 56 #define MX1_BTWUI_INT 57 @@ -163,6 +163,6 @@ * to not break drivers/usb/gadget/imx_udc. Should go * away after this driver uses the new name. */ -#define USBD_INT0 MX1_USBD_INT0 +#define USBD_INT0 MX1_INT_USBD0 #endif /* ifndef __MACH_MX1_H__ */ -- cgit v1.1 From 6332c1071811a1d588cfc93330d87a57a7460a1b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Tue, 2 Nov 2010 11:56:54 +0100 Subject: ARM: imx: allow specifying a dma mask when creating a platform device MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Uwe Kleine-König --- arch/arm/plat-mxc/devices.c | 23 +++++++++++++++++++++-- arch/arm/plat-mxc/include/mach/devices-common.h | 14 ++++++++++++-- 2 files changed, 33 insertions(+), 4 deletions(-) (limited to 'arch/arm/plat-mxc') diff --git a/arch/arm/plat-mxc/devices.c b/arch/arm/plat-mxc/devices.c index 735776d..e9bcefe 100644 --- a/arch/arm/plat-mxc/devices.c +++ b/arch/arm/plat-mxc/devices.c @@ -17,6 +17,7 @@ */ #include +#include #include #include #include @@ -36,9 +37,10 @@ int __init mxc_register_device(struct platform_device *pdev, void *data) return ret; } -struct platform_device *__init imx_add_platform_device(const char *name, int id, +struct platform_device *__init imx_add_platform_device_dmamask( + const char *name, int id, const struct resource *res, unsigned int num_resources, - const void *data, size_t size_data) + const void *data, size_t size_data, u64 dmamask) { int ret = -ENOMEM; struct platform_device *pdev; @@ -47,6 +49,23 @@ struct platform_device *__init imx_add_platform_device(const char *name, int id, if (!pdev) goto err; + if (dmamask) { + /* + * This memory isn't freed when the device is put, + * I don't have a nice idea for that though. Conceptually + * dma_mask in struct device should not be a pointer. + * See http://thread.gmane.org/gmane.linux.kernel.pci/9081 + */ + pdev->dev.dma_mask = + kmalloc(sizeof(*pdev->dev.dma_mask), GFP_KERNEL); + if (!pdev->dev.dma_mask) + /* ret is still -ENOMEM; */ + goto err; + + *pdev->dev.dma_mask = dmamask; + pdev->dev.coherent_dma_mask = dmamask; + } + if (res) { ret = platform_device_add_resources(pdev, res, num_resources); if (ret) diff --git a/arch/arm/plat-mxc/include/mach/devices-common.h b/arch/arm/plat-mxc/include/mach/devices-common.h index 4eb45fa..a5e97b8 100644 --- a/arch/arm/plat-mxc/include/mach/devices-common.h +++ b/arch/arm/plat-mxc/include/mach/devices-common.h @@ -10,9 +10,19 @@ #include #include -struct platform_device *imx_add_platform_device(const char *name, int id, +struct platform_device *imx_add_platform_device_dmamask( + const char *name, int id, const struct resource *res, unsigned int num_resources, - const void *data, size_t size_data); + const void *data, size_t size_data, u64 dmamask); + +static inline struct platform_device *imx_add_platform_device( + const char *name, int id, + const struct resource *res, unsigned int num_resources, + const void *data, size_t size_data) +{ + return imx_add_platform_device_dmamask( + name, id, res, num_resources, data, size_data, 0); +} #include struct imx_fec_data { -- cgit v1.1 From 9bb39b3f600101b09cbb35e0a0deb9d56c4fe67f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Tue, 2 Nov 2010 11:59:08 +0100 Subject: ARM: imx: dynamically allocate mx1-camera device MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Uwe Kleine-König --- arch/arm/plat-mxc/devices/Kconfig | 3 ++ arch/arm/plat-mxc/devices/Makefile | 1 + arch/arm/plat-mxc/devices/platform-mx1-camera.c | 42 +++++++++++++++++++++++++ arch/arm/plat-mxc/include/mach/devices-common.h | 10 ++++++ arch/arm/plat-mxc/include/mach/mx1.h | 2 +- 5 files changed, 57 insertions(+), 1 deletion(-) create mode 100644 arch/arm/plat-mxc/devices/platform-mx1-camera.c (limited to 'arch/arm/plat-mxc') diff --git a/arch/arm/plat-mxc/devices/Kconfig b/arch/arm/plat-mxc/devices/Kconfig index 2703f5a..61a3e25 100644 --- a/arch/arm/plat-mxc/devices/Kconfig +++ b/arch/arm/plat-mxc/devices/Kconfig @@ -25,6 +25,9 @@ config IMX_HAVE_PLATFORM_IMX_UART config IMX_HAVE_PLATFORM_IMX_UDC bool +config IMX_HAVE_PLATFORM_MX1_CAMERA + bool + config IMX_HAVE_PLATFORM_MXC_NAND bool diff --git a/arch/arm/plat-mxc/devices/Makefile b/arch/arm/plat-mxc/devices/Makefile index 7c3eaf1..86b47f2 100644 --- a/arch/arm/plat-mxc/devices/Makefile +++ b/arch/arm/plat-mxc/devices/Makefile @@ -7,6 +7,7 @@ obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_I2C) += platform-imx-i2c.o obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_SSI) += platform-imx-ssi.o obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_UART) += platform-imx-uart.o obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_UDC) += platform-imx_udc.o +obj-$(CONFIG_IMX_HAVE_PLATFORM_MX1_CAMERA) += platform-mx1-camera.o obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_NAND) += platform-mxc_nand.o obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_W1) += platform-mxc_w1.o obj-$(CONFIG_IMX_HAVE_PLATFORM_SPI_IMX) += platform-spi_imx.o diff --git a/arch/arm/plat-mxc/devices/platform-mx1-camera.c b/arch/arm/plat-mxc/devices/platform-mx1-camera.c new file mode 100644 index 0000000..edcc581 --- /dev/null +++ b/arch/arm/plat-mxc/devices/platform-mx1-camera.c @@ -0,0 +1,42 @@ +/* + * Copyright (C) 2010 Pengutronix + * Uwe Kleine-Koenig + * + * This program is free software; you can redistribute it and/or modify it under + * the terms of the GNU General Public License version 2 as published by the + * Free Software Foundation. + */ +#include +#include + +#define imx_mx1_camera_data_entry_single(soc, _size) \ + { \ + .iobase = soc ## _CSI ## _BASE_ADDR, \ + .iosize = _size, \ + .irq = soc ## _INT_CSI, \ + } + +#ifdef CONFIG_SOC_IMX1 +const struct imx_mx1_camera_data imx1_mx1_camera_data __initconst = + imx_mx1_camera_data_entry_single(MX1, 10); +#endif /* ifdef CONFIG_SOC_IMX1 */ + +struct platform_device *__init imx_add_mx1_camera( + const struct imx_mx1_camera_data *data, + const struct mx1_camera_pdata *pdata) +{ + struct resource res[] = { + { + .start = data->iobase, + .end = data->iobase + data->iosize - 1, + .flags = IORESOURCE_MEM, + }, { + .start = data->irq, + .end = data->irq, + .flags = IORESOURCE_IRQ, + }, + }; + return imx_add_platform_device_dmamask("mx1-camera", 0, + res, ARRAY_SIZE(res), + pdata, sizeof(*pdata), DMA_BIT_MASK(32)); +} diff --git a/arch/arm/plat-mxc/include/mach/devices-common.h b/arch/arm/plat-mxc/include/mach/devices-common.h index a5e97b8..ab0500a 100644 --- a/arch/arm/plat-mxc/include/mach/devices-common.h +++ b/arch/arm/plat-mxc/include/mach/devices-common.h @@ -108,6 +108,16 @@ struct platform_device *__init imx_add_imx_udc( const struct imx_imx_udc_data *data, const struct imxusb_platform_data *pdata); +#include +struct imx_mx1_camera_data { + resource_size_t iobase; + resource_size_t iosize; + resource_size_t irq; +}; +struct platform_device *__init imx_add_mx1_camera( + const struct imx_mx1_camera_data *data, + const struct mx1_camera_pdata *pdata); + #include struct imx_mxc_nand_data { /* diff --git a/arch/arm/plat-mxc/include/mach/mx1.h b/arch/arm/plat-mxc/include/mach/mx1.h index 2cd3fcd..f1e336e 100644 --- a/arch/arm/plat-mxc/include/mach/mx1.h +++ b/arch/arm/plat-mxc/include/mach/mx1.h @@ -77,7 +77,7 @@ /* fixed interrput numbers */ #define MX1_INT_SOFTINT 0 -#define MX1_CSI_INT 6 +#define MX1_INT_CSI 6 #define MX1_DSPA_MAC_INT 7 #define MX1_DSPA_INT 8 #define MX1_COMP_INT 9 -- cgit v1.1 From 3bde75b5370bd69fd7f07a8e254bef05b1b5b219 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Tue, 2 Nov 2010 16:42:27 +0100 Subject: ARM: imx/gpio: remove some useless casts MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Uwe Kleine-König --- arch/arm/plat-mxc/gpio.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm/plat-mxc') diff --git a/arch/arm/plat-mxc/gpio.c b/arch/arm/plat-mxc/gpio.c index 9c3e362..a43d9cc 100644 --- a/arch/arm/plat-mxc/gpio.c +++ b/arch/arm/plat-mxc/gpio.c @@ -175,7 +175,7 @@ static void mxc_gpio_irq_handler(struct mxc_gpio_port *port, u32 irq_stat) static void mx3_gpio_irq_handler(u32 irq, struct irq_desc *desc) { u32 irq_stat; - struct mxc_gpio_port *port = (struct mxc_gpio_port *)get_irq_data(irq); + struct mxc_gpio_port *port = get_irq_data(irq); irq_stat = __raw_readl(port->base + GPIO_ISR) & __raw_readl(port->base + GPIO_IMR); @@ -188,7 +188,7 @@ static void mx2_gpio_irq_handler(u32 irq, struct irq_desc *desc) { int i; u32 irq_msk, irq_stat; - struct mxc_gpio_port *port = (struct mxc_gpio_port *)get_irq_data(irq); + struct mxc_gpio_port *port = get_irq_data(irq); /* walk through all interrupt status registers */ for (i = 0; i < gpio_table_size; i++) { -- cgit v1.1 From b2997cb12b302ee6d233808e32214d00afdcf128 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Tue, 2 Nov 2010 17:50:55 +0100 Subject: ARM: imx: dynamically allocate mx2-camera device MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Uwe Kleine-König --- arch/arm/plat-mxc/devices/Kconfig | 3 ++ arch/arm/plat-mxc/devices/Makefile | 1 + arch/arm/plat-mxc/devices/platform-mx2-camera.c | 53 +++++++++++++++++++++++++ arch/arm/plat-mxc/include/mach/devices-common.h | 13 ++++++ arch/arm/plat-mxc/include/mach/mx27.h | 4 +- 5 files changed, 72 insertions(+), 2 deletions(-) create mode 100644 arch/arm/plat-mxc/devices/platform-mx2-camera.c (limited to 'arch/arm/plat-mxc') diff --git a/arch/arm/plat-mxc/devices/Kconfig b/arch/arm/plat-mxc/devices/Kconfig index 61a3e25..37d7e00 100644 --- a/arch/arm/plat-mxc/devices/Kconfig +++ b/arch/arm/plat-mxc/devices/Kconfig @@ -28,6 +28,9 @@ config IMX_HAVE_PLATFORM_IMX_UDC config IMX_HAVE_PLATFORM_MX1_CAMERA bool +config IMX_HAVE_PLATFORM_MX2_CAMERA + bool + config IMX_HAVE_PLATFORM_MXC_NAND bool diff --git a/arch/arm/plat-mxc/devices/Makefile b/arch/arm/plat-mxc/devices/Makefile index 86b47f2..88392fc 100644 --- a/arch/arm/plat-mxc/devices/Makefile +++ b/arch/arm/plat-mxc/devices/Makefile @@ -8,6 +8,7 @@ obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_SSI) += platform-imx-ssi.o obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_UART) += platform-imx-uart.o obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_UDC) += platform-imx_udc.o obj-$(CONFIG_IMX_HAVE_PLATFORM_MX1_CAMERA) += platform-mx1-camera.o +obj-$(CONFIG_IMX_HAVE_PLATFORM_MX2_CAMERA) += platform-mx2-camera.o obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_NAND) += platform-mxc_nand.o obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_W1) += platform-mxc_w1.o obj-$(CONFIG_IMX_HAVE_PLATFORM_SPI_IMX) += platform-spi_imx.o diff --git a/arch/arm/plat-mxc/devices/platform-mx2-camera.c b/arch/arm/plat-mxc/devices/platform-mx2-camera.c new file mode 100644 index 0000000..a18c803 --- /dev/null +++ b/arch/arm/plat-mxc/devices/platform-mx2-camera.c @@ -0,0 +1,53 @@ +/* + * Copyright (C) 2010 Pengutronix + * Uwe Kleine-Koenig + * + * This program is free software; you can redistribute it and/or modify it under + * the terms of the GNU General Public License version 2 as published by the + * Free Software Foundation. + */ +#include +#include + +#define imx_mx2_camera_data_entry_single(soc) \ + { \ + .iobasecsi = soc ## _CSI_BASE_ADDR, \ + .iosizecsi = SZ_32, \ + .irqcsi = soc ## _INT_CSI, \ + .iobaseemmaprp = soc ## _EMMAPRP_BASE_ADDR, \ + .iosizeemmaprp = SZ_32, \ + .irqemmaprp = soc ## _INT_EMMAPRP, \ + } + +#ifdef CONFIG_SOC_IMX27 +const struct imx_mx2_camera_data imx27_mx2_camera_data __initconst = + imx_mx2_camera_data_entry_single(MX27); +#endif /* ifdef CONFIG_SOC_IMX27 */ + +struct platform_device *__init imx_add_mx2_camera( + const struct imx_mx2_camera_data *data, + const struct mx2_camera_platform_data *pdata) +{ + struct resource res[] = { + { + .start = data->iobasecsi, + .end = data->iobasecsi + data->iosizecsi - 1, + .flags = IORESOURCE_MEM, + }, { + .start = data->iobaseemmaprp, + .end = data->iobaseemmaprp + data->iosizeemmaprp - 1, + .flags = IORESOURCE_MEM, + }, { + .start = data->irqcsi, + .end = data->irqcsi, + .flags = IORESOURCE_IRQ, + }, { + .start = data->irqemmaprp, + .end = data->irqemmaprp, + .flags = IORESOURCE_IRQ, + }, + }; + return imx_add_platform_device_dmamask("mx2-camera", 0, + res, ARRAY_SIZE(res), + pdata, sizeof(*pdata), DMA_BIT_MASK(32)); +} diff --git a/arch/arm/plat-mxc/include/mach/devices-common.h b/arch/arm/plat-mxc/include/mach/devices-common.h index ab0500a..e31fc50 100644 --- a/arch/arm/plat-mxc/include/mach/devices-common.h +++ b/arch/arm/plat-mxc/include/mach/devices-common.h @@ -118,6 +118,19 @@ struct platform_device *__init imx_add_mx1_camera( const struct imx_mx1_camera_data *data, const struct mx1_camera_pdata *pdata); +#include +struct imx_mx2_camera_data { + resource_size_t iobasecsi; + resource_size_t iosizecsi; + resource_size_t irqcsi; + resource_size_t iobaseemmaprp; + resource_size_t iosizeemmaprp; + resource_size_t irqemmaprp; +}; +struct platform_device *__init imx_add_mx2_camera( + const struct imx_mx2_camera_data *data, + const struct mx2_camera_platform_data *pdata); + #include struct imx_mxc_nand_data { /* diff --git a/arch/arm/plat-mxc/include/mach/mx27.h b/arch/arm/plat-mxc/include/mach/mx27.h index 3116b3b..2734d24 100644 --- a/arch/arm/plat-mxc/include/mach/mx27.h +++ b/arch/arm/plat-mxc/include/mach/mx27.h @@ -67,8 +67,8 @@ #define MX27_USBOTG_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x24000) #define MX27_OTG_BASE_ADDR MX27_USBOTG_BASE_ADDR #define MX27_SAHARA_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x25000) -#define MX27_EMMA_PP_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x26000) -#define MX27_EMMA_PRP_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x26400) +#define MX27_EMMAPP_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x26000) +#define MX27_EMMAPRP_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x26400) #define MX27_CCM_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x27000) #define MX27_SYSCTRL_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x27800) #define MX27_IIM_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x28000) -- cgit v1.1 From e0a1961df8ad898b661cf0adcf3519254f135a44 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Thu, 4 Nov 2010 10:09:10 +0100 Subject: ARM: imx: dynamically allocate imx2-wdt devices MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Currently there is no platform data used in the driver. In case this changes and for consistency NULL is passed unused to the soc specific functions. Signed-off-by: Uwe Kleine-König --- arch/arm/plat-mxc/devices/Kconfig | 3 ++ arch/arm/plat-mxc/devices/Makefile | 1 + arch/arm/plat-mxc/devices/platform-imx2-wdt.c | 40 +++++++++++++++++++++++++ arch/arm/plat-mxc/include/mach/devices-common.h | 6 ++++ 4 files changed, 50 insertions(+) create mode 100644 arch/arm/plat-mxc/devices/platform-imx2-wdt.c (limited to 'arch/arm/plat-mxc') diff --git a/arch/arm/plat-mxc/devices/Kconfig b/arch/arm/plat-mxc/devices/Kconfig index 37d7e00..01b0d0c 100644 --- a/arch/arm/plat-mxc/devices/Kconfig +++ b/arch/arm/plat-mxc/devices/Kconfig @@ -13,6 +13,9 @@ config IMX_HAVE_PLATFORM_GPIO_KEYS bool default y if ARCH_MX51 +config IMX_HAVE_PLATFORM_IMX2_WDT + bool + config IMX_HAVE_PLATFORM_IMX_I2C bool diff --git a/arch/arm/plat-mxc/devices/Makefile b/arch/arm/plat-mxc/devices/Makefile index 88392fc..224f665 100644 --- a/arch/arm/plat-mxc/devices/Makefile +++ b/arch/arm/plat-mxc/devices/Makefile @@ -2,6 +2,7 @@ obj-$(CONFIG_IMX_HAVE_PLATFORM_ESDHC) += platform-esdhc.o obj-$(CONFIG_IMX_HAVE_PLATFORM_FEC) += platform-fec.o obj-$(CONFIG_IMX_HAVE_PLATFORM_FLEXCAN) += platform-flexcan.o obj-$(CONFIG_IMX_HAVE_PLATFORM_GPIO_KEYS) += platform-gpio_keys.o +obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX2_WDT) += platform-imx2-wdt.o obj-y += platform-imx-dma.o obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_I2C) += platform-imx-i2c.o obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_SSI) += platform-imx-ssi.o diff --git a/arch/arm/plat-mxc/devices/platform-imx2-wdt.c b/arch/arm/plat-mxc/devices/platform-imx2-wdt.c new file mode 100644 index 0000000..86eb7f1 --- /dev/null +++ b/arch/arm/plat-mxc/devices/platform-imx2-wdt.c @@ -0,0 +1,40 @@ +/* + * Copyright (C) 2010 Pengutronix + * Uwe Kleine-Koenig + * + * This program is free software; you can redistribute it and/or modify it under + * the terms of the GNU General Public License version 2 as published by the + * Free Software Foundation. + */ +#include +#include +#include + +#define imx_imx2_wdt_data_entry_single(soc) \ + { \ + .iobase = soc ## _WDOG_BASE_ADDR, \ + } + +#ifdef CONFIG_SOC_IMX21 +const struct imx_imx2_wdt_data imx21_imx2_wdt_data __initconst = + imx_imx2_wdt_data_entry_single(MX21); +#endif /* ifdef CONFIG_SOC_IMX21 */ + +#ifdef CONFIG_SOC_IMX27 +const struct imx_imx2_wdt_data imx27_imx2_wdt_data __initconst = + imx_imx2_wdt_data_entry_single(MX27); +#endif /* ifdef CONFIG_SOC_IMX27 */ + +struct platform_device *__init imx_add_imx2_wdt( + const struct imx_imx2_wdt_data *data) +{ + struct resource res[] = { + { + .start = data->iobase, + .end = data->iobase + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + }; + return imx_add_platform_device("imx2-wdt", 0, + res, ARRAY_SIZE(res), NULL, 0); +} diff --git a/arch/arm/plat-mxc/include/mach/devices-common.h b/arch/arm/plat-mxc/include/mach/devices-common.h index e31fc50..a0ac8454 100644 --- a/arch/arm/plat-mxc/include/mach/devices-common.h +++ b/arch/arm/plat-mxc/include/mach/devices-common.h @@ -43,6 +43,12 @@ struct platform_device *__init imx_add_flexcan(int id, struct platform_device *__init imx_add_gpio_keys( const struct gpio_keys_platform_data *pdata); +struct imx_imx2_wdt_data { + resource_size_t iobase; +}; +struct platform_device *__init imx_add_imx2_wdt( + const struct imx_imx2_wdt_data *data); + #include struct imx_imx_i2c_data { int id; -- cgit v1.1 From fc40d0191943fa995f5359b5c23aa7c3dea69d7b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Thu, 4 Nov 2010 12:02:35 +0100 Subject: ARM: imx: change the way flexcan devices are registered MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Group soc specific data in a global struct instead of repeating it for each call to imxXX_add_flexcanX. The structs holding the actual data are placed in .init.constdata and so don't do much harm. Compared to the previous approach this reduces code size to call imx_add_flexcan. Signed-off-by: Uwe Kleine-König --- arch/arm/plat-mxc/devices/platform-flexcan.c | 48 +++++++++++++++++++------ arch/arm/plat-mxc/include/mach/devices-common.h | 11 ++++-- 2 files changed, 46 insertions(+), 13 deletions(-) (limited to 'arch/arm/plat-mxc') diff --git a/arch/arm/plat-mxc/devices/platform-flexcan.c b/arch/arm/plat-mxc/devices/platform-flexcan.c index 5e97a01..5189017 100644 --- a/arch/arm/plat-mxc/devices/platform-flexcan.c +++ b/arch/arm/plat-mxc/devices/platform-flexcan.c @@ -5,26 +5,54 @@ * the terms of the GNU General Public License version 2 as published by the * Free Software Foundation. */ - +#include #include -struct platform_device *__init imx_add_flexcan(int id, - resource_size_t iobase, resource_size_t iosize, - resource_size_t irq, +#define imx_flexcan_data_entry_single(soc, _id, _hwid, _size) \ + { \ + .id = _id, \ + .iobase = soc ## _CAN ## _hwid ## _BASE_ADDR, \ + .iosize = _size, \ + .irq = soc ## _INT_CAN ## _hwid, \ + } + +#define imx_flexcan_data_entry(soc, _id, _hwid, _size) \ + [_id] = imx_flexcan_data_entry_single(soc, _id, _hwid, _size) + +#ifdef CONFIG_ARCH_MX25 +const struct imx_flexcan_data imx25_flexcan_data[] __initconst = { +#define imx25_flexcan_data_entry(_id, _hwid) \ + imx_flexcan_data_entry(MX25, _id, _hwid, SZ_16K) + imx25_flexcan_data_entry(0, 1), + imx25_flexcan_data_entry(1, 2), +}; +#endif /* ifdef CONFIG_ARCH_MX25 */ + +#ifdef CONFIG_ARCH_MX35 +const struct imx_flexcan_data imx35_flexcan_data[] __initconst = { +#define imx35_flexcan_data_entry(_id, _hwid) \ + imx_flexcan_data_entry(MX35, _id, _hwid, SZ_16K) + imx35_flexcan_data_entry(0, 1), + imx35_flexcan_data_entry(1, 2), +}; +#endif /* ifdef CONFIG_ARCH_MX35 */ + +struct platform_device *__init imx_add_flexcan( + const struct imx_flexcan_data *data, const struct flexcan_platform_data *pdata) { struct resource res[] = { { - .start = iobase, - .end = iobase + iosize - 1, + .start = data->iobase, + .end = data->iobase + data->iosize - 1, .flags = IORESOURCE_MEM, }, { - .start = irq, - .end = irq, + .start = data->irq, + .end = data->irq, .flags = IORESOURCE_IRQ, }, }; - return imx_add_platform_device("flexcan", id, res, ARRAY_SIZE(res), - pdata, sizeof(*pdata)); + return imx_add_platform_device("flexcan", data->id, + res, ARRAY_SIZE(res), pdata, sizeof(*pdata)); } diff --git a/arch/arm/plat-mxc/include/mach/devices-common.h b/arch/arm/plat-mxc/include/mach/devices-common.h index a0ac8454..830369e 100644 --- a/arch/arm/plat-mxc/include/mach/devices-common.h +++ b/arch/arm/plat-mxc/include/mach/devices-common.h @@ -34,9 +34,14 @@ struct platform_device *__init imx_add_fec( const struct fec_platform_data *pdata); #include -struct platform_device *__init imx_add_flexcan(int id, - resource_size_t iobase, resource_size_t iosize, - resource_size_t irq, +struct imx_flexcan_data { + int id; + resource_size_t iobase; + resource_size_t iosize; + resource_size_t irq; +}; +struct platform_device *__init imx_add_flexcan( + const struct imx_flexcan_data *data, const struct flexcan_platform_data *pdata); #include -- cgit v1.1 From ad851bffba6afd6468f96a6180cc4a14e9ebee38 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Thu, 4 Nov 2010 17:07:48 +0100 Subject: ARM: imx: dynamically register imx-fb devices MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Uwe Kleine-König --- arch/arm/plat-mxc/devices/Kconfig | 3 ++ arch/arm/plat-mxc/devices/Makefile | 1 + arch/arm/plat-mxc/devices/platform-imx-fb.c | 46 +++++++++++++++++++++++++ arch/arm/plat-mxc/include/mach/devices-common.h | 9 +++++ arch/arm/plat-mxc/include/mach/imxfb.h | 3 ++ 5 files changed, 62 insertions(+) create mode 100644 arch/arm/plat-mxc/devices/platform-imx-fb.c (limited to 'arch/arm/plat-mxc') diff --git a/arch/arm/plat-mxc/devices/Kconfig b/arch/arm/plat-mxc/devices/Kconfig index 01b0d0c..2542371 100644 --- a/arch/arm/plat-mxc/devices/Kconfig +++ b/arch/arm/plat-mxc/devices/Kconfig @@ -16,6 +16,9 @@ config IMX_HAVE_PLATFORM_GPIO_KEYS config IMX_HAVE_PLATFORM_IMX2_WDT bool +config IMX_HAVE_PLATFORM_IMX_FB + bool + config IMX_HAVE_PLATFORM_IMX_I2C bool diff --git a/arch/arm/plat-mxc/devices/Makefile b/arch/arm/plat-mxc/devices/Makefile index 224f665..d3f845e 100644 --- a/arch/arm/plat-mxc/devices/Makefile +++ b/arch/arm/plat-mxc/devices/Makefile @@ -4,6 +4,7 @@ obj-$(CONFIG_IMX_HAVE_PLATFORM_FLEXCAN) += platform-flexcan.o obj-$(CONFIG_IMX_HAVE_PLATFORM_GPIO_KEYS) += platform-gpio_keys.o obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX2_WDT) += platform-imx2-wdt.o obj-y += platform-imx-dma.o +obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_FB) += platform-imx-fb.o obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_I2C) += platform-imx-i2c.o obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_SSI) += platform-imx-ssi.o obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_UART) += platform-imx-uart.o diff --git a/arch/arm/plat-mxc/devices/platform-imx-fb.c b/arch/arm/plat-mxc/devices/platform-imx-fb.c new file mode 100644 index 0000000..42ed3be --- /dev/null +++ b/arch/arm/plat-mxc/devices/platform-imx-fb.c @@ -0,0 +1,46 @@ +/* + * Copyright (C) 2010 Pengutronix + * Uwe Kleine-Koenig + * + * This program is free software; you can redistribute it and/or modify it under + * the terms of the GNU General Public License version 2 as published by the + * Free Software Foundation. + */ +#include +#include + +#define imx_imx_fb_data_entry_single(soc) \ + { \ + .iobase = soc ## _LCDC_BASE_ADDR, \ + .irq = soc ## _INT_LCDC, \ + } + +#ifdef CONFIG_SOC_IMX21 +const struct imx_imx_fb_data imx21_imx_fb_data __initconst = + imx_imx_fb_data_entry_single(MX21); +#endif /* ifdef CONFIG_SOC_IMX21 */ + +#ifdef CONFIG_SOC_IMX27 +const struct imx_imx_fb_data imx27_imx_fb_data __initconst = + imx_imx_fb_data_entry_single(MX27); +#endif /* ifdef CONFIG_SOC_IMX27 */ + +struct platform_device *__init imx_add_imx_fb( + const struct imx_imx_fb_data *data, + const struct imx_fb_platform_data *pdata) +{ + struct resource res[] = { + { + .start = data->iobase, + .end = data->iobase + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, { + .start = data->irq, + .end = data->irq, + .flags = IORESOURCE_IRQ, + }, + }; + return imx_add_platform_device_dmamask("imx-fb", 0, + res, ARRAY_SIZE(res), + pdata, sizeof(*pdata), DMA_BIT_MASK(32)); +} diff --git a/arch/arm/plat-mxc/include/mach/devices-common.h b/arch/arm/plat-mxc/include/mach/devices-common.h index 830369e..b1d7656 100644 --- a/arch/arm/plat-mxc/include/mach/devices-common.h +++ b/arch/arm/plat-mxc/include/mach/devices-common.h @@ -54,6 +54,15 @@ struct imx_imx2_wdt_data { struct platform_device *__init imx_add_imx2_wdt( const struct imx_imx2_wdt_data *data); +#include +struct imx_imx_fb_data { + resource_size_t iobase; + resource_size_t irq; +}; +struct platform_device *__init imx_add_imx_fb( + const struct imx_imx_fb_data *data, + const struct imx_fb_platform_data *pdata); + #include struct imx_imx_i2c_data { int id; diff --git a/arch/arm/plat-mxc/include/mach/imxfb.h b/arch/arm/plat-mxc/include/mach/imxfb.h index 5263506..9de8f06 100644 --- a/arch/arm/plat-mxc/include/mach/imxfb.h +++ b/arch/arm/plat-mxc/include/mach/imxfb.h @@ -1,6 +1,8 @@ /* * This structure describes the machine which we are running on. */ +#ifndef __MACH_IMXFB_H__ +#define __MACH_IMXFB_H__ #include @@ -79,3 +81,4 @@ struct imx_fb_platform_data { }; void set_imx_fb_info(struct imx_fb_platform_data *); +#endif /* ifndef __MACH_IMXFB_H__ */ -- cgit v1.1 From bf182bcc6e726cce2f02b699bd0fba787734554f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Fri, 5 Nov 2010 15:01:16 +0100 Subject: ARM: imx: dynamically allocate mxc_pwm devices MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Uwe Kleine-König --- arch/arm/plat-mxc/devices/Kconfig | 3 ++ arch/arm/plat-mxc/devices/Makefile | 1 + arch/arm/plat-mxc/devices/platform-mxc_pwm.c | 45 +++++++++++++++++++++++++ arch/arm/plat-mxc/include/mach/devices-common.h | 7 ++++ 4 files changed, 56 insertions(+) create mode 100644 arch/arm/plat-mxc/devices/platform-mxc_pwm.c (limited to 'arch/arm/plat-mxc') diff --git a/arch/arm/plat-mxc/devices/Kconfig b/arch/arm/plat-mxc/devices/Kconfig index 2542371..2ded17b 100644 --- a/arch/arm/plat-mxc/devices/Kconfig +++ b/arch/arm/plat-mxc/devices/Kconfig @@ -40,6 +40,9 @@ config IMX_HAVE_PLATFORM_MX2_CAMERA config IMX_HAVE_PLATFORM_MXC_NAND bool +config IMX_HAVE_PLATFORM_MXC_PWM + bool + config IMX_HAVE_PLATFORM_MXC_W1 bool diff --git a/arch/arm/plat-mxc/devices/Makefile b/arch/arm/plat-mxc/devices/Makefile index d3f845e..8ecd974 100644 --- a/arch/arm/plat-mxc/devices/Makefile +++ b/arch/arm/plat-mxc/devices/Makefile @@ -12,5 +12,6 @@ obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_UDC) += platform-imx_udc.o obj-$(CONFIG_IMX_HAVE_PLATFORM_MX1_CAMERA) += platform-mx1-camera.o obj-$(CONFIG_IMX_HAVE_PLATFORM_MX2_CAMERA) += platform-mx2-camera.o obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_NAND) += platform-mxc_nand.o +obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_PWM) += platform-mxc_pwm.o obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_W1) += platform-mxc_w1.o obj-$(CONFIG_IMX_HAVE_PLATFORM_SPI_IMX) += platform-spi_imx.o diff --git a/arch/arm/plat-mxc/devices/platform-mxc_pwm.c b/arch/arm/plat-mxc/devices/platform-mxc_pwm.c new file mode 100644 index 0000000..3ebbc67 --- /dev/null +++ b/arch/arm/plat-mxc/devices/platform-mxc_pwm.c @@ -0,0 +1,45 @@ +/* + * Copyright (C) 2009-2010 Pengutronix + * Uwe Kleine-Koenig + * + * This program is free software; you can redistribute it and/or modify it under + * the terms of the GNU General Public License version 2 as published by the + * Free Software Foundation. + */ +#include +#include + +#define imx_mxc_pwm_data_entry_single(soc) \ + { \ + .iobase = soc ## _PWM_BASE_ADDR, \ + .irq = soc ## _INT_PWM, \ + } + +#ifdef CONFIG_SOC_IMX21 +const struct imx_mxc_pwm_data imx21_mxc_pwm_data __initconst = + imx_mxc_pwm_data_entry_single(MX21); +#endif /* ifdef CONFIG_SOC_IMX21 */ + +#ifdef CONFIG_SOC_IMX27 +const struct imx_mxc_pwm_data imx27_mxc_pwm_data __initconst = + imx_mxc_pwm_data_entry_single(MX27); +#endif /* ifdef CONFIG_SOC_IMX27 */ + +struct platform_device *__init imx_add_mxc_pwm( + const struct imx_mxc_pwm_data *data) +{ + struct resource res[] = { + { + .start = data->iobase, + .end = data->iobase + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, { + .start = data->irq, + .end = data->irq, + .flags = IORESOURCE_IRQ, + }, + }; + + return imx_add_platform_device("mxc_pwm", 0, + res, ARRAY_SIZE(res), NULL, 0); +} diff --git a/arch/arm/plat-mxc/include/mach/devices-common.h b/arch/arm/plat-mxc/include/mach/devices-common.h index b1d7656..e241e41 100644 --- a/arch/arm/plat-mxc/include/mach/devices-common.h +++ b/arch/arm/plat-mxc/include/mach/devices-common.h @@ -168,6 +168,13 @@ struct platform_device *__init imx_add_mxc_nand( const struct imx_mxc_nand_data *data, const struct mxc_nand_platform_data *pdata); +struct imx_mxc_pwm_data { + resource_size_t iobase; + resource_size_t irq; +}; +struct platform_device *__init imx_add_mxc_pwm( + const struct imx_mxc_pwm_data *data); + struct imx_mxc_w1_data { resource_size_t iobase; }; -- cgit v1.1 From 9d3d945a8d5be2c915f646e8dff8422486a77030 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Fri, 5 Nov 2010 17:26:09 +0100 Subject: ARM: imx: dynamically register mxc-mmc devices MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit ... plus a trivial simplification of mx21ads_sdhc_init() Signed-off-by: Uwe Kleine-König --- arch/arm/plat-mxc/devices/Kconfig | 3 ++ arch/arm/plat-mxc/devices/Makefile | 1 + arch/arm/plat-mxc/devices/platform-mxc-mmc.c | 62 +++++++++++++++++++++++++ arch/arm/plat-mxc/include/mach/devices-common.h | 11 +++++ 4 files changed, 77 insertions(+) create mode 100644 arch/arm/plat-mxc/devices/platform-mxc-mmc.c (limited to 'arch/arm/plat-mxc') diff --git a/arch/arm/plat-mxc/devices/Kconfig b/arch/arm/plat-mxc/devices/Kconfig index 2ded17b..6560cf5 100644 --- a/arch/arm/plat-mxc/devices/Kconfig +++ b/arch/arm/plat-mxc/devices/Kconfig @@ -37,6 +37,9 @@ config IMX_HAVE_PLATFORM_MX1_CAMERA config IMX_HAVE_PLATFORM_MX2_CAMERA bool +config IMX_HAVE_PLATFORM_MXC_MMC + bool + config IMX_HAVE_PLATFORM_MXC_NAND bool diff --git a/arch/arm/plat-mxc/devices/Makefile b/arch/arm/plat-mxc/devices/Makefile index 8ecd974..d2b7a91 100644 --- a/arch/arm/plat-mxc/devices/Makefile +++ b/arch/arm/plat-mxc/devices/Makefile @@ -11,6 +11,7 @@ obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_UART) += platform-imx-uart.o obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_UDC) += platform-imx_udc.o obj-$(CONFIG_IMX_HAVE_PLATFORM_MX1_CAMERA) += platform-mx1-camera.o obj-$(CONFIG_IMX_HAVE_PLATFORM_MX2_CAMERA) += platform-mx2-camera.o +obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_MMC) += platform-mxc-mmc.o obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_NAND) += platform-mxc_nand.o obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_PWM) += platform-mxc_pwm.o obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_W1) += platform-mxc_w1.o diff --git a/arch/arm/plat-mxc/devices/platform-mxc-mmc.c b/arch/arm/plat-mxc/devices/platform-mxc-mmc.c new file mode 100644 index 0000000..953319e --- /dev/null +++ b/arch/arm/plat-mxc/devices/platform-mxc-mmc.c @@ -0,0 +1,62 @@ +/* + * Copyright (C) 2010 Pengutronix + * Uwe Kleine-Koenig + * + * This program is free software; you can redistribute it and/or modify it under + * the terms of the GNU General Public License version 2 as published by the + * Free Software Foundation. + */ +#include +#include + +#define imx_mxc_mmc_data_entry_single(soc, _id, _hwid) \ + { \ + .id = _id, \ + .iobase = soc ## _SDHC ## _hwid ## _BASE_ADDR, \ + .irq = soc ## _INT_SDHC ## _hwid, \ + .dmareq = soc ## _DMA_REQ_SDHC ## _hwid, \ + } +#define imx_mxc_mmc_data_entry(soc, _id, _hwid) \ + [_id] = imx_mxc_mmc_data_entry_single(soc, _id, _hwid) + +#ifdef CONFIG_SOC_IMX21 +const struct imx_mxc_mmc_data imx21_mxc_mmc_data[] __initconst = { +#define imx21_mxc_mmc_data_entry(_id, _hwid) \ + imx_mxc_mmc_data_entry(MX21, _id, _hwid) + imx21_mxc_mmc_data_entry(0, 1), + imx21_mxc_mmc_data_entry(1, 2), +}; +#endif /* ifdef CONFIG_SOC_IMX21 */ + +#ifdef CONFIG_SOC_IMX27 +const struct imx_mxc_mmc_data imx27_mxc_mmc_data[] __initconst = { +#define imx27_mxc_mmc_data_entry(_id, _hwid) \ + imx_mxc_mmc_data_entry(MX27, _id, _hwid) + imx27_mxc_mmc_data_entry(0, 1), + imx27_mxc_mmc_data_entry(1, 2), +}; +#endif /* ifdef CONFIG_SOC_IMX27 */ + +struct platform_device *__init imx_add_mxc_mmc( + const struct imx_mxc_mmc_data *data, + const struct imxmmc_platform_data *pdata) +{ + struct resource res[] = { + { + .start = data->iobase, + .end = data->iobase + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, { + .start = data->irq, + .end = data->irq, + .flags = IORESOURCE_IRQ, + }, { + .start = data->dmareq, + .end = data->dmareq, + .flags = IORESOURCE_DMA, + }, + }; + return imx_add_platform_device_dmamask("mxc-mmc", data->id, + res, ARRAY_SIZE(res), + pdata, sizeof(*pdata), DMA_BIT_MASK(32)); +} diff --git a/arch/arm/plat-mxc/include/mach/devices-common.h b/arch/arm/plat-mxc/include/mach/devices-common.h index e241e41..bb3b29c 100644 --- a/arch/arm/plat-mxc/include/mach/devices-common.h +++ b/arch/arm/plat-mxc/include/mach/devices-common.h @@ -151,6 +151,17 @@ struct platform_device *__init imx_add_mx2_camera( const struct imx_mx2_camera_data *data, const struct mx2_camera_platform_data *pdata); +#include +struct imx_mxc_mmc_data { + int id; + resource_size_t iobase; + resource_size_t irq; + resource_size_t dmareq; +}; +struct platform_device *__init imx_add_mxc_mmc( + const struct imx_mxc_mmc_data *data, + const struct imxmmc_platform_data *pdata); + #include struct imx_mxc_nand_data { /* -- cgit v1.1 From 2eb42d5c287f5e883a4b3ebe668ba880caa351e5 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Fri, 5 Nov 2010 18:52:09 +0100 Subject: ARM: imx: dynamically allocate mxc-ehci devices MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Uwe Kleine-König --- arch/arm/plat-mxc/devices/Kconfig | 3 ++ arch/arm/plat-mxc/devices/Makefile | 1 + arch/arm/plat-mxc/devices/platform-mxc-ehci.c | 46 +++++++++++++++++++++++++ arch/arm/plat-mxc/include/mach/devices-common.h | 10 ++++++ arch/arm/plat-mxc/include/mach/mx27.h | 12 ++++--- 5 files changed, 67 insertions(+), 5 deletions(-) create mode 100644 arch/arm/plat-mxc/devices/platform-mxc-ehci.c (limited to 'arch/arm/plat-mxc') diff --git a/arch/arm/plat-mxc/devices/Kconfig b/arch/arm/plat-mxc/devices/Kconfig index 6560cf5..d2d096c 100644 --- a/arch/arm/plat-mxc/devices/Kconfig +++ b/arch/arm/plat-mxc/devices/Kconfig @@ -37,6 +37,9 @@ config IMX_HAVE_PLATFORM_MX1_CAMERA config IMX_HAVE_PLATFORM_MX2_CAMERA bool +config IMX_HAVE_PLATFORM_MXC_EHCI + bool + config IMX_HAVE_PLATFORM_MXC_MMC bool diff --git a/arch/arm/plat-mxc/devices/Makefile b/arch/arm/plat-mxc/devices/Makefile index d2b7a91..c8734bd 100644 --- a/arch/arm/plat-mxc/devices/Makefile +++ b/arch/arm/plat-mxc/devices/Makefile @@ -11,6 +11,7 @@ obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_UART) += platform-imx-uart.o obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_UDC) += platform-imx_udc.o obj-$(CONFIG_IMX_HAVE_PLATFORM_MX1_CAMERA) += platform-mx1-camera.o obj-$(CONFIG_IMX_HAVE_PLATFORM_MX2_CAMERA) += platform-mx2-camera.o +obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_EHCI) += platform-mxc-ehci.o obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_MMC) += platform-mxc-mmc.o obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_NAND) += platform-mxc_nand.o obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_PWM) += platform-mxc_pwm.o diff --git a/arch/arm/plat-mxc/devices/platform-mxc-ehci.c b/arch/arm/plat-mxc/devices/platform-mxc-ehci.c new file mode 100644 index 0000000..0cb67bb --- /dev/null +++ b/arch/arm/plat-mxc/devices/platform-mxc-ehci.c @@ -0,0 +1,46 @@ +/* + * Copyright (C) 2010 Pengutronix + * Uwe Kleine-Koenig + * + * This program is free software; you can redistribute it and/or modify it under + * the terms of the GNU General Public License version 2 as published by the + * Free Software Foundation. + */ +#include +#include + +#define imx_mxc_ehci_data_entry_single(soc, _id, hs) \ + { \ + .id = _id, \ + .iobase = soc ## _USB_ ## hs ## _BASE_ADDR, \ + .irq = soc ## _INT_USB_ ## hs, \ + } + +#ifdef CONFIG_SOC_IMX27 +const struct imx_mxc_ehci_data imx27_mxc_ehci_otg_data __initconst = + imx_mxc_ehci_data_entry_single(MX27, 0, OTG); +const struct imx_mxc_ehci_data imx27_mxc_ehci_hs_data[] __initconst = { + imx_mxc_ehci_data_entry_single(MX27, 1, HS1), + imx_mxc_ehci_data_entry_single(MX27, 2, HS2), +}; +#endif /* ifdef CONFIG_SOC_IMX27 */ + +struct platform_device *__init imx_add_mxc_ehci( + const struct imx_mxc_ehci_data *data, + const struct mxc_usbh_platform_data *pdata) +{ + struct resource res[] = { + { + .start = data->iobase, + .end = data->iobase + SZ_512 - 1, + .flags = IORESOURCE_MEM, + }, { + .start = data->irq, + .end = data->irq, + .flags = IORESOURCE_IRQ, + }, + }; + return imx_add_platform_device_dmamask("mxc-ehci", data->id, + res, ARRAY_SIZE(res), + pdata, sizeof(*pdata), DMA_BIT_MASK(32)); +} diff --git a/arch/arm/plat-mxc/include/mach/devices-common.h b/arch/arm/plat-mxc/include/mach/devices-common.h index bb3b29c..7df7a9f 100644 --- a/arch/arm/plat-mxc/include/mach/devices-common.h +++ b/arch/arm/plat-mxc/include/mach/devices-common.h @@ -151,6 +151,16 @@ struct platform_device *__init imx_add_mx2_camera( const struct imx_mx2_camera_data *data, const struct mx2_camera_platform_data *pdata); +#include +struct imx_mxc_ehci_data { + int id; + resource_size_t iobase; + resource_size_t irq; +}; +struct platform_device *__init imx_add_mxc_ehci( + const struct imx_mxc_ehci_data *data, + const struct mxc_usbh_platform_data *pdata); + #include struct imx_mxc_mmc_data { int id; diff --git a/arch/arm/plat-mxc/include/mach/mx27.h b/arch/arm/plat-mxc/include/mach/mx27.h index 2734d24..45419b3 100644 --- a/arch/arm/plat-mxc/include/mach/mx27.h +++ b/arch/arm/plat-mxc/include/mach/mx27.h @@ -64,8 +64,10 @@ #define MX27_LCDC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x21000) #define MX27_SLCDC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x22000) #define MX27_VPU_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x23000) -#define MX27_USBOTG_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x24000) -#define MX27_OTG_BASE_ADDR MX27_USBOTG_BASE_ADDR +#define MX27_USB_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x24000) +#define MX27_USB_OTG_BASE_ADDR (MX27_USB_BASE_ADDR + 0x0000) +#define MX27_USB_HS1_BASE_ADDR (MX27_USB_BASE_ADDR + 0x0200) +#define MX27_USB_HS2_BASE_ADDR (MX27_USB_BASE_ADDR + 0x0400) #define MX27_SAHARA_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x25000) #define MX27_EMMAPP_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x26000) #define MX27_EMMAPRP_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x26400) @@ -187,9 +189,9 @@ static inline void mx27_setup_weimcs(size_t cs, #define MX27_INT_EMMAPRP 51 #define MX27_INT_EMMAPP 52 #define MX27_INT_VPU 53 -#define MX27_INT_USB1 54 -#define MX27_INT_USB2 55 -#define MX27_INT_USB3 56 +#define MX27_INT_USB_HS1 54 +#define MX27_INT_USB_HS2 55 +#define MX27_INT_USB_OTG 56 #define MX27_INT_SCC_SMN 57 #define MX27_INT_SCC_SCM 58 #define MX27_INT_SAHARA 59 -- cgit v1.1 From bd455ed36c487b949068182bfee478b785ee090b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Tue, 9 Nov 2010 17:52:14 +0100 Subject: ARM: imx: dynamically allocate fsl-usb2-udc devices MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Uwe Kleine-König --- arch/arm/plat-mxc/devices/Kconfig | 3 ++ arch/arm/plat-mxc/devices/Makefile | 1 + arch/arm/plat-mxc/devices/platform-fsl-usb2-udc.c | 41 +++++++++++++++++++++++ arch/arm/plat-mxc/include/mach/devices-common.h | 9 +++++ 4 files changed, 54 insertions(+) create mode 100644 arch/arm/plat-mxc/devices/platform-fsl-usb2-udc.c (limited to 'arch/arm/plat-mxc') diff --git a/arch/arm/plat-mxc/devices/Kconfig b/arch/arm/plat-mxc/devices/Kconfig index d2d096c..26196d9 100644 --- a/arch/arm/plat-mxc/devices/Kconfig +++ b/arch/arm/plat-mxc/devices/Kconfig @@ -9,6 +9,9 @@ config IMX_HAVE_PLATFORM_FLEXCAN select HAVE_CAN_FLEXCAN if CAN bool +config IMX_HAVE_PLATFORM_FSL_USB2_UDC + bool + config IMX_HAVE_PLATFORM_GPIO_KEYS bool default y if ARCH_MX51 diff --git a/arch/arm/plat-mxc/devices/Makefile b/arch/arm/plat-mxc/devices/Makefile index c8734bd..e40897e 100644 --- a/arch/arm/plat-mxc/devices/Makefile +++ b/arch/arm/plat-mxc/devices/Makefile @@ -1,6 +1,7 @@ obj-$(CONFIG_IMX_HAVE_PLATFORM_ESDHC) += platform-esdhc.o obj-$(CONFIG_IMX_HAVE_PLATFORM_FEC) += platform-fec.o obj-$(CONFIG_IMX_HAVE_PLATFORM_FLEXCAN) += platform-flexcan.o +obj-$(CONFIG_IMX_HAVE_PLATFORM_FSL_USB2_UDC) += platform-fsl-usb2-udc.o obj-$(CONFIG_IMX_HAVE_PLATFORM_GPIO_KEYS) += platform-gpio_keys.o obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX2_WDT) += platform-imx2-wdt.o obj-y += platform-imx-dma.o diff --git a/arch/arm/plat-mxc/devices/platform-fsl-usb2-udc.c b/arch/arm/plat-mxc/devices/platform-fsl-usb2-udc.c new file mode 100644 index 0000000..3116f9a --- /dev/null +++ b/arch/arm/plat-mxc/devices/platform-fsl-usb2-udc.c @@ -0,0 +1,41 @@ +/* + * Copyright (C) 2010 Pengutronix + * Uwe Kleine-Koenig + * + * This program is free software; you can redistribute it and/or modify it under + * the terms of the GNU General Public License version 2 as published by the + * Free Software Foundation. + */ +#include +#include + +#define imx_fsl_usb2_udc_data_entry_single(soc) \ + { \ + .iobase = soc ## _USB_OTG_BASE_ADDR, \ + .irq = soc ## _INT_USB_OTG, \ + } + +#ifdef CONFIG_SOC_IMX27 +const struct imx_fsl_usb2_udc_data imx27_fsl_usb2_udc_data __initconst = + imx_fsl_usb2_udc_data_entry_single(MX27); +#endif /* ifdef CONFIG_SOC_IMX27 */ + +struct platform_device *__init imx_add_fsl_usb2_udc( + const struct imx_fsl_usb2_udc_data *data, + const struct fsl_usb2_platform_data *pdata) +{ + struct resource res[] = { + { + .start = data->iobase, + .end = data->iobase + SZ_512 - 1, + .flags = IORESOURCE_MEM, + }, { + .start = data->irq, + .end = data->irq, + .flags = IORESOURCE_IRQ, + }, + }; + return imx_add_platform_device_dmamask("fsl-usb2-udc", -1, + res, ARRAY_SIZE(res), + pdata, sizeof(*pdata), DMA_BIT_MASK(32)); +} diff --git a/arch/arm/plat-mxc/include/mach/devices-common.h b/arch/arm/plat-mxc/include/mach/devices-common.h index 7df7a9f..f01fd28 100644 --- a/arch/arm/plat-mxc/include/mach/devices-common.h +++ b/arch/arm/plat-mxc/include/mach/devices-common.h @@ -44,6 +44,15 @@ struct platform_device *__init imx_add_flexcan( const struct imx_flexcan_data *data, const struct flexcan_platform_data *pdata); +#include +struct imx_fsl_usb2_udc_data { + resource_size_t iobase; + resource_size_t irq; +}; +struct platform_device *__init imx_add_fsl_usb2_udc( + const struct imx_fsl_usb2_udc_data *data, + const struct fsl_usb2_platform_data *pdata); + #include struct platform_device *__init imx_add_gpio_keys( const struct gpio_keys_platform_data *pdata); -- cgit v1.1 From 3f880141b8d12cdbb5faf0b9941ee50ac515ea1e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Wed, 10 Nov 2010 09:58:56 +0100 Subject: ARM: imx: dynamically allocate imx-keypad devices MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Uwe Kleine-König --- arch/arm/plat-mxc/devices/Kconfig | 3 ++ arch/arm/plat-mxc/devices/Makefile | 1 + arch/arm/plat-mxc/devices/platform-imx-keypad.c | 46 +++++++++++++++++++++++++ arch/arm/plat-mxc/include/mach/devices-common.h | 9 +++++ 4 files changed, 59 insertions(+) create mode 100644 arch/arm/plat-mxc/devices/platform-imx-keypad.c (limited to 'arch/arm/plat-mxc') diff --git a/arch/arm/plat-mxc/devices/Kconfig b/arch/arm/plat-mxc/devices/Kconfig index 26196d9..212f380 100644 --- a/arch/arm/plat-mxc/devices/Kconfig +++ b/arch/arm/plat-mxc/devices/Kconfig @@ -25,6 +25,9 @@ config IMX_HAVE_PLATFORM_IMX_FB config IMX_HAVE_PLATFORM_IMX_I2C bool +config IMX_HAVE_PLATFORM_IMX_KEYPAD + bool + config IMX_HAVE_PLATFORM_IMX_SSI bool diff --git a/arch/arm/plat-mxc/devices/Makefile b/arch/arm/plat-mxc/devices/Makefile index e40897e..dd23bab 100644 --- a/arch/arm/plat-mxc/devices/Makefile +++ b/arch/arm/plat-mxc/devices/Makefile @@ -7,6 +7,7 @@ obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX2_WDT) += platform-imx2-wdt.o obj-y += platform-imx-dma.o obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_FB) += platform-imx-fb.o obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_I2C) += platform-imx-i2c.o +obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_KEYPAD) += platform-imx-keypad.o obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_SSI) += platform-imx-ssi.o obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_UART) += platform-imx-uart.o obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_UDC) += platform-imx_udc.o diff --git a/arch/arm/plat-mxc/devices/platform-imx-keypad.c b/arch/arm/plat-mxc/devices/platform-imx-keypad.c new file mode 100644 index 0000000..fdfee55 --- /dev/null +++ b/arch/arm/plat-mxc/devices/platform-imx-keypad.c @@ -0,0 +1,46 @@ +/* + * Copyright (C) 2010 Pengutronix + * Uwe Kleine-Koenig + * + * This program is free software; you can redistribute it and/or modify it under + * the terms of the GNU General Public License version 2 as published by the + * Free Software Foundation. + */ +#include +#include + +#define imx_imx_keypad_data_entry_single(soc) \ + { \ + .iobase = soc ## _KPP_BASE_ADDR, \ + .irq = soc ## _INT_KPP, \ + } + +#ifdef CONFIG_SOC_IMX21 +const struct imx_imx_keypad_data imx21_imx_keypad_data __initconst = + imx_imx_keypad_data_entry_single(MX21); +#endif /* ifdef CONFIG_SOC_IMX21 */ + +#ifdef CONFIG_SOC_IMX27 +const struct imx_imx_keypad_data imx27_imx_keypad_data __initconst = + imx_imx_keypad_data_entry_single(MX27); +#endif /* ifdef CONFIG_SOC_IMX27 */ + +struct platform_device *__init imx_add_imx_keypad( + const struct imx_imx_keypad_data *data, + const struct matrix_keymap_data *pdata) +{ + struct resource res[] = { + { + .start = data->iobase, + .end = data->iobase + SZ_16 - 1, + .flags = IORESOURCE_MEM, + }, { + .start = data->irq, + .end = data->irq, + .flags = IORESOURCE_IRQ, + }, + }; + + return imx_add_platform_device("imx-keypad", -1, + res, ARRAY_SIZE(res), pdata, sizeof(*pdata)); +} diff --git a/arch/arm/plat-mxc/include/mach/devices-common.h b/arch/arm/plat-mxc/include/mach/devices-common.h index f01fd28..1a67299 100644 --- a/arch/arm/plat-mxc/include/mach/devices-common.h +++ b/arch/arm/plat-mxc/include/mach/devices-common.h @@ -83,6 +83,15 @@ struct platform_device *__init imx_add_imx_i2c( const struct imx_imx_i2c_data *data, const struct imxi2c_platform_data *pdata); +#include +struct imx_imx_keypad_data { + resource_size_t iobase; + resource_size_t irq; +}; +struct platform_device *__init imx_add_imx_keypad( + const struct imx_imx_keypad_data *data, + const struct matrix_keymap_data *pdata); + #include struct imx_imx_ssi_data { int id; -- cgit v1.1 From 9f871469893a6d87c6cddf412f82ebf588fd4eca Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Wed, 10 Nov 2010 10:11:23 +0100 Subject: ARM: imx: dynamically allocate imx21-hcd devices MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Uwe Kleine-König --- arch/arm/plat-mxc/devices/Kconfig | 3 ++ arch/arm/plat-mxc/devices/Makefile | 1 + arch/arm/plat-mxc/devices/platform-imx21-hcd.c | 41 +++++++++++++++++++++++++ arch/arm/plat-mxc/include/mach/devices-common.h | 9 ++++++ 4 files changed, 54 insertions(+) create mode 100644 arch/arm/plat-mxc/devices/platform-imx21-hcd.c (limited to 'arch/arm/plat-mxc') diff --git a/arch/arm/plat-mxc/devices/Kconfig b/arch/arm/plat-mxc/devices/Kconfig index 212f380..a0be2df 100644 --- a/arch/arm/plat-mxc/devices/Kconfig +++ b/arch/arm/plat-mxc/devices/Kconfig @@ -15,6 +15,9 @@ config IMX_HAVE_PLATFORM_FSL_USB2_UDC config IMX_HAVE_PLATFORM_GPIO_KEYS bool default y if ARCH_MX51 + +config IMX_HAVE_PLATFORM_IMX21_HCD + bool config IMX_HAVE_PLATFORM_IMX2_WDT bool diff --git a/arch/arm/plat-mxc/devices/Makefile b/arch/arm/plat-mxc/devices/Makefile index dd23bab..14b228e 100644 --- a/arch/arm/plat-mxc/devices/Makefile +++ b/arch/arm/plat-mxc/devices/Makefile @@ -3,6 +3,7 @@ obj-$(CONFIG_IMX_HAVE_PLATFORM_FEC) += platform-fec.o obj-$(CONFIG_IMX_HAVE_PLATFORM_FLEXCAN) += platform-flexcan.o obj-$(CONFIG_IMX_HAVE_PLATFORM_FSL_USB2_UDC) += platform-fsl-usb2-udc.o obj-$(CONFIG_IMX_HAVE_PLATFORM_GPIO_KEYS) += platform-gpio_keys.o +obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX21_HCD) += platform-imx21-hcd.o obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX2_WDT) += platform-imx2-wdt.o obj-y += platform-imx-dma.o obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_FB) += platform-imx-fb.o diff --git a/arch/arm/plat-mxc/devices/platform-imx21-hcd.c b/arch/arm/plat-mxc/devices/platform-imx21-hcd.c new file mode 100644 index 0000000..5770a42 --- /dev/null +++ b/arch/arm/plat-mxc/devices/platform-imx21-hcd.c @@ -0,0 +1,41 @@ +/* + * Copyright (C) 2010 Pengutronix + * Uwe Kleine-Koenig + * + * This program is free software; you can redistribute it and/or modify it under + * the terms of the GNU General Public License version 2 as published by the + * Free Software Foundation. + */ +#include +#include + +#define imx_imx21_hcd_data_entry_single(soc) \ + { \ + .iobase = soc ## _USBOTG_BASE_ADDR, \ + .irq = soc ## _INT_USBHOST, \ + } + +#ifdef CONFIG_SOC_IMX21 +const struct imx_imx21_hcd_data imx21_imx21_hcd_data __initconst = + imx_imx21_hcd_data_entry_single(MX21); +#endif /* ifdef CONFIG_SOC_IMX21 */ + +struct platform_device *__init imx_add_imx21_hcd( + const struct imx_imx21_hcd_data *data, + const struct mx21_usbh_platform_data *pdata) +{ + struct resource res[] = { + { + .start = data->iobase, + .end = data->iobase + SZ_8K - 1, + .flags = IORESOURCE_MEM, + }, { + .start = data->irq, + .end = data->irq, + .flags = IORESOURCE_IRQ, + }, + }; + return imx_add_platform_device_dmamask("imx21-hcd", 0, + res, ARRAY_SIZE(res), + pdata, sizeof(*pdata), DMA_BIT_MASK(32)); +} diff --git a/arch/arm/plat-mxc/include/mach/devices-common.h b/arch/arm/plat-mxc/include/mach/devices-common.h index 1a67299..f5d0000 100644 --- a/arch/arm/plat-mxc/include/mach/devices-common.h +++ b/arch/arm/plat-mxc/include/mach/devices-common.h @@ -57,6 +57,15 @@ struct platform_device *__init imx_add_fsl_usb2_udc( struct platform_device *__init imx_add_gpio_keys( const struct gpio_keys_platform_data *pdata); +#include +struct imx_imx21_hcd_data { + resource_size_t iobase; + resource_size_t irq; +}; +struct platform_device *__init imx_add_imx21_hcd( + const struct imx_imx21_hcd_data *data, + const struct mx21_usbh_platform_data *pdata); + struct imx_imx2_wdt_data { resource_size_t iobase; }; -- cgit v1.1 From e9f0bafb4f3d32d0bc0ea7e946d667a68bae59ce Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Wed, 10 Nov 2010 10:51:38 +0100 Subject: ARM: imx: move registration of gpios to plat-mxc/gpio.c MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This finally gets rid of mach-imx/devices.c. Signed-off-by: Uwe Kleine-König --- arch/arm/plat-mxc/gpio.c | 59 ++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 59 insertions(+) (limited to 'arch/arm/plat-mxc') diff --git a/arch/arm/plat-mxc/gpio.c b/arch/arm/plat-mxc/gpio.c index a43d9cc..2c00d9b 100644 --- a/arch/arm/plat-mxc/gpio.c +++ b/arch/arm/plat-mxc/gpio.c @@ -349,3 +349,62 @@ int __init mxc_gpio_init(struct mxc_gpio_port *port, int cnt) return 0; } + +#define DEFINE_IMX_GPIO_PORT_IRQ(soc, n, _irq) \ + { \ + .chip.label = "gpio-" #n, \ + .irq = _irq, \ + .base = soc ## _IO_ADDRESS(soc ## _GPIO_BASE_ADDR + \ + (n) * SZ_256), \ + .virtual_irq_start = MXC_GPIO_IRQ_START + (n) * 32, \ + } + +#define DEFINE_IMX_GPIO_PORT(soc, n) \ + DEFINE_IMX_GPIO_PORT_IRQ(soc, n, 0) + +#define DEFINE_REGISTER_FUNCTION(prefix) \ +int __init prefix ## _register_gpios(void) \ +{ \ + return mxc_gpio_init(prefix ## _gpio_ports, \ + ARRAY_SIZE(prefix ## _gpio_ports)); \ +} + +#if defined(CONFIG_SOC_IMX1) +static struct mxc_gpio_port imx1_gpio_ports[] = { + DEFINE_IMX_GPIO_PORT_IRQ(MX1, 0, MX1_GPIO_INT_PORTA), + DEFINE_IMX_GPIO_PORT_IRQ(MX1, 1, MX1_GPIO_INT_PORTB), + DEFINE_IMX_GPIO_PORT_IRQ(MX1, 2, MX1_GPIO_INT_PORTC), + DEFINE_IMX_GPIO_PORT_IRQ(MX1, 3, MX1_GPIO_INT_PORTD), +}; + +DEFINE_REGISTER_FUNCTION(imx1) + +#endif /* if defined(CONFIG_SOC_IMX1) */ + +#if defined(CONFIG_SOC_IMX21) +static struct mxc_gpio_port imx21_gpio_ports[] = { + DEFINE_IMX_GPIO_PORT_IRQ(MX21, 0, MX21_INT_GPIO), + DEFINE_IMX_GPIO_PORT(MX21, 1), + DEFINE_IMX_GPIO_PORT(MX21, 2), + DEFINE_IMX_GPIO_PORT(MX21, 3), + DEFINE_IMX_GPIO_PORT(MX21, 4), + DEFINE_IMX_GPIO_PORT(MX21, 5), +}; + +DEFINE_REGISTER_FUNCTION(imx21) + +#endif /* if defined(CONFIG_SOC_IMX21) */ + +#if defined(CONFIG_SOC_IMX27) +static struct mxc_gpio_port imx27_gpio_ports[] = { + DEFINE_IMX_GPIO_PORT_IRQ(MX27, 0, MX27_INT_GPIO), + DEFINE_IMX_GPIO_PORT(MX27, 1), + DEFINE_IMX_GPIO_PORT(MX27, 2), + DEFINE_IMX_GPIO_PORT(MX27, 3), + DEFINE_IMX_GPIO_PORT(MX27, 4), + DEFINE_IMX_GPIO_PORT(MX27, 5), +}; + +DEFINE_REGISTER_FUNCTION(imx27) + +#endif /* if defined(CONFIG_SOC_IMX27) */ -- cgit v1.1 From 2c20b9f19add2248dc867f1f78dcef1eb0944543 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Wed, 10 Nov 2010 21:27:55 +0100 Subject: ARM: mx25: dynamically allocate mxc-ehci devices MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit According to the reference manual of the i.MX25 the host controller uses an offset of 0x200 not 0x400 as was specified in the resources for mxc_usbh2. Needs-Testing: yes Signed-off-by: Uwe Kleine-König --- arch/arm/plat-mxc/devices/platform-mxc-ehci.c | 7 +++++++ arch/arm/plat-mxc/ehci.c | 4 ++-- arch/arm/plat-mxc/include/mach/mx25.h | 6 +++++- 3 files changed, 14 insertions(+), 3 deletions(-) (limited to 'arch/arm/plat-mxc') diff --git a/arch/arm/plat-mxc/devices/platform-mxc-ehci.c b/arch/arm/plat-mxc/devices/platform-mxc-ehci.c index 0cb67bb..825a048 100644 --- a/arch/arm/plat-mxc/devices/platform-mxc-ehci.c +++ b/arch/arm/plat-mxc/devices/platform-mxc-ehci.c @@ -16,6 +16,13 @@ .irq = soc ## _INT_USB_ ## hs, \ } +#ifdef CONFIG_ARCH_MX25 +const struct imx_mxc_ehci_data imx25_mxc_ehci_otg_data __initconst = + imx_mxc_ehci_data_entry_single(MX25, 0, OTG); +const struct imx_mxc_ehci_data imx25_mxc_ehci_hs_data __initconst = + imx_mxc_ehci_data_entry_single(MX25, 1, HS); +#endif /* ifdef CONFIG_ARCH_MX25 */ + #ifdef CONFIG_SOC_IMX27 const struct imx_mxc_ehci_data imx27_mxc_ehci_otg_data __initconst = imx_mxc_ehci_data_entry_single(MX27, 0, OTG); diff --git a/arch/arm/plat-mxc/ehci.c b/arch/arm/plat-mxc/ehci.c index 9915607..f699235 100644 --- a/arch/arm/plat-mxc/ehci.c +++ b/arch/arm/plat-mxc/ehci.c @@ -71,7 +71,7 @@ int mxc_initialize_usb_hw(int port, unsigned int flags) unsigned int v; #if defined(CONFIG_ARCH_MX25) if (cpu_is_mx25()) { - v = readl(MX25_IO_ADDRESS(MX25_OTG_BASE_ADDR + + v = readl(MX25_IO_ADDRESS(MX25_USB_BASE_ADDR + USBCTRL_OTGBASE_OFFSET)); switch (port) { @@ -108,7 +108,7 @@ int mxc_initialize_usb_hw(int port, unsigned int flags) return -EINVAL; } - writel(v, MX25_IO_ADDRESS(MX25_OTG_BASE_ADDR + + writel(v, MX25_IO_ADDRESS(MX25_USB_BASE_ADDR + USBCTRL_OTGBASE_OFFSET)); return 0; } diff --git a/arch/arm/plat-mxc/include/mach/mx25.h b/arch/arm/plat-mxc/include/mach/mx25.h index a2404b0..0d31f82 100644 --- a/arch/arm/plat-mxc/include/mach/mx25.h +++ b/arch/arm/plat-mxc/include/mach/mx25.h @@ -43,7 +43,9 @@ #define MX25_LCDC_BASE_ADDR 0x53fbc000 #define MX25_KPP_BASE_ADDR 0x43fa8000 #define MX25_SDMA_BASE_ADDR 0x53fd4000 -#define MX25_OTG_BASE_ADDR 0x53ff4000 +#define MX25_USB_BASE_ADDR 0x53ff4000 +#define MX25_USB_OTG_BASE_ADDR (MX25_USB_BASE_ADDR + 0x0000) +#define MX25_USB_HS_BASE_ADDR (MX25_USB_BASE_ADDR + 0x0200) #define MX25_CSI_BASE_ADDR 0x53ff8000 #define MX25_IO_P2V(x) IMX_IO_P2V(x) @@ -67,6 +69,8 @@ #define MX25_INT_UART2 32 #define MX25_INT_NFC 33 #define MX25_INT_SDMA 34 +#define MX25_INT_USB_HS 35 +#define MX25_INT_USB_OTG 37 #define MX25_INT_LCDC 39 #define MX25_INT_UART5 40 #define MX25_INT_CAN1 43 -- cgit v1.1 From 224b8c83641c2f31e3efc9bc5956636cc42cadf7 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Wed, 10 Nov 2010 21:50:07 +0100 Subject: ARM: mx25: dynamically allocate fsl-usb2-udc devices MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Uwe Kleine-König --- arch/arm/plat-mxc/devices/platform-fsl-usb2-udc.c | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch/arm/plat-mxc') diff --git a/arch/arm/plat-mxc/devices/platform-fsl-usb2-udc.c b/arch/arm/plat-mxc/devices/platform-fsl-usb2-udc.c index 3116f9a..cb5fb71 100644 --- a/arch/arm/plat-mxc/devices/platform-fsl-usb2-udc.c +++ b/arch/arm/plat-mxc/devices/platform-fsl-usb2-udc.c @@ -15,6 +15,11 @@ .irq = soc ## _INT_USB_OTG, \ } +#ifdef CONFIG_ARCH_MX25 +const struct imx_fsl_usb2_udc_data imx25_fsl_usb2_udc_data __initconst = + imx_fsl_usb2_udc_data_entry_single(MX25); +#endif + #ifdef CONFIG_SOC_IMX27 const struct imx_fsl_usb2_udc_data imx27_fsl_usb2_udc_data __initconst = imx_fsl_usb2_udc_data_entry_single(MX27); -- cgit v1.1 From 5f3d1092a949b33d01c95b7f5e5a83672629f131 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Wed, 10 Nov 2010 22:15:45 +0100 Subject: ARM: mx25: dynamically allocate mxc_pwm devices MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Uwe Kleine-König --- arch/arm/plat-mxc/devices/platform-mxc_pwm.c | 29 +++++++++++++++++++------ arch/arm/plat-mxc/include/mach/devices-common.h | 2 ++ arch/arm/plat-mxc/include/mach/mx25.h | 8 +++++++ 3 files changed, 32 insertions(+), 7 deletions(-) (limited to 'arch/arm/plat-mxc') diff --git a/arch/arm/plat-mxc/devices/platform-mxc_pwm.c b/arch/arm/plat-mxc/devices/platform-mxc_pwm.c index 3ebbc67..5a47d1e 100644 --- a/arch/arm/plat-mxc/devices/platform-mxc_pwm.c +++ b/arch/arm/plat-mxc/devices/platform-mxc_pwm.c @@ -9,20 +9,35 @@ #include #include -#define imx_mxc_pwm_data_entry_single(soc) \ +#define imx_mxc_pwm_data_entry_single(soc, _id, _hwid, _size) \ { \ - .iobase = soc ## _PWM_BASE_ADDR, \ - .irq = soc ## _INT_PWM, \ + .id = _id, \ + .iobase = soc ## _PWM ## _hwid ## _BASE_ADDR, \ + .iosize = _size, \ + .irq = soc ## _INT_PWM ## _hwid, \ } +#define imx_mxc_pwm_data_entry(soc, _id, _hwid, _size) \ + [_id] = imx_mxc_pwm_data_entry_single(soc, _id, _hwid, _size) #ifdef CONFIG_SOC_IMX21 const struct imx_mxc_pwm_data imx21_mxc_pwm_data __initconst = - imx_mxc_pwm_data_entry_single(MX21); + imx_mxc_pwm_data_entry_single(MX21, 0, , SZ_4K); #endif /* ifdef CONFIG_SOC_IMX21 */ +#ifdef CONFIG_ARCH_MX25 +const struct imx_mxc_pwm_data imx25_mxc_pwm_data[] __initconst = { +#define imx25_mxc_pwm_data_entry(_id, _hwid) \ + imx_mxc_pwm_data_entry(MX25, _id, _hwid, SZ_16K) + imx25_mxc_pwm_data_entry(0, 1), + imx25_mxc_pwm_data_entry(1, 2), + imx25_mxc_pwm_data_entry(2, 3), + imx25_mxc_pwm_data_entry(3, 4), +}; +#endif + #ifdef CONFIG_SOC_IMX27 const struct imx_mxc_pwm_data imx27_mxc_pwm_data __initconst = - imx_mxc_pwm_data_entry_single(MX27); + imx_mxc_pwm_data_entry_single(MX27, 0, , SZ_4K); #endif /* ifdef CONFIG_SOC_IMX27 */ struct platform_device *__init imx_add_mxc_pwm( @@ -31,7 +46,7 @@ struct platform_device *__init imx_add_mxc_pwm( struct resource res[] = { { .start = data->iobase, - .end = data->iobase + SZ_4K - 1, + .end = data->iobase + data->iosize - 1, .flags = IORESOURCE_MEM, }, { .start = data->irq, @@ -40,6 +55,6 @@ struct platform_device *__init imx_add_mxc_pwm( }, }; - return imx_add_platform_device("mxc_pwm", 0, + return imx_add_platform_device("mxc_pwm", data->id, res, ARRAY_SIZE(res), NULL, 0); } diff --git a/arch/arm/plat-mxc/include/mach/devices-common.h b/arch/arm/plat-mxc/include/mach/devices-common.h index f5d0000..07223b2 100644 --- a/arch/arm/plat-mxc/include/mach/devices-common.h +++ b/arch/arm/plat-mxc/include/mach/devices-common.h @@ -217,7 +217,9 @@ struct platform_device *__init imx_add_mxc_nand( const struct mxc_nand_platform_data *pdata); struct imx_mxc_pwm_data { + int id; resource_size_t iobase; + resource_size_t iosize; resource_size_t irq; }; struct platform_device *__init imx_add_mxc_pwm( diff --git a/arch/arm/plat-mxc/include/mach/mx25.h b/arch/arm/plat-mxc/include/mach/mx25.h index 0d31f82..cea851f 100644 --- a/arch/arm/plat-mxc/include/mach/mx25.h +++ b/arch/arm/plat-mxc/include/mach/mx25.h @@ -19,10 +19,14 @@ #define MX25_CRM_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0x80000) #define MX25_GPT1_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0x90000) #define MX25_GPIO4_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0x9c000) +#define MX25_PWM2_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xa0000) #define MX25_GPIO3_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xa4000) +#define MX25_PWM3_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xa8000) +#define MX25_PWM4_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xc8000) #define MX25_GPIO1_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xcc000) #define MX25_GPIO2_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xd0000) #define MX25_WDOG_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xdc000) +#define MX25_PWM1_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xe0000) #define MX25_UART1_BASE_ADDR 0x43f90000 #define MX25_UART2_BASE_ADDR 0x43f94000 @@ -66,13 +70,17 @@ #define MX25_INT_UART3 18 #define MX25_INT_KPP 24 #define MX25_INT_DRYICE 25 +#define MX25_INT_PWM1 26 #define MX25_INT_UART2 32 #define MX25_INT_NFC 33 #define MX25_INT_SDMA 34 #define MX25_INT_USB_HS 35 +#define MX25_INT_PWM2 36 #define MX25_INT_USB_OTG 37 #define MX25_INT_LCDC 39 #define MX25_INT_UART5 40 +#define MX25_INT_PWM3 41 +#define MX25_INT_PWM4 42 #define MX25_INT_CAN1 43 #define MX25_INT_CAN2 44 #define MX25_INT_UART1 45 -- cgit v1.1 From d485c7e71675abdd6133128e596b41284c2ee7b5 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Thu, 11 Nov 2010 10:52:33 +0100 Subject: ARM: mx25: move registration of gpios to plat-mxc/gpio.c MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit To use common macros to define the gpio ports for imx{1,21,25,27} the existing ones had to made more general and a few more base address defines were necessary. Signed-off-by: Uwe Kleine-König --- arch/arm/plat-mxc/gpio.c | 58 +++++++++++++++++++++-------------- arch/arm/plat-mxc/include/mach/mx1.h | 4 +++ arch/arm/plat-mxc/include/mach/mx21.h | 6 ++++ arch/arm/plat-mxc/include/mach/mx25.h | 4 +++ arch/arm/plat-mxc/include/mach/mx27.h | 6 ++++ 5 files changed, 55 insertions(+), 23 deletions(-) (limited to 'arch/arm/plat-mxc') diff --git a/arch/arm/plat-mxc/gpio.c b/arch/arm/plat-mxc/gpio.c index 2c00d9b..e59fb97 100644 --- a/arch/arm/plat-mxc/gpio.c +++ b/arch/arm/plat-mxc/gpio.c @@ -350,17 +350,17 @@ int __init mxc_gpio_init(struct mxc_gpio_port *port, int cnt) return 0; } -#define DEFINE_IMX_GPIO_PORT_IRQ(soc, n, _irq) \ +#define DEFINE_IMX_GPIO_PORT_IRQ(soc, _id, _hwid, _irq) \ { \ - .chip.label = "gpio-" #n, \ + .chip.label = "gpio-" #_id, \ .irq = _irq, \ - .base = soc ## _IO_ADDRESS(soc ## _GPIO_BASE_ADDR + \ - (n) * SZ_256), \ - .virtual_irq_start = MXC_GPIO_IRQ_START + (n) * 32, \ + .base = soc ## _IO_ADDRESS( \ + soc ## _GPIO ## _hwid ## _BASE_ADDR), \ + .virtual_irq_start = MXC_GPIO_IRQ_START + (_id) * 32, \ } -#define DEFINE_IMX_GPIO_PORT(soc, n) \ - DEFINE_IMX_GPIO_PORT_IRQ(soc, n, 0) +#define DEFINE_IMX_GPIO_PORT(soc, _id, _hwid) \ + DEFINE_IMX_GPIO_PORT_IRQ(soc, _id, _hwid, 0) #define DEFINE_REGISTER_FUNCTION(prefix) \ int __init prefix ## _register_gpios(void) \ @@ -371,10 +371,10 @@ int __init prefix ## _register_gpios(void) \ #if defined(CONFIG_SOC_IMX1) static struct mxc_gpio_port imx1_gpio_ports[] = { - DEFINE_IMX_GPIO_PORT_IRQ(MX1, 0, MX1_GPIO_INT_PORTA), - DEFINE_IMX_GPIO_PORT_IRQ(MX1, 1, MX1_GPIO_INT_PORTB), - DEFINE_IMX_GPIO_PORT_IRQ(MX1, 2, MX1_GPIO_INT_PORTC), - DEFINE_IMX_GPIO_PORT_IRQ(MX1, 3, MX1_GPIO_INT_PORTD), + DEFINE_IMX_GPIO_PORT_IRQ(MX1, 0, 1, MX1_GPIO_INT_PORTA), + DEFINE_IMX_GPIO_PORT_IRQ(MX1, 1, 2, MX1_GPIO_INT_PORTB), + DEFINE_IMX_GPIO_PORT_IRQ(MX1, 2, 3, MX1_GPIO_INT_PORTC), + DEFINE_IMX_GPIO_PORT_IRQ(MX1, 3, 4, MX1_GPIO_INT_PORTD), }; DEFINE_REGISTER_FUNCTION(imx1) @@ -383,26 +383,38 @@ DEFINE_REGISTER_FUNCTION(imx1) #if defined(CONFIG_SOC_IMX21) static struct mxc_gpio_port imx21_gpio_ports[] = { - DEFINE_IMX_GPIO_PORT_IRQ(MX21, 0, MX21_INT_GPIO), - DEFINE_IMX_GPIO_PORT(MX21, 1), - DEFINE_IMX_GPIO_PORT(MX21, 2), - DEFINE_IMX_GPIO_PORT(MX21, 3), - DEFINE_IMX_GPIO_PORT(MX21, 4), - DEFINE_IMX_GPIO_PORT(MX21, 5), + DEFINE_IMX_GPIO_PORT_IRQ(MX21, 0, 1, MX21_INT_GPIO), + DEFINE_IMX_GPIO_PORT(MX21, 1, 2), + DEFINE_IMX_GPIO_PORT(MX21, 2, 3), + DEFINE_IMX_GPIO_PORT(MX21, 3, 4), + DEFINE_IMX_GPIO_PORT(MX21, 4, 5), + DEFINE_IMX_GPIO_PORT(MX21, 5, 6), }; DEFINE_REGISTER_FUNCTION(imx21) #endif /* if defined(CONFIG_SOC_IMX21) */ +#if defined(CONFIG_ARCH_MX25) +static struct mxc_gpio_port imx25_gpio_ports[] = { + DEFINE_IMX_GPIO_PORT_IRQ(MX25, 0, 1, MX25_INT_GPIO1), + DEFINE_IMX_GPIO_PORT_IRQ(MX25, 1, 2, MX25_INT_GPIO2), + DEFINE_IMX_GPIO_PORT_IRQ(MX25, 2, 3, MX25_INT_GPIO3), + DEFINE_IMX_GPIO_PORT_IRQ(MX25, 3, 4, MX25_INT_GPIO4), +}; + +DEFINE_REGISTER_FUNCTION(imx25) + +#endif /* if defined(CONFIG_ARCH_MX25) */ + #if defined(CONFIG_SOC_IMX27) static struct mxc_gpio_port imx27_gpio_ports[] = { - DEFINE_IMX_GPIO_PORT_IRQ(MX27, 0, MX27_INT_GPIO), - DEFINE_IMX_GPIO_PORT(MX27, 1), - DEFINE_IMX_GPIO_PORT(MX27, 2), - DEFINE_IMX_GPIO_PORT(MX27, 3), - DEFINE_IMX_GPIO_PORT(MX27, 4), - DEFINE_IMX_GPIO_PORT(MX27, 5), + DEFINE_IMX_GPIO_PORT_IRQ(MX27, 0, 1, MX27_INT_GPIO), + DEFINE_IMX_GPIO_PORT(MX27, 1, 2), + DEFINE_IMX_GPIO_PORT(MX27, 2, 3), + DEFINE_IMX_GPIO_PORT(MX27, 3, 4), + DEFINE_IMX_GPIO_PORT(MX27, 4, 5), + DEFINE_IMX_GPIO_PORT(MX27, 5, 6), }; DEFINE_REGISTER_FUNCTION(imx27) diff --git a/arch/arm/plat-mxc/include/mach/mx1.h b/arch/arm/plat-mxc/include/mach/mx1.h index f1e336e..75d9621 100644 --- a/arch/arm/plat-mxc/include/mach/mx1.h +++ b/arch/arm/plat-mxc/include/mach/mx1.h @@ -65,6 +65,10 @@ #define MX1_CCM_BASE_ADDR (0x1B000 + MX1_IO_BASE_ADDR) #define MX1_SCM_BASE_ADDR (0x1B804 + MX1_IO_BASE_ADDR) #define MX1_GPIO_BASE_ADDR (0x1C000 + MX1_IO_BASE_ADDR) +#define MX1_GPIO1_BASE_ADDR (0x1C000 + MX1_IO_BASE_ADDR) +#define MX1_GPIO2_BASE_ADDR (0x1C100 + MX1_IO_BASE_ADDR) +#define MX1_GPIO3_BASE_ADDR (0x1C200 + MX1_IO_BASE_ADDR) +#define MX1_GPIO4_BASE_ADDR (0x1C300 + MX1_IO_BASE_ADDR) #define MX1_EIM_BASE_ADDR (0x20000 + MX1_IO_BASE_ADDR) #define MX1_SDRAMC_BASE_ADDR (0x21000 + MX1_IO_BASE_ADDR) #define MX1_MMA_BASE_ADDR (0x22000 + MX1_IO_BASE_ADDR) diff --git a/arch/arm/plat-mxc/include/mach/mx21.h b/arch/arm/plat-mxc/include/mach/mx21.h index a82f590..6cd049e 100644 --- a/arch/arm/plat-mxc/include/mach/mx21.h +++ b/arch/arm/plat-mxc/include/mach/mx21.h @@ -48,6 +48,12 @@ #define MX21_SDHC1_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x13000) #define MX21_SDHC2_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x14000) #define MX21_GPIO_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x15000) +#define MX21_GPIO1_BASE_ADDR (MX21_GPIO_BASE_ADDR + 0x000) +#define MX21_GPIO2_BASE_ADDR (MX21_GPIO_BASE_ADDR + 0x100) +#define MX21_GPIO3_BASE_ADDR (MX21_GPIO_BASE_ADDR + 0x200) +#define MX21_GPIO4_BASE_ADDR (MX21_GPIO_BASE_ADDR + 0x300) +#define MX21_GPIO5_BASE_ADDR (MX21_GPIO_BASE_ADDR + 0x400) +#define MX21_GPIO6_BASE_ADDR (MX21_GPIO_BASE_ADDR + 0x500) #define MX21_AUDMUX_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x16000) #define MX21_CSPI3_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x17000) #define MX21_LCDC_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x21000) diff --git a/arch/arm/plat-mxc/include/mach/mx25.h b/arch/arm/plat-mxc/include/mach/mx25.h index cea851f..024bebe 100644 --- a/arch/arm/plat-mxc/include/mach/mx25.h +++ b/arch/arm/plat-mxc/include/mach/mx25.h @@ -66,8 +66,10 @@ #define MX25_INT_SSI1 12 #define MX25_INT_CSPI2 13 #define MX25_INT_CSPI1 14 +#define MX25_INT_GPIO3 16 #define MX25_INT_CSI 17 #define MX25_INT_UART3 18 +#define MX25_INT_GPIO4 23 #define MX25_INT_KPP 24 #define MX25_INT_DRYICE 25 #define MX25_INT_PWM1 26 @@ -84,6 +86,8 @@ #define MX25_INT_CAN1 43 #define MX25_INT_CAN2 44 #define MX25_INT_UART1 45 +#define MX25_INT_GPIO2 51 +#define MX25_INT_GPIO1 52 #define MX25_INT_FEC 57 #define MX25_DMA_REQ_SSI2_RX1 22 diff --git a/arch/arm/plat-mxc/include/mach/mx27.h b/arch/arm/plat-mxc/include/mach/mx27.h index 45419b3..eb09ec0 100644 --- a/arch/arm/plat-mxc/include/mach/mx27.h +++ b/arch/arm/plat-mxc/include/mach/mx27.h @@ -51,6 +51,12 @@ #define MX27_SDHC1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x13000) #define MX27_SDHC2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x14000) #define MX27_GPIO_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x15000) +#define MX27_GPIO1_BASE_ADDR (MX27_GPIO_BASE_ADDR + 0x000) +#define MX27_GPIO2_BASE_ADDR (MX27_GPIO_BASE_ADDR + 0x100) +#define MX27_GPIO3_BASE_ADDR (MX27_GPIO_BASE_ADDR + 0x200) +#define MX27_GPIO4_BASE_ADDR (MX27_GPIO_BASE_ADDR + 0x300) +#define MX27_GPIO5_BASE_ADDR (MX27_GPIO_BASE_ADDR + 0x400) +#define MX27_GPIO6_BASE_ADDR (MX27_GPIO_BASE_ADDR + 0x500) #define MX27_AUDMUX_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x16000) #define MX27_CSPI3_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x17000) #define MX27_MSHC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x18000) -- cgit v1.1 From ab9cee4b2167f8bf01d85b537df5b9cbe342c780 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Thu, 11 Nov 2010 11:35:33 +0100 Subject: ARM: mx25: dynamically allocate imx-keypad devices MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The mxc-keypad device seems to be the result of an early and partial merge of the keypad driver. It's unused and there is no corresponding driver available, so just remove it. Cc: Alberto Panizzo Signed-off-by: Uwe Kleine-König --- arch/arm/plat-mxc/devices/platform-imx-keypad.c | 14 ++++++++++---- arch/arm/plat-mxc/include/mach/devices-common.h | 1 + 2 files changed, 11 insertions(+), 4 deletions(-) (limited to 'arch/arm/plat-mxc') diff --git a/arch/arm/plat-mxc/devices/platform-imx-keypad.c b/arch/arm/plat-mxc/devices/platform-imx-keypad.c index fdfee55..5995e81 100644 --- a/arch/arm/plat-mxc/devices/platform-imx-keypad.c +++ b/arch/arm/plat-mxc/devices/platform-imx-keypad.c @@ -9,20 +9,26 @@ #include #include -#define imx_imx_keypad_data_entry_single(soc) \ +#define imx_imx_keypad_data_entry_single(soc, _size) \ { \ .iobase = soc ## _KPP_BASE_ADDR, \ + .iosize = _size, \ .irq = soc ## _INT_KPP, \ } #ifdef CONFIG_SOC_IMX21 const struct imx_imx_keypad_data imx21_imx_keypad_data __initconst = - imx_imx_keypad_data_entry_single(MX21); + imx_imx_keypad_data_entry_single(MX21, SZ_16); #endif /* ifdef CONFIG_SOC_IMX21 */ +#ifdef CONFIG_ARCH_MX25 +const struct imx_imx_keypad_data imx25_imx_keypad_data __initconst = + imx_imx_keypad_data_entry_single(MX25, SZ_16K); +#endif + #ifdef CONFIG_SOC_IMX27 const struct imx_imx_keypad_data imx27_imx_keypad_data __initconst = - imx_imx_keypad_data_entry_single(MX27); + imx_imx_keypad_data_entry_single(MX27, SZ_16); #endif /* ifdef CONFIG_SOC_IMX27 */ struct platform_device *__init imx_add_imx_keypad( @@ -32,7 +38,7 @@ struct platform_device *__init imx_add_imx_keypad( struct resource res[] = { { .start = data->iobase, - .end = data->iobase + SZ_16 - 1, + .end = data->iobase + data->iosize - 1, .flags = IORESOURCE_MEM, }, { .start = data->irq, diff --git a/arch/arm/plat-mxc/include/mach/devices-common.h b/arch/arm/plat-mxc/include/mach/devices-common.h index 07223b2..8482613 100644 --- a/arch/arm/plat-mxc/include/mach/devices-common.h +++ b/arch/arm/plat-mxc/include/mach/devices-common.h @@ -95,6 +95,7 @@ struct platform_device *__init imx_add_imx_i2c( #include struct imx_imx_keypad_data { resource_size_t iobase; + resource_size_t iosize; resource_size_t irq; }; struct platform_device *__init imx_add_imx_keypad( -- cgit v1.1 From e7c74b343091e0c6b7bb67c12f9f7fb345aa6a50 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Thu, 11 Nov 2010 11:57:21 +0100 Subject: ARM: mx25: dynamically allocate imxdi_rtc devices MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Uwe Kleine-König --- arch/arm/plat-mxc/devices/Kconfig | 3 ++ arch/arm/plat-mxc/devices/Makefile | 1 + arch/arm/plat-mxc/devices/platform-imxdi_rtc.c | 41 +++++++++++++++++++++++++ arch/arm/plat-mxc/include/mach/devices-common.h | 7 +++++ 4 files changed, 52 insertions(+) create mode 100644 arch/arm/plat-mxc/devices/platform-imxdi_rtc.c (limited to 'arch/arm/plat-mxc') diff --git a/arch/arm/plat-mxc/devices/Kconfig b/arch/arm/plat-mxc/devices/Kconfig index a0be2df..81d7a54 100644 --- a/arch/arm/plat-mxc/devices/Kconfig +++ b/arch/arm/plat-mxc/devices/Kconfig @@ -22,6 +22,9 @@ config IMX_HAVE_PLATFORM_IMX21_HCD config IMX_HAVE_PLATFORM_IMX2_WDT bool +config IMX_HAVE_PLATFORM_IMXDI_RTC + bool + config IMX_HAVE_PLATFORM_IMX_FB bool diff --git a/arch/arm/plat-mxc/devices/Makefile b/arch/arm/plat-mxc/devices/Makefile index 14b228e..f1c3767 100644 --- a/arch/arm/plat-mxc/devices/Makefile +++ b/arch/arm/plat-mxc/devices/Makefile @@ -5,6 +5,7 @@ obj-$(CONFIG_IMX_HAVE_PLATFORM_FSL_USB2_UDC) += platform-fsl-usb2-udc.o obj-$(CONFIG_IMX_HAVE_PLATFORM_GPIO_KEYS) += platform-gpio_keys.o obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX21_HCD) += platform-imx21-hcd.o obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX2_WDT) += platform-imx2-wdt.o +obj-$(CONFIG_IMX_HAVE_PLATFORM_IMXDI_RTC) += platform-imxdi_rtc.o obj-y += platform-imx-dma.o obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_FB) += platform-imx-fb.o obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_I2C) += platform-imx-i2c.o diff --git a/arch/arm/plat-mxc/devices/platform-imxdi_rtc.c b/arch/arm/plat-mxc/devices/platform-imxdi_rtc.c new file mode 100644 index 0000000..387f650 --- /dev/null +++ b/arch/arm/plat-mxc/devices/platform-imxdi_rtc.c @@ -0,0 +1,41 @@ +/* + * Copyright (C) 2010 Pengutronix + * Uwe Kleine-Koenig + * + * This program is free software; you can redistribute it and/or modify it under + * the terms of the GNU General Public License version 2 as published by the + * Free Software Foundation. + */ +#include +#include +#include + +#define imx_imxdi_rtc_data_entry_single(soc) \ + { \ + .iobase = soc ## _DRYICE_BASE_ADDR, \ + .irq = soc ## _INT_DRYICE, \ + } + +#ifdef CONFIG_ARCH_MX25 +const struct imx_imxdi_rtc_data imx25_imxdi_rtc_data __initconst = + imx_imxdi_rtc_data_entry_single(MX25); +#endif /* ifdef CONFIG_ARCH_MX25 */ + +struct platform_device *__init imx_add_imxdi_rtc( + const struct imx_imxdi_rtc_data *data) +{ + struct resource res[] = { + { + .start = data->iobase, + .end = data->iobase + SZ_16K, + .flags = IORESOURCE_MEM, + }, { + .start = data->irq, + .end = data->irq, + .flags = IORESOURCE_IRQ, + }, + }; + + return imx_add_platform_device("imxdi_rtc", 0, + res, ARRAY_SIZE(res), NULL, 0); +} diff --git a/arch/arm/plat-mxc/include/mach/devices-common.h b/arch/arm/plat-mxc/include/mach/devices-common.h index 8482613..4d4b28b 100644 --- a/arch/arm/plat-mxc/include/mach/devices-common.h +++ b/arch/arm/plat-mxc/include/mach/devices-common.h @@ -72,6 +72,13 @@ struct imx_imx2_wdt_data { struct platform_device *__init imx_add_imx2_wdt( const struct imx_imx2_wdt_data *data); +struct imx_imxdi_rtc_data { + resource_size_t iobase; + resource_size_t irq; +}; +struct platform_device *__init imx_add_imxdi_rtc( + const struct imx_imxdi_rtc_data *data); + #include struct imx_imx_fb_data { resource_size_t iobase; -- cgit v1.1 From 194ee8e89cc02d8bea8a0b837271f79ca0c72873 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Thu, 11 Nov 2010 15:32:21 +0100 Subject: ARM: mx25: dynamically allocatate imx-fb devices MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Uwe Kleine-König --- arch/arm/plat-mxc/devices/platform-imx-fb.c | 14 ++++++++++---- arch/arm/plat-mxc/include/mach/devices-common.h | 1 + 2 files changed, 11 insertions(+), 4 deletions(-) (limited to 'arch/arm/plat-mxc') diff --git a/arch/arm/plat-mxc/devices/platform-imx-fb.c b/arch/arm/plat-mxc/devices/platform-imx-fb.c index 42ed3be..f228ba6 100644 --- a/arch/arm/plat-mxc/devices/platform-imx-fb.c +++ b/arch/arm/plat-mxc/devices/platform-imx-fb.c @@ -9,20 +9,26 @@ #include #include -#define imx_imx_fb_data_entry_single(soc) \ +#define imx_imx_fb_data_entry_single(soc, _size) \ { \ .iobase = soc ## _LCDC_BASE_ADDR, \ + .iosize = _size, \ .irq = soc ## _INT_LCDC, \ } #ifdef CONFIG_SOC_IMX21 const struct imx_imx_fb_data imx21_imx_fb_data __initconst = - imx_imx_fb_data_entry_single(MX21); + imx_imx_fb_data_entry_single(MX21, SZ_4K); #endif /* ifdef CONFIG_SOC_IMX21 */ +#ifdef CONFIG_ARCH_MX25 +const struct imx_imx_fb_data imx25_imx_fb_data __initconst = + imx_imx_fb_data_entry_single(MX25, SZ_16K); +#endif + #ifdef CONFIG_SOC_IMX27 const struct imx_imx_fb_data imx27_imx_fb_data __initconst = - imx_imx_fb_data_entry_single(MX27); + imx_imx_fb_data_entry_single(MX27, SZ_4K); #endif /* ifdef CONFIG_SOC_IMX27 */ struct platform_device *__init imx_add_imx_fb( @@ -32,7 +38,7 @@ struct platform_device *__init imx_add_imx_fb( struct resource res[] = { { .start = data->iobase, - .end = data->iobase + SZ_4K - 1, + .end = data->iobase + data->iosize - 1, .flags = IORESOURCE_MEM, }, { .start = data->irq, diff --git a/arch/arm/plat-mxc/include/mach/devices-common.h b/arch/arm/plat-mxc/include/mach/devices-common.h index 4d4b28b..e28453e 100644 --- a/arch/arm/plat-mxc/include/mach/devices-common.h +++ b/arch/arm/plat-mxc/include/mach/devices-common.h @@ -82,6 +82,7 @@ struct platform_device *__init imx_add_imxdi_rtc( #include struct imx_imx_fb_data { resource_size_t iobase; + resource_size_t iosize; resource_size_t irq; }; struct platform_device *__init imx_add_imx_fb( -- cgit v1.1 From 00871505dcf15418aebc402db9f124dd2738fa2d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Thu, 11 Nov 2010 16:58:50 +0100 Subject: ARM: mx25: dynamically allocate imx2-wdt devices MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Uwe Kleine-König --- arch/arm/plat-mxc/devices/platform-imx2-wdt.c | 14 ++++++++++---- arch/arm/plat-mxc/include/mach/devices-common.h | 1 + 2 files changed, 11 insertions(+), 4 deletions(-) (limited to 'arch/arm/plat-mxc') diff --git a/arch/arm/plat-mxc/devices/platform-imx2-wdt.c b/arch/arm/plat-mxc/devices/platform-imx2-wdt.c index 86eb7f1..8446e25 100644 --- a/arch/arm/plat-mxc/devices/platform-imx2-wdt.c +++ b/arch/arm/plat-mxc/devices/platform-imx2-wdt.c @@ -10,19 +10,25 @@ #include #include -#define imx_imx2_wdt_data_entry_single(soc) \ +#define imx_imx2_wdt_data_entry_single(soc, _size) \ { \ .iobase = soc ## _WDOG_BASE_ADDR, \ + .iosize = _size, \ } #ifdef CONFIG_SOC_IMX21 const struct imx_imx2_wdt_data imx21_imx2_wdt_data __initconst = - imx_imx2_wdt_data_entry_single(MX21); + imx_imx2_wdt_data_entry_single(MX21, SZ_4K); #endif /* ifdef CONFIG_SOC_IMX21 */ +#ifdef CONFIG_ARCH_MX25 +const struct imx_imx2_wdt_data imx25_imx2_wdt_data __initconst = + imx_imx2_wdt_data_entry_single(MX25, SZ_16K); +#endif /* ifdef CONFIG_ARCH_MX25 */ + #ifdef CONFIG_SOC_IMX27 const struct imx_imx2_wdt_data imx27_imx2_wdt_data __initconst = - imx_imx2_wdt_data_entry_single(MX27); + imx_imx2_wdt_data_entry_single(MX27, SZ_4K); #endif /* ifdef CONFIG_SOC_IMX27 */ struct platform_device *__init imx_add_imx2_wdt( @@ -31,7 +37,7 @@ struct platform_device *__init imx_add_imx2_wdt( struct resource res[] = { { .start = data->iobase, - .end = data->iobase + SZ_4K - 1, + .end = data->iobase + data->iosize - 1, .flags = IORESOURCE_MEM, }, }; diff --git a/arch/arm/plat-mxc/include/mach/devices-common.h b/arch/arm/plat-mxc/include/mach/devices-common.h index e28453e..95331ae 100644 --- a/arch/arm/plat-mxc/include/mach/devices-common.h +++ b/arch/arm/plat-mxc/include/mach/devices-common.h @@ -68,6 +68,7 @@ struct platform_device *__init imx_add_imx21_hcd( struct imx_imx2_wdt_data { resource_size_t iobase; + resource_size_t iosize; }; struct platform_device *__init imx_add_imx2_wdt( const struct imx_imx2_wdt_data *data); -- cgit v1.1 From bb4c853ff18fe3b0e2aec45053c318479e0c55e3 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Thu, 11 Nov 2010 17:11:34 +0100 Subject: ARM: mx25: dynamically allocate mx2-camera devices MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Uwe Kleine-König --- arch/arm/plat-mxc/devices/platform-mx2-camera.c | 23 +++++++++++++++++------ 1 file changed, 17 insertions(+), 6 deletions(-) (limited to 'arch/arm/plat-mxc') diff --git a/arch/arm/plat-mxc/devices/platform-mx2-camera.c b/arch/arm/plat-mxc/devices/platform-mx2-camera.c index a18c803..b3f4828 100644 --- a/arch/arm/plat-mxc/devices/platform-mx2-camera.c +++ b/arch/arm/plat-mxc/devices/platform-mx2-camera.c @@ -12,6 +12,12 @@ #define imx_mx2_camera_data_entry_single(soc) \ { \ .iobasecsi = soc ## _CSI_BASE_ADDR, \ + .iosizecsi = SZ_4K, \ + .irqcsi = soc ## _INT_CSI, \ + } +#define imx_mx2_camera_data_entry_single_emma(soc) \ + { \ + .iobasecsi = soc ## _CSI_BASE_ADDR, \ .iosizecsi = SZ_32, \ .irqcsi = soc ## _INT_CSI, \ .iobaseemmaprp = soc ## _EMMAPRP_BASE_ADDR, \ @@ -19,9 +25,14 @@ .irqemmaprp = soc ## _INT_EMMAPRP, \ } +#ifdef CONFIG_SOC_IMX25 +const struct imx_mx2_camera_data imx25_mx2_camera_data __initconst = + imx_mx2_camera_data_entry_single(MX25); +#endif /* ifdef CONFIG_SOC_IMX25 */ + #ifdef CONFIG_SOC_IMX27 const struct imx_mx2_camera_data imx27_mx2_camera_data __initconst = - imx_mx2_camera_data_entry_single(MX27); + imx_mx2_camera_data_entry_single_emma(MX27); #endif /* ifdef CONFIG_SOC_IMX27 */ struct platform_device *__init imx_add_mx2_camera( @@ -34,20 +45,20 @@ struct platform_device *__init imx_add_mx2_camera( .end = data->iobasecsi + data->iosizecsi - 1, .flags = IORESOURCE_MEM, }, { - .start = data->iobaseemmaprp, - .end = data->iobaseemmaprp + data->iosizeemmaprp - 1, - .flags = IORESOURCE_MEM, - }, { .start = data->irqcsi, .end = data->irqcsi, .flags = IORESOURCE_IRQ, }, { + .start = data->iobaseemmaprp, + .end = data->iobaseemmaprp + data->iosizeemmaprp - 1, + .flags = IORESOURCE_MEM, + }, { .start = data->irqemmaprp, .end = data->irqemmaprp, .flags = IORESOURCE_IRQ, }, }; return imx_add_platform_device_dmamask("mx2-camera", 0, - res, ARRAY_SIZE(res), + res, data->iobaseemmaprp ? 4 : 2, pdata, sizeof(*pdata), DMA_BIT_MASK(32)); } -- cgit v1.1 From e48ab1c16ff2af83e6a2a1228504710a5d339d08 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Thu, 11 Nov 2010 18:06:17 +0100 Subject: ARM: imx: move mx25 support to mach-imx MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Uwe Kleine-König --- arch/arm/plat-mxc/Kconfig | 5 ----- 1 file changed, 5 deletions(-) (limited to 'arch/arm/plat-mxc') diff --git a/arch/arm/plat-mxc/Kconfig b/arch/arm/plat-mxc/Kconfig index 64e3a64..a31fa16 100644 --- a/arch/arm/plat-mxc/Kconfig +++ b/arch/arm/plat-mxc/Kconfig @@ -21,10 +21,6 @@ config ARCH_MX2 config ARCH_MX25 bool "MX25-based" - select CPU_ARM926T - select ARCH_MXC_IOMUX_V3 - select HAVE_FB_IMX - select ARCH_MXC_AUDMUX_V2 help This enables support for systems based on the Freescale i.MX25 family @@ -51,7 +47,6 @@ endchoice source "arch/arm/mach-imx/Kconfig" source "arch/arm/mach-mx3/Kconfig" -source "arch/arm/mach-mx25/Kconfig" source "arch/arm/mach-mxc91231/Kconfig" source "arch/arm/mach-mx5/Kconfig" -- cgit v1.1 From fd2fa2e3238197ef10101277dff67da10e68a61b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Thu, 11 Nov 2010 18:11:29 +0100 Subject: ARM: imx: let IMX_HAVE_PLATFORM_IMX_FB select HAVE_FB_IMX MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This way FB_IMX can just depend on HAVE_FB_IMX and machines just need to select IMX_HAVE_PLATFORM_IMX_FB without bothering about HAVE_FB_IMX. Signed-off-by: Uwe Kleine-König --- arch/arm/plat-mxc/devices/Kconfig | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm/plat-mxc') diff --git a/arch/arm/plat-mxc/devices/Kconfig b/arch/arm/plat-mxc/devices/Kconfig index 81d7a54..dbb2078 100644 --- a/arch/arm/plat-mxc/devices/Kconfig +++ b/arch/arm/plat-mxc/devices/Kconfig @@ -27,6 +27,7 @@ config IMX_HAVE_PLATFORM_IMXDI_RTC config IMX_HAVE_PLATFORM_IMX_FB bool + select HAVE_FB_IMX config IMX_HAVE_PLATFORM_IMX_I2C bool -- cgit v1.1 From 972cc48207450ce6aeed416ac176fe4d0482a4a3 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Thu, 11 Nov 2010 18:35:01 +0100 Subject: ARM: imx: use SOC_IMX25 instead of ARCH_MX25 for multi-SoC MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Some usages of ARCH_MX25 are assuming that if it is defined the other SoCs are undefined. Use SOC_IMX25 for the save places. Signed-off-by: Uwe Kleine-König --- arch/arm/plat-mxc/audmux-v2.c | 4 ++-- arch/arm/plat-mxc/devices/platform-esdhc.c | 4 ++-- arch/arm/plat-mxc/devices/platform-fec.c | 4 ++-- arch/arm/plat-mxc/devices/platform-flexcan.c | 4 ++-- arch/arm/plat-mxc/devices/platform-fsl-usb2-udc.c | 4 ++-- arch/arm/plat-mxc/devices/platform-imx-dma.c | 6 +++--- arch/arm/plat-mxc/devices/platform-imx-fb.c | 4 ++-- arch/arm/plat-mxc/devices/platform-imx-i2c.c | 4 ++-- arch/arm/plat-mxc/devices/platform-imx-keypad.c | 4 ++-- arch/arm/plat-mxc/devices/platform-imx-ssi.c | 4 ++-- arch/arm/plat-mxc/devices/platform-imx-uart.c | 4 ++-- arch/arm/plat-mxc/devices/platform-imx2-wdt.c | 4 ++-- arch/arm/plat-mxc/devices/platform-imxdi_rtc.c | 4 ++-- arch/arm/plat-mxc/devices/platform-mxc-ehci.c | 4 ++-- arch/arm/plat-mxc/devices/platform-mxc_nand.c | 4 ++-- arch/arm/plat-mxc/devices/platform-mxc_pwm.c | 4 ++-- arch/arm/plat-mxc/devices/platform-spi_imx.c | 4 ++-- arch/arm/plat-mxc/ehci.c | 4 ++-- arch/arm/plat-mxc/gpio.c | 4 ++-- 19 files changed, 39 insertions(+), 39 deletions(-) (limited to 'arch/arm/plat-mxc') diff --git a/arch/arm/plat-mxc/audmux-v2.c b/arch/arm/plat-mxc/audmux-v2.c index 0be1ac7..175e364 100644 --- a/arch/arm/plat-mxc/audmux-v2.c +++ b/arch/arm/plat-mxc/audmux-v2.c @@ -209,7 +209,7 @@ static int mxc_audmux_v2_init(void) audmux_base = MX35_IO_ADDRESS(MX35_AUDMUX_BASE_ADDR); } #endif -#if defined(CONFIG_ARCH_MX25) +#if defined(CONFIG_SOC_IMX25) if (cpu_is_mx25()) { audmux_clk = clk_get(NULL, "audmux"); if (IS_ERR(audmux_clk)) { @@ -220,7 +220,7 @@ static int mxc_audmux_v2_init(void) } audmux_base = MX25_IO_ADDRESS(MX25_AUDMUX_BASE_ADDR); } -#endif +#endif /* if defined(CONFIG_SOC_IMX25) */ audmux_debugfs_init(); return 0; diff --git a/arch/arm/plat-mxc/devices/platform-esdhc.c b/arch/arm/plat-mxc/devices/platform-esdhc.c index 2605bfa..87df70b 100644 --- a/arch/arm/plat-mxc/devices/platform-esdhc.c +++ b/arch/arm/plat-mxc/devices/platform-esdhc.c @@ -20,14 +20,14 @@ #define imx_esdhc_imx_data_entry(soc, id, hwid) \ [id] = imx_esdhc_imx_data_entry_single(soc, id, hwid) -#ifdef CONFIG_ARCH_MX25 +#ifdef CONFIG_SOC_IMX25 const struct imx_esdhc_imx_data imx25_esdhc_data[] __initconst = { #define imx25_esdhc_data_entry(_id, _hwid) \ imx_esdhc_imx_data_entry(MX25, _id, _hwid) imx25_esdhc_data_entry(0, 1), imx25_esdhc_data_entry(1, 2), }; -#endif /* ifdef CONFIG_ARCH_MX25 */ +#endif /* ifdef CONFIG_SOC_IMX25 */ #ifdef CONFIG_ARCH_MX35 const struct imx_esdhc_imx_data imx35_esdhc_data[] __initconst = { diff --git a/arch/arm/plat-mxc/devices/platform-fec.c b/arch/arm/plat-mxc/devices/platform-fec.c index 11d087f..e6a365e 100644 --- a/arch/arm/plat-mxc/devices/platform-fec.c +++ b/arch/arm/plat-mxc/devices/platform-fec.c @@ -16,10 +16,10 @@ .irq = soc ## _INT_FEC, \ } -#ifdef CONFIG_ARCH_MX25 +#ifdef CONFIG_SOC_IMX25 const struct imx_fec_data imx25_fec_data __initconst = imx_fec_data_entry_single(MX25); -#endif /* ifdef CONFIG_ARCH_MX25 */ +#endif /* ifdef CONFIG_SOC_IMX25 */ #ifdef CONFIG_SOC_IMX27 const struct imx_fec_data imx27_fec_data __initconst = diff --git a/arch/arm/plat-mxc/devices/platform-flexcan.c b/arch/arm/plat-mxc/devices/platform-flexcan.c index 5189017..f10db6f 100644 --- a/arch/arm/plat-mxc/devices/platform-flexcan.c +++ b/arch/arm/plat-mxc/devices/platform-flexcan.c @@ -19,14 +19,14 @@ #define imx_flexcan_data_entry(soc, _id, _hwid, _size) \ [_id] = imx_flexcan_data_entry_single(soc, _id, _hwid, _size) -#ifdef CONFIG_ARCH_MX25 +#ifdef CONFIG_SOC_IMX25 const struct imx_flexcan_data imx25_flexcan_data[] __initconst = { #define imx25_flexcan_data_entry(_id, _hwid) \ imx_flexcan_data_entry(MX25, _id, _hwid, SZ_16K) imx25_flexcan_data_entry(0, 1), imx25_flexcan_data_entry(1, 2), }; -#endif /* ifdef CONFIG_ARCH_MX25 */ +#endif /* ifdef CONFIG_SOC_IMX25 */ #ifdef CONFIG_ARCH_MX35 const struct imx_flexcan_data imx35_flexcan_data[] __initconst = { diff --git a/arch/arm/plat-mxc/devices/platform-fsl-usb2-udc.c b/arch/arm/plat-mxc/devices/platform-fsl-usb2-udc.c index cb5fb71..42c3923 100644 --- a/arch/arm/plat-mxc/devices/platform-fsl-usb2-udc.c +++ b/arch/arm/plat-mxc/devices/platform-fsl-usb2-udc.c @@ -15,10 +15,10 @@ .irq = soc ## _INT_USB_OTG, \ } -#ifdef CONFIG_ARCH_MX25 +#ifdef CONFIG_SOC_IMX25 const struct imx_fsl_usb2_udc_data imx25_fsl_usb2_udc_data __initconst = imx_fsl_usb2_udc_data_entry_single(MX25); -#endif +#endif /* ifdef CONFIG_SOC_IMX25 */ #ifdef CONFIG_SOC_IMX27 const struct imx_fsl_usb2_udc_data imx27_fsl_usb2_udc_data __initconst = diff --git a/arch/arm/plat-mxc/devices/platform-imx-dma.c b/arch/arm/plat-mxc/devices/platform-imx-dma.c index 02d9890..cbafd93 100644 --- a/arch/arm/plat-mxc/devices/platform-imx-dma.c +++ b/arch/arm/plat-mxc/devices/platform-imx-dma.c @@ -39,10 +39,10 @@ struct imx_imx_sdma_data { }, \ } -#ifdef CONFIG_ARCH_MX25 +#ifdef CONFIG_SOC_IMX25 const struct imx_imx_sdma_data imx25_imx_sdma_data __initconst = imx_imx_sdma_data_entry_single(MX25, 1, "imx25", 0); -#endif /* ifdef CONFIG_ARCH_MX25 */ +#endif /* ifdef CONFIG_SOC_IMX25 */ #ifdef CONFIG_ARCH_MX31 struct imx_imx_sdma_data imx31_imx_sdma_data __initdata = @@ -94,7 +94,7 @@ static int __init imxXX_add_imx_dma(void) else #endif -#if defined(CONFIG_ARCH_MX25) +#if defined(CONFIG_SOC_IMX25) if (cpu_is_mx25()) ret = imx_add_imx_sdma(&imx25_imx_sdma_data); else diff --git a/arch/arm/plat-mxc/devices/platform-imx-fb.c b/arch/arm/plat-mxc/devices/platform-imx-fb.c index f228ba6..6100a7d 100644 --- a/arch/arm/plat-mxc/devices/platform-imx-fb.c +++ b/arch/arm/plat-mxc/devices/platform-imx-fb.c @@ -21,10 +21,10 @@ const struct imx_imx_fb_data imx21_imx_fb_data __initconst = imx_imx_fb_data_entry_single(MX21, SZ_4K); #endif /* ifdef CONFIG_SOC_IMX21 */ -#ifdef CONFIG_ARCH_MX25 +#ifdef CONFIG_SOC_IMX25 const struct imx_imx_fb_data imx25_imx_fb_data __initconst = imx_imx_fb_data_entry_single(MX25, SZ_16K); -#endif +#endif /* ifdef CONFIG_SOC_IMX25 */ #ifdef CONFIG_SOC_IMX27 const struct imx_imx_fb_data imx27_imx_fb_data __initconst = diff --git a/arch/arm/plat-mxc/devices/platform-imx-i2c.c b/arch/arm/plat-mxc/devices/platform-imx-i2c.c index 6795884..2cb0232 100644 --- a/arch/arm/plat-mxc/devices/platform-imx-i2c.c +++ b/arch/arm/plat-mxc/devices/platform-imx-i2c.c @@ -30,7 +30,7 @@ const struct imx_imx_i2c_data imx21_imx_i2c_data __initconst = imx_imx_i2c_data_entry_single(MX21, 0, , SZ_4K); #endif /* ifdef CONFIG_SOC_IMX21 */ -#ifdef CONFIG_ARCH_MX25 +#ifdef CONFIG_SOC_IMX25 const struct imx_imx_i2c_data imx25_imx_i2c_data[] __initconst = { #define imx25_imx_i2c_data_entry(_id, _hwid) \ imx_imx_i2c_data_entry(MX25, _id, _hwid, SZ_16K) @@ -38,7 +38,7 @@ const struct imx_imx_i2c_data imx25_imx_i2c_data[] __initconst = { imx25_imx_i2c_data_entry(1, 2), imx25_imx_i2c_data_entry(2, 3), }; -#endif /* ifdef CONFIG_ARCH_MX25 */ +#endif /* ifdef CONFIG_SOC_IMX25 */ #ifdef CONFIG_SOC_IMX27 const struct imx_imx_i2c_data imx27_imx_i2c_data[] __initconst = { diff --git a/arch/arm/plat-mxc/devices/platform-imx-keypad.c b/arch/arm/plat-mxc/devices/platform-imx-keypad.c index 5995e81..5f3b367 100644 --- a/arch/arm/plat-mxc/devices/platform-imx-keypad.c +++ b/arch/arm/plat-mxc/devices/platform-imx-keypad.c @@ -21,10 +21,10 @@ const struct imx_imx_keypad_data imx21_imx_keypad_data __initconst = imx_imx_keypad_data_entry_single(MX21, SZ_16); #endif /* ifdef CONFIG_SOC_IMX21 */ -#ifdef CONFIG_ARCH_MX25 +#ifdef CONFIG_SOC_IMX25 const struct imx_imx_keypad_data imx25_imx_keypad_data __initconst = imx_imx_keypad_data_entry_single(MX25, SZ_16K); -#endif +#endif /* ifdef CONFIG_SOC_IMX25 */ #ifdef CONFIG_SOC_IMX27 const struct imx_imx_keypad_data imx27_imx_keypad_data __initconst = diff --git a/arch/arm/plat-mxc/devices/platform-imx-ssi.c b/arch/arm/plat-mxc/devices/platform-imx-ssi.c index 38a7a0b..d6410e1 100644 --- a/arch/arm/plat-mxc/devices/platform-imx-ssi.c +++ b/arch/arm/plat-mxc/devices/platform-imx-ssi.c @@ -30,14 +30,14 @@ const struct imx_imx_ssi_data imx21_imx_ssi_data[] __initconst = { }; #endif /* ifdef CONFIG_SOC_IMX21 */ -#ifdef CONFIG_ARCH_MX25 +#ifdef CONFIG_SOC_IMX25 const struct imx_imx_ssi_data imx25_imx_ssi_data[] __initconst = { #define imx25_imx_ssi_data_entry(_id, _hwid) \ imx_imx_ssi_data_entry(MX25, _id, _hwid, SZ_4K) imx25_imx_ssi_data_entry(0, 1), imx25_imx_ssi_data_entry(1, 2), }; -#endif /* ifdef CONFIG_ARCH_MX25 */ +#endif /* ifdef CONFIG_SOC_IMX25 */ #ifdef CONFIG_SOC_IMX27 const struct imx_imx_ssi_data imx27_imx_ssi_data[] __initconst = { diff --git a/arch/arm/plat-mxc/devices/platform-imx-uart.c b/arch/arm/plat-mxc/devices/platform-imx-uart.c index 2039640..b10c736 100644 --- a/arch/arm/plat-mxc/devices/platform-imx-uart.c +++ b/arch/arm/plat-mxc/devices/platform-imx-uart.c @@ -47,7 +47,7 @@ const struct imx_imx_uart_1irq_data imx21_imx_uart_data[] __initconst = { }; #endif -#ifdef CONFIG_ARCH_MX25 +#ifdef CONFIG_SOC_IMX25 const struct imx_imx_uart_1irq_data imx25_imx_uart_data[] __initconst = { #define imx25_imx_uart_data_entry(_id, _hwid) \ imx_imx_uart_1irq_data_entry(MX25, _id, _hwid, SZ_16K) @@ -57,7 +57,7 @@ const struct imx_imx_uart_1irq_data imx25_imx_uart_data[] __initconst = { imx25_imx_uart_data_entry(3, 4), imx25_imx_uart_data_entry(4, 5), }; -#endif /* ifdef CONFIG_ARCH_MX25 */ +#endif /* ifdef CONFIG_SOC_IMX25 */ #ifdef CONFIG_SOC_IMX27 const struct imx_imx_uart_1irq_data imx27_imx_uart_data[] __initconst = { diff --git a/arch/arm/plat-mxc/devices/platform-imx2-wdt.c b/arch/arm/plat-mxc/devices/platform-imx2-wdt.c index 8446e25..d2c97aa 100644 --- a/arch/arm/plat-mxc/devices/platform-imx2-wdt.c +++ b/arch/arm/plat-mxc/devices/platform-imx2-wdt.c @@ -21,10 +21,10 @@ const struct imx_imx2_wdt_data imx21_imx2_wdt_data __initconst = imx_imx2_wdt_data_entry_single(MX21, SZ_4K); #endif /* ifdef CONFIG_SOC_IMX21 */ -#ifdef CONFIG_ARCH_MX25 +#ifdef CONFIG_SOC_IMX25 const struct imx_imx2_wdt_data imx25_imx2_wdt_data __initconst = imx_imx2_wdt_data_entry_single(MX25, SZ_16K); -#endif /* ifdef CONFIG_ARCH_MX25 */ +#endif /* ifdef CONFIG_SOC_IMX25 */ #ifdef CONFIG_SOC_IMX27 const struct imx_imx2_wdt_data imx27_imx2_wdt_data __initconst = diff --git a/arch/arm/plat-mxc/devices/platform-imxdi_rtc.c b/arch/arm/plat-mxc/devices/platform-imxdi_rtc.c index 387f650..10653cc 100644 --- a/arch/arm/plat-mxc/devices/platform-imxdi_rtc.c +++ b/arch/arm/plat-mxc/devices/platform-imxdi_rtc.c @@ -16,10 +16,10 @@ .irq = soc ## _INT_DRYICE, \ } -#ifdef CONFIG_ARCH_MX25 +#ifdef CONFIG_SOC_IMX25 const struct imx_imxdi_rtc_data imx25_imxdi_rtc_data __initconst = imx_imxdi_rtc_data_entry_single(MX25); -#endif /* ifdef CONFIG_ARCH_MX25 */ +#endif /* ifdef CONFIG_SOC_IMX25 */ struct platform_device *__init imx_add_imxdi_rtc( const struct imx_imxdi_rtc_data *data) diff --git a/arch/arm/plat-mxc/devices/platform-mxc-ehci.c b/arch/arm/plat-mxc/devices/platform-mxc-ehci.c index 825a048..9bec63f 100644 --- a/arch/arm/plat-mxc/devices/platform-mxc-ehci.c +++ b/arch/arm/plat-mxc/devices/platform-mxc-ehci.c @@ -16,12 +16,12 @@ .irq = soc ## _INT_USB_ ## hs, \ } -#ifdef CONFIG_ARCH_MX25 +#ifdef CONFIG_SOC_IMX25 const struct imx_mxc_ehci_data imx25_mxc_ehci_otg_data __initconst = imx_mxc_ehci_data_entry_single(MX25, 0, OTG); const struct imx_mxc_ehci_data imx25_mxc_ehci_hs_data __initconst = imx_mxc_ehci_data_entry_single(MX25, 1, HS); -#endif /* ifdef CONFIG_ARCH_MX25 */ +#endif /* ifdef CONFIG_SOC_IMX25 */ #ifdef CONFIG_SOC_IMX27 const struct imx_mxc_ehci_data imx27_mxc_ehci_otg_data __initconst = diff --git a/arch/arm/plat-mxc/devices/platform-mxc_nand.c b/arch/arm/plat-mxc/devices/platform-mxc_nand.c index 3fdcc32..967d847 100644 --- a/arch/arm/plat-mxc/devices/platform-mxc_nand.c +++ b/arch/arm/plat-mxc/devices/platform-mxc_nand.c @@ -31,10 +31,10 @@ const struct imx_mxc_nand_data imx21_mxc_nand_data __initconst = imx_mxc_nand_data_entry_single(MX21, SZ_4K); #endif /* ifdef CONFIG_SOC_IMX21 */ -#ifdef CONFIG_ARCH_MX25 +#ifdef CONFIG_SOC_IMX25 const struct imx_mxc_nand_data imx25_mxc_nand_data __initconst = imx_mxc_nand_data_entry_single(MX25, SZ_8K); -#endif /* ifdef CONFIG_ARCH_MX25 */ +#endif /* ifdef CONFIG_SOC_IMX25 */ #ifdef CONFIG_SOC_IMX27 const struct imx_mxc_nand_data imx27_mxc_nand_data __initconst = diff --git a/arch/arm/plat-mxc/devices/platform-mxc_pwm.c b/arch/arm/plat-mxc/devices/platform-mxc_pwm.c index 5a47d1e..3d8ebdb 100644 --- a/arch/arm/plat-mxc/devices/platform-mxc_pwm.c +++ b/arch/arm/plat-mxc/devices/platform-mxc_pwm.c @@ -24,7 +24,7 @@ const struct imx_mxc_pwm_data imx21_mxc_pwm_data __initconst = imx_mxc_pwm_data_entry_single(MX21, 0, , SZ_4K); #endif /* ifdef CONFIG_SOC_IMX21 */ -#ifdef CONFIG_ARCH_MX25 +#ifdef CONFIG_SOC_IMX25 const struct imx_mxc_pwm_data imx25_mxc_pwm_data[] __initconst = { #define imx25_mxc_pwm_data_entry(_id, _hwid) \ imx_mxc_pwm_data_entry(MX25, _id, _hwid, SZ_16K) @@ -33,7 +33,7 @@ const struct imx_mxc_pwm_data imx25_mxc_pwm_data[] __initconst = { imx25_mxc_pwm_data_entry(2, 3), imx25_mxc_pwm_data_entry(3, 4), }; -#endif +#endif /* ifdef CONFIG_SOC_IMX25 */ #ifdef CONFIG_SOC_IMX27 const struct imx_mxc_pwm_data imx27_mxc_pwm_data __initconst = diff --git a/arch/arm/plat-mxc/devices/platform-spi_imx.c b/arch/arm/plat-mxc/devices/platform-spi_imx.c index e48340e..bf2cb47 100644 --- a/arch/arm/plat-mxc/devices/platform-spi_imx.c +++ b/arch/arm/plat-mxc/devices/platform-spi_imx.c @@ -29,7 +29,7 @@ const struct imx_spi_imx_data imx21_cspi_data[] __initconst = { imx21_cspi_data_entry(1, 2), #endif -#ifdef CONFIG_ARCH_MX25 +#ifdef CONFIG_SOC_IMX25 const struct imx_spi_imx_data imx25_cspi_data[] __initconst = { #define imx25_cspi_data_entry(_id, _hwid) \ imx_spi_imx_data_entry(MX25, CSPI, "imx25-cspi", _id, _hwid, SZ_16K) @@ -37,7 +37,7 @@ const struct imx_spi_imx_data imx25_cspi_data[] __initconst = { imx25_cspi_data_entry(1, 2), imx25_cspi_data_entry(2, 3), }; -#endif /* ifdef CONFIG_ARCH_MX25 */ +#endif /* ifdef CONFIG_SOC_IMX25 */ #ifdef CONFIG_SOC_IMX27 const struct imx_spi_imx_data imx27_cspi_data[] __initconst = { diff --git a/arch/arm/plat-mxc/ehci.c b/arch/arm/plat-mxc/ehci.c index f699235..4bac3d5 100644 --- a/arch/arm/plat-mxc/ehci.c +++ b/arch/arm/plat-mxc/ehci.c @@ -69,7 +69,7 @@ int mxc_initialize_usb_hw(int port, unsigned int flags) { unsigned int v; -#if defined(CONFIG_ARCH_MX25) +#if defined(CONFIG_SOC_IMX25) if (cpu_is_mx25()) { v = readl(MX25_IO_ADDRESS(MX25_USB_BASE_ADDR + USBCTRL_OTGBASE_OFFSET)); @@ -112,7 +112,7 @@ int mxc_initialize_usb_hw(int port, unsigned int flags) USBCTRL_OTGBASE_OFFSET)); return 0; } -#endif /* CONFIG_ARCH_MX25 */ +#endif /* if defined(CONFIG_SOC_IMX25) */ #if defined(CONFIG_ARCH_MX3) if (cpu_is_mx31()) { v = readl(MX31_IO_ADDRESS(MX31_OTG_BASE_ADDR + diff --git a/arch/arm/plat-mxc/gpio.c b/arch/arm/plat-mxc/gpio.c index e59fb97..c853bfa 100644 --- a/arch/arm/plat-mxc/gpio.c +++ b/arch/arm/plat-mxc/gpio.c @@ -395,7 +395,7 @@ DEFINE_REGISTER_FUNCTION(imx21) #endif /* if defined(CONFIG_SOC_IMX21) */ -#if defined(CONFIG_ARCH_MX25) +#if defined(CONFIG_SOC_IMX25) static struct mxc_gpio_port imx25_gpio_ports[] = { DEFINE_IMX_GPIO_PORT_IRQ(MX25, 0, 1, MX25_INT_GPIO1), DEFINE_IMX_GPIO_PORT_IRQ(MX25, 1, 2, MX25_INT_GPIO2), @@ -405,7 +405,7 @@ static struct mxc_gpio_port imx25_gpio_ports[] = { DEFINE_REGISTER_FUNCTION(imx25) -#endif /* if defined(CONFIG_ARCH_MX25) */ +#endif /* if defined(CONFIG_SOC_IMX25) */ #if defined(CONFIG_SOC_IMX27) static struct mxc_gpio_port imx27_gpio_ports[] = { -- cgit v1.1 From d7e0951f929513ced7c57882d2f95d49a546e002 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Thu, 11 Nov 2010 18:50:50 +0100 Subject: ARM: mx3: move registration of gpios to plat-mxc/gpio.c MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Uwe Kleine-König --- arch/arm/plat-mxc/gpio.c | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) (limited to 'arch/arm/plat-mxc') diff --git a/arch/arm/plat-mxc/gpio.c b/arch/arm/plat-mxc/gpio.c index c853bfa..2fb1efa 100644 --- a/arch/arm/plat-mxc/gpio.c +++ b/arch/arm/plat-mxc/gpio.c @@ -420,3 +420,25 @@ static struct mxc_gpio_port imx27_gpio_ports[] = { DEFINE_REGISTER_FUNCTION(imx27) #endif /* if defined(CONFIG_SOC_IMX27) */ + +#if defined(CONFIG_ARCH_MX31) +static struct mxc_gpio_port imx31_gpio_ports[] = { + DEFINE_IMX_GPIO_PORT_IRQ(MX31, 0, 1, MX31_INT_GPIO1), + DEFINE_IMX_GPIO_PORT_IRQ(MX31, 1, 2, MX31_INT_GPIO2), + DEFINE_IMX_GPIO_PORT_IRQ(MX31, 2, 3, MX31_INT_GPIO3), +}; + +DEFINE_REGISTER_FUNCTION(imx31) + +#endif /* if defined(CONFIG_ARCH_MX31) */ + +#if defined(CONFIG_ARCH_MX35) +static struct mxc_gpio_port imx35_gpio_ports[] = { + DEFINE_IMX_GPIO_PORT_IRQ(MX35, 0, 1, MX35_INT_GPIO1), + DEFINE_IMX_GPIO_PORT_IRQ(MX35, 1, 2, MX35_INT_GPIO2), + DEFINE_IMX_GPIO_PORT_IRQ(MX35, 2, 3, MX35_INT_GPIO3), +}; + +DEFINE_REGISTER_FUNCTION(imx35) + +#endif /* if defined(CONFIG_ARCH_MX35) */ -- cgit v1.1 From a528bc87841d958bbd394abc9266aee9cdf45cb8 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Fri, 12 Nov 2010 10:11:42 +0100 Subject: ARM: mx3: introduce SOC_IMX31 and SOC_IMX35 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Additionally convert some known to be good usages to the new names. Signed-off-by: Uwe Kleine-König --- arch/arm/plat-mxc/devices/Kconfig | 2 +- arch/arm/plat-mxc/devices/platform-esdhc.c | 4 ++-- arch/arm/plat-mxc/devices/platform-fec.c | 2 +- arch/arm/plat-mxc/devices/platform-flexcan.c | 4 ++-- arch/arm/plat-mxc/devices/platform-imx-dma.c | 12 ++++++------ arch/arm/plat-mxc/devices/platform-imx-i2c.c | 8 ++++---- arch/arm/plat-mxc/devices/platform-imx-ssi.c | 8 ++++---- arch/arm/plat-mxc/devices/platform-imx-uart.c | 8 ++++---- arch/arm/plat-mxc/devices/platform-mxc_nand.c | 4 ++-- arch/arm/plat-mxc/devices/platform-mxc_w1.c | 8 ++++---- arch/arm/plat-mxc/devices/platform-spi_imx.c | 8 ++++---- arch/arm/plat-mxc/gpio.c | 8 ++++---- 12 files changed, 38 insertions(+), 38 deletions(-) (limited to 'arch/arm/plat-mxc') diff --git a/arch/arm/plat-mxc/devices/Kconfig b/arch/arm/plat-mxc/devices/Kconfig index dbb2078..1be4476 100644 --- a/arch/arm/plat-mxc/devices/Kconfig +++ b/arch/arm/plat-mxc/devices/Kconfig @@ -3,7 +3,7 @@ config IMX_HAVE_PLATFORM_ESDHC config IMX_HAVE_PLATFORM_FEC bool - default y if ARCH_MX25 || SOC_IMX27 || ARCH_MX35 || ARCH_MX51 + default y if ARCH_MX25 || SOC_IMX27 || SOC_IMX35 || ARCH_MX51 config IMX_HAVE_PLATFORM_FLEXCAN select HAVE_CAN_FLEXCAN if CAN diff --git a/arch/arm/plat-mxc/devices/platform-esdhc.c b/arch/arm/plat-mxc/devices/platform-esdhc.c index 87df70b..013e92f 100644 --- a/arch/arm/plat-mxc/devices/platform-esdhc.c +++ b/arch/arm/plat-mxc/devices/platform-esdhc.c @@ -29,7 +29,7 @@ const struct imx_esdhc_imx_data imx25_esdhc_data[] __initconst = { }; #endif /* ifdef CONFIG_SOC_IMX25 */ -#ifdef CONFIG_ARCH_MX35 +#ifdef CONFIG_SOC_IMX35 const struct imx_esdhc_imx_data imx35_esdhc_data[] __initconst = { #define imx35_esdhc_data_entry(_id, _hwid) \ imx_esdhc_imx_data_entry(MX35, _id, _hwid) @@ -37,7 +37,7 @@ const struct imx_esdhc_imx_data imx35_esdhc_data[] __initconst = { imx35_esdhc_data_entry(1, 2), imx35_esdhc_data_entry(2, 3), }; -#endif /* ifdef CONFIG_ARCH_MX35 */ +#endif /* ifdef CONFIG_SOC_IMX35 */ #ifdef CONFIG_ARCH_MX51 const struct imx_esdhc_imx_data imx51_esdhc_data[] __initconst = { diff --git a/arch/arm/plat-mxc/devices/platform-fec.c b/arch/arm/plat-mxc/devices/platform-fec.c index e6a365e..8d78aed 100644 --- a/arch/arm/plat-mxc/devices/platform-fec.c +++ b/arch/arm/plat-mxc/devices/platform-fec.c @@ -26,7 +26,7 @@ const struct imx_fec_data imx27_fec_data __initconst = imx_fec_data_entry_single(MX27); #endif /* ifdef CONFIG_SOC_IMX27 */ -#ifdef CONFIG_ARCH_MX35 +#ifdef CONFIG_SOC_IMX35 const struct imx_fec_data imx35_fec_data __initconst = imx_fec_data_entry_single(MX35); #endif diff --git a/arch/arm/plat-mxc/devices/platform-flexcan.c b/arch/arm/plat-mxc/devices/platform-flexcan.c index f10db6f..4e8497a 100644 --- a/arch/arm/plat-mxc/devices/platform-flexcan.c +++ b/arch/arm/plat-mxc/devices/platform-flexcan.c @@ -28,14 +28,14 @@ const struct imx_flexcan_data imx25_flexcan_data[] __initconst = { }; #endif /* ifdef CONFIG_SOC_IMX25 */ -#ifdef CONFIG_ARCH_MX35 +#ifdef CONFIG_SOC_IMX35 const struct imx_flexcan_data imx35_flexcan_data[] __initconst = { #define imx35_flexcan_data_entry(_id, _hwid) \ imx_flexcan_data_entry(MX35, _id, _hwid, SZ_16K) imx35_flexcan_data_entry(0, 1), imx35_flexcan_data_entry(1, 2), }; -#endif /* ifdef CONFIG_ARCH_MX35 */ +#endif /* ifdef CONFIG_SOC_IMX35 */ struct platform_device *__init imx_add_flexcan( const struct imx_flexcan_data *data, diff --git a/arch/arm/plat-mxc/devices/platform-imx-dma.c b/arch/arm/plat-mxc/devices/platform-imx-dma.c index cbafd93..10f41cc 100644 --- a/arch/arm/plat-mxc/devices/platform-imx-dma.c +++ b/arch/arm/plat-mxc/devices/platform-imx-dma.c @@ -44,15 +44,15 @@ const struct imx_imx_sdma_data imx25_imx_sdma_data __initconst = imx_imx_sdma_data_entry_single(MX25, 1, "imx25", 0); #endif /* ifdef CONFIG_SOC_IMX25 */ -#ifdef CONFIG_ARCH_MX31 +#ifdef CONFIG_SOC_IMX31 struct imx_imx_sdma_data imx31_imx_sdma_data __initdata = imx_imx_sdma_data_entry_single(MX31, 1, "imx31", 0); -#endif /* ifdef CONFIG_ARCH_MX31 */ +#endif /* ifdef CONFIG_SOC_IMX31 */ -#ifdef CONFIG_ARCH_MX35 +#ifdef CONFIG_SOC_IMX35 struct imx_imx_sdma_data imx35_imx_sdma_data __initdata = imx_imx_sdma_data_entry_single(MX35, 2, "imx35", 0); -#endif /* ifdef CONFIG_ARCH_MX35 */ +#endif /* ifdef CONFIG_SOC_IMX35 */ #ifdef CONFIG_ARCH_MX51 const struct imx_imx_sdma_data imx51_imx_sdma_data __initconst = @@ -100,14 +100,14 @@ static int __init imxXX_add_imx_dma(void) else #endif -#if defined(CONFIG_ARCH_MX31) +#if defined(CONFIG_SOC_IMX31) if (cpu_is_mx31()) { imx31_imx_sdma_data.pdata.to_version = mx31_revision() >> 4; ret = imx_add_imx_sdma(&imx31_imx_sdma_data); } else #endif -#if defined(CONFIG_ARCH_MX35) +#if defined(CONFIG_SOC_IMX35) if (cpu_is_mx35()) { imx35_imx_sdma_data.pdata.to_version = mx35_revision() >> 4; ret = imx_add_imx_sdma(&imx35_imx_sdma_data); diff --git a/arch/arm/plat-mxc/devices/platform-imx-i2c.c b/arch/arm/plat-mxc/devices/platform-imx-i2c.c index 2cb0232..075bd8e 100644 --- a/arch/arm/plat-mxc/devices/platform-imx-i2c.c +++ b/arch/arm/plat-mxc/devices/platform-imx-i2c.c @@ -49,7 +49,7 @@ const struct imx_imx_i2c_data imx27_imx_i2c_data[] __initconst = { }; #endif /* ifdef CONFIG_SOC_IMX27 */ -#ifdef CONFIG_ARCH_MX31 +#ifdef CONFIG_SOC_IMX31 const struct imx_imx_i2c_data imx31_imx_i2c_data[] __initconst = { #define imx31_imx_i2c_data_entry(_id, _hwid) \ imx_imx_i2c_data_entry(MX31, _id, _hwid, SZ_4K) @@ -57,9 +57,9 @@ const struct imx_imx_i2c_data imx31_imx_i2c_data[] __initconst = { imx31_imx_i2c_data_entry(1, 2), imx31_imx_i2c_data_entry(2, 3), }; -#endif /* ifdef CONFIG_ARCH_MX31 */ +#endif /* ifdef CONFIG_SOC_IMX31 */ -#ifdef CONFIG_ARCH_MX35 +#ifdef CONFIG_SOC_IMX35 const struct imx_imx_i2c_data imx35_imx_i2c_data[] __initconst = { #define imx35_imx_i2c_data_entry(_id, _hwid) \ imx_imx_i2c_data_entry(MX35, _id, _hwid, SZ_4K) @@ -67,7 +67,7 @@ const struct imx_imx_i2c_data imx35_imx_i2c_data[] __initconst = { imx35_imx_i2c_data_entry(1, 2), imx35_imx_i2c_data_entry(2, 3), }; -#endif /* ifdef CONFIG_ARCH_MX35 */ +#endif /* ifdef CONFIG_SOC_IMX35 */ #ifdef CONFIG_ARCH_MX51 const struct imx_imx_i2c_data imx51_imx_i2c_data[] __initconst = { diff --git a/arch/arm/plat-mxc/devices/platform-imx-ssi.c b/arch/arm/plat-mxc/devices/platform-imx-ssi.c index d6410e1..02002fc 100644 --- a/arch/arm/plat-mxc/devices/platform-imx-ssi.c +++ b/arch/arm/plat-mxc/devices/platform-imx-ssi.c @@ -48,23 +48,23 @@ const struct imx_imx_ssi_data imx27_imx_ssi_data[] __initconst = { }; #endif /* ifdef CONFIG_SOC_IMX27 */ -#ifdef CONFIG_ARCH_MX31 +#ifdef CONFIG_SOC_IMX31 const struct imx_imx_ssi_data imx31_imx_ssi_data[] __initconst = { #define imx31_imx_ssi_data_entry(_id, _hwid) \ imx_imx_ssi_data_entry(MX31, _id, _hwid, SZ_4K) imx31_imx_ssi_data_entry(0, 1), imx31_imx_ssi_data_entry(1, 2), }; -#endif /* ifdef CONFIG_ARCH_MX31 */ +#endif /* ifdef CONFIG_SOC_IMX31 */ -#ifdef CONFIG_ARCH_MX35 +#ifdef CONFIG_SOC_IMX35 const struct imx_imx_ssi_data imx35_imx_ssi_data[] __initconst = { #define imx35_imx_ssi_data_entry(_id, _hwid) \ imx_imx_ssi_data_entry(MX35, _id, _hwid, SZ_4K) imx35_imx_ssi_data_entry(0, 1), imx35_imx_ssi_data_entry(1, 2), }; -#endif /* ifdef CONFIG_ARCH_MX35 */ +#endif /* ifdef CONFIG_SOC_IMX35 */ #ifdef CONFIG_ARCH_MX51 const struct imx_imx_ssi_data imx51_imx_ssi_data[] __initconst = { diff --git a/arch/arm/plat-mxc/devices/platform-imx-uart.c b/arch/arm/plat-mxc/devices/platform-imx-uart.c index b10c736..08bbd65 100644 --- a/arch/arm/plat-mxc/devices/platform-imx-uart.c +++ b/arch/arm/plat-mxc/devices/platform-imx-uart.c @@ -72,7 +72,7 @@ const struct imx_imx_uart_1irq_data imx27_imx_uart_data[] __initconst = { }; #endif /* ifdef CONFIG_SOC_IMX27 */ -#ifdef CONFIG_ARCH_MX31 +#ifdef CONFIG_SOC_IMX31 const struct imx_imx_uart_1irq_data imx31_imx_uart_data[] __initconst = { #define imx31_imx_uart_data_entry(_id, _hwid) \ imx_imx_uart_1irq_data_entry(MX31, _id, _hwid, SZ_4K) @@ -82,9 +82,9 @@ const struct imx_imx_uart_1irq_data imx31_imx_uart_data[] __initconst = { imx31_imx_uart_data_entry(3, 4), imx31_imx_uart_data_entry(4, 5), }; -#endif /* ifdef CONFIG_ARCH_MX31 */ +#endif /* ifdef CONFIG_SOC_IMX31 */ -#ifdef CONFIG_ARCH_MX35 +#ifdef CONFIG_SOC_IMX35 const struct imx_imx_uart_1irq_data imx35_imx_uart_data[] __initconst = { #define imx35_imx_uart_data_entry(_id, _hwid) \ imx_imx_uart_1irq_data_entry(MX31, _id, _hwid, SZ_16K) @@ -92,7 +92,7 @@ const struct imx_imx_uart_1irq_data imx35_imx_uart_data[] __initconst = { imx35_imx_uart_data_entry(1, 2), imx35_imx_uart_data_entry(2, 3), }; -#endif /* ifdef CONFIG_ARCH_MX35 */ +#endif /* ifdef CONFIG_SOC_IMX35 */ #ifdef CONFIG_ARCH_MX51 const struct imx_imx_uart_1irq_data imx51_imx_uart_data[] __initconst = { diff --git a/arch/arm/plat-mxc/devices/platform-mxc_nand.c b/arch/arm/plat-mxc/devices/platform-mxc_nand.c index 967d847..f5beac0 100644 --- a/arch/arm/plat-mxc/devices/platform-mxc_nand.c +++ b/arch/arm/plat-mxc/devices/platform-mxc_nand.c @@ -41,12 +41,12 @@ const struct imx_mxc_nand_data imx27_mxc_nand_data __initconst = imx_mxc_nand_data_entry_single(MX27, SZ_4K); #endif /* ifdef CONFIG_SOC_IMX27 */ -#ifdef CONFIG_ARCH_MX31 +#ifdef CONFIG_SOC_IMX31 const struct imx_mxc_nand_data imx31_mxc_nand_data __initconst = imx_mxc_nand_data_entry_single(MX31, SZ_4K); #endif -#ifdef CONFIG_ARCH_MX35 +#ifdef CONFIG_SOC_IMX35 const struct imx_mxc_nand_data imx35_mxc_nand_data __initconst = imx_mxc_nand_data_entry_single(MX35, SZ_8K); #endif diff --git a/arch/arm/plat-mxc/devices/platform-mxc_w1.c b/arch/arm/plat-mxc/devices/platform-mxc_w1.c index 1355237..96fa5ea 100644 --- a/arch/arm/plat-mxc/devices/platform-mxc_w1.c +++ b/arch/arm/plat-mxc/devices/platform-mxc_w1.c @@ -24,15 +24,15 @@ const struct imx_mxc_w1_data imx27_mxc_w1_data __initconst = imx_mxc_w1_data_entry_single(MX27); #endif /* ifdef CONFIG_SOC_IMX27 */ -#ifdef CONFIG_ARCH_MX31 +#ifdef CONFIG_SOC_IMX31 const struct imx_mxc_w1_data imx31_mxc_w1_data __initconst = imx_mxc_w1_data_entry_single(MX31); -#endif /* ifdef CONFIG_ARCH_MX31 */ +#endif /* ifdef CONFIG_SOC_IMX31 */ -#ifdef CONFIG_ARCH_MX35 +#ifdef CONFIG_SOC_IMX35 const struct imx_mxc_w1_data imx35_mxc_w1_data __initconst = imx_mxc_w1_data_entry_single(MX35); -#endif /* ifdef CONFIG_ARCH_MX35 */ +#endif /* ifdef CONFIG_SOC_IMX35 */ struct platform_device *__init imx_add_mxc_w1( const struct imx_mxc_w1_data *data) diff --git a/arch/arm/plat-mxc/devices/platform-spi_imx.c b/arch/arm/plat-mxc/devices/platform-spi_imx.c index bf2cb47..8f2b60a 100644 --- a/arch/arm/plat-mxc/devices/platform-spi_imx.c +++ b/arch/arm/plat-mxc/devices/platform-spi_imx.c @@ -49,7 +49,7 @@ const struct imx_spi_imx_data imx27_cspi_data[] __initconst = { }; #endif /* ifdef CONFIG_SOC_IMX27 */ -#ifdef CONFIG_ARCH_MX31 +#ifdef CONFIG_SOC_IMX31 const struct imx_spi_imx_data imx31_cspi_data[] __initconst = { #define imx31_cspi_data_entry(_id, _hwid) \ imx_spi_imx_data_entry(MX31, CSPI, "imx31-cspi", _id, _hwid, SZ_4K) @@ -57,16 +57,16 @@ const struct imx_spi_imx_data imx31_cspi_data[] __initconst = { imx31_cspi_data_entry(1, 2), imx31_cspi_data_entry(2, 3), }; -#endif /* ifdef CONFIG_ARCH_MX31 */ +#endif /* ifdef CONFIG_SOC_IMX31 */ -#ifdef CONFIG_ARCH_MX35 +#ifdef CONFIG_SOC_IMX35 const struct imx_spi_imx_data imx35_cspi_data[] __initconst = { #define imx35_cspi_data_entry(_id, _hwid) \ imx_spi_imx_data_entry(MX35, CSPI, "imx35-cspi", _id, _hwid, SZ_4K) imx35_cspi_data_entry(0, 1), imx35_cspi_data_entry(1, 2), }; -#endif /* ifdef CONFIG_ARCH_MX35 */ +#endif /* ifdef CONFIG_SOC_IMX35 */ #ifdef CONFIG_ARCH_MX51 const struct imx_spi_imx_data imx51_cspi_data __initconst = diff --git a/arch/arm/plat-mxc/gpio.c b/arch/arm/plat-mxc/gpio.c index 2fb1efa..93a8d93 100644 --- a/arch/arm/plat-mxc/gpio.c +++ b/arch/arm/plat-mxc/gpio.c @@ -421,7 +421,7 @@ DEFINE_REGISTER_FUNCTION(imx27) #endif /* if defined(CONFIG_SOC_IMX27) */ -#if defined(CONFIG_ARCH_MX31) +#if defined(CONFIG_SOC_IMX31) static struct mxc_gpio_port imx31_gpio_ports[] = { DEFINE_IMX_GPIO_PORT_IRQ(MX31, 0, 1, MX31_INT_GPIO1), DEFINE_IMX_GPIO_PORT_IRQ(MX31, 1, 2, MX31_INT_GPIO2), @@ -430,9 +430,9 @@ static struct mxc_gpio_port imx31_gpio_ports[] = { DEFINE_REGISTER_FUNCTION(imx31) -#endif /* if defined(CONFIG_ARCH_MX31) */ +#endif /* if defined(CONFIG_SOC_IMX31) */ -#if defined(CONFIG_ARCH_MX35) +#if defined(CONFIG_SOC_IMX35) static struct mxc_gpio_port imx35_gpio_ports[] = { DEFINE_IMX_GPIO_PORT_IRQ(MX35, 0, 1, MX35_INT_GPIO1), DEFINE_IMX_GPIO_PORT_IRQ(MX35, 1, 2, MX35_INT_GPIO2), @@ -441,4 +441,4 @@ static struct mxc_gpio_port imx35_gpio_ports[] = { DEFINE_REGISTER_FUNCTION(imx35) -#endif /* if defined(CONFIG_ARCH_MX35) */ +#endif /* if defined(CONFIG_SOC_IMX35) */ -- cgit v1.1 From 6a697e3d310d79ea0e385975c57084ce22b04b36 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Fri, 12 Nov 2010 11:10:55 +0100 Subject: ARM: mx3: dynamically register mxc-mmc devices MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Compared to the static devices the dynamic have a DMA resource. This should be save as it seems unused in the driver. Signed-off-by: Uwe Kleine-König --- arch/arm/plat-mxc/devices/platform-mxc-mmc.c | 20 +++++++++++++++----- arch/arm/plat-mxc/include/mach/devices-common.h | 1 + arch/arm/plat-mxc/include/mach/mx31.h | 10 ++++++---- 3 files changed, 22 insertions(+), 9 deletions(-) (limited to 'arch/arm/plat-mxc') diff --git a/arch/arm/plat-mxc/devices/platform-mxc-mmc.c b/arch/arm/plat-mxc/devices/platform-mxc-mmc.c index 953319e..90d762f 100644 --- a/arch/arm/plat-mxc/devices/platform-mxc-mmc.c +++ b/arch/arm/plat-mxc/devices/platform-mxc-mmc.c @@ -9,20 +9,21 @@ #include #include -#define imx_mxc_mmc_data_entry_single(soc, _id, _hwid) \ +#define imx_mxc_mmc_data_entry_single(soc, _id, _hwid, _size) \ { \ .id = _id, \ .iobase = soc ## _SDHC ## _hwid ## _BASE_ADDR, \ + .iosize = _size, \ .irq = soc ## _INT_SDHC ## _hwid, \ .dmareq = soc ## _DMA_REQ_SDHC ## _hwid, \ } -#define imx_mxc_mmc_data_entry(soc, _id, _hwid) \ - [_id] = imx_mxc_mmc_data_entry_single(soc, _id, _hwid) +#define imx_mxc_mmc_data_entry(soc, _id, _hwid, _size) \ + [_id] = imx_mxc_mmc_data_entry_single(soc, _id, _hwid, _size) #ifdef CONFIG_SOC_IMX21 const struct imx_mxc_mmc_data imx21_mxc_mmc_data[] __initconst = { #define imx21_mxc_mmc_data_entry(_id, _hwid) \ - imx_mxc_mmc_data_entry(MX21, _id, _hwid) + imx_mxc_mmc_data_entry(MX21, _id, _hwid, SZ_4K) imx21_mxc_mmc_data_entry(0, 1), imx21_mxc_mmc_data_entry(1, 2), }; @@ -31,12 +32,21 @@ const struct imx_mxc_mmc_data imx21_mxc_mmc_data[] __initconst = { #ifdef CONFIG_SOC_IMX27 const struct imx_mxc_mmc_data imx27_mxc_mmc_data[] __initconst = { #define imx27_mxc_mmc_data_entry(_id, _hwid) \ - imx_mxc_mmc_data_entry(MX27, _id, _hwid) + imx_mxc_mmc_data_entry(MX27, _id, _hwid, SZ_4K) imx27_mxc_mmc_data_entry(0, 1), imx27_mxc_mmc_data_entry(1, 2), }; #endif /* ifdef CONFIG_SOC_IMX27 */ +#ifdef CONFIG_SOC_IMX31 +const struct imx_mxc_mmc_data imx31_mxc_mmc_data[] __initconst = { +#define imx31_mxc_mmc_data_entry(_id, _hwid) \ + imx_mxc_mmc_data_entry(MX31, _id, _hwid, SZ_16K) + imx31_mxc_mmc_data_entry(0, 1), + imx31_mxc_mmc_data_entry(1, 2), +}; +#endif /* ifdef CONFIG_SOC_IMX31 */ + struct platform_device *__init imx_add_mxc_mmc( const struct imx_mxc_mmc_data *data, const struct imxmmc_platform_data *pdata) diff --git a/arch/arm/plat-mxc/include/mach/devices-common.h b/arch/arm/plat-mxc/include/mach/devices-common.h index 95331ae..5a62dc4 100644 --- a/arch/arm/plat-mxc/include/mach/devices-common.h +++ b/arch/arm/plat-mxc/include/mach/devices-common.h @@ -202,6 +202,7 @@ struct platform_device *__init imx_add_mxc_ehci( struct imx_mxc_mmc_data { int id; resource_size_t iobase; + resource_size_t iosize; resource_size_t irq; resource_size_t dmareq; }; diff --git a/arch/arm/plat-mxc/include/mach/mx31.h b/arch/arm/plat-mxc/include/mach/mx31.h index 6d4b98f..d024c9c 100644 --- a/arch/arm/plat-mxc/include/mach/mx31.h +++ b/arch/arm/plat-mxc/include/mach/mx31.h @@ -41,8 +41,8 @@ #define MX31_SPBA0_BASE_ADDR 0x50000000 #define MX31_SPBA0_SIZE SZ_1M -#define MX31_MMC_SDHC1_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x04000) -#define MX31_MMC_SDHC2_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x08000) +#define MX31_SDHC1_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x04000) +#define MX31_SDHC2_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x08000) #define MX31_UART3_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x0c000) #define MX31_CSPI2_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x10000) #define MX31_SSI2_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x14000) @@ -134,8 +134,8 @@ static inline void mx31_setup_weimcs(size_t cs, #define MX31_INT_MPEG4_ENCODER 5 #define MX31_INT_RTIC 6 #define MX31_INT_FIRI 7 -#define MX31_INT_MMC_SDHC2 8 -#define MX31_INT_MMC_SDHC1 9 +#define MX31_INT_SDHC2 8 +#define MX31_INT_SDHC1 9 #define MX31_INT_I2C1 10 #define MX31_INT_SSI2 11 #define MX31_INT_SSI1 12 @@ -188,6 +188,8 @@ static inline void mx31_setup_weimcs(size_t cs, #define MX31_INT_EXT_WDOG 62 #define MX31_INT_EXT_TV 63 +#define MX31_DMA_REQ_SDHC1 20 +#define MX31_DMA_REQ_SDHC2 21 #define MX31_DMA_REQ_SSI2_RX1 22 #define MX31_DMA_REQ_SSI2_TX1 23 #define MX31_DMA_REQ_SSI2_RX0 24 -- cgit v1.1 From fed3d35b06bf3f6a3383c2637d054823c563200b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Fri, 12 Nov 2010 11:49:34 +0100 Subject: ARM: mx3: dynamically allocate mxc_rnga devices MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Uwe Kleine-König --- arch/arm/plat-mxc/devices/Kconfig | 4 ++ arch/arm/plat-mxc/devices/Makefile | 1 + arch/arm/plat-mxc/devices/platform-mxc_rnga.c | 56 +++++++++++++++++++++++++++ 3 files changed, 61 insertions(+) create mode 100644 arch/arm/plat-mxc/devices/platform-mxc_rnga.c (limited to 'arch/arm/plat-mxc') diff --git a/arch/arm/plat-mxc/devices/Kconfig b/arch/arm/plat-mxc/devices/Kconfig index 1be4476..f34c139 100644 --- a/arch/arm/plat-mxc/devices/Kconfig +++ b/arch/arm/plat-mxc/devices/Kconfig @@ -62,6 +62,10 @@ config IMX_HAVE_PLATFORM_MXC_NAND config IMX_HAVE_PLATFORM_MXC_PWM bool +config IMX_HAVE_PLATFORM_MXC_RNGA + bool + select ARCH_HAS_RNGA + config IMX_HAVE_PLATFORM_MXC_W1 bool diff --git a/arch/arm/plat-mxc/devices/Makefile b/arch/arm/plat-mxc/devices/Makefile index f1c3767..91fdd6c 100644 --- a/arch/arm/plat-mxc/devices/Makefile +++ b/arch/arm/plat-mxc/devices/Makefile @@ -19,5 +19,6 @@ obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_EHCI) += platform-mxc-ehci.o obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_MMC) += platform-mxc-mmc.o obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_NAND) += platform-mxc_nand.o obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_PWM) += platform-mxc_pwm.o +obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_RNGA) += platform-mxc_rnga.o obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_W1) += platform-mxc_w1.o obj-$(CONFIG_IMX_HAVE_PLATFORM_SPI_IMX) += platform-spi_imx.o diff --git a/arch/arm/plat-mxc/devices/platform-mxc_rnga.c b/arch/arm/plat-mxc/devices/platform-mxc_rnga.c new file mode 100644 index 0000000..b4b7612 --- /dev/null +++ b/arch/arm/plat-mxc/devices/platform-mxc_rnga.c @@ -0,0 +1,56 @@ +/* + * Copyright (C) 2010 Pengutronix + * Uwe Kleine-Koenig + * + * This program is free software; you can redistribute it and/or modify it under + * the terms of the GNU General Public License version 2 as published by the + * Free Software Foundation. + */ +#include +#include + +struct imx_mxc_rnga_data { + resource_size_t iobase; +}; + +#define imx_mxc_rnga_data_entry_single(soc) \ + { \ + .iobase = soc ## _RNGA_BASE_ADDR, \ + } + +#ifdef CONFIG_SOC_IMX31 +static const struct imx_mxc_rnga_data imx31_mxc_rnga_data __initconst = + imx_mxc_rnga_data_entry_single(MX31); +#endif /* ifdef CONFIG_SOC_IMX31 */ + +static struct platform_device *__init imx_add_mxc_rnga( + const struct imx_mxc_rnga_data *data) +{ + struct resource res[] = { + { + .start = data->iobase, + .end = data->iobase + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, + }; + return imx_add_platform_device("mxc_rnga", -1, + res, ARRAY_SIZE(res), NULL, 0); +} + +static int __init imxXX_add_mxc_rnga(void) +{ + struct platform_device *ret; + +#if defined(CONFIG_SOC_IMX31) + if (cpu_is_mx31()) + ret = imx_add_mxc_rnga(&imx31_mxc_rnga_data); + else +#endif /* if defined(CONFIG_SOC_IMX31) */ + ret = ERR_PTR(-ENODEV); + + if (IS_ERR(ret)) + return PTR_ERR(ret); + + return 0; +} +arch_initcall(imxXX_add_mxc_rnga); -- cgit v1.1 From 9e1dde33876ba83ad586c336647fff133d0f5472 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Fri, 12 Nov 2010 16:40:06 +0100 Subject: ARM: mx3: dynamically allocate fsl-usb2-udc devices MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit While adapting the #defines for this I noticed that the offset used for USB HS on i.MX35 differs from the documented offset. I kept the working offset and commented that the documentation differs. Signed-off-by: Uwe Kleine-König --- arch/arm/plat-mxc/devices/platform-fsl-usb2-udc.c | 10 ++++++++++ arch/arm/plat-mxc/include/mach/mx31.h | 12 +++++++----- arch/arm/plat-mxc/include/mach/mx35.h | 14 ++++++++++---- 3 files changed, 27 insertions(+), 9 deletions(-) (limited to 'arch/arm/plat-mxc') diff --git a/arch/arm/plat-mxc/devices/platform-fsl-usb2-udc.c b/arch/arm/plat-mxc/devices/platform-fsl-usb2-udc.c index 42c3923..59c33f6 100644 --- a/arch/arm/plat-mxc/devices/platform-fsl-usb2-udc.c +++ b/arch/arm/plat-mxc/devices/platform-fsl-usb2-udc.c @@ -25,6 +25,16 @@ const struct imx_fsl_usb2_udc_data imx27_fsl_usb2_udc_data __initconst = imx_fsl_usb2_udc_data_entry_single(MX27); #endif /* ifdef CONFIG_SOC_IMX27 */ +#ifdef CONFIG_SOC_IMX31 +const struct imx_fsl_usb2_udc_data imx31_fsl_usb2_udc_data __initconst = + imx_fsl_usb2_udc_data_entry_single(MX31); +#endif /* ifdef CONFIG_SOC_IMX31 */ + +#ifdef CONFIG_SOC_IMX35 +const struct imx_fsl_usb2_udc_data imx35_fsl_usb2_udc_data __initconst = + imx_fsl_usb2_udc_data_entry_single(MX35); +#endif /* ifdef CONFIG_SOC_IMX35 */ + struct platform_device *__init imx_add_fsl_usb2_udc( const struct imx_fsl_usb2_udc_data *data, const struct fsl_usb2_platform_data *pdata) diff --git a/arch/arm/plat-mxc/include/mach/mx31.h b/arch/arm/plat-mxc/include/mach/mx31.h index d024c9c..09232314 100644 --- a/arch/arm/plat-mxc/include/mach/mx31.h +++ b/arch/arm/plat-mxc/include/mach/mx31.h @@ -24,7 +24,10 @@ #define MX31_ECT_CTIO_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x18000) #define MX31_I2C1_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x80000) #define MX31_I2C3_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x84000) -#define MX31_OTG_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x88000) +#define MX31_USB_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x88000) +#define MX31_USB_OTG_BASE_ADDR (MX31_USB_BASE_ADDR + 0x0000) +#define MX31_USB_HS1_BASE_ADDR (MX31_USB_BASE_ADDR + 0x0200) +#define MX31_USB_HS2_BASE_ADDR (MX31_USB_BASE_ADDR + 0x0400) #define MX31_ATA_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x8c000) #define MX31_UART1_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x90000) #define MX31_UART2_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x94000) @@ -161,10 +164,9 @@ static inline void mx31_setup_weimcs(size_t cs, #define MX31_INT_UART2 32 #define MX31_INT_NFC 33 #define MX31_INT_SDMA 34 -#define MX31_INT_USB1 35 -#define MX31_INT_USB2 36 -#define MX31_INT_USB3 37 -#define MX31_INT_USB4 38 +#define MX31_INT_USB_HS1 35 +#define MX31_INT_USB_HS2 36 +#define MX31_INT_USB_OTG 37 #define MX31_INT_MSHC1 39 #define MX31_INT_MSHC2 40 #define MX31_INT_IPU_ERR 41 diff --git a/arch/arm/plat-mxc/include/mach/mx35.h b/arch/arm/plat-mxc/include/mach/mx35.h index 9067225..0fa3f68 100644 --- a/arch/arm/plat-mxc/include/mach/mx35.h +++ b/arch/arm/plat-mxc/include/mach/mx35.h @@ -65,8 +65,14 @@ #define MX35_CAN2_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xe8000) #define MX35_RTIC_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xec000) #define MX35_IIM_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xf0000) - -#define MX35_OTG_BASE_ADDR 0x53ff4000 +#define MX35_USB_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xf4000) +#define MX35_USB_OTG_BASE_ADDR (MX35_USB_BASE_ADDR + 0x0000) +/* + * The Reference Manual (IMX35RM, Rev. 2, 3/2009) claims an offset of 0x200 for + * HS. When host support was implemented only a preliminary document was + * available, which told 0x400. This works fine. + */ +#define MX35_USB_HS_BASE_ADDR (MX35_USB_BASE_ADDR + 0x0400) #define MX35_ROMP_BASE_ADDR 0x60000000 #define MX35_ROMP_SIZE SZ_1M @@ -143,8 +149,8 @@ #define MX35_INT_UART2 32 #define MX35_INT_NFC 33 #define MX35_INT_SDMA 34 -#define MX35_INT_USBHS 35 -#define MX35_INT_USBOTG 37 +#define MX35_INT_USB_HS 35 +#define MX35_INT_USB_OTG 37 #define MX35_INT_MSHC1 39 #define MX35_INT_ESAI 40 #define MX35_INT_IPU_ERR 41 -- cgit v1.1 From 2d58de2805f93bdb8fa0608d98e1871bb28ec091 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Mon, 15 Nov 2010 11:57:49 +0100 Subject: ARM: mx3: dynamically allocate mxc-ehci devices MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Uwe Kleine-König --- arch/arm/plat-mxc/devices/platform-mxc-ehci.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) (limited to 'arch/arm/plat-mxc') diff --git a/arch/arm/plat-mxc/devices/platform-mxc-ehci.c b/arch/arm/plat-mxc/devices/platform-mxc-ehci.c index 9bec63f..cc488f4 100644 --- a/arch/arm/plat-mxc/devices/platform-mxc-ehci.c +++ b/arch/arm/plat-mxc/devices/platform-mxc-ehci.c @@ -32,6 +32,22 @@ const struct imx_mxc_ehci_data imx27_mxc_ehci_hs_data[] __initconst = { }; #endif /* ifdef CONFIG_SOC_IMX27 */ +#ifdef CONFIG_SOC_IMX31 +const struct imx_mxc_ehci_data imx31_mxc_ehci_otg_data __initconst = + imx_mxc_ehci_data_entry_single(MX31, 0, OTG); +const struct imx_mxc_ehci_data imx31_mxc_ehci_hs_data[] __initconst = { + imx_mxc_ehci_data_entry_single(MX31, 1, HS1), + imx_mxc_ehci_data_entry_single(MX31, 2, HS2), +}; +#endif /* ifdef CONFIG_SOC_IMX31 */ + +#ifdef CONFIG_SOC_IMX35 +const struct imx_mxc_ehci_data imx35_mxc_ehci_otg_data __initconst = + imx_mxc_ehci_data_entry_single(MX35, 0, OTG); +const struct imx_mxc_ehci_data imx35_mxc_ehci_hs_data __initconst = + imx_mxc_ehci_data_entry_single(MX35, 1, HS); +#endif /* ifdef CONFIG_SOC_IMX35 */ + struct platform_device *__init imx_add_mxc_ehci( const struct imx_mxc_ehci_data *data, const struct mxc_usbh_platform_data *pdata) -- cgit v1.1 From 742269e2d971957c84f364c4e9f5c6439964ef01 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Mon, 15 Nov 2010 15:28:45 +0100 Subject: ARM: mx3: dynamically allocate imx2-wdt devices MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Uwe Kleine-König --- arch/arm/plat-mxc/devices/platform-imx2-wdt.c | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'arch/arm/plat-mxc') diff --git a/arch/arm/plat-mxc/devices/platform-imx2-wdt.c b/arch/arm/plat-mxc/devices/platform-imx2-wdt.c index d2c97aa..c61bd4e 100644 --- a/arch/arm/plat-mxc/devices/platform-imx2-wdt.c +++ b/arch/arm/plat-mxc/devices/platform-imx2-wdt.c @@ -31,6 +31,16 @@ const struct imx_imx2_wdt_data imx27_imx2_wdt_data __initconst = imx_imx2_wdt_data_entry_single(MX27, SZ_4K); #endif /* ifdef CONFIG_SOC_IMX27 */ +#ifdef CONFIG_SOC_IMX31 +const struct imx_imx2_wdt_data imx31_imx2_wdt_data __initconst = + imx_imx2_wdt_data_entry_single(MX31, SZ_16K); +#endif /* ifdef CONFIG_SOC_IMX31 */ + +#ifdef CONFIG_SOC_IMX35 +const struct imx_imx2_wdt_data imx35_imx2_wdt_data __initconst = + imx_imx2_wdt_data_entry_single(MX35, SZ_16K); +#endif /* ifdef CONFIG_SOC_IMX35 */ + struct platform_device *__init imx_add_imx2_wdt( const struct imx_imx2_wdt_data *data) { -- cgit v1.1 From d690b4c4778096cde018709efd005dfef9714297 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Tue, 16 Nov 2010 21:27:33 +0100 Subject: ARM: mx3: dynamically allocate imx-keypad devices MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Uwe Kleine-König --- arch/arm/plat-mxc/devices/platform-imx-keypad.c | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'arch/arm/plat-mxc') diff --git a/arch/arm/plat-mxc/devices/platform-imx-keypad.c b/arch/arm/plat-mxc/devices/platform-imx-keypad.c index 5f3b367..40238f0 100644 --- a/arch/arm/plat-mxc/devices/platform-imx-keypad.c +++ b/arch/arm/plat-mxc/devices/platform-imx-keypad.c @@ -31,6 +31,16 @@ const struct imx_imx_keypad_data imx27_imx_keypad_data __initconst = imx_imx_keypad_data_entry_single(MX27, SZ_16); #endif /* ifdef CONFIG_SOC_IMX27 */ +#ifdef CONFIG_SOC_IMX31 +const struct imx_imx_keypad_data imx31_imx_keypad_data __initconst = + imx_imx_keypad_data_entry_single(MX31, SZ_16); +#endif /* ifdef CONFIG_SOC_IMX31 */ + +#ifdef CONFIG_SOC_IMX35 +const struct imx_imx_keypad_data imx35_imx_keypad_data __initconst = + imx_imx_keypad_data_entry_single(MX35, SZ_16); +#endif /* ifdef CONFIG_SOC_IMX35 */ + struct platform_device *__init imx_add_imx_keypad( const struct imx_imx_keypad_data *data, const struct matrix_keymap_data *pdata) -- cgit v1.1 From 124bf94a9f9b52341562628cd56b252e7d820ee8 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Fri, 19 Nov 2010 21:03:33 +0100 Subject: ARM: imx: fix name for functions adding sdhci-esdhc-imx devices MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit and restore alphabetic ordering. Signed-off-by: Uwe Kleine-König --- arch/arm/plat-mxc/devices/Kconfig | 6 +- arch/arm/plat-mxc/devices/Makefile | 2 +- arch/arm/plat-mxc/devices/platform-esdhc.c | 71 --------------------- .../plat-mxc/devices/platform-sdhci-esdhc-imx.c | 74 ++++++++++++++++++++++ arch/arm/plat-mxc/include/mach/devices-common.h | 20 +++--- 5 files changed, 88 insertions(+), 85 deletions(-) delete mode 100644 arch/arm/plat-mxc/devices/platform-esdhc.c create mode 100644 arch/arm/plat-mxc/devices/platform-sdhci-esdhc-imx.c (limited to 'arch/arm/plat-mxc') diff --git a/arch/arm/plat-mxc/devices/Kconfig b/arch/arm/plat-mxc/devices/Kconfig index f34c139..b391f4d 100644 --- a/arch/arm/plat-mxc/devices/Kconfig +++ b/arch/arm/plat-mxc/devices/Kconfig @@ -1,6 +1,3 @@ -config IMX_HAVE_PLATFORM_ESDHC - bool - config IMX_HAVE_PLATFORM_FEC bool default y if ARCH_MX25 || SOC_IMX27 || SOC_IMX35 || ARCH_MX51 @@ -69,5 +66,8 @@ config IMX_HAVE_PLATFORM_MXC_RNGA config IMX_HAVE_PLATFORM_MXC_W1 bool +config IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX + bool + config IMX_HAVE_PLATFORM_SPI_IMX bool diff --git a/arch/arm/plat-mxc/devices/Makefile b/arch/arm/plat-mxc/devices/Makefile index 91fdd6c..75cd2ec 100644 --- a/arch/arm/plat-mxc/devices/Makefile +++ b/arch/arm/plat-mxc/devices/Makefile @@ -1,4 +1,3 @@ -obj-$(CONFIG_IMX_HAVE_PLATFORM_ESDHC) += platform-esdhc.o obj-$(CONFIG_IMX_HAVE_PLATFORM_FEC) += platform-fec.o obj-$(CONFIG_IMX_HAVE_PLATFORM_FLEXCAN) += platform-flexcan.o obj-$(CONFIG_IMX_HAVE_PLATFORM_FSL_USB2_UDC) += platform-fsl-usb2-udc.o @@ -21,4 +20,5 @@ obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_NAND) += platform-mxc_nand.o obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_PWM) += platform-mxc_pwm.o obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_RNGA) += platform-mxc_rnga.o obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_W1) += platform-mxc_w1.o +obj-$(CONFIG_IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX) += platform-sdhci-esdhc-imx.o obj-$(CONFIG_IMX_HAVE_PLATFORM_SPI_IMX) += platform-spi_imx.o diff --git a/arch/arm/plat-mxc/devices/platform-esdhc.c b/arch/arm/plat-mxc/devices/platform-esdhc.c deleted file mode 100644 index 013e92f..0000000 --- a/arch/arm/plat-mxc/devices/platform-esdhc.c +++ /dev/null @@ -1,71 +0,0 @@ -/* - * Copyright (C) 2010 Pengutronix, Wolfram Sang - * - * This program is free software; you can redistribute it and/or modify it under - * the terms of the GNU General Public License version 2 as published by the - * Free Software Foundation. - */ - -#include -#include -#include - -#define imx_esdhc_imx_data_entry_single(soc, _id, hwid) \ - { \ - .id = _id, \ - .iobase = soc ## _ESDHC ## hwid ## _BASE_ADDR, \ - .irq = soc ## _INT_ESDHC ## hwid, \ - } - -#define imx_esdhc_imx_data_entry(soc, id, hwid) \ - [id] = imx_esdhc_imx_data_entry_single(soc, id, hwid) - -#ifdef CONFIG_SOC_IMX25 -const struct imx_esdhc_imx_data imx25_esdhc_data[] __initconst = { -#define imx25_esdhc_data_entry(_id, _hwid) \ - imx_esdhc_imx_data_entry(MX25, _id, _hwid) - imx25_esdhc_data_entry(0, 1), - imx25_esdhc_data_entry(1, 2), -}; -#endif /* ifdef CONFIG_SOC_IMX25 */ - -#ifdef CONFIG_SOC_IMX35 -const struct imx_esdhc_imx_data imx35_esdhc_data[] __initconst = { -#define imx35_esdhc_data_entry(_id, _hwid) \ - imx_esdhc_imx_data_entry(MX35, _id, _hwid) - imx35_esdhc_data_entry(0, 1), - imx35_esdhc_data_entry(1, 2), - imx35_esdhc_data_entry(2, 3), -}; -#endif /* ifdef CONFIG_SOC_IMX35 */ - -#ifdef CONFIG_ARCH_MX51 -const struct imx_esdhc_imx_data imx51_esdhc_data[] __initconst = { -#define imx51_esdhc_data_entry(_id, _hwid) \ - imx_esdhc_imx_data_entry(MX51, _id, _hwid) - imx51_esdhc_data_entry(0, 1), - imx51_esdhc_data_entry(1, 2), - imx51_esdhc_data_entry(2, 3), - imx51_esdhc_data_entry(3, 4), -}; -#endif /* ifdef CONFIG_ARCH_MX51 */ - -struct platform_device *__init imx_add_esdhc( - const struct imx_esdhc_imx_data *data, - const struct esdhc_platform_data *pdata) -{ - struct resource res[] = { - { - .start = data->iobase, - .end = data->iobase + SZ_16K - 1, - .flags = IORESOURCE_MEM, - }, { - .start = data->irq, - .end = data->irq, - .flags = IORESOURCE_IRQ, - }, - }; - - return imx_add_platform_device("sdhci-esdhc-imx", data->id, res, - ARRAY_SIZE(res), pdata, sizeof(*pdata)); -} diff --git a/arch/arm/plat-mxc/devices/platform-sdhci-esdhc-imx.c b/arch/arm/plat-mxc/devices/platform-sdhci-esdhc-imx.c new file mode 100644 index 0000000..167cce8 --- /dev/null +++ b/arch/arm/plat-mxc/devices/platform-sdhci-esdhc-imx.c @@ -0,0 +1,74 @@ +/* + * Copyright (C) 2010 Pengutronix, Wolfram Sang + * + * This program is free software; you can redistribute it and/or modify it under + * the terms of the GNU General Public License version 2 as published by the + * Free Software Foundation. + */ + +#include +#include +#include + +#define imx_sdhci_esdhc_imx_data_entry_single(soc, _id, hwid) \ + { \ + .id = _id, \ + .iobase = soc ## _ESDHC ## hwid ## _BASE_ADDR, \ + .irq = soc ## _INT_ESDHC ## hwid, \ + } + +#define imx_sdhci_esdhc_imx_data_entry(soc, id, hwid) \ + [id] = imx_sdhci_esdhc_imx_data_entry_single(soc, id, hwid) + +#ifdef CONFIG_SOC_IMX25 +const struct imx_sdhci_esdhc_imx_data +imx25_sdhci_esdhc_imx_data[] __initconst = { +#define imx25_sdhci_esdhc_imx_data_entry(_id, _hwid) \ + imx_sdhci_esdhc_imx_data_entry(MX25, _id, _hwid) + imx25_sdhci_esdhc_imx_data_entry(0, 1), + imx25_sdhci_esdhc_imx_data_entry(1, 2), +}; +#endif /* ifdef CONFIG_SOC_IMX25 */ + +#ifdef CONFIG_SOC_IMX35 +const struct imx_sdhci_esdhc_imx_data +imx35_sdhci_esdhc_imx_data[] __initconst = { +#define imx35_sdhci_esdhc_imx_data_entry(_id, _hwid) \ + imx_sdhci_esdhc_imx_data_entry(MX35, _id, _hwid) + imx35_sdhci_esdhc_imx_data_entry(0, 1), + imx35_sdhci_esdhc_imx_data_entry(1, 2), + imx35_sdhci_esdhc_imx_data_entry(2, 3), +}; +#endif /* ifdef CONFIG_SOC_IMX35 */ + +#ifdef CONFIG_ARCH_MX51 +const struct imx_sdhci_esdhc_imx_data +imx51_sdhci_esdhc_imx_data[] __initconst = { +#define imx51_sdhci_esdhc_imx_data_entry(_id, _hwid) \ + imx_sdhci_esdhc_imx_data_entry(MX51, _id, _hwid) + imx51_sdhci_esdhc_imx_data_entry(0, 1), + imx51_sdhci_esdhc_imx_data_entry(1, 2), + imx51_sdhci_esdhc_imx_data_entry(2, 3), + imx51_sdhci_esdhc_imx_data_entry(3, 4), +}; +#endif /* ifdef CONFIG_ARCH_MX51 */ + +struct platform_device *__init imx_add_sdhci_esdhc_imx( + const struct imx_sdhci_esdhc_imx_data *data, + const struct esdhc_platform_data *pdata) +{ + struct resource res[] = { + { + .start = data->iobase, + .end = data->iobase + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, { + .start = data->irq, + .end = data->irq, + .flags = IORESOURCE_IRQ, + }, + }; + + return imx_add_platform_device("sdhci-esdhc-imx", data->id, res, + ARRAY_SIZE(res), pdata, sizeof(*pdata)); +} diff --git a/arch/arm/plat-mxc/include/mach/devices-common.h b/arch/arm/plat-mxc/include/mach/devices-common.h index 5a62dc4..3640eaf 100644 --- a/arch/arm/plat-mxc/include/mach/devices-common.h +++ b/arch/arm/plat-mxc/include/mach/devices-common.h @@ -242,6 +242,16 @@ struct imx_mxc_w1_data { struct platform_device *__init imx_add_mxc_w1( const struct imx_mxc_w1_data *data); +#include +struct imx_sdhci_esdhc_imx_data { + int id; + resource_size_t iobase; + resource_size_t irq; +}; +struct platform_device *__init imx_add_sdhci_esdhc_imx( + const struct imx_sdhci_esdhc_imx_data *data, + const struct esdhc_platform_data *pdata); + #include struct imx_spi_imx_data { const char *devid; @@ -253,13 +263,3 @@ struct imx_spi_imx_data { struct platform_device *__init imx_add_spi_imx( const struct imx_spi_imx_data *data, const struct spi_imx_master *pdata); - -#include -struct imx_esdhc_imx_data { - int id; - resource_size_t iobase; - resource_size_t irq; -}; -struct platform_device *__init imx_add_esdhc( - const struct imx_esdhc_imx_data *data, - const struct esdhc_platform_data *pdata); -- cgit v1.1 From 8f5260c8c1a1f9b25dfedd5ca749e4faef1b3eb9 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Lothar=20Wa=C3=9Fmann?= Date: Tue, 26 Oct 2010 14:28:31 +0200 Subject: ARM: i.MX IOMUX-V3 replace struct pad_desc with bitmapped cookie MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The following patch is a first step to convert the 'struct pad_desc' to a bitmapped cookie to facilitate adding platform specific pullup or drive strength definitions to existing pad definitions without need to rewrite the complete pad def. The patch wraps 'struct pad_desc' in an opaque data type and introduces macros to access the individual members. This patch does not constitute any functional change! Signed-off-by: Lothar Waßmann Signed-off-by: Sascha Hauer --- arch/arm/plat-mxc/include/mach/iomux-v3.h | 38 +++++++++++++++++++++++++++---- arch/arm/plat-mxc/iomux-v3.c | 22 +++++++++--------- 2 files changed, 45 insertions(+), 15 deletions(-) (limited to 'arch/arm/plat-mxc') diff --git a/arch/arm/plat-mxc/include/mach/iomux-v3.h b/arch/arm/plat-mxc/include/mach/iomux-v3.h index 0880a4a..811716f 100644 --- a/arch/arm/plat-mxc/include/mach/iomux-v3.h +++ b/arch/arm/plat-mxc/include/mach/iomux-v3.h @@ -44,7 +44,7 @@ * */ -struct pad_desc { +typedef struct deprecated_pad_desc { unsigned mux_ctrl_ofs:12; /* IOMUXC_SW_MUX_CTL_PAD offset */ unsigned mux_mode:8; unsigned pad_ctrl_ofs:12; /* IOMUXC_SW_PAD_CTRL offset */ @@ -52,7 +52,37 @@ struct pad_desc { unsigned pad_ctrl:17; unsigned select_input_ofs:12; /* IOMUXC_SELECT_INPUT offset */ unsigned select_input:3; -}; +} iomux_v3_cfg_t; + +static inline unsigned int MUX_CTRL_OFS(iomux_v3_cfg_t *pad) +{ + return pad->mux_ctrl_ofs; +} + +static inline unsigned int MUX_MODE(iomux_v3_cfg_t *pad) +{ + return pad->mux_mode; +} + +static inline unsigned int MUX_SELECT_INPUT_OFS(iomux_v3_cfg_t *pad) +{ + return pad->select_input_ofs; +} + +static inline unsigned int MUX_SELECT_INPUT(iomux_v3_cfg_t *pad) +{ + return pad->select_input; +} + +static inline unsigned int MUX_PAD_CTRL_OFS(iomux_v3_cfg_t *pad) +{ + return pad->pad_ctrl_ofs; +} + +static inline unsigned int MUX_PAD_CTRL(iomux_v3_cfg_t *pad) +{ + return pad->pad_ctrl; +} #define IOMUX_PAD(_pad_ctrl_ofs, _mux_ctrl_ofs, _mux_mode, _select_input_ofs, \ _select_input, _pad_ctrl) \ @@ -107,13 +137,13 @@ struct pad_desc { /* * setups a single pad in the iomuxer */ -int mxc_iomux_v3_setup_pad(struct pad_desc *pad); +int mxc_iomux_v3_setup_pad(iomux_v3_cfg_t *pad); /* * setups mutliple pads * convenient way to call the above function with tables */ -int mxc_iomux_v3_setup_multiple_pads(struct pad_desc *pad_list, unsigned count); +int mxc_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t *pad_list, unsigned count); /* * Initialise the iomux controller diff --git a/arch/arm/plat-mxc/iomux-v3.c b/arch/arm/plat-mxc/iomux-v3.c index b318c6a..975ca7c 100644 --- a/arch/arm/plat-mxc/iomux-v3.c +++ b/arch/arm/plat-mxc/iomux-v3.c @@ -32,26 +32,26 @@ static void __iomem *base; /* - * setups a single pad in the iomuxer + * configures a single pad in the iomuxer */ -int mxc_iomux_v3_setup_pad(struct pad_desc *pad) +int mxc_iomux_v3_setup_pad(iomux_v3_cfg_t *pad) { - if (pad->mux_ctrl_ofs) - __raw_writel(pad->mux_mode, base + pad->mux_ctrl_ofs); + if (MUX_CTRL_OFS(pad)) + __raw_writel(MUX_MODE(pad), base + MUX_CTRL_OFS(pad)); - if (pad->select_input_ofs) - __raw_writel(pad->select_input, - base + pad->select_input_ofs); + if (MUX_SELECT_INPUT_OFS(pad)) + __raw_writel(MUX_SELECT_INPUT(pad), + base + MUX_SELECT_INPUT(pad)); - if (!(pad->pad_ctrl & NO_PAD_CTRL) && pad->pad_ctrl_ofs) - __raw_writel(pad->pad_ctrl, base + pad->pad_ctrl_ofs); + if (!(MUX_PAD_CTRL(pad) & NO_PAD_CTRL) && MUX_PAD_CTRL_OFS(pad)) + __raw_writel(MUX_PAD_CTRL(pad), base + MUX_PAD_CTRL_OFS(pad)); return 0; } EXPORT_SYMBOL(mxc_iomux_v3_setup_pad); -int mxc_iomux_v3_setup_multiple_pads(struct pad_desc *pad_list, unsigned count) +int mxc_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t *pad_list, unsigned count) { - struct pad_desc *p = pad_list; + iomux_v3_cfg_t *p = pad_list; int i; int ret; -- cgit v1.1 From db9d42348f6f5b37ae658a506bf80fa935dc1b0a Mon Sep 17 00:00:00 2001 From: "Arnaud Patard (Rtp)" Date: Wed, 27 Oct 2010 14:40:47 +0200 Subject: imx51: fix iomux configuration - ALT0 is used to set GPIO mode of GPIO_1_{2,3,4,5,6,7,8,9} but it's ALT1 for GPIO_1_{0,1}. Signed-off-by: Arnaud Patard Signed-off-by: Sascha Hauer --- arch/arm/plat-mxc/include/mach/iomux-mx51.h | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) (limited to 'arch/arm/plat-mxc') diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx51.h b/arch/arm/plat-mxc/include/mach/iomux-mx51.h index d7a41e9..746dcad 100644 --- a/arch/arm/plat-mxc/include/mach/iomux-mx51.h +++ b/arch/arm/plat-mxc/include/mach/iomux-mx51.h @@ -370,18 +370,18 @@ typedef enum iomux_config { MX51_SDHCI_PAD_CTRL) #define MX51_PAD_GPIO_1_0__GPIO_1_0 IOMUX_PAD(0x7B4, 0x3AC, 1, 0x0, 0, MX51_GPIO_PAD_CTRL) #define MX51_PAD_GPIO_1_1__GPIO_1_1 IOMUX_PAD(0x7B8, 0x3B0, 1, 0x0, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_GPIO_1_2__GPIO_1_2 IOMUX_PAD(0x7D4, 0x3CC, 1, 0x0, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_GPIO_1_2__GPIO_1_2 IOMUX_PAD(0x7D4, 0x3CC, 0, 0x0, 0, MX51_GPIO_PAD_CTRL) #define MX51_PAD_GPIO_1_2__I2C2_SCL IOMUX_PAD(0x7D4, 0x3CC, (2 | IOMUX_CONFIG_SION), \ 0x9b8, 3, MX51_I2C_PAD_CTRL) -#define MX51_PAD_GPIO_1_3__GPIO_1_3 IOMUX_PAD(0x7D8, 0x3D0, 1, 0x0, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_GPIO_1_3__GPIO_1_3 IOMUX_PAD(0x7D8, 0x3D0, 0, 0x0, 0, MX51_GPIO_PAD_CTRL) #define MX51_PAD_GPIO_1_3__I2C2_SDA IOMUX_PAD(0x7D8, 0x3D0, (2 | IOMUX_CONFIG_SION), \ 0x9bc, 3, MX51_I2C_PAD_CTRL) #define MX51_PAD_PMIC_INT_REQ__PMIC_INT_REQ IOMUX_PAD(0x7FC, 0x3D4, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_1_4__GPIO_1_4 IOMUX_PAD(0x804, 0x3D8, 1, 0x0, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_GPIO_1_5__GPIO_1_5 IOMUX_PAD(0x808, 0x3DC, 1, 0x0, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_GPIO_1_6__GPIO_1_6 IOMUX_PAD(0x80C, 0x3E0, 1, 0x0, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_GPIO_1_7__GPIO_1_7 IOMUX_PAD(0x810, 0x3E4, 1, 0x0, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_GPIO_1_8__GPIO_1_8 IOMUX_PAD(0x814, 0x3E8, 1, 0x0, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_GPIO_1_9__GPIO_1_9 IOMUX_PAD(0x818, 0x3EC, 1, 0x0, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_GPIO_1_4__GPIO_1_4 IOMUX_PAD(0x804, 0x3D8, 0, 0x0, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_GPIO_1_5__GPIO_1_5 IOMUX_PAD(0x808, 0x3DC, 0, 0x0, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_GPIO_1_6__GPIO_1_6 IOMUX_PAD(0x80C, 0x3E0, 0, 0x0, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_GPIO_1_7__GPIO_1_7 IOMUX_PAD(0x810, 0x3E4, 0, 0x0, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_GPIO_1_8__GPIO_1_8 IOMUX_PAD(0x814, 0x3E8, 0, 0x0, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_GPIO_1_9__GPIO_1_9 IOMUX_PAD(0x818, 0x3EC, 0, 0x0, 0, MX51_GPIO_PAD_CTRL) #endif /* __MACH_IOMUX_MX51_H__ */ -- cgit v1.1 From 0a7d48712f9a279464d2587e52e60fdc81f9a65a Mon Sep 17 00:00:00 2001 From: "Arnaud Patard (Rtp)" Date: Wed, 27 Oct 2010 14:40:48 +0200 Subject: imx51: enhance iomux configuration for esdhc support - add definition to configure pads as ESDHC{1,2} WP and CD Signed-off-by: Arnaud Patard Signed-off-by: Sascha Hauer --- arch/arm/plat-mxc/include/mach/iomux-mx51.h | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'arch/arm/plat-mxc') diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx51.h b/arch/arm/plat-mxc/include/mach/iomux-mx51.h index 746dcad..fdf705e 100644 --- a/arch/arm/plat-mxc/include/mach/iomux-mx51.h +++ b/arch/arm/plat-mxc/include/mach/iomux-mx51.h @@ -40,6 +40,8 @@ typedef enum iomux_config { PAD_CTL_SRE_FAST) #define MX51_I2C_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_ODE | \ PAD_CTL_DSE_HIGH | PAD_CTL_PUS_100K_UP | PAD_CTL_HYS) +#define MX51_ESDHC_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_ODE | \ + PAD_CTL_DSE_HIGH | PAD_CTL_PUS_100K_UP | PAD_CTL_HYS) #define MX51_USBH1_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \ PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ PAD_CTL_PKE | PAD_CTL_HYS) @@ -368,7 +370,9 @@ typedef enum iomux_config { MX51_SDHCI_PAD_CTRL) #define MX51_PAD_SD2_DATA3__SD2_DATA3 IOMUX_PAD(0x7D0, 0x3C8, IOMUX_CONFIG_SION, 0x0, 0, \ MX51_SDHCI_PAD_CTRL) +#define MX51_PAD_GPIO_1_0__ESDHC1_CD IOMUX_PAD(0x7B4, 0x3AC, 0, 0x0, 0, MX51_ESDHC_PAD_CTRL) #define MX51_PAD_GPIO_1_0__GPIO_1_0 IOMUX_PAD(0x7B4, 0x3AC, 1, 0x0, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_GPIO_1_1__ESDHC1_WP IOMUX_PAD(0x7B8, 0x3B0, 0, 0x0, 0, MX51_ESDHC_PAD_CTRL) #define MX51_PAD_GPIO_1_1__GPIO_1_1 IOMUX_PAD(0x7B8, 0x3B0, 1, 0x0, 0, MX51_GPIO_PAD_CTRL) #define MX51_PAD_GPIO_1_2__GPIO_1_2 IOMUX_PAD(0x7D4, 0x3CC, 0, 0x0, 0, MX51_GPIO_PAD_CTRL) #define MX51_PAD_GPIO_1_2__I2C2_SCL IOMUX_PAD(0x7D4, 0x3CC, (2 | IOMUX_CONFIG_SION), \ @@ -381,7 +385,9 @@ typedef enum iomux_config { #define MX51_PAD_GPIO_1_5__GPIO_1_5 IOMUX_PAD(0x808, 0x3DC, 0, 0x0, 0, MX51_GPIO_PAD_CTRL) #define MX51_PAD_GPIO_1_6__GPIO_1_6 IOMUX_PAD(0x80C, 0x3E0, 0, 0x0, 0, MX51_GPIO_PAD_CTRL) #define MX51_PAD_GPIO_1_7__GPIO_1_7 IOMUX_PAD(0x810, 0x3E4, 0, 0x0, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_GPIO_1_7__ESDHC2_WP IOMUX_PAD(0x810, 0x3E4, 6, 0x0, 0, MX51_ESDHC_PAD_CTRL) #define MX51_PAD_GPIO_1_8__GPIO_1_8 IOMUX_PAD(0x814, 0x3E8, 0, 0x0, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_GPIO_1_8__ESDHC2_CD IOMUX_PAD(0x814, 0x3E8, 6, 0x0, 0, MX51_ESDHC_PAD_CTRL) #define MX51_PAD_GPIO_1_9__GPIO_1_9 IOMUX_PAD(0x818, 0x3EC, 0, 0x0, 0, MX51_GPIO_PAD_CTRL) #endif /* __MACH_IOMUX_MX51_H__ */ -- cgit v1.1 From 82df68ad26c1cb4c31e1a2750c0020038dd77cc6 Mon Sep 17 00:00:00 2001 From: "Arnaud Patard (Rtp)" Date: Wed, 27 Oct 2010 14:40:50 +0200 Subject: imx51: add gpio mode for csi1 {h,v}sync Add definitions for configuring CSI1_{H,V}SYNC as GPIO Signed-off-by: Arnaud Patard Signed-off-by: Sascha Hauer --- arch/arm/plat-mxc/include/mach/iomux-mx51.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/arm/plat-mxc') diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx51.h b/arch/arm/plat-mxc/include/mach/iomux-mx51.h index fdf705e..0998599 100644 --- a/arch/arm/plat-mxc/include/mach/iomux-mx51.h +++ b/arch/arm/plat-mxc/include/mach/iomux-mx51.h @@ -202,7 +202,9 @@ typedef enum iomux_config { #define MX51_PAD_CSI1_D18__CSI1_D18 IOMUX_PAD(0x5A4, 0x1BC, 0, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_CSI1_D19__CSI1_D19 IOMUX_PAD(0x5A8, 0x1C0, 0, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_CSI1_VSYNC__CSI1_VSYNC IOMUX_PAD(0x5AC, 0x1C4, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_CSI1_VSYNC__GPIO_3_14 IOMUX_PAD(0x5AC, 0x1C4, 3, 0x0, 0, MX51_GPIO_PAD_CTRL) #define MX51_PAD_CSI1_HSYNC__CSI1_HSYNC IOMUX_PAD(0x5B0, 0x1C8, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_CSI1_HSYNC__GPIO_3_15 IOMUX_PAD(0x5B0, 0x1C8, 3, 0x0, 0, MX51_GPIO_PAD_CTRL) #define MX51_PAD_CSI1_PIXCLK__CSI1_PIXCLK IOMUX_PAD(0x5B4, 0x000, 0, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_CSI1_MCLK__CSI1_MCLK IOMUX_PAD(0x5B8, 0x000, 0, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_CSI1_PKE0__CSI1_PKE0 IOMUX_PAD(0x860, 0x000, 0, 0x0, 0, NO_PAD_CTRL) -- cgit v1.1 From 0dea1c74642fb46cb94282719dafe7c2a7d3068f Mon Sep 17 00:00:00 2001 From: "Arnaud Patard (Rtp)" Date: Wed, 27 Oct 2010 14:40:53 +0200 Subject: imx51: fix gpio_4_24 and gpio_4_25 pad configuration s/NO_PAD_CTRL/MX51_GPIO_PAD_CTRL/ Signed-off-by: Arnaud Patard Signed-off-by: Sascha Hauer --- arch/arm/plat-mxc/include/mach/iomux-mx51.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm/plat-mxc') diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx51.h b/arch/arm/plat-mxc/include/mach/iomux-mx51.h index 0998599..e1600f3 100644 --- a/arch/arm/plat-mxc/include/mach/iomux-mx51.h +++ b/arch/arm/plat-mxc/include/mach/iomux-mx51.h @@ -236,9 +236,9 @@ typedef enum iomux_config { #define MX51_PAD_CSPI1_MISO__ECSPI1_MISO IOMUX_PAD(0x604, 0x214, 0, 0x0, 0, MX51_ECSPI_PAD_CTRL) #define MX51_PAD_CSPI1_MISO__GPIO_4_23 IOMUX_PAD(0x604, 0x214, 3, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_CSPI1_SS0__ECSPI1_SS0 IOMUX_PAD(0x608, 0x218, 0, 0x0, 0, MX51_ECSPI_PAD_CTRL) -#define MX51_PAD_CSPI1_SS0__GPIO_4_24 IOMUX_PAD(0x608, 0x218, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_CSPI1_SS0__GPIO_4_24 IOMUX_PAD(0x608, 0x218, 3, 0x0, 0, MX51_GPIO_PAD_CTRL) #define MX51_PAD_CSPI1_SS1__ECSPI1_SS1 IOMUX_PAD(0x60C, 0x21C, 0, 0x0, 0, MX51_ECSPI_PAD_CTRL) -#define MX51_PAD_CSPI1_SS1__GPIO_4_25 IOMUX_PAD(0x60C, 0x21C, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_CSPI1_SS1__GPIO_4_25 IOMUX_PAD(0x60C, 0x21C, 3, 0x0, 0, MX51_GPIO_PAD_CTRL) #define MX51_PAD_CSPI1_RDY__ECSPI1_RDY IOMUX_PAD(0x610, 0x220, 0, 0x0, 0, MX51_ECSPI_PAD_CTRL) #define MX51_PAD_CSPI1_RDY__GPIO_4_26 IOMUX_PAD(0x610, 0x220, 3, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK IOMUX_PAD(0x614, 0x224, 0, 0x0, 0, MX51_ECSPI_PAD_CTRL) -- cgit v1.1 From c2932bf47001697fc48e89f1d136532703ed4779 Mon Sep 17 00:00:00 2001 From: "Arnaud Patard (Rtp)" Date: Wed, 27 Oct 2010 14:40:55 +0200 Subject: efikamx: add reset The efikamx board is using a gpio to reset the board so add support for it Signed-off-by: Arnaud Patard Signed-off-by: Sascha Hauer --- arch/arm/plat-mxc/include/mach/common.h | 2 +- arch/arm/plat-mxc/system.c | 8 ++++++++ 2 files changed, 9 insertions(+), 1 deletion(-) (limited to 'arch/arm/plat-mxc') diff --git a/arch/arm/plat-mxc/include/mach/common.h b/arch/arm/plat-mxc/include/mach/common.h index 7a1e1f8..05676fb 100644 --- a/arch/arm/plat-mxc/include/mach/common.h +++ b/arch/arm/plat-mxc/include/mach/common.h @@ -50,5 +50,5 @@ extern void mxc_arch_reset_init(void __iomem *); extern void mxc91231_power_off(void); extern void mxc91231_arch_reset(int, const char *); extern void mxc91231_prepare_idle(void); - +extern void mx51_efikamx_reset(void); #endif diff --git a/arch/arm/plat-mxc/system.c b/arch/arm/plat-mxc/system.c index 925bce4..c3972c5 100644 --- a/arch/arm/plat-mxc/system.c +++ b/arch/arm/plat-mxc/system.c @@ -26,6 +26,7 @@ #include #include #include +#include static void __iomem *wdog_base; @@ -42,6 +43,13 @@ void arch_reset(char mode, const char *cmd) return; } #endif +#ifdef CONFIG_MACH_MX51_EFIKAMX + if (machine_is_mx51_efikamx()) { + mx51_efikamx_reset(); + return; + } +#endif + if (cpu_is_mx1()) { wcr_enable = (1 << 0); } else { -- cgit v1.1 From 28d6a7a2f37a349a2292e52a87d76f06f55dc9d8 Mon Sep 17 00:00:00 2001 From: "Arnaud Patard (Rtp)" Date: Wed, 3 Nov 2010 15:54:36 +0100 Subject: imx: fix iomux v3 Commit "ARM: i.MX IOMUX-V3 replace struct pad_desc with bitmapped cookie" (b705cb4d42e95a4a43a8945571c8613e71526c3d) introduced a typo which was preventing my efikamx to boot. This patch is fixing that. Signed-off-by: Arnaud Patard Tested-by: Fabio Estevam Signed-off-by: Sascha Hauer --- arch/arm/plat-mxc/iomux-v3.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm/plat-mxc') diff --git a/arch/arm/plat-mxc/iomux-v3.c b/arch/arm/plat-mxc/iomux-v3.c index 975ca7c..4cbbf2c 100644 --- a/arch/arm/plat-mxc/iomux-v3.c +++ b/arch/arm/plat-mxc/iomux-v3.c @@ -41,7 +41,7 @@ int mxc_iomux_v3_setup_pad(iomux_v3_cfg_t *pad) if (MUX_SELECT_INPUT_OFS(pad)) __raw_writel(MUX_SELECT_INPUT(pad), - base + MUX_SELECT_INPUT(pad)); + base + MUX_SELECT_INPUT_OFS(pad)); if (!(MUX_PAD_CTRL(pad) & NO_PAD_CTRL) && MUX_PAD_CTRL_OFS(pad)) __raw_writel(MUX_PAD_CTRL(pad), base + MUX_PAD_CTRL_OFS(pad)); -- cgit v1.1 From c7259df3af03aee00985e9bb64fb2afa593f703f Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Fri, 5 Nov 2010 09:37:22 +0100 Subject: ARM i.MX irq: Compile avic irq code only on SoCs that need it This patch adds a Kconfig option for the avic irq controller and lets the SoCs that need it select this option. Also, as we have two irq controllers for i.MX, irq.c is not appropriate anymore, so rename it to avic.c Signed-off-by: Sascha Hauer --- arch/arm/plat-mxc/Kconfig | 3 + arch/arm/plat-mxc/Makefile | 5 +- arch/arm/plat-mxc/avic.c | 152 +++++++++++++++++++++++++++++++++++++++++++++ arch/arm/plat-mxc/irq.c | 152 --------------------------------------------- 4 files changed, 158 insertions(+), 154 deletions(-) create mode 100644 arch/arm/plat-mxc/avic.c delete mode 100644 arch/arm/plat-mxc/irq.c (limited to 'arch/arm/plat-mxc') diff --git a/arch/arm/plat-mxc/Kconfig b/arch/arm/plat-mxc/Kconfig index a31fa16..6c66bc0 100644 --- a/arch/arm/plat-mxc/Kconfig +++ b/arch/arm/plat-mxc/Kconfig @@ -70,6 +70,9 @@ config MXC_TZIC containing this interrupt controller. Say N here only if you are really sure. +config MXC_AVIC + bool + config MXC_PWM tristate "Enable PWM driver" select HAVE_PWM diff --git a/arch/arm/plat-mxc/Makefile b/arch/arm/plat-mxc/Makefile index 3726709..989cb59 100644 --- a/arch/arm/plat-mxc/Makefile +++ b/arch/arm/plat-mxc/Makefile @@ -3,10 +3,11 @@ # # Common support -obj-y := irq.o clock.o gpio.o time.o devices.o cpu.o system.o +obj-y := clock.o gpio.o time.o devices.o cpu.o system.o -# MX51 uses the TZIC interrupt controller, older platforms use AVIC (irq.o) +# MX51 uses the TZIC interrupt controller, older platforms use AVIC obj-$(CONFIG_MXC_TZIC) += tzic.o +obj-$(CONFIG_MXC_AVIC) += avic.o obj-$(CONFIG_IMX_HAVE_IOMUX_V1) += iomux-v1.o obj-$(CONFIG_ARCH_MXC_IOMUX_V3) += iomux-v3.o diff --git a/arch/arm/plat-mxc/avic.c b/arch/arm/plat-mxc/avic.c new file mode 100644 index 0000000..7331f2a --- /dev/null +++ b/arch/arm/plat-mxc/avic.c @@ -0,0 +1,152 @@ +/* + * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2008 Juergen Beisert, kernel@pengutronix.de + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301, USA. + */ + +#include +#include +#include +#include +#include +#include + +#define AVIC_INTCNTL 0x00 /* int control reg */ +#define AVIC_NIMASK 0x04 /* int mask reg */ +#define AVIC_INTENNUM 0x08 /* int enable number reg */ +#define AVIC_INTDISNUM 0x0C /* int disable number reg */ +#define AVIC_INTENABLEH 0x10 /* int enable reg high */ +#define AVIC_INTENABLEL 0x14 /* int enable reg low */ +#define AVIC_INTTYPEH 0x18 /* int type reg high */ +#define AVIC_INTTYPEL 0x1C /* int type reg low */ +#define AVIC_NIPRIORITY(x) (0x20 + 4 * (7 - (x))) /* int priority */ +#define AVIC_NIVECSR 0x40 /* norm int vector/status */ +#define AVIC_FIVECSR 0x44 /* fast int vector/status */ +#define AVIC_INTSRCH 0x48 /* int source reg high */ +#define AVIC_INTSRCL 0x4C /* int source reg low */ +#define AVIC_INTFRCH 0x50 /* int force reg high */ +#define AVIC_INTFRCL 0x54 /* int force reg low */ +#define AVIC_NIPNDH 0x58 /* norm int pending high */ +#define AVIC_NIPNDL 0x5C /* norm int pending low */ +#define AVIC_FIPNDH 0x60 /* fast int pending high */ +#define AVIC_FIPNDL 0x64 /* fast int pending low */ + +void __iomem *avic_base; + +int imx_irq_set_priority(unsigned char irq, unsigned char prio) +{ +#ifdef CONFIG_MXC_IRQ_PRIOR + unsigned int temp; + unsigned int mask = 0x0F << irq % 8 * 4; + + if (irq >= MXC_INTERNAL_IRQS) + return -EINVAL;; + + temp = __raw_readl(avic_base + AVIC_NIPRIORITY(irq / 8)); + temp &= ~mask; + temp |= prio & mask; + + __raw_writel(temp, avic_base + AVIC_NIPRIORITY(irq / 8)); + + return 0; +#else + return -ENOSYS; +#endif +} +EXPORT_SYMBOL(imx_irq_set_priority); + +#ifdef CONFIG_FIQ +int mxc_set_irq_fiq(unsigned int irq, unsigned int type) +{ + unsigned int irqt; + + if (irq >= MXC_INTERNAL_IRQS) + return -EINVAL; + + if (irq < MXC_INTERNAL_IRQS / 2) { + irqt = __raw_readl(avic_base + AVIC_INTTYPEL) & ~(1 << irq); + __raw_writel(irqt | (!!type << irq), avic_base + AVIC_INTTYPEL); + } else { + irq -= MXC_INTERNAL_IRQS / 2; + irqt = __raw_readl(avic_base + AVIC_INTTYPEH) & ~(1 << irq); + __raw_writel(irqt | (!!type << irq), avic_base + AVIC_INTTYPEH); + } + + return 0; +} +EXPORT_SYMBOL(mxc_set_irq_fiq); +#endif /* CONFIG_FIQ */ + +/* Disable interrupt number "irq" in the AVIC */ +static void mxc_mask_irq(unsigned int irq) +{ + __raw_writel(irq, avic_base + AVIC_INTDISNUM); +} + +/* Enable interrupt number "irq" in the AVIC */ +static void mxc_unmask_irq(unsigned int irq) +{ + __raw_writel(irq, avic_base + AVIC_INTENNUM); +} + +static struct irq_chip mxc_avic_chip = { + .ack = mxc_mask_irq, + .mask = mxc_mask_irq, + .unmask = mxc_unmask_irq, +}; + +/* + * This function initializes the AVIC hardware and disables all the + * interrupts. It registers the interrupt enable and disable functions + * to the kernel for each interrupt source. + */ +void __init mxc_init_irq(void __iomem *irqbase) +{ + int i; + + avic_base = irqbase; + + /* put the AVIC into the reset value with + * all interrupts disabled + */ + __raw_writel(0, avic_base + AVIC_INTCNTL); + __raw_writel(0x1f, avic_base + AVIC_NIMASK); + + /* disable all interrupts */ + __raw_writel(0, avic_base + AVIC_INTENABLEH); + __raw_writel(0, avic_base + AVIC_INTENABLEL); + + /* all IRQ no FIQ */ + __raw_writel(0, avic_base + AVIC_INTTYPEH); + __raw_writel(0, avic_base + AVIC_INTTYPEL); + for (i = 0; i < MXC_INTERNAL_IRQS; i++) { + set_irq_chip(i, &mxc_avic_chip); + set_irq_handler(i, handle_level_irq); + set_irq_flags(i, IRQF_VALID); + } + + /* Set default priority value (0) for all IRQ's */ + for (i = 0; i < 8; i++) + __raw_writel(0, avic_base + AVIC_NIPRIORITY(i)); + +#ifdef CONFIG_FIQ + /* Initialize FIQ */ + init_FIQ(); +#endif + + printk(KERN_INFO "MXC IRQ initialized\n"); +} + diff --git a/arch/arm/plat-mxc/irq.c b/arch/arm/plat-mxc/irq.c deleted file mode 100644 index 7331f2a..0000000 --- a/arch/arm/plat-mxc/irq.c +++ /dev/null @@ -1,152 +0,0 @@ -/* - * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright 2008 Juergen Beisert, kernel@pengutronix.de - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, - * MA 02110-1301, USA. - */ - -#include -#include -#include -#include -#include -#include - -#define AVIC_INTCNTL 0x00 /* int control reg */ -#define AVIC_NIMASK 0x04 /* int mask reg */ -#define AVIC_INTENNUM 0x08 /* int enable number reg */ -#define AVIC_INTDISNUM 0x0C /* int disable number reg */ -#define AVIC_INTENABLEH 0x10 /* int enable reg high */ -#define AVIC_INTENABLEL 0x14 /* int enable reg low */ -#define AVIC_INTTYPEH 0x18 /* int type reg high */ -#define AVIC_INTTYPEL 0x1C /* int type reg low */ -#define AVIC_NIPRIORITY(x) (0x20 + 4 * (7 - (x))) /* int priority */ -#define AVIC_NIVECSR 0x40 /* norm int vector/status */ -#define AVIC_FIVECSR 0x44 /* fast int vector/status */ -#define AVIC_INTSRCH 0x48 /* int source reg high */ -#define AVIC_INTSRCL 0x4C /* int source reg low */ -#define AVIC_INTFRCH 0x50 /* int force reg high */ -#define AVIC_INTFRCL 0x54 /* int force reg low */ -#define AVIC_NIPNDH 0x58 /* norm int pending high */ -#define AVIC_NIPNDL 0x5C /* norm int pending low */ -#define AVIC_FIPNDH 0x60 /* fast int pending high */ -#define AVIC_FIPNDL 0x64 /* fast int pending low */ - -void __iomem *avic_base; - -int imx_irq_set_priority(unsigned char irq, unsigned char prio) -{ -#ifdef CONFIG_MXC_IRQ_PRIOR - unsigned int temp; - unsigned int mask = 0x0F << irq % 8 * 4; - - if (irq >= MXC_INTERNAL_IRQS) - return -EINVAL;; - - temp = __raw_readl(avic_base + AVIC_NIPRIORITY(irq / 8)); - temp &= ~mask; - temp |= prio & mask; - - __raw_writel(temp, avic_base + AVIC_NIPRIORITY(irq / 8)); - - return 0; -#else - return -ENOSYS; -#endif -} -EXPORT_SYMBOL(imx_irq_set_priority); - -#ifdef CONFIG_FIQ -int mxc_set_irq_fiq(unsigned int irq, unsigned int type) -{ - unsigned int irqt; - - if (irq >= MXC_INTERNAL_IRQS) - return -EINVAL; - - if (irq < MXC_INTERNAL_IRQS / 2) { - irqt = __raw_readl(avic_base + AVIC_INTTYPEL) & ~(1 << irq); - __raw_writel(irqt | (!!type << irq), avic_base + AVIC_INTTYPEL); - } else { - irq -= MXC_INTERNAL_IRQS / 2; - irqt = __raw_readl(avic_base + AVIC_INTTYPEH) & ~(1 << irq); - __raw_writel(irqt | (!!type << irq), avic_base + AVIC_INTTYPEH); - } - - return 0; -} -EXPORT_SYMBOL(mxc_set_irq_fiq); -#endif /* CONFIG_FIQ */ - -/* Disable interrupt number "irq" in the AVIC */ -static void mxc_mask_irq(unsigned int irq) -{ - __raw_writel(irq, avic_base + AVIC_INTDISNUM); -} - -/* Enable interrupt number "irq" in the AVIC */ -static void mxc_unmask_irq(unsigned int irq) -{ - __raw_writel(irq, avic_base + AVIC_INTENNUM); -} - -static struct irq_chip mxc_avic_chip = { - .ack = mxc_mask_irq, - .mask = mxc_mask_irq, - .unmask = mxc_unmask_irq, -}; - -/* - * This function initializes the AVIC hardware and disables all the - * interrupts. It registers the interrupt enable and disable functions - * to the kernel for each interrupt source. - */ -void __init mxc_init_irq(void __iomem *irqbase) -{ - int i; - - avic_base = irqbase; - - /* put the AVIC into the reset value with - * all interrupts disabled - */ - __raw_writel(0, avic_base + AVIC_INTCNTL); - __raw_writel(0x1f, avic_base + AVIC_NIMASK); - - /* disable all interrupts */ - __raw_writel(0, avic_base + AVIC_INTENABLEH); - __raw_writel(0, avic_base + AVIC_INTENABLEL); - - /* all IRQ no FIQ */ - __raw_writel(0, avic_base + AVIC_INTTYPEH); - __raw_writel(0, avic_base + AVIC_INTTYPEL); - for (i = 0; i < MXC_INTERNAL_IRQS; i++) { - set_irq_chip(i, &mxc_avic_chip); - set_irq_handler(i, handle_level_irq); - set_irq_flags(i, IRQF_VALID); - } - - /* Set default priority value (0) for all IRQ's */ - for (i = 0; i < 8; i++) - __raw_writel(0, avic_base + AVIC_NIPRIORITY(i)); - -#ifdef CONFIG_FIQ - /* Initialize FIQ */ - init_FIQ(); -#endif - - printk(KERN_INFO "MXC IRQ initialized\n"); -} - -- cgit v1.1 From ec4bb253fcc5c07519b5e701d2c87100aef0d2ba Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Fri, 5 Nov 2010 09:47:21 +0100 Subject: ARM i.MX51: Make CONFIG_MXC_TZIC an invisible option There's no point showing this option to the user. The correct value will be selected anyway. Signed-off-by: Sascha Hauer --- arch/arm/plat-mxc/Kconfig | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) (limited to 'arch/arm/plat-mxc') diff --git a/arch/arm/plat-mxc/Kconfig b/arch/arm/plat-mxc/Kconfig index 6c66bc0..389f217 100644 --- a/arch/arm/plat-mxc/Kconfig +++ b/arch/arm/plat-mxc/Kconfig @@ -63,12 +63,7 @@ config MXC_IRQ_PRIOR Say N here, unless you have a specialized requirement. config MXC_TZIC - bool "Enable TrustZone Interrupt Controller" - depends on ARCH_MX51 - help - This will be automatically selected for all processors - containing this interrupt controller. - Say N here only if you are really sure. + bool config MXC_AVIC bool -- cgit v1.1 From c0abefd30b2c9db015df4914a95d268ecdb39b00 Mon Sep 17 00:00:00 2001 From: Dinh Nguyen Date: Mon, 15 Nov 2010 11:29:59 -0600 Subject: ARM: imx: Add core definitions for MX53 Add iomux, clocks, and memory map for Freescale's MX53 SoC. Add cpu_is_mx53 function to common.h. Add 3 more banks of gpio's to mxc_gpio_ports. Add MX53 phys offset address. Signed-off-by: Dinh Nguyen Signed-off-by: Sascha Hauer --- arch/arm/plat-mxc/include/mach/common.h | 5 + arch/arm/plat-mxc/include/mach/hardware.h | 1 + arch/arm/plat-mxc/include/mach/iomux-mx53.h | 303 ++++++++++++++++++++++++ arch/arm/plat-mxc/include/mach/memory.h | 5 +- arch/arm/plat-mxc/include/mach/mx53.h | 353 ++++++++++++++++++++++++++++ arch/arm/plat-mxc/include/mach/mxc.h | 2 + 6 files changed, 668 insertions(+), 1 deletion(-) create mode 100644 arch/arm/plat-mxc/include/mach/iomux-mx53.h create mode 100644 arch/arm/plat-mxc/include/mach/mx53.h (limited to 'arch/arm/plat-mxc') diff --git a/arch/arm/plat-mxc/include/mach/common.h b/arch/arm/plat-mxc/include/mach/common.h index 05676fb..9d58ce5 100644 --- a/arch/arm/plat-mxc/include/mach/common.h +++ b/arch/arm/plat-mxc/include/mach/common.h @@ -21,6 +21,7 @@ extern void mx27_map_io(void); extern void mx31_map_io(void); extern void mx35_map_io(void); extern void mx51_map_io(void); +extern void mx53_map_io(void); extern void mxc91231_map_io(void); extern void mxc_init_irq(void __iomem *); extern void tzic_init_irq(void __iomem *); @@ -31,6 +32,7 @@ extern void mx27_init_irq(void); extern void mx31_init_irq(void); extern void mx35_init_irq(void); extern void mx51_init_irq(void); +extern void mx53_init_irq(void); extern void mxc91231_init_irq(void); extern void epit_timer_init(struct clk *timer_clk, void __iomem *base, int irq); extern void mxc_timer_init(struct clk *timer_clk, void __iomem *, int); @@ -42,6 +44,8 @@ extern int mx31_clocks_init(unsigned long fref); extern int mx35_clocks_init(void); extern int mx51_clocks_init(unsigned long ckil, unsigned long osc, unsigned long ckih1, unsigned long ckih2); +extern int mx53_clocks_init(unsigned long ckil, unsigned long osc, + unsigned long ckih1, unsigned long ckih2); extern int mxc91231_clocks_init(unsigned long fref); extern int mxc_register_gpios(void); extern int mxc_register_device(struct platform_device *pdev, void *data); @@ -51,4 +55,5 @@ extern void mxc91231_power_off(void); extern void mxc91231_arch_reset(int, const char *); extern void mxc91231_prepare_idle(void); extern void mx51_efikamx_reset(void); +extern int mx53_revision(void); #endif diff --git a/arch/arm/plat-mxc/include/mach/hardware.h b/arch/arm/plat-mxc/include/mach/hardware.h index dde777c..f9ed0ba 100644 --- a/arch/arm/plat-mxc/include/mach/hardware.h +++ b/arch/arm/plat-mxc/include/mach/hardware.h @@ -101,6 +101,7 @@ #ifdef CONFIG_ARCH_MX5 #include +#include #endif #ifdef CONFIG_ARCH_MX3 diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx53.h b/arch/arm/plat-mxc/include/mach/iomux-mx53.h new file mode 100644 index 0000000..80cb3c5 --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/iomux-mx53.h @@ -0,0 +1,303 @@ +/* + * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc.. + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#ifndef __MACH_IOMUX_MX53_H__ +#define __MACH_IOMUX_MX53_H__ + +#include + +/* + * various IOMUX alternate output functions (1-7) + */ +typedef enum iomux_config { + IOMUX_CONFIG_ALT0, + IOMUX_CONFIG_ALT1, + IOMUX_CONFIG_ALT2, + IOMUX_CONFIG_ALT3, + IOMUX_CONFIG_ALT4, + IOMUX_CONFIG_ALT5, + IOMUX_CONFIG_ALT6, + IOMUX_CONFIG_ALT7, + IOMUX_CONFIG_GPIO, /* added to help user use GPIO mode */ + IOMUX_CONFIG_SION = 0x1 << 4, /* LOOPBACK:MUX SION bit */ +} iomux_pin_cfg_t; + +/* These 2 defines are for pins that may not have a mux register, but could + * have a pad setting register, and vice-versa. */ +#define NON_MUX_I 0x00 +#define NON_PAD_I 0x00 + +#define MX53_PAD_GPIO_19__GPIO_4_5 IOMUX_PAD(0x348, 0x20,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_KEY_COL0__GPIO_4_6 IOMUX_PAD(0x34C, 0x24,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_KEY_ROW0__GPIO_4_7 IOMUX_PAD(0x350, 0x28,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_KEY_COL1__GPIO_4_8 IOMUX_PAD(0x354, 0x2C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_KEY_ROW1__GPIO_4_9 IOMUX_PAD(0x358, 0x30,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_KEY_COL2__GPIO_4_10 IOMUX_PAD(0x35C, 0x34,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_KEY_ROW2__GPIO_4_11 IOMUX_PAD(0x360, 0x38,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_KEY_COL3__GPIO_4_12 IOMUX_PAD(0x364, 0x3C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_KEY_ROW3__GPIO_4_13 IOMUX_PAD(0x368, 0x40,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_KEY_COL4__GPIO_4_14 IOMUX_PAD(0x36C, 0x44,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_KEY_ROW4__GPIO_4_15 IOMUX_PAD(0x370, 0x48,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_NVCC_KEYPAD__NVCC_KEYPAD IOMUX_PAD(0x374, NON_MUX_I,IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DI0_DISP_CLK__GPIO_4_16 IOMUX_PAD(0x378, 0x4C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DI0_PIN15__GPIO_4_17 IOMUX_PAD(0x37C, 0x50,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DI0_PIN2__GPIO_4_18 IOMUX_PAD(0x380, 0x54,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DI0_PIN3__GPIO_4_19 IOMUX_PAD(0x384, 0x58,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DI0_PIN4__GPIO_4_20 IOMUX_PAD(0x388, 0x5C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT0__GPIO_4_21 IOMUX_PAD(0x38C, 0x60,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT1__GPIO_4_22 IOMUX_PAD(0x390, 0x64,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT2__GPIO_4_23 IOMUX_PAD(0x394, 0x68,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT3__GPIO_4_24 IOMUX_PAD(0x398, 0x6C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT4__GPIO_4_25 IOMUX_PAD(0x39C, 0x70,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT5__GPIO_4_26 IOMUX_PAD(0x3A0, 0x74,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT6__GPIO_4_27 IOMUX_PAD(0x3A4, 0x78,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT7__GPIO_4_28 IOMUX_PAD(0x3A8, 0x7C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT8__GPIO_4_29 IOMUX_PAD(0x3AC, 0x80,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT9__GPIO_4_30 IOMUX_PAD(0x3B0, 0x84,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT10__GPIO_4_31 IOMUX_PAD(0x3B4, 0x88,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT11__GPIO_5_5 IOMUX_PAD(0x3B8, 0x8C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT12__GPIO_5_6 IOMUX_PAD(0x3BC, 0x90,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT13__GPIO_5_7 IOMUX_PAD(0x3C0, 0x94,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT14__GPIO_5_8 IOMUX_PAD(0x3C4, 0x98,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT15__GPIO_5_9 IOMUX_PAD(0x3C8, 0x9C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT16__GPIO_5_10 IOMUX_PAD(0x3CC, 0xA0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT17__GPIO_5_11 IOMUX_PAD(0x3D0, 0xA4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT18__GPIO_5_12 IOMUX_PAD(0x3D4, 0xA8,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT19__GPIO_5_13 IOMUX_PAD(0x3D8, 0xAC,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT20__GPIO_5_14 IOMUX_PAD(0x3DC, 0xB0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT21__GPIO_5_15 IOMUX_PAD(0x3E0, 0xB4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT22__GPIO_5_16 IOMUX_PAD(0x3E4, 0xB8,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT23__GPIO_5_17 IOMUX_PAD(0x3E8, 0xBC,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_PIXCLK__GPIO_5_18 IOMUX_PAD(0x3EC, 0xC0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_MCLK__GPIO_5_19 IOMUX_PAD(0x3F0, 0xC4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DATA_EN__GPIO_5_20 IOMUX_PAD(0x3F4, 0xC8,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_VSYNC__GPIO_5_21 IOMUX_PAD(0x3F8, 0xCC,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_D4__GPIO_5_22 IOMUX_PAD(0x3FC, 0xD0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_D5__GPIO_5_23 IOMUX_PAD(0x400, 0xD4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_D6__GPIO_5_24 IOMUX_PAD(0x404, 0xD8,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_D7__GPIO_5_25 IOMUX_PAD(0x408, 0xDC,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_D8__GPIO_5_26 IOMUX_PAD(0x40C, 0xE0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_D9__GPIO_5_27 IOMUX_PAD(0x410, 0xE4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_D10__GPIO_5_28 IOMUX_PAD(0x414, 0xE8,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_D11__GPIO_5_29 IOMUX_PAD(0x418, 0xEC,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_D12__GPIO_5_30 IOMUX_PAD(0x41C, 0xF0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_D13__GPIO_5_31 IOMUX_PAD(0x420, 0xF4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_D14__GPIO_6_0 IOMUX_PAD(0x424, 0xF8,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_D15__GPIO_6_1 IOMUX_PAD(0x428, 0xFC,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_D16__GPIO_6_2 IOMUX_PAD(0x42C, 0x100,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_D17__GPIO_6_3 IOMUX_PAD(0x430, 0x104,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_D18__GPIO_6_4 IOMUX_PAD(0x434, 0x108,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_D19__GPIO_6_5 IOMUX_PAD(0x438, 0x10C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_NVCC_CSI0__NVCC_CSI0 IOMUX_PAD(0x43C, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_JTAG_TMS__JTAG_TMS IOMUX_PAD(0x440, NON_MUX_I,IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_JTAG_MOD__JTAG_MOD IOMUX_PAD(0x444, NON_MUX_I,IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_JTAG_TRSTB__JTAG_TRSTB IOMUX_PAD(0x448, NON_MUX_I,IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_JTAG_TDI__JTAG_TDI IOMUX_PAD(0x44C, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_JTAG_TCK__JTAG_TCK IOMUX_PAD(0x450, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_JTAG_TDO__JTAG_TDO IOMUX_PAD(0x454, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_A25__GPIO_5_2 IOMUX_PAD(0x458, 0x110,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_EB2__GPIO_2_30 IOMUX_PAD(0x45C, 0x114,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D16__GPIO_3_16 IOMUX_PAD(0x460, 0x118,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D17__GPIO_3_17 IOMUX_PAD(0x464, 0x11C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D18__GPIO_3_18 IOMUX_PAD(0x468, 0x120,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D19__GPIO_3_19 IOMUX_PAD(0x46C, 0x124,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D20__GPIO_3_20 IOMUX_PAD(0x470, 0x128,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D21__GPIO_3_21 IOMUX_PAD(0x474, 0x12C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D22__GPIO_3_22 IOMUX_PAD(0x478, 0x130,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D23__GPIO_3_23 IOMUX_PAD(0x47C, 0x134,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_EB3__GPIO_2_31 IOMUX_PAD(0x480, 0x138,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D24__GPIO_3_24 IOMUX_PAD(0x484, 0x13C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D25__GPIO_3_25 IOMUX_PAD(0x488, 0x140,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D26__GPIO_3_26 IOMUX_PAD(0x48C, 0x144,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D27__GPIO_3_27 IOMUX_PAD(0x490, 0x148,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D28__GPIO_3_28 IOMUX_PAD(0x494, 0x14C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D29__GPIO_3_29 IOMUX_PAD(0x498, 0x150,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D30__GPIO_3_30 IOMUX_PAD(0x49C, 0x154,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D31__GPIO_3_31 IOMUX_PAD(0x4A0, 0x158,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_NVCC_EIM1__NVCC_EIM1 IOMUX_PAD(0x4A4, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_A24__GPIO_5_4 IOMUX_PAD(0x4A8, 0x15C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_A23__GPIO_6_6 IOMUX_PAD(0x4AC, 0x160,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_A22__GPIO_2_16 IOMUX_PAD(0x4B0, 0x164,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_A21__GPIO_2_17 IOMUX_PAD(0x4B4, 0x168,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_A20__GPIO_2_18 IOMUX_PAD(0x4B8, 0x16C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_A19__GPIO_2_19 IOMUX_PAD(0x4BC, 0x170,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_A18__GPIO_2_20 IOMUX_PAD(0x4C0, 0x174,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_A17__GPIO_2_21 IOMUX_PAD(0x4C4, 0x178,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_A16__GPIO_2_22 IOMUX_PAD(0x4C8, 0x17C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_CS0__GPIO_2_23 IOMUX_PAD(0x4CC, 0x180,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_CS1__GPIO_2_24 IOMUX_PAD(0x4D0, 0x184,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_OE__GPIO_2_25 IOMUX_PAD(0x4D4, 0x188,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_RW__GPIO_2_26 IOMUX_PAD(0x4D8, 0x18C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_LBA__GPIO_2_27 IOMUX_PAD(0x4DC, 0x190,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_NVCC_EIM4__NVCC_EIM4 IOMUX_PAD(0x4E0, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_EB0__GPIO_2_28 IOMUX_PAD(0x4E4, 0x194,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_EB1__GPIO_2_29 IOMUX_PAD(0x4E8, 0x198,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA0__GPIO_3_0 IOMUX_PAD(0x4EC, 0x19C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA1__GPIO_3_1 IOMUX_PAD(0x4F0, 0x1A0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA2__GPIO_3_2 IOMUX_PAD(0x4F4, 0x1A4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA3__GPIO_3_3 IOMUX_PAD(0x4F8, 0x1A8,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA4__GPIO_3_4 IOMUX_PAD(0x4FC, 0x1AC,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA5__GPIO_3_5 IOMUX_PAD(0x500, 0x1B0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA6__GPIO_3_6 IOMUX_PAD(0x504, 0x1B4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA7__GPIO_3_7 IOMUX_PAD(0x508, 0x1B8,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA8__GPIO_3_8 IOMUX_PAD(0x50C, 0x1BC,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA9__GPIO_3_9 IOMUX_PAD(0x510, 0x1C0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA10__GPIO_3_10 IOMUX_PAD(0x514, 0x1C4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA11__GPIO_3_11 IOMUX_PAD(0x518, 0x1C8,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA12__GPIO_3_12 IOMUX_PAD(0x51C, 0x1CC,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA13__GPIO_3_13 IOMUX_PAD(0x520, 0x1D0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA14__GPIO_3_14 IOMUX_PAD(0x524, 0x1D4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA15__GPIO_3_15 IOMUX_PAD(0x528, 0x1D8,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_NANDF_WE_B__GPIO_6_12 IOMUX_PAD(0x52C, 0x1DC,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_NANDF_RE_B__GPIO_6_13 IOMUX_PAD(0x530, 0x1E0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_WAIT__GPIO_5_0 IOMUX_PAD(0x534, 0x1E4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_BCLK__EIM_BCLK IOMUX_PAD(0x538, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_NVCC_EIM7__NVCC_EIM7 IOMUX_PAD(0x53C, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_LVDS1_TX3_P__GPIO_6_22 IOMUX_PAD(NON_PAD_I, 0x1EC, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_LVDS1_TX2_P__GPIO_6_24 IOMUX_PAD(NON_PAD_I, 0x1F0, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_LVDS1_CLK_P__GPIO_6_26 IOMUX_PAD(NON_PAD_I, 0x1F4, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_LVDS1_TX1_P__GPIO_6_28 IOMUX_PAD(NON_PAD_I, 0x1F8, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_LVDS1_TX0_P__GPIO_6_30 IOMUX_PAD(NON_PAD_I, 0x1FC, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_LVDS0_TX3_P__GPIO_7_22 IOMUX_PAD(NON_PAD_I, 0x200, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_LVDS0_CLK_P__GPIO_7_24 IOMUX_PAD(NON_PAD_I, 0x204, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_LVDS0_TX2_P__GPIO_7_26 IOMUX_PAD(NON_PAD_I, 0x208, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_LVDS0_TX1_P__GPIO_7_28 IOMUX_PAD(NON_PAD_I, 0x20C, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_LVDS0_TX0_P__GPIO_7_30 IOMUX_PAD(NON_PAD_I, 0x210, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_10__GPIO_4_0 IOMUX_PAD(0x540, 0x214, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_11__GPIO_4_1 IOMUX_PAD(0x544, 0x218, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_12__GPIO_4_2 IOMUX_PAD(0x548, 0x21C, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_13__GPIO_4_3 IOMUX_PAD(0x54C, 0x220, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_14__GPIO_4_4 IOMUX_PAD(0x550, 0x224, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DRAM_DQM3__DRAM_DQM3 IOMUX_PAD(0x554, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DRAM_SDQS3__DRAM_SDQS3 IOMUX_PAD(0x558, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DRAM_SDCKE1__DRAM_SDCKE1 IOMUX_PAD(0x55C, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DRAM_DQM2__DRAM_DQM2 IOMUX_PAD(0x560, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DRAM_SDODT1__DRAM_SDODT1 IOMUX_PAD(0x564, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DRAM_SDQS2__DRAM_SDQS2 IOMUX_PAD(0x568, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DRAM_RESET__DRAM_RESET IOMUX_PAD(0x56C, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DRAM_SDCLK1__DRAM_SDCLK1 IOMUX_PAD(0x570, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DRAM_CAS__DRAM_CAS IOMUX_PAD(0x574, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DRAM_SDCLK0__DRAM_SDCLK0 IOMUX_PAD(0x578, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DRAM_SDQS0__DRAM_SDQS0 IOMUX_PAD(0x57C, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DRAM_SDODT0__DRAM_SDODT0 IOMUX_PAD(0x580, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DRAM_DQM0__DRAM_DQM0 IOMUX_PAD(0x584, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DRAM_RAS__DRAM_RAS IOMUX_PAD(0x588, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DRAM_SDCKE0__DRAM_SDCKE0 IOMUX_PAD(0x58C, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DRAM_SDQS1__DRAM_SDQS1 IOMUX_PAD(0x590, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DRAM_DQM1__DRAM_DQM1 IOMUX_PAD(0x594, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_PMIC_ON_REQ__PMIC_ON_REQ IOMUX_PAD(0x598, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_PMIC_STBY_REQ__PMIC_STBY_REQ IOMUX_PAD(0x59C, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_NANDF_CLE__GPIO_6_7 IOMUX_PAD(0x5A0, 0x228,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_NANDF_ALE__GPIO_6_8 IOMUX_PAD(0x5A4, 0x22C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_NANDF_WP_B__GPIO_6_9 IOMUX_PAD(0x5A8, 0x230,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_NANDF_RB0__GPIO_6_10 IOMUX_PAD(0x5AC, 0x234,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_NANDF_CS0__GPIO_6_11 IOMUX_PAD(0x5B0, 0x238,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_NANDF_CS1__GPIO_6_14 IOMUX_PAD(0x5B4, 0x23C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_NANDF_CS2__GPIO_6_15 IOMUX_PAD(0x5B8, 0x240,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_NANDF_CS3__GPIO_6_16 IOMUX_PAD(0x5BC, 0x244,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_NVCC_NANDF__NVCC_NANDF IOMUX_PAD(0x5C0, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_FEC_MDIO__GPIO_1_22 IOMUX_PAD(0x5C4, 0x248,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_FEC_REF_CLK__GPIO_1_23 IOMUX_PAD(0x5C8, 0x24C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_FEC_RX_ER__GPIO_1_24 IOMUX_PAD(0x5CC, 0x250,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_FEC_CRS_DV__GPIO_1_25 IOMUX_PAD(0x5D0, 0x254,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_FEC_RXD1__GPIO_1_26 IOMUX_PAD(0x5D4, 0x258,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_FEC_RXD0__GPIO_1_27 IOMUX_PAD(0x5D8, 0x25C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_FEC_TX_EN__GPIO_1_28 IOMUX_PAD(0x5DC, 0x260,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_FEC_TXD1__GPIO_1_29 IOMUX_PAD(0x5E0, 0x264,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_FEC_TXD0__GPIO_1_30 IOMUX_PAD(0x5E4, 0x268,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_FEC_MDC__GPIO_1_31 IOMUX_PAD(0x5E8, 0x26C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_NVCC_FEC__NVCC_FEC IOMUX_PAD(0x5EC, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_ATA_DIOW__GPIO_6_17 IOMUX_PAD(0x5F0, 0x270,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_ATA_DMACK__GPIO_6_18 IOMUX_PAD(0x5F4, 0x274,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_ATA_DMARQ__GPIO_7_0 IOMUX_PAD(0x5F8, 0x278,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_ATA_BUFFER_EN__GPIO_7_1 IOMUX_PAD(0x5FC, 0x27C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_ATA_INTRQ__GPIO_7_2 IOMUX_PAD(0x600, 0x280,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_ATA_DIOR__GPIO_7_3 IOMUX_PAD(0x604, 0x284,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_ATA_RESET_B__GPIO_7_4 IOMUX_PAD(0x608, 0x288,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_ATA_IORDY__GPIO_7_5 IOMUX_PAD(0x60C, 0x28C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_ATA_DA_0__GPIO_7_6 IOMUX_PAD(0x610, 0x290,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_ATA_DA_1__GPIO_7_7 IOMUX_PAD(0x614, 0x294,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_ATA_DA_2__GPIO_7_8 IOMUX_PAD(0x618, 0x298,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_ATA_CS_0__GPIO_7_9 IOMUX_PAD(0x61C, 0x29C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_ATA_CS_1__GPIO_7_10 IOMUX_PAD(0x620, 0x2A0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_NVCC_ATA2__NVCC_ATA2 IOMUX_PAD(0x624, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_ATA_DATA0__GPIO_2_0 IOMUX_PAD(0x628, 0x2A4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_ATA_DATA1__GPIO_2_1 IOMUX_PAD(0x62C, 0x2A8,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_ATA_DATA2__GPIO_2_2 IOMUX_PAD(0x630, 0x2AC,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_ATA_DATA3__GPIO_2_3 IOMUX_PAD(0x634, 0x2B0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_ATA_DATA4__GPIO_2_4 IOMUX_PAD(0x638, 0x2B4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_ATA_DATA5__GPIO_2_5 IOMUX_PAD(0x63C, 0x2B8,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_ATA_DATA6__GPIO_2_6 IOMUX_PAD(0x640, 0x2BC,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_ATA_DATA7__GPIO_2_7 IOMUX_PAD(0x644, 0x2C0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_ATA_DATA8__GPIO_2_8 IOMUX_PAD(0x648, 0x2C4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_ATA_DATA9__GPIO_2_9 IOMUX_PAD(0x64C, 0x2C8,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_ATA_DATA10__GPIO_2_10 IOMUX_PAD(0x650, 0x2CC,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_ATA_DATA11__GPIO_2_11 IOMUX_PAD(0x654, 0x2D0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_ATA_DATA12__GPIO_2_12 IOMUX_PAD(0x658, 0x2D4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_ATA_DATA13__GPIO_2_13 IOMUX_PAD(0x65C, 0x2D8,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_ATA_DATA14__GPIO_2_14 IOMUX_PAD(0x660, 0x2DC,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_ATA_DATA15__GPIO_2_15 IOMUX_PAD(0x664, 0x2E0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_NVCC_ATA0__NVCC_ATA0 IOMUX_PAD(0x668, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_SD1_DATA0__GPIO_1_16 IOMUX_PAD(0x66C, 0x2E4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_SD1_DATA1__GPIO_1_17 IOMUX_PAD(0x670, 0x2E8,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_SD1_CMD__GPIO_1_18 IOMUX_PAD(0x674, 0x2EC,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_SD1_DATA2__GPIO_1_19 IOMUX_PAD(0x678, 0x2F0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_SD1_CLK__GPIO_1_20 IOMUX_PAD(0x67C, 0x2F4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_SD1_DATA3__GPIO_1_21 IOMUX_PAD(0x680, 0x2F8,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_NVCC_SD1__NVCC_SD1 IOMUX_PAD(0x684, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_SD2_CLK__GPIO_1_10 IOMUX_PAD(0x688, 0x2FC,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_SD2_CMD__GPIO_1_11 IOMUX_PAD(0x68C, 0x300,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_SD2_DATA3__GPIO_1_12 IOMUX_PAD(0x690, 0x304,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_SD2_DATA2__GPIO_1_13 IOMUX_PAD(0x694, 0x308,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_SD2_DATA1__GPIO_1_14 IOMUX_PAD(0x698, 0x30C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_SD2_DATA0__GPIO_1_15 IOMUX_PAD(0x69C, 0x310,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_NVCC_SD2__NVCC_SD2 IOMUX_PAD(0x6A0, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_0__GPIO_1_0 IOMUX_PAD(0x6A4, 0x314,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_1__GPIO_1_1 IOMUX_PAD(0x6A8, 0x318,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_9__GPIO_1_9 IOMUX_PAD(0x6AC, 0x31C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_3__GPIO_1_3 IOMUX_PAD(0x6B0, 0x320,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_6__GPIO_1_6 IOMUX_PAD(0x6B4, 0x324,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_2__GPIO_1_2 IOMUX_PAD(0x6B8, 0x328,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_4__GPIO_1_4 IOMUX_PAD(0x6BC, 0x32C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_5__GPIO_1_5 IOMUX_PAD(0x6C0, 0x330,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_7__GPIO_1_7 IOMUX_PAD(0x6C4, 0x334,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_8__GPIO_1_8 IOMUX_PAD(0x6C8, 0x338,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_16__GPIO_7_11 IOMUX_PAD(0x6CC, 0x33C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_17__GPIO_7_12 IOMUX_PAD(0x6D0, 0x340,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_18__GPIO_7_13 IOMUX_PAD(0x6D4, 0x344,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_NVCC_GPIO__NVCC_GPIO IOMUX_PAD(0x6D8, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_POR_B__POR_B IOMUX_PAD(0x6DC, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_BOOT_MODE1__BOOT_MODE1 IOMUX_PAD(0x6E0, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_RESET_IN_B__RESET_IN_B IOMUX_PAD(0x6E4, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_BOOT_MODE0__BOOT_MODE0 IOMUX_PAD(0x6E8, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_TEST_MODE__TEST_MODE IOMUX_PAD(0x6EC, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_GRP_ADDDS__GRP_ADDDS IOMUX_PAD(0x6F0, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_GRP_DDRMODE_CTL__GRP_DDRMODE_CTL IOMUX_PAD(0x6F4, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_GRP_DDRPKE__GRP_DDRPKE IOMUX_PAD(0x6FC, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_GRP_DDRPK__GRP_DDRPK IOMUX_PAD(0x708, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_GRP_TERM_CTL3__GRP_TERM_CTL3 IOMUX_PAD(0x70C, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_GRP_DDRHYS__GRP_DDRHYS IOMUX_PAD(0x710, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_GRP_DDRMODE__GRP_DDRMODE IOMUX_PAD(0x714, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_GRP_B0DS__GRP_B0DS IOMUX_PAD(0x718, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_GRP_B1DS__GRP_B1DS IOMUX_PAD(0x71C, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_GRP_CTLDS__GRP_CTLDS IOMUX_PAD(0x720, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_GRP_DDR_TYPE__GRP_DDR_TYPE IOMUX_PAD(0x724, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_GRP_B2DS__GRP_B2DS IOMUX_PAD(0x728, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_GRP_B3DS__GRP_B3DS IOMUX_PAD(0x72C, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) + +#endif /* __MACH_IOMUX_MX53_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/memory.h b/arch/arm/plat-mxc/include/mach/memory.h index 564ec9d..9a9a000 100644 --- a/arch/arm/plat-mxc/include/mach/memory.h +++ b/arch/arm/plat-mxc/include/mach/memory.h @@ -17,6 +17,7 @@ #define MX27_PHYS_OFFSET UL(0xa0000000) #define MX3x_PHYS_OFFSET UL(0x80000000) #define MX51_PHYS_OFFSET UL(0x90000000) +#define MX53_PHYS_OFFSET UL(0x70000000) #define MXC91231_PHYS_OFFSET UL(0x90000000) #if !defined(CONFIG_RUNTIME_PHYS_OFFSET) @@ -32,8 +33,10 @@ # define PHYS_OFFSET MX3x_PHYS_OFFSET # elif defined CONFIG_ARCH_MXC91231 # define PHYS_OFFSET MXC91231_PHYS_OFFSET -# elif defined CONFIG_ARCH_MX5 +# elif defined CONFIG_ARCH_MX51 # define PHYS_OFFSET MX51_PHYS_OFFSET +# elif defined CONFIG_ARCH_MX53 +# define PHYS_OFFSET MX53_PHYS_OFFSET # endif #endif diff --git a/arch/arm/plat-mxc/include/mach/mx53.h b/arch/arm/plat-mxc/include/mach/mx53.h new file mode 100644 index 0000000..9577cdb --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/mx53.h @@ -0,0 +1,353 @@ +#ifndef __MACH_MX53_H__ +#define __MACH_MX53_H__ + +/* + * IROM + */ +#define MX53_IROM_BASE_ADDR 0x0 +#define MX53_IROM_SIZE SZ_64K + +/* TZIC */ +#define MX53_TZIC_BASE_ADDR 0x0FFFC000 + +/* + * AHCI SATA + */ +#define MX53_SATA_BASE_ADDR 0x10000000 + +/* + * NFC + */ +#define MX53_NFC_AXI_BASE_ADDR 0xF7FF0000 /* NAND flash AXI */ +#define MX53_NFC_AXI_SIZE SZ_64K + +/* + * IRAM + */ +#define MX53_IRAM_BASE_ADDR 0xF8000000 /* internal ram */ +#define MX53_IRAM_PARTITIONS 16 +#define MX53_IRAM_SIZE (MX53_IRAM_PARTITIONS * SZ_8K) /* 128KB */ + +/* + * Graphics Memory of GPU + */ +#define MX53_IPU_CTRL_BASE_ADDR 0x18000000 +#define MX53_GPU2D_BASE_ADDR 0x20000000 +#define MX53_GPU_BASE_ADDR 0x30000000 +#define MX53_GPU_GMEM_BASE_ADDR 0xF8020000 + +#define MX53_DEBUG_BASE_ADDR 0x40000000 +#define MX53_DEBUG_SIZE SZ_1M +#define MX53_ETB_BASE_ADDR (MX53_DEBUG_BASE_ADDR + 0x00001000) +#define MX53_ETM_BASE_ADDR (MX53_DEBUG_BASE_ADDR + 0x00002000) +#define MX53_TPIU_BASE_ADDR (MX53_DEBUG_BASE_ADDR + 0x00003000) +#define MX53_CTI0_BASE_ADDR (MX53_DEBUG_BASE_ADDR + 0x00004000) +#define MX53_CTI1_BASE_ADDR (MX53_DEBUG_BASE_ADDR + 0x00005000) +#define MX53_CTI2_BASE_ADDR (MX53_DEBUG_BASE_ADDR + 0x00006000) +#define MX53_CTI3_BASE_ADDR (MX53_DEBUG_BASE_ADDR + 0x00007000) +#define MX53_CORTEX_DBG_BASE_ADDR (MX53_DEBUG_BASE_ADDR + 0x00008000) + +/* + * SPBA global module enabled #0 + */ +#define MX53_SPBA0_BASE_ADDR 0x50000000 +#define MX53_SPBA0_SIZE SZ_1M + +#define MX53_MMC_SDHC1_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00004000) +#define MX53_MMC_SDHC2_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00008000) +#define MX53_UART3_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x0000C000) +#define MX53_CSPI1_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00010000) +#define MX53_SSI2_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00014000) +#define MX53_MMC_SDHC3_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00020000) +#define MX53_MMC_SDHC4_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00024000) +#define MX53_SPDIF_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00028000) +#define MX53_ASRC_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x0002C000) +#define MX53_ATA_DMA_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00030000) +#define MX53_SLIM_DMA_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00034000) +#define MX53_HSI2C_DMA_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00038000) +#define MX53_SPBA_CTRL_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x0003C000) + +/* + * AIPS 1 + */ +#define MX53_AIPS1_BASE_ADDR 0x53F00000 +#define MX53_AIPS1_SIZE SZ_1M + +#define MX53_OTG_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x00080000) +#define MX53_GPIO1_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x00084000) +#define MX53_GPIO2_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x00088000) +#define MX53_GPIO3_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x0008C000) +#define MX53_GPIO4_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x00090000) +#define MX53_KPP_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x00094000) +#define MX53_WDOG_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x00098000) +#define MX53_WDOG2_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x0009C000) +#define MX53_GPT1_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000A0000) +#define MX53_SRTC_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000A4000) +#define MX53_IOMUXC_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000A8000) +#define MX53_EPIT1_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000AC000) +#define MX53_EPIT2_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000B0000) +#define MX53_PWM1_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000B4000) +#define MX53_PWM2_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000B8000) +#define MX53_UART1_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000BC000) +#define MX53_UART2_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000C0000) +#define MX53_SRC_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000D0000) +#define MX53_CCM_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000D4000) +#define MX53_GPC_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000D8000) +#define MX53_GPIO5_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000DC000) +#define MX53_GPIO6_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000E0000) +#define MX53_GPIO7_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000E4000) +#define MX53_ATA_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000E8000) +#define MX53_I2C3_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000EC000) +#define MX53_UART4_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000F0000) + +/* + * AIPS 2 + */ +#define MX53_AIPS2_BASE_ADDR 0x63F00000 +#define MX53_AIPS2_SIZE SZ_1M + +#define MX53_PLL1_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x00080000) +#define MX53_PLL2_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x00084000) +#define MX53_PLL3_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x00088000) +#define MX53_PLL4_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x0008C000) +#define MX53_UART5_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x00090000) +#define MX53_AHBMAX_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x00094000) +#define MX53_IIM_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x00098000) +#define MX53_CSU_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x0009C000) +#define MX53_ARM_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000A0000) +#define MX53_OWIRE_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000A4000) +#define MX53_FIRI_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000A8000) +#define MX53_CSPI2_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000AC000) +#define MX53_SDMA_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000B0000) +#define MX53_SCC_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000B4000) +#define MX53_ROMCP_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000B8000) +#define MX53_RTIC_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000BC000) +#define MX53_CSPI3_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000C0000) +#define MX53_I2C2_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000C4000) +#define MX53_I2C1_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000C8000) +#define MX53_SSI1_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000CC000) +#define MX53_AUDMUX_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000D0000) +#define MX53_RTC_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000D4000) +#define MX53_M4IF_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000D8000) +#define MX53_ESDCTL_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000D9000) +#define MX53_WEIM_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000DA000) +#define MX53_NFC_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000DB000) +#define MX53_EMI_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000DBF00) +#define MX53_MIPI_HSC_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000DC000) +#define MX53_MLB_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000E4000) +#define MX53_SSI3_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000E8000) +#define MX53_MXC_FEC_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000EC000) +#define MX53_TVE_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000F0000) +#define MX53_VPU_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000F4000) +#define MX53_SAHARA_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000F8000) +#define MX53_PTP_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000FC000) + +/* + * Memory regions and CS + */ +#define MX53_CSD0_BASE_ADDR 0x90000000 +#define MX53_CSD1_BASE_ADDR 0xA0000000 +#define MX53_CS0_BASE_ADDR 0xB0000000 +#define MX53_CS1_BASE_ADDR 0xB8000000 +#define MX53_CS2_BASE_ADDR 0xC0000000 +#define MX53_CS3_BASE_ADDR 0xC8000000 +#define MX53_CS4_BASE_ADDR 0xCC000000 +#define MX53_CS5_BASE_ADDR 0xCE000000 + +#define MX53_IO_P2V(x) IMX_IO_P2V(x) +#define MX53_IO_ADDRESS(x) IOMEM(MX53_IO_P2V(x)) + +/* + * defines for SPBA modules + */ +#define MX53_SPBA_SDHC1 0x04 +#define MX53_SPBA_SDHC2 0x08 +#define MX53_SPBA_UART3 0x0C +#define MX53_SPBA_CSPI1 0x10 +#define MX53_SPBA_SSI2 0x14 +#define MX53_SPBA_SDHC3 0x20 +#define MX53_SPBA_SDHC4 0x24 +#define MX53_SPBA_SPDIF 0x28 +#define MX53_SPBA_ATA 0x30 +#define MX53_SPBA_SLIM 0x34 +#define MX53_SPBA_HSI2C 0x38 +#define MX53_SPBA_CTRL 0x3C + +/* + * DMA request assignments + */ +#define MX53_DMA_REQ_SSI3_TX1 47 +#define MX53_DMA_REQ_SSI3_RX1 46 +#define MX53_DMA_REQ_SSI3_TX2 45 +#define MX53_DMA_REQ_SSI3_RX2 44 +#define MX53_DMA_REQ_UART3_TX 43 +#define MX53_DMA_REQ_UART3_RX 42 +#define MX53_DMA_REQ_ESAI_TX 41 +#define MX53_DMA_REQ_ESAI_RX 40 +#define MX53_DMA_REQ_CSPI_TX 39 +#define MX53_DMA_REQ_CSPI_RX 38 +#define MX53_DMA_REQ_ASRC_DMA6 37 +#define MX53_DMA_REQ_ASRC_DMA5 36 +#define MX53_DMA_REQ_ASRC_DMA4 35 +#define MX53_DMA_REQ_ASRC_DMA3 34 +#define MX53_DMA_REQ_ASRC_DMA2 33 +#define MX53_DMA_REQ_ASRC_DMA1 32 +#define MX53_DMA_REQ_EMI_WR 31 +#define MX53_DMA_REQ_EMI_RD 30 +#define MX53_DMA_REQ_SSI1_TX1 29 +#define MX53_DMA_REQ_SSI1_RX1 28 +#define MX53_DMA_REQ_SSI1_TX2 27 +#define MX53_DMA_REQ_SSI1_RX2 26 +#define MX53_DMA_REQ_SSI2_TX1 25 +#define MX53_DMA_REQ_SSI2_RX1 24 +#define MX53_DMA_REQ_SSI2_TX2 23 +#define MX53_DMA_REQ_SSI2_RX2 22 +#define MX53_DMA_REQ_I2C2_SDHC2 21 +#define MX53_DMA_REQ_I2C1_SDHC1 20 +#define MX53_DMA_REQ_UART1_TX 19 +#define MX53_DMA_REQ_UART1_RX 18 +#define MX53_DMA_REQ_UART5_TX 17 +#define MX53_DMA_REQ_UART5_RX 16 +#define MX53_DMA_REQ_SPDIF_TX 15 +#define MX53_DMA_REQ_SPDIF_RX 14 +#define MX53_DMA_REQ_UART2_FIRI_TX 13 +#define MX53_DMA_REQ_UART2_FIRI_RX 12 +#define MX53_DMA_REQ_SDHC4 11 +#define MX53_DMA_REQ_I2C3_SDHC3 10 +#define MX53_DMA_REQ_CSPI2_TX 9 +#define MX53_DMA_REQ_CSPI2_RX 8 +#define MX53_DMA_REQ_CSPI1_TX 7 +#define MX53_DMA_REQ_CSPI1_RX 6 +#define MX53_DMA_REQ_IPU 5 +#define MX53_DMA_REQ_ATA_TX_END 4 +#define MX53_DMA_REQ_ATA_UART4_TX 3 +#define MX53_DMA_REQ_ATA_UART4_RX 2 +#define MX53_DMA_REQ_GPC 1 +#define MX53_DMA_REQ_VPU 0 + +/* + * Interrupt numbers + */ +#define MX53_INT_RESV0 0 +#define MX53_INT_MMC_SDHC1 1 +#define MX53_INT_MMC_SDHC2 2 +#define MX53_INT_MMC_SDHC3 3 +#define MX53_INT_MMC_SDHC4 4 +#define MX53_INT_RESV5 5 +#define MX53_INT_SDMA 6 +#define MX53_INT_IOMUX 7 +#define MX53_INT_NFC 8 +#define MX53_INT_VPU 9 +#define MX53_INT_IPU_ERR 10 +#define MX53_INT_IPU_SYN 11 +#define MX53_INT_GPU 12 +#define MX53_INT_RESV13 13 +#define MX53_INT_USB_H1 14 +#define MX53_INT_EMI 15 +#define MX53_INT_USB_H2 16 +#define MX53_INT_USB_H3 17 +#define MX53_INT_USB_OTG 18 +#define MX53_INT_SAHARA_H0 19 +#define MX53_INT_SAHARA_H1 20 +#define MX53_INT_SCC_SMN 21 +#define MX53_INT_SCC_STZ 22 +#define MX53_INT_SCC_SCM 23 +#define MX53_INT_SRTC_NTZ 24 +#define MX53_INT_SRTC_TZ 25 +#define MX53_INT_RTIC 26 +#define MX53_INT_CSU 27 +#define MX53_INT_SATA 28 +#define MX53_INT_SSI1 29 +#define MX53_INT_SSI2 30 +#define MX53_INT_UART1 31 +#define MX53_INT_UART2 32 +#define MX53_INT_UART3 33 +#define MX53_INT_RESV34 34 +#define MX53_INT_RESV35 35 +#define MX53_INT_CSPI1 36 +#define MX53_INT_CSPI2 37 +#define MX53_INT_CSPI 38 +#define MX53_INT_GPT 39 +#define MX53_INT_EPIT1 40 +#define MX53_INT_EPIT2 41 +#define MX53_INT_GPIO1_INT7 42 +#define MX53_INT_GPIO1_INT6 43 +#define MX53_INT_GPIO1_INT5 44 +#define MX53_INT_GPIO1_INT4 45 +#define MX53_INT_GPIO1_INT3 46 +#define MX53_INT_GPIO1_INT2 47 +#define MX53_INT_GPIO1_INT1 48 +#define MX53_INT_GPIO1_INT0 49 +#define MX53_INT_GPIO1_LOW 50 +#define MX53_INT_GPIO1_HIGH 51 +#define MX53_INT_GPIO2_LOW 52 +#define MX53_INT_GPIO2_HIGH 53 +#define MX53_INT_GPIO3_LOW 54 +#define MX53_INT_GPIO3_HIGH 55 +#define MX53_INT_GPIO4_LOW 56 +#define MX53_INT_GPIO4_HIGH 57 +#define MX53_INT_WDOG1 58 +#define MX53_INT_WDOG2 59 +#define MX53_INT_KPP 60 +#define MX53_INT_PWM1 61 +#define MX53_INT_I2C1 62 +#define MX53_INT_I2C2 63 +#define MX53_INT_I2C3 64 +#define MX53_INT_RESV65 65 +#define MX53_INT_RESV66 66 +#define MX53_INT_SPDIF 67 +#define MX53_INT_SIM_DAT 68 +#define MX53_INT_IIM 69 +#define MX53_INT_ATA 70 +#define MX53_INT_CCM1 71 +#define MX53_INT_CCM2 72 +#define MX53_INT_GPC1 73 +#define MX53_INT_GPC2 74 +#define MX53_INT_SRC 75 +#define MX53_INT_NM 76 +#define MX53_INT_PMU 77 +#define MX53_INT_CTI_IRQ 78 +#define MX53_INT_CTI1_TG0 79 +#define MX53_INT_CTI1_TG1 80 +#define MX53_INT_ESAI 81 +#define MX53_INT_CAN1 82 +#define MX53_INT_CAN2 83 +#define MX53_INT_GPU2_IRQ 84 +#define MX53_INT_GPU2_BUSY 85 +#define MX53_INT_RESV86 86 +#define MX53_INT_FEC 87 +#define MX53_INT_OWIRE 88 +#define MX53_INT_CTI1_TG2 89 +#define MX53_INT_SJC 90 +#define MX53_INT_TVE 92 +#define MX53_INT_FIRI 93 +#define MX53_INT_PWM2 94 +#define MX53_INT_SLIM_EXP 95 +#define MX53_INT_SSI3 96 +#define MX53_INT_EMI_BOOT 97 +#define MX53_INT_CTI1_TG3 98 +#define MX53_INT_SMC_RX 99 +#define MX53_INT_VPU_IDLE 100 +#define MX53_INT_EMI_NFC 101 +#define MX53_INT_GPU_IDLE 102 +#define MX53_INT_GPIO5_LOW 103 +#define MX53_INT_GPIO5_HIGH 104 +#define MX53_INT_GPIO6_LOW 105 +#define MX53_INT_GPIO6_HIGH 106 +#define MX53_INT_GPIO7_LOW 107 +#define MX53_INT_GPIO7_HIGH 108 + +/* silicon revisions specific to i.MX53 */ +#define MX53_CHIP_REV_1_0 0x10 +#define MX53_CHIP_REV_1_1 0x11 +#define MX53_CHIP_REV_1_2 0x12 +#define MX53_CHIP_REV_1_3 0x13 +#define MX53_CHIP_REV_2_0 0x20 +#define MX53_CHIP_REV_2_1 0x21 +#define MX53_CHIP_REV_2_2 0x22 +#define MX53_CHIP_REV_2_3 0x23 +#define MX53_CHIP_REV_3_0 0x30 +#define MX53_CHIP_REV_3_1 0x31 +#define MX53_CHIP_REV_3_2 0x32 + +#endif /* ifndef __MACH_MX53_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/mxc.h b/arch/arm/plat-mxc/include/mach/mxc.h index a42c720..4c17515 100644 --- a/arch/arm/plat-mxc/include/mach/mxc.h +++ b/arch/arm/plat-mxc/include/mach/mxc.h @@ -33,6 +33,7 @@ #define MXC_CPU_MX31 31 #define MXC_CPU_MX35 35 #define MXC_CPU_MX51 51 +#define MXC_CPU_MX53 53 #define MXC_CPU_MXC91231 91231 #ifndef __ASSEMBLY__ @@ -119,6 +120,7 @@ extern unsigned int __mxc_cpu_type; # define mxc_cpu_type MXC_CPU_MX51 # endif # define cpu_is_mx51() (mxc_cpu_type == MXC_CPU_MX51) +# define cpu_is_mx53() (mxc_cpu_type == MXC_CPU_MX53) #else # define cpu_is_mx51() (0) #endif -- cgit v1.1 From 9ab4650f718a0e1cb8792bab4ef97efca4ac75c2 Mon Sep 17 00:00:00 2001 From: Dinh Nguyen Date: Mon, 15 Nov 2010 11:30:01 -0600 Subject: ARM: imx: Get the silicon version from the IIM module Instead of reading the silicon version from ROM, we should read the SREV register from the IIM. Freescale has dropped all support for MX51 REV1.0, only MX51 REV 2.0 and 3.0 are valid. Signed-off-by: Dinh Nguyen Signed-off-by: Sascha Hauer --- arch/arm/plat-mxc/include/mach/mx27.h | 4 ---- arch/arm/plat-mxc/include/mach/mx31.h | 16 ---------------- arch/arm/plat-mxc/include/mach/mx35.h | 3 --- arch/arm/plat-mxc/include/mach/mx3x.h | 16 ---------------- arch/arm/plat-mxc/include/mach/mx51.h | 13 ------------- arch/arm/plat-mxc/include/mach/mxc.h | 14 ++++++++++++++ 6 files changed, 14 insertions(+), 52 deletions(-) (limited to 'arch/arm/plat-mxc') diff --git a/arch/arm/plat-mxc/include/mach/mx27.h b/arch/arm/plat-mxc/include/mach/mx27.h index eb09ec0..cbc43ad 100644 --- a/arch/arm/plat-mxc/include/mach/mx27.h +++ b/arch/arm/plat-mxc/include/mach/mx27.h @@ -244,10 +244,6 @@ static inline void mx27_setup_weimcs(size_t cs, #define MX27_DMA_REQ_SDHC3 36 #define MX27_DMA_REQ_NFC 37 -/* silicon revisions specific to i.MX27 */ -#define CHIP_REV_1_0 0x00 -#define CHIP_REV_2_0 0x01 - #ifndef __ASSEMBLY__ extern int mx27_revision(void); #endif diff --git a/arch/arm/plat-mxc/include/mach/mx31.h b/arch/arm/plat-mxc/include/mach/mx31.h index 09232314..79e7fc0 100644 --- a/arch/arm/plat-mxc/include/mach/mx31.h +++ b/arch/arm/plat-mxc/include/mach/mx31.h @@ -203,20 +203,4 @@ static inline void mx31_setup_weimcs(size_t cs, #define MX31_PROD_SIGNATURE 0x1 /* For MX31 */ -/* silicon revisions specific to i.MX31 */ -#define MX31_CHIP_REV_1_0 0x10 -#define MX31_CHIP_REV_1_1 0x11 -#define MX31_CHIP_REV_1_2 0x12 -#define MX31_CHIP_REV_1_3 0x13 -#define MX31_CHIP_REV_2_0 0x20 -#define MX31_CHIP_REV_2_1 0x21 -#define MX31_CHIP_REV_2_2 0x22 -#define MX31_CHIP_REV_2_3 0x23 -#define MX31_CHIP_REV_3_0 0x30 -#define MX31_CHIP_REV_3_1 0x31 -#define MX31_CHIP_REV_3_2 0x32 - -#define MX31_SYSTEM_REV_MIN MX31_CHIP_REV_1_0 -#define MX31_SYSTEM_REV_NUM 3 - #endif /* ifndef __MACH_MX31_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/mx35.h b/arch/arm/plat-mxc/include/mach/mx35.h index 0fa3f68..d13dbfe 100644 --- a/arch/arm/plat-mxc/include/mach/mx35.h +++ b/arch/arm/plat-mxc/include/mach/mx35.h @@ -186,7 +186,4 @@ #define MX35_PROD_SIGNATURE 0x1 /* For MX31 */ -#define MX35_SYSTEM_REV_MIN MX3x_CHIP_REV_1_0 -#define MX35_SYSTEM_REV_NUM 3 - #endif /* ifndef __MACH_MX35_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/mx3x.h b/arch/arm/plat-mxc/include/mach/mx3x.h index 8c7f34e..388a407 100644 --- a/arch/arm/plat-mxc/include/mach/mx3x.h +++ b/arch/arm/plat-mxc/include/mach/mx3x.h @@ -184,22 +184,6 @@ #define MX3x_PROD_SIGNATURE 0x1 /* For MX31 */ -/* silicon revisions specific to i.MX31 and i.MX35 */ -#define MX3x_CHIP_REV_1_0 0x10 -#define MX3x_CHIP_REV_1_1 0x11 -#define MX3x_CHIP_REV_1_2 0x12 -#define MX3x_CHIP_REV_1_3 0x13 -#define MX3x_CHIP_REV_2_0 0x20 -#define MX3x_CHIP_REV_2_1 0x21 -#define MX3x_CHIP_REV_2_2 0x22 -#define MX3x_CHIP_REV_2_3 0x23 -#define MX3x_CHIP_REV_3_0 0x30 -#define MX3x_CHIP_REV_3_1 0x31 -#define MX3x_CHIP_REV_3_2 0x32 - -#define MX3x_SYSTEM_REV_MIN MX3x_CHIP_REV_1_0 -#define MX3x_SYSTEM_REV_NUM 3 - /* Mandatory defines used globally */ #if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS) diff --git a/arch/arm/plat-mxc/include/mach/mx51.h b/arch/arm/plat-mxc/include/mach/mx51.h index 636347c..8fddfef 100644 --- a/arch/arm/plat-mxc/include/mach/mx51.h +++ b/arch/arm/plat-mxc/include/mach/mx51.h @@ -345,19 +345,6 @@ #define MX51_MXC_INT_EMI_NFC 101 #define MX51_MXC_INT_GPU_IDLE 102 -/* silicon revisions specific to i.MX51 */ -#define MX51_CHIP_REV_1_0 0x10 -#define MX51_CHIP_REV_1_1 0x11 -#define MX51_CHIP_REV_1_2 0x12 -#define MX51_CHIP_REV_1_3 0x13 -#define MX51_CHIP_REV_2_0 0x20 -#define MX51_CHIP_REV_2_1 0x21 -#define MX51_CHIP_REV_2_2 0x22 -#define MX51_CHIP_REV_2_3 0x23 -#define MX51_CHIP_REV_3_0 0x30 -#define MX51_CHIP_REV_3_1 0x31 -#define MX51_CHIP_REV_3_2 0x32 - #if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS) extern int mx51_revision(void); #endif diff --git a/arch/arm/plat-mxc/include/mach/mxc.h b/arch/arm/plat-mxc/include/mach/mxc.h index 4c17515..4abbdd1 100644 --- a/arch/arm/plat-mxc/include/mach/mxc.h +++ b/arch/arm/plat-mxc/include/mach/mxc.h @@ -36,6 +36,20 @@ #define MXC_CPU_MX53 53 #define MXC_CPU_MXC91231 91231 +#define IMX_CHIP_REVISION_1_0 0x10 +#define IMX_CHIP_REVISION_1_1 0x11 +#define IMX_CHIP_REVISION_1_2 0x12 +#define IMX_CHIP_REVISION_1_3 0x13 +#define IMX_CHIP_REVISION_2_0 0x20 +#define IMX_CHIP_REVISION_2_1 0x21 +#define IMX_CHIP_REVISION_2_2 0x22 +#define IMX_CHIP_REVISION_2_3 0x23 +#define IMX_CHIP_REVISION_3_0 0x30 +#define IMX_CHIP_REVISION_3_1 0x31 +#define IMX_CHIP_REVISION_3_2 0x32 +#define IMX_CHIP_REVISION_3_3 0x33 +#define IMX_CHIP_REVISION_UNKNOWN 0xff + #ifndef __ASSEMBLY__ extern unsigned int __mxc_cpu_type; #endif -- cgit v1.1 From 5b28aa319bba96987316425a1131813d87cbab35 Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Wed, 6 Oct 2010 15:41:15 +0200 Subject: dmaengine i.MX SDMA: Allow to run without firmware The SDMA firmware consists of a ROM part and a RAM part. The ROM part is always present in the SDMA engine and is sufficient for many cases. This patch allows to pass in platform data containing the script addresses in ROM, so loading a firmware is optional now. Signed-off-by: Sascha Hauer Acked-by: Dan Williams --- arch/arm/plat-mxc/include/mach/sdma.h | 46 +++++++++++++++++++++++++++++++++++ 1 file changed, 46 insertions(+) (limited to 'arch/arm/plat-mxc') diff --git a/arch/arm/plat-mxc/include/mach/sdma.h b/arch/arm/plat-mxc/include/mach/sdma.h index 9be1122..913e043 100644 --- a/arch/arm/plat-mxc/include/mach/sdma.h +++ b/arch/arm/plat-mxc/include/mach/sdma.h @@ -2,16 +2,62 @@ #define __MACH_MXC_SDMA_H__ /** + * struct sdma_script_start_addrs - SDMA script start pointers + * + * start addresses of the different functions in the physical + * address space of the SDMA engine. + */ +struct sdma_script_start_addrs { + s32 ap_2_ap_addr; + s32 ap_2_bp_addr; + s32 ap_2_ap_fixed_addr; + s32 bp_2_ap_addr; + s32 loopback_on_dsp_side_addr; + s32 mcu_interrupt_only_addr; + s32 firi_2_per_addr; + s32 firi_2_mcu_addr; + s32 per_2_firi_addr; + s32 mcu_2_firi_addr; + s32 uart_2_per_addr; + s32 uart_2_mcu_addr; + s32 per_2_app_addr; + s32 mcu_2_app_addr; + s32 per_2_per_addr; + s32 uartsh_2_per_addr; + s32 uartsh_2_mcu_addr; + s32 per_2_shp_addr; + s32 mcu_2_shp_addr; + s32 ata_2_mcu_addr; + s32 mcu_2_ata_addr; + s32 app_2_per_addr; + s32 app_2_mcu_addr; + s32 shp_2_per_addr; + s32 shp_2_mcu_addr; + s32 mshc_2_mcu_addr; + s32 mcu_2_mshc_addr; + s32 spdif_2_mcu_addr; + s32 mcu_2_spdif_addr; + s32 asrc_2_mcu_addr; + s32 ext_mem_2_ipu_addr; + s32 descrambler_addr; + s32 dptc_dvfs_addr; + s32 utra_addr; + s32 ram_code_start_addr; +}; + +/** * struct sdma_platform_data - platform specific data for SDMA engine * * @sdma_version The version of this SDMA engine * @cpu_name used to generate the firmware name * @to_version CPU Tape out version + * @script_addrs SDMA scripts addresses in SDMA ROM */ struct sdma_platform_data { int sdma_version; char *cpu_name; int to_version; + struct sdma_script_start_addrs *script_addrs; }; #endif /* __MACH_MXC_SDMA_H__ */ -- cgit v1.1 From 4e5cf41eeb254b7e50666496ac5697188b31320b Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Thu, 4 Nov 2010 15:50:38 +0100 Subject: ARM i.MX SDMA: Add ROM script addresses to platform_data Signed-off-by: Sascha Hauer --- arch/arm/plat-mxc/devices/platform-imx-dma.c | 105 +++++++++++++++++++++++++-- 1 file changed, 97 insertions(+), 8 deletions(-) (limited to 'arch/arm/plat-mxc') diff --git a/arch/arm/plat-mxc/devices/platform-imx-dma.c b/arch/arm/plat-mxc/devices/platform-imx-dma.c index 10f41cc..93e2fdc 100644 --- a/arch/arm/plat-mxc/devices/platform-imx-dma.c +++ b/arch/arm/plat-mxc/devices/platform-imx-dma.c @@ -40,7 +40,7 @@ struct imx_imx_sdma_data { } #ifdef CONFIG_SOC_IMX25 -const struct imx_imx_sdma_data imx25_imx_sdma_data __initconst = +struct imx_imx_sdma_data imx25_imx_sdma_data __initconst = imx_imx_sdma_data_entry_single(MX25, 1, "imx25", 0); #endif /* ifdef CONFIG_SOC_IMX25 */ @@ -55,7 +55,7 @@ struct imx_imx_sdma_data imx35_imx_sdma_data __initdata = #endif /* ifdef CONFIG_SOC_IMX35 */ #ifdef CONFIG_ARCH_MX51 -const struct imx_imx_sdma_data imx51_imx_sdma_data __initconst = +struct imx_imx_sdma_data imx51_imx_sdma_data __initconst = imx_imx_sdma_data_entry_single(MX51, 2, "imx51", 0); #endif /* ifdef CONFIG_ARCH_MX51 */ @@ -84,6 +84,83 @@ static struct platform_device __init __maybe_unused *imx_add_imx_dma(void) return imx_add_platform_device("imx-dma", -1, NULL, 0, NULL, 0); } +#ifdef CONFIG_ARCH_MX25 +static struct sdma_script_start_addrs addr_imx25_to1 = { + .ap_2_ap_addr = 729, + .uart_2_mcu_addr = 904, + .per_2_app_addr = 1255, + .mcu_2_app_addr = 834, + .uartsh_2_mcu_addr = 1120, + .per_2_shp_addr = 1329, + .mcu_2_shp_addr = 1048, + .ata_2_mcu_addr = 1560, + .mcu_2_ata_addr = 1479, + .app_2_per_addr = 1189, + .app_2_mcu_addr = 770, + .shp_2_per_addr = 1407, + .shp_2_mcu_addr = 979, +}; +#endif + +#ifdef CONFIG_ARCH_MX31 +static struct sdma_script_start_addrs addr_imx31_to1 = { + .per_2_per_addr = 1677, +}; + +static struct sdma_script_start_addrs addr_imx31_to2 = { + .ap_2_ap_addr = 423, + .ap_2_bp_addr = 829, + .bp_2_ap_addr = 1029, +}; +#endif + +#ifdef CONFIG_ARCH_MX35 +static struct sdma_script_start_addrs addr_imx35_to1 = { + .ap_2_ap_addr = 642, + .uart_2_mcu_addr = 817, + .mcu_2_app_addr = 747, + .uartsh_2_mcu_addr = 1183, + .per_2_shp_addr = 1033, + .mcu_2_shp_addr = 961, + .ata_2_mcu_addr = 1333, + .mcu_2_ata_addr = 1252, + .app_2_mcu_addr = 683, + .shp_2_per_addr = 1111, + .shp_2_mcu_addr = 892, +}; + +static struct sdma_script_start_addrs addr_imx35_to2 = { + .ap_2_ap_addr = 729, + .uart_2_mcu_addr = 904, + .per_2_app_addr = 1597, + .mcu_2_app_addr = 834, + .uartsh_2_mcu_addr = 1270, + .per_2_shp_addr = 1120, + .mcu_2_shp_addr = 1048, + .ata_2_mcu_addr = 1429, + .mcu_2_ata_addr = 1339, + .app_2_per_addr = 1531, + .app_2_mcu_addr = 770, + .shp_2_per_addr = 1198, + .shp_2_mcu_addr = 979, +}; +#endif + +#ifdef CONFIG_ARCH_MX51 +static struct sdma_script_start_addrs addr_imx51_to1 = { + .ap_2_ap_addr = 642, + .uart_2_mcu_addr = 817, + .mcu_2_app_addr = 747, + .mcu_2_shp_addr = 961, + .ata_2_mcu_addr = 1473, + .mcu_2_ata_addr = 1392, + .app_2_per_addr = 1033, + .app_2_mcu_addr = 683, + .shp_2_per_addr = 1251, + .shp_2_mcu_addr = 892, +}; +#endif + static int __init imxXX_add_imx_dma(void) { struct platform_device *ret; @@ -95,29 +172,41 @@ static int __init imxXX_add_imx_dma(void) #endif #if defined(CONFIG_SOC_IMX25) - if (cpu_is_mx25()) + if (cpu_is_mx25()) { + imx25_imx_sdma_data.pdata.script_addrs = &addr_imx25_to1; ret = imx_add_imx_sdma(&imx25_imx_sdma_data); - else + } else #endif #if defined(CONFIG_SOC_IMX31) if (cpu_is_mx31()) { - imx31_imx_sdma_data.pdata.to_version = mx31_revision() >> 4; + int to_version = mx31_revision() >> 4; + imx31_imx_sdma_data.pdata.to_version = to_version; + if (to_version == 1) + imx31_imx_sdma_data.pdata.script_addrs = &addr_imx31_to1; + else + imx31_imx_sdma_data.pdata.script_addrs = &addr_imx31_to2; ret = imx_add_imx_sdma(&imx31_imx_sdma_data); } else #endif #if defined(CONFIG_SOC_IMX35) if (cpu_is_mx35()) { - imx35_imx_sdma_data.pdata.to_version = mx35_revision() >> 4; + int to_version = mx35_revision() >> 4; + imx35_imx_sdma_data.pdata.to_version = to_version; + if (to_version == 1) + imx35_imx_sdma_data.pdata.script_addrs = &addr_imx35_to1; + else + imx35_imx_sdma_data.pdata.script_addrs = &addr_imx35_to2; ret = imx_add_imx_sdma(&imx35_imx_sdma_data); } else #endif #if defined(CONFIG_ARCH_MX51) - if (cpu_is_mx51()) + if (cpu_is_mx51()) { + imx51_imx_sdma_data.pdata.script_addrs = &addr_imx51_to1; ret = imx_add_imx_sdma(&imx51_imx_sdma_data); - else + } else #endif ret = ERR_PTR(-ENODEV); -- cgit v1.1 From 29bb6afcb077bd153c7738e73840dde808132fb5 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Eric=20B=C3=A9nard?= Date: Sat, 27 Nov 2010 09:15:38 +0100 Subject: plat-mxc/ehci.c: fix compile breakage MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit commits 2eb42d5c287f5e883a4b3ebe668ba880caa351e5 and 9e1dde33876ba83ad586c336647fff133d0f5472 renamed some defines but didn't fix all the places where these defines are used leading to a compile failure for USB on i.MX31, 35 and 27. Signed-off-by: Eric Bénard Signed-off-by: Sascha Hauer --- arch/arm/plat-mxc/ehci.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) (limited to 'arch/arm/plat-mxc') diff --git a/arch/arm/plat-mxc/ehci.c b/arch/arm/plat-mxc/ehci.c index 4bac3d5..b79c809 100644 --- a/arch/arm/plat-mxc/ehci.c +++ b/arch/arm/plat-mxc/ehci.c @@ -115,7 +115,7 @@ int mxc_initialize_usb_hw(int port, unsigned int flags) #endif /* if defined(CONFIG_SOC_IMX25) */ #if defined(CONFIG_ARCH_MX3) if (cpu_is_mx31()) { - v = readl(MX31_IO_ADDRESS(MX31_OTG_BASE_ADDR + + v = readl(MX31_IO_ADDRESS(MX31_USB_BASE_ADDR + USBCTRL_OTGBASE_OFFSET)); switch (port) { @@ -153,13 +153,13 @@ int mxc_initialize_usb_hw(int port, unsigned int flags) return -EINVAL; } - writel(v, MX31_IO_ADDRESS(MX31_OTG_BASE_ADDR + + writel(v, MX31_IO_ADDRESS(MX31_USB_BASE_ADDR + USBCTRL_OTGBASE_OFFSET)); return 0; } if (cpu_is_mx35()) { - v = readl(MX35_IO_ADDRESS(MX35_OTG_BASE_ADDR + + v = readl(MX35_IO_ADDRESS(MX35_USB_BASE_ADDR + USBCTRL_OTGBASE_OFFSET)); switch (port) { @@ -196,7 +196,7 @@ int mxc_initialize_usb_hw(int port, unsigned int flags) return -EINVAL; } - writel(v, MX35_IO_ADDRESS(MX35_OTG_BASE_ADDR + + writel(v, MX35_IO_ADDRESS(MX35_USB_BASE_ADDR + USBCTRL_OTGBASE_OFFSET)); return 0; } @@ -206,7 +206,7 @@ int mxc_initialize_usb_hw(int port, unsigned int flags) /* On i.MX27 we can use the i.MX31 USBCTRL bits, they * are identical */ - v = readl(MX27_IO_ADDRESS(MX27_OTG_BASE_ADDR + + v = readl(MX27_IO_ADDRESS(MX27_USB_BASE_ADDR + USBCTRL_OTGBASE_OFFSET)); switch (port) { case 0: /* OTG port */ @@ -241,7 +241,7 @@ int mxc_initialize_usb_hw(int port, unsigned int flags) default: return -EINVAL; } - writel(v, MX27_IO_ADDRESS(MX27_OTG_BASE_ADDR + + writel(v, MX27_IO_ADDRESS(MX27_USB_BASE_ADDR + USBCTRL_OTGBASE_OFFSET)); return 0; } -- cgit v1.1 From 4c6c32b3f856346158161a8c9824b4dd2bff0893 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Mon, 29 Nov 2010 08:58:14 +0100 Subject: ARM: mx25: fix offset for usb host controller MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit In commit 2c20b9f (ARM: mx25: dynamically allocate mxc-ehci devices) I changed the offset to the value specified in the reference manual intending to test this change on hardware. This slipped through and now prooved to be wrong. So fix it and add a comment about the documentation being wrong. Reported-by: Jaume Ribot Cc: Michael Trimarchi Cc: Shawn Guo Signed-off-by: Uwe Kleine-König Signed-off-by: Sascha Hauer --- arch/arm/plat-mxc/include/mach/mx25.h | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) (limited to 'arch/arm/plat-mxc') diff --git a/arch/arm/plat-mxc/include/mach/mx25.h b/arch/arm/plat-mxc/include/mach/mx25.h index 024bebe..087cd7a 100644 --- a/arch/arm/plat-mxc/include/mach/mx25.h +++ b/arch/arm/plat-mxc/include/mach/mx25.h @@ -49,7 +49,12 @@ #define MX25_SDMA_BASE_ADDR 0x53fd4000 #define MX25_USB_BASE_ADDR 0x53ff4000 #define MX25_USB_OTG_BASE_ADDR (MX25_USB_BASE_ADDR + 0x0000) -#define MX25_USB_HS_BASE_ADDR (MX25_USB_BASE_ADDR + 0x0200) +/* + * The reference manual (IMX25RM, Rev. 1, 06/2009) specifies an offset of 0x200 + * for the host controller. Early documentation drafts specified 0x400 and + * Freescale internal sources confirm only the latter value to work. + */ +#define MX25_USB_HS_BASE_ADDR (MX25_USB_BASE_ADDR + 0x0400) #define MX25_CSI_BASE_ADDR 0x53ff8000 #define MX25_IO_P2V(x) IMX_IO_P2V(x) -- cgit v1.1 From d94ed1287e11f91e4f4096838179984b0206be5e Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Fri, 26 Nov 2010 12:25:58 -0200 Subject: ARM: mx5: introduce SOC_IMX51 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Introduce SOC_IMX51 to keep consistency with the other i.MX devices Signed-off-by: Fabio Estevam Acked-by: Uwe Kleine-König Signed-off-by: Sascha Hauer --- arch/arm/plat-mxc/devices/Kconfig | 4 ++-- arch/arm/plat-mxc/devices/platform-fec.c | 2 +- arch/arm/plat-mxc/devices/platform-imx-dma.c | 6 +++--- arch/arm/plat-mxc/devices/platform-imx-i2c.c | 4 ++-- arch/arm/plat-mxc/devices/platform-imx-ssi.c | 4 ++-- arch/arm/plat-mxc/devices/platform-imx-uart.c | 4 ++-- arch/arm/plat-mxc/devices/platform-mxc_nand.c | 2 +- arch/arm/plat-mxc/devices/platform-sdhci-esdhc-imx.c | 4 ++-- arch/arm/plat-mxc/devices/platform-spi_imx.c | 4 ++-- arch/arm/plat-mxc/ehci.c | 2 +- 10 files changed, 18 insertions(+), 18 deletions(-) (limited to 'arch/arm/plat-mxc') diff --git a/arch/arm/plat-mxc/devices/Kconfig b/arch/arm/plat-mxc/devices/Kconfig index b391f4d..2537166 100644 --- a/arch/arm/plat-mxc/devices/Kconfig +++ b/arch/arm/plat-mxc/devices/Kconfig @@ -1,6 +1,6 @@ config IMX_HAVE_PLATFORM_FEC bool - default y if ARCH_MX25 || SOC_IMX27 || SOC_IMX35 || ARCH_MX51 + default y if ARCH_MX25 || SOC_IMX27 || SOC_IMX35 || SOC_IMX51 config IMX_HAVE_PLATFORM_FLEXCAN select HAVE_CAN_FLEXCAN if CAN @@ -11,7 +11,7 @@ config IMX_HAVE_PLATFORM_FSL_USB2_UDC config IMX_HAVE_PLATFORM_GPIO_KEYS bool - default y if ARCH_MX51 + default y if SOC_IMX51 config IMX_HAVE_PLATFORM_IMX21_HCD bool diff --git a/arch/arm/plat-mxc/devices/platform-fec.c b/arch/arm/plat-mxc/devices/platform-fec.c index 8d78aed..269ec78 100644 --- a/arch/arm/plat-mxc/devices/platform-fec.c +++ b/arch/arm/plat-mxc/devices/platform-fec.c @@ -31,7 +31,7 @@ const struct imx_fec_data imx35_fec_data __initconst = imx_fec_data_entry_single(MX35); #endif -#ifdef CONFIG_ARCH_MX51 +#ifdef CONFIG_SOC_IMX51 const struct imx_fec_data imx51_fec_data __initconst = imx_fec_data_entry_single(MX51); #endif diff --git a/arch/arm/plat-mxc/devices/platform-imx-dma.c b/arch/arm/plat-mxc/devices/platform-imx-dma.c index 93e2fdc..96b7c2b 100644 --- a/arch/arm/plat-mxc/devices/platform-imx-dma.c +++ b/arch/arm/plat-mxc/devices/platform-imx-dma.c @@ -54,10 +54,10 @@ struct imx_imx_sdma_data imx35_imx_sdma_data __initdata = imx_imx_sdma_data_entry_single(MX35, 2, "imx35", 0); #endif /* ifdef CONFIG_SOC_IMX35 */ -#ifdef CONFIG_ARCH_MX51 +#ifdef CONFIG_SOC_IMX51 struct imx_imx_sdma_data imx51_imx_sdma_data __initconst = imx_imx_sdma_data_entry_single(MX51, 2, "imx51", 0); -#endif /* ifdef CONFIG_ARCH_MX51 */ +#endif /* ifdef CONFIG_SOC_IMX51 */ static struct platform_device __init __maybe_unused *imx_add_imx_sdma( const struct imx_imx_sdma_data *data) @@ -146,7 +146,7 @@ static struct sdma_script_start_addrs addr_imx35_to2 = { }; #endif -#ifdef CONFIG_ARCH_MX51 +#ifdef CONFIG_SOC_IMX51 static struct sdma_script_start_addrs addr_imx51_to1 = { .ap_2_ap_addr = 642, .uart_2_mcu_addr = 817, diff --git a/arch/arm/plat-mxc/devices/platform-imx-i2c.c b/arch/arm/plat-mxc/devices/platform-imx-i2c.c index 075bd8e..72ba880 100644 --- a/arch/arm/plat-mxc/devices/platform-imx-i2c.c +++ b/arch/arm/plat-mxc/devices/platform-imx-i2c.c @@ -69,14 +69,14 @@ const struct imx_imx_i2c_data imx35_imx_i2c_data[] __initconst = { }; #endif /* ifdef CONFIG_SOC_IMX35 */ -#ifdef CONFIG_ARCH_MX51 +#ifdef CONFIG_SOC_IMX51 const struct imx_imx_i2c_data imx51_imx_i2c_data[] __initconst = { #define imx51_imx_i2c_data_entry(_id, _hwid) \ imx_imx_i2c_data_entry(MX51, _id, _hwid, SZ_4K) imx51_imx_i2c_data_entry(0, 1), imx51_imx_i2c_data_entry(1, 2), }; -#endif /* ifdef CONFIG_ARCH_MX51 */ +#endif /* ifdef CONFIG_SOC_IMX51 */ struct platform_device *__init imx_add_imx_i2c( const struct imx_imx_i2c_data *data, diff --git a/arch/arm/plat-mxc/devices/platform-imx-ssi.c b/arch/arm/plat-mxc/devices/platform-imx-ssi.c index 02002fc..ac3d572 100644 --- a/arch/arm/plat-mxc/devices/platform-imx-ssi.c +++ b/arch/arm/plat-mxc/devices/platform-imx-ssi.c @@ -66,14 +66,14 @@ const struct imx_imx_ssi_data imx35_imx_ssi_data[] __initconst = { }; #endif /* ifdef CONFIG_SOC_IMX35 */ -#ifdef CONFIG_ARCH_MX51 +#ifdef CONFIG_SOC_IMX51 const struct imx_imx_ssi_data imx51_imx_ssi_data[] __initconst = { #define imx51_imx_ssi_data_entry(_id, _hwid) \ imx_imx_ssi_data_entry(MX51, _id, _hwid, SZ_4K) imx51_imx_ssi_data_entry(0, 1), imx51_imx_ssi_data_entry(1, 2), }; -#endif /* ifdef CONFIG_ARCH_MX51 */ +#endif /* ifdef CONFIG_SOC_IMX51 */ struct platform_device *__init imx_add_imx_ssi( const struct imx_imx_ssi_data *data, diff --git a/arch/arm/plat-mxc/devices/platform-imx-uart.c b/arch/arm/plat-mxc/devices/platform-imx-uart.c index 08bbd65..7b45b78 100644 --- a/arch/arm/plat-mxc/devices/platform-imx-uart.c +++ b/arch/arm/plat-mxc/devices/platform-imx-uart.c @@ -94,7 +94,7 @@ const struct imx_imx_uart_1irq_data imx35_imx_uart_data[] __initconst = { }; #endif /* ifdef CONFIG_SOC_IMX35 */ -#ifdef CONFIG_ARCH_MX51 +#ifdef CONFIG_SOC_IMX51 const struct imx_imx_uart_1irq_data imx51_imx_uart_data[] __initconst = { #define imx51_imx_uart_data_entry(_id, _hwid) \ imx_imx_uart_1irq_data_entry(MX51, _id, _hwid, SZ_4K) @@ -102,7 +102,7 @@ const struct imx_imx_uart_1irq_data imx51_imx_uart_data[] __initconst = { imx51_imx_uart_data_entry(1, 2), imx51_imx_uart_data_entry(2, 3), }; -#endif /* ifdef CONFIG_ARCH_MX51 */ +#endif /* ifdef CONFIG_SOC_IMX51 */ struct platform_device *__init imx_add_imx_uart_3irq( const struct imx_imx_uart_3irq_data *data, diff --git a/arch/arm/plat-mxc/devices/platform-mxc_nand.c b/arch/arm/plat-mxc/devices/platform-mxc_nand.c index f5beac0..1568f39 100644 --- a/arch/arm/plat-mxc/devices/platform-mxc_nand.c +++ b/arch/arm/plat-mxc/devices/platform-mxc_nand.c @@ -51,7 +51,7 @@ const struct imx_mxc_nand_data imx35_mxc_nand_data __initconst = imx_mxc_nand_data_entry_single(MX35, SZ_8K); #endif -#ifdef CONFIG_ARCH_MX51 +#ifdef CONFIG_SOC_IMX51 const struct imx_mxc_nand_data imx51_mxc_nand_data __initconst = imx_mxc_nandv3_data_entry_single(MX51, SZ_16K); #endif diff --git a/arch/arm/plat-mxc/devices/platform-sdhci-esdhc-imx.c b/arch/arm/plat-mxc/devices/platform-sdhci-esdhc-imx.c index 167cce8..b352564 100644 --- a/arch/arm/plat-mxc/devices/platform-sdhci-esdhc-imx.c +++ b/arch/arm/plat-mxc/devices/platform-sdhci-esdhc-imx.c @@ -41,7 +41,7 @@ imx35_sdhci_esdhc_imx_data[] __initconst = { }; #endif /* ifdef CONFIG_SOC_IMX35 */ -#ifdef CONFIG_ARCH_MX51 +#ifdef CONFIG_SOC_IMX51 const struct imx_sdhci_esdhc_imx_data imx51_sdhci_esdhc_imx_data[] __initconst = { #define imx51_sdhci_esdhc_imx_data_entry(_id, _hwid) \ @@ -51,7 +51,7 @@ imx51_sdhci_esdhc_imx_data[] __initconst = { imx51_sdhci_esdhc_imx_data_entry(2, 3), imx51_sdhci_esdhc_imx_data_entry(3, 4), }; -#endif /* ifdef CONFIG_ARCH_MX51 */ +#endif /* ifdef CONFIG_SOC_IMX51 */ struct platform_device *__init imx_add_sdhci_esdhc_imx( const struct imx_sdhci_esdhc_imx_data *data, diff --git a/arch/arm/plat-mxc/devices/platform-spi_imx.c b/arch/arm/plat-mxc/devices/platform-spi_imx.c index 8f2b60a..e1ffa1f 100644 --- a/arch/arm/plat-mxc/devices/platform-spi_imx.c +++ b/arch/arm/plat-mxc/devices/platform-spi_imx.c @@ -68,7 +68,7 @@ const struct imx_spi_imx_data imx35_cspi_data[] __initconst = { }; #endif /* ifdef CONFIG_SOC_IMX35 */ -#ifdef CONFIG_ARCH_MX51 +#ifdef CONFIG_SOC_IMX51 const struct imx_spi_imx_data imx51_cspi_data __initconst = imx_spi_imx_data_entry_single(MX51, CSPI, "imx51-cspi", 0, , SZ_4K); @@ -78,7 +78,7 @@ const struct imx_spi_imx_data imx51_ecspi_data[] __initconst = { imx51_ecspi_data_entry(0, 1), imx51_ecspi_data_entry(1, 2), }; -#endif /* ifdef CONFIG_ARCH_MX51 */ +#endif /* ifdef CONFIG_SOC_IMX51 */ struct platform_device *__init imx_add_spi_imx( const struct imx_spi_imx_data *data, diff --git a/arch/arm/plat-mxc/ehci.c b/arch/arm/plat-mxc/ehci.c index b79c809..c1a7146 100644 --- a/arch/arm/plat-mxc/ehci.c +++ b/arch/arm/plat-mxc/ehci.c @@ -246,7 +246,7 @@ int mxc_initialize_usb_hw(int port, unsigned int flags) return 0; } #endif /* CONFIG_MACH_MX27 */ -#ifdef CONFIG_ARCH_MX51 +#ifdef CONFIG_SOC_IMX51 if (cpu_is_mx51()) { void __iomem *usb_base; void __iomem *usbotg_base; -- cgit v1.1 From b99545cb59dc0a55507100a1335f4fd0ed521032 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Fri, 26 Nov 2010 12:25:59 -0200 Subject: ARM: mx5: dynamically allocate imx2-wdt devices Signed-off-by: Fabio Estevam Signed-off-by: Sascha Hauer --- arch/arm/plat-mxc/devices/platform-imx2-wdt.c | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch/arm/plat-mxc') diff --git a/arch/arm/plat-mxc/devices/platform-imx2-wdt.c b/arch/arm/plat-mxc/devices/platform-imx2-wdt.c index c61bd4e..8dc19f6 100644 --- a/arch/arm/plat-mxc/devices/platform-imx2-wdt.c +++ b/arch/arm/plat-mxc/devices/platform-imx2-wdt.c @@ -41,6 +41,11 @@ const struct imx_imx2_wdt_data imx35_imx2_wdt_data __initconst = imx_imx2_wdt_data_entry_single(MX35, SZ_16K); #endif /* ifdef CONFIG_SOC_IMX35 */ +#ifdef CONFIG_SOC_IMX51 +const struct imx_imx2_wdt_data imx51_imx2_wdt_data __initconst = + imx_imx2_wdt_data_entry_single(MX51, SZ_16K); +#endif /* ifdef CONFIG_SOC_IMX51 */ + struct platform_device *__init imx_add_imx2_wdt( const struct imx_imx2_wdt_data *data) { -- cgit v1.1 From 96886c4361f1ae3f6c775d7c9295e2d557101d0f Mon Sep 17 00:00:00 2001 From: "Arnaud Patard (Rtp)" Date: Fri, 26 Nov 2010 15:20:52 +0100 Subject: iMX51: introduce IMX_GPIO_NR MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Currently, to define a GPIO number, we're using something like : #define EFIKAMX_PCBID0 (2*32 + 16) to define GPIO 3 16. This is not really readable and it's error prone imho (note the 3 vs 2). So, I'm introducing a new macro to define this in a better way. Now, the code sample become : #define EFIKAMX_PCBID0 IMX_GPIO_NR(3, 16) v2: - move to gpio.h - add parens & spaces - switch to IMX_GPIO_NR instead of MX51_GPIO_NR Signed-off-by: Arnaud Patard Cc: Amit Kucheria Cc: Sascha Hauer Cc: Eric Bénard Signed-off-by: Sascha Hauer --- arch/arm/plat-mxc/include/mach/gpio.h | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch/arm/plat-mxc') diff --git a/arch/arm/plat-mxc/include/mach/gpio.h b/arch/arm/plat-mxc/include/mach/gpio.h index af33b74..0044e2f 100644 --- a/arch/arm/plat-mxc/include/mach/gpio.h +++ b/arch/arm/plat-mxc/include/mach/gpio.h @@ -23,6 +23,11 @@ #include #include + +/* There's a off-by-one betweem the gpio bank number and the gpiochip */ +/* range e.g. GPIO_1_5 is gpio 5 under linux */ +#define IMX_GPIO_NR(bank, nr) (((bank) - 1) * 32 + (nr)) + /* use gpiolib dispatchers */ #define gpio_get_value __gpio_get_value #define gpio_set_value __gpio_set_value -- cgit v1.1 From 8c2efec3cd5fcc6240da8931222ccab556a40ff3 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Mon, 6 Dec 2010 16:38:32 -0200 Subject: ARM: mx5: add support for the two watchdog modules MX51 has two watchdog modules. Add support for both of them. Signed-off-by: Fabio Estevam Signed-off-by: Sascha Hauer --- arch/arm/plat-mxc/devices/platform-imx2-wdt.c | 27 ++++++++++++++++--------- arch/arm/plat-mxc/include/mach/devices-common.h | 1 + arch/arm/plat-mxc/include/mach/mx51.h | 2 +- 3 files changed, 19 insertions(+), 11 deletions(-) (limited to 'arch/arm/plat-mxc') diff --git a/arch/arm/plat-mxc/devices/platform-imx2-wdt.c b/arch/arm/plat-mxc/devices/platform-imx2-wdt.c index 8dc19f6..e0aec61 100644 --- a/arch/arm/plat-mxc/devices/platform-imx2-wdt.c +++ b/arch/arm/plat-mxc/devices/platform-imx2-wdt.c @@ -10,40 +10,47 @@ #include #include -#define imx_imx2_wdt_data_entry_single(soc, _size) \ +#define imx_imx2_wdt_data_entry_single(soc, _id, _hwid, _size) \ { \ - .iobase = soc ## _WDOG_BASE_ADDR, \ + .id = _id, \ + .iobase = soc ## _WDOG ## _hwid ## _BASE_ADDR, \ .iosize = _size, \ } +#define imx_imx2_wdt_data_entry(soc, _id, _hwid, _size) \ + [_id] = imx_imx2_wdt_data_entry_single(soc, _id, _hwid, _size) #ifdef CONFIG_SOC_IMX21 const struct imx_imx2_wdt_data imx21_imx2_wdt_data __initconst = - imx_imx2_wdt_data_entry_single(MX21, SZ_4K); + imx_imx2_wdt_data_entry_single(MX21, 0, , SZ_4K); #endif /* ifdef CONFIG_SOC_IMX21 */ #ifdef CONFIG_SOC_IMX25 const struct imx_imx2_wdt_data imx25_imx2_wdt_data __initconst = - imx_imx2_wdt_data_entry_single(MX25, SZ_16K); + imx_imx2_wdt_data_entry_single(MX25, 0, , SZ_16K); #endif /* ifdef CONFIG_SOC_IMX25 */ #ifdef CONFIG_SOC_IMX27 const struct imx_imx2_wdt_data imx27_imx2_wdt_data __initconst = - imx_imx2_wdt_data_entry_single(MX27, SZ_4K); + imx_imx2_wdt_data_entry_single(MX27, 0, , SZ_4K); #endif /* ifdef CONFIG_SOC_IMX27 */ #ifdef CONFIG_SOC_IMX31 const struct imx_imx2_wdt_data imx31_imx2_wdt_data __initconst = - imx_imx2_wdt_data_entry_single(MX31, SZ_16K); + imx_imx2_wdt_data_entry_single(MX31, 0, , SZ_16K); #endif /* ifdef CONFIG_SOC_IMX31 */ #ifdef CONFIG_SOC_IMX35 const struct imx_imx2_wdt_data imx35_imx2_wdt_data __initconst = - imx_imx2_wdt_data_entry_single(MX35, SZ_16K); + imx_imx2_wdt_data_entry_single(MX35, 0, , SZ_16K); #endif /* ifdef CONFIG_SOC_IMX35 */ #ifdef CONFIG_SOC_IMX51 -const struct imx_imx2_wdt_data imx51_imx2_wdt_data __initconst = - imx_imx2_wdt_data_entry_single(MX51, SZ_16K); +const struct imx_imx2_wdt_data imx51_imx2_wdt_data[] __initconst = { +#define imx51_imx2_wdt_data_entry(_id, _hwid) \ + imx_imx2_wdt_data_entry(MX51, _id, _hwid, SZ_16K) + imx51_imx2_wdt_data_entry(0, 1), + imx51_imx2_wdt_data_entry(1, 2), +}; #endif /* ifdef CONFIG_SOC_IMX51 */ struct platform_device *__init imx_add_imx2_wdt( @@ -56,6 +63,6 @@ struct platform_device *__init imx_add_imx2_wdt( .flags = IORESOURCE_MEM, }, }; - return imx_add_platform_device("imx2-wdt", 0, + return imx_add_platform_device("imx2-wdt", data->id, res, ARRAY_SIZE(res), NULL, 0); } diff --git a/arch/arm/plat-mxc/include/mach/devices-common.h b/arch/arm/plat-mxc/include/mach/devices-common.h index 3640eaf..8658c9c 100644 --- a/arch/arm/plat-mxc/include/mach/devices-common.h +++ b/arch/arm/plat-mxc/include/mach/devices-common.h @@ -67,6 +67,7 @@ struct platform_device *__init imx_add_imx21_hcd( const struct mx21_usbh_platform_data *pdata); struct imx_imx2_wdt_data { + int id; resource_size_t iobase; resource_size_t iosize; }; diff --git a/arch/arm/plat-mxc/include/mach/mx51.h b/arch/arm/plat-mxc/include/mach/mx51.h index 8fddfef..882f1f4 100644 --- a/arch/arm/plat-mxc/include/mach/mx51.h +++ b/arch/arm/plat-mxc/include/mach/mx51.h @@ -61,7 +61,7 @@ #define MX51_GPIO3_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x8c000) #define MX51_GPIO4_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x90000) #define MX51_KPP_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x94000) -#define MX51_WDOG_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x98000) +#define MX51_WDOG1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x98000) #define MX51_WDOG2_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x9c000) #define MX51_GPT1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xa0000) #define MX51_SRTC_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xa4000) -- cgit v1.1 From 2c1f4672f0711e7f23ae49cbb7541088126fe576 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Tue, 7 Dec 2010 14:16:04 -0200 Subject: watchdog: imx: use clk_get to acquire the watchdog clock Use clk_get to acquire the watchdog clock and also avoid hardcoding the clock name. Signed-off-by: Fabio Estevam Signed-off-by: Sascha Hauer --- arch/arm/plat-mxc/system.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm/plat-mxc') diff --git a/arch/arm/plat-mxc/system.c b/arch/arm/plat-mxc/system.c index c3972c5..3455fc0 100644 --- a/arch/arm/plat-mxc/system.c +++ b/arch/arm/plat-mxc/system.c @@ -55,7 +55,7 @@ void arch_reset(char mode, const char *cmd) } else { struct clk *clk; - clk = clk_get_sys("imx-wdt.0", NULL); + clk = clk_get_sys("imx2-wdt.0", NULL); if (!IS_ERR(clk)) clk_enable(clk); wcr_enable = (1 << 2); -- cgit v1.1 From f25972233fbe4b60dc4b514def4caf40aa1bb85a Mon Sep 17 00:00:00 2001 From: Peter Horton Date: Fri, 3 Dec 2010 17:07:28 +0000 Subject: mx51: add SSI3 Add SSI3 to MX51 Signed-off-by: Peter Horton Signed-off-by: Sascha Hauer --- arch/arm/plat-mxc/devices/platform-imx-ssi.c | 1 + arch/arm/plat-mxc/include/mach/mx51.h | 12 ++++++------ 2 files changed, 7 insertions(+), 6 deletions(-) (limited to 'arch/arm/plat-mxc') diff --git a/arch/arm/plat-mxc/devices/platform-imx-ssi.c b/arch/arm/plat-mxc/devices/platform-imx-ssi.c index ac3d572..2569c8d 100644 --- a/arch/arm/plat-mxc/devices/platform-imx-ssi.c +++ b/arch/arm/plat-mxc/devices/platform-imx-ssi.c @@ -72,6 +72,7 @@ const struct imx_imx_ssi_data imx51_imx_ssi_data[] __initconst = { imx_imx_ssi_data_entry(MX51, _id, _hwid, SZ_4K) imx51_imx_ssi_data_entry(0, 1), imx51_imx_ssi_data_entry(1, 2), + imx51_imx_ssi_data_entry(2, 3), }; #endif /* ifdef CONFIG_SOC_IMX51 */ diff --git a/arch/arm/plat-mxc/include/mach/mx51.h b/arch/arm/plat-mxc/include/mach/mx51.h index 882f1f4..fa3a2a5 100644 --- a/arch/arm/plat-mxc/include/mach/mx51.h +++ b/arch/arm/plat-mxc/include/mach/mx51.h @@ -109,7 +109,7 @@ #define MX51_MIPI_HSC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xdc000) #define MX51_ATA_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xe0000) #define MX51_SIM_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xe4000) -#define MX51_SSI3BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xe8000) +#define MX51_SSI3_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xe8000) #define MX51_FEC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xec000) #define MX51_TVE_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xf0000) #define MX51_VPU_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xf4000) @@ -223,9 +223,9 @@ #define MX51_DMA_REQ_EMI_WR 32 #define MX51_DMA_REQ_CTI2_1 33 #define MX51_DMA_REQ_EPIT2 34 -#define MX51_DMA_REQ_SSI3_RX2 35 +#define MX51_DMA_REQ_SSI3_RX1 35 #define MX51_DMA_REQ_IPU 36 -#define MX51_DMA_REQ_SSI3_TX2 37 +#define MX51_DMA_REQ_SSI3_TX1 37 #define MX51_DMA_REQ_CSPI_RX 38 #define MX51_DMA_REQ_CSPI_TX 39 #define MX51_DMA_REQ_SDHC3 40 @@ -234,8 +234,8 @@ #define MX51_DMA_REQ_UART3_RX 43 #define MX51_DMA_REQ_UART3_TX 44 #define MX51_DMA_REQ_SPDIF 45 -#define MX51_DMA_REQ_SSI3_RX1 46 -#define MX51_DMA_REQ_SSI3_TX1 47 +#define MX51_DMA_REQ_SSI3_RX0 46 +#define MX51_DMA_REQ_SSI3_TX0 47 /* * Interrupt numbers @@ -337,7 +337,7 @@ #define MX51_MXC_INT_FIRI 93 #define MX51_MXC_INT_PWM2 94 #define MX51_MXC_INT_SLIM_EXP 95 -#define MX51_MXC_INT_SSI3 96 +#define MX51_INT_SSI3 96 #define MX51_MXC_INT_EMI_BOOT 97 #define MX51_MXC_INT_CTI1_TG3 98 #define MX51_MXC_INT_SMC_RX 99 -- cgit v1.1 From cdc3f10630ecddb7870e087ff9679eef3d7b4e21 Mon Sep 17 00:00:00 2001 From: Peter Horton Date: Mon, 6 Dec 2010 11:37:38 +0000 Subject: mx51: support FIQ on TZIC, revised Add support for FIQ on mx51 TZIC TZIC changes tested with FIQ audio on an mx51 board AVIC changes build with mx3_defconfig, not tested Signed-off-by: Peter Horton Signed-off-by: Sascha Hauer --- arch/arm/plat-mxc/Makefile | 2 +- arch/arm/plat-mxc/avic.c | 32 +++++++++------ arch/arm/plat-mxc/include/mach/entry-macro.S | 14 +++---- arch/arm/plat-mxc/irq-common.c | 60 ++++++++++++++++++++++++++++ arch/arm/plat-mxc/irq-common.h | 29 ++++++++++++++ arch/arm/plat-mxc/tzic.c | 46 +++++++++++++++++---- 6 files changed, 155 insertions(+), 28 deletions(-) create mode 100644 arch/arm/plat-mxc/irq-common.c create mode 100644 arch/arm/plat-mxc/irq-common.h (limited to 'arch/arm/plat-mxc') diff --git a/arch/arm/plat-mxc/Makefile b/arch/arm/plat-mxc/Makefile index 989cb59..5fd20e9 100644 --- a/arch/arm/plat-mxc/Makefile +++ b/arch/arm/plat-mxc/Makefile @@ -3,7 +3,7 @@ # # Common support -obj-y := clock.o gpio.o time.o devices.o cpu.o system.o +obj-y := clock.o gpio.o time.o devices.o cpu.o system.o irq-common.o # MX51 uses the TZIC interrupt controller, older platforms use AVIC obj-$(CONFIG_MXC_TZIC) += tzic.o diff --git a/arch/arm/plat-mxc/avic.c b/arch/arm/plat-mxc/avic.c index 7331f2a..9a4e8a2 100644 --- a/arch/arm/plat-mxc/avic.c +++ b/arch/arm/plat-mxc/avic.c @@ -24,6 +24,8 @@ #include #include +#include "irq-common.h" + #define AVIC_INTCNTL 0x00 /* int control reg */ #define AVIC_NIMASK 0x04 /* int mask reg */ #define AVIC_INTENNUM 0x08 /* int enable number reg */ @@ -46,9 +48,9 @@ void __iomem *avic_base; -int imx_irq_set_priority(unsigned char irq, unsigned char prio) -{ #ifdef CONFIG_MXC_IRQ_PRIOR +static int avic_irq_set_priority(unsigned char irq, unsigned char prio) +{ unsigned int temp; unsigned int mask = 0x0F << irq % 8 * 4; @@ -62,14 +64,11 @@ int imx_irq_set_priority(unsigned char irq, unsigned char prio) __raw_writel(temp, avic_base + AVIC_NIPRIORITY(irq / 8)); return 0; -#else - return -ENOSYS; -#endif } -EXPORT_SYMBOL(imx_irq_set_priority); +#endif #ifdef CONFIG_FIQ -int mxc_set_irq_fiq(unsigned int irq, unsigned int type) +static int avic_set_irq_fiq(unsigned int irq, unsigned int type) { unsigned int irqt; @@ -87,7 +86,6 @@ int mxc_set_irq_fiq(unsigned int irq, unsigned int type) return 0; } -EXPORT_SYMBOL(mxc_set_irq_fiq); #endif /* CONFIG_FIQ */ /* Disable interrupt number "irq" in the AVIC */ @@ -102,10 +100,18 @@ static void mxc_unmask_irq(unsigned int irq) __raw_writel(irq, avic_base + AVIC_INTENNUM); } -static struct irq_chip mxc_avic_chip = { - .ack = mxc_mask_irq, - .mask = mxc_mask_irq, - .unmask = mxc_unmask_irq, +static struct mxc_irq_chip mxc_avic_chip = { + .base = { + .ack = mxc_mask_irq, + .mask = mxc_mask_irq, + .unmask = mxc_unmask_irq, + }, +#ifdef CONFIG_MXC_IRQ_PRIOR + .set_priority = avic_irq_set_priority, +#endif +#ifdef CONFIG_FIQ + .set_irq_fiq = avic_set_irq_fiq, +#endif }; /* @@ -133,7 +139,7 @@ void __init mxc_init_irq(void __iomem *irqbase) __raw_writel(0, avic_base + AVIC_INTTYPEH); __raw_writel(0, avic_base + AVIC_INTTYPEL); for (i = 0; i < MXC_INTERNAL_IRQS; i++) { - set_irq_chip(i, &mxc_avic_chip); + set_irq_chip(i, &mxc_avic_chip.base); set_irq_handler(i, handle_level_irq); set_irq_flags(i, IRQF_VALID); } diff --git a/arch/arm/plat-mxc/include/mach/entry-macro.S b/arch/arm/plat-mxc/include/mach/entry-macro.S index aeb0869..bd9bb97 100644 --- a/arch/arm/plat-mxc/include/mach/entry-macro.S +++ b/arch/arm/plat-mxc/include/mach/entry-macro.S @@ -54,15 +54,15 @@ #elif defined CONFIG_MXC_TZIC @ Load offset & priority of the highest priority @ interrupt pending. + @ 0x080 is INTSEC0 register @ 0xD80 is HIPND0 register mov \irqnr, #0 - mov \irqstat, #0x0D80 -1000: - ldr \tmp, [\irqstat, \base] - cmp \tmp, #0 - bne 1001f - addeq \irqnr, \irqnr, #32 - addeq \irqstat, \irqstat, #4 +1000: add \irqstat, \base, \irqnr, lsr #3 + ldr \tmp, [\irqstat, #0xd80] + ldr \irqstat, [\irqstat, #0x080] + ands \tmp, \tmp, \irqstat + bne 1001f + add \irqnr, \irqnr, #32 cmp \irqnr, #128 blo 1000b b 2001f diff --git a/arch/arm/plat-mxc/irq-common.c b/arch/arm/plat-mxc/irq-common.c new file mode 100644 index 0000000..0c799ac --- /dev/null +++ b/arch/arm/plat-mxc/irq-common.c @@ -0,0 +1,60 @@ +/* + * Copyright (C) BitBox Ltd 2010 + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301, USA. + */ + +#include +#include + +#include "irq-common.h" + +int imx_irq_set_priority(unsigned char irq, unsigned char prio) +{ + struct mxc_irq_chip *chip; + struct irq_chip *base; + int ret; + + ret = -ENOSYS; + + base = get_irq_chip(irq); + if (base) { + chip = container_of(base, struct mxc_irq_chip, base); + if (chip->set_priority) + ret = chip->set_priority(irq, prio); + } + + return ret; +} +EXPORT_SYMBOL(imx_irq_set_priority); + +int mxc_set_irq_fiq(unsigned int irq, unsigned int type) +{ + struct mxc_irq_chip *chip; + struct irq_chip *base; + int ret; + + ret = -ENOSYS; + + base = get_irq_chip(irq); + if (base) { + chip = container_of(base, struct mxc_irq_chip, base); + if (chip->set_irq_fiq) + ret = chip->set_irq_fiq(irq, type); + } + + return ret; +} +EXPORT_SYMBOL(mxc_set_irq_fiq); diff --git a/arch/arm/plat-mxc/irq-common.h b/arch/arm/plat-mxc/irq-common.h new file mode 100644 index 0000000..7203543 --- /dev/null +++ b/arch/arm/plat-mxc/irq-common.h @@ -0,0 +1,29 @@ +/* + * Copyright (C) BitBox Ltd 2010 + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301, USA. + */ + +#ifndef __PLAT_MXC_IRQ_COMMON_H__ +#define __PLAT_MXC_IRQ_COMMON_H__ + +struct mxc_irq_chip +{ + struct irq_chip base; + int (*set_priority)(unsigned char irq, unsigned char prio); + int (*set_irq_fiq)(unsigned int irq, unsigned int type); +}; + +#endif diff --git a/arch/arm/plat-mxc/tzic.c b/arch/arm/plat-mxc/tzic.c index 3703ab2..e69ed8a 100644 --- a/arch/arm/plat-mxc/tzic.c +++ b/arch/arm/plat-mxc/tzic.c @@ -21,6 +21,8 @@ #include #include +#include "irq-common.h" + /* ***************************************** * TZIC Registers * @@ -47,6 +49,25 @@ void __iomem *tzic_base; /* Used as irq controller base in entry-macro.S */ +#ifdef CONFIG_FIQ +static int tzic_set_irq_fiq(unsigned int irq, unsigned int type) +{ + unsigned int index, mask, value; + + index = irq >> 5; + if (unlikely(index >= 4)) + return -EINVAL; + mask = 1U << (irq & 0x1F); + + value = __raw_readl(tzic_base + TZIC_INTSEC0(index)) | mask; + if (type) + value &= ~mask; + __raw_writel(value, tzic_base + TZIC_INTSEC0(index)); + + return 0; +} +#endif + /** * tzic_mask_irq() - Disable interrupt number "irq" in the TZIC * @@ -104,12 +125,17 @@ static int tzic_set_wake_irq(unsigned int irq, unsigned int enable) return 0; } -static struct irq_chip mxc_tzic_chip = { - .name = "MXC_TZIC", - .ack = tzic_mask_irq, - .mask = tzic_mask_irq, - .unmask = tzic_unmask_irq, - .set_wake = tzic_set_wake_irq, +static struct mxc_irq_chip mxc_tzic_chip = { + .base = { + .name = "MXC_TZIC", + .ack = tzic_mask_irq, + .mask = tzic_mask_irq, + .unmask = tzic_unmask_irq, + .set_wake = tzic_set_wake_irq, + }, +#ifdef CONFIG_FIQ + .set_irq_fiq = tzic_set_irq_fiq, +#endif }; /* @@ -141,10 +167,16 @@ void __init tzic_init_irq(void __iomem *irqbase) /* all IRQ no FIQ Warning :: No selection */ for (i = 0; i < MXC_INTERNAL_IRQS; i++) { - set_irq_chip(i, &mxc_tzic_chip); + set_irq_chip(i, &mxc_tzic_chip.base); set_irq_handler(i, handle_level_irq); set_irq_flags(i, IRQF_VALID); } + +#ifdef CONFIG_FIQ + /* Initialize FIQ */ + init_FIQ(); +#endif + pr_info("TrustZone Interrupt Controller (TZIC) initialized\n"); } -- cgit v1.1 From bb477de2efc560e55c4a830329273661f3664bc8 Mon Sep 17 00:00:00 2001 From: "Arnaud Patard (Rtp)" Date: Wed, 1 Dec 2010 09:37:17 +0100 Subject: Fix imx cpufreq driver as module When building as module: ERROR: "cpufreq_gov_performance" [arch/arm/plat-mxc/cpufreq.ko] undefined! WARNING: modpost: Found 1 section mismatch(es). To see full details build your kernel with: 'make CONFIG_DEBUG_SECTION_MISMATCH=y' make[1]: *** [__modpost] Error 1 make: *** [modules] Error 2 It's due to the driver using CPUFREQ_DEFAULT_GOVERNOR, even it should not (see commit 8122c6cea033e8034e99d3b10a4e3f377ce23994 in Linus tree), so remove it. Signed-off-by: Arnaud Patard Signed-off-by: Sascha Hauer --- arch/arm/plat-mxc/cpufreq.c | 1 - 1 file changed, 1 deletion(-) (limited to 'arch/arm/plat-mxc') diff --git a/arch/arm/plat-mxc/cpufreq.c b/arch/arm/plat-mxc/cpufreq.c index 039538e..ce81481 100644 --- a/arch/arm/plat-mxc/cpufreq.c +++ b/arch/arm/plat-mxc/cpufreq.c @@ -144,7 +144,6 @@ static int __init mxc_cpufreq_init(struct cpufreq_policy *policy) imx_freq_table[i].frequency = CPUFREQ_TABLE_END; policy->cur = clk_get_rate(cpu_clk) / 1000; - policy->governor = CPUFREQ_DEFAULT_GOVERNOR; policy->min = policy->cpuinfo.min_freq = cpu_freq_khz_min; policy->max = policy->cpuinfo.max_freq = cpu_freq_khz_max; -- cgit v1.1 From 28a4f908acb342350b9ecbfcdf0a999cb83e05aa Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Mon, 13 Dec 2010 10:47:05 -0200 Subject: ARM: mx5: check for error in ioremap Signed-off-by: Fabio Estevam Signed-off-by: Sascha Hauer --- arch/arm/plat-mxc/ehci.c | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/arm/plat-mxc') diff --git a/arch/arm/plat-mxc/ehci.c b/arch/arm/plat-mxc/ehci.c index c1a7146..d59f5fe 100644 --- a/arch/arm/plat-mxc/ehci.c +++ b/arch/arm/plat-mxc/ehci.c @@ -254,6 +254,10 @@ int mxc_initialize_usb_hw(int port, unsigned int flags) int ret = 0; usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K); + if (!usb_base) { + printk(KERN_ERR "%s(): ioremap failed\n", __func__); + return -ENOMEM; + } switch (port) { case 0: /* OTG port */ -- cgit v1.1 From 96f3e2568456402769f3998e111746941f549dc6 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Lothar=20Wa=C3=9Fmann?= Date: Mon, 22 Nov 2010 09:39:51 +0100 Subject: MXC IOMUX-V3 replace struct pad_desc with bitmapped cookie (step 2) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This patch actually replaces the 'struct pad_desc' with a u64 cookie to facilitate adding platform specific pad_ctrl settings to an existing pad definition. So, instead of: iomux_v3_cfg_t power_key = MX51_PAD_EIM_A27__GPIO_2_21; power_key.pad_ctrl = MX51_GPIO_PAD_CTRL_2; mxc_iomux_v3_setup_pad(&power_key); one can write: mxc_iomux_v3_setup_pad((MX51_PAD_EIM_A27__GPIO_2_21 & ~MUX_PAD_CTRL_MASK) | MX51_GPIO_PAD_CTRL_2); Patch applies to branch 'imx-for-2.6.38' of git://git.pengutronix.de/git/imx/linux-2.6 Signed-Off-By: Lothar Waßmann Signed-off-by: Sascha Hauer --- arch/arm/plat-mxc/include/mach/iomux-v3.h | 90 +++++++++++++------------------ arch/arm/plat-mxc/iomux-v3.c | 25 +++++---- 2 files changed, 53 insertions(+), 62 deletions(-) (limited to 'arch/arm/plat-mxc') diff --git a/arch/arm/plat-mxc/include/mach/iomux-v3.h b/arch/arm/plat-mxc/include/mach/iomux-v3.h index 811716f..1462a1c 100644 --- a/arch/arm/plat-mxc/include/mach/iomux-v3.h +++ b/arch/arm/plat-mxc/include/mach/iomux-v3.h @@ -42,58 +42,42 @@ * If or refers to a GPIO, it is named * GPIO__ * - */ - -typedef struct deprecated_pad_desc { - unsigned mux_ctrl_ofs:12; /* IOMUXC_SW_MUX_CTL_PAD offset */ - unsigned mux_mode:8; - unsigned pad_ctrl_ofs:12; /* IOMUXC_SW_PAD_CTRL offset */ -#define NO_PAD_CTRL (1 << 16) - unsigned pad_ctrl:17; - unsigned select_input_ofs:12; /* IOMUXC_SELECT_INPUT offset */ - unsigned select_input:3; -} iomux_v3_cfg_t; - -static inline unsigned int MUX_CTRL_OFS(iomux_v3_cfg_t *pad) -{ - return pad->mux_ctrl_ofs; -} - -static inline unsigned int MUX_MODE(iomux_v3_cfg_t *pad) -{ - return pad->mux_mode; -} - -static inline unsigned int MUX_SELECT_INPUT_OFS(iomux_v3_cfg_t *pad) -{ - return pad->select_input_ofs; -} - -static inline unsigned int MUX_SELECT_INPUT(iomux_v3_cfg_t *pad) -{ - return pad->select_input; -} - -static inline unsigned int MUX_PAD_CTRL_OFS(iomux_v3_cfg_t *pad) -{ - return pad->pad_ctrl_ofs; -} - -static inline unsigned int MUX_PAD_CTRL(iomux_v3_cfg_t *pad) -{ - return pad->pad_ctrl; -} - -#define IOMUX_PAD(_pad_ctrl_ofs, _mux_ctrl_ofs, _mux_mode, _select_input_ofs, \ - _select_input, _pad_ctrl) \ - { \ - .mux_ctrl_ofs = _mux_ctrl_ofs, \ - .mux_mode = _mux_mode, \ - .pad_ctrl_ofs = _pad_ctrl_ofs, \ - .pad_ctrl = _pad_ctrl, \ - .select_input_ofs = _select_input_ofs, \ - .select_input = _select_input, \ - } + * IOMUX/PAD Bit field definitions + * + * MUX_CTRL_OFS: 0..11 (12) + * PAD_CTRL_OFS: 12..23 (12) + * SEL_INPUT_OFS: 24..35 (12) + * MUX_MODE + SION: 36..40 (5) + * PAD_CTRL + NO_PAD_CTRL: 41..57 (17) + * SEL_INP: 58..61 (4) + * reserved: 63 (1) +*/ + +typedef u64 iomux_v3_cfg_t; + +#define MUX_CTRL_OFS_SHIFT 0 +#define MUX_CTRL_OFS_MASK ((iomux_v3_cfg_t)0xfff << MUX_CTRL_OFS_SHIFT) +#define MUX_PAD_CTRL_OFS_SHIFT 12 +#define MUX_PAD_CTRL_OFS_MASK ((iomux_v3_cfg_t)0xfff << MUX_PAD_CTRL_OFS_SHIFT) +#define MUX_SEL_INPUT_OFS_SHIFT 24 +#define MUX_SEL_INPUT_OFS_MASK ((iomux_v3_cfg_t)0xfff << MUX_SEL_INPUT_OFS_SHIFT) + +#define MUX_MODE_SHIFT 36 +#define MUX_MODE_MASK ((iomux_v3_cfg_t)0x1f << MUX_MODE_SHIFT) +#define MUX_PAD_CTRL_SHIFT 41 +#define MUX_PAD_CTRL_MASK ((iomux_v3_cfg_t)0x1ffff << MUX_PAD_CTRL_SHIFT) +#define NO_PAD_CTRL ((iomux_v3_cfg_t)1 << (MUX_PAD_CTRL_SHIFT + 16)) +#define MUX_SEL_INPUT_SHIFT 58 +#define MUX_SEL_INPUT_MASK ((iomux_v3_cfg_t)0xf << MUX_SEL_INPUT_SHIFT) + +#define IOMUX_PAD(_pad_ctrl_ofs, _mux_ctrl_ofs, _mux_mode, _sel_input_ofs, \ + _sel_input, _pad_ctrl) \ + (((iomux_v3_cfg_t)(_mux_ctrl_ofs) << MUX_CTRL_OFS_SHIFT) | \ + ((iomux_v3_cfg_t)(_mux_mode) << MUX_MODE_SHIFT) | \ + ((iomux_v3_cfg_t)(_pad_ctrl_ofs) << MUX_PAD_CTRL_OFS_SHIFT) | \ + ((iomux_v3_cfg_t)(_pad_ctrl) << MUX_PAD_CTRL_SHIFT) | \ + ((iomux_v3_cfg_t)(_sel_input_ofs) << MUX_SEL_INPUT_OFS_SHIFT) | \ + ((iomux_v3_cfg_t)(_sel_input) << MUX_SEL_INPUT_SHIFT)) /* * Use to set PAD control @@ -137,7 +121,7 @@ static inline unsigned int MUX_PAD_CTRL(iomux_v3_cfg_t *pad) /* * setups a single pad in the iomuxer */ -int mxc_iomux_v3_setup_pad(iomux_v3_cfg_t *pad); +int mxc_iomux_v3_setup_pad(iomux_v3_cfg_t pad); /* * setups mutliple pads diff --git a/arch/arm/plat-mxc/iomux-v3.c b/arch/arm/plat-mxc/iomux-v3.c index 4cbbf2c..99a9cdb 100644 --- a/arch/arm/plat-mxc/iomux-v3.c +++ b/arch/arm/plat-mxc/iomux-v3.c @@ -34,17 +34,24 @@ static void __iomem *base; /* * configures a single pad in the iomuxer */ -int mxc_iomux_v3_setup_pad(iomux_v3_cfg_t *pad) +int mxc_iomux_v3_setup_pad(iomux_v3_cfg_t pad) { - if (MUX_CTRL_OFS(pad)) - __raw_writel(MUX_MODE(pad), base + MUX_CTRL_OFS(pad)); + u32 mux_ctrl_ofs = (pad & MUX_CTRL_OFS_MASK) >> MUX_CTRL_OFS_SHIFT; + u32 mux_mode = (pad & MUX_MODE_MASK) >> MUX_MODE_SHIFT; + u32 sel_input_ofs = (pad & MUX_SEL_INPUT_OFS_MASK) >> MUX_SEL_INPUT_OFS_SHIFT; + u32 sel_input = (pad & MUX_SEL_INPUT_MASK) >> MUX_SEL_INPUT_SHIFT; + u32 pad_ctrl_ofs = (pad & MUX_PAD_CTRL_OFS_MASK) >> MUX_PAD_CTRL_OFS_SHIFT; + u32 pad_ctrl = (pad & MUX_PAD_CTRL_MASK) >> MUX_PAD_CTRL_SHIFT; - if (MUX_SELECT_INPUT_OFS(pad)) - __raw_writel(MUX_SELECT_INPUT(pad), - base + MUX_SELECT_INPUT_OFS(pad)); + if (mux_ctrl_ofs) + __raw_writel(mux_mode, base + mux_ctrl_ofs); + + if (sel_input_ofs) + __raw_writel(sel_input, base + sel_input_ofs); + + if (!(pad_ctrl & NO_PAD_CTRL) && pad_ctrl_ofs) + __raw_writel(pad_ctrl, base + pad_ctrl_ofs); - if (!(MUX_PAD_CTRL(pad) & NO_PAD_CTRL) && MUX_PAD_CTRL_OFS(pad)) - __raw_writel(MUX_PAD_CTRL(pad), base + MUX_PAD_CTRL_OFS(pad)); return 0; } EXPORT_SYMBOL(mxc_iomux_v3_setup_pad); @@ -56,7 +63,7 @@ int mxc_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t *pad_list, unsigned count) int ret; for (i = 0; i < count; i++) { - ret = mxc_iomux_v3_setup_pad(p); + ret = mxc_iomux_v3_setup_pad(*p); if (ret) return ret; p++; -- cgit v1.1 From ee1ae4d7b1c9a8b73e232fa33dc733be59368ff6 Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Wed, 15 Dec 2010 09:56:35 +0100 Subject: ARM i.MX51: Full iomux support This iomux file has been constructed from the Freescale pinmux tool. It contains all pins from the tool, but the datasheet lists some configurations not present in the tool, these are not yet added. Signed-off-by: Sascha Hauer --- arch/arm/plat-mxc/include/mach/iomux-mx51.h | 1904 ++++++++++++++++++++++----- arch/arm/plat-mxc/include/mach/iomux-v3.h | 2 + 2 files changed, 1540 insertions(+), 366 deletions(-) (limited to 'arch/arm/plat-mxc') diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx51.h b/arch/arm/plat-mxc/include/mach/iomux-mx51.h index e1600f3..b6767f9 100644 --- a/arch/arm/plat-mxc/include/mach/iomux-mx51.h +++ b/arch/arm/plat-mxc/include/mach/iomux-mx51.h @@ -15,381 +15,1553 @@ #include -/* - * various IOMUX alternate output functions (1-7) - */ -typedef enum iomux_config { - IOMUX_CONFIG_ALT0, - IOMUX_CONFIG_ALT1, - IOMUX_CONFIG_ALT2, - IOMUX_CONFIG_ALT3, - IOMUX_CONFIG_ALT4, - IOMUX_CONFIG_ALT5, - IOMUX_CONFIG_ALT6, - IOMUX_CONFIG_ALT7, - IOMUX_CONFIG_GPIO, /* added to help user use GPIO mode */ - IOMUX_CONFIG_SION = 0x1 << 4, /* LOOPBACK:MUX SION bit */ -} iomux_pin_cfg_t; - /* Pad control groupings */ -#define MX51_UART1_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PKE | PAD_CTL_PUE | \ - PAD_CTL_DSE_HIGH) -#define MX51_UART2_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_DSE_HIGH | \ - PAD_CTL_SRE_FAST) -#define MX51_UART3_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_DSE_HIGH | \ - PAD_CTL_SRE_FAST) +#define MX51_UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_DSE_HIGH | \ + PAD_CTL_HYS | PAD_CTL_SRE_FAST) #define MX51_I2C_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_ODE | \ - PAD_CTL_DSE_HIGH | PAD_CTL_PUS_100K_UP | PAD_CTL_HYS) + PAD_CTL_DSE_HIGH | PAD_CTL_PUS_100K_UP | \ + PAD_CTL_HYS) #define MX51_ESDHC_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_ODE | \ - PAD_CTL_DSE_HIGH | PAD_CTL_PUS_100K_UP | PAD_CTL_HYS) -#define MX51_USBH1_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \ - PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ - PAD_CTL_PKE | PAD_CTL_HYS) -#define MX51_GPIO_PAD_CTRL (PAD_CTL_DSE_HIGH | PAD_CTL_PKE | \ - PAD_CTL_SRE_FAST) -#define MX51_GPIO_PAD_CTRL_2 (PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \ - PAD_CTL_PUS_100K_UP) -#define MX51_ECSPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PKE | PAD_CTL_DSE_HIGH | \ - PAD_CTL_SRE_FAST) -#define MX51_SDHCI_PAD_CTRL (PAD_CTL_DSE_HIGH | PAD_CTL_PUS_47K_UP | \ - PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_SRE_FAST | \ - PAD_CTL_DVS) + PAD_CTL_DSE_HIGH | PAD_CTL_PUS_100K_UP | \ + PAD_CTL_HYS) +#define MX51_USBH1_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_SRE_FAST | \ + PAD_CTL_DSE_HIGH | PAD_CTL_PUS_100K_UP | \ + PAD_CTL_HYS | PAD_CTL_PUE) +#define MX51_ECSPI_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_HYS | \ + PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST) +#define MX51_SDHCI_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_DSE_HIGH | \ + PAD_CTL_PUS_47K_UP | PAD_CTL_PUE | \ + PAD_CTL_SRE_FAST | PAD_CTL_DVS) +#define MX51_GPIO_PAD_CTRL (PAD_CTL_DSE_HIGH | PAD_CTL_PKE | PAD_CTL_SRE_FAST) -#define MX51_PAD_CTRL_1 (PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \ - PAD_CTL_PUE | PAD_CTL_PKE | PAD_CTL_HYS) -#define MX51_PAD_CTRL_2 (PAD_CTL_HYS | PAD_CTL_PKE) -#define MX51_PAD_CTRL_3 (PAD_CTL_PKE | PAD_CTL_PUS_100K_UP) -#define MX51_PAD_CTRL_4 (PAD_CTL_DVS | PAD_CTL_HYS | PAD_CTL_PKE) -#define MX51_PAD_CTRL_5 (PAD_CTL_DVS | PAD_CTL_DSE_HIGH) +#define MX51_PAD_CTRL_2 (PAD_CTL_PKE | PAD_CTL_HYS) +#define MX51_PAD_CTRL_3 (PAD_CTL_PKE | PAD_CTL_PUS_100K_UP) +#define MX51_PAD_CTRL_4 (PAD_CTL_PKE | PAD_CTL_DVS | PAD_CTL_HYS) +#define MX51_PAD_CTRL_5 (PAD_CTL_DVS | PAD_CTL_DSE_HIGH) /* * The naming convention for the pad modes is MX51_PAD___ - * If or refers to a GPIO, it is named GPIO__ + * If or refers to a GPIO, it is named GPIO_ * See also iomux-v3.h */ -/* PAD MUX ALT INPSE PATH PADCTRL */ -#define MX51_PAD_EIM_DA0__EIM_DA0 IOMUX_PAD(0x7a8, 0x01c, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_DA1__EIM_DA1 IOMUX_PAD(0x7a8, 0x020, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_DA2__EIM_DA2 IOMUX_PAD(0x7a8, 0x024, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_DA3__EIM_DA3 IOMUX_PAD(0x7a8, 0x028, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_DA4__EIM_DA4 IOMUX_PAD(0x7ac, 0x02c, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_DA5__EIM_DA5 IOMUX_PAD(0x7ac, 0x030, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_DA6__EIM_DA6 IOMUX_PAD(0x7ac, 0x034, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_DA7__EIM_DA7 IOMUX_PAD(0x7ac, 0x038, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_DA8__EIM_DA8 IOMUX_PAD(0x7b0, 0x03c, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_DA9__EIM_DA9 IOMUX_PAD(0x7b0, 0x040, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_DA10__EIM_DA10 IOMUX_PAD(0x7b0, 0x044, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_DA11__EIM_DA11 IOMUX_PAD(0x7b0, 0x048, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_DA12__EIM_DA12 IOMUX_PAD(0x7bc, 0x04c, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_DA13__EIM_DA13 IOMUX_PAD(0x7bc, 0x050, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_DA14__EIM_DA14 IOMUX_PAD(0x7bc, 0x054, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_DA15__EIM_DA15 IOMUX_PAD(0x7bc, 0x058, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_D16__GPIO_2_0 IOMUX_PAD(0x3f0, 0x05c, 1, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_D16__I2C1_SDA IOMUX_PAD(0x3f0, 0x05c, (4 | IOMUX_CONFIG_SION), \ - 0x09b4, 0, MX51_I2C_PAD_CTRL) -#define MX51_PAD_EIM_D17__GPIO_2_1 IOMUX_PAD(0x3f4, 0x060, 1, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_D18__GPIO_2_2 IOMUX_PAD(0x3f8, 0x064, 1, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_D19__GPIO_2_3 IOMUX_PAD(0x3fc, 0x068, 1, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_D19__I2C1_SCL IOMUX_PAD(0x3fc, 0x068, (4 | IOMUX_CONFIG_SION), \ - 0x09b0, 0, MX51_I2C_PAD_CTRL) -#define MX51_PAD_EIM_D20__GPIO_2_4 IOMUX_PAD(0x400, 0x06c, 1, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_D21__GPIO_2_5 IOMUX_PAD(0x404, 0x070, 1, 0x0, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_EIM_D22__GPIO_2_6 IOMUX_PAD(0x408, 0x074, 1, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_D23__GPIO_2_7 IOMUX_PAD(0x40c, 0x078, 1, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_D24__UART3_CTS IOMUX_PAD(0x410, 0x07c, 3, 0x0, 0, MX51_UART3_PAD_CTRL) -#define MX51_PAD_EIM_D25__UART3_RXD IOMUX_PAD(0x414, 0x080, 3, 0x9f4, 0, MX51_UART3_PAD_CTRL) -#define MX51_PAD_EIM_D25__UART2_CTS IOMUX_PAD(0x414, 0x080, 4, 0x0, 0, MX51_UART2_PAD_CTRL) -#define MX51_PAD_EIM_D26__UART3_TXD IOMUX_PAD(0x418, 0x084, 3, 0x0, 0, MX51_UART3_PAD_CTRL) -#define MX51_PAD_EIM_D26__UART2_RTS IOMUX_PAD(0x418, 0x084, 4, 0x9e8, 3, MX51_UART2_PAD_CTRL) -#define MX51_PAD_EIM_D27__UART3_RTS IOMUX_PAD(0x41c, 0x088, 3, 0x9f0, 3, MX51_UART3_PAD_CTRL) -#define MX51_PAD_EIM_D28__EIM_D28 IOMUX_PAD(0x420, 0x08c, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_D29__EIM_D29 IOMUX_PAD(0x424, 0x090, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_D30__EIM_D30 IOMUX_PAD(0x428, 0x094, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_D31__EIM_D31 IOMUX_PAD(0x42c, 0x09c, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_A16__GPIO_2_10 IOMUX_PAD(0x430, 0x09c, 1, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_A17__GPIO_2_11 IOMUX_PAD(0x434, 0x0a0, 1, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_A18__GPIO_2_12 IOMUX_PAD(0x438, 0x0a4, 1, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_A19__GPIO_2_13 IOMUX_PAD(0x43c, 0x0a8, 1, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_A20__GPIO_2_14 IOMUX_PAD(0x440, 0x0ac, 1, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_A21__GPIO_2_15 IOMUX_PAD(0x444, 0x0b0, 1, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_A22__GPIO_2_16 IOMUX_PAD(0x448, 0x0b4, 1, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_A23__GPIO_2_17 IOMUX_PAD(0x44c, 0x0b8, 1, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_A24__GPIO_2_18 IOMUX_PAD(0x450, 0x0bc, 1, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_A25__GPIO_2_19 IOMUX_PAD(0x454, 0x0c0, 1, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_A26__GPIO_2_20 IOMUX_PAD(0x458, 0x0c4, 1, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_A27__GPIO_2_21 IOMUX_PAD(0x45c, 0x0c8, 1, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_EB0__EIM_EB0 IOMUX_PAD(0x460, 0x0cc, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_EB1__EIM_EB1 IOMUX_PAD(0x464, 0x0d0, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_EB2__GPIO_2_22 IOMUX_PAD(0x468, 0x0d4, 1, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_EB2__FEC_MDIO IOMUX_PAD(0x468, 0x0d4, 3, 0x0, 0, MX51_PAD_CTRL_1 | PAD_CTL_PUS_22K_UP) -#define MX51_PAD_EIM_EB3__GPIO_2_23 IOMUX_PAD(0x46c, 0x0d8, 1, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_EB3__FEC_RDAT1 IOMUX_PAD(0x46c, 0x0d8, 3, 0x0, 0, MX51_PAD_CTRL_2) -#define MX51_PAD_EIM_OE__GPIO_2_24 IOMUX_PAD(0x470, 0x0dc, 1, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_CS0__GPIO_2_25 IOMUX_PAD(0x474, 0x0e0, 1, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_CS1__GPIO_2_26 IOMUX_PAD(0x478, 0x0e4, 1, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_CS2__GPIO_2_27 IOMUX_PAD(0x47c, 0x0e8, 1, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_CS2__FEC_RDAT2 IOMUX_PAD(0x47c, 0x0e8, 3, 0x0, 0, MX51_PAD_CTRL_2) -#define MX51_PAD_EIM_CS3__GPIO_2_28 IOMUX_PAD(0x480, 0x0ec, 1, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_CS3__FEC_RDAT3 IOMUX_PAD(0x480, 0x0ec, 3, 0x0, 0, MX51_PAD_CTRL_2) -#define MX51_PAD_EIM_CS4__GPIO_2_29 IOMUX_PAD(0x484, 0x0f0, 1, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_CS4__FEC_RX_ER IOMUX_PAD(0x484, 0x0f0, 3, 0x0, 0, MX51_PAD_CTRL_2) -#define MX51_PAD_EIM_CS5__GPIO_2_30 IOMUX_PAD(0x488, 0x0f4, 1, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_CS5__FEC_CRS IOMUX_PAD(0x488, 0x0f4, 3, 0x0, 0, MX51_PAD_CTRL_2) -#define MX51_PAD_EIM_DTACK__GPIO_2_31 IOMUX_PAD(0x48c, 0x0f8, 1, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_LBA__GPIO_3_1 IOMUX_PAD(0x494, 0x0FC, 1, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_CRE__GPIO_3_2 IOMUX_PAD(0x4A0, 0x100, 1, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DRAM_CS1__DRAM_CS1 IOMUX_PAD(0x4D0, 0x104, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_WE_B__GPIO_3_3 IOMUX_PAD(0x4E4, 0x108, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_RE_B__GPIO_3_4 IOMUX_PAD(0x4E8, 0x10C, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_ALE__GPIO_3_5 IOMUX_PAD(0x4EC, 0x110, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_CLE__GPIO_3_6 IOMUX_PAD(0x4F0, 0x114, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_WP_B__GPIO_3_7 IOMUX_PAD(0x4F4, 0x118, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_RB0__GPIO_3_8 IOMUX_PAD(0x4F8, 0x11C, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_RB1__GPIO_3_9 IOMUX_PAD(0x4FC, 0x120, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_RB2__GPIO_3_10 IOMUX_PAD(0x500, 0x124, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_RB2__ECSPI2_SCLK IOMUX_PAD(0x500, 0x124, 2, 0x0, 0, MX51_ECSPI_PAD_CTRL) -#define MX51_PAD_NANDF_RB2__FEC_COL IOMUX_PAD(0x500, 0x124, 1, 0x0, 0, MX51_PAD_CTRL_2) -#define MX51_PAD_NANDF_RB3__GPIO_3_11 IOMUX_PAD(0x504, 0x128, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_RB3__ECSPI2_MISO IOMUX_PAD(0x504, 0x128, 2, 0x0, 0, MX51_ECSPI_PAD_CTRL) -#define MX51_PAD_NANDF_RB3__FEC_RXCLK IOMUX_PAD(0x504, 0x128, 1, 0x0, 0, MX51_PAD_CTRL_2) -#define MX51_PAD_NANDF_RB6__FEC_RDAT0 IOMUX_PAD(0x5DC, 0x134, 1, 0x0, 0, MX51_PAD_CTRL_4) -#define MX51_PAD_NANDF_RB7__FEC_TDAT0 IOMUX_PAD(0x5E0, 0x138, 1, 0x0, 0, MX51_PAD_CTRL_5) -#define MX51_PAD_GPIO_NAND__GPIO_3_12 IOMUX_PAD(0x514, 0x12C, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_CS0__GPIO_3_16 IOMUX_PAD(0x518, 0x130, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_CS1__GPIO_3_17 IOMUX_PAD(0x51C, 0x134, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_CS2__GPIO_3_18 IOMUX_PAD(0x520, 0x138, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_CS2__FEC_TX_ER IOMUX_PAD(0x520, 0x138, 2, 0x0, 0, MX51_PAD_CTRL_5) -#define MX51_PAD_NANDF_CS3__GPIO_3_19 IOMUX_PAD(0x524, 0x13C, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_CS3__FEC_MDC IOMUX_PAD(0x524, 0x13C, 2, 0x0, 0, MX51_PAD_CTRL_5) -#define MX51_PAD_NANDF_CS4__GPIO_3_20 IOMUX_PAD(0x528, 0x140, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_CS4__FEC_TDAT1 IOMUX_PAD(0x528, 0x140, 2, 0x0, 0, MX51_PAD_CTRL_5) -#define MX51_PAD_NANDF_CS5__GPIO_3_21 IOMUX_PAD(0x52C, 0x144, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_CS5__FEC_TDAT2 IOMUX_PAD(0x52C, 0x144, 2, 0x0, 0, MX51_PAD_CTRL_5) -#define MX51_PAD_NANDF_CS6__GPIO_3_22 IOMUX_PAD(0x530, 0x148, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_CS6__FEC_TDAT3 IOMUX_PAD(0x530, 0x148, 2, 0x0, 0, MX51_PAD_CTRL_5) -#define MX51_PAD_NANDF_CS7__GPIO_3_23 IOMUX_PAD(0x534, 0x14C, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_CS7__FEC_TX_EN IOMUX_PAD(0x534, 0x14C, 1, 0x0, 0, MX51_PAD_CTRL_5) -#define MX51_PAD_NANDF_RDY_INT__GPIO_3_24 IOMUX_PAD(0x538, 0x150, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK IOMUX_PAD(0x538, 0x150, 1, 0x0, 0, MX51_PAD_CTRL_4) -#define MX51_PAD_NANDF_D15__GPIO_3_25 IOMUX_PAD(0x53C, 0x154, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_D15__ECSPI2_MOSI IOMUX_PAD(0x53C, 0x154, 2, 0x0, 0, MX51_ECSPI_PAD_CTRL) -#define MX51_PAD_NANDF_D14__GPIO_3_26 IOMUX_PAD(0x540, 0x158, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_D13__GPIO_3_27 IOMUX_PAD(0x544, 0x15C, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_D12__GPIO_3_28 IOMUX_PAD(0x548, 0x160, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_D11__GPIO_3_29 IOMUX_PAD(0x54C, 0x164, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_D10__GPIO_3_30 IOMUX_PAD(0x550, 0x168, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_D9__GPIO_3_31 IOMUX_PAD(0x554, 0x16C, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_D8__GPIO_4_0 IOMUX_PAD(0x558, 0x170, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_D7__GPIO_4_1 IOMUX_PAD(0x55C, 0x174, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_D6__GPIO_4_2 IOMUX_PAD(0x560, 0x178, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_D5__GPIO_4_3 IOMUX_PAD(0x564, 0x17C, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_D4__GPIO_4_4 IOMUX_PAD(0x568, 0x180, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_D3__GPIO_4_5 IOMUX_PAD(0x56C, 0x184, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_D2__GPIO_4_6 IOMUX_PAD(0x570, 0x188, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_D1__GPIO_4_7 IOMUX_PAD(0x574, 0x18C, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_D0__GPIO_4_8 IOMUX_PAD(0x578, 0x190, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_CSI1_D8__GPIO_3_12 IOMUX_PAD(0x57C, 0x194, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_CSI1_D9__GPIO_3_13 IOMUX_PAD(0x580, 0x198, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_CSI1_D10__CSI1_D10 IOMUX_PAD(0x584, 0x19C, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_CSI1_D11__CSI1_D11 IOMUX_PAD(0x588, 0x1A0, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_CSI1_D12__CSI1_D12 IOMUX_PAD(0x58C, 0x1A4, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_CSI1_D13__CSI1_D13 IOMUX_PAD(0x590, 0x1A8, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_CSI1_D14__CSI1_D14 IOMUX_PAD(0x594, 0x1AC, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_CSI1_D15__CSI1_D15 IOMUX_PAD(0x598, 0x1B0, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_CSI1_D16__CSI1_D16 IOMUX_PAD(0x59C, 0x1B4, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_CSI1_D17__CSI1_D17 IOMUX_PAD(0x5A0, 0x1B8, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_CSI1_D18__CSI1_D18 IOMUX_PAD(0x5A4, 0x1BC, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_CSI1_D19__CSI1_D19 IOMUX_PAD(0x5A8, 0x1C0, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_CSI1_VSYNC__CSI1_VSYNC IOMUX_PAD(0x5AC, 0x1C4, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_CSI1_VSYNC__GPIO_3_14 IOMUX_PAD(0x5AC, 0x1C4, 3, 0x0, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_CSI1_HSYNC__CSI1_HSYNC IOMUX_PAD(0x5B0, 0x1C8, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_CSI1_HSYNC__GPIO_3_15 IOMUX_PAD(0x5B0, 0x1C8, 3, 0x0, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_CSI1_PIXCLK__CSI1_PIXCLK IOMUX_PAD(0x5B4, 0x000, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_CSI1_MCLK__CSI1_MCLK IOMUX_PAD(0x5B8, 0x000, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_CSI1_PKE0__CSI1_PKE0 IOMUX_PAD(0x860, 0x000, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_CSI2_D12__GPIO_4_9 IOMUX_PAD(0x5BC, 0x1CC, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_CSI2_D13__GPIO_4_10 IOMUX_PAD(0x5C0, 0x1D0, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_CSI2_D14__GPIO_4_11 IOMUX_PAD(0x5C4, 0x1D4, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_CSI2_D15__GPIO_4_12 IOMUX_PAD(0x5C8, 0x1D8, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_CSI2_D16__GPIO_4_11 IOMUX_PAD(0x5CC, 0x1DC, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_CSI2_D17__GPIO_4_12 IOMUX_PAD(0x5D0, 0x1E0, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_CSI2_D18__GPIO_4_11 IOMUX_PAD(0x5D4, 0x1E4, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_CSI2_D19__GPIO_4_12 IOMUX_PAD(0x5D8, 0x1E8, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_CSI2_VSYNC__GPIO_4_13 IOMUX_PAD(0x5DC, 0x1EC, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_CSI2_HSYNC__GPIO_4_14 IOMUX_PAD(0x5E0, 0x1F0, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_CSI2_PIXCLK__GPIO_4_15 IOMUX_PAD(0x5E4, 0x1F4, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_I2C1_CLK__GPIO_4_16 IOMUX_PAD(0x5E8, 0x1F8, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_I2C1_CLK__HSI2C_CLK IOMUX_PAD(0x5E8, 0x1F8, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_I2C1_DAT__GPIO_4_17 IOMUX_PAD(0x5EC, 0x1FC, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_I2C1_DAT__HSI2C_DAT IOMUX_PAD(0x5EC, 0x1FC, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_AUD3_BB_TXD__AUD3_BB_TXD IOMUX_PAD(0x5F0, 0x200, IOMUX_CONFIG_SION, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_AUD3_BB_TXD__GPIO_4_18 IOMUX_PAD(0x5F0, 0x200, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_AUD3_BB_RXD__AUD3_BB_RXD IOMUX_PAD(0x5F4, 0x204, IOMUX_CONFIG_SION, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_AUD3_BB_RXD__GPIO_4_19 IOMUX_PAD(0x5F4, 0x204, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_AUD3_BB_CK__AUD3_BB_CK IOMUX_PAD(0x5F8, 0x208, IOMUX_CONFIG_SION, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_AUD3_BB_CK__GPIO_4_20 IOMUX_PAD(0x5F8, 0x208, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_AUD3_BB_FS__AUD3_BB_FS IOMUX_PAD(0x5FC, 0x20C, IOMUX_CONFIG_SION, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_AUD3_BB_FS__GPIO_4_21 IOMUX_PAD(0x5FC, 0x20C, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI IOMUX_PAD(0x600, 0x210, 0, 0x0, 0, MX51_ECSPI_PAD_CTRL) -#define MX51_PAD_CSPI1_MOSI__GPIO_4_22 IOMUX_PAD(0x600, 0x210, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_CSPI1_MISO__ECSPI1_MISO IOMUX_PAD(0x604, 0x214, 0, 0x0, 0, MX51_ECSPI_PAD_CTRL) -#define MX51_PAD_CSPI1_MISO__GPIO_4_23 IOMUX_PAD(0x604, 0x214, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_CSPI1_SS0__ECSPI1_SS0 IOMUX_PAD(0x608, 0x218, 0, 0x0, 0, MX51_ECSPI_PAD_CTRL) -#define MX51_PAD_CSPI1_SS0__GPIO_4_24 IOMUX_PAD(0x608, 0x218, 3, 0x0, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_CSPI1_SS1__ECSPI1_SS1 IOMUX_PAD(0x60C, 0x21C, 0, 0x0, 0, MX51_ECSPI_PAD_CTRL) -#define MX51_PAD_CSPI1_SS1__GPIO_4_25 IOMUX_PAD(0x60C, 0x21C, 3, 0x0, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_CSPI1_RDY__ECSPI1_RDY IOMUX_PAD(0x610, 0x220, 0, 0x0, 0, MX51_ECSPI_PAD_CTRL) -#define MX51_PAD_CSPI1_RDY__GPIO_4_26 IOMUX_PAD(0x610, 0x220, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK IOMUX_PAD(0x614, 0x224, 0, 0x0, 0, MX51_ECSPI_PAD_CTRL) -#define MX51_PAD_CSPI1_SCLK__GPIO_4_27 IOMUX_PAD(0x614, 0x224, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_UART1_RXD__UART1_RXD IOMUX_PAD(0x618, 0x228, 0, 0x9e4, 0, MX51_UART1_PAD_CTRL | PAD_CTL_SRE_FAST) -#define MX51_PAD_UART1_TXD__UART1_TXD IOMUX_PAD(0x61C, 0x22C, 0, 0x0, 0, MX51_UART1_PAD_CTRL | PAD_CTL_SRE_FAST) -#define MX51_PAD_UART1_RTS__UART1_RTS IOMUX_PAD(0x620, 0x230, 0, 0x9e0, 0, MX51_UART1_PAD_CTRL) -#define MX51_PAD_UART1_CTS__UART1_CTS IOMUX_PAD(0x624, 0x234, 0, 0x0, 0, MX51_UART1_PAD_CTRL) -#define MX51_PAD_UART2_RXD__UART2_RXD IOMUX_PAD(0x628, 0x238, 0, 0x9ec, 2, MX51_UART2_PAD_CTRL) -#define MX51_PAD_UART2_TXD__UART2_TXD IOMUX_PAD(0x62C, 0x23C, 0, 0x0, 0, MX51_UART2_PAD_CTRL) -#define MX51_PAD_UART3_RXD__UART3_RXD IOMUX_PAD(0x630, 0x240, 1, 0x9f4, 4, MX51_UART3_PAD_CTRL) -#define MX51_PAD_UART3_RXD__GPIO_1_22 IOMUX_PAD(0x630, 0x240, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_UART3_TXD__UART3_TXD IOMUX_PAD(0x634, 0x244, 1, 0x0, 0, MX51_UART3_PAD_CTRL) -#define MX51_PAD_UART3_TXD__GPIO_1_23 IOMUX_PAD(0x634, 0x244, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_OWIRE_LINE__GPIO_1_24 IOMUX_PAD(0x638, 0x248, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_KEY_ROW0__KEY_ROW0 IOMUX_PAD(0x63C, 0x24C, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_KEY_ROW1__KEY_ROW1 IOMUX_PAD(0x640, 0x250, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_KEY_ROW2__KEY_ROW2 IOMUX_PAD(0x644, 0x254, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_KEY_ROW3__KEY_ROW3 IOMUX_PAD(0x648, 0x258, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_KEY_COL0__KEY_COL0 IOMUX_PAD(0x64C, 0x25C, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_KEY_COL1__KEY_COL1 IOMUX_PAD(0x650, 0x260, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_KEY_COL2__KEY_COL2 IOMUX_PAD(0x654, 0x264, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_KEY_COL3__KEY_COL3 IOMUX_PAD(0x658, 0x268, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_KEY_COL4__KEY_COL4 IOMUX_PAD(0x65C, 0x26C, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_KEY_COL4__UART3_RTS IOMUX_PAD(0x65C, 0x26C, 2, 0x9f0, 4, MX51_UART3_PAD_CTRL) -#define MX51_PAD_KEY_COL4__I2C2_SCL IOMUX_PAD(0x65C, 0x26C, (3 | IOMUX_CONFIG_SION), \ - 0x09b8, 1, MX51_I2C_PAD_CTRL) -#define MX51_PAD_KEY_COL5__KEY_COL5 IOMUX_PAD(0x660, 0x270, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_KEY_COL5__UART3_CTS IOMUX_PAD(0x660, 0x270, 2, 0, 0, MX51_UART3_PAD_CTRL) -#define MX51_PAD_KEY_COL5__I2C2_SDA IOMUX_PAD(0x660, 0x270, (3 | IOMUX_CONFIG_SION), \ - 0x09bc, 1, MX51_I2C_PAD_CTRL) -#define MX51_PAD_USBH1_CLK__USBH1_CLK IOMUX_PAD(0x678, 0x278, 0, 0x0, 0, MX51_USBH1_PAD_CTRL) -#define MX51_PAD_USBH1_DIR__USBH1_DIR IOMUX_PAD(0x67C, 0x27C, 0, 0x0, 0, MX51_USBH1_PAD_CTRL) -#define MX51_PAD_USBH1_STP__USBH1_STP IOMUX_PAD(0x680, 0x280, 0, 0x0, 0, MX51_USBH1_PAD_CTRL) -#define MX51_PAD_USBH1_STP__GPIO_1_27 IOMUX_PAD(0x680, 0x280, 2, 0x0, 0, MX51_USBH1_PAD_CTRL) -#define MX51_PAD_USBH1_NXT__USBH1_NXT IOMUX_PAD(0x684, 0x284, 0, 0x0, 0, MX51_USBH1_PAD_CTRL) -#define MX51_PAD_USBH1_DATA0__USBH1_DATA0 IOMUX_PAD(0x688, 0x288, 0, 0x0, 0, MX51_USBH1_PAD_CTRL) -#define MX51_PAD_USBH1_DATA1__USBH1_DATA1 IOMUX_PAD(0x68C, 0x28C, 0, 0x0, 0, MX51_USBH1_PAD_CTRL) -#define MX51_PAD_USBH1_DATA2__USBH1_DATA2 IOMUX_PAD(0x690, 0x290, 0, 0x0, 0, MX51_USBH1_PAD_CTRL) -#define MX51_PAD_USBH1_DATA3__USBH1_DATA3 IOMUX_PAD(0x694, 0x294, 0, 0x0, 0, MX51_USBH1_PAD_CTRL) -#define MX51_PAD_USBH1_DATA4__USBH1_DATA4 IOMUX_PAD(0x698, 0x298, 0, 0x0, 0, MX51_USBH1_PAD_CTRL) -#define MX51_PAD_USBH1_DATA5__USBH1_DATA5 IOMUX_PAD(0x69C, 0x29C, 0, 0x0, 0, MX51_USBH1_PAD_CTRL) -#define MX51_PAD_USBH1_DATA6__USBH1_DATA6 IOMUX_PAD(0x6A0, 0x2A0, 0, 0x0, 0, MX51_USBH1_PAD_CTRL) -#define MX51_PAD_USBH1_DATA7__USBH1_DATA7 IOMUX_PAD(0x6A4, 0x2A4, 0, 0x0, 0, MX51_USBH1_PAD_CTRL) -#define MX51_PAD_DI1_PIN11__GPIO_3_0 IOMUX_PAD(0x6A8, 0x2A8, 4, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DI1_PIN12__GPIO_3_1 IOMUX_PAD(0x6AC, 0x2AC, 4, 0x978, 1, NO_PAD_CTRL) -#define MX51_PAD_DI1_PIN13__GPIO_3_2 IOMUX_PAD(0x6B0, 0x2B0, 4, 0x97c, 1, NO_PAD_CTRL) -#define MX51_PAD_DI1_D0_CS__GPIO_3_3 IOMUX_PAD(0x6B4, 0x2B4, 4, 0x980, 1, NO_PAD_CTRL) -#define MX51_PAD_DI1_D1_CS__GPIO_3_4 IOMUX_PAD(0x6B8, 0x2B8, 4, 0x984, 1, NO_PAD_CTRL) -#define MX51_PAD_DISPB2_SER_DIN__GPIO_3_5 IOMUX_PAD(0x6BC, 0x2BC, 4, 0x988, 1, NO_PAD_CTRL) -#define MX51_PAD_DISPB2_SER_DIO__GPIO_3_6 IOMUX_PAD(0x6C0, 0x2C0, 4, 0x98c, 1, NO_PAD_CTRL) -#define MX51_PAD_DISPB2_SER_CLK__GPIO_3_7 IOMUX_PAD(0x6C4, 0x2C4, 4, 0x990, 1, NO_PAD_CTRL) -#define MX51_PAD_DISPB2_SER_RS__GPIO_3_8 IOMUX_PAD(0x6C8, 0x2C8, 4, 0x994, 1, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT0__DISP1_DAT0 IOMUX_PAD(0x6CC, 0x2CC, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT1__DISP1_DAT1 IOMUX_PAD(0x6D0, 0x2D0, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT2__DISP1_DAT2 IOMUX_PAD(0x6D4, 0x2D4, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT3__DISP1_DAT3 IOMUX_PAD(0x6D8, 0x2D8, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT4__DISP1_DAT4 IOMUX_PAD(0x6DC, 0x2DC, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT5__DISP1_DAT5 IOMUX_PAD(0x6E0, 0x2E0, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT6__DISP1_DAT6 IOMUX_PAD(0x6E4, 0x2E4, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT7__DISP1_DAT7 IOMUX_PAD(0x6E8, 0x2E8, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT8__DISP1_DAT8 IOMUX_PAD(0x6EC, 0x2EC, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT9__DISP1_DAT9 IOMUX_PAD(0x6F0, 0x2F0, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT10__DISP1_DAT10 IOMUX_PAD(0x6F4, 0x2F4, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT11__DISP1_DAT11 IOMUX_PAD(0x6F8, 0x2F8, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT12__DISP1_DAT12 IOMUX_PAD(0x6FC, 0x2FC, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT13__DISP1_DAT13 IOMUX_PAD(0x700, 0x300, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT14__DISP1_DAT14 IOMUX_PAD(0x704, 0x304, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT15__DISP1_DAT15 IOMUX_PAD(0x708, 0x308, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT16__DISP1_DAT16 IOMUX_PAD(0x70C, 0x30C, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT17__DISP1_DAT17 IOMUX_PAD(0x710, 0x310, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT18__DISP1_DAT18 IOMUX_PAD(0x714, 0x314, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT19__DISP1_DAT19 IOMUX_PAD(0x718, 0x318, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT20__DISP1_DAT20 IOMUX_PAD(0x71C, 0x31C, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT21__DISP1_DAT21 IOMUX_PAD(0x720, 0x320, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT22__DISP1_DAT22 IOMUX_PAD(0x724, 0x324, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT23__DISP1_DAT23 IOMUX_PAD(0x728, 0x328, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DI1_PIN3__DI1_PIN3 IOMUX_PAD(0x72C, 0x32C, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DI1_PIN2__DI1_PIN2 IOMUX_PAD(0x734, 0x330, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DI_GP1__DI_GP1 IOMUX_PAD(0x73C, 0x334, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DI_GP2__DI_GP2 IOMUX_PAD(0x740, 0x338, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DI_GP3__DI_GP3 IOMUX_PAD(0x744, 0x33C, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DI2_PIN4__DI2_PIN4 IOMUX_PAD(0x748, 0x340, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DI2_PIN2__DI2_PIN2 IOMUX_PAD(0x74C, 0x344, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DI2_PIN3__DI2_PIN3 IOMUX_PAD(0x750, 0x348, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK IOMUX_PAD(0x754, 0x34C, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DI_GP4__DI_GP4 IOMUX_PAD(0x758, 0x350, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP2_DAT0__DISP2_DAT0 IOMUX_PAD(0x75C, 0x354, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP2_DAT1__DISP2_DAT1 IOMUX_PAD(0x760, 0x358, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP2_DAT2__DISP2_DAT2 IOMUX_PAD(0x764, 0x35C, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP2_DAT3__DISP2_DAT3 IOMUX_PAD(0x768, 0x360, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP2_DAT4__DISP2_DAT4 IOMUX_PAD(0x76C, 0x364, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP2_DAT5__DISP2_DAT5 IOMUX_PAD(0x770, 0x368, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP2_DAT6__GPIO_1_19 IOMUX_PAD(0x774, 0x36C, 5, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP2_DAT7__GPIO_1_29 IOMUX_PAD(0x778, 0x370, 5, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP2_DAT8__GPIO_1_30 IOMUX_PAD(0x77C, 0x374, 5, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP2_DAT9__GPIO_1_31 IOMUX_PAD(0x780, 0x378, 5, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP2_DAT10__DISP2_DAT10 IOMUX_PAD(0x784, 0x37C, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP2_DAT11__DISP2_DAT11 IOMUX_PAD(0x788, 0x380, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP2_DAT12__DISP2_DAT12 IOMUX_PAD(0x78C, 0x384, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP2_DAT13__DISP2_DAT13 IOMUX_PAD(0x790, 0x388, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP2_DAT14__DISP2_DAT14 IOMUX_PAD(0x794, 0x38C, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP2_DAT15__DISP2_DAT15 IOMUX_PAD(0x798, 0x390, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_SD1_CMD__SD1_CMD IOMUX_PAD(0x79C, 0x394, IOMUX_CONFIG_SION, 0x0, 0, \ - MX51_SDHCI_PAD_CTRL) -#define MX51_PAD_SD1_CMD__AUD5_RXFS IOMUX_PAD(0x79C, 0x394, 1, 0x8e0, 1, NO_PAD_CTRL) -#define MX51_PAD_SD1_CLK__SD1_CLK IOMUX_PAD(0x7A0, 0x398, IOMUX_CONFIG_SION, 0x0, 0, \ - MX51_SDHCI_PAD_CTRL | PAD_CTL_HYS) -#define MX51_PAD_SD1_CLK__AUD5_RXC IOMUX_PAD(0x7A0, 0x398, 1, 0x8dc, 1, NO_PAD_CTRL) -#define MX51_PAD_SD1_DATA0__SD1_DATA0 IOMUX_PAD(0x7A4, 0x39C, IOMUX_CONFIG_SION, 0x0, 0, \ - MX51_SDHCI_PAD_CTRL) -#define MX51_PAD_SD1_DATA0__AUD5_TXD IOMUX_PAD(0x7A4, 0x39C, 1, 0x8d8, 2, NO_PAD_CTRL) -#define MX51_PAD_SD1_DATA1__SD1_DATA1 IOMUX_PAD(0x7A8, 0x3A0, IOMUX_CONFIG_SION, 0x0, 0, \ - MX51_SDHCI_PAD_CTRL) -#define MX51_PAD_SD1_DATA1__AUD5_RXD IOMUX_PAD(0x7A8, 0x3A0, 1, 0x8d4, 2, NO_PAD_CTRL) -#define MX51_PAD_SD1_DATA2__SD1_DATA2 IOMUX_PAD(0x7AC, 0x3A4, IOMUX_CONFIG_SION, 0x0, 0, \ - MX51_SDHCI_PAD_CTRL) -#define MX51_PAD_SD1_DATA2__AUD5_TXC IOMUX_PAD(0x7AC, 0x3A4, 1, 0x8e4, 2, NO_PAD_CTRL) -#define MX51_PAD_SD1_DATA3__SD1_DATA3 IOMUX_PAD(0x7B0, 0x3A8, IOMUX_CONFIG_SION, 0x0, 0, \ - MX51_SDHCI_PAD_CTRL) -#define MX51_PAD_SD1_DATA3__AUD5_TXFS IOMUX_PAD(0x7B0, 0x3A8, 1, 0x8e8, 2, NO_PAD_CTRL) -#define MX51_PAD_SD2_CMD__SD2_CMD IOMUX_PAD(0x7BC, 0x3B4, IOMUX_CONFIG_SION, 0x0, 1, \ - MX51_SDHCI_PAD_CTRL) -#define MX51_PAD_SD2_CLK__SD2_CLK IOMUX_PAD(0x7C0, 0x3B8, IOMUX_CONFIG_SION, 0x0, 0, \ - MX51_SDHCI_PAD_CTRL | PAD_CTL_HYS) -#define MX51_PAD_SD2_DATA0__SD2_DATA0 IOMUX_PAD(0x7C4, 0x3BC, IOMUX_CONFIG_SION, 0x0, 0, \ - MX51_SDHCI_PAD_CTRL) -#define MX51_PAD_SD2_DATA1__SD2_DATA1 IOMUX_PAD(0x7C8, 0x3C0, IOMUX_CONFIG_SION, 0x0, 0, \ - MX51_SDHCI_PAD_CTRL) -#define MX51_PAD_SD2_DATA2__SD2_DATA2 IOMUX_PAD(0x7CC, 0x3C4, IOMUX_CONFIG_SION, 0x0, 0, \ - MX51_SDHCI_PAD_CTRL) -#define MX51_PAD_SD2_DATA3__SD2_DATA3 IOMUX_PAD(0x7D0, 0x3C8, IOMUX_CONFIG_SION, 0x0, 0, \ - MX51_SDHCI_PAD_CTRL) -#define MX51_PAD_GPIO_1_0__ESDHC1_CD IOMUX_PAD(0x7B4, 0x3AC, 0, 0x0, 0, MX51_ESDHC_PAD_CTRL) -#define MX51_PAD_GPIO_1_0__GPIO_1_0 IOMUX_PAD(0x7B4, 0x3AC, 1, 0x0, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_GPIO_1_1__ESDHC1_WP IOMUX_PAD(0x7B8, 0x3B0, 0, 0x0, 0, MX51_ESDHC_PAD_CTRL) -#define MX51_PAD_GPIO_1_1__GPIO_1_1 IOMUX_PAD(0x7B8, 0x3B0, 1, 0x0, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_GPIO_1_2__GPIO_1_2 IOMUX_PAD(0x7D4, 0x3CC, 0, 0x0, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_GPIO_1_2__I2C2_SCL IOMUX_PAD(0x7D4, 0x3CC, (2 | IOMUX_CONFIG_SION), \ - 0x9b8, 3, MX51_I2C_PAD_CTRL) -#define MX51_PAD_GPIO_1_3__GPIO_1_3 IOMUX_PAD(0x7D8, 0x3D0, 0, 0x0, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_GPIO_1_3__I2C2_SDA IOMUX_PAD(0x7D8, 0x3D0, (2 | IOMUX_CONFIG_SION), \ - 0x9bc, 3, MX51_I2C_PAD_CTRL) -#define MX51_PAD_PMIC_INT_REQ__PMIC_INT_REQ IOMUX_PAD(0x7FC, 0x3D4, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_1_4__GPIO_1_4 IOMUX_PAD(0x804, 0x3D8, 0, 0x0, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_GPIO_1_5__GPIO_1_5 IOMUX_PAD(0x808, 0x3DC, 0, 0x0, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_GPIO_1_6__GPIO_1_6 IOMUX_PAD(0x80C, 0x3E0, 0, 0x0, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_GPIO_1_7__GPIO_1_7 IOMUX_PAD(0x810, 0x3E4, 0, 0x0, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_GPIO_1_7__ESDHC2_WP IOMUX_PAD(0x810, 0x3E4, 6, 0x0, 0, MX51_ESDHC_PAD_CTRL) -#define MX51_PAD_GPIO_1_8__GPIO_1_8 IOMUX_PAD(0x814, 0x3E8, 0, 0x0, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_GPIO_1_8__ESDHC2_CD IOMUX_PAD(0x814, 0x3E8, 6, 0x0, 0, MX51_ESDHC_PAD_CTRL) -#define MX51_PAD_GPIO_1_9__GPIO_1_9 IOMUX_PAD(0x818, 0x3EC, 0, 0x0, 0, MX51_GPIO_PAD_CTRL) +/* Raw pin modes without pad control */ +/* PAD MUX ALT INPSE PATH PADCTRL */ +#define _MX51_PAD_EIM_D16__AUD4_RXFS IOMUX_PAD(0x3f0, 0x5c, 5, 0x0000, 0, 0) +#define _MX51_PAD_EIM_D16__AUD5_TXD IOMUX_PAD(0x3f0, 0x5c, 7, 0x08d8, 0, 0) +#define _MX51_PAD_EIM_D16__EIM_D16 IOMUX_PAD(0x3f0, 0x5c, 0, 0x0000, 0, 0) +#define _MX51_PAD_EIM_D16__GPIO2_0 IOMUX_PAD(0x3f0, 0x5c, 1, 0x0000, 0, 0) +#define _MX51_PAD_EIM_D16__I2C1_SDA IOMUX_PAD(0x3f0, 0x5c, 0x14, 0x09b4, 0, 0) +#define _MX51_PAD_EIM_D16__UART2_CTS IOMUX_PAD(0x3f0, 0x5c, 3, 0x0000, 0, 0) +#define _MX51_PAD_EIM_D16__USBH2_DATA0 IOMUX_PAD(0x3f0, 0x5c, 2, 0x0000, 0, 0) +#define _MX51_PAD_EIM_D17__AUD5_RXD IOMUX_PAD(0x3f4, 0x60, 7, 0x08d4, 0, 0) +#define _MX51_PAD_EIM_D17__EIM_D17 IOMUX_PAD(0x3f4, 0x60, 0, 0x0000, 0, 0) +#define _MX51_PAD_EIM_D17__GPIO2_1 IOMUX_PAD(0x3f4, 0x60, 1, 0x0000, 0, 0) +#define _MX51_PAD_EIM_D17__UART2_RXD IOMUX_PAD(0x3f4, 0x60, 3, 0x09ec, 0, 0) +#define _MX51_PAD_EIM_D17__UART3_CTS IOMUX_PAD(0x3f4, 0x60, 4, 0x0000, 0, 0) +#define _MX51_PAD_EIM_D17__USBH2_DATA1 IOMUX_PAD(0x3f4, 0x60, 2, 0x0000, 0, 0) +#define _MX51_PAD_EIM_D18__AUD5_TXC IOMUX_PAD(0x3f8, 0x64, 7, 0x08e4, 0, 0) +#define _MX51_PAD_EIM_D18__EIM_D18 IOMUX_PAD(0x3f8, 0x64, 0, 0x0000, 0, 0) +#define _MX51_PAD_EIM_D18__GPIO2_2 IOMUX_PAD(0x3f8, 0x64, 1, 0x0000, 0, 0) +#define _MX51_PAD_EIM_D18__UART2_TXD IOMUX_PAD(0x3f8, 0x64, 3, 0x0000, 0, 0) +#define _MX51_PAD_EIM_D18__UART3_RTS IOMUX_PAD(0x3f8, 0x64, 4, 0x09f0, 1, 0) +#define _MX51_PAD_EIM_D18__USBH2_DATA2 IOMUX_PAD(0x3f8, 0x64, 2, 0x0000, 0, 0) +#define _MX51_PAD_EIM_D19__AUD4_RXC IOMUX_PAD(0x3fc, 0x68, 5, 0x0000, 0, 0) +#define _MX51_PAD_EIM_D19__AUD5_TXFS IOMUX_PAD(0x3fc, 0x68, 7, 0x08e8, 0, 0) +#define _MX51_PAD_EIM_D19__EIM_D19 IOMUX_PAD(0x3fc, 0x68, 0, 0x0000, 0, 0) +#define _MX51_PAD_EIM_D19__GPIO2_3 IOMUX_PAD(0x3fc, 0x68, 1, 0x0000, 0, 0) +#define _MX51_PAD_EIM_D19__I2C1_SCL IOMUX_PAD(0x3fc, 0x68, 0x14, 0x09b0, 0, 0) +#define _MX51_PAD_EIM_D19__UART2_RTS IOMUX_PAD(0x3fc, 0x68, 3, 0x09e8, 1, 0) +#define _MX51_PAD_EIM_D19__USBH2_DATA3 IOMUX_PAD(0x3fc, 0x68, 2, 0x0000, 0, 0) +#define _MX51_PAD_EIM_D20__AUD4_TXD IOMUX_PAD(0x400, 0x6c, 5, 0x08c8, 0, 0) +#define _MX51_PAD_EIM_D20__EIM_D20 IOMUX_PAD(0x400, 0x6c, 0, 0x0000, 0, 0) +#define _MX51_PAD_EIM_D20__GPIO2_4 IOMUX_PAD(0x400, 0x6c, 1, 0x0000, 0, 0) +#define _MX51_PAD_EIM_D20__SRTC_ALARM_DEB IOMUX_PAD(0x400, 0x6c, 4, 0x0000, 0, 0) +#define _MX51_PAD_EIM_D20__USBH2_DATA4 IOMUX_PAD(0x400, 0x6c, 2, 0x0000, 0, 0) +#define _MX51_PAD_EIM_D21__AUD4_RXD IOMUX_PAD(0x404, 0x70, 5, 0x08c4, 0, 0) +#define _MX51_PAD_EIM_D21__EIM_D21 IOMUX_PAD(0x404, 0x70, 0, 0x0000, 0, 0) +#define _MX51_PAD_EIM_D21__GPIO2_5 IOMUX_PAD(0x404, 0x70, 1, 0x0000, 0, 0) +#define _MX51_PAD_EIM_D21__SRTC_ALARM_DEB IOMUX_PAD(0x404, 0x70, 3, 0x0000, 0, 0) +#define _MX51_PAD_EIM_D21__USBH2_DATA5 IOMUX_PAD(0x404, 0x70, 2, 0x0000, 0, 0) +#define _MX51_PAD_EIM_D22__AUD4_TXC IOMUX_PAD(0x408, 0x74, 5, 0x08cc, 0, 0) +#define _MX51_PAD_EIM_D22__EIM_D22 IOMUX_PAD(0x408, 0x74, 0, 0x0000, 0, 0) +#define _MX51_PAD_EIM_D22__GPIO2_6 IOMUX_PAD(0x408, 0x74, 1, 0x0000, 0, 0) +#define _MX51_PAD_EIM_D22__USBH2_DATA6 IOMUX_PAD(0x408, 0x74, 2, 0x0000, 0, 0) +#define _MX51_PAD_EIM_D23__AUD4_TXFS IOMUX_PAD(0x40c, 0x78, 5, 0x08d0, 0, 0) +#define _MX51_PAD_EIM_D23__EIM_D23 IOMUX_PAD(0x40c, 0x78, 0, 0x0000, 0, 0) +#define _MX51_PAD_EIM_D23__GPIO2_7 IOMUX_PAD(0x40c, 0x78, 1, 0x0000, 0, 0) +#define _MX51_PAD_EIM_D23__SPDIF_OUT1 IOMUX_PAD(0x40c, 0x78, 4, 0x0000, 0, 0) +#define _MX51_PAD_EIM_D23__USBH2_DATA7 IOMUX_PAD(0x40c, 0x78, 2, 0x0000, 0, 0) +#define _MX51_PAD_EIM_D24__AUD6_RXFS IOMUX_PAD(0x410, 0x7c, 5, 0x08f8, 0, 0) +#define _MX51_PAD_EIM_D24__EIM_D24 IOMUX_PAD(0x410, 0x7c, 0, 0x0000, 0, 0) +#define _MX51_PAD_EIM_D24__GPIO2_8 IOMUX_PAD(0x410, 0x7c, 1, 0x0000, 0, 0) +#define _MX51_PAD_EIM_D24__I2C2_SDA IOMUX_PAD(0x410, 0x7c, 0x14, 0x09bc, 0, 0) +#define _MX51_PAD_EIM_D24__UART3_CTS IOMUX_PAD(0x410, 0x7c, 3, 0x0000, 0, 0) +#define _MX51_PAD_EIM_D24__USBOTG_DATA0 IOMUX_PAD(0x410, 0x7c, 2, 0x0000, 0, 0) +#define _MX51_PAD_EIM_D25__EIM_D25 IOMUX_PAD(0x414, 0x80, 0, 0x0000, 0, 0) +#define _MX51_PAD_EIM_D25__KEY_COL6 IOMUX_PAD(0x414, 0x80, 1, 0x09c8, 0, 0) +#define _MX51_PAD_EIM_D25__UART2_CTS IOMUX_PAD(0x414, 0x80, 4, 0x0000, 0, 0) +#define _MX51_PAD_EIM_D25__UART3_RXD IOMUX_PAD(0x414, 0x80, 3, 0x09f4, 0, 0) +#define _MX51_PAD_EIM_D25__USBOTG_DATA1 IOMUX_PAD(0x414, 0x80, 2, 0x0000, 0, 0) +#define _MX51_PAD_EIM_D26__EIM_D26 IOMUX_PAD(0x418, 0x84, 0, 0x0000, 0, 0) +#define _MX51_PAD_EIM_D26__KEY_COL7 IOMUX_PAD(0x418, 0x84, 1, 0x09cc, 0, 0) +#define _MX51_PAD_EIM_D26__UART2_RTS IOMUX_PAD(0x418, 0x84, 4, 0x09e8, 3, 0) +#define _MX51_PAD_EIM_D26__UART3_TXD IOMUX_PAD(0x418, 0x84, 3, 0x0000, 0, 0) +#define _MX51_PAD_EIM_D26__USBOTG_DATA2 IOMUX_PAD(0x418, 0x84, 2, 0x0000, 0, 0) +#define _MX51_PAD_EIM_D27__AUD6_RXC IOMUX_PAD(0x41c, 0x88, 5, 0x08f4, 0, 0) +#define _MX51_PAD_EIM_D27__EIM_D27 IOMUX_PAD(0x41c, 0x88, 0, 0x0000, 0, 0) +#define _MX51_PAD_EIM_D27__GPIO2_9 IOMUX_PAD(0x41c, 0x88, 1, 0x0000, 0, 0) +#define _MX51_PAD_EIM_D27__I2C2_SCL IOMUX_PAD(0x41c, 0x88, 0x14, 0x09b8, 0, 0) +#define _MX51_PAD_EIM_D27__UART3_RTS IOMUX_PAD(0x41c, 0x88, 3, 0x09f0, 3, 0) +#define _MX51_PAD_EIM_D27__USBOTG_DATA3 IOMUX_PAD(0x41c, 0x88, 2, 0x0000, 0, 0) +#define _MX51_PAD_EIM_D28__AUD6_TXD IOMUX_PAD(0x420, 0x8c, 5, 0x08f0, 0, 0) +#define _MX51_PAD_EIM_D28__EIM_D28 IOMUX_PAD(0x420, 0x8c, 0, 0x0000, 0, 0) +#define _MX51_PAD_EIM_D28__KEY_ROW4 IOMUX_PAD(0x420, 0x8c, 1, 0x09d0, 0, 0) +#define _MX51_PAD_EIM_D28__USBOTG_DATA4 IOMUX_PAD(0x420, 0x8c, 2, 0x0000, 0, 0) +#define _MX51_PAD_EIM_D29__AUD6_RXD IOMUX_PAD(0x424, 0x90, 5, 0x08ec, 0, 0) +#define _MX51_PAD_EIM_D29__EIM_D29 IOMUX_PAD(0x424, 0x90, 0, 0x0000, 0, 0) +#define _MX51_PAD_EIM_D29__KEY_ROW5 IOMUX_PAD(0x424, 0x90, 1, 0x09d4, 0, 0) +#define _MX51_PAD_EIM_D29__USBOTG_DATA5 IOMUX_PAD(0x424, 0x90, 2, 0x0000, 0, 0) +#define _MX51_PAD_EIM_D30__AUD6_TXC IOMUX_PAD(0x428, 0x94, 5, 0x08fc, 0, 0) +#define _MX51_PAD_EIM_D30__EIM_D30 IOMUX_PAD(0x428, 0x94, 0, 0x0000, 0, 0) +#define _MX51_PAD_EIM_D30__KEY_ROW6 IOMUX_PAD(0x428, 0x94, 1, 0x09d8, 0, 0) +#define _MX51_PAD_EIM_D30__USBOTG_DATA6 IOMUX_PAD(0x428, 0x94, 2, 0x0000, 0, 0) +#define _MX51_PAD_EIM_D31__AUD6_TXFS IOMUX_PAD(0x42c, 0x98, 5, 0x0900, 0, 0) +#define _MX51_PAD_EIM_D31__EIM_D31 IOMUX_PAD(0x42c, 0x98, 0, 0x0000, 0, 0) +#define _MX51_PAD_EIM_D31__KEY_ROW7 IOMUX_PAD(0x42c, 0x98, 1, 0x09dc, 0, 0) +#define _MX51_PAD_EIM_D31__USBOTG_DATA7 IOMUX_PAD(0x42c, 0x98, 2, 0x0000, 0, 0) +#define _MX51_PAD_EIM_A16__EIM_A16 IOMUX_PAD(0x430, 0x9c, 0, 0x0000, 0, 0) +#define _MX51_PAD_EIM_A16__GPIO2_10 IOMUX_PAD(0x430, 0x9c, 1, 0x0000, 0, 0) +#define _MX51_PAD_EIM_A16__OSC_FREQ_SEL0 IOMUX_PAD(0x430, 0x9c, 7, 0x0000, 0, 0) +#define _MX51_PAD_EIM_A17__EIM_A17 IOMUX_PAD(0x434, 0xa0, 0, 0x0000, 0, 0) +#define _MX51_PAD_EIM_A17__GPIO2_11 IOMUX_PAD(0x434, 0xa0, 1, 0x0000, 0, 0) +#define _MX51_PAD_EIM_A17__OSC_FREQ_SEL1 IOMUX_PAD(0x434, 0xa0, 7, 0x0000, 0, 0) +#define _MX51_PAD_EIM_A18__BOOT_LPB0 IOMUX_PAD(0x438, 0xa4, 7, 0x0000, 0, 0) +#define _MX51_PAD_EIM_A18__EIM_A18 IOMUX_PAD(0x438, 0xa4, 0, 0x0000, 0, 0) +#define _MX51_PAD_EIM_A18__GPIO2_12 IOMUX_PAD(0x438, 0xa4, 1, 0x0000, 0, 0) +#define _MX51_PAD_EIM_A19__BOOT_LPB1 IOMUX_PAD(0x43c, 0xa8, 7, 0x0000, 0, 0) +#define _MX51_PAD_EIM_A19__EIM_A19 IOMUX_PAD(0x43c, 0xa8, 0, 0x0000, 0, 0) +#define _MX51_PAD_EIM_A19__GPIO2_13 IOMUX_PAD(0x43c, 0xa8, 1, 0x0000, 0, 0) +#define _MX51_PAD_EIM_A20__BOOT_UART_SRC0 IOMUX_PAD(0x440, 0xac, 7, 0x0000, 0, 0) +#define _MX51_PAD_EIM_A20__EIM_A20 IOMUX_PAD(0x440, 0xac, 0, 0x0000, 0, 0) +#define _MX51_PAD_EIM_A20__GPIO2_14 IOMUX_PAD(0x440, 0xac, 1, 0x0000, 0, 0) +#define _MX51_PAD_EIM_A21__BOOT_UART_SRC1 IOMUX_PAD(0x444, 0xb0, 7, 0x0000, 0, 0) +#define _MX51_PAD_EIM_A21__EIM_A21 IOMUX_PAD(0x444, 0xb0, 0, 0x0000, 0, 0) +#define _MX51_PAD_EIM_A21__GPIO2_15 IOMUX_PAD(0x444, 0xb0, 1, 0x0000, 0, 0) +#define _MX51_PAD_EIM_A22__EIM_A22 IOMUX_PAD(0x448, 0xb4, 0, 0x0000, 0, 0) +#define _MX51_PAD_EIM_A22__GPIO2_16 IOMUX_PAD(0x448, 0xb4, 1, 0x0000, 0, 0) +#define _MX51_PAD_EIM_A23__BOOT_HPN_EN IOMUX_PAD(0x44c, 0xb8, 7, 0x0000, 0, 0) +#define _MX51_PAD_EIM_A23__EIM_A23 IOMUX_PAD(0x44c, 0xb8, 0, 0x0000, 0, 0) +#define _MX51_PAD_EIM_A23__GPIO2_17 IOMUX_PAD(0x44c, 0xb8, 1, 0x0000, 0, 0) +#define _MX51_PAD_EIM_A24__EIM_A24 IOMUX_PAD(0x450, 0xbc, 0, 0x0000, 0, 0) +#define _MX51_PAD_EIM_A24__GPIO2_18 IOMUX_PAD(0x450, 0xbc, 1, 0x0000, 0, 0) +#define _MX51_PAD_EIM_A24__USBH2_CLK IOMUX_PAD(0x450, 0xbc, 2, 0x0000, 0, 0) +#define _MX51_PAD_EIM_A25__DISP1_PIN4 IOMUX_PAD(0x454, 0xc0, 6, 0x0000, 0, 0) +#define _MX51_PAD_EIM_A25__EIM_A25 IOMUX_PAD(0x454, 0xc0, 0, 0x0000, 0, 0) +#define _MX51_PAD_EIM_A25__GPIO2_19 IOMUX_PAD(0x454, 0xc0, 1, 0x0000, 0, 0) +#define _MX51_PAD_EIM_A25__USBH2_DIR IOMUX_PAD(0x454, 0xc0, 2, 0x0000, 0, 0) +#define _MX51_PAD_EIM_A26__CSI1_DATA_EN IOMUX_PAD(0x458, 0xc4, 5, 0x09a0, 0, 0) +#define _MX51_PAD_EIM_A26__DISP2_EXT_CLK IOMUX_PAD(0x458, 0xc4, 6, 0x0908, 0, 0) +#define _MX51_PAD_EIM_A26__EIM_A26 IOMUX_PAD(0x458, 0xc4, 0, 0x0000, 0, 0) +#define _MX51_PAD_EIM_A26__GPIO2_20 IOMUX_PAD(0x458, 0xc4, 1, 0x0000, 0, 0) +#define _MX51_PAD_EIM_A26__USBH2_STP IOMUX_PAD(0x458, 0xc4, 2, 0x0000, 0, 0) +#define _MX51_PAD_EIM_A27__CSI2_DATA_EN IOMUX_PAD(0x45c, 0xc8, 5, 0x099c, 0, 0) +#define _MX51_PAD_EIM_A27__DISP1_PIN1 IOMUX_PAD(0x45c, 0xc8, 6, 0x09a4, 0, 0) +#define _MX51_PAD_EIM_A27__EIM_A27 IOMUX_PAD(0x45c, 0xc8, 0, 0x0000, 0, 0) +#define _MX51_PAD_EIM_A27__GPIO2_21 IOMUX_PAD(0x45c, 0xc8, 1, 0x0000, 0, 0) +#define _MX51_PAD_EIM_A27__USBH2_NXT IOMUX_PAD(0x45c, 0xc8, 2, 0x0000, 0, 0) +#define _MX51_PAD_EIM_EB0__EIM_EB0 IOMUX_PAD(0x460, 0xcc, 0, 0x0000, 0, 0) +#define _MX51_PAD_EIM_EB1__EIM_EB1 IOMUX_PAD(0x464, 0xd0, 0, 0x0000, 0, 0) +#define _MX51_PAD_EIM_EB2__AUD5_RXFS IOMUX_PAD(0x468, 0xd4, 6, 0x08e0, 0, 0) +#define _MX51_PAD_EIM_EB2__CSI1_D2 IOMUX_PAD(0x468, 0xd4, 5, 0x0000, 0, 0) +#define _MX51_PAD_EIM_EB2__EIM_EB2 IOMUX_PAD(0x468, 0xd4, 0, 0x0000, 0, 0) +#define _MX51_PAD_EIM_EB2__FEC_MDIO IOMUX_PAD(0x468, 0xd4, 3, 0x0954, 0, 0) +#define _MX51_PAD_EIM_EB2__GPIO2_22 IOMUX_PAD(0x468, 0xd4, 1, 0x0000, 0, 0) +#define _MX51_PAD_EIM_EB2__GPT_CMPOUT1 IOMUX_PAD(0x468, 0xd4, 7, 0x0000, 0, 0) +#define _MX51_PAD_EIM_EB3__AUD5_RXC IOMUX_PAD(0x46c, 0xd8, 6, 0x08dc, 0, 0) +#define _MX51_PAD_EIM_EB3__CSI1_D3 IOMUX_PAD(0x46c, 0xd8, 5, 0x0000, 0, 0) +#define _MX51_PAD_EIM_EB3__EIM_EB3 IOMUX_PAD(0x46c, 0xd8, 0, 0x0000, 0, 0) +#define _MX51_PAD_EIM_EB3__FEC_RDATA1 IOMUX_PAD(0x46c, 0xd8, 3, 0x095c, 0, 0) +#define _MX51_PAD_EIM_EB3__GPIO2_23 IOMUX_PAD(0x46c, 0xd8, 1, 0x0000, 0, 0) +#define _MX51_PAD_EIM_EB3__GPT_CMPOUT2 IOMUX_PAD(0x46c, 0xd8, 7, 0x0000, 0, 0) +#define _MX51_PAD_EIM_OE__EIM_OE IOMUX_PAD(0x470, 0xdc, 0, 0x0000, 0, 0) +#define _MX51_PAD_EIM_OE__GPIO2_24 IOMUX_PAD(0x470, 0xdc, 1, 0x0000, 0, 0) +#define _MX51_PAD_EIM_CS0__EIM_CS0 IOMUX_PAD(0x474, 0xe0, 0, 0x0000, 0, 0) +#define _MX51_PAD_EIM_CS0__GPIO2_25 IOMUX_PAD(0x474, 0xe0, 1, 0x0000, 0, 0) +#define _MX51_PAD_EIM_CS1__EIM_CS1 IOMUX_PAD(0x478, 0xe4, 0, 0x0000, 0, 0) +#define _MX51_PAD_EIM_CS1__GPIO2_26 IOMUX_PAD(0x478, 0xe4, 1, 0x0000, 0, 0) +#define _MX51_PAD_EIM_CS2__AUD5_TXD IOMUX_PAD(0x47c, 0xe8, 6, 0x08d8, 1, 0) +#define _MX51_PAD_EIM_CS2__CSI1_D4 IOMUX_PAD(0x47c, 0xe8, 5, 0x0000, 0, 0) +#define _MX51_PAD_EIM_CS2__EIM_CS2 IOMUX_PAD(0x47c, 0xe8, 0, 0x0000, 0, 0) +#define _MX51_PAD_EIM_CS2__FEC_RDATA2 IOMUX_PAD(0x47c, 0xe8, 3, 0x0960, 0, 0) +#define _MX51_PAD_EIM_CS2__GPIO2_27 IOMUX_PAD(0x47c, 0xe8, 1, 0x0000, 0, 0) +#define _MX51_PAD_EIM_CS2__USBOTG_STP IOMUX_PAD(0x47c, 0xe8, 2, 0x0000, 0, 0) +#define _MX51_PAD_EIM_CS3__AUD5_RXD IOMUX_PAD(0x480, 0xec, 6, 0x08d4, 1, 0) +#define _MX51_PAD_EIM_CS3__CSI1_D5 IOMUX_PAD(0x480, 0xec, 5, 0x0000, 0, 0) +#define _MX51_PAD_EIM_CS3__EIM_CS3 IOMUX_PAD(0x480, 0xec, 0, 0x0000, 0, 0) +#define _MX51_PAD_EIM_CS3__FEC_RDATA3 IOMUX_PAD(0x480, 0xec, 3, 0x0964, 0, 0) +#define _MX51_PAD_EIM_CS3__GPIO2_28 IOMUX_PAD(0x480, 0xec, 1, 0x0000, 0, 0) +#define _MX51_PAD_EIM_CS3__USBOTG_NXT IOMUX_PAD(0x480, 0xec, 2, 0x0000, 0, 0) +#define _MX51_PAD_EIM_CS4__AUD5_TXC IOMUX_PAD(0x484, 0xf0, 6, 0x08e4, 1, 0) +#define _MX51_PAD_EIM_CS4__CSI1_D6 IOMUX_PAD(0x484, 0xf0, 5, 0x0000, 0, 0) +#define _MX51_PAD_EIM_CS4__EIM_CS4 IOMUX_PAD(0x484, 0xf0, 0, 0x0000, 0, 0) +#define _MX51_PAD_EIM_CS4__FEC_RX_ER IOMUX_PAD(0x484, 0xf0, 3, 0x0970, 0, 0) +#define _MX51_PAD_EIM_CS4__GPIO2_29 IOMUX_PAD(0x484, 0xf0, 1, 0x0000, 0, 0) +#define _MX51_PAD_EIM_CS4__USBOTG_CLK IOMUX_PAD(0x484, 0xf0, 2, 0x0000, 0, 0) +#define _MX51_PAD_EIM_CS5__AUD5_TXFS IOMUX_PAD(0x488, 0xf4, 6, 0x08e8, 1, 0) +#define _MX51_PAD_EIM_CS5__CSI1_D7 IOMUX_PAD(0x488, 0xf4, 5, 0x0000, 0, 0) +#define _MX51_PAD_EIM_CS5__DISP1_EXT_CLK IOMUX_PAD(0x488, 0xf4, 4, 0x0904, 0, 0) +#define _MX51_PAD_EIM_CS5__EIM_CS5 IOMUX_PAD(0x488, 0xf4, 0, 0x0000, 0, 0) +#define _MX51_PAD_EIM_CS5__FEC_CRS IOMUX_PAD(0x488, 0xf4, 3, 0x0950, 0, 0) +#define _MX51_PAD_EIM_CS5__GPIO2_30 IOMUX_PAD(0x488, 0xf4, 1, 0x0000, 0, 0) +#define _MX51_PAD_EIM_CS5__USBOTG_DIR IOMUX_PAD(0x488, 0xf4, 2, 0x0000, 0, 0) +#define _MX51_PAD_EIM_DTACK__EIM_DTACK IOMUX_PAD(0x48c, 0xf8, 0, 0x0000, 0, 0) +#define _MX51_PAD_EIM_DTACK__GPIO2_31 IOMUX_PAD(0x48c, 0xf8, 1, 0x0000, 0, 0) +#define _MX51_PAD_EIM_LBA__EIM_LBA IOMUX_PAD(0x494, 0xfc, 0, 0x0000, 0, 0) +#define _MX51_PAD_EIM_LBA__GPIO3_1 IOMUX_PAD(0x494, 0xfc, 1, 0x0978, 0, 0) +#define _MX51_PAD_EIM_CRE__EIM_CRE IOMUX_PAD(0x4a0, 0x100, 0, 0x0000, 0, 0) +#define _MX51_PAD_EIM_CRE__GPIO3_2 IOMUX_PAD(0x4a0, 0x100, 1, 0x097c, 0, 0) +#define _MX51_PAD_DRAM_CS1__DRAM_CS1 IOMUX_PAD(0x4d0, 0x104, 0, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_WE_B__GPIO3_3 IOMUX_PAD(0x4e4, 0x108, 3, 0x0980, 0, 0) +#define _MX51_PAD_NANDF_WE_B__NANDF_WE_B IOMUX_PAD(0x4e4, 0x108, 0, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_WE_B__PATA_DIOW IOMUX_PAD(0x4e4, 0x108, 1, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_WE_B__SD3_DATA0 IOMUX_PAD(0x4e4, 0x108, 2, 0x093c, 0, 0) +#define _MX51_PAD_NANDF_RE_B__GPIO3_4 IOMUX_PAD(0x4e8, 0x10c, 3, 0x0984, 0, 0) +#define _MX51_PAD_NANDF_RE_B__NANDF_RE_B IOMUX_PAD(0x4e8, 0x10c, 0, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_RE_B__PATA_DIOR IOMUX_PAD(0x4e8, 0x10c, 1, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_RE_B__SD3_DATA1 IOMUX_PAD(0x4e8, 0x10c, 2, 0x0940, 0, 0) +#define _MX51_PAD_NANDF_ALE__GPIO3_5 IOMUX_PAD(0x4ec, 0x110, 3, 0x0988, 0, 0) +#define _MX51_PAD_NANDF_ALE__NANDF_ALE IOMUX_PAD(0x4ec, 0x110, 0, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_ALE__PATA_BUFFER_EN IOMUX_PAD(0x4ec, 0x110, 1, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_CLE__GPIO3_6 IOMUX_PAD(0x4f0, 0x114, 3, 0x098c, 0, 0) +#define _MX51_PAD_NANDF_CLE__NANDF_CLE IOMUX_PAD(0x4f0, 0x114, 0, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_CLE__PATA_RESET_B IOMUX_PAD(0x4f0, 0x114, 1, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_WP_B__GPIO3_7 IOMUX_PAD(0x4f4, 0x118, 3, 0x0990, 0, 0) +#define _MX51_PAD_NANDF_WP_B__NANDF_WP_B IOMUX_PAD(0x4f4, 0x118, 0, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_WP_B__PATA_DMACK IOMUX_PAD(0x4f4, 0x118, 1, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_WP_B__SD3_DATA2 IOMUX_PAD(0x4f4, 0x118, 2, 0x0944, 0, 0) +#define _MX51_PAD_NANDF_RB0__ECSPI2_SS1 IOMUX_PAD(0x4f8, 0x11c, 5, 0x0930, 0, 0) +#define _MX51_PAD_NANDF_RB0__GPIO3_8 IOMUX_PAD(0x4f8, 0x11c, 3, 0x0994, 0, 0) +#define _MX51_PAD_NANDF_RB0__NANDF_RB0 IOMUX_PAD(0x4f8, 0x11c, 0, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_RB0__PATA_DMARQ IOMUX_PAD(0x4f8, 0x11c, 1, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_RB0__SD3_DATA3 IOMUX_PAD(0x4f8, 0x11c, 2, 0x0948, 0, 0) +#define _MX51_PAD_NANDF_RB1__CSPI_MOSI IOMUX_PAD(0x4fc, 0x120, 6, 0x091c, 0, 0) +#define _MX51_PAD_NANDF_RB1__ECSPI2_RDY IOMUX_PAD(0x4fc, 0x120, 2, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_RB1__GPIO3_9 IOMUX_PAD(0x4fc, 0x120, 3, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_RB1__NANDF_RB1 IOMUX_PAD(0x4fc, 0x120, 0, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_RB1__PATA_IORDY IOMUX_PAD(0x4fc, 0x120, 1, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_RB1__SD4_CMD IOMUX_PAD(0x4fc, 0x120, 5, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_RB2__DISP2_WAIT IOMUX_PAD(0x500, 0x124, 5, 0x09a8, 0, 0) +#define _MX51_PAD_NANDF_RB2__ECSPI2_SCLK IOMUX_PAD(0x500, 0x124, 2, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_RB2__FEC_COL IOMUX_PAD(0x500, 0x124, 1, 0x094c, 0, 0) +#define _MX51_PAD_NANDF_RB2__GPIO3_10 IOMUX_PAD(0x500, 0x124, 3, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_RB2__NANDF_RB2 IOMUX_PAD(0x500, 0x124, 0, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_RB2__USBH3_H3_DP IOMUX_PAD(0x500, 0x124, 7, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_RB2__USBH3_NXT IOMUX_PAD(0x500, 0x124, 6, 0x0a20, 0, 0) +#define _MX51_PAD_NANDF_RB3__DISP1_WAIT IOMUX_PAD(0x504, 0x128, 5, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_RB3__ECSPI2_MISO IOMUX_PAD(0x504, 0x128, 2, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_RB3__FEC_RX_CLK IOMUX_PAD(0x504, 0x128, 1, 0x0968, 0, 0) +#define _MX51_PAD_NANDF_RB3__GPIO3_11 IOMUX_PAD(0x504, 0x128, 3, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_RB3__NANDF_RB3 IOMUX_PAD(0x504, 0x128, 0, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_RB3__USBH3_CLK IOMUX_PAD(0x504, 0x128, 6, 0x09f8, 0, 0) +#define _MX51_PAD_NANDF_RB3__USBH3_H3_DM IOMUX_PAD(0x504, 0x128, 7, 0x0000, 0, 0) +#define _MX51_PAD_GPIO_NAND__GPIO_NAND IOMUX_PAD(0x514, 0x12c, 0, 0x0998, 0, 0) +#define _MX51_PAD_GPIO_NAND__PATA_INTRQ IOMUX_PAD(0x514, 0x12c, 1, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_CS0__GPIO3_16 IOMUX_PAD(0x518, 0x130, 3, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_CS0__NANDF_CS0 IOMUX_PAD(0x518, 0x130, 0, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_CS1__GPIO3_17 IOMUX_PAD(0x51c, 0x134, 3, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_CS1__NANDF_CS1 IOMUX_PAD(0x51c, 0x134, 0, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_CS2__CSPI_SCLK IOMUX_PAD(0x520, 0x138, 6, 0x0914, 0, 0) +#define _MX51_PAD_NANDF_CS2__FEC_TX_ER IOMUX_PAD(0x520, 0x138, 2, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_CS2__GPIO3_18 IOMUX_PAD(0x520, 0x138, 3, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_CS2__NANDF_CS2 IOMUX_PAD(0x520, 0x138, 0, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_CS2__PATA_CS_0 IOMUX_PAD(0x520, 0x138, 1, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_CS2__SD4_CLK IOMUX_PAD(0x520, 0x138, 5, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_CS2__USBH3_H1_DP IOMUX_PAD(0x520, 0x138, 7, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_CS3__FEC_MDC IOMUX_PAD(0x524, 0x13c, 2, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_CS3__GPIO3_19 IOMUX_PAD(0x524, 0x13c, 3, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_CS3__NANDF_CS3 IOMUX_PAD(0x524, 0x13c, 0, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_CS3__PATA_CS_1 IOMUX_PAD(0x524, 0x13c, 1, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_CS3__SD4_DAT0 IOMUX_PAD(0x524, 0x13c, 5, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_CS3__USBH3_H1_DM IOMUX_PAD(0x524, 0x13c, 7, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_CS4__FEC_TDATA1 IOMUX_PAD(0x528, 0x140, 2, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_CS4__GPIO3_20 IOMUX_PAD(0x528, 0x140, 3, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_CS4__NANDF_CS4 IOMUX_PAD(0x528, 0x140, 0, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_CS4__PATA_DA_0 IOMUX_PAD(0x528, 0x140, 1, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_CS4__SD4_DAT1 IOMUX_PAD(0x528, 0x140, 5, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_CS4__USBH3_STP IOMUX_PAD(0x528, 0x140, 7, 0x0a24, 0, 0) +#define _MX51_PAD_NANDF_CS5__FEC_TDATA2 IOMUX_PAD(0x52c, 0x144, 2, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_CS5__GPIO3_21 IOMUX_PAD(0x52c, 0x144, 3, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_CS5__NANDF_CS5 IOMUX_PAD(0x52c, 0x144, 0, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_CS5__PATA_DA_1 IOMUX_PAD(0x52c, 0x144, 1, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_CS5__SD4_DAT2 IOMUX_PAD(0x52c, 0x144, 5, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_CS5__USBH3_DIR IOMUX_PAD(0x52c, 0x144, 7, 0x0a1c, 0, 0) +#define _MX51_PAD_NANDF_CS6__CSPI_SS3 IOMUX_PAD(0x530, 0x148, 7, 0x0928, 0, 0) +#define _MX51_PAD_NANDF_CS6__FEC_TDATA3 IOMUX_PAD(0x530, 0x148, 2, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_CS6__GPIO3_22 IOMUX_PAD(0x530, 0x148, 3, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_CS6__NANDF_CS6 IOMUX_PAD(0x530, 0x148, 0, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_CS6__PATA_DA_2 IOMUX_PAD(0x530, 0x148, 1, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_CS6__SD4_DAT3 IOMUX_PAD(0x530, 0x148, 5, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_CS7__FEC_TX_EN IOMUX_PAD(0x534, 0x14c, 1, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_CS7__GPIO3_23 IOMUX_PAD(0x534, 0x14c, 3, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_CS7__NANDF_CS7 IOMUX_PAD(0x534, 0x14c, 0, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_CS7__SD3_CLK IOMUX_PAD(0x534, 0x14c, 5, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_RDY_INT__ECSPI2_SS0 IOMUX_PAD(0x538, 0x150, 2, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK IOMUX_PAD(0x538, 0x150, 1, 0x0974, 0, 0) +#define _MX51_PAD_NANDF_RDY_INT__GPIO3_24 IOMUX_PAD(0x538, 0x150, 3, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_RDY_INT__NANDF_RDY_INT IOMUX_PAD(0x538, 0x150, 0, 0x0938, 0, 0) +#define _MX51_PAD_NANDF_RDY_INT__SD3_CMD IOMUX_PAD(0x538, 0x150, 5, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_D15__ECSPI2_MOSI IOMUX_PAD(0x53c, 0x154, 2, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_D15__GPIO3_25 IOMUX_PAD(0x53c, 0x154, 3, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_D15__NANDF_D15 IOMUX_PAD(0x53c, 0x154, 0, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_D15__PATA_DATA15 IOMUX_PAD(0x53c, 0x154, 1, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_D15__SD3_DAT7 IOMUX_PAD(0x53c, 0x154, 5, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_D14__ECSPI2_SS3 IOMUX_PAD(0x540, 0x158, 2, 0x0934, 0, 0) +#define _MX51_PAD_NANDF_D14__GPIO3_26 IOMUX_PAD(0x540, 0x158, 3, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_D14__NANDF_D14 IOMUX_PAD(0x540, 0x158, 0, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_D14__PATA_DATA14 IOMUX_PAD(0x540, 0x158, 1, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_D14__SD3_DAT6 IOMUX_PAD(0x540, 0x158, 5, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_D13__ECSPI2_SS2 IOMUX_PAD(0x544, 0x15c, 2, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_D13__GPIO3_27 IOMUX_PAD(0x544, 0x15c, 3, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_D13__NANDF_D13 IOMUX_PAD(0x544, 0x15c, 0, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_D13__PATA_DATA13 IOMUX_PAD(0x544, 0x15c, 1, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_D13__SD3_DAT5 IOMUX_PAD(0x544, 0x15c, 5, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_D12__ECSPI2_SS1 IOMUX_PAD(0x548, 0x160, 2, 0x0930, 1, 0) +#define _MX51_PAD_NANDF_D12__GPIO3_28 IOMUX_PAD(0x548, 0x160, 3, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_D12__NANDF_D12 IOMUX_PAD(0x548, 0x160, 0, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_D12__PATA_DATA12 IOMUX_PAD(0x548, 0x160, 1, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_D12__SD3_DAT4 IOMUX_PAD(0x548, 0x160, 5, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_D11__FEC_RX_DV IOMUX_PAD(0x54c, 0x164, 2, 0x096c, 0, 0) +#define _MX51_PAD_NANDF_D11__GPIO3_29 IOMUX_PAD(0x54c, 0x164, 3, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_D11__NANDF_D11 IOMUX_PAD(0x54c, 0x164, 0, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_D11__PATA_DATA11 IOMUX_PAD(0x54c, 0x164, 1, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_D11__SD3_DATA3 IOMUX_PAD(0x54c, 0x164, 5, 0x0948, 1, 0) +#define _MX51_PAD_NANDF_D10__GPIO3_30 IOMUX_PAD(0x550, 0x168, 3, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_D10__NANDF_D10 IOMUX_PAD(0x550, 0x168, 0, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_D10__PATA_DATA10 IOMUX_PAD(0x550, 0x168, 1, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_D10__SD3_DATA2 IOMUX_PAD(0x550, 0x168, 5, 0x0944, 1, 0) +#define _MX51_PAD_NANDF_D9__FEC_RDATA0 IOMUX_PAD(0x554, 0x16c, 0x12, 0x0958, 0, 0) +#define _MX51_PAD_NANDF_D9__GPIO3_31 IOMUX_PAD(0x554, 0x16c, 3, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_D9__NANDF_D9 IOMUX_PAD(0x554, 0x16c, 0, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_D9__PATA_DATA9 IOMUX_PAD(0x554, 0x16c, 1, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_D9__SD3_DATA1 IOMUX_PAD(0x554, 0x16c, 5, 0x0940, 1, 0) +#define _MX51_PAD_NANDF_D8__FEC_TDATA0 IOMUX_PAD(0x558, 0x170, 2, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_D8__GPIO4_0 IOMUX_PAD(0x558, 0x170, 3, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_D8__NANDF_D8 IOMUX_PAD(0x558, 0x170, 0, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_D8__PATA_DATA8 IOMUX_PAD(0x558, 0x170, 1, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_D8__SD3_DATA0 IOMUX_PAD(0x558, 0x170, 5, 0x093c, 1, 0) +#define _MX51_PAD_NANDF_D7__GPIO4_1 IOMUX_PAD(0x55c, 0x174, 3, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_D7__NANDF_D7 IOMUX_PAD(0x55c, 0x174, 0, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_D7__PATA_DATA7 IOMUX_PAD(0x55c, 0x174, 1, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_D7__USBH3_DATA0 IOMUX_PAD(0x55c, 0x174, 5, 0x09fc, 0, 0) +#define _MX51_PAD_NANDF_D6__GPIO4_2 IOMUX_PAD(0x560, 0x178, 3, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_D6__NANDF_D6 IOMUX_PAD(0x560, 0x178, 0, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_D6__PATA_DATA6 IOMUX_PAD(0x560, 0x178, 1, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_D6__SD4_LCTL IOMUX_PAD(0x560, 0x178, 2, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_D6__USBH3_DATA1 IOMUX_PAD(0x560, 0x178, 5, 0x0a00, 0, 0) +#define _MX51_PAD_NANDF_D5__GPIO4_3 IOMUX_PAD(0x564, 0x17c, 3, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_D5__NANDF_D5 IOMUX_PAD(0x564, 0x17c, 0, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_D5__PATA_DATA5 IOMUX_PAD(0x564, 0x17c, 1, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_D5__SD4_WP IOMUX_PAD(0x564, 0x17c, 2, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_D5__USBH3_DATA2 IOMUX_PAD(0x564, 0x17c, 5, 0x0a04, 0, 0) +#define _MX51_PAD_NANDF_D4__GPIO4_4 IOMUX_PAD(0x568, 0x180, 3, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_D4__NANDF_D4 IOMUX_PAD(0x568, 0x180, 0, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_D4__PATA_DATA4 IOMUX_PAD(0x568, 0x180, 1, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_D4__SD4_CD IOMUX_PAD(0x568, 0x180, 2, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_D4__USBH3_DATA3 IOMUX_PAD(0x568, 0x180, 5, 0x0a08, 0, 0) +#define _MX51_PAD_NANDF_D3__GPIO4_5 IOMUX_PAD(0x56c, 0x184, 3, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_D3__NANDF_D3 IOMUX_PAD(0x56c, 0x184, 0, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_D3__PATA_DATA3 IOMUX_PAD(0x56c, 0x184, 1, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_D3__SD4_DAT4 IOMUX_PAD(0x56c, 0x184, 2, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_D3__USBH3_DATA4 IOMUX_PAD(0x56c, 0x184, 5, 0x0a0c, 0, 0) +#define _MX51_PAD_NANDF_D2__GPIO4_6 IOMUX_PAD(0x570, 0x188, 3, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_D2__NANDF_D2 IOMUX_PAD(0x570, 0x188, 0, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_D2__PATA_DATA2 IOMUX_PAD(0x570, 0x188, 1, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_D2__SD4_DAT5 IOMUX_PAD(0x570, 0x188, 2, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_D2__USBH3_DATA5 IOMUX_PAD(0x570, 0x188, 5, 0x0a10, 0, 0) +#define _MX51_PAD_NANDF_D1__GPIO4_7 IOMUX_PAD(0x574, 0x18c, 3, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_D1__NANDF_D1 IOMUX_PAD(0x574, 0x18c, 0, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_D1__PATA_DATA1 IOMUX_PAD(0x574, 0x18c, 1, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_D1__SD4_DAT6 IOMUX_PAD(0x574, 0x18c, 2, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_D1__USBH3_DATA6 IOMUX_PAD(0x574, 0x18c, 5, 0x0a14, 0, 0) +#define _MX51_PAD_NANDF_D0__GPIO4_8 IOMUX_PAD(0x578, 0x190, 3, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_D0__NANDF_D0 IOMUX_PAD(0x578, 0x190, 0, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_D0__PATA_DATA0 IOMUX_PAD(0x578, 0x190, 1, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_D0__SD4_DAT7 IOMUX_PAD(0x578, 0x190, 2, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_D0__USBH3_DATA7 IOMUX_PAD(0x578, 0x190, 5, 0x0a18, 0, 0) +#define _MX51_PAD_CSI1_D8__CSI1_D8 IOMUX_PAD(0x57c, 0x194, 0, 0x0000, 0, 0) +#define _MX51_PAD_CSI1_D8__GPIO3_12 IOMUX_PAD(0x57c, 0x194, 3, 0x0998, 1, 0) +#define _MX51_PAD_CSI1_D9__CSI1_D9 IOMUX_PAD(0x580, 0x198, 0, 0x0000, 0, 0) +#define _MX51_PAD_CSI1_D9__GPIO3_13 IOMUX_PAD(0x580, 0x198, 3, 0x0000, 0, 0) +#define _MX51_PAD_CSI1_D10__CSI1_D10 IOMUX_PAD(0x584, 0x19c, 0, 0x0000, 0, 0) +#define _MX51_PAD_CSI1_D11__CSI1_D11 IOMUX_PAD(0x588, 0x1a0, 0, 0x0000, 0, 0) +#define _MX51_PAD_CSI1_D12__CSI1_D12 IOMUX_PAD(0x58c, 0x1a4, 0, 0x0000, 0, 0) +#define _MX51_PAD_CSI1_D13__CSI1_D13 IOMUX_PAD(0x590, 0x1a8, 0, 0x0000, 0, 0) +#define _MX51_PAD_CSI1_D14__CSI1_D14 IOMUX_PAD(0x594, 0x1ac, 0, 0x0000, 0, 0) +#define _MX51_PAD_CSI1_D15__CSI1_D15 IOMUX_PAD(0x598, 0x1b0, 0, 0x0000, 0, 0) +#define _MX51_PAD_CSI1_D16__CSI1_D16 IOMUX_PAD(0x59c, 0x1b4, 0, 0x0000, 0, 0) +#define _MX51_PAD_CSI1_D17__CSI1_D17 IOMUX_PAD(0x5a0, 0x1b8, 0, 0x0000, 0, 0) +#define _MX51_PAD_CSI1_D18__CSI1_D18 IOMUX_PAD(0x5a4, 0x1bc, 0, 0x0000, 0, 0) +#define _MX51_PAD_CSI1_D19__CSI1_D19 IOMUX_PAD(0x5a8, 0x1c0, 0, 0x0000, 0, 0) +#define _MX51_PAD_CSI1_VSYNC__CSI1_VSYNC IOMUX_PAD(0x5ac, 0x1c4, 0, 0x0000, 0, 0) +#define _MX51_PAD_CSI1_VSYNC__GPIO3_14 IOMUX_PAD(0x5ac, 0x1c4, 3, 0x0000, 0, 0) +#define _MX51_PAD_CSI1_HSYNC__CSI1_HSYNC IOMUX_PAD(0x5b0, 0x1c8, 0, 0x0000, 0, 0) +#define _MX51_PAD_CSI1_HSYNC__GPIO3_15 IOMUX_PAD(0x5b0, 0x1c8, 3, 0x0000, 0, 0) +#define _MX51_PAD_CSI1_PIXCLK__CSI1_PIXCLK IOMUX_PAD(0x5b4, 0x000, 0, 0x0000, 0, 0) +#define _MX51_PAD_CSI1_MCLK__CSI1_MCLK IOMUX_PAD(0x5b8, 0x000, 0, 0x0000, 0, 0) +#define _MX51_PAD_CSI2_D12__CSI2_D12 IOMUX_PAD(0x5bc, 0x1cc, 0, 0x0000, 0, 0) +#define _MX51_PAD_CSI2_D12__GPIO4_9 IOMUX_PAD(0x5bc, 0x1cc, 3, 0x0000, 0, 0) +#define _MX51_PAD_CSI2_D13__CSI2_D13 IOMUX_PAD(0x5c0, 0x1d0, 0, 0x0000, 0, 0) +#define _MX51_PAD_CSI2_D13__GPIO4_10 IOMUX_PAD(0x5c0, 0x1d0, 3, 0x0000, 0, 0) +#define _MX51_PAD_CSI2_D14__CSI2_D14 IOMUX_PAD(0x5c4, 0x1d4, 0, 0x0000, 0, 0) +#define _MX51_PAD_CSI2_D15__CSI2_D15 IOMUX_PAD(0x5c8, 0x1d8, 0, 0x0000, 0, 0) +#define _MX51_PAD_CSI2_D16__CSI2_D16 IOMUX_PAD(0x5cc, 0x1dc, 0, 0x0000, 0, 0) +#define _MX51_PAD_CSI2_D17__CSI2_D17 IOMUX_PAD(0x5d0, 0x1e0, 0, 0x0000, 0, 0) +#define _MX51_PAD_CSI2_D18__CSI2_D18 IOMUX_PAD(0x5d4, 0x1e4, 0, 0x0000, 0, 0) +#define _MX51_PAD_CSI2_D18__GPIO4_11 IOMUX_PAD(0x5d4, 0x1e4, 3, 0x0000, 0, 0) +#define _MX51_PAD_CSI2_D19__CSI2_D19 IOMUX_PAD(0x5d8, 0x1e8, 0, 0x0000, 0, 0) +#define _MX51_PAD_CSI2_D19__GPIO4_12 IOMUX_PAD(0x5d8, 0x1e8, 3, 0x0000, 0, 0) +#define _MX51_PAD_CSI2_VSYNC__CSI2_VSYNC IOMUX_PAD(0x5dc, 0x1ec, 0, 0x0000, 0, 0) +#define _MX51_PAD_CSI2_VSYNC__GPIO4_13 IOMUX_PAD(0x5dc, 0x1ec, 3, 0x0000, 0, 0) +#define _MX51_PAD_CSI2_HSYNC__CSI2_HSYNC IOMUX_PAD(0x5e0, 0x1f0, 0, 0x0000, 0, 0) +#define _MX51_PAD_CSI2_HSYNC__GPIO4_14 IOMUX_PAD(0x5e0, 0x1f0, 3, 0x0000, 0, 0) +#define _MX51_PAD_CSI2_PIXCLK__CSI2_PIXCLK IOMUX_PAD(0x5e4, 0x1f4, 0, 0x0000, 0, 0) +#define _MX51_PAD_CSI2_PIXCLK__GPIO4_15 IOMUX_PAD(0x5e4, 0x1f4, 3, 0x0000, 0, 0) +#define _MX51_PAD_I2C1_CLK__GPIO4_16 IOMUX_PAD(0x5e8, 0x1f8, 3, 0x0000, 0, 0) +#define _MX51_PAD_I2C1_CLK__I2C1_CLK IOMUX_PAD(0x5e8, 0x1f8, 0x10, 0x0000, 0, 0) +#define _MX51_PAD_I2C1_DAT__GPIO4_17 IOMUX_PAD(0x5ec, 0x1fc, 3, 0x0000, 0, 0) +#define _MX51_PAD_I2C1_DAT__I2C1_DAT IOMUX_PAD(0x5ec, 0x1fc, 0x10, 0x0000, 0, 0) +#define _MX51_PAD_AUD3_BB_TXD__AUD3_TXD IOMUX_PAD(0x5f0, 0x200, 0, 0x0000, 0, 0) +#define _MX51_PAD_AUD3_BB_TXD__GPIO4_18 IOMUX_PAD(0x5f0, 0x200, 3, 0x0000, 0, 0) +#define _MX51_PAD_AUD3_BB_RXD__AUD3_RXD IOMUX_PAD(0x5f4, 0x204, 0, 0x0000, 0, 0) +#define _MX51_PAD_AUD3_BB_RXD__GPIO4_19 IOMUX_PAD(0x5f4, 0x204, 3, 0x0000, 0, 0) +#define _MX51_PAD_AUD3_BB_RXD__UART3_RXD IOMUX_PAD(0x5f4, 0x204, 1, 0x09f4, 2, 0) +#define _MX51_PAD_AUD3_BB_CK__AUD3_TXC IOMUX_PAD(0x5f8, 0x208, 0, 0x0000, 0, 0) +#define _MX51_PAD_AUD3_BB_CK__GPIO4_20 IOMUX_PAD(0x5f8, 0x208, 3, 0x0000, 0, 0) +#define _MX51_PAD_AUD3_BB_FS__AUD3_TXFS IOMUX_PAD(0x5fc, 0x20c, 0, 0x0000, 0, 0) +#define _MX51_PAD_AUD3_BB_FS__GPIO4_21 IOMUX_PAD(0x5fc, 0x20c, 3, 0x0000, 0, 0) +#define _MX51_PAD_AUD3_BB_FS__UART3_TXD IOMUX_PAD(0x5fc, 0x20c, 1, 0x0000, 0, 0) +#define _MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI IOMUX_PAD(0x600, 0x210, 0, 0x0000, 0, 0) +#define _MX51_PAD_CSPI1_MOSI__GPIO4_22 IOMUX_PAD(0x600, 0x210, 3, 0x0000, 0, 0) +#define _MX51_PAD_CSPI1_MOSI__I2C1_SDA IOMUX_PAD(0x600, 0x210, 0x11, 0x09b4, 1, 0) +#define _MX51_PAD_CSPI1_MISO__AUD4_RXD IOMUX_PAD(0x604, 0x214, 1, 0x08c4, 1, 0) +#define _MX51_PAD_CSPI1_MISO__ECSPI1_MISO IOMUX_PAD(0x604, 0x214, 0, 0x0000, 0, 0) +#define _MX51_PAD_CSPI1_MISO__GPIO4_23 IOMUX_PAD(0x604, 0x214, 3, 0x0000, 0, 0) +#define _MX51_PAD_CSPI1_SS0__AUD4_TXC IOMUX_PAD(0x608, 0x218, 1, 0x08cc, 1, 0) +#define _MX51_PAD_CSPI1_SS0__ECSPI1_SS0 IOMUX_PAD(0x608, 0x218, 0, 0x0000, 0, 0) +#define _MX51_PAD_CSPI1_SS0__GPIO4_24 IOMUX_PAD(0x608, 0x218, 3, 0x0000, 0, 0) +#define _MX51_PAD_CSPI1_SS1__AUD4_TXD IOMUX_PAD(0x60c, 0x21c, 1, 0x08c8, 1, 0) +#define _MX51_PAD_CSPI1_SS1__ECSPI1_SS1 IOMUX_PAD(0x60c, 0x21c, 0, 0x0000, 0, 0) +#define _MX51_PAD_CSPI1_SS1__GPIO4_25 IOMUX_PAD(0x60c, 0x21c, 3, 0x0000, 0, 0) +#define _MX51_PAD_CSPI1_RDY__AUD4_TXFS IOMUX_PAD(0x610, 0x220, 1, 0x08d0, 1, 0) +#define _MX51_PAD_CSPI1_RDY__ECSPI1_RDY IOMUX_PAD(0x610, 0x220, 0, 0x0000, 0, 0) +#define _MX51_PAD_CSPI1_RDY__GPIO4_26 IOMUX_PAD(0x610, 0x220, 3, 0x0000, 0, 0) +#define _MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK IOMUX_PAD(0x614, 0x224, 0, 0x0000, 0, 0) +#define _MX51_PAD_CSPI1_SCLK__GPIO4_27 IOMUX_PAD(0x614, 0x224, 3, 0x0000, 0, 0) +#define _MX51_PAD_CSPI1_SCLK__I2C1_SCL IOMUX_PAD(0x614, 0x224, 0x11, 0x09b0, 1, 0) +#define _MX51_PAD_UART1_RXD__GPIO4_28 IOMUX_PAD(0x618, 0x228, 3, 0x0000, 0, 0) +#define _MX51_PAD_UART1_RXD__UART1_RXD IOMUX_PAD(0x618, 0x228, 0, 0x09e4, 0, 0) +#define _MX51_PAD_UART1_TXD__GPIO4_29 IOMUX_PAD(0x61c, 0x22c, 3, 0x0000, 0, 0) +#define _MX51_PAD_UART1_TXD__PWM2_PWMO IOMUX_PAD(0x61c, 0x22c, 1, 0x0000, 0, 0) +#define _MX51_PAD_UART1_TXD__UART1_TXD IOMUX_PAD(0x61c, 0x22c, 0, 0x0000, 0, 0) +#define _MX51_PAD_UART1_RTS__GPIO4_30 IOMUX_PAD(0x620, 0x230, 3, 0x0000, 0, 0) +#define _MX51_PAD_UART1_RTS__UART1_RTS IOMUX_PAD(0x620, 0x230, 0, 0x09e0, 0, 0) +#define _MX51_PAD_UART1_CTS__GPIO4_31 IOMUX_PAD(0x624, 0x234, 3, 0x0000, 0, 0) +#define _MX51_PAD_UART1_CTS__UART1_CTS IOMUX_PAD(0x624, 0x234, 0, 0x0000, 0, 0) +#define _MX51_PAD_UART2_RXD__FIRI_TXD IOMUX_PAD(0x628, 0x238, 1, 0x0000, 0, 0) +#define _MX51_PAD_UART2_RXD__GPIO1_20 IOMUX_PAD(0x628, 0x238, 3, 0x0000, 0, 0) +#define _MX51_PAD_UART2_RXD__UART2_RXD IOMUX_PAD(0x628, 0x238, 0, 0x09ec, 2, 0) +#define _MX51_PAD_UART2_TXD__FIRI_RXD IOMUX_PAD(0x62c, 0x23c, 1, 0x0000, 0, 0) +#define _MX51_PAD_UART2_TXD__GPIO1_21 IOMUX_PAD(0x62c, 0x23c, 3, 0x0000, 0, 0) +#define _MX51_PAD_UART2_TXD__UART2_TXD IOMUX_PAD(0x62c, 0x23c, 0, 0x09ec, 3, 0) +#define _MX51_PAD_UART3_RXD__CSI1_D0 IOMUX_PAD(0x630, 0x240, 2, 0x0000, 0, 0) +#define _MX51_PAD_UART3_RXD__GPIO1_22 IOMUX_PAD(0x630, 0x240, 3, 0x0000, 0, 0) +#define _MX51_PAD_UART3_RXD__UART1_DTR IOMUX_PAD(0x630, 0x240, 0, 0x0000, 0, 0) +#define _MX51_PAD_UART3_RXD__UART3_RXD IOMUX_PAD(0x630, 0x240, 1, 0x09f4, 4, 0) +#define _MX51_PAD_UART3_TXD__CSI1_D1 IOMUX_PAD(0x634, 0x244, 2, 0x0000, 0, 0) +#define _MX51_PAD_UART3_TXD__GPIO1_23 IOMUX_PAD(0x634, 0x244, 3, 0x0000, 0, 0) +#define _MX51_PAD_UART3_TXD__UART1_DSR IOMUX_PAD(0x634, 0x244, 0, 0x0000, 0, 0) +#define _MX51_PAD_UART3_TXD__UART3_TXD IOMUX_PAD(0x634, 0x244, 1, 0x0000, 0, 0) +#define _MX51_PAD_OWIRE_LINE__GPIO1_24 IOMUX_PAD(0x638, 0x248, 3, 0x0000, 0, 0) +#define _MX51_PAD_OWIRE_LINE__OWIRE_LINE IOMUX_PAD(0x638, 0x248, 0, 0x0000, 0, 0) +#define _MX51_PAD_OWIRE_LINE__SPDIF_OUT IOMUX_PAD(0x638, 0x248, 6, 0x0000, 0, 0) +#define _MX51_PAD_KEY_ROW0__KEY_ROW0 IOMUX_PAD(0x63c, 0x24c, 0, 0x0000, 0, 0) +#define _MX51_PAD_KEY_ROW1__KEY_ROW1 IOMUX_PAD(0x640, 0x250, 0, 0x0000, 0, 0) +#define _MX51_PAD_KEY_ROW2__KEY_ROW2 IOMUX_PAD(0x644, 0x254, 0, 0x0000, 0, 0) +#define _MX51_PAD_KEY_ROW3__KEY_ROW3 IOMUX_PAD(0x648, 0x258, 0, 0x0000, 0, 0) +#define _MX51_PAD_KEY_COL0__KEY_COL0 IOMUX_PAD(0x64c, 0x25c, 0, 0x0000, 0, 0) +#define _MX51_PAD_KEY_COL0__PLL1_BYP IOMUX_PAD(0x64c, 0x25c, 7, 0x090c, 0, 0) +#define _MX51_PAD_KEY_COL1__KEY_COL1 IOMUX_PAD(0x650, 0x260, 0, 0x0000, 0, 0) +#define _MX51_PAD_KEY_COL1__PLL2_BYP IOMUX_PAD(0x650, 0x260, 7, 0x0910, 0, 0) +#define _MX51_PAD_KEY_COL2__KEY_COL2 IOMUX_PAD(0x654, 0x264, 0, 0x0000, 0, 0) +#define _MX51_PAD_KEY_COL2__PLL3_BYP IOMUX_PAD(0x654, 0x264, 7, 0x0000, 0, 0) +#define _MX51_PAD_KEY_COL3__KEY_COL3 IOMUX_PAD(0x658, 0x268, 0, 0x0000, 0, 0) +#define _MX51_PAD_KEY_COL4__I2C2_SCL IOMUX_PAD(0x65c, 0x26c, 0x13, 0x09b8, 1, 0) +#define _MX51_PAD_KEY_COL4__KEY_COL4 IOMUX_PAD(0x65c, 0x26c, 0, 0x0000, 0, 0) +#define _MX51_PAD_KEY_COL4__SPDIF_OUT1 IOMUX_PAD(0x65c, 0x26c, 6, 0x0000, 0, 0) +#define _MX51_PAD_KEY_COL4__UART1_RI IOMUX_PAD(0x65c, 0x26c, 1, 0x0000, 0, 0) +#define _MX51_PAD_KEY_COL4__UART3_RTS IOMUX_PAD(0x65c, 0x26c, 2, 0x09f0, 4, 0) +#define _MX51_PAD_KEY_COL5__I2C2_SDA IOMUX_PAD(0x660, 0x270, 0x13, 0x09bc, 1, 0) +#define _MX51_PAD_KEY_COL5__KEY_COL5 IOMUX_PAD(0x660, 0x270, 0, 0x0000, 0, 0) +#define _MX51_PAD_KEY_COL5__UART1_DCD IOMUX_PAD(0x660, 0x270, 1, 0x0000, 0, 0) +#define _MX51_PAD_KEY_COL5__UART3_CTS IOMUX_PAD(0x660, 0x270, 2, 0x0000, 0, 0) +#define _MX51_PAD_USBH1_CLK__CSPI_SCLK IOMUX_PAD(0x678, 0x278, 1, 0x0914, 1, 0) +#define _MX51_PAD_USBH1_CLK__GPIO1_25 IOMUX_PAD(0x678, 0x278, 2, 0x0000, 0, 0) +#define _MX51_PAD_USBH1_CLK__I2C2_SCL IOMUX_PAD(0x678, 0x278, 0x15, 0x09b8, 2, 0) +#define _MX51_PAD_USBH1_CLK__USBH1_CLK IOMUX_PAD(0x678, 0x278, 0, 0x0000, 0, 0) +#define _MX51_PAD_USBH1_DIR__CSPI_MOSI IOMUX_PAD(0x67c, 0x27c, 1, 0x091c, 1, 0) +#define _MX51_PAD_USBH1_DIR__GPIO1_26 IOMUX_PAD(0x67c, 0x27c, 2, 0x0000, 0, 0) +#define _MX51_PAD_USBH1_DIR__I2C2_SDA IOMUX_PAD(0x67c, 0x27c, 0x15, 0x09bc, 2, 0) +#define _MX51_PAD_USBH1_DIR__USBH1_DIR IOMUX_PAD(0x67c, 0x27c, 0, 0x0000, 0, 0) +#define _MX51_PAD_USBH1_STP__CSPI_RDY IOMUX_PAD(0x680, 0x280, 1, 0x0000, 0, 0) +#define _MX51_PAD_USBH1_STP__GPIO1_27 IOMUX_PAD(0x680, 0x280, 2, 0x0000, 0, 0) +#define _MX51_PAD_USBH1_STP__UART3_RXD IOMUX_PAD(0x680, 0x280, 5, 0x09f4, 6, 0) +#define _MX51_PAD_USBH1_STP__USBH1_STP IOMUX_PAD(0x680, 0x280, 0, 0x0000, 0, 0) +#define _MX51_PAD_USBH1_NXT__CSPI_MISO IOMUX_PAD(0x684, 0x284, 1, 0x0918, 0, 0) +#define _MX51_PAD_USBH1_NXT__GPIO1_28 IOMUX_PAD(0x684, 0x284, 2, 0x0000, 0, 0) +#define _MX51_PAD_USBH1_NXT__UART3_TXD IOMUX_PAD(0x684, 0x284, 5, 0x0000, 0, 0) +#define _MX51_PAD_USBH1_NXT__USBH1_NXT IOMUX_PAD(0x684, 0x284, 0, 0x0000, 0, 0) +#define _MX51_PAD_USBH1_DATA0__GPIO1_11 IOMUX_PAD(0x688, 0x288, 2, 0x0000, 0, 0) +#define _MX51_PAD_USBH1_DATA0__UART2_CTS IOMUX_PAD(0x688, 0x288, 1, 0x0000, 0, 0) +#define _MX51_PAD_USBH1_DATA0__USBH1_DATA0 IOMUX_PAD(0x688, 0x288, 0, 0x0000, 0, 0) +#define _MX51_PAD_USBH1_DATA1__GPIO1_12 IOMUX_PAD(0x68c, 0x28c, 2, 0x0000, 0, 0) +#define _MX51_PAD_USBH1_DATA1__UART2_RXD IOMUX_PAD(0x68c, 0x28c, 1, 0x09ec, 4, 0) +#define _MX51_PAD_USBH1_DATA1__USBH1_DATA1 IOMUX_PAD(0x68c, 0x28c, 0, 0x0000, 0, 0) +#define _MX51_PAD_USBH1_DATA2__GPIO1_13 IOMUX_PAD(0x690, 0x290, 2, 0x0000, 0, 0) +#define _MX51_PAD_USBH1_DATA2__UART2_TXD IOMUX_PAD(0x690, 0x290, 1, 0x09ec, 5, 0) +#define _MX51_PAD_USBH1_DATA2__USBH1_DATA2 IOMUX_PAD(0x690, 0x290, 0, 0x0000, 0, 0) +#define _MX51_PAD_USBH1_DATA3__GPIO1_14 IOMUX_PAD(0x694, 0x294, 2, 0x0000, 0, 0) +#define _MX51_PAD_USBH1_DATA3__UART2_RTS IOMUX_PAD(0x694, 0x294, 1, 0x09e8, 5, 0) +#define _MX51_PAD_USBH1_DATA3__USBH1_DATA3 IOMUX_PAD(0x694, 0x294, 0, 0x0000, 0, 0) +#define _MX51_PAD_USBH1_DATA4__CSPI_SS0 IOMUX_PAD(0x698, 0x298, 1, 0x0000, 0, 0) +#define _MX51_PAD_USBH1_DATA4__GPIO1_15 IOMUX_PAD(0x698, 0x298, 2, 0x0000, 0, 0) +#define _MX51_PAD_USBH1_DATA4__USBH1_DATA4 IOMUX_PAD(0x698, 0x298, 0, 0x0000, 0, 0) +#define _MX51_PAD_USBH1_DATA5__CSPI_SS1 IOMUX_PAD(0x69c, 0x29c, 1, 0x0920, 0, 0) +#define _MX51_PAD_USBH1_DATA5__GPIO1_16 IOMUX_PAD(0x69c, 0x29c, 2, 0x0000, 0, 0) +#define _MX51_PAD_USBH1_DATA5__USBH1_DATA5 IOMUX_PAD(0x69c, 0x29c, 0, 0x0000, 0, 0) +#define _MX51_PAD_USBH1_DATA6__CSPI_SS3 IOMUX_PAD(0x6a0, 0x2a0, 1, 0x0928, 1, 0) +#define _MX51_PAD_USBH1_DATA6__GPIO1_17 IOMUX_PAD(0x6a0, 0x2a0, 2, 0x0000, 0, 0) +#define _MX51_PAD_USBH1_DATA6__USBH1_DATA6 IOMUX_PAD(0x6a0, 0x2a0, 0, 0x0000, 0, 0) +#define _MX51_PAD_USBH1_DATA7__ECSPI1_SS3 IOMUX_PAD(0x6a4, 0x2a4, 1, 0x0000, 0, 0) +#define _MX51_PAD_USBH1_DATA7__ECSPI2_SS3 IOMUX_PAD(0x6a4, 0x2a4, 5, 0x0934, 1, 0) +#define _MX51_PAD_USBH1_DATA7__GPIO1_18 IOMUX_PAD(0x6a4, 0x2a4, 2, 0x0000, 0, 0) +#define _MX51_PAD_USBH1_DATA7__USBH1_DATA7 IOMUX_PAD(0x6a4, 0x2a4, 0, 0x0000, 0, 0) +#define _MX51_PAD_DI1_PIN11__DI1_PIN11 IOMUX_PAD(0x6a8, 0x2a8, 0, 0x0000, 0, 0) +#define _MX51_PAD_DI1_PIN11__ECSPI1_SS2 IOMUX_PAD(0x6a8, 0x2a8, 7, 0x0000, 0, 0) +#define _MX51_PAD_DI1_PIN11__GPIO3_0 IOMUX_PAD(0x6a8, 0x2a8, 4, 0x0000, 0, 0) +#define _MX51_PAD_DI1_PIN12__DI1_PIN12 IOMUX_PAD(0x6ac, 0x2ac, 0, 0x0000, 0, 0) +#define _MX51_PAD_DI1_PIN12__GPIO3_1 IOMUX_PAD(0x6ac, 0x2ac, 4, 0x0978, 1, 0) +#define _MX51_PAD_DI1_PIN13__DI1_PIN13 IOMUX_PAD(0x6b0, 0x2b0, 0, 0x0000, 0, 0) +#define _MX51_PAD_DI1_PIN13__GPIO3_2 IOMUX_PAD(0x6b0, 0x2b0, 4, 0x097c, 1, 0) +#define _MX51_PAD_DI1_D0_CS__DI1_D0_CS IOMUX_PAD(0x6b4, 0x2b4, 0, 0x0000, 0, 0) +#define _MX51_PAD_DI1_D0_CS__GPIO3_3 IOMUX_PAD(0x6b4, 0x2b4, 4, 0x0980, 1, 0) +#define _MX51_PAD_DI1_D1_CS__DI1_D1_CS IOMUX_PAD(0x6b8, 0x2b8, 0, 0x0000, 0, 0) +#define _MX51_PAD_DI1_D1_CS__DISP1_PIN14 IOMUX_PAD(0x6b8, 0x2b8, 2, 0x0000, 0, 0) +#define _MX51_PAD_DI1_D1_CS__DISP1_PIN5 IOMUX_PAD(0x6b8, 0x2b8, 3, 0x0000, 0, 0) +#define _MX51_PAD_DI1_D1_CS__GPIO3_4 IOMUX_PAD(0x6b8, 0x2b8, 4, 0x0984, 1, 0) +#define _MX51_PAD_DISPB2_SER_DIN__DISP1_PIN1 IOMUX_PAD(0x6bc, 0x2bc, 2, 0x09a4, 1, 0) +#define _MX51_PAD_DISPB2_SER_DIN__DISPB2_SER_DIN IOMUX_PAD(0x6bc, 0x2bc, 0, 0x09c4, 0, 0) +#define _MX51_PAD_DISPB2_SER_DIN__GPIO3_5 IOMUX_PAD(0x6bc, 0x2bc, 4, 0x0988, 1, 0) +#define _MX51_PAD_DISPB2_SER_DIO__DISP1_PIN6 IOMUX_PAD(0x6c0, 0x2c0, 3, 0x0000, 0, 0) +#define _MX51_PAD_DISPB2_SER_DIO__DISPB2_SER_DIO IOMUX_PAD(0x6c0, 0x2c0, 0, 0x09c4, 1, 0) +#define _MX51_PAD_DISPB2_SER_DIO__GPIO3_6 IOMUX_PAD(0x6c0, 0x2c0, 4, 0x098c, 1, 0) +#define _MX51_PAD_DISPB2_SER_CLK__DISP1_PIN17 IOMUX_PAD(0x6c4, 0x2c4, 2, 0x0000, 0, 0) +#define _MX51_PAD_DISPB2_SER_CLK__DISP1_PIN7 IOMUX_PAD(0x6c4, 0x2c4, 3, 0x0000, 0, 0) +#define _MX51_PAD_DISPB2_SER_CLK__DISPB2_SER_CLK IOMUX_PAD(0x6c4, 0x2c4, 0, 0x0000, 0, 0) +#define _MX51_PAD_DISPB2_SER_CLK__GPIO3_7 IOMUX_PAD(0x6c4, 0x2c4, 4, 0x0990, 1, 0) +#define _MX51_PAD_DISPB2_SER_RS__DISP1_EXT_CLK IOMUX_PAD(0x6c8, 0x2c8, 2, 0x0000, 0, 0) +#define _MX51_PAD_DISPB2_SER_RS__DISP1_PIN16 IOMUX_PAD(0x6c8, 0x2c8, 2, 0x0000, 0, 0) +#define _MX51_PAD_DISPB2_SER_RS__DISP1_PIN8 IOMUX_PAD(0x6c8, 0x2c8, 3, 0x0000, 0, 0) +#define _MX51_PAD_DISPB2_SER_RS__DISPB2_SER_RS IOMUX_PAD(0x6c8, 0x2c8, 0, 0x0000, 0, 0) +#define _MX51_PAD_DISPB2_SER_RS__DISPB2_SER_RS IOMUX_PAD(0x6c8, 0x2c8, 0, 0x0000, 0, 0) +#define _MX51_PAD_DISPB2_SER_RS__GPIO3_8 IOMUX_PAD(0x6c8, 0x2c8, 4, 0x0994, 1, 0) +#define _MX51_PAD_DISP1_DAT0__DISP1_DAT0 IOMUX_PAD(0x6cc, 0x2cc, 0, 0x0000, 0, 0) +#define _MX51_PAD_DISP1_DAT1__DISP1_DAT1 IOMUX_PAD(0x6d0, 0x2d0, 0, 0x0000, 0, 0) +#define _MX51_PAD_DISP1_DAT2__DISP1_DAT2 IOMUX_PAD(0x6d4, 0x2d4, 0, 0x0000, 0, 0) +#define _MX51_PAD_DISP1_DAT3__DISP1_DAT3 IOMUX_PAD(0x6d8, 0x2d8, 0, 0x0000, 0, 0) +#define _MX51_PAD_DISP1_DAT4__DISP1_DAT4 IOMUX_PAD(0x6dc, 0x2dc, 0, 0x0000, 0, 0) +#define _MX51_PAD_DISP1_DAT5__DISP1_DAT5 IOMUX_PAD(0x6e0, 0x2e0, 0, 0x0000, 0, 0) +#define _MX51_PAD_DISP1_DAT6__BOOT_USB_SRC IOMUX_PAD(0x6e4, 0x2e4, 7, 0x0000, 0, 0) +#define _MX51_PAD_DISP1_DAT6__DISP1_DAT6 IOMUX_PAD(0x6e4, 0x2e4, 0, 0x0000, 0, 0) +#define _MX51_PAD_DISP1_DAT7__BOOT_EEPROM_CFG IOMUX_PAD(0x6e8, 0x2e8, 7, 0x0000, 0, 0) +#define _MX51_PAD_DISP1_DAT7__DISP1_DAT7 IOMUX_PAD(0x6e8, 0x2e8, 0, 0x0000, 0, 0) +#define _MX51_PAD_DISP1_DAT8__BOOT_SRC0 IOMUX_PAD(0x6ec, 0x2ec, 7, 0x0000, 0, 0) +#define _MX51_PAD_DISP1_DAT8__DISP1_DAT8 IOMUX_PAD(0x6ec, 0x2ec, 0, 0x0000, 0, 0) +#define _MX51_PAD_DISP1_DAT9__BOOT_SRC1 IOMUX_PAD(0x6f0, 0x2f0, 7, 0x0000, 0, 0) +#define _MX51_PAD_DISP1_DAT9__DISP1_DAT9 IOMUX_PAD(0x6f0, 0x2f0, 0, 0x0000, 0, 0) +#define _MX51_PAD_DISP1_DAT10__BOOT_SPARE_SIZE IOMUX_PAD(0x6f4, 0x2f4, 7, 0x0000, 0, 0) +#define _MX51_PAD_DISP1_DAT10__DISP1_DAT10 IOMUX_PAD(0x6f4, 0x2f4, 0, 0x0000, 0, 0) +#define _MX51_PAD_DISP1_DAT11__BOOT_LPB_FREQ2 IOMUX_PAD(0x6f8, 0x2f8, 7, 0x0000, 0, 0) +#define _MX51_PAD_DISP1_DAT11__DISP1_DAT11 IOMUX_PAD(0x6f8, 0x2f8, 0, 0x0000, 0, 0) +#define _MX51_PAD_DISP1_DAT12__BOOT_MLC_SEL IOMUX_PAD(0x6fc, 0x2fc, 7, 0x0000, 0, 0) +#define _MX51_PAD_DISP1_DAT12__DISP1_DAT12 IOMUX_PAD(0x6fc, 0x2fc, 0, 0x0000, 0, 0) +#define _MX51_PAD_DISP1_DAT13__BOOT_MEM_CTL0 IOMUX_PAD(0x700, 0x300, 7, 0x0000, 0, 0) +#define _MX51_PAD_DISP1_DAT13__DISP1_DAT13 IOMUX_PAD(0x700, 0x300, 0, 0x0000, 0, 0) +#define _MX51_PAD_DISP1_DAT14__BOOT_MEM_CTL1 IOMUX_PAD(0x704, 0x304, 7, 0x0000, 0, 0) +#define _MX51_PAD_DISP1_DAT14__DISP1_DAT14 IOMUX_PAD(0x704, 0x304, 0, 0x0000, 0, 0) +#define _MX51_PAD_DISP1_DAT15__BOOT_BUS_WIDTH IOMUX_PAD(0x708, 0x308, 7, 0x0000, 0, 0) +#define _MX51_PAD_DISP1_DAT15__DISP1_DAT15 IOMUX_PAD(0x708, 0x308, 0, 0x0000, 0, 0) +#define _MX51_PAD_DISP1_DAT16__BOOT_PAGE_SIZE0 IOMUX_PAD(0x70c, 0x30c, 7, 0x0000, 0, 0) +#define _MX51_PAD_DISP1_DAT16__DISP1_DAT16 IOMUX_PAD(0x70c, 0x30c, 0, 0x0000, 0, 0) +#define _MX51_PAD_DISP1_DAT17__BOOT_PAGE_SIZE1 IOMUX_PAD(0x710, 0x310, 7, 0x0000, 0, 0) +#define _MX51_PAD_DISP1_DAT17__DISP1_DAT17 IOMUX_PAD(0x710, 0x310, 0, 0x0000, 0, 0) +#define _MX51_PAD_DISP1_DAT18__BOOT_WEIM_MUXED0 IOMUX_PAD(0x714, 0x314, 7, 0x0000, 0, 0) +#define _MX51_PAD_DISP1_DAT18__DISP1_DAT18 IOMUX_PAD(0x714, 0x314, 0, 0x0000, 0, 0) +#define _MX51_PAD_DISP1_DAT18__DISP2_PIN11 IOMUX_PAD(0x714, 0x314, 5, 0x0000, 0, 0) +#define _MX51_PAD_DISP1_DAT18__DISP2_PIN5 IOMUX_PAD(0x714, 0x314, 4, 0x0000, 0, 0) +#define _MX51_PAD_DISP1_DAT19__BOOT_WEIM_MUXED1 IOMUX_PAD(0x718, 0x318, 7, 0x0000, 0, 0) +#define _MX51_PAD_DISP1_DAT19__DISP1_DAT19 IOMUX_PAD(0x718, 0x318, 0, 0x0000, 0, 0) +#define _MX51_PAD_DISP1_DAT19__DISP2_PIN12 IOMUX_PAD(0x718, 0x318, 5, 0x0000, 0, 0) +#define _MX51_PAD_DISP1_DAT19__DISP2_PIN6 IOMUX_PAD(0x718, 0x318, 4, 0x0000, 0, 0) +#define _MX51_PAD_DISP1_DAT20__BOOT_MEM_TYPE0 IOMUX_PAD(0x71c, 0x31c, 7, 0x0000, 0, 0) +#define _MX51_PAD_DISP1_DAT20__DISP1_DAT20 IOMUX_PAD(0x71c, 0x31c, 0, 0x0000, 0, 0) +#define _MX51_PAD_DISP1_DAT20__DISP2_PIN13 IOMUX_PAD(0x71c, 0x31c, 5, 0x0000, 0, 0) +#define _MX51_PAD_DISP1_DAT20__DISP2_PIN7 IOMUX_PAD(0x71c, 0x31c, 4, 0x0000, 0, 0) +#define _MX51_PAD_DISP1_DAT21__BOOT_MEM_TYPE1 IOMUX_PAD(0x720, 0x320, 7, 0x0000, 0, 0) +#define _MX51_PAD_DISP1_DAT21__DISP1_DAT21 IOMUX_PAD(0x720, 0x320, 0, 0x0000, 0, 0) +#define _MX51_PAD_DISP1_DAT21__DISP2_PIN14 IOMUX_PAD(0x720, 0x320, 5, 0x0000, 0, 0) +#define _MX51_PAD_DISP1_DAT21__DISP2_PIN8 IOMUX_PAD(0x720, 0x320, 4, 0x0000, 0, 0) +#define _MX51_PAD_DISP1_DAT22__BOOT_LPB_FREQ0 IOMUX_PAD(0x724, 0x324, 7, 0x0000, 0, 0) +#define _MX51_PAD_DISP1_DAT22__DISP1_DAT22 IOMUX_PAD(0x724, 0x324, 0, 0x0000, 0, 0) +#define _MX51_PAD_DISP1_DAT22__DISP2_D0_CS IOMUX_PAD(0x724, 0x324, 6, 0x0000, 0, 0) +#define _MX51_PAD_DISP1_DAT22__DISP2_DAT16 IOMUX_PAD(0x724, 0x324, 5, 0x0000, 0, 0) +#define _MX51_PAD_DISP1_DAT23__BOOT_LPB_FREQ1 IOMUX_PAD(0x728, 0x328, 7, 0x0000, 0, 0) +#define _MX51_PAD_DISP1_DAT23__DISP1_DAT23 IOMUX_PAD(0x728, 0x328, 0, 0x0000, 0, 0) +#define _MX51_PAD_DISP1_DAT23__DISP2_D1_CS IOMUX_PAD(0x728, 0x328, 6, 0x0000, 0, 0) +#define _MX51_PAD_DISP1_DAT23__DISP2_DAT17 IOMUX_PAD(0x728, 0x328, 5, 0x0000, 0, 0) +#define _MX51_PAD_DISP1_DAT23__DISP2_SER_CS IOMUX_PAD(0x728, 0x328, 4, 0x0000, 0, 0) +#define _MX51_PAD_DI1_PIN3__DI1_PIN3 IOMUX_PAD(0x72c, 0x32c, 0, 0x0000, 0, 0) +#define _MX51_PAD_DI1_PIN2__DI1_PIN2 IOMUX_PAD(0x734, 0x330, 0, 0x0000, 0, 0) +#define _MX51_PAD_DI_GP2__DISP1_SER_CLK IOMUX_PAD(0x740, 0x338, 0, 0x0000, 0, 0) +#define _MX51_PAD_DI_GP2__DISP2_WAIT IOMUX_PAD(0x740, 0x338, 2, 0x09a8, 1, 0) +#define _MX51_PAD_DI_GP3__CSI1_DATA_EN IOMUX_PAD(0x744, 0x33c, 3, 0x09a0, 1, 0) +#define _MX51_PAD_DI_GP3__DISP1_SER_DIO IOMUX_PAD(0x744, 0x33c, 0, 0x09c0, 0, 0) +#define _MX51_PAD_DI_GP3__FEC_TX_ER IOMUX_PAD(0x744, 0x33c, 2, 0x0000, 0, 0) +#define _MX51_PAD_DI2_PIN4__CSI2_DATA_EN IOMUX_PAD(0x748, 0x340, 3, 0x099c, 1, 0) +#define _MX51_PAD_DI2_PIN4__DI2_PIN4 IOMUX_PAD(0x748, 0x340, 0, 0x0000, 0, 0) +#define _MX51_PAD_DI2_PIN4__FEC_CRS IOMUX_PAD(0x748, 0x340, 2, 0x0950, 1, 0) +#define _MX51_PAD_DI2_PIN2__DI2_PIN2 IOMUX_PAD(0x74c, 0x344, 0, 0x0000, 0, 0) +#define _MX51_PAD_DI2_PIN2__FEC_MDC IOMUX_PAD(0x74c, 0x344, 2, 0x0000, 0, 0) +#define _MX51_PAD_DI2_PIN3__DI2_PIN3 IOMUX_PAD(0x750, 0x348, 0, 0x0000, 0, 0) +#define _MX51_PAD_DI2_PIN3__FEC_MDIO IOMUX_PAD(0x750, 0x348, 2, 0x0954, 1, 0) +#define _MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK IOMUX_PAD(0x754, 0x34c, 0, 0x0000, 0, 0) +#define _MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 IOMUX_PAD(0x754, 0x34c, 2, 0x095c, 1, 0) +#define _MX51_PAD_DI_GP4__DI2_PIN15 IOMUX_PAD(0x758, 0x350, 4, 0x0000, 0, 0) +#define _MX51_PAD_DI_GP4__DISP1_SER_DIN IOMUX_PAD(0x758, 0x350, 0, 0x09c0, 1, 0) +#define _MX51_PAD_DI_GP4__DISP2_PIN1 IOMUX_PAD(0x758, 0x350, 3, 0x0000, 0, 0) +#define _MX51_PAD_DI_GP4__FEC_RDATA2 IOMUX_PAD(0x758, 0x350, 2, 0x0960, 1, 0) +#define _MX51_PAD_DISP2_DAT0__DISP2_DAT0 IOMUX_PAD(0x75c, 0x354, 0, 0x0000, 0, 0) +#define _MX51_PAD_DISP2_DAT0__FEC_RDATA3 IOMUX_PAD(0x75c, 0x354, 2, 0x0964, 1, 0) +#define _MX51_PAD_DISP2_DAT0__KEY_COL6 IOMUX_PAD(0x75c, 0x354, 4, 0x09c8, 1, 0) +#define _MX51_PAD_DISP2_DAT0__UART3_RXD IOMUX_PAD(0x75c, 0x354, 5, 0x09f4, 8, 0) +#define _MX51_PAD_DISP2_DAT0__USBH3_CLK IOMUX_PAD(0x75c, 0x354, 3, 0x09f8, 1, 0) +#define _MX51_PAD_DISP2_DAT1__DISP2_DAT1 IOMUX_PAD(0x760, 0x358, 0, 0x0000, 0, 0) +#define _MX51_PAD_DISP2_DAT1__FEC_RX_ER IOMUX_PAD(0x760, 0x358, 2, 0x0970, 1, 0) +#define _MX51_PAD_DISP2_DAT1__KEY_COL7 IOMUX_PAD(0x760, 0x358, 4, 0x09cc, 1, 0) +#define _MX51_PAD_DISP2_DAT1__UART3_TXD IOMUX_PAD(0x760, 0x358, 5, 0x0000, 0, 0) +#define _MX51_PAD_DISP2_DAT1__USBH3_DIR IOMUX_PAD(0x760, 0x358, 3, 0x0a1c, 1, 0) +#define _MX51_PAD_DISP2_DAT2__DISP2_DAT2 IOMUX_PAD(0x764, 0x35c, 0, 0x0000, 0, 0) +#define _MX51_PAD_DISP2_DAT3__DISP2_DAT3 IOMUX_PAD(0x768, 0x360, 0, 0x0000, 0, 0) +#define _MX51_PAD_DISP2_DAT4__DISP2_DAT4 IOMUX_PAD(0x76c, 0x364, 0, 0x0000, 0, 0) +#define _MX51_PAD_DISP2_DAT5__DISP2_DAT5 IOMUX_PAD(0x770, 0x368, 0, 0x0000, 0, 0) +#define _MX51_PAD_DISP2_DAT6__DISP2_DAT6 IOMUX_PAD(0x774, 0x36c, 0, 0x0000, 0, 0) +#define _MX51_PAD_DISP2_DAT6__FEC_TDATA1 IOMUX_PAD(0x774, 0x36c, 2, 0x0000, 0, 0) +#define _MX51_PAD_DISP2_DAT6__GPIO1_19 IOMUX_PAD(0x774, 0x36c, 5, 0x0000, 0, 0) +#define _MX51_PAD_DISP2_DAT6__KEY_ROW4 IOMUX_PAD(0x774, 0x36c, 4, 0x09d0, 1, 0) +#define _MX51_PAD_DISP2_DAT6__USBH3_STP IOMUX_PAD(0x774, 0x36c, 3, 0x0a24, 1, 0) +#define _MX51_PAD_DISP2_DAT7__DISP2_DAT7 IOMUX_PAD(0x778, 0x370, 0, 0x0000, 0, 0) +#define _MX51_PAD_DISP2_DAT7__FEC_TDATA2 IOMUX_PAD(0x778, 0x370, 2, 0x0000, 0, 0) +#define _MX51_PAD_DISP2_DAT7__GPIO1_29 IOMUX_PAD(0x778, 0x370, 5, 0x0000, 0, 0) +#define _MX51_PAD_DISP2_DAT7__KEY_ROW5 IOMUX_PAD(0x778, 0x370, 4, 0x09d4, 1, 0) +#define _MX51_PAD_DISP2_DAT7__USBH3_NXT IOMUX_PAD(0x778, 0x370, 3, 0x0a20, 1, 0) +#define _MX51_PAD_DISP2_DAT8__DISP2_DAT8 IOMUX_PAD(0x77c, 0x374, 0, 0x0000, 0, 0) +#define _MX51_PAD_DISP2_DAT8__FEC_TDATA3 IOMUX_PAD(0x77c, 0x374, 2, 0x0000, 0, 0) +#define _MX51_PAD_DISP2_DAT8__GPIO1_30 IOMUX_PAD(0x77c, 0x374, 5, 0x0000, 0, 0) +#define _MX51_PAD_DISP2_DAT8__KEY_ROW6 IOMUX_PAD(0x77c, 0x374, 4, 0x09d8, 1, 0) +#define _MX51_PAD_DISP2_DAT8__USBH3_DATA0 IOMUX_PAD(0x77c, 0x374, 3, 0x09fc, 1, 0) +#define _MX51_PAD_DISP2_DAT9__AUD6_RXC IOMUX_PAD(0x780, 0x378, 4, 0x08f4, 1, 0) +#define _MX51_PAD_DISP2_DAT9__DISP2_DAT9 IOMUX_PAD(0x780, 0x378, 0, 0x0000, 0, 0) +#define _MX51_PAD_DISP2_DAT9__FEC_TX_EN IOMUX_PAD(0x780, 0x378, 2, 0x0000, 0, 0) +#define _MX51_PAD_DISP2_DAT9__GPIO1_31 IOMUX_PAD(0x780, 0x378, 5, 0x0000, 0, 0) +#define _MX51_PAD_DISP2_DAT9__USBH3_DATA1 IOMUX_PAD(0x780, 0x378, 3, 0x0a00, 1, 0) +#define _MX51_PAD_DISP2_DAT10__DISP2_DAT10 IOMUX_PAD(0x784, 0x37c, 0, 0x0000, 0, 0) +#define _MX51_PAD_DISP2_DAT10__DISP2_SER_CS IOMUX_PAD(0x784, 0x37c, 5, 0x0000, 0, 0) +#define _MX51_PAD_DISP2_DAT10__FEC_COL IOMUX_PAD(0x784, 0x37c, 2, 0x094c, 1, 0) +#define _MX51_PAD_DISP2_DAT10__KEY_ROW7 IOMUX_PAD(0x784, 0x37c, 4, 0x09dc, 1, 0) +#define _MX51_PAD_DISP2_DAT10__USBH3_DATA2 IOMUX_PAD(0x784, 0x37c, 3, 0x0a04, 1, 0) +#define _MX51_PAD_DISP2_DAT11__AUD6_TXD IOMUX_PAD(0x788, 0x380, 4, 0x08f0, 1, 0) +#define _MX51_PAD_DISP2_DAT11__DISP2_DAT11 IOMUX_PAD(0x788, 0x380, 0, 0x0000, 0, 0) +#define _MX51_PAD_DISP2_DAT11__FEC_RX_CLK IOMUX_PAD(0x788, 0x380, 2, 0x0968, 1, 0) +#define _MX51_PAD_DISP2_DAT11__GPIO1_10 IOMUX_PAD(0x788, 0x380, 7, 0x0000, 0, 0) +#define _MX51_PAD_DISP2_DAT11__USBH3_DATA3 IOMUX_PAD(0x788, 0x380, 3, 0x0a08, 1, 0) +#define _MX51_PAD_DISP2_DAT12__AUD6_RXD IOMUX_PAD(0x78c, 0x384, 4, 0x08ec, 1, 0) +#define _MX51_PAD_DISP2_DAT12__DISP2_DAT12 IOMUX_PAD(0x78c, 0x384, 0, 0x0000, 0, 0) +#define _MX51_PAD_DISP2_DAT12__FEC_RX_DV IOMUX_PAD(0x78c, 0x384, 2, 0x096c, 1, 0) +#define _MX51_PAD_DISP2_DAT12__USBH3_DATA4 IOMUX_PAD(0x78c, 0x384, 3, 0x0a0c, 1, 0) +#define _MX51_PAD_DISP2_DAT13__AUD6_TXC IOMUX_PAD(0x790, 0x388, 4, 0x08fc, 1, 0) +#define _MX51_PAD_DISP2_DAT13__DISP2_DAT13 IOMUX_PAD(0x790, 0x388, 0, 0x0000, 0, 0) +#define _MX51_PAD_DISP2_DAT13__FEC_TX_CLK IOMUX_PAD(0x790, 0x388, 2, 0x0974, 1, 0) +#define _MX51_PAD_DISP2_DAT13__USBH3_DATA5 IOMUX_PAD(0x790, 0x388, 3, 0x0a10, 1, 0) +#define _MX51_PAD_DISP2_DAT14__AUD6_TXFS IOMUX_PAD(0x794, 0x38c, 4, 0x0900, 1, 0) +#define _MX51_PAD_DISP2_DAT14__DISP2_DAT14 IOMUX_PAD(0x794, 0x38c, 0, 0x0000, 0, 0) +#define _MX51_PAD_DISP2_DAT14__FEC_RDATA0 IOMUX_PAD(0x794, 0x38c, 2, 0x0958, 1, 0) +#define _MX51_PAD_DISP2_DAT14__USBH3_DATA6 IOMUX_PAD(0x794, 0x38c, 3, 0x0a14, 1, 0) +#define _MX51_PAD_DISP2_DAT15__AUD6_RXFS IOMUX_PAD(0x798, 0x390, 4, 0x08f8, 1, 0) +#define _MX51_PAD_DISP2_DAT15__DISP1_SER_CS IOMUX_PAD(0x798, 0x390, 5, 0x0000, 0, 0) +#define _MX51_PAD_DISP2_DAT15__DISP2_DAT15 IOMUX_PAD(0x798, 0x390, 0, 0x0000, 0, 0) +#define _MX51_PAD_DISP2_DAT15__FEC_TDATA0 IOMUX_PAD(0x798, 0x390, 2, 0x0000, 0, 0) +#define _MX51_PAD_DISP2_DAT15__USBH3_DATA7 IOMUX_PAD(0x798, 0x390, 3, 0x0a18, 1, 0) +#define _MX51_PAD_SD1_CMD__AUD5_RXFS IOMUX_PAD(0x79c, 0x394, 1, 0x08e0, 1, 0) +#define _MX51_PAD_SD1_CMD__CSPI_MOSI IOMUX_PAD(0x79c, 0x394, 2, 0x091c, 2, 0) +#define _MX51_PAD_SD1_CMD__SD1_CMD IOMUX_PAD(0x79c, 0x394, 0x10, 0x0000, 0, 0) +#define _MX51_PAD_SD1_CLK__AUD5_RXC IOMUX_PAD(0x7a0, 0x398, 1, 0x08dc, 1, 0) +#define _MX51_PAD_SD1_CLK__CSPI_SCLK IOMUX_PAD(0x7a0, 0x398, 2, 0x0914, 2, 0) +#define _MX51_PAD_SD1_CLK__SD1_CLK IOMUX_PAD(0x7a0, 0x398, 0x10, 0x0000, 0, 0) +#define _MX51_PAD_SD1_DATA0__AUD5_TXD IOMUX_PAD(0x7a4, 0x39c, 1, 0x08d8, 2, 0) +#define _MX51_PAD_SD1_DATA0__CSPI_MISO IOMUX_PAD(0x7a4, 0x39c, 2, 0x0918, 1, 0) +#define _MX51_PAD_SD1_DATA0__SD1_DATA0 IOMUX_PAD(0x7a4, 0x39c, 0x10, 0x0000, 0, 0) +#define _MX51_PAD_EIM_DA0__EIM_DA0 IOMUX_PAD(0x000, 0x01c, 0, 0x0000, 0, 0) +#define _MX51_PAD_EIM_DA1__EIM_DA1 IOMUX_PAD(0x000, 0x020, 0, 0x0000, 0, 0) +#define _MX51_PAD_EIM_DA2__EIM_DA2 IOMUX_PAD(0x000, 0x024, 0, 0x0000, 0, 0) +#define _MX51_PAD_EIM_DA3__EIM_DA3 IOMUX_PAD(0x000, 0x028, 0, 0x0000, 0, 0) +#define _MX51_PAD_SD1_DATA1__AUD5_RXD IOMUX_PAD(0x7a8, 0x3a0, 1, 0x08d4, 2, 0) +#define _MX51_PAD_SD1_DATA1__SD1_DATA1 IOMUX_PAD(0x7a8, 0x3a0, 0x10, 0x0000, 0, 0) +#define _MX51_PAD_EIM_DA4__EIM_DA4 IOMUX_PAD(0x000, 0x02c, 0, 0x0000, 0, 0) +#define _MX51_PAD_EIM_DA5__EIM_DA5 IOMUX_PAD(0x000, 0x030, 0, 0x0000, 0, 0) +#define _MX51_PAD_EIM_DA6__EIM_DA6 IOMUX_PAD(0x000, 0x034, 0, 0x0000, 0, 0) +#define _MX51_PAD_EIM_DA7__EIM_DA7 IOMUX_PAD(0x000, 0x038, 0, 0x0000, 0, 0) +#define _MX51_PAD_SD1_DATA2__AUD5_TXC IOMUX_PAD(0x7ac, 0x3a4, 1, 0x08e4, 2, 0) +#define _MX51_PAD_SD1_DATA2__SD1_DATA2 IOMUX_PAD(0x7ac, 0x3a4, 0x10, 0x0000, 0, 0) +#define _MX51_PAD_EIM_DA10__EIM_DA10 IOMUX_PAD(0x000, 0x044, 0, 0x0000, 0, 0) +#define _MX51_PAD_EIM_DA11__EIM_DA11 IOMUX_PAD(0x000, 0x048, 0, 0x0000, 0, 0) +#define _MX51_PAD_EIM_DA8__EIM_DA8 IOMUX_PAD(0x000, 0x03c, 0, 0x0000, 0, 0) +#define _MX51_PAD_EIM_DA9__EIM_DA9 IOMUX_PAD(0x000, 0x040, 0, 0x0000, 0, 0) +#define _MX51_PAD_SD1_DATA3__AUD5_TXFS IOMUX_PAD(0x7b0, 0x3a8, 1, 0x08e8, 2, 0) +#define _MX51_PAD_SD1_DATA3__CSPI_SS1 IOMUX_PAD(0x7b0, 0x3a8, 2, 0x0920, 1, 0) +#define _MX51_PAD_SD1_DATA3__SD1_DATA3 IOMUX_PAD(0x7b0, 0x3a8, 0x10, 0x0000, 0, 0) +#define _MX51_PAD_GPIO1_0__CSPI_SS2 IOMUX_PAD(0x7b4, 0x3ac, 2, 0x0924, 0, 0) +#define _MX51_PAD_GPIO1_0__GPIO1_0 IOMUX_PAD(0x7b4, 0x3ac, 1, 0x0000, 0, 0) +#define _MX51_PAD_GPIO1_0__SD1_CD IOMUX_PAD(0x7b4, 0x3ac, 0, 0x0000, 0, 0) +#define _MX51_PAD_GPIO1_1__CSPI_MISO IOMUX_PAD(0x7b8, 0x3b0, 2, 0x0918, 2, 0) +#define _MX51_PAD_GPIO1_1__GPIO1_1 IOMUX_PAD(0x7b8, 0x3b0, 1, 0x0000, 0, 0) +#define _MX51_PAD_GPIO1_1__SD1_WP IOMUX_PAD(0x7b8, 0x3b0, 0, 0x0000, 0, 0) +#define _MX51_PAD_EIM_DA12__EIM_DA12 IOMUX_PAD(0x000, 0x04c, 0, 0x0000, 0, 0) +#define _MX51_PAD_EIM_DA13__EIM_DA13 IOMUX_PAD(0x000, 0x050, 0, 0x0000, 0, 0) +#define _MX51_PAD_EIM_DA14__EIM_DA14 IOMUX_PAD(0x000, 0x054, 0, 0x0000, 0, 0) +#define _MX51_PAD_EIM_DA15__EIM_DA15 IOMUX_PAD(0x000, 0x058, 0, 0x0000, 0, 0) +#define _MX51_PAD_SD2_CMD__CSPI_MOSI IOMUX_PAD(0x000, 0x3b4, 2, 0x091c, 3, 0) +#define _MX51_PAD_SD2_CMD__I2C1_SCL IOMUX_PAD(0x7bc, 0x3b4, 0x11, 0x09b0, 2, 0) +#define _MX51_PAD_SD2_CMD__SD2_CMD IOMUX_PAD(0x7bc, 0x3b4, 0x10, 0x0000, 0, 0) +#define _MX51_PAD_SD2_CLK__CSPI_SCLK IOMUX_PAD(0x7c0, 0x3b8, 2, 0x0914, 3, 0) +#define _MX51_PAD_SD2_CLK__I2C1_SDA IOMUX_PAD(0x7c0, 0x3b8, 0x11, 0x09b4, 2, 0) +#define _MX51_PAD_SD2_CLK__SD2_CLK IOMUX_PAD(0x7c0, 0x3b8, 0x10, 0x0000, 0, 0) +#define _MX51_PAD_SD2_DATA0__CSPI_MISO IOMUX_PAD(0x7c4, 0x3bc, 2, 0x0918, 3, 0) +#define _MX51_PAD_SD2_DATA0__SD1_DAT4 IOMUX_PAD(0x7c4, 0x3bc, 1, 0x0000, 0, 0) +#define _MX51_PAD_SD2_DATA0__SD2_DATA0 IOMUX_PAD(0x7c4, 0x3bc, 0x10, 0x0000, 0, 0) +#define _MX51_PAD_SD2_DATA1__SD1_DAT5 IOMUX_PAD(0x7c8, 0x3c0, 1, 0x0000, 0, 0) +#define _MX51_PAD_SD2_DATA1__SD2_DATA1 IOMUX_PAD(0x7c8, 0x3c0, 0x10, 0x0000, 0, 0) +#define _MX51_PAD_SD2_DATA1__USBH3_H2_DP IOMUX_PAD(0x7c8, 0x3c0, 2, 0x0000, 0, 0) +#define _MX51_PAD_SD2_DATA2__SD1_DAT6 IOMUX_PAD(0x7cc, 0x3c4, 1, 0x0000, 0, 0) +#define _MX51_PAD_SD2_DATA2__SD2_DATA2 IOMUX_PAD(0x7cc, 0x3c4, 0x10, 0x0000, 0, 0) +#define _MX51_PAD_SD2_DATA2__USBH3_H2_DM IOMUX_PAD(0x7cc, 0x3c4, 2, 0x0000, 0, 0) +#define _MX51_PAD_SD2_DATA3__CSPI_SS2 IOMUX_PAD(0x7d0, 0x3c8, 2, 0x0924, 1, 0) +#define _MX51_PAD_SD2_DATA3__SD1_DAT7 IOMUX_PAD(0x7d0, 0x3c8, 1, 0x0000, 0, 0) +#define _MX51_PAD_SD2_DATA3__SD2_DATA3 IOMUX_PAD(0x7d0, 0x3c8, 0x10, 0x0000, 0, 0) +#define _MX51_PAD_GPIO1_2__CCM_OUT_2 IOMUX_PAD(0x7d4, 0x3cc, 5, 0x0000, 0, 0) +#define _MX51_PAD_GPIO1_2__GPIO1_2 IOMUX_PAD(0x7d4, 0x3cc, 0, 0x0000, 0, 0) +#define _MX51_PAD_GPIO1_2__I2C2_SCL IOMUX_PAD(0x7d4, 0x3cc, 0x12, 0x09b8, 3, 0) +#define _MX51_PAD_GPIO1_2__PLL1_BYP IOMUX_PAD(0x7d4, 0x3cc, 7, 0x090c, 1, 0) +#define _MX51_PAD_GPIO1_2__PWM1_PWMO IOMUX_PAD(0x7d4, 0x3cc, 1, 0x0000, 0, 0) +#define _MX51_PAD_GPIO1_3__GPIO1_3 IOMUX_PAD(0x7d8, 0x3d0, 0, 0x0000, 0, 0) +#define _MX51_PAD_GPIO1_3__I2C2_SDA IOMUX_PAD(0x7d8, 0x3d0, 0x12, 0x09bc, 3, 0) +#define _MX51_PAD_GPIO1_3__PLL2_BYP IOMUX_PAD(0x7d8, 0x3d0, 7, 0x0910, 1, 0) +#define _MX51_PAD_GPIO1_3__PWM2_PWMO IOMUX_PAD(0x7d8, 0x3d0, 1, 0x0000, 0, 0) +#define _MX51_PAD_PMIC_INT_REQ__PMIC_INT_REQ IOMUX_PAD(0x7fc, 0x3d4, 0, 0x0000, 0, 0) +#define _MX51_PAD_PMIC_INT_REQ__PMIC_PMU_IRQ_B IOMUX_PAD(0x7fc, 0x3d4, 1, 0x0000, 0, 0) +#define _MX51_PAD_GPIO1_4__DISP2_EXT_CLK IOMUX_PAD(0x804, 0x3d8, 4, 0x0908, 1, 0) +#define _MX51_PAD_GPIO1_4__EIM_RDY IOMUX_PAD(0x804, 0x3d8, 3, 0x0938, 1, 0) +#define _MX51_PAD_GPIO1_4__GPIO1_4 IOMUX_PAD(0x804, 0x3d8, 0, 0x0000, 0, 0) +#define _MX51_PAD_GPIO1_4__WDOG1_WDOG_B IOMUX_PAD(0x804, 0x3d8, 2, 0x0000, 0, 0) +#define _MX51_PAD_GPIO1_5__CSI2_MCLK IOMUX_PAD(0x808, 0x3dc, 6, 0x0000, 0, 0) +#define _MX51_PAD_GPIO1_5__DISP2_PIN16 IOMUX_PAD(0x808, 0x3dc, 3, 0x0000, 0, 0) +#define _MX51_PAD_GPIO1_5__GPIO1_5 IOMUX_PAD(0x808, 0x3dc, 0, 0x0000, 0, 0) +#define _MX51_PAD_GPIO1_5__WDOG2_WDOG_B IOMUX_PAD(0x808, 0x3dc, 2, 0x0000, 0, 0) +#define _MX51_PAD_GPIO1_6__DISP2_PIN17 IOMUX_PAD(0x80c, 0x3e0, 4, 0x0000, 0, 0) +#define _MX51_PAD_GPIO1_6__GPIO1_6 IOMUX_PAD(0x80c, 0x3e0, 0, 0x0000, 0, 0) +#define _MX51_PAD_GPIO1_6__REF_EN_B IOMUX_PAD(0x80c, 0x3e0, 3, 0x0000, 0, 0) +#define _MX51_PAD_GPIO1_7__CCM_OUT_0 IOMUX_PAD(0x810, 0x3e4, 3, 0x0000, 0, 0) +#define _MX51_PAD_GPIO1_7__GPIO1_7 IOMUX_PAD(0x810, 0x3e4, 0, 0x0000, 0, 0) +#define _MX51_PAD_GPIO1_7__SD2_WP IOMUX_PAD(0x810, 0x3e4, 6, 0x0000, 0, 0) +#define _MX51_PAD_GPIO1_7__SPDIF_OUT1 IOMUX_PAD(0x810, 0x3e4, 2, 0x0000, 0, 0) +#define _MX51_PAD_GPIO1_8__CSI2_DATA_EN IOMUX_PAD(0x814, 0x3e8, 2, 0x099c, 2, 0) +#define _MX51_PAD_GPIO1_8__GPIO1_8 IOMUX_PAD(0x814, 0x3e8, 0, 0x0000, 0, 0) +#define _MX51_PAD_GPIO1_8__SD2_CD IOMUX_PAD(0x814, 0x3e8, 6, 0x0000, 0, 0) +#define _MX51_PAD_GPIO1_8__USBH3_PWR IOMUX_PAD(0x814, 0x3e8, 1, 0x0000, 0, 0) +#define _MX51_PAD_GPIO1_9__CCM_OUT_1 IOMUX_PAD(0x818, 0x3ec, 3, 0x0000, 0, 0) +#define _MX51_PAD_GPIO1_9__DISP2_D1_CS IOMUX_PAD(0x818, 0x3ec, 2, 0x0000, 0, 0) +#define _MX51_PAD_GPIO1_9__DISP2_SER_CS IOMUX_PAD(0x818, 0x3ec, 7, 0x0000, 0, 0) +#define _MX51_PAD_GPIO1_9__GPIO1_9 IOMUX_PAD(0x818, 0x3ec, 0, 0x0000, 0, 0) +#define _MX51_PAD_GPIO1_9__SD2_LCTL IOMUX_PAD(0x818, 0x3ec, 6, 0x0000, 0, 0) +#define _MX51_PAD_GPIO1_9__USBH3_OC IOMUX_PAD(0x818, 0x3ec, 1, 0x0000, 0, 0) + +/* The same pins as above but with the default pad control values applied */ +#define MX51_PAD_EIM_D16__AUD4_RXFS (_MX51_PAD_EIM_D16__AUD4_RXFS | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_D16__AUD5_TXD (_MX51_PAD_EIM_D16__AUD5_TXD | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_D16__EIM_D16 (_MX51_PAD_EIM_D16__EIM_D16 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_D16__GPIO2_0 (_MX51_PAD_EIM_D16__GPIO2_0 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_EIM_D16__I2C1_SDA (_MX51_PAD_EIM_D16__I2C1_SDA | MUX_PAD_CTRL(MX51_I2C_PAD_CTRL)) +#define MX51_PAD_EIM_D16__UART2_CTS (_MX51_PAD_EIM_D16__UART2_CTS | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) +#define MX51_PAD_EIM_D16__USBH2_DATA0 (_MX51_PAD_EIM_D16__USBH2_DATA0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_D17__AUD5_RXD (_MX51_PAD_EIM_D17__AUD5_RXD | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_D17__EIM_D17 (_MX51_PAD_EIM_D17__EIM_D17 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_D17__GPIO2_1 (_MX51_PAD_EIM_D17__GPIO2_1 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_EIM_D17__UART2_RXD (_MX51_PAD_EIM_D17__UART2_RXD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) +#define MX51_PAD_EIM_D17__UART3_CTS (_MX51_PAD_EIM_D17__UART3_CTS | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) +#define MX51_PAD_EIM_D17__USBH2_DATA1 (_MX51_PAD_EIM_D17__USBH2_DATA1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_D18__AUD5_TXC (_MX51_PAD_EIM_D18__AUD5_TXC | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_D18__EIM_D18 (_MX51_PAD_EIM_D18__EIM_D18 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_D18__GPIO2_2 (_MX51_PAD_EIM_D18__GPIO2_2 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_EIM_D18__UART2_TXD (_MX51_PAD_EIM_D18__UART2_TXD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) +#define MX51_PAD_EIM_D18__UART3_RTS (_MX51_PAD_EIM_D18__UART3_RTS | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) +#define MX51_PAD_EIM_D18__USBH2_DATA2 (_MX51_PAD_EIM_D18__USBH2_DATA2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_D19__AUD4_RXC (_MX51_PAD_EIM_D19__AUD4_RXC | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_D19__AUD5_TXFS (_MX51_PAD_EIM_D19__AUD5_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_D19__EIM_D19 (_MX51_PAD_EIM_D19__EIM_D19 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_D19__GPIO2_3 (_MX51_PAD_EIM_D19__GPIO2_3 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_EIM_D19__I2C1_SCL (_MX51_PAD_EIM_D19__I2C1_SCL | MUX_PAD_CTRL(MX51_I2C_PAD_CTRL)) +#define MX51_PAD_EIM_D19__UART2_RTS (_MX51_PAD_EIM_D19__UART2_RTS | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) +#define MX51_PAD_EIM_D19__USBH2_DATA3 (_MX51_PAD_EIM_D19__USBH2_DATA3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_D20__AUD4_TXD (_MX51_PAD_EIM_D20__AUD4_TXD | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_D20__EIM_D20 (_MX51_PAD_EIM_D20__EIM_D20 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_D20__GPIO2_4 (_MX51_PAD_EIM_D20__GPIO2_4 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_EIM_D20__SRTC_ALARM_DEB (_MX51_PAD_EIM_D20__SRTC_ALARM_DEB | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_D20__USBH2_DATA4 (_MX51_PAD_EIM_D20__USBH2_DATA4 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_D21__AUD4_RXD (_MX51_PAD_EIM_D21__AUD4_RXD | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_D21__EIM_D21 (_MX51_PAD_EIM_D21__EIM_D21 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_D21__GPIO2_5 (_MX51_PAD_EIM_D21__GPIO2_5 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_EIM_D21__SRTC_ALARM_DEB (_MX51_PAD_EIM_D21__SRTC_ALARM_DEB | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_D21__USBH2_DATA5 (_MX51_PAD_EIM_D21__USBH2_DATA5 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_D22__AUD4_TXC (_MX51_PAD_EIM_D22__AUD4_TXC | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_D22__EIM_D22 (_MX51_PAD_EIM_D22__EIM_D22 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_D22__GPIO2_6 (_MX51_PAD_EIM_D22__GPIO2_6 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_EIM_D22__USBH2_DATA6 (_MX51_PAD_EIM_D22__USBH2_DATA6 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_D23__AUD4_TXFS (_MX51_PAD_EIM_D23__AUD4_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_D23__EIM_D23 (_MX51_PAD_EIM_D23__EIM_D23 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_D23__GPIO2_7 (_MX51_PAD_EIM_D23__GPIO2_7 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_EIM_D23__SPDIF_OUT1 (_MX51_PAD_EIM_D23__SPDIF_OUT1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_D23__USBH2_DATA7 (_MX51_PAD_EIM_D23__USBH2_DATA7 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_D24__AUD6_RXFS (_MX51_PAD_EIM_D24__AUD6_RXFS | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_D24__EIM_D24 (_MX51_PAD_EIM_D24__EIM_D24 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_D24__GPIO2_8 (_MX51_PAD_EIM_D24__GPIO2_8 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_EIM_D24__I2C2_SDA (_MX51_PAD_EIM_D24__I2C2_SDA | MUX_PAD_CTRL(MX51_I2C_PAD_CTRL)) +#define MX51_PAD_EIM_D24__UART3_CTS (_MX51_PAD_EIM_D24__UART3_CTS | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) +#define MX51_PAD_EIM_D24__USBOTG_DATA0 (_MX51_PAD_EIM_D24__USBOTG_DATA0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_D25__EIM_D25 (_MX51_PAD_EIM_D25__EIM_D25 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_D25__KEY_COL6 (_MX51_PAD_EIM_D25__KEY_COL6 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_D25__UART2_CTS (_MX51_PAD_EIM_D25__UART2_CTS | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) +#define MX51_PAD_EIM_D25__UART3_RXD (_MX51_PAD_EIM_D25__UART3_RXD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) +#define MX51_PAD_EIM_D25__USBOTG_DATA1 (_MX51_PAD_EIM_D25__USBOTG_DATA1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_D26__EIM_D26 (_MX51_PAD_EIM_D26__EIM_D26 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_D26__KEY_COL7 (_MX51_PAD_EIM_D26__KEY_COL7 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_D26__UART2_RTS (_MX51_PAD_EIM_D26__UART2_RTS | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) +#define MX51_PAD_EIM_D26__UART3_TXD (_MX51_PAD_EIM_D26__UART3_TXD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) +#define MX51_PAD_EIM_D26__USBOTG_DATA2 (_MX51_PAD_EIM_D26__USBOTG_DATA2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_D27__AUD6_RXC (_MX51_PAD_EIM_D27__AUD6_RXC | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_D27__EIM_D27 (_MX51_PAD_EIM_D27__EIM_D27 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_D27__GPIO2_9 (_MX51_PAD_EIM_D27__GPIO2_9 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_EIM_D27__I2C2_SCL (_MX51_PAD_EIM_D27__I2C2_SCL | MUX_PAD_CTRL(MX51_I2C_PAD_CTRL)) +#define MX51_PAD_EIM_D27__UART3_RTS (_MX51_PAD_EIM_D27__UART3_RTS | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) +#define MX51_PAD_EIM_D27__USBOTG_DATA3 (_MX51_PAD_EIM_D27__USBOTG_DATA3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_D28__AUD6_TXD (_MX51_PAD_EIM_D28__AUD6_TXD | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_D28__EIM_D28 (_MX51_PAD_EIM_D28__EIM_D28 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_D28__KEY_ROW4 (_MX51_PAD_EIM_D28__KEY_ROW4 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_D28__USBOTG_DATA4 (_MX51_PAD_EIM_D28__USBOTG_DATA4 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_D29__AUD6_RXD (_MX51_PAD_EIM_D29__AUD6_RXD | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_D29__EIM_D29 (_MX51_PAD_EIM_D29__EIM_D29 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_D29__KEY_ROW5 (_MX51_PAD_EIM_D29__KEY_ROW5 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_D29__USBOTG_DATA5 (_MX51_PAD_EIM_D29__USBOTG_DATA5 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_D30__AUD6_TXC (_MX51_PAD_EIM_D30__AUD6_TXC | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_D30__EIM_D30 (_MX51_PAD_EIM_D30__EIM_D30 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_D30__KEY_ROW6 (_MX51_PAD_EIM_D30__KEY_ROW6 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_D30__USBOTG_DATA6 (_MX51_PAD_EIM_D30__USBOTG_DATA6 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_D31__AUD6_TXFS (_MX51_PAD_EIM_D31__AUD6_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_D31__EIM_D31 (_MX51_PAD_EIM_D31__EIM_D31 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_D31__KEY_ROW7 (_MX51_PAD_EIM_D31__KEY_ROW7 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_D31__USBOTG_DATA7 (_MX51_PAD_EIM_D31__USBOTG_DATA7 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_A16__EIM_A16 (_MX51_PAD_EIM_A16__EIM_A16 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_A16__GPIO2_10 (_MX51_PAD_EIM_A16__GPIO2_10 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_EIM_A16__OSC_FREQ_SEL0 (_MX51_PAD_EIM_A16__OSC_FREQ_SEL0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_A17__EIM_A17 (_MX51_PAD_EIM_A17__EIM_A17 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_A17__GPIO2_11 (_MX51_PAD_EIM_A17__GPIO2_11 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_EIM_A17__OSC_FREQ_SEL1 (_MX51_PAD_EIM_A17__OSC_FREQ_SEL1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_A18__BOOT_LPB0 (_MX51_PAD_EIM_A18__BOOT_LPB0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_A18__EIM_A18 (_MX51_PAD_EIM_A18__EIM_A18 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_A18__GPIO2_12 (_MX51_PAD_EIM_A18__GPIO2_12 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_EIM_A19__BOOT_LPB1 (_MX51_PAD_EIM_A19__BOOT_LPB1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_A19__EIM_A19 (_MX51_PAD_EIM_A19__EIM_A19 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_A19__GPIO2_13 (_MX51_PAD_EIM_A19__GPIO2_13 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_EIM_A20__BOOT_UART_SRC0 (_MX51_PAD_EIM_A20__BOOT_UART_SRC0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_A20__EIM_A20 (_MX51_PAD_EIM_A20__EIM_A20 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_A20__GPIO2_14 (_MX51_PAD_EIM_A20__GPIO2_14 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_EIM_A21__BOOT_UART_SRC1 (_MX51_PAD_EIM_A21__BOOT_UART_SRC1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_A21__EIM_A21 (_MX51_PAD_EIM_A21__EIM_A21 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_A21__GPIO2_15 (_MX51_PAD_EIM_A21__GPIO2_15 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_EIM_A22__EIM_A22 (_MX51_PAD_EIM_A22__EIM_A22 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_A22__GPIO2_16 (_MX51_PAD_EIM_A22__GPIO2_16 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_EIM_A23__BOOT_HPN_EN (_MX51_PAD_EIM_A23__BOOT_HPN_EN | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_A23__EIM_A23 (_MX51_PAD_EIM_A23__EIM_A23 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_A23__GPIO2_17 (_MX51_PAD_EIM_A23__GPIO2_17 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_EIM_A24__EIM_A24 (_MX51_PAD_EIM_A24__EIM_A24 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_A24__GPIO2_18 (_MX51_PAD_EIM_A24__GPIO2_18 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_EIM_A24__USBH2_CLK (_MX51_PAD_EIM_A24__USBH2_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_A25__DISP1_PIN4 (_MX51_PAD_EIM_A25__DISP1_PIN4 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_A25__EIM_A25 (_MX51_PAD_EIM_A25__EIM_A25 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_A25__GPIO2_19 (_MX51_PAD_EIM_A25__GPIO2_19 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_EIM_A25__USBH2_DIR (_MX51_PAD_EIM_A25__USBH2_DIR | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_A26__CSI1_DATA_EN (_MX51_PAD_EIM_A26__CSI1_DATA_EN | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_A26__DISP2_EXT_CLK (_MX51_PAD_EIM_A26__DISP2_EXT_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_A26__EIM_A26 (_MX51_PAD_EIM_A26__EIM_A26 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_A26__GPIO2_20 (_MX51_PAD_EIM_A26__GPIO2_20 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_EIM_A26__USBH2_STP (_MX51_PAD_EIM_A26__USBH2_STP | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_A27__CSI2_DATA_EN (_MX51_PAD_EIM_A27__CSI2_DATA_EN | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_A27__DISP1_PIN1 (_MX51_PAD_EIM_A27__DISP1_PIN1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_A27__EIM_A27 (_MX51_PAD_EIM_A27__EIM_A27 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_A27__GPIO2_21 (_MX51_PAD_EIM_A27__GPIO2_21 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_EIM_A27__USBH2_NXT (_MX51_PAD_EIM_A27__USBH2_NXT | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_EB0__EIM_EB0 (_MX51_PAD_EIM_EB0__EIM_EB0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_EB1__EIM_EB1 (_MX51_PAD_EIM_EB1__EIM_EB1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_EB2__AUD5_RXFS (_MX51_PAD_EIM_EB2__AUD5_RXFS | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_EB2__CSI1_D2 (_MX51_PAD_EIM_EB2__CSI1_D2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_EB2__EIM_EB2 (_MX51_PAD_EIM_EB2__EIM_EB2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_EB2__FEC_MDIO (_MX51_PAD_EIM_EB2__FEC_MDIO | \ + MUX_PAD_CTRL(PAD_CTL_PUS_22K_UP | PAD_CTL_PKE | PAD_CTL_SRE_FAST | \ + PAD_CTL_DSE_HIGH | PAD_CTL_PUE | PAD_CTL_HYS)) +#define MX51_PAD_EIM_EB2__GPIO2_22 (_MX51_PAD_EIM_EB2__GPIO2_22 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_EIM_EB2__GPT_CMPOUT1 (_MX51_PAD_EIM_EB2__GPT_CMPOUT1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_EB3__AUD5_RXC (_MX51_PAD_EIM_EB3__AUD5_RXC | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_EB3__CSI1_D3 (_MX51_PAD_EIM_EB3__CSI1_D3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_EB3__EIM_EB3 (_MX51_PAD_EIM_EB3__EIM_EB3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_EB3__FEC_RDATA1 (_MX51_PAD_EIM_EB3__FEC_RDATA1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_EB3__GPIO2_23 (_MX51_PAD_EIM_EB3__GPIO2_23 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_EIM_EB3__GPT_CMPOUT2 (_MX51_PAD_EIM_EB3__GPT_CMPOUT2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_OE__EIM_OE (_MX51_PAD_EIM_OE__EIM_OE | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_OE__GPIO2_24 (_MX51_PAD_EIM_OE__GPIO2_24 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_EIM_CS0__EIM_CS0 (_MX51_PAD_EIM_CS0__EIM_CS0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_CS0__GPIO2_25 (_MX51_PAD_EIM_CS0__GPIO2_25 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_EIM_CS1__EIM_CS1 (_MX51_PAD_EIM_CS1__EIM_CS1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_CS1__GPIO2_26 (_MX51_PAD_EIM_CS1__GPIO2_26 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_EIM_CS2__AUD5_TXD (_MX51_PAD_EIM_CS2__AUD5_TXD | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_CS2__CSI1_D4 (_MX51_PAD_EIM_CS2__CSI1_D4 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_CS2__EIM_CS2 (_MX51_PAD_EIM_CS2__EIM_CS2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_CS2__FEC_RDATA2 (_MX51_PAD_EIM_CS2__FEC_RDATA2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_CS2__GPIO2_27 (_MX51_PAD_EIM_CS2__GPIO2_27 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_EIM_CS2__USBOTG_STP (_MX51_PAD_EIM_CS2__USBOTG_STP | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_CS3__AUD5_RXD (_MX51_PAD_EIM_CS3__AUD5_RXD | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_CS3__CSI1_D5 (_MX51_PAD_EIM_CS3__CSI1_D5 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_CS3__EIM_CS3 (_MX51_PAD_EIM_CS3__EIM_CS3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_CS3__FEC_RDATA3 (_MX51_PAD_EIM_CS3__FEC_RDATA3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_CS3__GPIO2_28 (_MX51_PAD_EIM_CS3__GPIO2_28 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_EIM_CS3__USBOTG_NXT (_MX51_PAD_EIM_CS3__USBOTG_NXT | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_CS4__AUD5_TXC (_MX51_PAD_EIM_CS4__AUD5_TXC | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_CS4__CSI1_D6 (_MX51_PAD_EIM_CS4__CSI1_D6 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_CS4__EIM_CS4 (_MX51_PAD_EIM_CS4__EIM_CS4 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_CS4__FEC_RX_ER (_MX51_PAD_EIM_CS4__FEC_RX_ER | MUX_PAD_CTRL(MX51_PAD_CTRL_2)) +#define MX51_PAD_EIM_CS4__GPIO2_29 (_MX51_PAD_EIM_CS4__GPIO2_29 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_EIM_CS4__USBOTG_CLK (_MX51_PAD_EIM_CS4__USBOTG_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_CS5__AUD5_TXFS (_MX51_PAD_EIM_CS5__AUD5_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_CS5__CSI1_D7 (_MX51_PAD_EIM_CS5__CSI1_D7 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_CS5__DISP1_EXT_CLK (_MX51_PAD_EIM_CS5__DISP1_EXT_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_CS5__EIM_CS5 (_MX51_PAD_EIM_CS5__EIM_CS5 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_CS5__FEC_CRS (_MX51_PAD_EIM_CS5__FEC_CRS | MUX_PAD_CTRL(MX51_PAD_CTRL_2)) +#define MX51_PAD_EIM_CS5__GPIO2_30 (_MX51_PAD_EIM_CS5__GPIO2_30 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_EIM_CS5__USBOTG_DIR (_MX51_PAD_EIM_CS5__USBOTG_DIR | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_DTACK__EIM_DTACK (_MX51_PAD_EIM_DTACK__EIM_DTACK | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_DTACK__GPIO2_31 (_MX51_PAD_EIM_DTACK__GPIO2_31 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_EIM_LBA__EIM_LBA (_MX51_PAD_EIM_LBA__EIM_LBA | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_LBA__GPIO3_1 (_MX51_PAD_EIM_LBA__GPIO3_1 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_EIM_CRE__EIM_CRE (_MX51_PAD_EIM_CRE__EIM_CRE | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_CRE__GPIO3_2 (_MX51_PAD_EIM_CRE__GPIO3_2 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_DRAM_CS1__DRAM_CS1 (_MX51_PAD_DRAM_CS1__DRAM_CS1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_WE_B__GPIO3_3 (_MX51_PAD_NANDF_WE_B__GPIO3_3 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_NANDF_WE_B__NANDF_WE_B (_MX51_PAD_NANDF_WE_B__NANDF_WE_B | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_WE_B__PATA_DIOW (_MX51_PAD_NANDF_WE_B__PATA_DIOW | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_WE_B__SD3_DATA0 (_MX51_PAD_NANDF_WE_B__SD3_DATA0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_RE_B__GPIO3_4 (_MX51_PAD_NANDF_RE_B__GPIO3_4 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_NANDF_RE_B__NANDF_RE_B (_MX51_PAD_NANDF_RE_B__NANDF_RE_B | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_RE_B__PATA_DIOR (_MX51_PAD_NANDF_RE_B__PATA_DIOR | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_RE_B__SD3_DATA1 (_MX51_PAD_NANDF_RE_B__SD3_DATA1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_ALE__GPIO3_5 (_MX51_PAD_NANDF_ALE__GPIO3_5 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_NANDF_ALE__NANDF_ALE (_MX51_PAD_NANDF_ALE__NANDF_ALE | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_ALE__PATA_BUFFER_EN (_MX51_PAD_NANDF_ALE__PATA_BUFFER_EN | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_CLE__GPIO3_6 (_MX51_PAD_NANDF_CLE__GPIO3_6 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_NANDF_CLE__NANDF_CLE (_MX51_PAD_NANDF_CLE__NANDF_CLE | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_CLE__PATA_RESET_B (_MX51_PAD_NANDF_CLE__PATA_RESET_B | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_WP_B__GPIO3_7 (_MX51_PAD_NANDF_WP_B__GPIO3_7 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_NANDF_WP_B__NANDF_WP_B (_MX51_PAD_NANDF_WP_B__NANDF_WP_B | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_WP_B__PATA_DMACK (_MX51_PAD_NANDF_WP_B__PATA_DMACK | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_WP_B__SD3_DATA2 (_MX51_PAD_NANDF_WP_B__SD3_DATA2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_RB0__ECSPI2_SS1 (_MX51_PAD_NANDF_RB0__ECSPI2_SS1 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) +#define MX51_PAD_NANDF_RB0__GPIO3_8 (_MX51_PAD_NANDF_RB0__GPIO3_8 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_NANDF_RB0__NANDF_RB0 (_MX51_PAD_NANDF_RB0__NANDF_RB0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_RB0__PATA_DMARQ (_MX51_PAD_NANDF_RB0__PATA_DMARQ | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_RB0__SD3_DATA3 (_MX51_PAD_NANDF_RB0__SD3_DATA3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_RB1__CSPI_MOSI (_MX51_PAD_NANDF_RB1__CSPI_MOSI | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) +#define MX51_PAD_NANDF_RB1__ECSPI2_RDY (_MX51_PAD_NANDF_RB1__ECSPI2_RDY | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) +#define MX51_PAD_NANDF_RB1__GPIO3_9 (_MX51_PAD_NANDF_RB1__GPIO3_9 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_NANDF_RB1__NANDF_RB1 (_MX51_PAD_NANDF_RB1__NANDF_RB1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_RB1__PATA_IORDY (_MX51_PAD_NANDF_RB1__PATA_IORDY | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_RB1__SD4_CMD (_MX51_PAD_NANDF_RB1__SD4_CMD | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_RB2__DISP2_WAIT (_MX51_PAD_NANDF_RB2__DISP2_WAIT | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_RB2__ECSPI2_SCLK (_MX51_PAD_NANDF_RB2__ECSPI2_SCLK | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) +#define MX51_PAD_NANDF_RB2__FEC_COL (_MX51_PAD_NANDF_RB2__FEC_COL | MUX_PAD_CTRL(MX51_PAD_CTRL_2)) +#define MX51_PAD_NANDF_RB2__GPIO3_10 (_MX51_PAD_NANDF_RB2__GPIO3_10 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_NANDF_RB2__NANDF_RB2 (_MX51_PAD_NANDF_RB2__NANDF_RB2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_RB2__USBH3_H3_DP (_MX51_PAD_NANDF_RB2__USBH3_H3_DP | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_RB2__USBH3_NXT (_MX51_PAD_NANDF_RB2__USBH3_NXT | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_RB3__DISP1_WAIT (_MX51_PAD_NANDF_RB3__DISP1_WAIT | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_RB3__ECSPI2_MISO (_MX51_PAD_NANDF_RB3__ECSPI2_MISO | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) +#define MX51_PAD_NANDF_RB3__FEC_RX_CLK (_MX51_PAD_NANDF_RB3__FEC_RX_CLK | MUX_PAD_CTRL(MX51_PAD_CTRL_2)) +#define MX51_PAD_NANDF_RB3__GPIO3_11 (_MX51_PAD_NANDF_RB3__GPIO3_11 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_NANDF_RB3__NANDF_RB3 (_MX51_PAD_NANDF_RB3__NANDF_RB3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_RB3__USBH3_CLK (_MX51_PAD_NANDF_RB3__USBH3_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_RB3__USBH3_H3_DM (_MX51_PAD_NANDF_RB3__USBH3_H3_DM | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_GPIO_NAND__GPIO_NAND (_MX51_PAD_GPIO_NAND__GPIO_NAND | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_GPIO_NAND__PATA_INTRQ (_MX51_PAD_GPIO_NAND__PATA_INTRQ | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_CS0__GPIO3_16 (_MX51_PAD_NANDF_CS0__GPIO3_16 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_NANDF_CS0__NANDF_CS0 (_MX51_PAD_NANDF_CS0__NANDF_CS0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_CS1__GPIO3_17 (_MX51_PAD_NANDF_CS1__GPIO3_17 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_NANDF_CS1__NANDF_CS1 (_MX51_PAD_NANDF_CS1__NANDF_CS1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_CS2__CSPI_SCLK (_MX51_PAD_NANDF_CS2__CSPI_SCLK | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) +#define MX51_PAD_NANDF_CS2__FEC_TX_ER (_MX51_PAD_NANDF_CS2__FEC_TX_ER | MUX_PAD_CTRL(MX51_PAD_CTRL_5)) +#define MX51_PAD_NANDF_CS2__GPIO3_18 (_MX51_PAD_NANDF_CS2__GPIO3_18 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_NANDF_CS2__NANDF_CS2 (_MX51_PAD_NANDF_CS2__NANDF_CS2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_CS2__PATA_CS_0 (_MX51_PAD_NANDF_CS2__PATA_CS_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_CS2__SD4_CLK (_MX51_PAD_NANDF_CS2__SD4_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_CS2__USBH3_H1_DP (_MX51_PAD_NANDF_CS2__USBH3_H1_DP | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_CS3__FEC_MDC (_MX51_PAD_NANDF_CS3__FEC_MDC | MUX_PAD_CTRL(MX51_PAD_CTRL_5)) +#define MX51_PAD_NANDF_CS3__GPIO3_19 (_MX51_PAD_NANDF_CS3__GPIO3_19 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_NANDF_CS3__NANDF_CS3 (_MX51_PAD_NANDF_CS3__NANDF_CS3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_CS3__PATA_CS_1 (_MX51_PAD_NANDF_CS3__PATA_CS_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_CS3__SD4_DAT0 (_MX51_PAD_NANDF_CS3__SD4_DAT0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_CS3__USBH3_H1_DM (_MX51_PAD_NANDF_CS3__USBH3_H1_DM | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_CS4__FEC_TDATA1 (_MX51_PAD_NANDF_CS4__FEC_TDATA1 | MUX_PAD_CTRL(MX51_PAD_CTRL_5)) +#define MX51_PAD_NANDF_CS4__GPIO3_20 (_MX51_PAD_NANDF_CS4__GPIO3_20 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_NANDF_CS4__NANDF_CS4 (_MX51_PAD_NANDF_CS4__NANDF_CS4 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_CS4__PATA_DA_0 (_MX51_PAD_NANDF_CS4__PATA_DA_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_CS4__SD4_DAT1 (_MX51_PAD_NANDF_CS4__SD4_DAT1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_CS4__USBH3_STP (_MX51_PAD_NANDF_CS4__USBH3_STP | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_CS5__FEC_TDATA2 (_MX51_PAD_NANDF_CS5__FEC_TDATA2 | MUX_PAD_CTRL(MX51_PAD_CTRL_5)) +#define MX51_PAD_NANDF_CS5__GPIO3_21 (_MX51_PAD_NANDF_CS5__GPIO3_21 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_NANDF_CS5__NANDF_CS5 (_MX51_PAD_NANDF_CS5__NANDF_CS5 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_CS5__PATA_DA_1 (_MX51_PAD_NANDF_CS5__PATA_DA_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_CS5__SD4_DAT2 (_MX51_PAD_NANDF_CS5__SD4_DAT2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_CS5__USBH3_DIR (_MX51_PAD_NANDF_CS5__USBH3_DIR | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_CS6__CSPI_SS3 (_MX51_PAD_NANDF_CS6__CSPI_SS3 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) +#define MX51_PAD_NANDF_CS6__FEC_TDATA3 (_MX51_PAD_NANDF_CS6__FEC_TDATA3 | MUX_PAD_CTRL(MX51_PAD_CTRL_5)) +#define MX51_PAD_NANDF_CS6__GPIO3_22 (_MX51_PAD_NANDF_CS6__GPIO3_22 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_NANDF_CS6__NANDF_CS6 (_MX51_PAD_NANDF_CS6__NANDF_CS6 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_CS6__PATA_DA_2 (_MX51_PAD_NANDF_CS6__PATA_DA_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_CS6__SD4_DAT3 (_MX51_PAD_NANDF_CS6__SD4_DAT3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_CS7__FEC_TX_EN (_MX51_PAD_NANDF_CS7__FEC_TX_EN | MUX_PAD_CTRL(MX51_PAD_CTRL_5)) +#define MX51_PAD_NANDF_CS7__GPIO3_23 (_MX51_PAD_NANDF_CS7__GPIO3_23 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_NANDF_CS7__NANDF_CS7 (_MX51_PAD_NANDF_CS7__NANDF_CS7 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_CS7__SD3_CLK (_MX51_PAD_NANDF_CS7__SD3_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_RDY_INT__ECSPI2_SS0 (_MX51_PAD_NANDF_RDY_INT__ECSPI2_SS0 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) +#define MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK (_MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK | MUX_PAD_CTRL(MX51_PAD_CTRL_4)) +#define MX51_PAD_NANDF_RDY_INT__GPIO3_24 (_MX51_PAD_NANDF_RDY_INT__GPIO3_24 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_NANDF_RDY_INT__NANDF_RDY_INT (_MX51_PAD_NANDF_RDY_INT__NANDF_RDY_INT | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_RDY_INT__SD3_CMD (_MX51_PAD_NANDF_RDY_INT__SD3_CMD | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_D15__ECSPI2_MOSI (_MX51_PAD_NANDF_D15__ECSPI2_MOSI | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) +#define MX51_PAD_NANDF_D15__GPIO3_25 (_MX51_PAD_NANDF_D15__GPIO3_25 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_NANDF_D15__NANDF_D15 (_MX51_PAD_NANDF_D15__NANDF_D15 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_D15__PATA_DATA15 (_MX51_PAD_NANDF_D15__PATA_DATA15 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_D15__SD3_DAT7 (_MX51_PAD_NANDF_D15__SD3_DAT7 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_D14__ECSPI2_SS3 (_MX51_PAD_NANDF_D14__ECSPI2_SS3 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) +#define MX51_PAD_NANDF_D14__GPIO3_26 (_MX51_PAD_NANDF_D14__GPIO3_26 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_NANDF_D14__NANDF_D14 (_MX51_PAD_NANDF_D14__NANDF_D14 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_D14__PATA_DATA14 (_MX51_PAD_NANDF_D14__PATA_DATA14 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_D14__SD3_DAT6 (_MX51_PAD_NANDF_D14__SD3_DAT6 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_D13__ECSPI2_SS2 (_MX51_PAD_NANDF_D13__ECSPI2_SS2 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) +#define MX51_PAD_NANDF_D13__GPIO3_27 (_MX51_PAD_NANDF_D13__GPIO3_27 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_NANDF_D13__NANDF_D13 (_MX51_PAD_NANDF_D13__NANDF_D13 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_D13__PATA_DATA13 (_MX51_PAD_NANDF_D13__PATA_DATA13 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_D13__SD3_DAT5 (_MX51_PAD_NANDF_D13__SD3_DAT5 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_D12__ECSPI2_SS1 (_MX51_PAD_NANDF_D12__ECSPI2_SS1 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) +#define MX51_PAD_NANDF_D12__GPIO3_28 (_MX51_PAD_NANDF_D12__GPIO3_28 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_NANDF_D12__NANDF_D12 (_MX51_PAD_NANDF_D12__NANDF_D12 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_D12__PATA_DATA12 (_MX51_PAD_NANDF_D12__PATA_DATA12 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_D12__SD3_DAT4 (_MX51_PAD_NANDF_D12__SD3_DAT4 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_D11__FEC_RX_DV (_MX51_PAD_NANDF_D11__FEC_RX_DV | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_D11__GPIO3_29 (_MX51_PAD_NANDF_D11__GPIO3_29 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_NANDF_D11__NANDF_D11 (_MX51_PAD_NANDF_D11__NANDF_D11 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_D11__PATA_DATA11 (_MX51_PAD_NANDF_D11__PATA_DATA11 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_D11__SD3_DATA3 (_MX51_PAD_NANDF_D11__SD3_DATA3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_D10__GPIO3_30 (_MX51_PAD_NANDF_D10__GPIO3_30 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_NANDF_D10__NANDF_D10 (_MX51_PAD_NANDF_D10__NANDF_D10 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_D10__PATA_DATA10 (_MX51_PAD_NANDF_D10__PATA_DATA10 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_D10__SD3_DATA2 (_MX51_PAD_NANDF_D10__SD3_DATA2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_D9__FEC_RDATA0 (_MX51_PAD_NANDF_D9__FEC_RDATA0 | MUX_PAD_CTRL(MX51_PAD_CTRL_4)) +#define MX51_PAD_NANDF_D9__GPIO3_31 (_MX51_PAD_NANDF_D9__GPIO3_31 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_NANDF_D9__NANDF_D9 (_MX51_PAD_NANDF_D9__NANDF_D9 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_D9__PATA_DATA9 (_MX51_PAD_NANDF_D9__PATA_DATA9 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_D9__SD3_DATA1 (_MX51_PAD_NANDF_D9__SD3_DATA1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_D8__FEC_TDATA0 (_MX51_PAD_NANDF_D8__FEC_TDATA0 | MUX_PAD_CTRL(MX51_PAD_CTRL_5)) +#define MX51_PAD_NANDF_D8__GPIO4_0 (_MX51_PAD_NANDF_D8__GPIO4_0 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_NANDF_D8__NANDF_D8 (_MX51_PAD_NANDF_D8__NANDF_D8 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_D8__PATA_DATA8 (_MX51_PAD_NANDF_D8__PATA_DATA8 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_D8__SD3_DATA0 (_MX51_PAD_NANDF_D8__SD3_DATA0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_D7__GPIO4_1 (_MX51_PAD_NANDF_D7__GPIO4_1 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_NANDF_D7__NANDF_D7 (_MX51_PAD_NANDF_D7__NANDF_D7 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_D7__PATA_DATA7 (_MX51_PAD_NANDF_D7__PATA_DATA7 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_D7__USBH3_DATA0 (_MX51_PAD_NANDF_D7__USBH3_DATA0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_D6__GPIO4_2 (_MX51_PAD_NANDF_D6__GPIO4_2 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_NANDF_D6__NANDF_D6 (_MX51_PAD_NANDF_D6__NANDF_D6 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_D6__PATA_DATA6 (_MX51_PAD_NANDF_D6__PATA_DATA6 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_D6__SD4_LCTL (_MX51_PAD_NANDF_D6__SD4_LCTL | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_D6__USBH3_DATA1 (_MX51_PAD_NANDF_D6__USBH3_DATA1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_D5__GPIO4_3 (_MX51_PAD_NANDF_D5__GPIO4_3 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_NANDF_D5__NANDF_D5 (_MX51_PAD_NANDF_D5__NANDF_D5 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_D5__PATA_DATA5 (_MX51_PAD_NANDF_D5__PATA_DATA5 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_D5__SD4_WP (_MX51_PAD_NANDF_D5__SD4_WP | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_D5__USBH3_DATA2 (_MX51_PAD_NANDF_D5__USBH3_DATA2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_D4__GPIO4_4 (_MX51_PAD_NANDF_D4__GPIO4_4 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_NANDF_D4__NANDF_D4 (_MX51_PAD_NANDF_D4__NANDF_D4 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_D4__PATA_DATA4 (_MX51_PAD_NANDF_D4__PATA_DATA4 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_D4__SD4_CD (_MX51_PAD_NANDF_D4__SD4_CD | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_D4__USBH3_DATA3 (_MX51_PAD_NANDF_D4__USBH3_DATA3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_D3__GPIO4_5 (_MX51_PAD_NANDF_D3__GPIO4_5 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_NANDF_D3__NANDF_D3 (_MX51_PAD_NANDF_D3__NANDF_D3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_D3__PATA_DATA3 (_MX51_PAD_NANDF_D3__PATA_DATA3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_D3__SD4_DAT4 (_MX51_PAD_NANDF_D3__SD4_DAT4 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_D3__USBH3_DATA4 (_MX51_PAD_NANDF_D3__USBH3_DATA4 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_D2__GPIO4_6 (_MX51_PAD_NANDF_D2__GPIO4_6 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_NANDF_D2__NANDF_D2 (_MX51_PAD_NANDF_D2__NANDF_D2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_D2__PATA_DATA2 (_MX51_PAD_NANDF_D2__PATA_DATA2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_D2__SD4_DAT5 (_MX51_PAD_NANDF_D2__SD4_DAT5 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_D2__USBH3_DATA5 (_MX51_PAD_NANDF_D2__USBH3_DATA5 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_D1__GPIO4_7 (_MX51_PAD_NANDF_D1__GPIO4_7 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_NANDF_D1__NANDF_D1 (_MX51_PAD_NANDF_D1__NANDF_D1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_D1__PATA_DATA1 (_MX51_PAD_NANDF_D1__PATA_DATA1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_D1__SD4_DAT6 (_MX51_PAD_NANDF_D1__SD4_DAT6 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_D1__USBH3_DATA6 (_MX51_PAD_NANDF_D1__USBH3_DATA6 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_D0__GPIO4_8 (_MX51_PAD_NANDF_D0__GPIO4_8 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_NANDF_D0__NANDF_D0 (_MX51_PAD_NANDF_D0__NANDF_D0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_D0__PATA_DATA0 (_MX51_PAD_NANDF_D0__PATA_DATA0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_D0__SD4_DAT7 (_MX51_PAD_NANDF_D0__SD4_DAT7 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_D0__USBH3_DATA7 (_MX51_PAD_NANDF_D0__USBH3_DATA7 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_CSI1_D8__CSI1_D8 (_MX51_PAD_CSI1_D8__CSI1_D8 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_CSI1_D8__GPIO3_12 (_MX51_PAD_CSI1_D8__GPIO3_12 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_CSI1_D9__CSI1_D9 (_MX51_PAD_CSI1_D9__CSI1_D9 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_CSI1_D9__GPIO3_13 (_MX51_PAD_CSI1_D9__GPIO3_13 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_CSI1_D10__CSI1_D10 (_MX51_PAD_CSI1_D10__CSI1_D10 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_CSI1_D11__CSI1_D11 (_MX51_PAD_CSI1_D11__CSI1_D11 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_CSI1_D12__CSI1_D12 (_MX51_PAD_CSI1_D12__CSI1_D12 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_CSI1_D13__CSI1_D13 (_MX51_PAD_CSI1_D13__CSI1_D13 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_CSI1_D14__CSI1_D14 (_MX51_PAD_CSI1_D14__CSI1_D14 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_CSI1_D15__CSI1_D15 (_MX51_PAD_CSI1_D15__CSI1_D15 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_CSI1_D16__CSI1_D16 (_MX51_PAD_CSI1_D16__CSI1_D16 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_CSI1_D17__CSI1_D17 (_MX51_PAD_CSI1_D17__CSI1_D17 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_CSI1_D18__CSI1_D18 (_MX51_PAD_CSI1_D18__CSI1_D18 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_CSI1_D19__CSI1_D19 (_MX51_PAD_CSI1_D19__CSI1_D19 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_CSI1_VSYNC__CSI1_VSYNC (_MX51_PAD_CSI1_VSYNC__CSI1_VSYNC | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_CSI1_VSYNC__GPIO3_14 (_MX51_PAD_CSI1_VSYNC__GPIO3_14 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_CSI1_HSYNC__CSI1_HSYNC (_MX51_PAD_CSI1_HSYNC__CSI1_HSYNC | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_CSI1_HSYNC__GPIO3_15 (_MX51_PAD_CSI1_HSYNC__GPIO3_15 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_CSI1_PIXCLK__CSI1_PIXCLK (_MX51_PAD_CSI1_PIXCLK__CSI1_PIXCLK | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_CSI1_MCLK__CSI1_MCLK (_MX51_PAD_CSI1_MCLK__CSI1_MCLK | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_CSI2_D12__CSI2_D12 (_MX51_PAD_CSI2_D12__CSI2_D12 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_CSI2_D12__GPIO4_9 (_MX51_PAD_CSI2_D12__GPIO4_9 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_CSI2_D13__CSI2_D13 (_MX51_PAD_CSI2_D13__CSI2_D13 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_CSI2_D13__GPIO4_10 (_MX51_PAD_CSI2_D13__GPIO4_10 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_CSI2_D14__CSI2_D14 (_MX51_PAD_CSI2_D14__CSI2_D14 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_CSI2_D15__CSI2_D15 (_MX51_PAD_CSI2_D15__CSI2_D15 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_CSI2_D16__CSI2_D16 (_MX51_PAD_CSI2_D16__CSI2_D16 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_CSI2_D17__CSI2_D17 (_MX51_PAD_CSI2_D17__CSI2_D17 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_CSI2_D18__CSI2_D18 (_MX51_PAD_CSI2_D18__CSI2_D18 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_CSI2_D18__GPIO4_11 (_MX51_PAD_CSI2_D18__GPIO4_11 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_CSI2_D19__CSI2_D19 (_MX51_PAD_CSI2_D19__CSI2_D19 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_CSI2_D19__GPIO4_12 (_MX51_PAD_CSI2_D19__GPIO4_12 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_CSI2_VSYNC__CSI2_VSYNC (_MX51_PAD_CSI2_VSYNC__CSI2_VSYNC | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_CSI2_VSYNC__GPIO4_13 (_MX51_PAD_CSI2_VSYNC__GPIO4_13 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_CSI2_HSYNC__CSI2_HSYNC (_MX51_PAD_CSI2_HSYNC__CSI2_HSYNC | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_CSI2_HSYNC__GPIO4_14 (_MX51_PAD_CSI2_HSYNC__GPIO4_14 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_CSI2_PIXCLK__CSI2_PIXCLK (_MX51_PAD_CSI2_PIXCLK__CSI2_PIXCLK | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_CSI2_PIXCLK__GPIO4_15 (_MX51_PAD_CSI2_PIXCLK__GPIO4_15 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_I2C1_CLK__GPIO4_16 (_MX51_PAD_I2C1_CLK__GPIO4_16 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_I2C1_CLK__I2C1_CLK (_MX51_PAD_I2C1_CLK__I2C1_CLK | MUX_PAD_CTRL(MX51_I2C_PAD_CTRL)) +#define MX51_PAD_I2C1_DAT__GPIO4_17 (_MX51_PAD_I2C1_DAT__GPIO4_17 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_I2C1_DAT__I2C1_DAT (_MX51_PAD_I2C1_DAT__I2C1_DAT | MUX_PAD_CTRL(MX51_I2C_PAD_CTRL)) +#define MX51_PAD_AUD3_BB_TXD__AUD3_TXD (_MX51_PAD_AUD3_BB_TXD__AUD3_TXD | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_AUD3_BB_TXD__GPIO4_18 (_MX51_PAD_AUD3_BB_TXD__GPIO4_18 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_AUD3_BB_RXD__AUD3_RXD (_MX51_PAD_AUD3_BB_RXD__AUD3_RXD | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_AUD3_BB_RXD__GPIO4_19 (_MX51_PAD_AUD3_BB_RXD__GPIO4_19 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_AUD3_BB_RXD__UART3_RXD (_MX51_PAD_AUD3_BB_RXD__UART3_RXD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) +#define MX51_PAD_AUD3_BB_CK__AUD3_TXC (_MX51_PAD_AUD3_BB_CK__AUD3_TXC | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_AUD3_BB_CK__GPIO4_20 (_MX51_PAD_AUD3_BB_CK__GPIO4_20 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_AUD3_BB_FS__AUD3_TXFS (_MX51_PAD_AUD3_BB_FS__AUD3_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_AUD3_BB_FS__GPIO4_21 (_MX51_PAD_AUD3_BB_FS__GPIO4_21 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_AUD3_BB_FS__UART3_TXD (_MX51_PAD_AUD3_BB_FS__UART3_TXD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) +#define MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI (_MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) +#define MX51_PAD_CSPI1_MOSI__GPIO4_22 (_MX51_PAD_CSPI1_MOSI__GPIO4_22 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_CSPI1_MOSI__I2C1_SDA (_MX51_PAD_CSPI1_MOSI__I2C1_SDA | MUX_PAD_CTRL(MX51_I2C_PAD_CTRL)) +#define MX51_PAD_CSPI1_MISO__AUD4_RXD (_MX51_PAD_CSPI1_MISO__AUD4_RXD | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_CSPI1_MISO__ECSPI1_MISO (_MX51_PAD_CSPI1_MISO__ECSPI1_MISO | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) +#define MX51_PAD_CSPI1_MISO__GPIO4_23 (_MX51_PAD_CSPI1_MISO__GPIO4_23 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_CSPI1_SS0__AUD4_TXC (_MX51_PAD_CSPI1_SS0__AUD4_TXC | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_CSPI1_SS0__ECSPI1_SS0 (_MX51_PAD_CSPI1_SS0__ECSPI1_SS0 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) +#define MX51_PAD_CSPI1_SS0__GPIO4_24 (_MX51_PAD_CSPI1_SS0__GPIO4_24 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_CSPI1_SS1__AUD4_TXD (_MX51_PAD_CSPI1_SS1__AUD4_TXD | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_CSPI1_SS1__ECSPI1_SS1 (_MX51_PAD_CSPI1_SS1__ECSPI1_SS1 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) +#define MX51_PAD_CSPI1_SS1__GPIO4_25 (_MX51_PAD_CSPI1_SS1__GPIO4_25 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_CSPI1_RDY__AUD4_TXFS (_MX51_PAD_CSPI1_RDY__AUD4_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_CSPI1_RDY__ECSPI1_RDY (_MX51_PAD_CSPI1_RDY__ECSPI1_RDY | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) +#define MX51_PAD_CSPI1_RDY__GPIO4_26 (_MX51_PAD_CSPI1_RDY__GPIO4_26 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK (_MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) +#define MX51_PAD_CSPI1_SCLK__GPIO4_27 (_MX51_PAD_CSPI1_SCLK__GPIO4_27 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_CSPI1_SCLK__I2C1_SCL (_MX51_PAD_CSPI1_SCLK__I2C1_SCL | MUX_PAD_CTRL(MX51_I2C_PAD_CTRL)) +#define MX51_PAD_UART1_RXD__GPIO4_28 (_MX51_PAD_UART1_RXD__GPIO4_28 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_UART1_RXD__UART1_RXD (_MX51_PAD_UART1_RXD__UART1_RXD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) +#define MX51_PAD_UART1_TXD__GPIO4_29 (_MX51_PAD_UART1_TXD__GPIO4_29 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_UART1_TXD__PWM2_PWMO (_MX51_PAD_UART1_TXD__PWM2_PWMO | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_UART1_TXD__UART1_TXD (_MX51_PAD_UART1_TXD__UART1_TXD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) +#define MX51_PAD_UART1_RTS__GPIO4_30 (_MX51_PAD_UART1_RTS__GPIO4_30 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_UART1_RTS__UART1_RTS (_MX51_PAD_UART1_RTS__UART1_RTS | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) +#define MX51_PAD_UART1_CTS__GPIO4_31 (_MX51_PAD_UART1_CTS__GPIO4_31 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_UART1_CTS__UART1_CTS (_MX51_PAD_UART1_CTS__UART1_CTS | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) +#define MX51_PAD_UART2_RXD__FIRI_TXD (_MX51_PAD_UART2_RXD__FIRI_TXD | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_UART2_RXD__GPIO1_20 (_MX51_PAD_UART2_RXD__GPIO1_20 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_UART2_RXD__UART2_RXD (_MX51_PAD_UART2_RXD__UART2_RXD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) +#define MX51_PAD_UART2_TXD__FIRI_RXD (_MX51_PAD_UART2_TXD__FIRI_RXD | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_UART2_TXD__GPIO1_21 (_MX51_PAD_UART2_TXD__GPIO1_21 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_UART2_TXD__UART2_TXD (_MX51_PAD_UART2_TXD__UART2_TXD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) +#define MX51_PAD_UART3_RXD__CSI1_D0 (_MX51_PAD_UART3_RXD__CSI1_D0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_UART3_RXD__GPIO1_22 (_MX51_PAD_UART3_RXD__GPIO1_22 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_UART3_RXD__UART1_DTR (_MX51_PAD_UART3_RXD__UART1_DTR | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_UART3_RXD__UART3_RXD (_MX51_PAD_UART3_RXD__UART3_RXD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) +#define MX51_PAD_UART3_TXD__CSI1_D1 (_MX51_PAD_UART3_TXD__CSI1_D1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_UART3_TXD__GPIO1_23 (_MX51_PAD_UART3_TXD__GPIO1_23 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_UART3_TXD__UART1_DSR (_MX51_PAD_UART3_TXD__UART1_DSR | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) +#define MX51_PAD_UART3_TXD__UART3_TXD (_MX51_PAD_UART3_TXD__UART3_TXD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) +#define MX51_PAD_OWIRE_LINE__GPIO1_24 (_MX51_PAD_OWIRE_LINE__GPIO1_24 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_OWIRE_LINE__OWIRE_LINE (_MX51_PAD_OWIRE_LINE__OWIRE_LINE | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_OWIRE_LINE__SPDIF_OUT (_MX51_PAD_OWIRE_LINE__SPDIF_OUT | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_KEY_ROW0__KEY_ROW0 (_MX51_PAD_KEY_ROW0__KEY_ROW0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_KEY_ROW1__KEY_ROW1 (_MX51_PAD_KEY_ROW1__KEY_ROW1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_KEY_ROW2__KEY_ROW2 (_MX51_PAD_KEY_ROW2__KEY_ROW2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_KEY_ROW3__KEY_ROW3 (_MX51_PAD_KEY_ROW3__KEY_ROW3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_KEY_COL0__KEY_COL0 (_MX51_PAD_KEY_COL0__KEY_COL0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_KEY_COL0__PLL1_BYP (_MX51_PAD_KEY_COL0__PLL1_BYP | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_KEY_COL1__KEY_COL1 (_MX51_PAD_KEY_COL1__KEY_COL1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_KEY_COL1__PLL2_BYP (_MX51_PAD_KEY_COL1__PLL2_BYP | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_KEY_COL2__KEY_COL2 (_MX51_PAD_KEY_COL2__KEY_COL2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_KEY_COL2__PLL3_BYP (_MX51_PAD_KEY_COL2__PLL3_BYP | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_KEY_COL3__KEY_COL3 (_MX51_PAD_KEY_COL3__KEY_COL3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_KEY_COL4__I2C2_SCL (_MX51_PAD_KEY_COL4__I2C2_SCL | MUX_PAD_CTRL(MX51_I2C_PAD_CTRL)) +#define MX51_PAD_KEY_COL4__KEY_COL4 (_MX51_PAD_KEY_COL4__KEY_COL4 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_KEY_COL4__SPDIF_OUT1 (_MX51_PAD_KEY_COL4__SPDIF_OUT1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_KEY_COL4__UART1_RI (_MX51_PAD_KEY_COL4__UART1_RI | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) +#define MX51_PAD_KEY_COL4__UART3_RTS (_MX51_PAD_KEY_COL4__UART3_RTS | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) +#define MX51_PAD_KEY_COL5__I2C2_SDA (_MX51_PAD_KEY_COL5__I2C2_SDA | MUX_PAD_CTRL(MX51_I2C_PAD_CTRL)) +#define MX51_PAD_KEY_COL5__KEY_COL5 (_MX51_PAD_KEY_COL5__KEY_COL5 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_KEY_COL5__UART1_DCD (_MX51_PAD_KEY_COL5__UART1_DCD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) +#define MX51_PAD_KEY_COL5__UART3_CTS (_MX51_PAD_KEY_COL5__UART3_CTS | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) +#define MX51_PAD_USBH1_CLK__CSPI_SCLK (_MX51_PAD_USBH1_CLK__CSPI_SCLK | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) +#define MX51_PAD_USBH1_CLK__GPIO1_25 (_MX51_PAD_USBH1_CLK__GPIO1_25 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_USBH1_CLK__I2C2_SCL (_MX51_PAD_USBH1_CLK__I2C2_SCL | MUX_PAD_CTRL(MX51_I2C_PAD_CTRL)) +#define MX51_PAD_USBH1_CLK__USBH1_CLK (_MX51_PAD_USBH1_CLK__USBH1_CLK | MUX_PAD_CTRL(MX51_USBH1_PAD_CTRL)) +#define MX51_PAD_USBH1_DIR__CSPI_MOSI (_MX51_PAD_USBH1_DIR__CSPI_MOSI | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) +#define MX51_PAD_USBH1_DIR__GPIO1_26 (_MX51_PAD_USBH1_DIR__GPIO1_26 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_USBH1_DIR__I2C2_SDA (_MX51_PAD_USBH1_DIR__I2C2_SDA | MUX_PAD_CTRL(MX51_I2C_PAD_CTRL)) +#define MX51_PAD_USBH1_DIR__USBH1_DIR (_MX51_PAD_USBH1_DIR__USBH1_DIR | MUX_PAD_CTRL(MX51_USBH1_PAD_CTRL)) +#define MX51_PAD_USBH1_STP__CSPI_RDY (_MX51_PAD_USBH1_STP__CSPI_RDY | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) +#define MX51_PAD_USBH1_STP__GPIO1_27 (_MX51_PAD_USBH1_STP__GPIO1_27 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_USBH1_STP__UART3_RXD (_MX51_PAD_USBH1_STP__UART3_RXD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) +#define MX51_PAD_USBH1_STP__USBH1_STP (_MX51_PAD_USBH1_STP__USBH1_STP | MUX_PAD_CTRL(MX51_USBH1_PAD_CTRL)) +#define MX51_PAD_USBH1_NXT__CSPI_MISO (_MX51_PAD_USBH1_NXT__CSPI_MISO | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) +#define MX51_PAD_USBH1_NXT__GPIO1_28 (_MX51_PAD_USBH1_NXT__GPIO1_28 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_USBH1_NXT__UART3_TXD (_MX51_PAD_USBH1_NXT__UART3_TXD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) +#define MX51_PAD_USBH1_NXT__USBH1_NXT (_MX51_PAD_USBH1_NXT__USBH1_NXT | MUX_PAD_CTRL(MX51_USBH1_PAD_CTRL)) +#define MX51_PAD_USBH1_DATA0__GPIO1_11 (_MX51_PAD_USBH1_DATA0__GPIO1_11 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_USBH1_DATA0__UART2_CTS (_MX51_PAD_USBH1_DATA0__UART2_CTS | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) +#define MX51_PAD_USBH1_DATA0__USBH1_DATA0 (_MX51_PAD_USBH1_DATA0__USBH1_DATA0 | MUX_PAD_CTRL(MX51_USBH1_PAD_CTRL)) +#define MX51_PAD_USBH1_DATA1__GPIO1_12 (_MX51_PAD_USBH1_DATA1__GPIO1_12 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_USBH1_DATA1__UART2_RXD (_MX51_PAD_USBH1_DATA1__UART2_RXD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) +#define MX51_PAD_USBH1_DATA1__USBH1_DATA1 (_MX51_PAD_USBH1_DATA1__USBH1_DATA1 | MUX_PAD_CTRL(MX51_USBH1_PAD_CTRL)) +#define MX51_PAD_USBH1_DATA2__GPIO1_13 (_MX51_PAD_USBH1_DATA2__GPIO1_13 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_USBH1_DATA2__UART2_TXD (_MX51_PAD_USBH1_DATA2__UART2_TXD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) +#define MX51_PAD_USBH1_DATA2__USBH1_DATA2 (_MX51_PAD_USBH1_DATA2__USBH1_DATA2 | MUX_PAD_CTRL(MX51_USBH1_PAD_CTRL)) +#define MX51_PAD_USBH1_DATA3__GPIO1_14 (_MX51_PAD_USBH1_DATA3__GPIO1_14 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_USBH1_DATA3__UART2_RTS (_MX51_PAD_USBH1_DATA3__UART2_RTS | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) +#define MX51_PAD_USBH1_DATA3__USBH1_DATA3 (_MX51_PAD_USBH1_DATA3__USBH1_DATA3 | MUX_PAD_CTRL(MX51_USBH1_PAD_CTRL)) +#define MX51_PAD_USBH1_DATA4__CSPI_SS0 (_MX51_PAD_USBH1_DATA4__CSPI_SS0 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) +#define MX51_PAD_USBH1_DATA4__GPIO1_15 (_MX51_PAD_USBH1_DATA4__GPIO1_15 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_USBH1_DATA4__USBH1_DATA4 (_MX51_PAD_USBH1_DATA4__USBH1_DATA4 | MUX_PAD_CTRL(MX51_USBH1_PAD_CTRL)) +#define MX51_PAD_USBH1_DATA5__CSPI_SS1 (_MX51_PAD_USBH1_DATA5__CSPI_SS1 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) +#define MX51_PAD_USBH1_DATA5__GPIO1_16 (_MX51_PAD_USBH1_DATA5__GPIO1_16 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_USBH1_DATA5__USBH1_DATA5 (_MX51_PAD_USBH1_DATA5__USBH1_DATA5 | MUX_PAD_CTRL(MX51_USBH1_PAD_CTRL)) +#define MX51_PAD_USBH1_DATA6__CSPI_SS3 (_MX51_PAD_USBH1_DATA6__CSPI_SS3 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) +#define MX51_PAD_USBH1_DATA6__GPIO1_17 (_MX51_PAD_USBH1_DATA6__GPIO1_17 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_USBH1_DATA6__USBH1_DATA6 (_MX51_PAD_USBH1_DATA6__USBH1_DATA6 | MUX_PAD_CTRL(MX51_USBH1_PAD_CTRL)) +#define MX51_PAD_USBH1_DATA7__ECSPI1_SS3 (_MX51_PAD_USBH1_DATA7__ECSPI1_SS3 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) +#define MX51_PAD_USBH1_DATA7__ECSPI2_SS3 (_MX51_PAD_USBH1_DATA7__ECSPI2_SS3 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) +#define MX51_PAD_USBH1_DATA7__GPIO1_18 (_MX51_PAD_USBH1_DATA7__GPIO1_18 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_USBH1_DATA7__USBH1_DATA7 (_MX51_PAD_USBH1_DATA7__USBH1_DATA7 | MUX_PAD_CTRL(MX51_USBH1_PAD_CTRL)) +#define MX51_PAD_DI1_PIN11__DI1_PIN11 (_MX51_PAD_DI1_PIN11__DI1_PIN11 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DI1_PIN11__ECSPI1_SS2 (_MX51_PAD_DI1_PIN11__ECSPI1_SS2 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) +#define MX51_PAD_DI1_PIN11__GPIO3_0 (_MX51_PAD_DI1_PIN11__GPIO3_0 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_DI1_PIN12__DI1_PIN12 (_MX51_PAD_DI1_PIN12__DI1_PIN12 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DI1_PIN12__GPIO3_1 (_MX51_PAD_DI1_PIN12__GPIO3_1 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_DI1_PIN13__DI1_PIN13 (_MX51_PAD_DI1_PIN13__DI1_PIN13 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DI1_PIN13__GPIO3_2 (_MX51_PAD_DI1_PIN13__GPIO3_2 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_DI1_D0_CS__DI1_D0_CS (_MX51_PAD_DI1_D0_CS__DI1_D0_CS | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DI1_D0_CS__GPIO3_3 (_MX51_PAD_DI1_D0_CS__GPIO3_3 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_DI1_D1_CS__DI1_D1_CS (_MX51_PAD_DI1_D1_CS__DI1_D1_CS | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DI1_D1_CS__DISP1_PIN14 (_MX51_PAD_DI1_D1_CS__DISP1_PIN14 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DI1_D1_CS__DISP1_PIN5 (_MX51_PAD_DI1_D1_CS__DISP1_PIN5 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DI1_D1_CS__GPIO3_4 (_MX51_PAD_DI1_D1_CS__GPIO3_4 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_DISPB2_SER_DIN__DISP1_PIN1 (_MX51_PAD_DISPB2_SER_DIN__DISP1_PIN1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISPB2_SER_DIN__DISPB2_SER_DIN (_MX51_PAD_DISPB2_SER_DIN__DISPB2_SER_DIN | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISPB2_SER_DIN__GPIO3_5 (_MX51_PAD_DISPB2_SER_DIN__GPIO3_5 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_DISPB2_SER_DIO__DISP1_PIN6 (_MX51_PAD_DISPB2_SER_DIO__DISP1_PIN6 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISPB2_SER_DIO__DISPB2_SER_DIO (_MX51_PAD_DISPB2_SER_DIO__DISPB2_SER_DIO | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISPB2_SER_DIO__GPIO3_6 (_MX51_PAD_DISPB2_SER_DIO__GPIO3_6 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_DISPB2_SER_CLK__DISP1_PIN17 (_MX51_PAD_DISPB2_SER_CLK__DISP1_PIN17 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISPB2_SER_CLK__DISP1_PIN7 (_MX51_PAD_DISPB2_SER_CLK__DISP1_PIN7 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISPB2_SER_CLK__DISPB2_SER_CLK (_MX51_PAD_DISPB2_SER_CLK__DISPB2_SER_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISPB2_SER_CLK__GPIO3_7 (_MX51_PAD_DISPB2_SER_CLK__GPIO3_7 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_DISPB2_SER_RS__DISP1_EXT_CLK (_MX51_PAD_DISPB2_SER_RS__DISP1_EXT_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISPB2_SER_RS__DISP1_PIN16 (_MX51_PAD_DISPB2_SER_RS__DISP1_PIN16 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISPB2_SER_RS__DISP1_PIN8 (_MX51_PAD_DISPB2_SER_RS__DISP1_PIN8 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISPB2_SER_RS__DISPB2_SER_RS (_MX51_PAD_DISPB2_SER_RS__DISPB2_SER_RS | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISPB2_SER_RS__DISPB2_SER_RS (_MX51_PAD_DISPB2_SER_RS__DISPB2_SER_RS | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISPB2_SER_RS__GPIO3_8 (_MX51_PAD_DISPB2_SER_RS__GPIO3_8 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_DISP1_DAT0__DISP1_DAT0 (_MX51_PAD_DISP1_DAT0__DISP1_DAT0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP1_DAT1__DISP1_DAT1 (_MX51_PAD_DISP1_DAT1__DISP1_DAT1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP1_DAT2__DISP1_DAT2 (_MX51_PAD_DISP1_DAT2__DISP1_DAT2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP1_DAT3__DISP1_DAT3 (_MX51_PAD_DISP1_DAT3__DISP1_DAT3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP1_DAT4__DISP1_DAT4 (_MX51_PAD_DISP1_DAT4__DISP1_DAT4 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP1_DAT5__DISP1_DAT5 (_MX51_PAD_DISP1_DAT5__DISP1_DAT5 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP1_DAT6__BOOT_USB_SRC (_MX51_PAD_DISP1_DAT6__BOOT_USB_SRC | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP1_DAT6__DISP1_DAT6 (_MX51_PAD_DISP1_DAT6__DISP1_DAT6 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP1_DAT7__BOOT_EEPROM_CFG (_MX51_PAD_DISP1_DAT7__BOOT_EEPROM_CFG | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP1_DAT7__DISP1_DAT7 (_MX51_PAD_DISP1_DAT7__DISP1_DAT7 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP1_DAT8__BOOT_SRC0 (_MX51_PAD_DISP1_DAT8__BOOT_SRC0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP1_DAT8__DISP1_DAT8 (_MX51_PAD_DISP1_DAT8__DISP1_DAT8 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP1_DAT9__BOOT_SRC1 (_MX51_PAD_DISP1_DAT9__BOOT_SRC1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP1_DAT9__DISP1_DAT9 (_MX51_PAD_DISP1_DAT9__DISP1_DAT9 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP1_DAT10__BOOT_SPARE_SIZE (_MX51_PAD_DISP1_DAT10__BOOT_SPARE_SIZE | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP1_DAT10__DISP1_DAT10 (_MX51_PAD_DISP1_DAT10__DISP1_DAT10 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP1_DAT11__BOOT_LPB_FREQ2 (_MX51_PAD_DISP1_DAT11__BOOT_LPB_FREQ2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP1_DAT11__DISP1_DAT11 (_MX51_PAD_DISP1_DAT11__DISP1_DAT11 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP1_DAT12__BOOT_MLC_SEL (_MX51_PAD_DISP1_DAT12__BOOT_MLC_SEL | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP1_DAT12__DISP1_DAT12 (_MX51_PAD_DISP1_DAT12__DISP1_DAT12 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP1_DAT13__BOOT_MEM_CTL0 (_MX51_PAD_DISP1_DAT13__BOOT_MEM_CTL0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP1_DAT13__DISP1_DAT13 (_MX51_PAD_DISP1_DAT13__DISP1_DAT13 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP1_DAT14__BOOT_MEM_CTL1 (_MX51_PAD_DISP1_DAT14__BOOT_MEM_CTL1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP1_DAT14__DISP1_DAT14 (_MX51_PAD_DISP1_DAT14__DISP1_DAT14 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP1_DAT15__BOOT_BUS_WIDTH (_MX51_PAD_DISP1_DAT15__BOOT_BUS_WIDTH | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP1_DAT15__DISP1_DAT15 (_MX51_PAD_DISP1_DAT15__DISP1_DAT15 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP1_DAT16__BOOT_PAGE_SIZE0 (_MX51_PAD_DISP1_DAT16__BOOT_PAGE_SIZE0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP1_DAT16__DISP1_DAT16 (_MX51_PAD_DISP1_DAT16__DISP1_DAT16 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP1_DAT17__BOOT_PAGE_SIZE1 (_MX51_PAD_DISP1_DAT17__BOOT_PAGE_SIZE1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP1_DAT17__DISP1_DAT17 (_MX51_PAD_DISP1_DAT17__DISP1_DAT17 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP1_DAT18__BOOT_WEIM_MUXED0 (_MX51_PAD_DISP1_DAT18__BOOT_WEIM_MUXED0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP1_DAT18__DISP1_DAT18 (_MX51_PAD_DISP1_DAT18__DISP1_DAT18 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP1_DAT18__DISP2_PIN11 (_MX51_PAD_DISP1_DAT18__DISP2_PIN11 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP1_DAT18__DISP2_PIN5 (_MX51_PAD_DISP1_DAT18__DISP2_PIN5 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP1_DAT19__BOOT_WEIM_MUXED1 (_MX51_PAD_DISP1_DAT19__BOOT_WEIM_MUXED1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP1_DAT19__DISP1_DAT19 (_MX51_PAD_DISP1_DAT19__DISP1_DAT19 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP1_DAT19__DISP2_PIN12 (_MX51_PAD_DISP1_DAT19__DISP2_PIN12 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP1_DAT19__DISP2_PIN6 (_MX51_PAD_DISP1_DAT19__DISP2_PIN6 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP1_DAT20__BOOT_MEM_TYPE0 (_MX51_PAD_DISP1_DAT20__BOOT_MEM_TYPE0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP1_DAT20__DISP1_DAT20 (_MX51_PAD_DISP1_DAT20__DISP1_DAT20 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP1_DAT20__DISP2_PIN13 (_MX51_PAD_DISP1_DAT20__DISP2_PIN13 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP1_DAT20__DISP2_PIN7 (_MX51_PAD_DISP1_DAT20__DISP2_PIN7 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP1_DAT21__BOOT_MEM_TYPE1 (_MX51_PAD_DISP1_DAT21__BOOT_MEM_TYPE1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP1_DAT21__DISP1_DAT21 (_MX51_PAD_DISP1_DAT21__DISP1_DAT21 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP1_DAT21__DISP2_PIN14 (_MX51_PAD_DISP1_DAT21__DISP2_PIN14 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP1_DAT21__DISP2_PIN8 (_MX51_PAD_DISP1_DAT21__DISP2_PIN8 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP1_DAT22__BOOT_LPB_FREQ0 (_MX51_PAD_DISP1_DAT22__BOOT_LPB_FREQ0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP1_DAT22__DISP1_DAT22 (_MX51_PAD_DISP1_DAT22__DISP1_DAT22 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP1_DAT22__DISP2_D0_CS (_MX51_PAD_DISP1_DAT22__DISP2_D0_CS | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP1_DAT22__DISP2_DAT16 (_MX51_PAD_DISP1_DAT22__DISP2_DAT16 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP1_DAT23__BOOT_LPB_FREQ1 (_MX51_PAD_DISP1_DAT23__BOOT_LPB_FREQ1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP1_DAT23__DISP1_DAT23 (_MX51_PAD_DISP1_DAT23__DISP1_DAT23 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP1_DAT23__DISP2_D1_CS (_MX51_PAD_DISP1_DAT23__DISP2_D1_CS | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP1_DAT23__DISP2_DAT17 (_MX51_PAD_DISP1_DAT23__DISP2_DAT17 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP1_DAT23__DISP2_SER_CS (_MX51_PAD_DISP1_DAT23__DISP2_SER_CS | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DI1_PIN3__DI1_PIN3 (_MX51_PAD_DI1_PIN3__DI1_PIN3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DI1_PIN2__DI1_PIN2 (_MX51_PAD_DI1_PIN2__DI1_PIN2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DI_GP2__DISP1_SER_CLK (_MX51_PAD_DI_GP2__DISP1_SER_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DI_GP2__DISP2_WAIT (_MX51_PAD_DI_GP2__DISP2_WAIT | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DI_GP3__CSI1_DATA_EN (_MX51_PAD_DI_GP3__CSI1_DATA_EN | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DI_GP3__DISP1_SER_DIO (_MX51_PAD_DI_GP3__DISP1_SER_DIO | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DI_GP3__FEC_TX_ER (_MX51_PAD_DI_GP3__FEC_TX_ER | MUX_PAD_CTRL(MX51_PAD_CTRL_5)) +#define MX51_PAD_DI2_PIN4__CSI2_DATA_EN (_MX51_PAD_DI2_PIN4__CSI2_DATA_EN | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DI2_PIN4__DI2_PIN4 (_MX51_PAD_DI2_PIN4__DI2_PIN4 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DI2_PIN4__FEC_CRS (_MX51_PAD_DI2_PIN4__FEC_CRS | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DI2_PIN2__DI2_PIN2 (_MX51_PAD_DI2_PIN2__DI2_PIN2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DI2_PIN2__FEC_MDC (_MX51_PAD_DI2_PIN2__FEC_MDC | MUX_PAD_CTRL(MX51_PAD_CTRL_5)) +#define MX51_PAD_DI2_PIN3__DI2_PIN3 (_MX51_PAD_DI2_PIN3__DI2_PIN3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DI2_PIN3__FEC_MDIO (_MX51_PAD_DI2_PIN3__FEC_MDIO | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK (_MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 (_MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DI_GP4__DI2_PIN15 (_MX51_PAD_DI_GP4__DI2_PIN15 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DI_GP4__DISP1_SER_DIN (_MX51_PAD_DI_GP4__DISP1_SER_DIN | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DI_GP4__DISP2_PIN1 (_MX51_PAD_DI_GP4__DISP2_PIN1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DI_GP4__FEC_RDATA2 (_MX51_PAD_DI_GP4__FEC_RDATA2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP2_DAT0__DISP2_DAT0 (_MX51_PAD_DISP2_DAT0__DISP2_DAT0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP2_DAT0__FEC_RDATA3 (_MX51_PAD_DISP2_DAT0__FEC_RDATA3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP2_DAT0__KEY_COL6 (_MX51_PAD_DISP2_DAT0__KEY_COL6 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP2_DAT0__UART3_RXD (_MX51_PAD_DISP2_DAT0__UART3_RXD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) +#define MX51_PAD_DISP2_DAT0__USBH3_CLK (_MX51_PAD_DISP2_DAT0__USBH3_CLK | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) +#define MX51_PAD_DISP2_DAT1__DISP2_DAT1 (_MX51_PAD_DISP2_DAT1__DISP2_DAT1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP2_DAT1__FEC_RX_ER (_MX51_PAD_DISP2_DAT1__FEC_RX_ER | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP2_DAT1__KEY_COL7 (_MX51_PAD_DISP2_DAT1__KEY_COL7 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP2_DAT1__UART3_TXD (_MX51_PAD_DISP2_DAT1__UART3_TXD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) +#define MX51_PAD_DISP2_DAT1__USBH3_DIR (_MX51_PAD_DISP2_DAT1__USBH3_DIR | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP2_DAT2__DISP2_DAT2 (_MX51_PAD_DISP2_DAT2__DISP2_DAT2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP2_DAT3__DISP2_DAT3 (_MX51_PAD_DISP2_DAT3__DISP2_DAT3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP2_DAT4__DISP2_DAT4 (_MX51_PAD_DISP2_DAT4__DISP2_DAT4 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP2_DAT5__DISP2_DAT5 (_MX51_PAD_DISP2_DAT5__DISP2_DAT5 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP2_DAT6__DISP2_DAT6 (_MX51_PAD_DISP2_DAT6__DISP2_DAT6 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP2_DAT6__FEC_TDATA1 (_MX51_PAD_DISP2_DAT6__FEC_TDATA1 | MUX_PAD_CTRL(MX51_PAD_CTRL_5)) +#define MX51_PAD_DISP2_DAT6__GPIO1_19 (_MX51_PAD_DISP2_DAT6__GPIO1_19 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP2_DAT6__KEY_ROW4 (_MX51_PAD_DISP2_DAT6__KEY_ROW4 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP2_DAT6__USBH3_STP (_MX51_PAD_DISP2_DAT6__USBH3_STP | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP2_DAT7__DISP2_DAT7 (_MX51_PAD_DISP2_DAT7__DISP2_DAT7 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP2_DAT7__FEC_TDATA2 (_MX51_PAD_DISP2_DAT7__FEC_TDATA2 | MUX_PAD_CTRL(MX51_PAD_CTRL_5)) +#define MX51_PAD_DISP2_DAT7__GPIO1_29 (_MX51_PAD_DISP2_DAT7__GPIO1_29 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP2_DAT7__KEY_ROW5 (_MX51_PAD_DISP2_DAT7__KEY_ROW5 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP2_DAT7__USBH3_NXT (_MX51_PAD_DISP2_DAT7__USBH3_NXT | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP2_DAT8__DISP2_DAT8 (_MX51_PAD_DISP2_DAT8__DISP2_DAT8 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP2_DAT8__FEC_TDATA3 (_MX51_PAD_DISP2_DAT8__FEC_TDATA3 | MUX_PAD_CTRL(MX51_PAD_CTRL_5)) +#define MX51_PAD_DISP2_DAT8__GPIO1_30 (_MX51_PAD_DISP2_DAT8__GPIO1_30 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP2_DAT8__KEY_ROW6 (_MX51_PAD_DISP2_DAT8__KEY_ROW6 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP2_DAT8__USBH3_DATA0 (_MX51_PAD_DISP2_DAT8__USBH3_DATA0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP2_DAT9__AUD6_RXC (_MX51_PAD_DISP2_DAT9__AUD6_RXC | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP2_DAT9__DISP2_DAT9 (_MX51_PAD_DISP2_DAT9__DISP2_DAT9 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP2_DAT9__FEC_TX_EN (_MX51_PAD_DISP2_DAT9__FEC_TX_EN | MUX_PAD_CTRL(MX51_PAD_CTRL_5)) +#define MX51_PAD_DISP2_DAT9__GPIO1_31 (_MX51_PAD_DISP2_DAT9__GPIO1_31 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP2_DAT9__USBH3_DATA1 (_MX51_PAD_DISP2_DAT9__USBH3_DATA1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP2_DAT10__DISP2_DAT10 (_MX51_PAD_DISP2_DAT10__DISP2_DAT10 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP2_DAT10__DISP2_SER_CS (_MX51_PAD_DISP2_DAT10__DISP2_SER_CS | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP2_DAT10__FEC_COL (_MX51_PAD_DISP2_DAT10__FEC_COL | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP2_DAT10__KEY_ROW7 (_MX51_PAD_DISP2_DAT10__KEY_ROW7 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP2_DAT10__USBH3_DATA2 (_MX51_PAD_DISP2_DAT10__USBH3_DATA2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP2_DAT11__AUD6_TXD (_MX51_PAD_DISP2_DAT11__AUD6_TXD | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP2_DAT11__DISP2_DAT11 (_MX51_PAD_DISP2_DAT11__DISP2_DAT11 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP2_DAT11__FEC_RX_CLK (_MX51_PAD_DISP2_DAT11__FEC_RX_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP2_DAT11__GPIO1_10 (_MX51_PAD_DISP2_DAT11__GPIO1_10 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP2_DAT11__USBH3_DATA3 (_MX51_PAD_DISP2_DAT11__USBH3_DATA3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP2_DAT12__AUD6_RXD (_MX51_PAD_DISP2_DAT12__AUD6_RXD | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP2_DAT12__DISP2_DAT12 (_MX51_PAD_DISP2_DAT12__DISP2_DAT12 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP2_DAT12__FEC_RX_DV (_MX51_PAD_DISP2_DAT12__FEC_RX_DV | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP2_DAT12__USBH3_DATA4 (_MX51_PAD_DISP2_DAT12__USBH3_DATA4 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP2_DAT13__AUD6_TXC (_MX51_PAD_DISP2_DAT13__AUD6_TXC | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP2_DAT13__DISP2_DAT13 (_MX51_PAD_DISP2_DAT13__DISP2_DAT13 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP2_DAT13__FEC_TX_CLK (_MX51_PAD_DISP2_DAT13__FEC_TX_CLK | MUX_PAD_CTRL(MX51_PAD_CTRL_4)) +#define MX51_PAD_DISP2_DAT13__USBH3_DATA5 (_MX51_PAD_DISP2_DAT13__USBH3_DATA5 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP2_DAT14__AUD6_TXFS (_MX51_PAD_DISP2_DAT14__AUD6_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP2_DAT14__DISP2_DAT14 (_MX51_PAD_DISP2_DAT14__DISP2_DAT14 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP2_DAT14__FEC_RDATA0 (_MX51_PAD_DISP2_DAT14__FEC_RDATA0 | MUX_PAD_CTRL(MX51_PAD_CTRL_4)) +#define MX51_PAD_DISP2_DAT14__USBH3_DATA6 (_MX51_PAD_DISP2_DAT14__USBH3_DATA6 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP2_DAT15__AUD6_RXFS (_MX51_PAD_DISP2_DAT15__AUD6_RXFS | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP2_DAT15__DISP1_SER_CS (_MX51_PAD_DISP2_DAT15__DISP1_SER_CS | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP2_DAT15__DISP2_DAT15 (_MX51_PAD_DISP2_DAT15__DISP2_DAT15 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP2_DAT15__FEC_TDATA0 (_MX51_PAD_DISP2_DAT15__FEC_TDATA0 | MUX_PAD_CTRL(MX51_PAD_CTRL_5)) +#define MX51_PAD_DISP2_DAT15__USBH3_DATA7 (_MX51_PAD_DISP2_DAT15__USBH3_DATA7 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_SD1_CMD__AUD5_RXFS (_MX51_PAD_SD1_CMD__AUD5_RXFS | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_SD1_CMD__CSPI_MOSI (_MX51_PAD_SD1_CMD__CSPI_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_SD1_CMD__SD1_CMD (_MX51_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL)) +#define MX51_PAD_SD1_CLK__AUD5_RXC (_MX51_PAD_SD1_CLK__AUD5_RXC | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_SD1_CLK__CSPI_SCLK (_MX51_PAD_SD1_CLK__CSPI_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_SD1_CLK__SD1_CLK (_MX51_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL | PAD_CTL_HYS)) +#define MX51_PAD_SD1_DATA0__AUD5_TXD (_MX51_PAD_SD1_DATA0__AUD5_TXD | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_SD1_DATA0__CSPI_MISO (_MX51_PAD_SD1_DATA0__CSPI_MISO | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) +#define MX51_PAD_SD1_DATA0__SD1_DATA0 (_MX51_PAD_SD1_DATA0__SD1_DATA0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_DA0__EIM_DA0 (_MX51_PAD_EIM_DA0__EIM_DA0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_DA1__EIM_DA1 (_MX51_PAD_EIM_DA1__EIM_DA1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_DA2__EIM_DA2 (_MX51_PAD_EIM_DA2__EIM_DA2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_DA3__EIM_DA3 (_MX51_PAD_EIM_DA3__EIM_DA3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_SD1_DATA1__AUD5_RXD (_MX51_PAD_SD1_DATA1__AUD5_RXD | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_SD1_DATA1__SD1_DATA1 (_MX51_PAD_SD1_DATA1__SD1_DATA1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_DA4__EIM_DA4 (_MX51_PAD_EIM_DA4__EIM_DA4 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_DA5__EIM_DA5 (_MX51_PAD_EIM_DA5__EIM_DA5 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_DA6__EIM_DA6 (_MX51_PAD_EIM_DA6__EIM_DA6 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_DA7__EIM_DA7 (_MX51_PAD_EIM_DA7__EIM_DA7 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_SD1_DATA2__AUD5_TXC (_MX51_PAD_SD1_DATA2__AUD5_TXC | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_SD1_DATA2__SD1_DATA2 (_MX51_PAD_SD1_DATA2__SD1_DATA2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_DA10__EIM_DA10 (_MX51_PAD_EIM_DA10__EIM_DA10 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_DA11__EIM_DA11 (_MX51_PAD_EIM_DA11__EIM_DA11 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_DA8__EIM_DA8 (_MX51_PAD_EIM_DA8__EIM_DA8 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_DA9__EIM_DA9 (_MX51_PAD_EIM_DA9__EIM_DA9 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_SD1_DATA3__AUD5_TXFS (_MX51_PAD_SD1_DATA3__AUD5_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_SD1_DATA3__CSPI_SS1 (_MX51_PAD_SD1_DATA3__CSPI_SS1 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) +#define MX51_PAD_SD1_DATA3__SD1_DATA3 (_MX51_PAD_SD1_DATA3__SD1_DATA3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_GPIO1_0__CSPI_SS2 (_MX51_PAD_GPIO1_0__CSPI_SS2 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) +#define MX51_PAD_GPIO1_0__GPIO1_0 (_MX51_PAD_GPIO1_0__GPIO1_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_GPIO1_0__SD1_CD (_MX51_PAD_GPIO1_0__SD1_CD | MUX_PAD_CTRL(MX51_ESDHC_PAD_CTRL)) +#define MX51_PAD_GPIO1_1__CSPI_MISO (_MX51_PAD_GPIO1_1__CSPI_MISO | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) +#define MX51_PAD_GPIO1_1__GPIO1_1 (_MX51_PAD_GPIO1_1__GPIO1_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_GPIO1_1__SD1_WP (_MX51_PAD_GPIO1_1__SD1_WP | MUX_PAD_CTRL(MX51_ESDHC_PAD_CTRL)) +#define MX51_PAD_EIM_DA12__EIM_DA12 (_MX51_PAD_EIM_DA12__EIM_DA12 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_DA13__EIM_DA13 (_MX51_PAD_EIM_DA13__EIM_DA13 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_DA14__EIM_DA14 (_MX51_PAD_EIM_DA14__EIM_DA14 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_DA15__EIM_DA15 (_MX51_PAD_EIM_DA15__EIM_DA15 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_SD2_CMD__CSPI_MOSI (_MX51_PAD_SD2_CMD__CSPI_MOSI | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) +#define MX51_PAD_SD2_CMD__I2C1_SCL (_MX51_PAD_SD2_CMD__I2C1_SCL | MUX_PAD_CTRL(MX51_I2C_PAD_CTRL)) +#define MX51_PAD_SD2_CMD__SD2_CMD (_MX51_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL)) +#define MX51_PAD_SD2_CLK__CSPI_SCLK (_MX51_PAD_SD2_CLK__CSPI_SCLK | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) +#define MX51_PAD_SD2_CLK__I2C1_SDA (_MX51_PAD_SD2_CLK__I2C1_SDA | MUX_PAD_CTRL(MX51_I2C_PAD_CTRL)) +#define MX51_PAD_SD2_CLK__SD2_CLK (_MX51_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL | PAD_CTL_HYS)) +#define MX51_PAD_SD2_DATA0__CSPI_MISO (_MX51_PAD_SD2_DATA0__CSPI_MISO | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) +#define MX51_PAD_SD2_DATA0__SD1_DAT4 (_MX51_PAD_SD2_DATA0__SD1_DAT4 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_SD2_DATA0__SD2_DATA0 (_MX51_PAD_SD2_DATA0__SD2_DATA0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_SD2_DATA1__SD1_DAT5 (_MX51_PAD_SD2_DATA1__SD1_DAT5 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_SD2_DATA1__SD2_DATA1 (_MX51_PAD_SD2_DATA1__SD2_DATA1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_SD2_DATA1__USBH3_H2_DP (_MX51_PAD_SD2_DATA1__USBH3_H2_DP | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_SD2_DATA2__SD1_DAT6 (_MX51_PAD_SD2_DATA2__SD1_DAT6 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_SD2_DATA2__SD2_DATA2 (_MX51_PAD_SD2_DATA2__SD2_DATA2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_SD2_DATA2__USBH3_H2_DM (_MX51_PAD_SD2_DATA2__USBH3_H2_DM | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_SD2_DATA3__CSPI_SS2 (_MX51_PAD_SD2_DATA3__CSPI_SS2 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) +#define MX51_PAD_SD2_DATA3__SD1_DAT7 (_MX51_PAD_SD2_DATA3__SD1_DAT7 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_SD2_DATA3__SD2_DATA3 (_MX51_PAD_SD2_DATA3__SD2_DATA3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_GPIO1_2__CCM_OUT_2 (_MX51_PAD_GPIO1_2__CCM_OUT_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_GPIO1_2__GPIO1_2 (_MX51_PAD_GPIO1_2__GPIO1_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_GPIO1_2__I2C2_SCL (_MX51_PAD_GPIO1_2__I2C2_SCL | MUX_PAD_CTRL(MX51_I2C_PAD_CTRL)) +#define MX51_PAD_GPIO1_2__PLL1_BYP (_MX51_PAD_GPIO1_2__PLL1_BYP | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_GPIO1_2__PWM1_PWMO (_MX51_PAD_GPIO1_2__PWM1_PWMO | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_GPIO1_3__GPIO1_3 (_MX51_PAD_GPIO1_3__GPIO1_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_GPIO1_3__I2C2_SDA (_MX51_PAD_GPIO1_3__I2C2_SDA | MUX_PAD_CTRL(MX51_I2C_PAD_CTRL)) +#define MX51_PAD_GPIO1_3__PLL2_BYP (_MX51_PAD_GPIO1_3__PLL2_BYP | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_GPIO1_3__PWM2_PWMO (_MX51_PAD_GPIO1_3__PWM2_PWMO | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_PMIC_INT_REQ__PMIC_INT_REQ (_MX51_PAD_PMIC_INT_REQ__PMIC_INT_REQ | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_PMIC_INT_REQ__PMIC_PMU_IRQ_B (_MX51_PAD_PMIC_INT_REQ__PMIC_PMU_IRQ_B | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_GPIO1_4__DISP2_EXT_CLK (_MX51_PAD_GPIO1_4__DISP2_EXT_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_GPIO1_4__EIM_RDY (_MX51_PAD_GPIO1_4__EIM_RDY | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_GPIO1_4__GPIO1_4 (_MX51_PAD_GPIO1_4__GPIO1_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_GPIO1_4__WDOG1_WDOG_B (_MX51_PAD_GPIO1_4__WDOG1_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_GPIO1_5__CSI2_MCLK (_MX51_PAD_GPIO1_5__CSI2_MCLK | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_GPIO1_5__DISP2_PIN16 (_MX51_PAD_GPIO1_5__DISP2_PIN16 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_GPIO1_5__GPIO1_5 (_MX51_PAD_GPIO1_5__GPIO1_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_GPIO1_5__WDOG2_WDOG_B (_MX51_PAD_GPIO1_5__WDOG2_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_GPIO1_6__DISP2_PIN17 (_MX51_PAD_GPIO1_6__DISP2_PIN17 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_GPIO1_6__GPIO1_6 (_MX51_PAD_GPIO1_6__GPIO1_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_GPIO1_6__REF_EN_B (_MX51_PAD_GPIO1_6__REF_EN_B | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_GPIO1_7__CCM_OUT_0 (_MX51_PAD_GPIO1_7__CCM_OUT_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_GPIO1_7__GPIO1_7 (_MX51_PAD_GPIO1_7__GPIO1_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_GPIO1_7__SD2_WP (_MX51_PAD_GPIO1_7__SD2_WP | MUX_PAD_CTRL(MX51_ESDHC_PAD_CTRL)) +#define MX51_PAD_GPIO1_7__SPDIF_OUT1 (_MX51_PAD_GPIO1_7__SPDIF_OUT1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_GPIO1_8__CSI2_DATA_EN (_MX51_PAD_GPIO1_8__CSI2_DATA_EN | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_GPIO1_8__GPIO1_8 (_MX51_PAD_GPIO1_8__GPIO1_8 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_GPIO1_8__SD2_CD (_MX51_PAD_GPIO1_8__SD2_CD | MUX_PAD_CTRL(MX51_ESDHC_PAD_CTRL)) +#define MX51_PAD_GPIO1_8__USBH3_PWR (_MX51_PAD_GPIO1_8__USBH3_PWR | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_GPIO1_9__CCM_OUT_1 (_MX51_PAD_GPIO1_9__CCM_OUT_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_GPIO1_9__DISP2_D1_CS (_MX51_PAD_GPIO1_9__DISP2_D1_CS | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_GPIO1_9__DISP2_SER_CS (_MX51_PAD_GPIO1_9__DISP2_SER_CS | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_GPIO1_9__GPIO1_9 (_MX51_PAD_GPIO1_9__GPIO1_9 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_GPIO1_9__SD2_LCTL (_MX51_PAD_GPIO1_9__SD2_LCTL | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_GPIO1_9__USBH3_OC (_MX51_PAD_GPIO1_9__USBH3_OC | MUX_PAD_CTRL(NO_PAD_CTRL)) #endif /* __MACH_IOMUX_MX51_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/iomux-v3.h b/arch/arm/plat-mxc/include/mach/iomux-v3.h index 1462a1c..2277b01 100644 --- a/arch/arm/plat-mxc/include/mach/iomux-v3.h +++ b/arch/arm/plat-mxc/include/mach/iomux-v3.h @@ -70,6 +70,8 @@ typedef u64 iomux_v3_cfg_t; #define MUX_SEL_INPUT_SHIFT 58 #define MUX_SEL_INPUT_MASK ((iomux_v3_cfg_t)0xf << MUX_SEL_INPUT_SHIFT) +#define MUX_PAD_CTRL(x) ((iomux_v3_cfg_t)(x) << MUX_PAD_CTRL_SHIFT) + #define IOMUX_PAD(_pad_ctrl_ofs, _mux_ctrl_ofs, _mux_mode, _sel_input_ofs, \ _sel_input, _pad_ctrl) \ (((iomux_v3_cfg_t)(_mux_ctrl_ofs) << MUX_CTRL_OFS_SHIFT) | \ -- cgit v1.1 From b086e97b20f150e81609a04ed7da92e12d77f1b0 Mon Sep 17 00:00:00 2001 From: Richard Zhao Date: Thu, 30 Dec 2010 19:25:01 +0800 Subject: arm: plat-mxc: add full parameter macro to define gpio port MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Richard Zhao Acked-by: Uwe Kleine-König Signed-off-by: Sascha Hauer --- arch/arm/plat-mxc/gpio.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) (limited to 'arch/arm/plat-mxc') diff --git a/arch/arm/plat-mxc/gpio.c b/arch/arm/plat-mxc/gpio.c index 93a8d93..dd4f813 100644 --- a/arch/arm/plat-mxc/gpio.c +++ b/arch/arm/plat-mxc/gpio.c @@ -350,15 +350,18 @@ int __init mxc_gpio_init(struct mxc_gpio_port *port, int cnt) return 0; } -#define DEFINE_IMX_GPIO_PORT_IRQ(soc, _id, _hwid, _irq) \ +#define DEFINE_IMX_GPIO_PORT_IRQ_HIGH(soc, _id, _hwid, _irq, _irq_high) \ { \ .chip.label = "gpio-" #_id, \ .irq = _irq, \ + .irq_high = _irq_high, \ .base = soc ## _IO_ADDRESS( \ soc ## _GPIO ## _hwid ## _BASE_ADDR), \ .virtual_irq_start = MXC_GPIO_IRQ_START + (_id) * 32, \ } +#define DEFINE_IMX_GPIO_PORT_IRQ(soc, _id, _hwid, _irq) \ + DEFINE_IMX_GPIO_PORT_IRQ_HIGH(soc, _id, _hwid, _irq, 0) #define DEFINE_IMX_GPIO_PORT(soc, _id, _hwid) \ DEFINE_IMX_GPIO_PORT_IRQ(soc, _id, _hwid, 0) -- cgit v1.1 From dca3abf8d071cb78bac8c8f50259e9fe3a81a4bd Mon Sep 17 00:00:00 2001 From: Richard Zhao Date: Thu, 30 Dec 2010 19:25:02 +0800 Subject: arm: mx51: define mx51's own MXC_GPIO_IRQS MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit mx5 SoCs have different GPIO port count. Signed-off-by: Richard Zhao Acked-by: Uwe Kleine-König Signed-off-by: Sascha Hauer --- arch/arm/plat-mxc/include/mach/irqs.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm/plat-mxc') diff --git a/arch/arm/plat-mxc/include/mach/irqs.h b/arch/arm/plat-mxc/include/mach/irqs.h index 86781f7..769a137 100644 --- a/arch/arm/plat-mxc/include/mach/irqs.h +++ b/arch/arm/plat-mxc/include/mach/irqs.h @@ -29,7 +29,7 @@ #define MXC_GPIO_IRQS (32 * 4) #elif defined CONFIG_ARCH_MX25 #define MXC_GPIO_IRQS (32 * 4) -#elif defined CONFIG_ARCH_MX5 +#elif defined CONFIG_ARCH_MX51 #define MXC_GPIO_IRQS (32 * 4) #elif defined CONFIG_ARCH_MXC91231 #define MXC_GPIO_IRQS (32 * 4) -- cgit v1.1 From 02226a20bcfb01322d4a168f2ed6a6e4366796fd Mon Sep 17 00:00:00 2001 From: Richard Zhao Date: Thu, 30 Dec 2010 19:25:03 +0800 Subject: arm: mx5: mx51/53 have different mxc_cpu_type definition MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Richard Zhao Acked-by: Uwe Kleine-König Signed-off-by: Sascha Hauer --- arch/arm/plat-mxc/include/mach/mxc.h | 15 +++++++++++++-- 1 file changed, 13 insertions(+), 2 deletions(-) (limited to 'arch/arm/plat-mxc') diff --git a/arch/arm/plat-mxc/include/mach/mxc.h b/arch/arm/plat-mxc/include/mach/mxc.h index 4abbdd1..eca8f83 100644 --- a/arch/arm/plat-mxc/include/mach/mxc.h +++ b/arch/arm/plat-mxc/include/mach/mxc.h @@ -126,7 +126,7 @@ extern unsigned int __mxc_cpu_type; # define cpu_is_mx35() (0) #endif -#ifdef CONFIG_ARCH_MX5 +#ifdef CONFIG_ARCH_MX51 # ifdef mxc_cpu_type # undef mxc_cpu_type # define mxc_cpu_type __mxc_cpu_type @@ -134,11 +134,22 @@ extern unsigned int __mxc_cpu_type; # define mxc_cpu_type MXC_CPU_MX51 # endif # define cpu_is_mx51() (mxc_cpu_type == MXC_CPU_MX51) -# define cpu_is_mx53() (mxc_cpu_type == MXC_CPU_MX53) #else # define cpu_is_mx51() (0) #endif +#ifdef CONFIG_ARCH_MX53 +# ifdef mxc_cpu_type +# undef mxc_cpu_type +# define mxc_cpu_type __mxc_cpu_type +# else +# define mxc_cpu_type MXC_CPU_MX53 +# endif +# define cpu_is_mx53() (mxc_cpu_type == MXC_CPU_MX53) +#else +# define cpu_is_mx53() (0) +#endif + #ifdef CONFIG_ARCH_MXC91231 # ifdef mxc_cpu_type # undef mxc_cpu_type -- cgit v1.1 From 3d5a44be308203a9a192a77037fb613c2f82ed85 Mon Sep 17 00:00:00 2001 From: Richard Zhao Date: Thu, 30 Dec 2010 19:25:05 +0800 Subject: arm: mx50: add core functions support except clock Add core definitions and memory map, gpio, irq, iomux, uart device support. Signed-off-by: Richard Zhao Signed-off-by: Sascha Hauer --- arch/arm/plat-mxc/devices/platform-imx-uart.c | 12 + arch/arm/plat-mxc/gpio.c | 14 + arch/arm/plat-mxc/include/mach/common.h | 2 + arch/arm/plat-mxc/include/mach/hardware.h | 6 + arch/arm/plat-mxc/include/mach/iomux-mx50.h | 977 ++++++++++++++++++++++++++ arch/arm/plat-mxc/include/mach/irqs.h | 2 + arch/arm/plat-mxc/include/mach/memory.h | 3 + arch/arm/plat-mxc/include/mach/mx50.h | 285 ++++++++ arch/arm/plat-mxc/include/mach/mxc.h | 13 + 9 files changed, 1314 insertions(+) create mode 100644 arch/arm/plat-mxc/include/mach/iomux-mx50.h create mode 100644 arch/arm/plat-mxc/include/mach/mx50.h (limited to 'arch/arm/plat-mxc') diff --git a/arch/arm/plat-mxc/devices/platform-imx-uart.c b/arch/arm/plat-mxc/devices/platform-imx-uart.c index 7b45b78..0c69fbc 100644 --- a/arch/arm/plat-mxc/devices/platform-imx-uart.c +++ b/arch/arm/plat-mxc/devices/platform-imx-uart.c @@ -94,6 +94,18 @@ const struct imx_imx_uart_1irq_data imx35_imx_uart_data[] __initconst = { }; #endif /* ifdef CONFIG_SOC_IMX35 */ +#ifdef CONFIG_SOC_IMX50 +const struct imx_imx_uart_1irq_data imx50_imx_uart_data[] __initconst = { +#define imx50_imx_uart_data_entry(_id, _hwid) \ + imx_imx_uart_1irq_data_entry(MX50, _id, _hwid, SZ_4K) + imx50_imx_uart_data_entry(0, 1), + imx50_imx_uart_data_entry(1, 2), + imx50_imx_uart_data_entry(2, 3), + imx50_imx_uart_data_entry(3, 4), + imx50_imx_uart_data_entry(4, 5), +}; +#endif /* ifdef CONFIG_SOC_IMX50 */ + #ifdef CONFIG_SOC_IMX51 const struct imx_imx_uart_1irq_data imx51_imx_uart_data[] __initconst = { #define imx51_imx_uart_data_entry(_id, _hwid) \ diff --git a/arch/arm/plat-mxc/gpio.c b/arch/arm/plat-mxc/gpio.c index dd4f813..bc2c7bc 100644 --- a/arch/arm/plat-mxc/gpio.c +++ b/arch/arm/plat-mxc/gpio.c @@ -445,3 +445,17 @@ static struct mxc_gpio_port imx35_gpio_ports[] = { DEFINE_REGISTER_FUNCTION(imx35) #endif /* if defined(CONFIG_SOC_IMX35) */ + +#if defined(CONFIG_SOC_IMX50) +static struct mxc_gpio_port imx50_gpio_ports[] = { + DEFINE_IMX_GPIO_PORT_IRQ_HIGH(MX50, 0, 1, MX50_INT_GPIO1_LOW, MX50_INT_GPIO1_HIGH), + DEFINE_IMX_GPIO_PORT_IRQ_HIGH(MX50, 1, 2, MX50_INT_GPIO2_LOW, MX50_INT_GPIO2_HIGH), + DEFINE_IMX_GPIO_PORT_IRQ_HIGH(MX50, 2, 3, MX50_INT_GPIO3_LOW, MX50_INT_GPIO3_HIGH), + DEFINE_IMX_GPIO_PORT_IRQ_HIGH(MX50, 3, 4, MX50_INT_GPIO3_LOW, MX50_INT_GPIO3_HIGH), + DEFINE_IMX_GPIO_PORT_IRQ_HIGH(MX50, 4, 5, MX50_INT_GPIO3_LOW, MX50_INT_GPIO3_HIGH), + DEFINE_IMX_GPIO_PORT_IRQ_HIGH(MX50, 5, 6, MX50_INT_GPIO3_LOW, MX50_INT_GPIO3_HIGH), +}; + +DEFINE_REGISTER_FUNCTION(imx50) + +#endif /* if defined(CONFIG_SOC_IMX50) */ diff --git a/arch/arm/plat-mxc/include/mach/common.h b/arch/arm/plat-mxc/include/mach/common.h index 9d58ce5..aea2cd3 100644 --- a/arch/arm/plat-mxc/include/mach/common.h +++ b/arch/arm/plat-mxc/include/mach/common.h @@ -20,6 +20,7 @@ extern void mx25_map_io(void); extern void mx27_map_io(void); extern void mx31_map_io(void); extern void mx35_map_io(void); +extern void mx50_map_io(void); extern void mx51_map_io(void); extern void mx53_map_io(void); extern void mxc91231_map_io(void); @@ -31,6 +32,7 @@ extern void mx25_init_irq(void); extern void mx27_init_irq(void); extern void mx31_init_irq(void); extern void mx35_init_irq(void); +extern void mx50_init_irq(void); extern void mx51_init_irq(void); extern void mx53_init_irq(void); extern void mxc91231_init_irq(void); diff --git a/arch/arm/plat-mxc/include/mach/hardware.h b/arch/arm/plat-mxc/include/mach/hardware.h index f9ed0ba..26bb1ba 100644 --- a/arch/arm/plat-mxc/include/mach/hardware.h +++ b/arch/arm/plat-mxc/include/mach/hardware.h @@ -75,6 +75,11 @@ * AVIC 0x68000000+0x100000 -> 0xf5800000+0x100000 * X_MEMC 0xb8000000+0x010000 -> 0xf4c00000+0x010000 * SPBA0 0x50000000+0x100000 -> 0xf5400000+0x100000 + * mx50: + * TZIC 0x0fffc000+0x004000 -> 0xf4bfc000+0x004000 + * SPBA0 0x50000000+0x100000 -> 0xf5400000+0x100000 + * AIPS1 0x53f00000+0x100000 -> 0xf5700000+0x100000 + * AIPS2 0x63f00000+0x100000 -> 0xf5300000+0x100000 * mx51: * IRAM 0x1ffe0000+0x020000 -> 0xf4fe0000+0x020000 * DEBUG 0x60000000+0x100000 -> 0xf5000000+0x100000 @@ -100,6 +105,7 @@ #define IMX_IO_ADDRESS(x) IOMEM(IMX_IO_P2V(x)) #ifdef CONFIG_ARCH_MX5 +#include #include #include #endif diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx50.h b/arch/arm/plat-mxc/include/mach/iomux-mx50.h new file mode 100644 index 0000000..058a922 --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/iomux-mx50.h @@ -0,0 +1,977 @@ +/* + * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#ifndef __MACH_IOMUX_MX50_H__ +#define __MACH_IOMUX_MX50_H__ + +#include + +#define MX50_ELCDIF_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_DSE_HIGH) + +#define MX50_SD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_HIGH) + +#define MX50_UART_PAD_CTRL (PAD_CTL_DSE_HIGH | PAD_CTL_PKE) + +#define MX50_I2C_PAD_CTRL (PAD_CTL_ODE | PAD_CTL_DSE_HIGH | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_HYS) + +#define MX50_USB_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_DSE_HIGH | PAD_CTL_PUS_47K_UP) + +#define MX50_FEC_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_22K_UP | PAD_CTL_ODE | \ + PAD_CTL_DSE_HIGH) + +#define MX50_OWIRE_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_ODE | \ + PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST) + +#define MX50_KEYPAD_CTRL (PAD_CTL_HYS | PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_DSE_HIGH) + +#define MX50_CSPI_SS_PAD (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_22K_UP | PAD_CTL_DSE_HIGH) + +#define MX50_PAD_KEY_COL0__KEY_COL0 IOMUX_PAD(0x2CC, 0x20, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_KEY_COL0__GPIO_4_0 IOMUX_PAD(0x2CC, 0x20, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_KEY_COL0__NANDF_CLE IOMUX_PAD(0x2CC, 0x20, 2, 0x0, 0, PAD_CTL_DSE_HIGH) + +#define MX50_PAD_KEY_ROW0__KEY_ROW0 IOMUX_PAD(0x2D0, 0x24, 0, 0x0, 0, MX50_KEYPAD_CTRL) +#define MX50_PAD_KEY_ROW0__GPIO_4_1 IOMUX_PAD(0x2D0, 0x24, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_KEY_ROW0__NANDF_ALE IOMUX_PAD(0x2D0, 0x24, 2, 0x0, 0, PAD_CTL_DSE_HIGH) + +#define MX50_PAD_KEY_COL1__KEY_COL1 IOMUX_PAD(0x2D4, 0x28, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_KEY_COL1__GPIO_4_2 IOMUX_PAD(0x2D4, 0x28, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_KEY_COL1__NANDF_CE0 IOMUX_PAD(0x2D4, 0x28, 2, 0x0, 0, PAD_CTL_DSE_HIGH) + +#define MX50_PAD_KEY_ROW1__KEY_ROW1 IOMUX_PAD(0x2D8, 0x2C, 0, 0x0, 0, MX50_KEYPAD_CTRL) +#define MX50_PAD_KEY_ROW1__GPIO_4_3 IOMUX_PAD(0x2D8, 0x2C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_KEY_ROW1__NANDF_CE1 IOMUX_PAD(0x2D8, 0x2C, 2, 0x0, 0, PAD_CTL_DSE_HIGH) + +#define MX50_PAD_KEY_COL2__KEY_COL2 IOMUX_PAD(0x2DC, 0x30, 0, 0x0, 0, MX50_KEYPAD_CTRL) +#define MX50_PAD_KEY_COL2__GPIO_4_4 IOMUX_PAD(0x2DC, 0x30, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_KEY_COL2__NANDF_CE2 IOMUX_PAD(0x2DC, 0x30, 2, 0x0, 0, PAD_CTL_DSE_HIGH) + +#define MX50_PAD_KEY_ROW2__KEY_ROW2 IOMUX_PAD(0x2E0, 0x34, 0, 0x0, 0, MX50_KEYPAD_CTRL) +#define MX50_PAD_KEY_ROW2__GPIO_4_5 IOMUX_PAD(0x2E0, 0x34, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_KEY_ROW2__NANDF_CE3 IOMUX_PAD(0x2E0, 0x34, 2, 0x0, 0, PAD_CTL_DSE_HIGH) + +#define MX50_PAD_KEY_COL3__KEY_COL3 IOMUX_PAD(0x2E4, 0x38, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_KEY_COL3__GPIO_4_6 IOMUX_PAD(0x2E4, 0x38, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_KEY_COL3__NANDF_READY IOMUX_PAD(0x2E4, 0x38, 2, 0x7b4, 0, PAD_CTL_PKE | \ + PAD_CTL_PUE | PAD_CTL_PUS_100K_UP) +#define MX50_PAD_KEY_COL3__SDMA_EXT0 IOMUX_PAD(0x2E4, 0x38, 6, 0x7b8, 0, NO_PAD_CTRL) + +#define MX50_PAD_KEY_ROW3__KEY_ROW3 IOMUX_PAD(0x2E8, 0x3C, 0, 0x0, 0, MX50_KEYPAD_CTRL) +#define MX50_PAD_KEY_ROW3__GPIO_4_7 IOMUX_PAD(0x2E8, 0x3C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_KEY_ROW3__NANDF_DQS IOMUX_PAD(0x2E8, 0x3C, 2, 0x7b0, 0, PAD_CTL_DSE_HIGH) +#define MX50_PAD_KEY_ROW3__SDMA_EXT1 IOMUX_PAD(0x2E8, 0x3C, 6, 0x7bc, 0, NO_PAD_CTRL) + +#define MX50_PAD_I2C1_SCL__I2C1_SCL IOMUX_PAD(0x2EC, 0x40, IOMUX_CONFIG_SION, 0x0, 0, \ + MX50_I2C_PAD_CTRL) +#define MX50_PAD_I2C1_SCL__GPIO_6_18 IOMUX_PAD(0x2EC, 0x40, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_I2C1_SCL__UART2_TXD IOMUX_PAD(0x2EC, 0x40, 2, 0x7cc, 0, MX50_UART_PAD_CTRL) + +#define MX50_PAD_I2C1_SDA__I2C1_SDA IOMUX_PAD(0x2F0, 0x44, IOMUX_CONFIG_SION, 0x0, 0, \ + MX50_I2C_PAD_CTRL) +#define MX50_PAD_I2C1_SDA__GPIO_6_19 IOMUX_PAD(0x2F0, 0x44, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_I2C1_SDA__UART2_RXD IOMUX_PAD(0x2F0, 0x44, 2, 0x7cc, 1, MX50_UART_PAD_CTRL) + +#define MX50_PAD_I2C2_SCL__I2C2_SCL IOMUX_PAD(0x2F4, 0x48, IOMUX_CONFIG_SION, 0x0, 0, \ + MX50_I2C_PAD_CTRL) +#define MX50_PAD_I2C2_SCL__GPIO_6_20 IOMUX_PAD(0x2F4, 0x48, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_I2C2_SCL__UART2_CTS IOMUX_PAD(0x2F4, 0x48, 2, 0x7c8, 0, MX50_UART_PAD_CTRL) +#define MX50_PAD_I2C2_SCL__DCDC_OK IOMUX_PAD(0x2F4, 0x48, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_I2C2_SDA__I2C2_SDA IOMUX_PAD(0x2F8, 0x4C, IOMUX_CONFIG_SION, 0x0, 0, \ + MX50_I2C_PAD_CTRL) +#define MX50_PAD_I2C2_SDA__GPIO_6_21 IOMUX_PAD(0x2F8, 0x4C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_I2C2_SDA__UART2_RTS IOMUX_PAD(0x2F8, 0x4C, 2, 0x7c8, 1, MX50_UART_PAD_CTRL) +#define MX50_PAD_I2C2_SDA__PWRSTABLE IOMUX_PAD(0x2F8, 0x4C, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_I2C3_SCL__I2C3_SCL IOMUX_PAD(0x2FC, 0x50, IOMUX_CONFIG_SION, 0x0, 0, \ + MX50_I2C_PAD_CTRL) +#define MX50_PAD_I2C3_SCL__GPIO_6_22 IOMUX_PAD(0x2FC, 0x50, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_I2C3_SCL__FEC_MDC IOMUX_PAD(0x2FC, 0x50, 2, 0x0, 0, PAD_CTL_DSE_HIGH) +#define MX50_PAD_I2C3_SCL__PMIC_RDY IOMUX_PAD(0x2FC, 0x50, 3, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_I2C3_SCL__GPT_CAPIN1 IOMUX_PAD(0x2FC, 0x50, 5, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_I2C3_SCL__USBOTG_OC IOMUX_PAD(0x2FC, 0x50, 7, 0x7E8, 0, MX50_USB_PAD_CTRL) + +#define MX50_PAD_I2C3_SDA__I2C3_SDA IOMUX_PAD(0x300, 0x54, IOMUX_CONFIG_SION, 0x0, 0, \ + MX50_I2C_PAD_CTRL) +#define MX50_PAD_I2C3_SDA__GPIO_6_23 IOMUX_PAD(0x300, 0x54, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_I2C3_SDA__FEC_MDIO IOMUX_PAD(0x300, 0x54, 2, 0x774, 0, MX50_FEC_PAD_CTRL) +#define MX50_PAD_I2C3_SDA__PWRFAIL_INT IOMUX_PAD(0x300, 0x54, 3, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_I2C3_SDA__ALARM_DEB IOMUX_PAD(0x300, 0x54, 4, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_I2C3_SDA__GPT_CAPIN1 IOMUX_PAD(0x300, 0x54, 5, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_I2C3_SDA__USBOTG_PWR IOMUX_PAD(0x300, 0x54, 7, 0x0, 0, \ + PAD_CTL_PKE | PAD_CTL_DSE_HIGH) + +#define MX50_PAD_PWM1__PWM1_PWMO IOMUX_PAD(0x304, 0x58, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_PWM1__GPIO_6_24 IOMUX_PAD(0x304, 0x58, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_PWM1__USBOTG_OC IOMUX_PAD(0x304, 0x58, 2, 0x7E8, 1, MX50_USB_PAD_CTRL) +#define MX50_PAD_PWM1__GPT_CMPOUT1 IOMUX_PAD(0x304, 0x58, 5, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_PWM2__PWM2_PWMO IOMUX_PAD(0x308, 0x5C, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_PWM2__GPIO_6_25 IOMUX_PAD(0x308, 0x5C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_PWM2__USBOTG_PWR IOMUX_PAD(0x308, 0x5C, 2, 0x0, 0, \ + PAD_CTL_PKE | PAD_CTL_DSE_HIGH) +#define MX50_PAD_PWM2__DCDC_PWM IOMUX_PAD(0x308, 0x5C, 4, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_PWM2__GPT_CMPOUT2 IOMUX_PAD(0x308, 0x5C, 5, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_PWM2__ANY_PU_RST IOMUX_PAD(0x308, 0x5C, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_OWIRE__OWIRE IOMUX_PAD(0x30C, 0x60, 0, 0x0, 0, MX50_OWIRE_PAD_CTRL) +#define MX50_PAD_OWIRE__GPIO_6_26 IOMUX_PAD(0x30C, 0x60, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_OWIRE__USBH1_OC IOMUX_PAD(0x30C, 0x60, 2, 0x0, 0, MX50_USB_PAD_CTRL) +#define MX50_PAD_OWIRE__SSI_EXT1_CLK IOMUX_PAD(0x30C, 0x60, 3, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_OWIRE__EPDC_PWRIRQ IOMUX_PAD(0x30C, 0x60, 4, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_OWIRE__GPT_CMPOUT3 IOMUX_PAD(0x30C, 0x60, 5, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_EPITO__EPITO IOMUX_PAD(0x310, 0x64, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPITO__GPIO_6_27 IOMUX_PAD(0x310, 0x64, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPITO__USBH1_PWR IOMUX_PAD(0x310, 0x64, 2, 0x0, 0, \ + PAD_CTL_PKE | PAD_CTL_DSE_HIGH) +#define MX50_PAD_EPITO__SSI_EXT2_CLK IOMUX_PAD(0x310, 0x64, 3, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPITO__TOG_EN IOMUX_PAD(0x310, 0x64, 4, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPITO__GPT_CLKIN IOMUX_PAD(0x310, 0x64, 5, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_WDOG__WDOG IOMUX_PAD(0x314, 0x68, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_WDOG__GPIO_6_28 IOMUX_PAD(0x314, 0x68, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_WDOG__WDOG_RST IOMUX_PAD(0x314, 0x68, 2, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_WDOG__XTAL32K IOMUX_PAD(0x314, 0x68, 6, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_SSI_TXFS__SSI_TXFS IOMUX_PAD(0x318, 0x6C, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_SSI_TXFS__GPIO_6_0 IOMUX_PAD(0x318, 0x6C, 1, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_SSI_TXC__SSI_TXC IOMUX_PAD(0x31C, 0x70, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_SSI_TXC__GPIO_6_1 IOMUX_PAD(0x31C, 0x70, 1, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_SSI_TXD__SSI_TXD IOMUX_PAD(0x320, 0x74, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_SSI_TXD__GPIO_6_2 IOMUX_PAD(0x320, 0x74, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_SSI_TXD__CSPI_RDY IOMUX_PAD(0x320, 0x74, 4, 0x6e8, 0, NO_PAD_CTRL) + +#define MX50_PAD_SSI_RXD__SSI_RXD IOMUX_PAD(0x324, 0x78, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_SSI_RXD__GPIO_6_3 IOMUX_PAD(0x324, 0x78, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_SSI_RXD__CSPI_SS3 IOMUX_PAD(0x324, 0x78, 4, 0x6f4, 0, MX50_CSPI_SS_PAD) + +#define MX50_PAD_SSI_RXFS__AUD3_RXFS IOMUX_PAD(0x328, 0x7C, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_SSI_RXFS__GPIO_6_4 IOMUX_PAD(0x328, 0x7C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_SSI_RXFS__UART5_TXD IOMUX_PAD(0x328, 0x7C, 2, 0x7e4, 0, MX50_UART_PAD_CTRL) +#define MX50_PAD_SSI_RXFS__WEIM_D6 IOMUX_PAD(0x328, 0x7C, 3, 0x804, 0, NO_PAD_CTRL) +#define MX50_PAD_SSI_RXFS__CSPI_SS2 IOMUX_PAD(0x328, 0x7C, 4, 0x6f0, 0, MX50_CSPI_SS_PAD) +#define MX50_PAD_SSI_RXFS__FEC_COL IOMUX_PAD(0x328, 0x7C, 5, 0x770, 0, PAD_CTL_DSE_HIGH) +#define MX50_PAD_SSI_RXFS__FEC_MDC IOMUX_PAD(0x328, 0x7C, 6, 0x0, 0, PAD_CTL_DSE_HIGH) + +#define MX50_PAD_SSI_RXC__AUD3_RXC IOMUX_PAD(0x32C, 0x80, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_SSI_RXC__GPIO_6_5 IOMUX_PAD(0x32C, 0x80, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_SSI_RXC__UART5_RXD IOMUX_PAD(0x32C, 0x80, 2, 0x7e4, 1, MX50_UART_PAD_CTRL) +#define MX50_PAD_SSI_RXC__WEIM_D7 IOMUX_PAD(0x32C, 0x80, 3, 0x808, 0, NO_PAD_CTRL) +#define MX50_PAD_SSI_RXC__CSPI_SS1 IOMUX_PAD(0x32C, 0x80, 4, 0x6ec, 0, MX50_CSPI_SS_PAD) +#define MX50_PAD_SSI_RXC__FEC_RX_CLK IOMUX_PAD(0x32C, 0x80, 5, 0x780, 0, NO_PAD_CTRL) +#define MX50_PAD_SSI_RXC__FEC_MDIO IOMUX_PAD(0x32C, 0x80, 6, 0x774, 1, MX50_FEC_PAD_CTRL) + +#define MX50_PAD_UART1_TXD__UART1_TXD IOMUX_PAD(0x330, 0x84, 0, 0x7c4, 0, MX50_UART_PAD_CTRL) +#define MX50_PAD_UART1_TXD__GPIO_6_6 IOMUX_PAD(0x330, 0x84, 1, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_UART1_RXD__UART1_RXD IOMUX_PAD(0x334, 0x88, 0, 0x7c4, 1, MX50_UART_PAD_CTRL) +#define MX50_PAD_UART1_RXD__GPIO_6_7 IOMUX_PAD(0x334, 0x88, 1, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_UART1_CTS__UART1_CTS IOMUX_PAD(0x338, 0x8C, 0, 0x7c0, 0, MX50_UART_PAD_CTRL) +#define MX50_PAD_UART1_CTS__GPIO_6_8 IOMUX_PAD(0x338, 0x8C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_UART1_CTS__UART5_TXD IOMUX_PAD(0x338, 0x8C, 2, 0x7e4, 2, MX50_UART_PAD_CTRL) +#define MX50_PAD_UART1_CTS__SD4_D4 IOMUX_PAD(0x338, 0x8C, 4, 0x760, 0, MX50_SD_PAD_CTRL) +#define MX50_PAD_UART1_CTS__SD4_CMD IOMUX_PAD(0x338, 0x8C, 5, 0x74c, 0, MX50_SD_PAD_CTRL) + +#define MX50_PAD_UART1_RTS__UART1_RTS IOMUX_PAD(0x33C, 0x90, 0, 0x7c0, 1, MX50_UART_PAD_CTRL) +#define MX50_PAD_UART1_RTS__GPIO_6_9 IOMUX_PAD(0x33C, 0x90, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_UART1_RTS__UART5_RXD IOMUX_PAD(0x33C, 0x90, 2, 0x7e4, 3, MX50_UART_PAD_CTRL) +#define MX50_PAD_UART1_RTS__SD4_D5 IOMUX_PAD(0x33C, 0x90, 4, 0x0, 1, MX50_SD_PAD_CTRL) +#define MX50_PAD_UART1_RTS__SD4_CLK IOMUX_PAD(0x33C, 0x90, 5, 0x0, 1, MX50_SD_PAD_CTRL) + +#define MX50_PAD_UART2_TXD__UART2_TXD IOMUX_PAD(0x340, 0x94, 0, 0x7cc, 2, MX50_UART_PAD_CTRL) +#define MX50_PAD_UART2_TXD__GPIO_6_10 IOMUX_PAD(0x340, 0x94, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_UART2_TXD__SD4_D6 IOMUX_PAD(0x340, 0x94, 4, 0x768, 0, MX50_SD_PAD_CTRL) +#define MX50_PAD_UART2_TXD__SD4_D4 IOMUX_PAD(0x340, 0x94, 5, 0x760, 1, MX50_SD_PAD_CTRL) + +#define MX50_PAD_UART2_RXD__UART2_RXD IOMUX_PAD(0x344, 0x98, 0, 0x7cc, 3, MX50_UART_PAD_CTRL) +#define MX50_PAD_UART2_RXD__GPIO_6_11 IOMUX_PAD(0x344, 0x98, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_UART2_RXD__SD4_D7 IOMUX_PAD(0x344, 0x98, 4, 0x76c, 0, MX50_SD_PAD_CTRL) +#define MX50_PAD_UART2_RXD__SD4_D5 IOMUX_PAD(0x344, 0x98, 5, 0x764, 1, MX50_SD_PAD_CTRL) + +#define MX50_PAD_UART2_CTS__UART2_CTS IOMUX_PAD(0x348, 0x9C, 0, 0x7c8, 2, MX50_UART_PAD_CTRL) +#define MX50_PAD_UART2_CTS__GPIO_6_12 IOMUX_PAD(0x348, 0x9C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_UART2_CTS__SD4_CMD IOMUX_PAD(0x348, 0x9C, 4, 0x74c, 1, MX50_SD_PAD_CTRL) +#define MX50_PAD_UART2_CTS__SD4_D6 IOMUX_PAD(0x348, 0x9C, 5, 0x768, 1, MX50_SD_PAD_CTRL) + +#define MX50_PAD_UART2_RTS__UART2_RTS IOMUX_PAD(0x34C, 0xA0, 0, 0x7c8, 3, MX50_UART_PAD_CTRL) +#define MX50_PAD_UART2_RTS__GPIO_6_13 IOMUX_PAD(0x34C, 0xA0, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_UART2_RTS__SD4_CLK IOMUX_PAD(0x34C, 0xA0, 4, 0x748, 1, MX50_SD_PAD_CTRL) +#define MX50_PAD_UART2_RTS__SD4_D7 IOMUX_PAD(0x34C, 0xA0, 5, 0x76c, 1, MX50_SD_PAD_CTRL) + +#define MX50_PAD_UART3_TXD__UART3_TXD IOMUX_PAD(0x350, 0xA4, 0, 0x7d4, 0, MX50_UART_PAD_CTRL) +#define MX50_PAD_UART3_TXD__GPIO_6_14 IOMUX_PAD(0x350, 0xA4, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_UART3_TXD__SD1_D4 IOMUX_PAD(0x350, 0xA4, 3, 0x0, 0, MX50_SD_PAD_CTRL) +#define MX50_PAD_UART3_TXD__SD4_D0 IOMUX_PAD(0x350, 0xA4, 4, 0x750, 0, MX50_SD_PAD_CTRL) +#define MX50_PAD_UART3_TXD__SD2_WP IOMUX_PAD(0x350, 0xA4, 5, 0x744, 0, MX50_SD_PAD_CTRL) +#define MX50_PAD_UART3_TXD__WEIM_D12 IOMUX_PAD(0x350, 0xA4, 6, 0x81c, 0, NO_PAD_CTRL) + +#define MX50_PAD_UART3_RXD__UART3_RXD IOMUX_PAD(0x354, 0xA8, 0, 0x7d4, 1, MX50_UART_PAD_CTRL) +#define MX50_PAD_UART3_RXD__GPIO_6_15 IOMUX_PAD(0x354, 0xA8, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_UART3_RXD__SD1_D5 IOMUX_PAD(0x354, 0xA8, 3, 0x0, 0, MX50_SD_PAD_CTRL) +#define MX50_PAD_UART3_RXD__SD4_D1 IOMUX_PAD(0x354, 0xA8, 4, 0x754, 0, MX50_SD_PAD_CTRL) +#define MX50_PAD_UART3_RXD__SD2_CD IOMUX_PAD(0x354, 0xA8, 5, 0x740, 0, MX50_SD_PAD_CTRL) +#define MX50_PAD_UART3_RXD__WEIM_D13 IOMUX_PAD(0x354, 0xA8, 6, 0x820, 0, NO_PAD_CTRL) + +#define MX50_PAD_UART4_TXD__UART4_TXD IOMUX_PAD(0x358, 0xAC, 0, 0x7dc, 0, MX50_UART_PAD_CTRL) +#define MX50_PAD_UART4_TXD__GPIO_6_16 IOMUX_PAD(0x358, 0xAC, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_UART4_TXD__UART3_CTS IOMUX_PAD(0x358, 0xAC, 2, 0x7d0, 0, MX50_UART_PAD_CTRL) +#define MX50_PAD_UART4_TXD__SD1_D6 IOMUX_PAD(0x358, 0xAC, 3, 0x0, 0, MX50_SD_PAD_CTRL) +#define MX50_PAD_UART4_TXD__SD4_D2 IOMUX_PAD(0x358, 0xAC, 4, 0x758, 0, MX50_SD_PAD_CTRL) +#define MX50_PAD_UART4_TXD__SD2_LCTL IOMUX_PAD(0x358, 0xAC, 5, 0x0, 0, MX50_SD_PAD_CTRL) +#define MX50_PAD_UART4_TXD__WEIM_D14 IOMUX_PAD(0x358, 0xAC, 6, 0x824, 0, NO_PAD_CTRL) + +#define MX50_PAD_UART4_RXD__UART4_RXD IOMUX_PAD(0x35C, 0xB0, 0, 0x7dc, 1, MX50_UART_PAD_CTRL) +#define MX50_PAD_UART4_RXD__GPIO_6_17 IOMUX_PAD(0x35C, 0xB0, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_UART4_RXD__UART3_RTS IOMUX_PAD(0x35C, 0xB0, 2, 0x7d0, 1, MX50_UART_PAD_CTRL) +#define MX50_PAD_UART4_RXD__SD1_D7 IOMUX_PAD(0x35C, 0xB0, 3, 0x0, 0, MX50_SD_PAD_CTRL) +#define MX50_PAD_UART4_RXD__SD4_D3 IOMUX_PAD(0x35C, 0xB0, 4, 0x75c, 0, MX50_SD_PAD_CTRL) +#define MX50_PAD_UART4_RXD__SD1_LCTL IOMUX_PAD(0x35C, 0xB0, 5, 0x0, 0, MX50_SD_PAD_CTRL) +#define MX50_PAD_UART4_RXD__WEIM_D15 IOMUX_PAD(0x35C, 0xB0, 6, 0x828, 0, NO_PAD_CTRL) + +#define MX50_PAD_CSPI_SCLK__CSPI_SCLK IOMUX_PAD(0x360, 0xB4, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_CSPI_SCLK__GPIO_4_8 IOMUX_PAD(0x360, 0xB4, 1, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_CSPI_MOSI__CSPI_MOSI IOMUX_PAD(0x364, 0xB8, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_CSPI_MOSI__GPIO_4_9 IOMUX_PAD(0x364, 0xB8, 1, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_CSPI_MISO__CSPI_MISO IOMUX_PAD(0x368, 0xBC, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_CSPI_MISO__GPIO_4_10 IOMUX_PAD(0x368, 0xBC, 1, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_CSPI_SS0__CSPI_SS0 IOMUX_PAD(0x36C, 0xC0, 0, 0x0, 0, MX50_CSPI_SS_PAD) +#define MX50_PAD_CSPI_SS0__GPIO_4_11 IOMUX_PAD(0x36C, 0xC0, 1, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_ECSPI1_SCLK__ECSPI1_SCLK IOMUX_PAD(0x370, 0xC4, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_ECSPI1_SCLK__GPIO_4_12 IOMUX_PAD(0x370, 0xC4, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_ECSPI1_SCLK__CSPI_RDY IOMUX_PAD(0x370, 0xC4, 2, 0x6e8, 1, NO_PAD_CTRL) +#define MX50_PAD_ECSPI1_SCLK__ECSPI2_RDY IOMUX_PAD(0x370, 0xC4, 3, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_ECSPI1_SCLK__UART3_RTS IOMUX_PAD(0x370, 0xC4, 4, 0x7d0, 2, MX50_UART_PAD_CTRL) +#define MX50_PAD_ECSPI1_SCLK__EPDC_SDCE6 IOMUX_PAD(0x370, 0xC4, 5, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_ECSPI1_SCLK__WEIM_D8 IOMUX_PAD(0x370, 0xC4, 7, 0x80c, 0, NO_PAD_CTRL) + +#define MX50_PAD_ECSPI1_MOSI__ECSPI1_MOSI IOMUX_PAD(0x374, 0xC8, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_ECSPI1_MOSI__GPIO_4_13 IOMUX_PAD(0x374, 0xC8, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_ECSPI1_MOSI__CSPI_SS1 IOMUX_PAD(0x374, 0xC8, 2, 0x6ec, 1, MX50_CSPI_SS_PAD) +#define MX50_PAD_ECSPI1_MOSI__ECSPI2_SS1 IOMUX_PAD(0x374, 0xC8, 3, 0x0, 0, MX50_CSPI_SS_PAD) +#define MX50_PAD_ECSPI1_MOSI__UART3_CTS IOMUX_PAD(0x374, 0xC8, 4, 0x7d0, 3, MX50_UART_PAD_CTRL) +#define MX50_PAD_ECSPI1_MOSI__EPDC_SDCE7 IOMUX_PAD(0x374, 0xC8, 5, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_ECSPI1_MOSI__WEIM_D9 IOMUX_PAD(0x374, 0xC8, 7, 0x810, 0, NO_PAD_CTRL) + +#define MX50_PAD_ECSPI1_MISO__ECSPI1_MISO IOMUX_PAD(0x378, 0xCC, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_ECSPI1_MISO__GPIO_4_14 IOMUX_PAD(0x378, 0xCC, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_ECSPI1_MISO__CSPI_SS2 IOMUX_PAD(0x378, 0xCC, 2, 0x6f0, 1, MX50_CSPI_SS_PAD) +#define MX50_PAD_ECSPI1_MISO__ECSPI2_SS2 IOMUX_PAD(0x378, 0xCC, 3, 0x0, 0, MX50_CSPI_SS_PAD) +#define MX50_PAD_ECSPI1_MISO__UART4_RTS IOMUX_PAD(0x378, 0xCC, 4, 0x7d8, 0, MX50_UART_PAD_CTRL) +#define MX50_PAD_ECSPI1_MISO__EPDC_SDCE8 IOMUX_PAD(0x378, 0xCC, 5, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_ECSPI1_MISO__WEIM_D10 IOMUX_PAD(0x378, 0xCC, 7, 0x814, 0, NO_PAD_CTRL) + +#define MX50_PAD_ECSPI1_SS0__ECSPI1_SS0 IOMUX_PAD(0x37C, 0xD0, 0, 0x0, 0, MX50_CSPI_SS_PAD) +#define MX50_PAD_ECSPI1_SS0__GPIO_4_15 IOMUX_PAD(0x37C, 0xD0, 1, 0x0, 0, PAD_CTL_PUS_100K_UP) +#define MX50_PAD_ECSPI1_SS0__CSPI_SS3 IOMUX_PAD(0x37C, 0xD0, 2, 0x6f4, 1, MX50_CSPI_SS_PAD) +#define MX50_PAD_ECSPI1_SS0__ECSPI2_SS3 IOMUX_PAD(0x37C, 0xD0, 3, 0x0, 0, MX50_CSPI_SS_PAD) +#define MX50_PAD_ECSPI1_SS0__UART4_CTS IOMUX_PAD(0x37C, 0xD0, 4, 0x7d8, 1, MX50_UART_PAD_CTRL) +#define MX50_PAD_ECSPI1_SS0__EPDC_SDCE9 IOMUX_PAD(0x37C, 0xD0, 5, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_ECSPI1_SS0__WEIM_D11 IOMUX_PAD(0x37C, 0xD0, 7, 0x818, 0, NO_PAD_CTRL) + +#define MX50_PAD_ECSPI2_SCLK__ECSPI2_SCLK IOMUX_PAD(0x380, 0xD4, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_ECSPI2_SCLK__GPIO_4_16 IOMUX_PAD(0x380, 0xD4, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_ECSPI2_SCLK__ELCDIF_WR IOMUX_PAD(0x380, 0xD4, 2, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_ECSPI2_SCLK__ECSPI1_RDY IOMUX_PAD(0x380, 0xD4, 3, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_ECSPI2_SCLK__UART5_RTS IOMUX_PAD(0x380, 0xD4, 4, 0x7e0, 0, MX50_UART_PAD_CTRL) +#define MX50_PAD_ECSPI2_SCLK__ELCDIF_DOTCLK IOMUX_PAD(0x380, 0xD4, 5, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_ECSPI2_SCLK__NANDF_CEN4 IOMUX_PAD(0x380, 0xD4, 6, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_ECSPI2_SCLK__WEIM_D8 IOMUX_PAD(0x380, 0xD4, 7, 0x80c, 1, NO_PAD_CTRL) + +#define MX50_PAD_ECSPI2_MOSI__ECSPI2_MOSI IOMUX_PAD(0x384, 0xD8, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_ECSPI2_MOSI__GPIO_4_17 IOMUX_PAD(0x384, 0xD8, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_ECSPI2_MOSI__ELCDIF_RD IOMUX_PAD(0x384, 0xD8, 2, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_ECSPI2_MOSI__ECSPI1_SS1 IOMUX_PAD(0x384, 0xD8, 3, 0x0, 0, MX50_CSPI_SS_PAD) +#define MX50_PAD_ECSPI2_MOSI__UART5_CTS IOMUX_PAD(0x384, 0xD8, 4, 0x7e0, 1, MX50_UART_PAD_CTRL) +#define MX50_PAD_ECSPI2_MOSI__ELCDIF_EN IOMUX_PAD(0x384, 0xD8, 5, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_ECSPI2_MOSI__NANDF_CEN5 IOMUX_PAD(0x384, 0xD8, 6, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_ECSPI2_MOSI__WEIM_D9 IOMUX_PAD(0x384, 0xD8, 7, 0x810, 1, NO_PAD_CTRL) + +#define MX50_PAD_ECSPI2_MISO__ECSPI2_MISO IOMUX_PAD(0x388, 0xDC, 0, 0x73c, 0, NO_PAD_CTRL) +#define MX50_PAD_ECSPI2_MISO__GPIO_4_18 IOMUX_PAD(0x388, 0xDC, 1, 0x0, 0, PAD_CTL_PUS_100K_UP) +#define MX50_PAD_ECSPI2_MISO__ELCDIF_RS IOMUX_PAD(0x388, 0xDC, 2, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_ECSPI2_MISO__ECSPI1_SS2 IOMUX_PAD(0x388, 0xDC, 3, 0x0, 0, MX50_CSPI_SS_PAD) +#define MX50_PAD_ECSPI2_MISO__UART5_TXD IOMUX_PAD(0x388, 0xDC, 4, 0x7e4, 4, MX50_UART_PAD_CTRL) +#define MX50_PAD_ECSPI2_MISO__ELCDIF_VSYNC IOMUX_PAD(0x388, 0xDC, 5, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_ECSPI2_MISO__NANDF_CEN6 IOMUX_PAD(0x388, 0xDC, 6, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_ECSPI2_MISO__WEIM_D10 IOMUX_PAD(0x388, 0xDC, 7, 0x814, 1, NO_PAD_CTRL) + +#define MX50_PAD_ECSPI2_SS0__ECSPI2_SS0 IOMUX_PAD(0x38C, 0xE0, 0, 0x0, 0, MX50_CSPI_SS_PAD) +#define MX50_PAD_ECSPI2_SS0__GPIO_4_19 IOMUX_PAD(0x38C, 0xE0, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_ECSPI2_SS0__ELCDIF_CS IOMUX_PAD(0x38C, 0xE0, 2, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_ECSPI2_SS0__ECSPI1_SS3 IOMUX_PAD(0x38C, 0xE0, 3, 0x0, 0, MX50_CSPI_SS_PAD) +#define MX50_PAD_ECSPI2_SS0__UART5_RXD IOMUX_PAD(0x38C, 0xE0, 4, 0x7e4, 5, MX50_UART_PAD_CTRL) +#define MX50_PAD_ECSPI2_SS0__ELCDIF_HSYNC IOMUX_PAD(0x38C, 0xE0, 5, 0x6f8, 0, NO_PAD_CTRL) +#define MX50_PAD_ECSPI2_SS0__NANDF_CEN7 IOMUX_PAD(0x38C, 0xE0, 6, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_ECSPI2_SS0__WEIM_D11 IOMUX_PAD(0x38C, 0xE0, 7, 0x818, 1, NO_PAD_CTRL) + +#define MX50_PAD_SD1_CLK__SD1_CLK IOMUX_PAD(0x390, 0xE4, IOMUX_CONFIG_SION, 0x0, 0, MX50_SD_PAD_CTRL) +#define MX50_PAD_SD1_CLK__GPIO_5_0 IOMUX_PAD(0x390, 0xE4, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_SD1_CLK__CLKO IOMUX_PAD(0x390, 0xE4, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_SD1_CMD__SD1_CMD IOMUX_PAD(0x394, 0xE8, IOMUX_CONFIG_SION, 0x0, 0, MX50_SD_PAD_CTRL) +#define MX50_PAD_SD1_CMD__GPIO_5_1 IOMUX_PAD(0x394, 0xE8, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_SD1_CMD__CLKO2 IOMUX_PAD(0x394, 0xE8, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_SD1_D0__SD1_D0 IOMUX_PAD(0x398, 0xEC, 0, 0x0, 0, MX50_SD_PAD_CTRL) +#define MX50_PAD_SD1_D0__GPIO_5_2 IOMUX_PAD(0x398, 0xEC, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_SD1_D0__PLL1_BYP IOMUX_PAD(0x398, 0xEC, 7, 0x6dc, 0, NO_PAD_CTRL) + +#define MX50_PAD_SD1_D1__SD1_D1 IOMUX_PAD(0x39C, 0xF0, 0, 0x0, 0, MX50_SD_PAD_CTRL) +#define MX50_PAD_SD1_D1__GPIO_5_3 IOMUX_PAD(0x39C, 0xF0, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_SD1_D1__PLL2_BYP IOMUX_PAD(0x39C, 0xF0, 7, 0x6e0, 0, NO_PAD_CTRL) + +#define MX50_PAD_SD1_D2__SD1_D2 IOMUX_PAD(0x3A0, 0xF4, 0, 0x0, 0, MX50_SD_PAD_CTRL) +#define MX50_PAD_SD1_D2__GPIO_5_4 IOMUX_PAD(0x3A0, 0xF4, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_SD1_D2__PLL3_BYP IOMUX_PAD(0x3A0, 0xF4, 7, 0x6e4, 0, NO_PAD_CTRL) + +#define MX50_PAD_SD1_D3__SD1_D3 IOMUX_PAD(0x3A4, 0xF8, 0, 0x0, 0, MX50_SD_PAD_CTRL) +#define MX50_PAD_SD1_D3__GPIO_5_5 IOMUX_PAD(0x3A4, 0xF8, 1, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_SD2_CLK__SD2_CLK IOMUX_PAD(0x3A8, 0xFC, IOMUX_CONFIG_SION, 0x0, 0, MX50_SD_PAD_CTRL) +#define MX50_PAD_SD2_CLK__GPIO_5_6 IOMUX_PAD(0x3A8, 0xFC, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_SD2_CLK__MSHC_SCLK IOMUX_PAD(0x3A8, 0xFC, 2, 0x0, 0, MX50_SD_PAD_CTRL) + +#define MX50_PAD_SD2_CMD__SD2_CMD IOMUX_PAD(0x3AC, 0x100, IOMUX_CONFIG_SION, 0x0, 0, MX50_SD_PAD_CTRL) +#define MX50_PAD_SD2_CMD__GPIO_5_7 IOMUX_PAD(0x3AC, 0x100, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_SD2_CMD__MSHC_BS IOMUX_PAD(0x3AC, 0x100, 2, 0x0, 0, MX50_SD_PAD_CTRL) + +#define MX50_PAD_SD2_D0__SD2_D0 IOMUX_PAD(0x3B0, 0x104, 0, 0x0, 0, MX50_SD_PAD_CTRL) +#define MX50_PAD_SD2_D0__GPIO_5_8 IOMUX_PAD(0x3B0, 0x104, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_SD2_D0__MSHC_D0 IOMUX_PAD(0x3B0, 0x104, 2, 0x0, 0, MX50_SD_PAD_CTRL) +#define MX50_PAD_SD2_D0__KEY_COL4 IOMUX_PAD(0x3B0, 0x104, 3, 0x790, 0, NO_PAD_CTRL) + +#define MX50_PAD_SD2_D1__SD2_D1 IOMUX_PAD(0x3B4, 0x108, 0, 0x0, 0, MX50_SD_PAD_CTRL) +#define MX50_PAD_SD2_D1__GPIO_5_9 IOMUX_PAD(0x3B4, 0x108, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_SD2_D1__MSHC_D1 IOMUX_PAD(0x3B4, 0x108, 2, 0x0, 0, MX50_SD_PAD_CTRL) +#define MX50_PAD_SD2_D1__KEY_ROW4 IOMUX_PAD(0x3B4, 0x108, 3, 0x7a0, 0, NO_PAD_CTRL) + +#define MX50_PAD_SD2_D2__SD2_D2 IOMUX_PAD(0x3B8, 0x10C, 0, 0x0, 0, MX50_SD_PAD_CTRL) +#define MX50_PAD_SD2_D2__GPIO_5_10 IOMUX_PAD(0x3B8, 0x10C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_SD2_D2__MSHC_D2 IOMUX_PAD(0x3B8, 0x10C, 2, 0x0, 0, MX50_SD_PAD_CTRL) +#define MX50_PAD_SD2_D2__KEY_COL5 IOMUX_PAD(0x3B8, 0x10C, 3, 0x794, 0, NO_PAD_CTRL) + +#define MX50_PAD_SD2_D3__SD2_D3 IOMUX_PAD(0x3BC, 0x110, 0, 0x0, 0, MX50_SD_PAD_CTRL) +#define MX50_PAD_SD2_D3__GPIO_5_11 IOMUX_PAD(0x3BC, 0x110, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_SD2_D3__MSHC_D3 IOMUX_PAD(0x3BC, 0x110, 2, 0x0, 0, MX50_SD_PAD_CTRL) +#define MX50_PAD_SD2_D3__KEY_ROW5 IOMUX_PAD(0x3BC, 0x110, 3, 0x7a4, 0, NO_PAD_CTRL) + +#define MX50_PAD_SD2_D4__SD2_D4 IOMUX_PAD(0x3C0, 0x114, 0, 0x0, 0, MX50_SD_PAD_CTRL) +#define MX50_PAD_SD2_D4__GPIO_5_12 IOMUX_PAD(0x3C0, 0x114, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_SD2_D4__AUD4_RXFS IOMUX_PAD(0x3C0, 0x114, 2, 0x6d0, 0, NO_PAD_CTRL) +#define MX50_PAD_SD2_D4__KEY_COL6 IOMUX_PAD(0x3C0, 0x114, 3, 0x798, 0, NO_PAD_CTRL) +#define MX50_PAD_SD2_D4__WEIM_D0 IOMUX_PAD(0x3C0, 0x114, 4, 0x7ec, 0, NO_PAD_CTRL) +#define MX50_PAD_SD2_D4__CCM_OUT0 IOMUX_PAD(0x3C0, 0x114, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_SD2_D5__SD2_D5 IOMUX_PAD(0x3C4, 0x118, 0, 0x0, 0, MX50_SD_PAD_CTRL) +#define MX50_PAD_SD2_D5__GPIO_5_13 IOMUX_PAD(0x3C4, 0x118, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_SD2_D5__AUD4_RXC IOMUX_PAD(0x3C4, 0x118, 2, 0x6cc, 0, NO_PAD_CTRL) +#define MX50_PAD_SD2_D5__KEY_ROW6 IOMUX_PAD(0x3C4, 0x118, 3, 0x7a8, 0, NO_PAD_CTRL) +#define MX50_PAD_SD2_D5__WEIM_D1 IOMUX_PAD(0x3C4, 0x118, 4, 0x7f0, 0, NO_PAD_CTRL) +#define MX50_PAD_SD2_D5__CCM_OUT1 IOMUX_PAD(0x3C4, 0x118, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_SD2_D6__SD2_D6 IOMUX_PAD(0x3C8, 0x11C, 0, 0x0, 0, MX50_SD_PAD_CTRL) +#define MX50_PAD_SD2_D6__GPIO_5_14 IOMUX_PAD(0x3C8, 0x11C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_SD2_D6__AUD4_RXD IOMUX_PAD(0x3C8, 0x11C, 2, 0x6c4, 0, NO_PAD_CTRL) +#define MX50_PAD_SD2_D6__KEY_COL7 IOMUX_PAD(0x3C8, 0x11C, 3, 0x79c, 0, NO_PAD_CTRL) +#define MX50_PAD_SD2_D6__WEIM_D2 IOMUX_PAD(0x3C8, 0x11C, 4, 0x7f4, 0, NO_PAD_CTRL) +#define MX50_PAD_SD2_D6__CCM_OUT2 IOMUX_PAD(0x3C8, 0x11C, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_SD2_D7__SD2_D7 IOMUX_PAD(0x3CC, 0x120, 0, 0x0, 0, MX50_SD_PAD_CTRL) +#define MX50_PAD_SD2_D7__GPIO_5_15 IOMUX_PAD(0x3CC, 0x120, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_SD2_D7__AUD4_TXFS IOMUX_PAD(0x3CC, 0x120, 2, 0x6d8, 0, NO_PAD_CTRL) +#define MX50_PAD_SD2_D7__KEY_ROW7 IOMUX_PAD(0x3CC, 0x120, 3, 0x7ac, 0, NO_PAD_CTRL) +#define MX50_PAD_SD2_D7__WEIM_D3 IOMUX_PAD(0x3CC, 0x120, 4, 0x7f8, 0, NO_PAD_CTRL) +#define MX50_PAD_SD2_D7__CCM_STOP IOMUX_PAD(0x3CC, 0x120, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_SD2_WP__SD2_WP IOMUX_PAD(0x3D0, 0x124, 0, 0x744, 1, MX50_SD_PAD_CTRL) +#define MX50_PAD_SD2_WP__GPIO_5_16 IOMUX_PAD(0x3D0, 0x124, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_SD2_WP__AUD4_TXD IOMUX_PAD(0x3D0, 0x124, 2, 0x6c8, 0, NO_PAD_CTRL) +#define MX50_PAD_SD2_WP__WEIM_D4 IOMUX_PAD(0x3D0, 0x124, 4, 0x7fc, 0, NO_PAD_CTRL) +#define MX50_PAD_SD2_WP__CCM_WAIT IOMUX_PAD(0x3D0, 0x124, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_SD2_CD__SD2_CD IOMUX_PAD(0x3D4, 0x128, 0, 0x740, 1, MX50_SD_PAD_CTRL) +#define MX50_PAD_SD2_CD__GPIO_5_17 IOMUX_PAD(0x3D4, 0x128, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_SD2_CD__AUD4_TXC IOMUX_PAD(0x3D4, 0x128, 2, 0x6d4, 0, NO_PAD_CTRL) +#define MX50_PAD_SD2_CD__WEIM_D5 IOMUX_PAD(0x3D4, 0x128, 4, 0x800, 0, NO_PAD_CTRL) +#define MX50_PAD_SD2_CD__CCM_REF_EN IOMUX_PAD(0x3D4, 0x128, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_PMIC_ON_REQ__PMIC_ON_REQ IOMUX_PAD(0x3D8, 0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_PMIC_STBY_REQ__PMIC_STBY_REQ IOMUX_PAD(0x3DC, 0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_PMIC_PORT_B__PMIC_PORT_B IOMUX_PAD(0x3E0, 0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_PMIC_BOOT_MODE1__PMIC_BOOT_MODE1 IOMUX_PAD(0x3E4, 0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_PMIC_RESET_IN_B__PMIC_RESET_IN_B IOMUX_PAD(0x3E8, 0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_PMIC_BOOT_MODE0__PMIC_BOOT_MODE0 IOMUX_PAD(0x3EC, 0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_PMIC_TEST_MODE__PMIC_TEST_MODE IOMUX_PAD(0x3F0, 0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_PMIC_JTAG_TMS__PMIC_JTAG_TMS IOMUX_PAD(0x3F4, 0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_PMIC_JTAG_MOD__PMIC_JTAG_MOD IOMUX_PAD(0x3F8, 0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_PMIC_JTAG_TRSTB__PMIC_JTAG_TRSTB IOMUX_PAD(0x3FC, 0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_PMIC_JTAG_TDI__PMIC_JTAG_TDI IOMUX_PAD(0x400, 0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_PMIC_JTAG_TCK__PMIC_JTAG_TCK IOMUX_PAD(0x404, 0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_PMIC_JTAG_TDO__PMIC_JTAG_TDO IOMUX_PAD(0x408, 0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_DISP_D0__DISP_D0 IOMUX_PAD(0x40C, 0x12C, 0, 0x6fc, 0, MX50_ELCDIF_PAD_CTRL) +#define MX50_PAD_DISP_D0__GPIO_2_0 IOMUX_PAD(0x40C, 0x12C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_D0__FEC_TXCLK IOMUX_PAD(0x40C, 0x12C, 2, 0x78c, 0, PAD_CTL_HYS | PAD_CTL_PKE) + +#define MX50_PAD_DISP_D1__DISP_D1 IOMUX_PAD(0x410, 0x130, 0, 0x700, 0, MX50_ELCDIF_PAD_CTRL) +#define MX50_PAD_DISP_D1__GPIO_2_1 IOMUX_PAD(0x410, 0x130, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_D1__FEC_RX_ER IOMUX_PAD(0x410, 0x130, 2, 0x788, 0, PAD_CTL_HYS | PAD_CTL_PKE) +#define MX50_PAD_DISP_D1__WEIM_A17 IOMUX_PAD(0x410, 0x130, 3, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_DISP_D2__DISP_D2 IOMUX_PAD(0x414, 0x134, 0, 0x704, 0, MX50_ELCDIF_PAD_CTRL) +#define MX50_PAD_DISP_D2__GPIO_2_2 IOMUX_PAD(0x414, 0x134, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_D2__FEC_RX_DV IOMUX_PAD(0x414, 0x134, 2, 0x784, 0, PAD_CTL_HYS | PAD_CTL_PKE) +#define MX50_PAD_DISP_D2__WEIM_A18 IOMUX_PAD(0x414, 0x134, 3, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_DISP_D3__DISP_D3 IOMUX_PAD(0x418, 0x138, 0, 0x708, 0, MX50_ELCDIF_PAD_CTRL) +#define MX50_PAD_DISP_D3__GPIO_2_3 IOMUX_PAD(0x418, 0x138, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_D3__FEC_RXD1 IOMUX_PAD(0x418, 0x138, 2, 0x77C, 0, PAD_CTL_HYS | PAD_CTL_PKE) +#define MX50_PAD_DISP_D3__WEIM_A19 IOMUX_PAD(0x418, 0x138, 3, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_D3__FEC_COL IOMUX_PAD(0x418, 0x138, 4, 0x770, 1, NO_PAD_CTRL) + +#define MX50_PAD_DISP_D4__DISP_D4 IOMUX_PAD(0x41C, 0x13C, 0, 0x70c, 0, MX50_ELCDIF_PAD_CTRL) +#define MX50_PAD_DISP_D4__GPIO_2_4 IOMUX_PAD(0x41C, 0x13C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_D4__FEC_RXD0 IOMUX_PAD(0x41C, 0x13C, 2, 0x778, 0, PAD_CTL_HYS | PAD_CTL_PKE) +#define MX50_PAD_DISP_D4__WEIM_A20 IOMUX_PAD(0x41C, 0x13C, 3, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_DISP_D5__DISP_D5 IOMUX_PAD(0x420, 0x140, 0, 0x710, 0, MX50_ELCDIF_PAD_CTRL) +#define MX50_PAD_DISP_D5__GPIO_2_5 IOMUX_PAD(0x420, 0x140, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_D5__FEC_TX_EN IOMUX_PAD(0x420, 0x140, 2, 0x0, 0, PAD_CTL_DSE_HIGH) +#define MX50_PAD_DISP_D5__WEIM_A21 IOMUX_PAD(0x420, 0x140, 3, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_DISP_D6__DISP_D6 IOMUX_PAD(0x424, 0x144, 0, 0x714, 0, MX50_ELCDIF_PAD_CTRL) +#define MX50_PAD_DISP_D6__GPIO_2_6 IOMUX_PAD(0x424, 0x144, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_D6__FEC_TXD1 IOMUX_PAD(0x424, 0x144, 2, 0x0, 0, PAD_CTL_DSE_HIGH) +#define MX50_PAD_DISP_D6__WEIM_A22 IOMUX_PAD(0x424, 0x144, 3, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_D6__FEC_RX_CLK IOMUX_PAD(0x424, 0x144, 4, 0x780, 1, NO_PAD_CTRL) + +#define MX50_PAD_DISP_D7__DISP_D7 IOMUX_PAD(0x428, 0x148, 0, 0x718, 0, MX50_ELCDIF_PAD_CTRL) +#define MX50_PAD_DISP_D7__GPIO_2_7 IOMUX_PAD(0x428, 0x148, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_D7__FEC_TXD0 IOMUX_PAD(0x428, 0x148, 2, 0x0, 0, PAD_CTL_DSE_HIGH) +#define MX50_PAD_DISP_D7__WEIM_A23 IOMUX_PAD(0x428, 0x148, 3, 0x0, 0, NO_PAD_CTRL) + + +#define MX50_PAD_DISP_WR__ELCDIF_WR IOMUX_PAD(0x42C, 0x14C, 0, 0x0, 0, MX50_ELCDIF_PAD_CTRL) +#define MX50_PAD_DISP_WR__GPIO_2_16 IOMUX_PAD(0x42C, 0x14C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_WR__ELCDIF_PIXCLK IOMUX_PAD(0x42C, 0x14C, 2, 0x0, 0, MX50_ELCDIF_PAD_CTRL) +#define MX50_PAD_DISP_WR__WEIM_A24 IOMUX_PAD(0x42C, 0x14C, 3, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_DISP_RD__ELCDIF_RD IOMUX_PAD(0x430, 0x150, 0, 0x0, 0, MX50_ELCDIF_PAD_CTRL) +#define MX50_PAD_DISP_RD__GPIO_2_19 IOMUX_PAD(0x430, 0x150, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_RD__ELCDIF_EN IOMUX_PAD(0x430, 0x150, 2, 0x0, 0, MX50_ELCDIF_PAD_CTRL) +#define MX50_PAD_DISP_RD__WEIM_A25 IOMUX_PAD(0x430, 0x150, 3, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_DISP_RS__ELCDIF_RS IOMUX_PAD(0x434, 0x154, 0, 0x73c, 1, MX50_ELCDIF_PAD_CTRL) +#define MX50_PAD_DISP_RS__GPIO_2_17 IOMUX_PAD(0x434, 0x154, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_RS__ELCDIF_VSYNC IOMUX_PAD(0x434, 0x154, 2, 0x73c, 1, MX50_ELCDIF_PAD_CTRL) +#define MX50_PAD_DISP_RS__WEIM_A26 IOMUX_PAD(0x434, 0x154, 3, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_DISP_CS__ELCDIF_CS IOMUX_PAD(0x438, 0x158, 0, 0x0, 0, MX50_ELCDIF_PAD_CTRL) +#define MX50_PAD_DISP_CS__GPIO_2_21 IOMUX_PAD(0x438, 0x158, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_CS__ELCDIF_HSYNC IOMUX_PAD(0x438, 0x158, 2, 0x6f8, 1, MX50_ELCDIF_PAD_CTRL) +#define MX50_PAD_DISP_CS__WEIM_A27 IOMUX_PAD(0x438, 0x158, 3, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_CS__WEIM_CS3 IOMUX_PAD(0x438, 0x158, 4, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_DISP_BUSY__ELCDIF_HSYNC IOMUX_PAD(0x43C, 0x15C, 0, 0x6f8, 2, MX50_ELCDIF_PAD_CTRL) +#define MX50_PAD_DISP_BUSY__GPIO_2_18 IOMUX_PAD(0x43C, 0x15C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_BUSY__WEIM_CS3 IOMUX_PAD(0x43C, 0x15C, 3, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_DISP_RESET__ELCDIF_RST IOMUX_PAD(0x440, 0x160, 0, 0x0, 0, MX50_ELCDIF_PAD_CTRL) +#define MX50_PAD_DISP_RESET__GPIO_2_20 IOMUX_PAD(0x440, 0x160, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_RESET__WEIM_CS3 IOMUX_PAD(0x440, 0x160, 4, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_SD3_CMD__SD3_CMD IOMUX_PAD(0x444, 0x164, 0, 0x0, 0, MX50_SD_PAD_CTRL) +#define MX50_PAD_SD3_CMD__GPIO_5_18 IOMUX_PAD(0x444, 0x164, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PIN_SD3_CMD__NANDF_WRN IOMUX_PAD(0x444, 0x164, 2, 0x0, 0, PAD_CTL_DSE_HIGH) +#define MX50_PAD_SD3_CMD__SSP_CMD IOMUX_PAD(0x444, 0x164, 3, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_SD3_CLK__SD3_CLK IOMUX_PAD(0x448, 0x168, 0, 0x0, 0, MX50_SD_PAD_CTRL) +#define MX50_PAD_SD3_CLK__GPIO_5_19 IOMUX_PAD(0x448, 0x168, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PIN_SD3_CLK__NANDF_RDN IOMUX_PAD(0x448, 0x168, 2, 0x0, 0, PAD_CTL_DSE_HIGH) +#define MX50_PAD_SD3_CLK__SSP_CLK IOMUX_PAD(0x448, 0x168, 3, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_SD3_D0__SD3_D0 IOMUX_PAD(0x44C, 0x16C, 0, 0x0, 0, MX50_SD_PAD_CTRL) +#define MX50_PAD_SD3_D0__GPIO_5_20 IOMUX_PAD(0x44C, 0x16C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PIN_SD3_D0__NANDF_D4 IOMUX_PAD(0x44C, 0x16C, 2, 0x0, 0, PAD_CTL_DSE_HIGH) +#define MX50_PAD_SD3_D0__SSP_D0 IOMUX_PAD(0x44C, 0x16C, 3, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_SD3_D0__PLL1_BYP IOMUX_PAD(0x44C, 0x16C, 7, 0x6dc, 1, NO_PAD_CTRL) + +#define MX50_PAD_SD3_D1__SD3_D1 IOMUX_PAD(0x450, 0x170, 0, 0x0, 0, MX50_SD_PAD_CTRL) +#define MX50_PAD_SD3_D1__GPIO_5_21 IOMUX_PAD(0x450, 0x170, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PIN_SD3_D1__NANDF_D5 IOMUX_PAD(0x450, 0x170, 2, 0x0, 0, PAD_CTL_DSE_HIGH) +#define MX50_PAD_SD3_D1__PLL2_BYP IOMUX_PAD(0x450, 0x170, 7, 0x6e0, 1, NO_PAD_CTRL) + +#define MX50_PAD_SD3_D2__SD3_D2 IOMUX_PAD(0x454, 0x174, 0, 0x0, 0, MX50_SD_PAD_CTRL) +#define MX50_PAD_SD3_D2__GPIO_5_22 IOMUX_PAD(0x454, 0x174, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PIN_SD3_D2__NANDF_D6 IOMUX_PAD(0x454, 0x174, 2, 0x0, 0, PAD_CTL_DSE_HIGH) +#define MX50_PAD_SD3_D2__SSP_D2 IOMUX_PAD(0x454, 0x174, 3, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_SD3_D2__PLL3_BYP IOMUX_PAD(0x454, 0x174, 7, 0x6e4, 1, NO_PAD_CTRL) + +#define MX50_PAD_SD3_D3__SD3_D3 IOMUX_PAD(0x458, 0x178, 0, 0x0, 0, MX50_SD_PAD_CTRL) +#define MX50_PAD_SD3_D3__GPIO_5_23 IOMUX_PAD(0x458, 0x178, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PIN_SD3_D3__NANDF_D7 IOMUX_PAD(0x458, 0x178, 2, 0x0, 0, PAD_CTL_DSE_HIGH) +#define MX50_PAD_SD3_D3__SSP_D3 IOMUX_PAD(0x458, 0x178, 3, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_SD3_D4__SD3_D4 IOMUX_PAD(0x45C, 0x17C, 0, 0x0, 0, MX50_SD_PAD_CTRL) +#define MX50_PAD_SD3_D4__GPIO_5_24 IOMUX_PAD(0x45C, 0x17C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PIN_SD3_D4__NANDF_D0 IOMUX_PAD(0x45C, 0x17C, 2, 0x0, 0, PAD_CTL_DSE_HIGH) +#define MX50_PAD_SD3_D4__SSP_D4 IOMUX_PAD(0x45C, 0x17C, 1, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_SD3_D5__SD3_D5 IOMUX_PAD(0x460, 0x180, 0, 0x0, 0, MX50_SD_PAD_CTRL) +#define MX50_PAD_SD3_D5__GPIO_5_25 IOMUX_PAD(0x460, 0x180, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PIN_SD3_D5__NANDF_D1 IOMUX_PAD(0x460, 0x180, 2, 0x0, 0, PAD_CTL_DSE_HIGH) +#define MX50_PAD_SD3_D5__SSP_D5 IOMUX_PAD(0x460, 0x180, 3, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_SD3_D6__SD3_D6 IOMUX_PAD(0x464, 0x184, 0, 0x0, 0, MX50_SD_PAD_CTRL) +#define MX50_PAD_SD3_D6__GPIO_5_26 IOMUX_PAD(0x464, 0x184, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PIN_SD3_D6__NANDF_D2 IOMUX_PAD(0x464, 0x184, 2, 0x0, 0, PAD_CTL_DSE_HIGH) +#define MX50_PAD_SD3_D6__SSP_D6 IOMUX_PAD(0x464, 0x184, 3, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_SD3_D7__SD3_D7 IOMUX_PAD(0x468, 0x188, 0, 0x0, 0, MX50_SD_PAD_CTRL) +#define MX50_PAD_SD3_D7__GPIO_5_27 IOMUX_PAD(0x468, 0x188, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PIN_SD3_D7__NANDF_D3 IOMUX_PAD(0x468, 0x188, 2, 0x0, 0, PAD_CTL_DSE_HIGH) +#define MX50_PAD_SD3_D7__SSP_D7 IOMUX_PAD(0x468, 0x188, 3, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_SD3_WP__SD3_WP IOMUX_PAD(0x46C, 0x18C, 0, 0x0, 0, MX50_SD_PAD_CTRL) +#define MX50_PAD_SD3_WP__GPIO_5_28 IOMUX_PAD(0x46C, 0x18C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PIN_SD3_WP__NANDF_RESETN IOMUX_PAD(0x46C, 0x18C, 2, 0x0, 0, PAD_CTL_DSE_HIGH) +#define MX50_PAD_SD3_WP__SSP_CD IOMUX_PAD(0x46C, 0x18C, 3, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_SD3_WP__SD4_LCTL IOMUX_PAD(0x46C, 0x18C, 4, 0x0, 0, MX50_SD_PAD_CTRL) +#define MX50_PAD_SD3_WP__WEIM_CS3 IOMUX_PAD(0x46C, 0x18C, 5, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_DISP_D8__DISP_D8 IOMUX_PAD(0x470, 0x190, 0, 0x71c, 0, MX50_ELCDIF_PAD_CTRL) +#define MX50_PAD_DISP_D8__GPIO_2_8 IOMUX_PAD(0x470, 0x190, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_D8__NANDF_CLE IOMUX_PAD(0x470, 0x190, 2, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_D8__SD1_LCTL IOMUX_PAD(0x470, 0x190, 3, 0x0, 0, MX50_SD_PAD_CTRL) +#define MX50_PAD_DISP_D8__SD4_CMD IOMUX_PAD(0x470, 0x190, 4, 0x74c, 2, MX50_SD_PAD_CTRL) +#define MX50_PAD_DISP_D8__KEY_COL4 IOMUX_PAD(0x470, 0x190, 5, 0x790, 1, NO_PAD_CTRL) +#define MX50_PAD_DISP_D8__FEC_TX_CLK IOMUX_PAD(0x470, 0x190, 6, 0x78c, 1, NO_PAD_CTRL) + +#define MX50_PAD_DISP_D9__DISP_D9 IOMUX_PAD(0x474, 0x194, 0, 0x720, 0, MX50_ELCDIF_PAD_CTRL) +#define MX50_PAD_DISP_D9__GPIO_2_9 IOMUX_PAD(0x474, 0x194, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_D9__NANDF_ALE IOMUX_PAD(0x474, 0x194, 2, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_D9__SD2_LCTL IOMUX_PAD(0x474, 0x194, 3, 0x0, 0, MX50_SD_PAD_CTRL) +#define MX50_PAD_DISP_D9__SD4_CLK IOMUX_PAD(0x474, 0x194, 4, 0x748, 2, MX50_SD_PAD_CTRL) +#define MX50_PAD_DISP_D9__KEY_ROW4 IOMUX_PAD(0x474, 0x194, 5, 0x7a0, 1, NO_PAD_CTRL) +#define MX50_PAD_DISP_D9__FEC_RX_ER IOMUX_PAD(0x474, 0x194, 6, 0x788, 1, NO_PAD_CTRL) + +#define MX50_PAD_DISP_D10__DISP_D10 IOMUX_PAD(0x478, 0x198, 0, 0x724, 0, MX50_ELCDIF_PAD_CTRL) +#define MX50_PAD_DISP_D10__GPIO_2_10 IOMUX_PAD(0x478, 0x198, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_D10__NANDF_CEN0 IOMUX_PAD(0x478, 0x198, 2, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_D10__SD3_LCTL IOMUX_PAD(0x478, 0x198, 3, 0x0, 0, MX50_SD_PAD_CTRL) +#define MX50_PAD_DISP_D10__SD4_D0 IOMUX_PAD(0x478, 0x198, 4, 0x750, 1, MX50_SD_PAD_CTRL) +#define MX50_PAD_DISP_D10__KEY_COL5 IOMUX_PAD(0x478, 0x198, 5, 0x794, 1, NO_PAD_CTRL) +#define MX50_PAD_DISP_D10__FEC_RX_DV IOMUX_PAD(0x478, 0x198, 6, 0x784, 1, NO_PAD_CTRL) + +#define MX50_PAD_DISP_D11__DISP_D11 IOMUX_PAD(0x47C, 0x19C, 0, 0x728, 0, MX50_ELCDIF_PAD_CTRL) +#define MX50_PAD_DISP_D11__GPIO_2_11 IOMUX_PAD(0x47C, 0x19C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_D11__NANDF_CEN1 IOMUX_PAD(0x47C, 0x19C, 2, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_D11__SD4_D1 IOMUX_PAD(0x47C, 0x19C, 4, 0x754, 1, MX50_SD_PAD_CTRL) +#define MX50_PAD_DISP_D11__KEY_ROW5 IOMUX_PAD(0x47C, 0x19C, 5, 0x7a4, 1, NO_PAD_CTRL) +#define MX50_PAD_DISP_D11__FEC_RDAT1 IOMUX_PAD(0x47C, 0x19C, 6, 0x77c, 1, NO_PAD_CTRL) + +#define MX50_PAD_DISP_D12__DISP_D12 IOMUX_PAD(0x480, 0x1A0, 0, 0x72c, 0, MX50_ELCDIF_PAD_CTRL) +#define MX50_PAD_DISP_D12__GPIO_2_12 IOMUX_PAD(0x480, 0x1A0, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_D12__NANDF_CEN2 IOMUX_PAD(0x480, 0x1A0, 2, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_D12__SD1_CD IOMUX_PAD(0x480, 0x1A0, 3, 0x0, 0, MX50_SD_PAD_CTRL) +#define MX50_PAD_DISP_D12__SD4_D2 IOMUX_PAD(0x480, 0x1A0, 4, 0x758, 1, MX50_SD_PAD_CTRL) +#define MX50_PAD_DISP_D12__KEY_COL6 IOMUX_PAD(0x480, 0x1A0, 5, 0x798, 1, NO_PAD_CTRL) +#define MX50_PAD_DISP_D12__FEC_RDAT0 IOMUX_PAD(0x480, 0x1A0, 6, 0x778, 1, NO_PAD_CTRL) + +#define MX50_PAD_DISP_D13__DISP_D13 IOMUX_PAD(0x484, 0x1A4, 0, 0x730, 0, MX50_ELCDIF_PAD_CTRL) +#define MX50_PAD_DISP_D13__GPIO_2_13 IOMUX_PAD(0x484, 0x1A4, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_D13__NANDF_CEN3 IOMUX_PAD(0x484, 0x1A4, 2, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_D13__SD3_CD IOMUX_PAD(0x484, 0x1A4, 3, 0x0, 0, MX50_SD_PAD_CTRL) +#define MX50_PAD_DISP_D13__SD4_D3 IOMUX_PAD(0x484, 0x1A4, 4, 0x75c, 1, MX50_SD_PAD_CTRL) +#define MX50_PAD_DISP_D13__KEY_ROW6 IOMUX_PAD(0x484, 0x1A4, 5, 0x7a8, 1, NO_PAD_CTRL) +#define MX50_PAD_DISP_D13__FEC_TX_EN IOMUX_PAD(0x484, 0x1A4, 6, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_DISP_D14__DISP_D14 IOMUX_PAD(0x488, 0x1A8, 0, 0x734, 0, MX50_ELCDIF_PAD_CTRL) +#define MX50_PAD_DISP_D14__GPIO_2_14 IOMUX_PAD(0x488, 0x1A8, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_D14__NANDF_RDY0 IOMUX_PAD(0x488, 0x1A8, 2, 0x7b4, 1, NO_PAD_CTRL) +#define MX50_PAD_DISP_D14__SD1_WP IOMUX_PAD(0x488, 0x1A8, 3, 0x0, 0, MX50_SD_PAD_CTRL) +#define MX50_PAD_DISP_D14__SD4_WP IOMUX_PAD(0x488, 0x1A8, 4, 0x0, 0, MX50_SD_PAD_CTRL) +#define MX50_PAD_DISP_D14__KEY_COL7 IOMUX_PAD(0x488, 0x1A8, 5, 0x79c, 1, NO_PAD_CTRL) +#define MX50_PAD_DISP_D14__FEC_TDAT1 IOMUX_PAD(0x488, 0x1A8, 6, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_DISP_D15__DISP_D15 IOMUX_PAD(0x48C, 0x1AC, 0, 0x738, 0, MX50_ELCDIF_PAD_CTRL) +#define MX50_PAD_DISP_D15__GPIO_2_15 IOMUX_PAD(0x48C, 0x1AC, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_D15__NANDF_DQS IOMUX_PAD(0x48C, 0x1AC, 2, 0x7b0, 1, NO_PAD_CTRL) +#define MX50_PAD_DISP_D15__SD3_RST IOMUX_PAD(0x48C, 0x1AC, 3, 0x0, 0, MX50_SD_PAD_CTRL) +#define MX50_PAD_DISP_D15__SD4_CD IOMUX_PAD(0x48C, 0x1AC, 4, 0x0, 0, MX50_SD_PAD_CTRL) +#define MX50_PAD_DISP_D15__KEY_ROW7 IOMUX_PAD(0x48C, 0x1AC, 5, 0x7ac, 1, NO_PAD_CTRL) +#define MX50_PAD_DISP_D15__FEC_TDAT0 IOMUX_PAD(0x48C, 0x1AC, 6, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_EPDC_D0__EPDC_D0 IOMUX_PAD(0x54C, 0x1B0, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D0__GPIO_3_0 IOMUX_PAD(0x54C, 0x1B0, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D0__WEIM_D0 IOMUX_PAD(0x54C, 0x1B0, 2, 0x7ec, 1, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D0__ELCDIF_RS IOMUX_PAD(0x54C, 0x1B0, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL) +#define MX50_PAD_EPDC_D0__ELCDIF_PIXCLK IOMUX_PAD(0x54C, 0x1B0, 4, 0x0, 0, MX50_ELCDIF_PAD_CTRL) + +#define MX50_PAD_EPDC_D1__EPDC_D1 IOMUX_PAD(0x550, 0x1B4, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D1__GPIO_3_1 IOMUX_PAD(0x550, 0x1B4, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D1__WEIM_D1 IOMUX_PAD(0x550, 0x1B4, 2, 0x7f0, 1, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D1__ELCDIF_CS IOMUX_PAD(0x550, 0x1B4, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL) +#define MX50_PAD_EPDC_D1__ELCDIF_EN IOMUX_PAD(0x550, 0x1B4, 4, 0x0, 0, MX50_ELCDIF_PAD_CTRL) + +#define MX50_PAD_EPDC_D2__EPDC_D2 IOMUX_PAD(0x554, 0x1B8, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D2__GPIO_3_2 IOMUX_PAD(0x554, 0x1B8, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D2__WEIM_D2 IOMUX_PAD(0x554, 0x1B8, 2, 0x7f4, 1, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D2__ELCDIF_WR IOMUX_PAD(0x554, 0x1B8, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL) +#define MX50_PAD_EPDC_D2__ELCDIF_VSYNC IOMUX_PAD(0x554, 0x1B8, 4, 0x73c, 2, MX50_ELCDIF_PAD_CTRL) + +#define MX50_PAD_EPDC_D3__EPDC_D3 IOMUX_PAD(0x558, 0x1BC, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D3__GPIO_3_3 IOMUX_PAD(0x558, 0x1BC, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D3__WEIM_D3 IOMUX_PAD(0x558, 0x1BC, 2, 0x7f8, 1, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D3__ELCDIF_RD IOMUX_PAD(0x558, 0x1BC, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL) +#define MX50_PAD_EPDC_D3__ELCDIF_HSYNC IOMUX_PAD(0x558, 0x1BC, 4, 0x6f8, 3, MX50_ELCDIF_PAD_CTRL) + +#define MX50_PAD_EPDC_D4__EPDC_D4 IOMUX_PAD(0x55C, 0x1C0, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D4__GPIO_3_4 IOMUX_PAD(0x55C, 0x1C0, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D4__WEIM_D4 IOMUX_PAD(0x55C, 0x1C0, 2, 0x7fc, 1, NO_PAD_CTRL) + +#define MX50_PAD_EPDC_D5__EPDC_D5 IOMUX_PAD(0x560, 0x1C4, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D5__GPIO_3_5 IOMUX_PAD(0x560, 0x1C4, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D5__WEIM_D5 IOMUX_PAD(0x560, 0x1C4, 2, 0x800, 1, NO_PAD_CTRL) + +#define MX50_PAD_EPDC_D6__EPDC_D6 IOMUX_PAD(0x564, 0x1C8, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D6__GPIO_3_6 IOMUX_PAD(0x564, 0x1C8, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D6__WEIM_D6 IOMUX_PAD(0x564, 0x1C8, 2, 0x804, 1, NO_PAD_CTRL) + +#define MX50_PAD_EPDC_D7__EPDC_D7 IOMUX_PAD(0x568, 0x1CC, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D7__GPIO_3_7 IOMUX_PAD(0x568, 0x1CC, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D7__WEIM_D7 IOMUX_PAD(0x568, 0x1CC, 2, 0x808, 1, NO_PAD_CTRL) + +#define MX50_PAD_EPDC_D8__EPDC_D8 IOMUX_PAD(0x56C, 0x1D0, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D8__GPIO_3_8 IOMUX_PAD(0x56C, 0x1D0, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D8__WEIM_D8 IOMUX_PAD(0x56C, 0x1D0, 2, 0x80c, 2, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D8__ELCDIF_D24 IOMUX_PAD(0x56C, 0x1D0, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL) + +#define MX50_PAD_EPDC_D9__EPDC_D9 IOMUX_PAD(0x570, 0x1D4, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D9__GPIO_3_9 IOMUX_PAD(0x570, 0x1D4, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D9__WEIM_D9 IOMUX_PAD(0x570, 0x1D4, 2, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D9__ELCDIF_D25 IOMUX_PAD(0x570, 0x1D4, 3, 0x810, 2, MX50_ELCDIF_PAD_CTRL) + +#define MX50_PAD_EPDC_D10__EPDC_D10 IOMUX_PAD(0x574, 0x1D8, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D10__GPIO_3_10 IOMUX_PAD(0x574, 0x1D8, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D10__WEIM_D10 IOMUX_PAD(0x574, 0x1D8, 2, 0x814, 2, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D10__ELCDIF_D26 IOMUX_PAD(0x574, 0x1D8, 3, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_EPDC_D11__EPDC_D11 IOMUX_PAD(0x578, 0x1DC, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D11__GPIO_3_11 IOMUX_PAD(0x578, 0x1DC, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D11__WEIM_D11 IOMUX_PAD(0x578, 0x1DC, 2, 0x818, 2, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D11__ELCDIF_D27 IOMUX_PAD(0x578, 0x1DC, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL) + +#define MX50_PAD_EPDC_D12__EPDC_D12 IOMUX_PAD(0x57C, 0x1E0, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D12__GPIO_3_12 IOMUX_PAD(0x57C, 0x1E0, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D12__WEIM_D12 IOMUX_PAD(0x57C, 0x1E0, 2, 0x81c, 1, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D12__ELCDIF_D28 IOMUX_PAD(0x57C, 0x1E0, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL) + +#define MX50_PAD_EPDC_D13__EPDC_D13 IOMUX_PAD(0x580, 0x1E4, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D13__GPIO_3_13 IOMUX_PAD(0x580, 0x1E4, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D13__WEIM_D13 IOMUX_PAD(0x580, 0x1E4, 2, 0x820, 1, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D13__ELCDIF_D29 IOMUX_PAD(0x580, 0x1E4, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL) + +#define MX50_PAD_EPDC_D14__EPDC_D14 IOMUX_PAD(0x584, 0x1E8, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D14__GPIO_3_14 IOMUX_PAD(0x584, 0x1E8, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D14__WEIM_D14 IOMUX_PAD(0x584, 0x1E8, 2, 0x824, 1, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D14__ELCDIF_D30 IOMUX_PAD(0x584, 0x1E8, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL) +#define MX50_PAD_EPDC_D14__AUD6_TXD IOMUX_PAD(0x584, 0x1E8, 4, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_EPDC_D15__EPDC_D15 IOMUX_PAD(0x588, 0x1EC, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D15__GPIO_3_15 IOMUX_PAD(0x588, 0x1EC, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D15__WEIM_D15 IOMUX_PAD(0x588, 0x1EC, 2, 0x828, 1, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D15__ELCDIF_D31 IOMUX_PAD(0x588, 0x1EC, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL) +#define MX50_PAD_EPDC_D15__AUD6_TXC IOMUX_PAD(0x588, 0x1EC, 4, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_EPDC_GDCLK__EPDC_GDCLK IOMUX_PAD(0x58C, 0x1F0, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_GDCLK__GPIO_3_16 IOMUX_PAD(0x58C, 0x1F0, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_GDCLK__WEIM_D16 IOMUX_PAD(0x58C, 0x1F0, 2, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_GDCLK__ELCDIF_D16 IOMUX_PAD(0x58C, 0x1F0, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL) +#define MX50_PAD_EPDC_GDCLK__AUD6_TXFS IOMUX_PAD(0x58C, 0x1F0, 4, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_EPDC_GDSP__EPDC_GDSP IOMUX_PAD(0x590, 0x1F4, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_GDSP__GPIO_3_17 IOMUX_PAD(0x590, 0x1F4, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_GDSP__WEIM_D17 IOMUX_PAD(0x590, 0x1F4, 2, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_GDSP__ELCDIF_D17 IOMUX_PAD(0x590, 0x1F4, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL) +#define MX50_PAD_EPDC_GDSP__AUD6_RXD IOMUX_PAD(0x590, 0x1F4, 4, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_EPDC_GDOE__EPDC_GDOE IOMUX_PAD(0x594, 0x1F8, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_GDOE__GPIO_3_18 IOMUX_PAD(0x594, 0x1F8, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_GDOE__WEIM_D18 IOMUX_PAD(0x594, 0x1F8, 2, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_GDOE__ELCDIF_D18 IOMUX_PAD(0x594, 0x1F8, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL) +#define MX50_PAD_EPDC_GDOE__AUD6_RXC IOMUX_PAD(0x594, 0x1F8, 4, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_EPDC_GDRL__EPDC_GDRL IOMUX_PAD(0x598, 0x1FC, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_GDRL__GPIO_3_19 IOMUX_PAD(0x598, 0x1FC, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_GDRL__WEIM_D19 IOMUX_PAD(0x598, 0x1FC, 2, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_GDRL__ELCDIF_D19 IOMUX_PAD(0x598, 0x1FC, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL) +#define MX50_PAD_EPDC_GDRL__AUD6_RXFS IOMUX_PAD(0x598, 0x1FC, 4, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_EPDC_SDCLK__EPDC_SDCLK IOMUX_PAD(0x59C, 0x200, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDCLK__GPIO_3_20 IOMUX_PAD(0x59C, 0x200, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDCLK__WEIM_D20 IOMUX_PAD(0x59C, 0x200, 2, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDCLK__ELCDIF_D20 IOMUX_PAD(0x59C, 0x200, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL) +#define MX50_PAD_EPDC_SDCLK__AUD5_TXD IOMUX_PAD(0x59C, 0x200, 4, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_EPDC_SDOEZ__EPDC_SDOEZ IOMUX_PAD(0x5A0, 0x204, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDOEZ__GPIO_3_21 IOMUX_PAD(0x5A0, 0x204, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDOEZ__WEIM_D21 IOMUX_PAD(0x5A0, 0x204, 2, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDOEZ__ELCDIF_D21 IOMUX_PAD(0x5A0, 0x204, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL) +#define MX50_PAD_EPDC_SDOEZ__AUD5_TXC IOMUX_PAD(0x5A0, 0x204, 4, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_EPDC_SDOED__EPDC_SDOED IOMUX_PAD(0x5A4, 0x208, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDOED__GPIO_3_22 IOMUX_PAD(0x5A4, 0x208, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDOED__WEIM_D22 IOMUX_PAD(0x5A4, 0x208, 2, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDOED__ELCDIF_D22 IOMUX_PAD(0x5A4, 0x208, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL) +#define MX50_PAD_EPDC_SDOED__AUD5_TXFS IOMUX_PAD(0x5A4, 0x208, 4, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_EPDC_SDOE__EPDC_SDOE IOMUX_PAD(0x5A8, 0x20C, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDOE__GPIO_3_23 IOMUX_PAD(0x5A8, 0x20C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDOE__WEIM_D23 IOMUX_PAD(0x5A8, 0x20C, 2, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDOE__ELCDIF_D23 IOMUX_PAD(0x5A8, 0x20C, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL) +#define MX50_PAD_EPDC_SDOE__AUD5_RXD IOMUX_PAD(0x5A8, 0x20C, 4, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_EPDC_SDLE__EPDC_SDLE IOMUX_PAD(0x5AC, 0x210, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDLE__GPIO_3_24 IOMUX_PAD(0x5AC, 0x210, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDLE__WEIM_D24 IOMUX_PAD(0x5AC, 0x210, 2, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDLE__ELCDIF_D8 IOMUX_PAD(0x5AC, 0x210, 3, 0x71c, 1, MX50_ELCDIF_PAD_CTRL) +#define MX50_PAD_EPDC_SDLE__AUD5_RXC IOMUX_PAD(0x5AC, 0x210, 4, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_EPDC_SDCLKN__EPDC_SDCLKN IOMUX_PAD(0x5B0, 0x214, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDCLKN__GPIO_3_25 IOMUX_PAD(0x5B0, 0x214, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDCLKN__WEIM_D25 IOMUX_PAD(0x5B0, 0x214, 2, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDCLKN__ELCDIF_D9 IOMUX_PAD(0x5B0, 0x214, 3, 0x720, 1, MX50_ELCDIF_PAD_CTRL) +#define MX50_PAD_EPDC_SDCLKN__AUD5_RXFS IOMUX_PAD(0x5B0, 0x214, 4, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_EPDC_SDSHR__EPDC_SDSHR IOMUX_PAD(0x5B4, 0x218, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDSHR__GPIO_3_26 IOMUX_PAD(0x5B4, 0x218, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDSHR__WEIM_D26 IOMUX_PAD(0x5B4, 0x218, 2, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDSHR__ELCDIF_D10 IOMUX_PAD(0x5B4, 0x218, 3, 0x724, 1, MX50_ELCDIF_PAD_CTRL) +#define MX50_PAD_EPDC_SDSHR__AUD4_TXD IOMUX_PAD(0x5B4, 0x218, 4, 0x6c8, 1, NO_PAD_CTRL) + +#define MX50_PAD_EPDC_PWRCOM__EPDC_PWRCOM IOMUX_PAD(0x5B8, 0x21C, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_PWRCOM__GPIO_3_27 IOMUX_PAD(0x5B8, 0x21C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_PWRCOM__WEIM_D27 IOMUX_PAD(0x5B8, 0x21C, 2, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_PWRCOM__ELCDIF_D11 IOMUX_PAD(0x5B8, 0x21C, 3, 0x728, 1, MX50_ELCDIF_PAD_CTRL) +#define MX50_PAD_EPDC_PWRCOM__AUD4_TXC IOMUX_PAD(0x5B8, 0x21C, 4, 0x6d4, 1, NO_PAD_CTRL) + +#define MX50_PAD_EPDC_PWRSTAT__EPDC_PWRSTAT IOMUX_PAD(0x5BC, 0x220, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_PWRSTAT__GPIO_3_28 IOMUX_PAD(0x5BC, 0x220, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_PWRSTAT__WEIM_D28 IOMUX_PAD(0x5BC, 0x220, 2, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_PWRSTAT__ELCDIF_D12 IOMUX_PAD(0x5BC, 0x220, 3, 0x72c, 1, MX50_ELCDIF_PAD_CTRL) +#define MX50_PAD_EPDC_PWRSTAT__AUD4_TXFS IOMUX_PAD(0x5BC, 0x220, 4, 0x6d8, 1, NO_PAD_CTRL) + +#define MX50_PAD_EPDC_PWRCTRL0__EPDC_PWRCTRL0 IOMUX_PAD(0x5C0, 0x224, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_PWRCTRL0__GPIO_3_29 IOMUX_PAD(0x5C0, 0x224, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_PWRCTRL0__WEIM_D29 IOMUX_PAD(0x5C0, 0x224, 2, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_PWRCTRL0__ELCDIF_D13 IOMUX_PAD(0x5C0, 0x224, 3, 0x730, 1, MX50_ELCDIF_PAD_CTRL) +#define MX50_PAD_EPDC_PWRCTRL0__AUD4_RXD IOMUX_PAD(0x5C0, 0x224, 4, 0x6c4, 1, NO_PAD_CTRL) + +#define MX50_PAD_EPDC_PWRCTRL1__EPDC_PWRCTRL1 IOMUX_PAD(0x5C4, 0x228, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_PWRCTRL1__GPIO_3_30 IOMUX_PAD(0x5C4, 0x228, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_PWRCTRL1__WEIM_D30 IOMUX_PAD(0x5C4, 0x228, 2, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_PWRCTRL1__ELCDIF_D14 IOMUX_PAD(0x5C4, 0x228, 3, 0x734, 1, MX50_ELCDIF_PAD_CTRL) +#define MX50_PAD_EPDC_PWRCTRL1__AUD4_RXC IOMUX_PAD(0x5C4, 0x228, 4, 0x6cc, 1, NO_PAD_CTRL) + +#define MX50_PAD_EPDC_PWRCTRL2__EPDC_PWRCTRL2 IOMUX_PAD(0x5C8, 0x22C, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_PWRCTRL2__GPIO_3_31 IOMUX_PAD(0x5C8, 0x22C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_PWRCTRL2__WEIM_D31 IOMUX_PAD(0x5C8, 0x22C, 2, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_PWRCTRL2__ELCDIF_D15 IOMUX_PAD(0x5C8, 0x22C, 3, 0x738, 1, MX50_ELCDIF_PAD_CTRL) +#define MX50_PAD_EPDC_PWRCTRL2__AUD4_RXFS IOMUX_PAD(0x5C8, 0x22C, 4, 0x6d0, 1, NO_PAD_CTRL) +#define MX50_PAD_EPDC_PWRCTRL2__SDMA_EXT0 IOMUX_PAD(0x5C8, 0x22C, 6, 0x7b8, 1, NO_PAD_CTRL) + +#define MX50_PAD_EPDC_PWRCTRL3__PWRCTRL3 IOMUX_PAD(0x5CC, 0x230, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_PWRCTRL3__GPIO_4_20 IOMUX_PAD(0x5CC, 0x230, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_PWRCTRL3__WEIM_EB2 IOMUX_PAD(0x5CC, 0x230, 2, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_PWRCTRL3__SDMA_EXT1 IOMUX_PAD(0x5CC, 0x230, 6, 0x7bc, 1, NO_PAD_CTRL) + +#define MX50_PAD_EPDC_VCOM0__EPDC_VCOM0 IOMUX_PAD(0x5D0, 0x234, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_VCOM0__GPIO_4_21 IOMUX_PAD(0x5D0, 0x234, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_VCOM0__WEIM_EB3 IOMUX_PAD(0x5D0, 0x234, 2, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_EPDC_VCOM1__EPDC_VCOM1 IOMUX_PAD(0x5D4, 0x238, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_VCOM1__GPIO_4_22 IOMUX_PAD(0x5D4, 0x238, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_VCOM1__WEIM_CS3 IOMUX_PAD(0x5D4, 0x238, 2, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_EPDC_BDR0__EPDC_BDR0 IOMUX_PAD(0x5D8, 0x23C, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_BDR0__GPIO_4_23 IOMUX_PAD(0x5D8, 0x23C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_BDR0__ELCDIF_D7 IOMUX_PAD(0x5D8, 0x23C, 3, 0x718, 1, MX50_ELCDIF_PAD_CTRL) + +#define MX50_PAD_EPDC_BDR1__EPDC_BDR1 IOMUX_PAD(0x5DC, 0x240, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_BDR1__GPIO_4_24 IOMUX_PAD(0x5DC, 0x240, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_BDR1__ELCDIF_D6 IOMUX_PAD(0x5DC, 0x240, 3, 0x714, 1, MX50_ELCDIF_PAD_CTRL) + +#define MX50_PAD_EPDC_SDCE0__EPDC_SDCE0 IOMUX_PAD(0x5E0, 0x244, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDCE0__GPIO_4_25 IOMUX_PAD(0x5E0, 0x244, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDCE0__ELCDIF_D5 IOMUX_PAD(0x5E0, 0x244, 3, 0x710, 1, MX50_ELCDIF_PAD_CTRL) + +#define MX50_PAD_EPDC_SDCE1__EPDC_SDCE1 IOMUX_PAD(0x5E4, 0x248, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDCE1__GPIO_4_26 IOMUX_PAD(0x5E4, 0x248, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDCE1__ELCDIF_D4 IOMUX_PAD(0x5E4, 0x248, 2, 0x70c, 1, MX50_ELCDIF_PAD_CTRL) + +#define MX50_PAD_EPDC_SDCE2__EPDC_SDCE2 IOMUX_PAD(0x5E8, 0x24C, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDCE2__GPIO_4_27 IOMUX_PAD(0x5E8, 0x24C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDCE2__ELCDIF_DAT3 IOMUX_PAD(0x5E8, 0x24C, 3, 0x708, 1, MX50_ELCDIF_PAD_CTRL) + +#define MX50_PAD_EPDC_SDCE3__EPDC_SDCE3 IOMUX_PAD(0x5EC, 0x250, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDCE3__GPIO_4_28 IOMUX_PAD(0x5EC, 0x250, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDCE3__ELCDIF_D2 IOMUX_PAD(0x5EC, 0x250, 3, 0x704, 1, MX50_ELCDIF_PAD_CTRL) + +#define MX50_PAD_EPDC_SDCE4__EPDC_SDCE4 IOMUX_PAD(0x5F0, 0x254, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDCE4__GPIO_4_29 IOMUX_PAD(0x5F0, 0x254, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDCE4__ELCDIF_D1 IOMUX_PAD(0x5F0, 0x254, 3, 0x700, 1, MX50_ELCDIF_PAD_CTRL) + +#define MX50_PAD_EPDC_SDCE5__EPDC_SDCE5 IOMUX_PAD(0x5F4, 0x258, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDCE5__GPIO_4_30 IOMUX_PAD(0x5F4, 0x258, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDCE5__ELCDIF_D0 IOMUX_PAD(0x5F4, 0x258, 3, 0x6fc, 1, MX50_ELCDIF_PAD_CTRL) + +#define MX50_PAD_EIM_DA0__WEIM_A0 IOMUX_PAD(0x5F8, 0x25C, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_DA0__GPIO_1_0 IOMUX_PAD(0x5F8, 0x25C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_DA0__KEY_COL4 IOMUX_PAD(0x5f8, 0x25C, 3, 0x790, 2, NO_PAD_CTRL) + +#define MX50_PAD_EIM_DA1__WEIM_A1 IOMUX_PAD(0x5FC, 0x260, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_DA1__GPIO_1_1 IOMUX_PAD(0x5FC, 0x260, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_DA1__KEY_ROW4 IOMUX_PAD(0x5fc, 0x260, 3, 0x7a0, 2, MX50_KEYPAD_CTRL) + +#define MX50_PAD_EIM_DA2__WEIM_A2 IOMUX_PAD(0x600, 0x264, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_DA2__GPIO_1_2 IOMUX_PAD(0x600, 0x264, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_DA2__KEY_COL5 IOMUX_PAD(0x600, 0x264, 3, 0x794, 2, NO_PAD_CTRL) + +#define MX50_PAD_EIM_DA3__WEIM_A3 IOMUX_PAD(0x604, 0x268, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_DA3__GPIO_1_3 IOMUX_PAD(0x604, 0x268, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_DA3__KEY_ROW5 IOMUX_PAD(0x604, 0x268, 3, 0x7a4, 2, MX50_KEYPAD_CTRL) + +#define MX50_PAD_EIM_DA4__WEIM_A4 IOMUX_PAD(0x608, 0x26C, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_DA4__GPIO_1_4 IOMUX_PAD(0x608, 0x26C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_DA4__KEY_COL6 IOMUX_PAD(0x608, 0x26C, 3, 0x798, 2, NO_PAD_CTRL) + +#define MX50_PAD_EIM_DA5__WEIM_A5 IOMUX_PAD(0x60C, 0x270, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_DA5__GPIO_1_5 IOMUX_PAD(0x60C, 0x270, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_DA5__KEY_ROW6 IOMUX_PAD(0x60C, 0x270, 3, 0x7a8, 2, MX50_KEYPAD_CTRL) + +#define MX50_PAD_EIM_DA6__WEIM_A6 IOMUX_PAD(0x610, 0x274, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_DA6__GPIO_1_6 IOMUX_PAD(0x610, 0x274, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_DA6__KEY_COL7 IOMUX_PAD(0x610, 0x274, 3, 0x79c, 2, NO_PAD_CTRL) + +#define MX50_PAD_EIM_DA7__WEIM_A7 IOMUX_PAD(0x614, 0x278, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_DA7__GPIO_1_7 IOMUX_PAD(0x614, 0x278, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_DA7__KEY_ROW7 IOMUX_PAD(0x614, 0x278, 3, 0x7ac, 2, MX50_KEYPAD_CTRL) + +#define MX50_PAD_EIM_DA8__WEIM_A8 IOMUX_PAD(0x618, 0x27C, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_DA8__GPIO_1_8 IOMUX_PAD(0x618, 0x27C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PIN_EIM_DA8__NANDF_CLE IOMUX_PAD(0x618, 0x27C, 2, 0x0, 0, PAD_CTL_DSE_HIGH) + +#define MX50_PAD_EIM_DA9__WEIM_A9 IOMUX_PAD(0x61C, 0x280, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_DA9__GPIO_1_9 IOMUX_PAD(0x61C, 0x280, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PIN_EIM_DA9__NANDF_ALE IOMUX_PAD(0x61C, 0x280, 2, 0x0, 0, PAD_CTL_DSE_HIGH) + +#define MX50_PAD_EIM_DA10__WEIM_A10 IOMUX_PAD(0x620, 0x284, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_DA10__GPIO_1_10 IOMUX_PAD(0x620, 0x284, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PIN_EIM_DA10__NANDF_CE0 IOMUX_PAD(0x620, 0x284, 2, 0x0, 0, PAD_CTL_DSE_HIGH) + +#define MX50_PAD_EIM_DA11__WEIM_A11 IOMUX_PAD(0x624, 0x288, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_DA11__GPIO_1_11 IOMUX_PAD(0x624, 0x288, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PIN_EIM_DA11__NANDF_CE1 IOMUX_PAD(0x624, 0x288, 2, 0x0, 0, PAD_CTL_DSE_HIGH) + +#define MX50_PAD_EIM_DA12__WEIM_A12 IOMUX_PAD(0x628, 0x28C, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_DA12__GPIO_1_12 IOMUX_PAD(0x628, 0x28C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PIN_EIM_DA12__NANDF_CE2 IOMUX_PAD(0x628, 0x28C, 2, 0x0, 0, PAD_CTL_DSE_HIGH) +#define MX50_PAD_EIM_DA12__EPDC_SDCE6 IOMUX_PAD(0x628, 0x28C, 3, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_EIM_DA13__WEIM_A13 IOMUX_PAD(0x62C, 0x290, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_DA13__GPIO_1_13 IOMUX_PAD(0x62C, 0x290, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PIN_EIM_DA13__NANDF_CE3 IOMUX_PAD(0x62C, 0x290, 2, 0x0, 0, PAD_CTL_DSE_HIGH) +#define MX50_PIN_EIM_DA13__EPDC_SDCE7 IOMUX_PAD(0x62C, 0x290, 3, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_EIM_DA14__WEIM_A14 IOMUX_PAD(0x630, 0x294, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_DA14__GPIO_1_14 IOMUX_PAD(0x630, 0x294, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_DA14__NANDF_READY IOMUX_PAD(0x630, 0x294, 2, 0x7B4, 2, PAD_CTL_PKE | \ + PAD_CTL_PUE | PAD_CTL_PUS_100K_UP) +#define MX50_PAD_EIM_DA14__EPDC_SDCE8 IOMUX_PAD(0x630, 0x294, 3, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_EIM_DA15__WEIM_A15 IOMUX_PAD(0x634, 0x298, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_DA15__GPIO_1_15 IOMUX_PAD(0x634, 0x298, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PIN_EIM_DA15__NANDF_DQS IOMUX_PAD(0x634, 0x298, 2, 0x7B0, 2, PAD_CTL_DSE_HIGH) +#define MX50_PAD_EIM_DA15__EPDC_SDCE9 IOMUX_PAD(0x634, 0x298, 3, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_EIM_CS2__WEIM_CS2 IOMUX_PAD(0x638, 0x29C, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_CS2__GPIO_1_16 IOMUX_PAD(0x638, 0x29C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_CS2__WEIM_A27 IOMUX_PAD(0x638, 0x29C, 2, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_EIM_CS1__WEIM_CS1 IOMUX_PAD(0x63C, 0x2A0, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_CS1__GPIO_1_17 IOMUX_PAD(0x63C, 0x2A0, 1, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_EIM_CS0__WEIM_CS0 IOMUX_PAD(0x640, 0x2A4, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_CS0__GPIO_1_18 IOMUX_PAD(0x640, 0x2A4, 1, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_EIM_EB0__WEIM_EB0 IOMUX_PAD(0x644, 0x2A8, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_EB0__GPIO_1_19 IOMUX_PAD(0x644, 0x2A8, 1, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_EIM_EB1__WEIM_EB1 IOMUX_PAD(0x648, 0x2AC, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_EB1__GPIO_1_20 IOMUX_PAD(0x648, 0x2AC, 1, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_EIM_WAIT__WEIM_WAIT IOMUX_PAD(0x64C, 0x2B0, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_WAIT__GPIO_1_21 IOMUX_PAD(0x64C, 0x2B0, 1, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_EIM_BCLK__WEIM_BCLK IOMUX_PAD(0x650, 0x2B4, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_BCLK__GPIO_1_22 IOMUX_PAD(0x650, 0x2B4, 1, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_EIM_RDY__WEIM_RDY IOMUX_PAD(0x654, 0x2B8, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_RDY__GPIO_1_23 IOMUX_PAD(0x654, 0x2B8, 1, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_EIM_OE__WEIM_OE IOMUX_PAD(0x658, 0x2BC, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_OE__GPIO_1_24 IOMUX_PAD(0x658, 0x2BC, 1, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_EIM_RW__WEIM_RW IOMUX_PAD(0x65C, 0x2C0, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_RW__GPIO_1_25 IOMUX_PAD(0x65C, 0x2C0, 1, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_EIM_LBA__WEIM_LBA IOMUX_PAD(0x660, 0x2C4, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_LBA__GPIO_1_26 IOMUX_PAD(0x660, 0x2C4, 1, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_EIM_CRE__WEIM_CRE IOMUX_PAD(0x664, 0x2C8, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_CRE__GPIO_1_27 IOMUX_PAD(0x664, 0x2C8, 1, 0x0, 0, NO_PAD_CTRL) + +#endif /* __MACH_IOMUX_MX50_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/irqs.h b/arch/arm/plat-mxc/include/mach/irqs.h index 769a137..064026b 100644 --- a/arch/arm/plat-mxc/include/mach/irqs.h +++ b/arch/arm/plat-mxc/include/mach/irqs.h @@ -25,6 +25,8 @@ /* these are ordered by size to support multi-SoC kernels */ #if defined CONFIG_ARCH_MX2 #define MXC_GPIO_IRQS (32 * 6) +#elif defined CONFIG_ARCH_MX50 +#define MXC_GPIO_IRQS (32 * 6) #elif defined CONFIG_ARCH_MX1 #define MXC_GPIO_IRQS (32 * 4) #elif defined CONFIG_ARCH_MX25 diff --git a/arch/arm/plat-mxc/include/mach/memory.h b/arch/arm/plat-mxc/include/mach/memory.h index 9a9a000..8386140 100644 --- a/arch/arm/plat-mxc/include/mach/memory.h +++ b/arch/arm/plat-mxc/include/mach/memory.h @@ -16,6 +16,7 @@ #define MX25_PHYS_OFFSET UL(0x80000000) #define MX27_PHYS_OFFSET UL(0xa0000000) #define MX3x_PHYS_OFFSET UL(0x80000000) +#define MX50_PHYS_OFFSET UL(0x70000000) #define MX51_PHYS_OFFSET UL(0x90000000) #define MX53_PHYS_OFFSET UL(0x70000000) #define MXC91231_PHYS_OFFSET UL(0x90000000) @@ -33,6 +34,8 @@ # define PHYS_OFFSET MX3x_PHYS_OFFSET # elif defined CONFIG_ARCH_MXC91231 # define PHYS_OFFSET MXC91231_PHYS_OFFSET +# elif defined CONFIG_ARCH_MX50 +# define PHYS_OFFSET MX50_PHYS_OFFSET # elif defined CONFIG_ARCH_MX51 # define PHYS_OFFSET MX51_PHYS_OFFSET # elif defined CONFIG_ARCH_MX53 diff --git a/arch/arm/plat-mxc/include/mach/mx50.h b/arch/arm/plat-mxc/include/mach/mx50.h new file mode 100644 index 0000000..aaec2a6 --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/mx50.h @@ -0,0 +1,285 @@ +#ifndef __MACH_MX50_H__ +#define __MACH_MX50_H__ + +/* + * IROM + */ +#define MX50_IROM_BASE_ADDR 0x0 +#define MX50_IROM_SIZE SZ_64K + +/* TZIC */ +#define MX50_TZIC_BASE_ADDR 0x0fffc000 +#define MX50_TZIC_SIZE SZ_16K + +/* + * IRAM + */ +#define MX50_IRAM_BASE_ADDR 0xf8000000 /* internal ram */ +#define MX50_IRAM_PARTITIONS 16 +#define MX50_IRAM_SIZE (MX50_IRAM_PARTITIONS * SZ_8K) /* 128KB */ + +/* + * Databahn + */ +#define MX50_DATABAHN_BASE_ADDR 0x14000000 + +/* + * Graphics Memory of GPU + */ +#define MX50_GPU2D_BASE_ADDR 0x20000000 + +#define MX50_DEBUG_BASE_ADDR 0x40000000 +#define MX50_DEBUG_SIZE SZ_1M +#define MX50_ETB_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x00001000) +#define MX50_ETM_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x00002000) +#define MX50_TPIU_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x00003000) +#define MX50_CTI0_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x00004000) +#define MX50_CTI1_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x00005000) +#define MX50_CTI2_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x00006000) +#define MX50_CTI3_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x00007000) +#define MX50_CORTEX_DBG_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x00008000) + +#define MX50_APBHDMA_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x01000000) +#define MX50_OCOTP_CTRL_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x01002000) +#define MX50_DIGCTL_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x01004000) +#define MX50_GPMI_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x01006000) +#define MX50_BCH_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x01008000) +#define MX50_ELCDIF_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x0100a000) +#define MX50_EPXP_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x0100c000) +#define MX50_DCP_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x0100e000) +#define MX50_EPDC_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x01010000) +#define MX50_QOSC_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x01012000) +#define MX50_PERFMON_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x01014000) +#define MX50_SSP_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x01016000) +#define MX50_ANATOP_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x01018000) +#define MX50_NIC_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x08000000) + +/* + * SPBA global module enabled #0 + */ +#define MX50_SPBA0_BASE_ADDR 0x50000000 +#define MX50_SPBA0_SIZE SZ_1M + +#define MX50_MMC_SDHC1_BASE_ADDR (MX50_SPBA0_BASE_ADDR + 0x00004000) +#define MX50_MMC_SDHC2_BASE_ADDR (MX50_SPBA0_BASE_ADDR + 0x00008000) +#define MX50_UART3_BASE_ADDR (MX50_SPBA0_BASE_ADDR + 0x0000c000) +#define MX50_CSPI1_BASE_ADDR (MX50_SPBA0_BASE_ADDR + 0x00010000) +#define MX50_SSI2_BASE_ADDR (MX50_SPBA0_BASE_ADDR + 0x00014000) +#define MX50_MMC_SDHC3_BASE_ADDR (MX50_SPBA0_BASE_ADDR + 0x00020000) +#define MX50_MMC_SDHC4_BASE_ADDR (MX50_SPBA0_BASE_ADDR + 0x00024000) + +/* + * AIPS 1 + */ +#define MX50_AIPS1_BASE_ADDR 0x53f00000 +#define MX50_AIPS1_SIZE SZ_1M + +#define MX50_OTG_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x00080000) +#define MX50_GPIO1_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x00084000) +#define MX50_GPIO2_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x00088000) +#define MX50_GPIO3_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x0008c000) +#define MX50_GPIO4_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x00090000) +#define MX50_KPP_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x00094000) +#define MX50_WDOG_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x00098000) +#define MX50_GPT1_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000a0000) +#define MX50_SRTC_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000a4000) +#define MX50_IOMUXC_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000a8000) +#define MX50_EPIT1_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000ac000) +#define MX50_PWM1_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000b4000) +#define MX50_PWM2_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000b8000) +#define MX50_UART1_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000bc000) +#define MX50_UART2_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000c0000) +#define MX50_SRC_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000d0000) +#define MX50_CCM_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000d4000) +#define MX50_GPC_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000d8000) +#define MX50_GPIO5_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000dc000) +#define MX50_GPIO6_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000e0000) +#define MX50_I2C3_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000ec000) +#define MX50_UART4_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000f0000) + +#define MX50_MSHC_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000f4000) +#define MX50_RNGB_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000f8000) + +/* + * AIPS 2 + */ +#define MX50_AIPS2_BASE_ADDR 0x63f00000 +#define MX50_AIPS2_SIZE SZ_1M + +#define MX50_PLL1_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x00080000) +#define MX50_PLL2_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x00084000) +#define MX50_PLL3_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x00088000) +#define MX50_UART5_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x00090000) +#define MX50_AHBMAX_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x00094000) +#define MX50_ARM_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000a0000) +#define MX50_OWIRE_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000a4000) +#define MX50_CSPI2_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000ac000) +#define MX50_SDMA_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000b0000) +#define MX50_ROMCP_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000b8000) +#define MX50_CSPI3_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000c0000) +#define MX50_I2C2_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000c4000) +#define MX50_I2C1_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000c8000) +#define MX50_SSI1_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000cc000) +#define MX50_AUDMUX_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000d0000) +#define MX50_WEIM_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000d8000) +#define MX50_FEC_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000ec000) + +/* + * Memory regions and CS + */ +#define MX50_CSD0_BASE_ADDR 0x70000000 +#define MX50_CSD1_BASE_ADDR 0xb0000000 +#define MX50_CS0_BASE_ADDR 0xf0000000 + +#define MX50_IO_P2V(x) IMX_IO_P2V(x) +#define MX50_IO_ADDRESS(x) IOMEM(MX50_IO_P2V(x)) + +/* + * defines for SPBA modules + */ +#define MX50_SPBA_SDHC1 0x04 +#define MX50_SPBA_SDHC2 0x08 +#define MX50_SPBA_UART3 0x0c +#define MX50_SPBA_CSPI1 0x10 +#define MX50_SPBA_SSI2 0x14 +#define MX50_SPBA_SDHC3 0x20 +#define MX50_SPBA_SDHC4 0x24 +#define MX50_SPBA_SPDIF 0x28 +#define MX50_SPBA_ATA 0x30 +#define MX50_SPBA_SLIM 0x34 +#define MX50_SPBA_HSI2C 0x38 +#define MX50_SPBA_CTRL 0x3c + +/* + * DMA request assignments + */ +#define MX50_DMA_REQ_GPC 1 +#define MX50_DMA_REQ_ATA_UART4_RX 2 +#define MX50_DMA_REQ_ATA_UART4_TX 3 +#define MX50_DMA_REQ_CSPI1_RX 6 +#define MX50_DMA_REQ_CSPI1_TX 7 +#define MX50_DMA_REQ_CSPI2_RX 8 +#define MX50_DMA_REQ_CSPI2_TX 9 +#define MX50_DMA_REQ_I2C3_SDHC3 10 +#define MX50_DMA_REQ_SDHC4 11 +#define MX50_DMA_REQ_UART2_FIRI_RX 12 +#define MX50_DMA_REQ_UART2_FIRI_TX 13 +#define MX50_DMA_REQ_EXT0 14 +#define MX50_DMA_REQ_EXT1 15 +#define MX50_DMA_REQ_UART5_RX 16 +#define MX50_DMA_REQ_UART5_TX 17 +#define MX50_DMA_REQ_UART1_RX 18 +#define MX50_DMA_REQ_UART1_TX 19 +#define MX50_DMA_REQ_I2C1_SDHC1 20 +#define MX50_DMA_REQ_I2C2_SDHC2 21 +#define MX50_DMA_REQ_SSI2_RX2 22 +#define MX50_DMA_REQ_SSI2_TX2 23 +#define MX50_DMA_REQ_SSI2_RX1 24 +#define MX50_DMA_REQ_SSI2_TX1 25 +#define MX50_DMA_REQ_SSI1_RX2 26 +#define MX50_DMA_REQ_SSI1_TX2 27 +#define MX50_DMA_REQ_SSI1_RX1 28 +#define MX50_DMA_REQ_SSI1_TX1 29 +#define MX50_DMA_REQ_CSPI_RX 38 +#define MX50_DMA_REQ_CSPI_TX 39 +#define MX50_DMA_REQ_UART3_RX 42 +#define MX50_DMA_REQ_UART3_TX 43 + +/* + * Interrupt numbers + */ +#define MX50_INT_MMC_SDHC1 1 +#define MX50_INT_MMC_SDHC2 2 +#define MX50_INT_MMC_SDHC3 3 +#define MX50_INT_MMC_SDHC4 4 +#define MX50_INT_DAP 5 +#define MX50_INT_SDMA 6 +#define MX50_INT_IOMUX 7 +#define MX50_INT_UART4 13 +#define MX50_INT_USB_H1 14 +#define MX50_INT_USB_OTG 18 +#define MX50_INT_DATABAHN 19 +#define MX50_INT_ELCDIF 20 +#define MX50_INT_EPXP 21 +#define MX50_INT_SRTC_NTZ 24 +#define MX50_INT_SRTC_TZ 25 +#define MX50_INT_EPDC 27 +#define MX50_INT_NIC 28 +#define MX50_INT_SSI1 29 +#define MX50_INT_SSI2 30 +#define MX50_INT_UART1 31 +#define MX50_INT_UART2 32 +#define MX50_INT_UART3 33 +#define MX50_INT_RESV34 34 +#define MX50_INT_RESV35 35 +#define MX50_INT_CSPI1 36 +#define MX50_INT_CSPI2 37 +#define MX50_INT_CSPI 38 +#define MX50_INT_GPT 39 +#define MX50_INT_EPIT1 40 +#define MX50_INT_GPIO1_INT7 42 +#define MX50_INT_GPIO1_INT6 43 +#define MX50_INT_GPIO1_INT5 44 +#define MX50_INT_GPIO1_INT4 45 +#define MX50_INT_GPIO1_INT3 46 +#define MX50_INT_GPIO1_INT2 47 +#define MX50_INT_GPIO1_INT1 48 +#define MX50_INT_GPIO1_INT0 49 +#define MX50_INT_GPIO1_LOW 50 +#define MX50_INT_GPIO1_HIGH 51 +#define MX50_INT_GPIO2_LOW 52 +#define MX50_INT_GPIO2_HIGH 53 +#define MX50_INT_GPIO3_LOW 54 +#define MX50_INT_GPIO3_HIGH 55 +#define MX50_INT_GPIO4_LOW 56 +#define MX50_INT_GPIO4_HIGH 57 +#define MX50_INT_WDOG1 58 +#define MX50_INT_KPP 60 +#define MX50_INT_PWM1 61 +#define MX50_INT_I2C1 62 +#define MX50_INT_I2C2 63 +#define MX50_INT_I2C3 64 +#define MX50_INT_RESV65 65 +#define MX50_INT_DCDC 66 +#define MX50_INT_THERMAL_ALARM 67 +#define MX50_INT_ANA3 68 +#define MX50_INT_ANA4 69 +#define MX50_INT_CCM1 71 +#define MX50_INT_CCM2 72 +#define MX50_INT_GPC1 73 +#define MX50_INT_GPC2 74 +#define MX50_INT_SRC 75 +#define MX50_INT_NM 76 +#define MX50_INT_PMU 77 +#define MX50_INT_CTI_IRQ 78 +#define MX50_INT_CTI1_TG0 79 +#define MX50_INT_CTI1_TG1 80 +#define MX50_INT_GPU2_IRQ 84 +#define MX50_INT_GPU2_BUSY 85 +#define MX50_INT_UART5 86 +#define MX50_INT_FEC 87 +#define MX50_INT_OWIRE 88 +#define MX50_INT_CTI1_TG2 89 +#define MX50_INT_SJC 90 +#define MX50_INT_DCP_CHAN1_3 91 +#define MX50_INT_DCP_CHAN0 92 +#define MX50_INT_PWM2 94 +#define MX50_INT_RNGB 97 +#define MX50_INT_CTI1_TG3 98 +#define MX50_INT_RAWNAND_BCH 100 +#define MX50_INT_RAWNAND_GPMI 102 +#define MX50_INT_GPIO5_LOW 103 +#define MX50_INT_GPIO5_HIGH 104 +#define MX50_INT_GPIO6_LOW 105 +#define MX50_INT_GPIO6_HIGH 106 +#define MX50_INT_MSHC 109 +#define MX50_INT_APBHDMA_CHAN0 110 +#define MX50_INT_APBHDMA_CHAN1 111 +#define MX50_INT_APBHDMA_CHAN2 112 +#define MX50_INT_APBHDMA_CHAN3 113 +#define MX50_INT_APBHDMA_CHAN4 114 +#define MX50_INT_APBHDMA_CHAN5 115 +#define MX50_INT_APBHDMA_CHAN6 116 +#define MX50_INT_APBHDMA_CHAN7 117 + +#endif /* ifndef __MACH_MX50_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/mxc.h b/arch/arm/plat-mxc/include/mach/mxc.h index eca8f83..04c7a26 100644 --- a/arch/arm/plat-mxc/include/mach/mxc.h +++ b/arch/arm/plat-mxc/include/mach/mxc.h @@ -32,6 +32,7 @@ #define MXC_CPU_MX27 27 #define MXC_CPU_MX31 31 #define MXC_CPU_MX35 35 +#define MXC_CPU_MX50 50 #define MXC_CPU_MX51 51 #define MXC_CPU_MX53 53 #define MXC_CPU_MXC91231 91231 @@ -126,6 +127,18 @@ extern unsigned int __mxc_cpu_type; # define cpu_is_mx35() (0) #endif +#ifdef CONFIG_ARCH_MX50 +# ifdef mxc_cpu_type +# undef mxc_cpu_type +# define mxc_cpu_type __mxc_cpu_type +# else +# define mxc_cpu_type MXC_CPU_MX50 +# endif +# define cpu_is_mx50() (mxc_cpu_type == MXC_CPU_MX50) +#else +# define cpu_is_mx50() (0) +#endif + #ifdef CONFIG_ARCH_MX51 # ifdef mxc_cpu_type # undef mxc_cpu_type -- cgit v1.1 From d3d4b60b12369eded0ea0c5dffee0888ec4d80cd Mon Sep 17 00:00:00 2001 From: Richard Zhao Date: Thu, 30 Dec 2010 19:25:06 +0800 Subject: arm: mx50: add mx50 reference design board support Add basic function and uart device support. Signed-off-by: Richard Zhao Signed-off-by: Sascha Hauer --- arch/arm/plat-mxc/include/mach/uncompress.h | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/arm/plat-mxc') diff --git a/arch/arm/plat-mxc/include/mach/uncompress.h b/arch/arm/plat-mxc/include/mach/uncompress.h index 9dd9c20..5ccf3ef 100644 --- a/arch/arm/plat-mxc/include/mach/uncompress.h +++ b/arch/arm/plat-mxc/include/mach/uncompress.h @@ -63,6 +63,7 @@ static inline void flush(void) #define MX3X_UART1_BASE_ADDR 0x43F90000 #define MX3X_UART2_BASE_ADDR 0x43F94000 #define MX51_UART1_BASE_ADDR 0x73fbc000 +#define MX50_UART1_BASE_ADDR 0x53fbc000 static __inline__ void __arch_decomp_setup(unsigned long arch_id) { @@ -102,6 +103,9 @@ static __inline__ void __arch_decomp_setup(unsigned long arch_id) case MACH_TYPE_EUKREA_CPUIMX51SD: uart_base = MX51_UART1_BASE_ADDR; break; + case MACH_TYPE_MX50_RDP: + uart_base = MX50_UART1_BASE_ADDR; + break; default: break; } -- cgit v1.1 From 08406f540c7ce4cfed96fb240906eee04b9e3eb7 Mon Sep 17 00:00:00 2001 From: "Arnaud Patard (Rtp)" Date: Mon, 20 Dec 2010 16:48:56 +0100 Subject: arch/arm/plat-mxc/ehci.c: fix errors/typos This patch is fixing some issues : - MXC_OTG_UCTRL_OPM_BIT is for USBCTRL register and not PHYCTRL register. - the MXC_EHCI_WAKEUP_ENABLED check was only clearing the bits so never allows to set them. Signed-off-by: Arnaud Patard Signed-off-by: Sascha Hauer --- arch/arm/plat-mxc/ehci.c | 26 ++++++++++++++++++-------- 1 file changed, 18 insertions(+), 8 deletions(-) (limited to 'arch/arm/plat-mxc') diff --git a/arch/arm/plat-mxc/ehci.c b/arch/arm/plat-mxc/ehci.c index d59f5fe..a456603 100644 --- a/arch/arm/plat-mxc/ehci.c +++ b/arch/arm/plat-mxc/ehci.c @@ -278,10 +278,13 @@ int mxc_initialize_usb_hw(int port, unsigned int flags) if (flags & MXC_EHCI_INTERNAL_PHY) { v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET); - if (flags & MXC_EHCI_POWER_PINS_ENABLED) - v |= (MXC_OTG_PHYCTRL_OC_DIS_BIT | MXC_OTG_UCTRL_OPM_BIT); /* OC/USBPWR is not used */ - else - v &= ~(MXC_OTG_PHYCTRL_OC_DIS_BIT | MXC_OTG_UCTRL_OPM_BIT); /* OC/USBPWR is used */ + if (flags & MXC_EHCI_POWER_PINS_ENABLED) { + /* OC/USBPWR is not used */ + v |= MXC_OTG_PHYCTRL_OC_DIS_BIT; + } else { + /* OC/USBPWR is used */ + v &= ~MXC_OTG_PHYCTRL_OC_DIS_BIT; + } __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET); v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET); @@ -289,16 +292,23 @@ int mxc_initialize_usb_hw(int port, unsigned int flags) v |= MXC_OTG_UCTRL_OWIE_BIT;/* OTG wakeup enable */ else v &= ~MXC_OTG_UCTRL_OWIE_BIT;/* OTG wakeup disable */ + if (flags & MXC_EHCI_POWER_PINS_ENABLED) + v |= MXC_OTG_UCTRL_OPM_BIT; + else + v &= ~MXC_OTG_UCTRL_OPM_BIT; __raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET); } break; case 1: /* Host 1 */ /*Host ULPI */ v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET); - if (flags & MXC_EHCI_WAKEUP_ENABLED) - v &= ~(MXC_H1_UCTRL_H1WIE_BIT | MXC_H1_UCTRL_H1UIE_BIT);/* HOST1 wakeup/ULPI intr disable */ - else - v &= ~(MXC_H1_UCTRL_H1WIE_BIT | MXC_H1_UCTRL_H1UIE_BIT);/* HOST1 wakeup/ULPI intr disable */ + if (flags & MXC_EHCI_WAKEUP_ENABLED) { + /* HOST1 wakeup/ULPI intr enable */ + v |= (MXC_H1_UCTRL_H1WIE_BIT | MXC_H1_UCTRL_H1UIE_BIT); + } else { + /* HOST1 wakeup/ULPI intr disable */ + v &= ~(MXC_H1_UCTRL_H1WIE_BIT | MXC_H1_UCTRL_H1UIE_BIT); + } if (flags & MXC_EHCI_POWER_PINS_ENABLED) v &= ~MXC_H1_UCTRL_H1PM_BIT; /* HOST1 power mask used*/ -- cgit v1.1 From 8305ed75d1418f02933a48bcabdbb5032d885628 Mon Sep 17 00:00:00 2001 From: "Arnaud Patard (Rtp)" Date: Mon, 20 Dec 2010 16:48:57 +0100 Subject: MX51: Add support for usb host 2 Signed-off-by: Arnaud Patard Signed-off-by: Sascha Hauer --- arch/arm/plat-mxc/ehci.c | 25 +++++++++++++++++++++++++ arch/arm/plat-mxc/include/mach/mxc_ehci.h | 1 + 2 files changed, 26 insertions(+) (limited to 'arch/arm/plat-mxc') diff --git a/arch/arm/plat-mxc/ehci.c b/arch/arm/plat-mxc/ehci.c index a456603..8772ce3 100644 --- a/arch/arm/plat-mxc/ehci.c +++ b/arch/arm/plat-mxc/ehci.c @@ -49,6 +49,7 @@ #define MXC_OTG_OFFSET 0 #define MXC_H1_OFFSET 0x200 +#define MXC_H2_OFFSET 0x400 /* USB_CTRL */ #define MXC_OTG_UCTRL_OWIE_BIT (1 << 27) /* OTG wakeup intr enable */ @@ -61,6 +62,11 @@ #define MXC_OTG_PHYCTRL_OC_DIS_BIT (1 << 8) /* OTG Disable Overcurrent Event */ #define MXC_H1_OC_DIS_BIT (1 << 5) /* UH1 Disable Overcurrent Event */ +/* USBH2CTRL */ +#define MXC_H2_UCTRL_H2UIE_BIT (1 << 8) +#define MXC_H2_UCTRL_H2WIE_BIT (1 << 7) +#define MXC_H2_UCTRL_H2PM_BIT (1 << 4) + #define MXC_USBCMD_OFFSET 0x140 /* USBCMD */ @@ -266,6 +272,9 @@ int mxc_initialize_usb_hw(int port, unsigned int flags) case 1: /* Host 1 port */ usbotg_base = usb_base + MXC_H1_OFFSET; break; + case 2: /* Host 2 port */ + usbotg_base = usb_base + MXC_H2_OFFSET; + break; default: printk(KERN_ERR"%s no such port %d\n", __func__, port); ret = -ENOENT; @@ -329,6 +338,22 @@ int mxc_initialize_usb_hw(int port, unsigned int flags) v &= MXC_UCMD_ITC_NO_THRESHOLD_MASK; __raw_writel(v, usbotg_base + MXC_USBCMD_OFFSET); break; + case 2: /* Host 2 ULPI */ + v = __raw_readl(usbother_base + MXC_USBH2CTRL_OFFSET); + if (flags & MXC_EHCI_WAKEUP_ENABLED) { + /* HOST1 wakeup/ULPI intr enable */ + v |= (MXC_H2_UCTRL_H2WIE_BIT | MXC_H2_UCTRL_H2UIE_BIT); + } else { + /* HOST1 wakeup/ULPI intr disable */ + v &= ~(MXC_H2_UCTRL_H2WIE_BIT | MXC_H2_UCTRL_H2UIE_BIT); + } + + if (flags & MXC_EHCI_POWER_PINS_ENABLED) + v &= ~MXC_H2_UCTRL_H2PM_BIT; /* HOST2 power mask used*/ + else + v |= MXC_H2_UCTRL_H2PM_BIT; /* HOST2 power mask used*/ + __raw_writel(v, usbother_base + MXC_USBH2CTRL_OFFSET); + break; } error: diff --git a/arch/arm/plat-mxc/include/mach/mxc_ehci.h b/arch/arm/plat-mxc/include/mach/mxc_ehci.h index 7fc5f99..a523a40 100644 --- a/arch/arm/plat-mxc/include/mach/mxc_ehci.h +++ b/arch/arm/plat-mxc/include/mach/mxc_ehci.h @@ -31,6 +31,7 @@ #define MXC_USBCTRL_OFFSET 0 #define MXC_USB_PHY_CTR_FUNC_OFFSET 0x8 #define MXC_USB_PHY_CTR_FUNC2_OFFSET 0xc +#define MXC_USBH2CTRL_OFFSET 0x14 #define MX5_USBOTHER_REGS_OFFSET 0x800 -- cgit v1.1 From 96de6d447f40612acb93f81a561a834177cca685 Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Mon, 6 Dec 2010 11:37:30 +0100 Subject: ARM i.MX51: rename IPU irqs Signed-off-by: Sascha Hauer --- arch/arm/plat-mxc/include/mach/mx51.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm/plat-mxc') diff --git a/arch/arm/plat-mxc/include/mach/mx51.h b/arch/arm/plat-mxc/include/mach/mx51.h index fa3a2a5..873807f 100644 --- a/arch/arm/plat-mxc/include/mach/mx51.h +++ b/arch/arm/plat-mxc/include/mach/mx51.h @@ -251,8 +251,8 @@ #define MX51_MXC_INT_IOMUX 7 #define MX51_INT_NFC 8 #define MX51_MXC_INT_VPU 9 -#define MX51_MXC_INT_IPU_ERR 10 -#define MX51_MXC_INT_IPU_SYN 11 +#define MX51_INT_IPU_ERR 10 +#define MX51_INT_IPU_SYN 11 #define MX51_MXC_INT_GPU 12 #define MX51_MXC_INT_RESV13 13 #define MX51_MXC_INT_USB_H1 14 -- cgit v1.1 From a58154d1c3535f451a409abbd0bda6770b2d9380 Mon Sep 17 00:00:00 2001 From: Yong Shen Date: Tue, 4 Jan 2011 14:22:56 +0800 Subject: ARM i.MX53: Make MX53 EVK bootable 1. Add entries to Kconfig 2. Add machine definition 3. Add Uart platform data, pad setting and base address 4. Adjust GPIO irq number Signed-off-by: Yong Shen Signed-off-by: Sascha Hauer --- arch/arm/plat-mxc/devices/platform-imx-uart.c | 10 ++++++++++ arch/arm/plat-mxc/include/mach/iomux-mx53.h | 20 ++++++++++++++++++++ arch/arm/plat-mxc/include/mach/irqs.h | 4 +++- arch/arm/plat-mxc/include/mach/uncompress.h | 4 ++++ 4 files changed, 37 insertions(+), 1 deletion(-) (limited to 'arch/arm/plat-mxc') diff --git a/arch/arm/plat-mxc/devices/platform-imx-uart.c b/arch/arm/plat-mxc/devices/platform-imx-uart.c index 0c69fbc..3c854c2 100644 --- a/arch/arm/plat-mxc/devices/platform-imx-uart.c +++ b/arch/arm/plat-mxc/devices/platform-imx-uart.c @@ -116,6 +116,16 @@ const struct imx_imx_uart_1irq_data imx51_imx_uart_data[] __initconst = { }; #endif /* ifdef CONFIG_SOC_IMX51 */ +#ifdef CONFIG_SOC_IMX53 +const struct imx_imx_uart_1irq_data imx53_imx_uart_data[] __initconst = { +#define imx53_imx_uart_data_entry(_id, _hwid) \ + imx_imx_uart_1irq_data_entry(MX53, _id, _hwid, SZ_4K) + imx53_imx_uart_data_entry(0, 1), + imx53_imx_uart_data_entry(1, 2), + imx53_imx_uart_data_entry(2, 3), +}; +#endif /* ifdef CONFIG_SOC_IMX53 */ + struct platform_device *__init imx_add_imx_uart_3irq( const struct imx_imx_uart_3irq_data *data, const struct imxuart_platform_data *pdata) diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx53.h b/arch/arm/plat-mxc/include/mach/iomux-mx53.h index 80cb3c5..5deee01 100644 --- a/arch/arm/plat-mxc/include/mach/iomux-mx53.h +++ b/arch/arm/plat-mxc/include/mach/iomux-mx53.h @@ -42,6 +42,26 @@ typedef enum iomux_config { #define NON_MUX_I 0x00 #define NON_PAD_I 0x00 +#define MX53_UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST | PAD_CTL_HYS) +/* UART1 */ +#define MX53_PAD_CSI0_D10__UART1_TXD IOMUX_PAD(0x414, 0xE8, 2, 0x0, 0, MX53_UART_PAD_CTRL) +#define MX53_PAD_CSI0_D11__UART1_RXD IOMUX_PAD(0x418, 0xEC, 2, 0x878, 1, MX53_UART_PAD_CTRL) +#define MX53_PAD_ATA_DIOW__UART1_TXD IOMUX_PAD(0x5F0, 0x270, 3, 0x0, 0, MX53_UART_PAD_CTRL) +#define MX53_PAD_ATA_DMACK__UART1_RXD IOMUX_PAD(0x5F4, 0x274, 3, 0x880, 3, MX53_UART_PAD_CTRL) + +/* UART2 */ +#define MX53_PAD_ATA_BUFFER_EN__UART2_RXD IOMUX_PAD(0x5FC, 0x27C, 3, 0x880, 3, MX53_UART_PAD_CTRL) +#define MX53_PAD_ATA_DMARQ__UART2_TXD IOMUX_PAD(0x5F8, 0x278, 3, 0x0, 0, MX53_UART_PAD_CTRL) +#define MX53_PAD_ATA_DIOR__UART2_RTS IOMUX_PAD(0x604, 0x284, 3, 0x87C, 3, MX53_UART_PAD_CTRL) +#define MX53_PAD_ATA_INTRQ__UART2_CTS IOMUX_PAD(0x600, 0x280, 3, 0x0, 0, MX53_UART_PAD_CTRL) + +/* UART3 */ +#define MX53_PAD_ATA_CS_0__UART3_TXD IOMUX_PAD(0x61C, 0x29C, 4, 0x0, 0, MX53_UART_PAD_CTRL) +#define MX53_PAD_ATA_CS_1__UART3_RXD IOMUX_PAD(0x620, 0x2A0, 4, 0x888, 3, MX53_UART_PAD_CTRL) +#define MX53_PAD_ATA_DA_1__UART3_CTS IOMUX_PAD(0x614, 0x294, 4, 0x0, 0, MX53_UART_PAD_CTRL) +#define MX53_PAD_ATA_DA_2__UART3_RTS IOMUX_PAD(0x618, 0x298, 4, 0x884, 5, MX53_UART_PAD_CTRL) + #define MX53_PAD_GPIO_19__GPIO_4_5 IOMUX_PAD(0x348, 0x20,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) #define MX53_PAD_KEY_COL0__GPIO_4_6 IOMUX_PAD(0x34C, 0x24,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) #define MX53_PAD_KEY_ROW0__GPIO_4_7 IOMUX_PAD(0x350, 0x28,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) diff --git a/arch/arm/plat-mxc/include/mach/irqs.h b/arch/arm/plat-mxc/include/mach/irqs.h index 064026b..58a49cc 100644 --- a/arch/arm/plat-mxc/include/mach/irqs.h +++ b/arch/arm/plat-mxc/include/mach/irqs.h @@ -23,7 +23,9 @@ #define MXC_GPIO_IRQ_START MXC_INTERNAL_IRQS /* these are ordered by size to support multi-SoC kernels */ -#if defined CONFIG_ARCH_MX2 +#if defined CONFIG_ARCH_MX53 +#define MXC_GPIO_IRQS (32 * 7) +#elif defined CONFIG_ARCH_MX2 #define MXC_GPIO_IRQS (32 * 6) #elif defined CONFIG_ARCH_MX50 #define MXC_GPIO_IRQS (32 * 6) diff --git a/arch/arm/plat-mxc/include/mach/uncompress.h b/arch/arm/plat-mxc/include/mach/uncompress.h index 5ccf3ef..3a70ebf 100644 --- a/arch/arm/plat-mxc/include/mach/uncompress.h +++ b/arch/arm/plat-mxc/include/mach/uncompress.h @@ -64,6 +64,7 @@ static inline void flush(void) #define MX3X_UART2_BASE_ADDR 0x43F94000 #define MX51_UART1_BASE_ADDR 0x73fbc000 #define MX50_UART1_BASE_ADDR 0x53fbc000 +#define MX53_UART1_BASE_ADDR 0x53fbc000 static __inline__ void __arch_decomp_setup(unsigned long arch_id) { @@ -106,6 +107,9 @@ static __inline__ void __arch_decomp_setup(unsigned long arch_id) case MACH_TYPE_MX50_RDP: uart_base = MX50_UART1_BASE_ADDR; break; + case MACH_TYPE_MX53_EVK: + uart_base = MX53_UART1_BASE_ADDR; + break; default: break; } -- cgit v1.1