From 19a0519d3642d140bfb1bd602a34dc4f98606b19 Mon Sep 17 00:00:00 2001 From: Ezequiel Garcia Date: Fri, 16 Aug 2013 10:28:24 +0100 Subject: ARM: 7818/1: feroceon: Add suspend/resume operation Add support for suspend/resume operations. The implemented procedures are identical to the ones for ARM926. Signed-off-by: Ezequiel Garcia Signed-off-by: Russell King --- arch/arm/mm/proc-feroceon.S | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) (limited to 'arch/arm/mm/proc-feroceon.S') diff --git a/arch/arm/mm/proc-feroceon.S b/arch/arm/mm/proc-feroceon.S index d5146b9..db79b62 100644 --- a/arch/arm/mm/proc-feroceon.S +++ b/arch/arm/mm/proc-feroceon.S @@ -514,6 +514,32 @@ ENTRY(cpu_feroceon_set_pte_ext) #endif mov pc, lr +/* Suspend/resume support: taken from arch/arm/mm/proc-arm926.S */ +.globl cpu_feroceon_suspend_size +.equ cpu_feroceon_suspend_size, 4 * 3 +#ifdef CONFIG_ARM_CPU_SUSPEND +ENTRY(cpu_feroceon_do_suspend) + stmfd sp!, {r4 - r6, lr} + mrc p15, 0, r4, c13, c0, 0 @ PID + mrc p15, 0, r5, c3, c0, 0 @ Domain ID + mrc p15, 0, r6, c1, c0, 0 @ Control register + stmia r0, {r4 - r6} + ldmfd sp!, {r4 - r6, pc} +ENDPROC(cpu_feroceon_do_suspend) + +ENTRY(cpu_feroceon_do_resume) + mov ip, #0 + mcr p15, 0, ip, c8, c7, 0 @ invalidate I+D TLBs + mcr p15, 0, ip, c7, c7, 0 @ invalidate I+D caches + ldmia r0, {r4 - r6} + mcr p15, 0, r4, c13, c0, 0 @ PID + mcr p15, 0, r5, c3, c0, 0 @ Domain ID + mcr p15, 0, r1, c2, c0, 0 @ TTB address + mov r0, r6 @ control register + b cpu_resume_mmu +ENDPROC(cpu_feroceon_do_resume) +#endif + .type __feroceon_setup, #function __feroceon_setup: mov r0, #0 -- cgit v1.1