From 732078c369f0b6ad9fe75c1faff721e91260bc5d Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 20 Mar 2013 11:11:43 +0100 Subject: arm: zynq: Load scu baseaddress at run time Use Cortex a9 cp15 to read scu baseaddress. Signed-off-by: Michal Simek --- arch/arm/mach-zynq/common.c | 34 ++++++++++++++++++++++------------ arch/arm/mach-zynq/common.h | 2 ++ 2 files changed, 24 insertions(+), 12 deletions(-) (limited to 'arch/arm/mach-zynq') diff --git a/arch/arm/mach-zynq/common.c b/arch/arm/mach-zynq/common.c index 68e0907..f9e5f3a 100644 --- a/arch/arm/mach-zynq/common.c +++ b/arch/arm/mach-zynq/common.c @@ -33,10 +33,13 @@ #include #include #include +#include #include #include "common.h" +void __iomem *zynq_scu_base; + static struct of_device_id zynq_of_bus_ids[] __initdata = { { .compatible = "simple-bus", }, {} @@ -56,17 +59,6 @@ static void __init xilinx_init_machine(void) of_platform_bus_probe(NULL, zynq_of_bus_ids, NULL); } -#define SCU_PERIPH_PHYS 0xF8F00000 -#define SCU_PERIPH_SIZE SZ_8K -#define SCU_PERIPH_VIRT (VMALLOC_END - SCU_PERIPH_SIZE) - -static struct map_desc scu_desc __initdata = { - .virtual = SCU_PERIPH_VIRT, - .pfn = __phys_to_pfn(SCU_PERIPH_PHYS), - .length = SCU_PERIPH_SIZE, - .type = MT_DEVICE, -}; - static void __init xilinx_zynq_timer_init(void) { struct device_node *np; @@ -81,13 +73,31 @@ static void __init xilinx_zynq_timer_init(void) clocksource_of_init(); } +static struct map_desc zynq_cortex_a9_scu_map __initdata = { + .length = SZ_256, + .type = MT_DEVICE, +}; + +static void __init zynq_scu_map_io(void) +{ + unsigned long base; + + base = scu_a9_get_base(); + zynq_cortex_a9_scu_map.pfn = __phys_to_pfn(base); + /* Expected address is in vmalloc area that's why simple assign here */ + zynq_cortex_a9_scu_map.virtual = base; + iotable_init(&zynq_cortex_a9_scu_map, 1); + zynq_scu_base = (void __iomem *)base; + BUG_ON(!zynq_scu_base); +} + /** * xilinx_map_io() - Create memory mappings needed for early I/O. */ static void __init xilinx_map_io(void) { debug_ll_io_init(); - iotable_init(&scu_desc, 1); + zynq_scu_map_io(); } static const char *xilinx_dt_match[] = { diff --git a/arch/arm/mach-zynq/common.h b/arch/arm/mach-zynq/common.h index 5050bb1..d7164d5 100644 --- a/arch/arm/mach-zynq/common.h +++ b/arch/arm/mach-zynq/common.h @@ -17,4 +17,6 @@ #ifndef __MACH_ZYNQ_COMMON_H__ #define __MACH_ZYNQ_COMMON_H__ +extern void __iomem *zynq_scu_base; + #endif -- cgit v1.1 From 64b889b39e9958fdcfe5e9b7aa1ac0ffca3fc9a2 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 27 Mar 2013 12:37:53 +0100 Subject: arm: zynq: Move slcr initialization to separate file Create separate slcr driver instead of polluting common code. Signed-off-by: Michal Simek --- arch/arm/mach-zynq/Makefile | 2 +- arch/arm/mach-zynq/common.c | 10 +------ arch/arm/mach-zynq/common.h | 3 ++ arch/arm/mach-zynq/slcr.c | 69 +++++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 74 insertions(+), 10 deletions(-) create mode 100644 arch/arm/mach-zynq/slcr.c (limited to 'arch/arm/mach-zynq') diff --git a/arch/arm/mach-zynq/Makefile b/arch/arm/mach-zynq/Makefile index 320faed..13ee09b 100644 --- a/arch/arm/mach-zynq/Makefile +++ b/arch/arm/mach-zynq/Makefile @@ -3,4 +3,4 @@ # # Common support -obj-y := common.o +obj-y := common.o slcr.o diff --git a/arch/arm/mach-zynq/common.c b/arch/arm/mach-zynq/common.c index f9e5f3a..cd3968c 100644 --- a/arch/arm/mach-zynq/common.c +++ b/arch/arm/mach-zynq/common.c @@ -61,15 +61,7 @@ static void __init xilinx_init_machine(void) static void __init xilinx_zynq_timer_init(void) { - struct device_node *np; - void __iomem *slcr; - - np = of_find_compatible_node(NULL, NULL, "xlnx,zynq-slcr"); - slcr = of_iomap(np, 0); - WARN_ON(!slcr); - - xilinx_zynq_clocks_init(slcr); - + zynq_slcr_init(); clocksource_of_init(); } diff --git a/arch/arm/mach-zynq/common.h b/arch/arm/mach-zynq/common.h index d7164d5..dd594e6 100644 --- a/arch/arm/mach-zynq/common.h +++ b/arch/arm/mach-zynq/common.h @@ -17,6 +17,9 @@ #ifndef __MACH_ZYNQ_COMMON_H__ #define __MACH_ZYNQ_COMMON_H__ +extern int zynq_slcr_init(void); + +extern void __iomem *zynq_slcr_base; extern void __iomem *zynq_scu_base; #endif diff --git a/arch/arm/mach-zynq/slcr.c b/arch/arm/mach-zynq/slcr.c new file mode 100644 index 0000000..f9f3349 --- /dev/null +++ b/arch/arm/mach-zynq/slcr.c @@ -0,0 +1,69 @@ +/* + * Xilinx SLCR driver + * + * Copyright (c) 2011-2013 Xilinx Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + * + * You should have received a copy of the GNU General Public + * License along with this program; if not, write to the Free + * Software Foundation, Inc., 675 Mass Ave, Cambridge, MA + * 02139, USA. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "common.h" + +#define SLCR_UNLOCK_MAGIC 0xDF0D +#define SLCR_UNLOCK 0x8 /* SCLR unlock register */ + +void __iomem *zynq_slcr_base; + +/** + * zynq_slcr_init + * Returns 0 on success, negative errno otherwise. + * + * Called early during boot from platform code to remap SLCR area. + */ +int __init zynq_slcr_init(void) +{ + struct device_node *np; + + np = of_find_compatible_node(NULL, NULL, "xlnx,zynq-slcr"); + if (!np) { + pr_err("%s: no slcr node found\n", __func__); + BUG(); + } + + zynq_slcr_base = of_iomap(np, 0); + if (!zynq_slcr_base) { + pr_err("%s: Unable to map I/O memory\n", __func__); + BUG(); + } + + /* unlock the SLCR so that registers can be changed */ + writel(SLCR_UNLOCK_MAGIC, zynq_slcr_base + SLCR_UNLOCK); + + pr_info("%s mapped to %p\n", np->name, zynq_slcr_base); + + xilinx_zynq_clocks_init(zynq_slcr_base); + + of_node_put(np); + + return 0; +} -- cgit v1.1 From 96790f0a283976bc59f68657237293fe97b02334 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 20 Mar 2013 11:42:15 +0100 Subject: arm: zynq: Add support for system reset Do system reset via slcr registers. Signed-off-by: Michal Simek --- arch/arm/mach-zynq/common.c | 6 ++++++ arch/arm/mach-zynq/common.h | 1 + arch/arm/mach-zynq/slcr.c | 27 +++++++++++++++++++++++++++ 3 files changed, 34 insertions(+) (limited to 'arch/arm/mach-zynq') diff --git a/arch/arm/mach-zynq/common.c b/arch/arm/mach-zynq/common.c index cd3968c..f0a8533 100644 --- a/arch/arm/mach-zynq/common.c +++ b/arch/arm/mach-zynq/common.c @@ -92,6 +92,11 @@ static void __init xilinx_map_io(void) zynq_scu_map_io(); } +static void zynq_system_reset(char mode, const char *cmd) +{ + zynq_slcr_system_reset(); +} + static const char *xilinx_dt_match[] = { "xlnx,zynq-zc702", "xlnx,zynq-7000", @@ -104,4 +109,5 @@ MACHINE_START(XILINX_EP107, "Xilinx Zynq Platform") .init_machine = xilinx_init_machine, .init_time = xilinx_zynq_timer_init, .dt_compat = xilinx_dt_match, + .restart = zynq_system_reset, MACHINE_END diff --git a/arch/arm/mach-zynq/common.h b/arch/arm/mach-zynq/common.h index dd594e6..d7ec3ca 100644 --- a/arch/arm/mach-zynq/common.h +++ b/arch/arm/mach-zynq/common.h @@ -18,6 +18,7 @@ #define __MACH_ZYNQ_COMMON_H__ extern int zynq_slcr_init(void); +extern void zynq_slcr_system_reset(void); extern void __iomem *zynq_slcr_base; extern void __iomem *zynq_scu_base; diff --git a/arch/arm/mach-zynq/slcr.c b/arch/arm/mach-zynq/slcr.c index f9f3349..d58c996 100644 --- a/arch/arm/mach-zynq/slcr.c +++ b/arch/arm/mach-zynq/slcr.c @@ -32,9 +32,36 @@ #define SLCR_UNLOCK_MAGIC 0xDF0D #define SLCR_UNLOCK 0x8 /* SCLR unlock register */ +#define SLCR_PS_RST_CTRL_OFFSET 0x200 /* PS Software Reset Control */ +#define SLCR_REBOOT_STATUS 0x258 /* PS Reboot Status */ + void __iomem *zynq_slcr_base; /** + * zynq_slcr_system_reset - Reset the entire system. + */ +void zynq_slcr_system_reset(void) +{ + u32 reboot; + + /* + * Unlock the SLCR then reset the system. + * Note that this seems to require raw i/o + * functions or there's a lockup? + */ + writel(SLCR_UNLOCK_MAGIC, zynq_slcr_base + SLCR_UNLOCK); + + /* + * Clear 0x0F000000 bits of reboot status register to workaround + * the FSBL not loading the bitstream after soft-reboot + * This is a temporary solution until we know more. + */ + reboot = readl(zynq_slcr_base + SLCR_REBOOT_STATUS); + writel(reboot & 0xF0FFFFFF, zynq_slcr_base + SLCR_REBOOT_STATUS); + writel(1, zynq_slcr_base + SLCR_PS_RST_CTRL_OFFSET); +} + +/** * zynq_slcr_init * Returns 0 on success, negative errno otherwise. * -- cgit v1.1 From 889faa88142801ee6bec2de2b8fb4c606076d52f Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 27 Mar 2013 13:07:00 +0100 Subject: arm: zynq: Get rid of xilinx function prefix Xilinx is vendor name not SoC name. Use zynq instead. Also remove one checkpatch warning: WARNING: static const char * array should probably be static const char * const +static const char *xilinx_dt_match[] = { Signed-off-by: Michal Simek --- arch/arm/mach-zynq/common.c | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) (limited to 'arch/arm/mach-zynq') diff --git a/arch/arm/mach-zynq/common.c b/arch/arm/mach-zynq/common.c index f0a8533..e1b6131 100644 --- a/arch/arm/mach-zynq/common.c +++ b/arch/arm/mach-zynq/common.c @@ -46,10 +46,10 @@ static struct of_device_id zynq_of_bus_ids[] __initdata = { }; /** - * xilinx_init_machine() - System specific initialization, intended to be - * called from board specific initialization. + * zynq_init_machine - System specific initialization, intended to be + * called from board specific initialization. */ -static void __init xilinx_init_machine(void) +static void __init zynq_init_machine(void) { /* * 64KB way size, 8-way associativity, parity disabled @@ -59,7 +59,7 @@ static void __init xilinx_init_machine(void) of_platform_bus_probe(NULL, zynq_of_bus_ids, NULL); } -static void __init xilinx_zynq_timer_init(void) +static void __init zynq_timer_init(void) { zynq_slcr_init(); clocksource_of_init(); @@ -84,9 +84,9 @@ static void __init zynq_scu_map_io(void) } /** - * xilinx_map_io() - Create memory mappings needed for early I/O. + * zynq_map_io - Create memory mappings needed for early I/O. */ -static void __init xilinx_map_io(void) +static void __init zynq_map_io(void) { debug_ll_io_init(); zynq_scu_map_io(); @@ -97,17 +97,17 @@ static void zynq_system_reset(char mode, const char *cmd) zynq_slcr_system_reset(); } -static const char *xilinx_dt_match[] = { +static const char * const zynq_dt_match[] = { "xlnx,zynq-zc702", "xlnx,zynq-7000", NULL }; MACHINE_START(XILINX_EP107, "Xilinx Zynq Platform") - .map_io = xilinx_map_io, + .map_io = zynq_map_io, .init_irq = irqchip_init, - .init_machine = xilinx_init_machine, - .init_time = xilinx_zynq_timer_init, - .dt_compat = xilinx_dt_match, + .init_machine = zynq_init_machine, + .init_time = zynq_timer_init, + .dt_compat = zynq_dt_match, .restart = zynq_system_reset, MACHINE_END -- cgit v1.1 From aa7eb2bb4e4a22e41bbe4612ff46e5885b13c33e Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 20 Mar 2013 13:50:12 +0100 Subject: arm: zynq: Add smp support Zynq is dual core Cortex A9 which starts always at zero. Using simple trampoline ensure long jump to secondary_startup code. Signed-off-by: Michal Simek Signed-off-by: Steffen Trumtrar --- arch/arm/mach-zynq/Kconfig | 1 + arch/arm/mach-zynq/Makefile | 1 + arch/arm/mach-zynq/common.c | 1 + arch/arm/mach-zynq/common.h | 11 ++++ arch/arm/mach-zynq/headsmp.S | 24 +++++++ arch/arm/mach-zynq/platsmp.c | 149 +++++++++++++++++++++++++++++++++++++++++++ arch/arm/mach-zynq/slcr.c | 29 +++++++++ 7 files changed, 216 insertions(+) create mode 100644 arch/arm/mach-zynq/headsmp.S create mode 100644 arch/arm/mach-zynq/platsmp.c (limited to 'arch/arm/mach-zynq') diff --git a/arch/arm/mach-zynq/Kconfig b/arch/arm/mach-zynq/Kconfig index d70651e..f4a7e63 100644 --- a/arch/arm/mach-zynq/Kconfig +++ b/arch/arm/mach-zynq/Kconfig @@ -8,6 +8,7 @@ config ARCH_ZYNQ select ICST select MIGHT_HAVE_CACHE_L2X0 select USE_OF + select HAVE_SMP select SPARSE_IRQ select CADENCE_TTC_TIMER help diff --git a/arch/arm/mach-zynq/Makefile b/arch/arm/mach-zynq/Makefile index 13ee09b..b595d22 100644 --- a/arch/arm/mach-zynq/Makefile +++ b/arch/arm/mach-zynq/Makefile @@ -4,3 +4,4 @@ # Common support obj-y := common.o slcr.o +obj-$(CONFIG_SMP) += headsmp.o platsmp.o diff --git a/arch/arm/mach-zynq/common.c b/arch/arm/mach-zynq/common.c index e1b6131..5bfe703 100644 --- a/arch/arm/mach-zynq/common.c +++ b/arch/arm/mach-zynq/common.c @@ -104,6 +104,7 @@ static const char * const zynq_dt_match[] = { }; MACHINE_START(XILINX_EP107, "Xilinx Zynq Platform") + .smp = smp_ops(zynq_smp_ops), .map_io = zynq_map_io, .init_irq = irqchip_init, .init_machine = zynq_init_machine, diff --git a/arch/arm/mach-zynq/common.h b/arch/arm/mach-zynq/common.h index d7ec3ca..fd308f8 100644 --- a/arch/arm/mach-zynq/common.h +++ b/arch/arm/mach-zynq/common.h @@ -19,6 +19,17 @@ extern int zynq_slcr_init(void); extern void zynq_slcr_system_reset(void); +extern void zynq_slcr_cpu_stop(int cpu); +extern void zynq_slcr_cpu_start(int cpu); + +#ifdef CONFIG_SMP +extern void secondary_startup(void); +extern char zynq_secondary_trampoline; +extern char zynq_secondary_trampoline_jump; +extern char zynq_secondary_trampoline_end; +extern int __cpuinit zynq_cpun_start(u32 address, int cpu); +extern struct smp_operations zynq_smp_ops __initdata; +#endif extern void __iomem *zynq_slcr_base; extern void __iomem *zynq_scu_base; diff --git a/arch/arm/mach-zynq/headsmp.S b/arch/arm/mach-zynq/headsmp.S new file mode 100644 index 0000000..d183cd2 --- /dev/null +++ b/arch/arm/mach-zynq/headsmp.S @@ -0,0 +1,24 @@ +/* + * Copyright (c) 2013 Steffen Trumtrar + * Copyright (c) 2012-2013 Xilinx + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#include +#include + + __CPUINIT + +ENTRY(zynq_secondary_trampoline) + ldr r0, [pc] + bx r0 +.globl zynq_secondary_trampoline_jump +zynq_secondary_trampoline_jump: + /* Space for jumping address */ + .word /* cpu 1 */ +.globl zynq_secondary_trampoline_end +zynq_secondary_trampoline_end: + +ENDPROC(zynq_secondary_trampoline) diff --git a/arch/arm/mach-zynq/platsmp.c b/arch/arm/mach-zynq/platsmp.c new file mode 100644 index 0000000..cdfd888 --- /dev/null +++ b/arch/arm/mach-zynq/platsmp.c @@ -0,0 +1,149 @@ +/* + * This file contains Xilinx specific SMP code, used to start up + * the second processor. + * + * Copyright (C) 2011-2013 Xilinx + * + * based on linux/arch/arm/mach-realview/platsmp.c + * + * Copyright (C) 2002 ARM Ltd. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include "common.h" + +/* + * Store number of cores in the system + * Because of scu_get_core_count() must be in __init section and can't + * be called from zynq_cpun_start() because it is in __cpuinit section. + */ +static int ncores; + +/* Secondary CPU kernel startup is a 2 step process. The primary CPU + * starts the secondary CPU by giving it the address of the kernel and + * then sending it an event to wake it up. The secondary CPU then + * starts the kernel and tells the primary CPU it's up and running. + */ +static void __cpuinit zynq_secondary_init(unsigned int cpu) +{ + /* + * if any interrupts are already enabled for the primary + * core (e.g. timer irq), then they will not have been enabled + * for us: do so + */ + gic_secondary_init(0); +} + +int __cpuinit zynq_cpun_start(u32 address, int cpu) +{ + u32 trampoline_code_size = &zynq_secondary_trampoline_end - + &zynq_secondary_trampoline; + + if (cpu > ncores) { + pr_warn("CPU No. is not available in the system\n"); + return -1; + } + + /* MS: Expectation that SLCR are directly map and accessible */ + /* Not possible to jump to non aligned address */ + if (!(address & 3) && (!address || (address >= trampoline_code_size))) { + /* Store pointer to ioremap area which points to address 0x0 */ + static u8 __iomem *zero; + u32 trampoline_size = &zynq_secondary_trampoline_jump - + &zynq_secondary_trampoline; + + zynq_slcr_cpu_stop(cpu); + + if (__pa(PAGE_OFFSET)) { + zero = ioremap(0, trampoline_code_size); + if (!zero) { + pr_warn("BOOTUP jump vectors not accessible\n"); + return -1; + } + } else { + zero = (__force u8 __iomem *)PAGE_OFFSET; + } + + /* + * This is elegant way how to jump to any address + * 0x0: Load address at 0x8 to r0 + * 0x4: Jump by mov instruction + * 0x8: Jumping address + */ + memcpy((__force void *)zero, &zynq_secondary_trampoline, + trampoline_size); + writel(address, zero + trampoline_size); + + flush_cache_all(); + outer_flush_range(0, trampoline_code_size); + smp_wmb(); + + if (__pa(PAGE_OFFSET)) + iounmap(zero); + + zynq_slcr_cpu_start(cpu); + + return 0; + } + + pr_warn("Can't start CPU%d: Wrong starting address %x\n", cpu, address); + + return -1; +} +EXPORT_SYMBOL(zynq_cpun_start); + +static int __cpuinit zynq_boot_secondary(unsigned int cpu, + struct task_struct *idle) +{ + return zynq_cpun_start(virt_to_phys(secondary_startup), cpu); +} + +/* + * Initialise the CPU possible map early - this describes the CPUs + * which may be present or become present in the system. + */ +static void __init zynq_smp_init_cpus(void) +{ + int i; + + ncores = scu_get_core_count(zynq_scu_base); + + for (i = 0; i < ncores && i < CONFIG_NR_CPUS; i++) + set_cpu_possible(i, true); +} + +static void __init zynq_smp_prepare_cpus(unsigned int max_cpus) +{ + int i; + + /* + * Initialise the present map, which describes the set of CPUs + * actually populated at the present time. + */ + for (i = 0; i < max_cpus; i++) + set_cpu_present(i, true); + + scu_enable(zynq_scu_base); +} + +struct smp_operations zynq_smp_ops __initdata = { + .smp_init_cpus = zynq_smp_init_cpus, + .smp_prepare_cpus = zynq_smp_prepare_cpus, + .smp_secondary_init = zynq_secondary_init, + .smp_boot_secondary = zynq_boot_secondary, +}; diff --git a/arch/arm/mach-zynq/slcr.c b/arch/arm/mach-zynq/slcr.c index d58c996..c70969b 100644 --- a/arch/arm/mach-zynq/slcr.c +++ b/arch/arm/mach-zynq/slcr.c @@ -33,6 +33,11 @@ #define SLCR_UNLOCK 0x8 /* SCLR unlock register */ #define SLCR_PS_RST_CTRL_OFFSET 0x200 /* PS Software Reset Control */ + +#define SLCR_A9_CPU_CLKSTOP 0x10 +#define SLCR_A9_CPU_RST 0x1 + +#define SLCR_A9_CPU_RST_CTRL 0x244 /* CPU Software Reset Control */ #define SLCR_REBOOT_STATUS 0x258 /* PS Reboot Status */ void __iomem *zynq_slcr_base; @@ -62,6 +67,30 @@ void zynq_slcr_system_reset(void) } /** + * zynq_slcr_cpu_start - Start cpu + * @cpu: cpu number + */ +void zynq_slcr_cpu_start(int cpu) +{ + /* enable CPUn */ + writel(SLCR_A9_CPU_CLKSTOP << cpu, + zynq_slcr_base + SLCR_A9_CPU_RST_CTRL); + /* enable CLK for CPUn */ + writel(0x0 << cpu, zynq_slcr_base + SLCR_A9_CPU_RST_CTRL); +} + +/** + * zynq_slcr_cpu_stop - Stop cpu + * @cpu: cpu number + */ +void zynq_slcr_cpu_stop(int cpu) +{ + /* stop CLK and reset CPUn */ + writel((SLCR_A9_CPU_CLKSTOP | SLCR_A9_CPU_RST) << cpu, + zynq_slcr_base + SLCR_A9_CPU_RST_CTRL); +} + +/** * zynq_slcr_init * Returns 0 on success, negative errno otherwise. * -- cgit v1.1 From c7c28b0fdd06d8eb9414d21f8956b7c773ceea93 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 20 Mar 2013 13:56:15 +0100 Subject: arm: zynq: Add hotplug support Signed-off-by: Michal Simek --- arch/arm/mach-zynq/Makefile | 3 ++ arch/arm/mach-zynq/common.h | 3 ++ arch/arm/mach-zynq/hotplug.c | 104 +++++++++++++++++++++++++++++++++++++++++++ arch/arm/mach-zynq/platsmp.c | 3 ++ 4 files changed, 113 insertions(+) create mode 100644 arch/arm/mach-zynq/hotplug.c (limited to 'arch/arm/mach-zynq') diff --git a/arch/arm/mach-zynq/Makefile b/arch/arm/mach-zynq/Makefile index b595d22..1b25d92 100644 --- a/arch/arm/mach-zynq/Makefile +++ b/arch/arm/mach-zynq/Makefile @@ -4,4 +4,7 @@ # Common support obj-y := common.o slcr.o +CFLAGS_REMOVE_hotplug.o =-march=armv6k +CFLAGS_hotplug.o =-Wa,-march=armv7-a -mcpu=cortex-a9 +obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o obj-$(CONFIG_SMP) += headsmp.o platsmp.o diff --git a/arch/arm/mach-zynq/common.h b/arch/arm/mach-zynq/common.h index fd308f8..fbbd0e2 100644 --- a/arch/arm/mach-zynq/common.h +++ b/arch/arm/mach-zynq/common.h @@ -34,4 +34,7 @@ extern struct smp_operations zynq_smp_ops __initdata; extern void __iomem *zynq_slcr_base; extern void __iomem *zynq_scu_base; +/* Hotplug */ +extern void zynq_platform_cpu_die(unsigned int cpu); + #endif diff --git a/arch/arm/mach-zynq/hotplug.c b/arch/arm/mach-zynq/hotplug.c new file mode 100644 index 0000000..c89672b --- /dev/null +++ b/arch/arm/mach-zynq/hotplug.c @@ -0,0 +1,104 @@ +/* + * Copyright (C) 2012-2013 Xilinx + * + * based on linux/arch/arm/mach-realview/hotplug.c + * + * Copyright (C) 2002 ARM Ltd. + * All Rights Reserved + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#include +#include +#include + +#include +#include +#include "common.h" + +static inline void zynq_cpu_enter_lowpower(void) +{ + unsigned int v; + + flush_cache_all(); + asm volatile( + " mcr p15, 0, %1, c7, c5, 0\n" + " dsb\n" + /* + * Turn off coherency + */ + " mrc p15, 0, %0, c1, c0, 1\n" + " bic %0, %0, #0x40\n" + " mcr p15, 0, %0, c1, c0, 1\n" + " mrc p15, 0, %0, c1, c0, 0\n" + " bic %0, %0, %2\n" + " mcr p15, 0, %0, c1, c0, 0\n" + : "=&r" (v) + : "r" (0), "Ir" (CR_C) + : "cc"); +} + +static inline void zynq_cpu_leave_lowpower(void) +{ + unsigned int v; + + asm volatile( + " mrc p15, 0, %0, c1, c0, 0\n" + " orr %0, %0, %1\n" + " mcr p15, 0, %0, c1, c0, 0\n" + " mrc p15, 0, %0, c1, c0, 1\n" + " orr %0, %0, #0x40\n" + " mcr p15, 0, %0, c1, c0, 1\n" + : "=&r" (v) + : "Ir" (CR_C) + : "cc"); +} + +static inline void zynq_platform_do_lowpower(unsigned int cpu, int *spurious) +{ + /* + * there is no power-control hardware on this platform, so all + * we can do is put the core into WFI; this is safe as the calling + * code will have already disabled interrupts + */ + for (;;) { + dsb(); + wfi(); + + /* + * Getting here, means that we have come out of WFI without + * having been woken up - this shouldn't happen + * + * Just note it happening - when we're woken, we can report + * its occurrence. + */ + (*spurious)++; + } +} + +/* + * platform-specific code to shutdown a CPU + * + * Called with IRQs disabled + */ +void zynq_platform_cpu_die(unsigned int cpu) +{ + int spurious = 0; + + /* + * we're ready for shutdown now, so do it + */ + zynq_cpu_enter_lowpower(); + zynq_platform_do_lowpower(cpu, &spurious); + + /* + * bring this CPU back into the world of cache + * coherency, and then restore interrupts + */ + zynq_cpu_leave_lowpower(); + + if (spurious) + pr_warn("CPU%u: %u spurious wakeup calls\n", cpu, spurious); +} diff --git a/arch/arm/mach-zynq/platsmp.c b/arch/arm/mach-zynq/platsmp.c index cdfd888..3072cbd 100644 --- a/arch/arm/mach-zynq/platsmp.c +++ b/arch/arm/mach-zynq/platsmp.c @@ -146,4 +146,7 @@ struct smp_operations zynq_smp_ops __initdata = { .smp_prepare_cpus = zynq_smp_prepare_cpus, .smp_secondary_init = zynq_secondary_init, .smp_boot_secondary = zynq_boot_secondary, +#ifdef CONFIG_HOTPLUG_CPU + .cpu_die = zynq_platform_cpu_die, +#endif }; -- cgit v1.1