From d6dd735f4bda19bfe07d96d9025c94c4619d4596 Mon Sep 17 00:00:00 2001 From: Dinh Nguyen Date: Mon, 11 Feb 2013 17:30:33 -0600 Subject: arm: socfpga: Add SMP support for actual socfpga harware Because the CPU1 start address is different for socfpga-vt and socfpga-cyclone5, we add code to use the correct CPU1 start addr. Signed-off-by: Dinh Nguyen Signed-off-by: Pavel Machek Cc: Russell King Cc: Arnd Bergmann Cc: Olof Johansson Cc: Rob Herring Cc: Grant Likely Signed-off-by: Olof Johansson --- arch/arm/mach-socfpga/headsmp.S | 16 ++++++++++++---- 1 file changed, 12 insertions(+), 4 deletions(-) (limited to 'arch/arm/mach-socfpga/headsmp.S') diff --git a/arch/arm/mach-socfpga/headsmp.S b/arch/arm/mach-socfpga/headsmp.S index f09b128..9004bfb 100644 --- a/arch/arm/mach-socfpga/headsmp.S +++ b/arch/arm/mach-socfpga/headsmp.S @@ -13,13 +13,21 @@ __CPUINIT .arch armv7-a -#define CPU1_START_ADDR 0xffd08010 - ENTRY(secondary_trampoline) - movw r0, #:lower16:CPU1_START_ADDR - movt r0, #:upper16:CPU1_START_ADDR + movw r2, #:lower16:cpu1start_addr + movt r2, #:upper16:cpu1start_addr + + /* The socfpga VT cannot handle a 0xC0000000 page offset when loading + the cpu1start_addr, we bit clear it. Tested on HW and VT. */ + bic r2, r2, #0x40000000 + ldr r0, [r2] ldr r1, [r0] bx r1 ENTRY(secondary_trampoline_end) + +ENTRY(socfpga_secondary_startup) + bl v7_invalidate_l1 + b secondary_startup +ENDPROC(socfpga_secondary_startup) -- cgit v1.1