From 52e329ebb05983153bbde7351c94449018651290 Mon Sep 17 00:00:00 2001 From: Kukjin Kim Date: Tue, 4 Oct 2011 19:41:43 +0900 Subject: ARM: SAMSUNG: Consolidate plat/pll.h Removed - arch/arm/plat-s3c24xx/include/plat/pll.h - arch/arm/mach-s3c64xx/include/mach/pll.h - arch/arm/plat-s5p/include/plat/pll.h - arch/arm/plat-samsung/include/plat/pll6553x.h And created - arch/arm/plat-samsung/include/plat/pll.h Cc: Ben Dooks [kgene.kim@samsung.com: changed title] [kgene.kim@samsung.com: fixed conflicts in plat-s5p/include/pll.h] Signed-off-by: Kukjin Kim --- arch/arm/mach-s3c64xx/clock.c | 5 ++-- arch/arm/mach-s3c64xx/include/mach/pll.h | 45 -------------------------------- 2 files changed, 3 insertions(+), 47 deletions(-) delete mode 100644 arch/arm/mach-s3c64xx/include/mach/pll.h (limited to 'arch/arm/mach-s3c64xx') diff --git a/arch/arm/mach-s3c64xx/clock.c b/arch/arm/mach-s3c64xx/clock.c index 8cf39e3..4adc51c 100644 --- a/arch/arm/mach-s3c64xx/clock.c +++ b/arch/arm/mach-s3c64xx/clock.c @@ -25,13 +25,13 @@ #include #include -#include #include #include #include #include #include +#include /* fin_apll, fin_mpll and fin_epll are all the same clock, which we call * ext_xtal_mux for want of an actual name from the manual. @@ -735,7 +735,8 @@ void __init_or_cpufreq s3c6400_setup_clocks(void) /* For now assume the mux always selects the crystal */ clk_ext_xtal_mux.parent = xtal_clk; - epll = s3c6400_get_epll(xtal); + epll = s3c_get_pll6553x(xtal, __raw_readl(S3C_EPLL_CON0), + __raw_readl(S3C_EPLL_CON1)); mpll = s3c6400_get_pll(xtal, __raw_readl(S3C_MPLL_CON)); apll = s3c6400_get_pll(xtal, __raw_readl(S3C_APLL_CON)); diff --git a/arch/arm/mach-s3c64xx/include/mach/pll.h b/arch/arm/mach-s3c64xx/include/mach/pll.h deleted file mode 100644 index 5ef0bb6..0000000 --- a/arch/arm/mach-s3c64xx/include/mach/pll.h +++ /dev/null @@ -1,45 +0,0 @@ -/* arch/arm/plat-s3c64xx/include/plat/pll.h - * - * Copyright 2008 Openmoko, Inc. - * Copyright 2008 Simtec Electronics - * Ben Dooks - * http://armlinux.simtec.co.uk/ - * - * S3C64XX PLL code - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#define S3C6400_PLL_MDIV_MASK ((1 << (25-16+1)) - 1) -#define S3C6400_PLL_PDIV_MASK ((1 << (13-8+1)) - 1) -#define S3C6400_PLL_SDIV_MASK ((1 << (2-0+1)) - 1) -#define S3C6400_PLL_MDIV_SHIFT (16) -#define S3C6400_PLL_PDIV_SHIFT (8) -#define S3C6400_PLL_SDIV_SHIFT (0) - -#include -#include - -static inline unsigned long s3c6400_get_pll(unsigned long baseclk, - u32 pllcon) -{ - u32 mdiv, pdiv, sdiv; - u64 fvco = baseclk; - - mdiv = (pllcon >> S3C6400_PLL_MDIV_SHIFT) & S3C6400_PLL_MDIV_MASK; - pdiv = (pllcon >> S3C6400_PLL_PDIV_SHIFT) & S3C6400_PLL_PDIV_MASK; - sdiv = (pllcon >> S3C6400_PLL_SDIV_SHIFT) & S3C6400_PLL_SDIV_MASK; - - fvco *= mdiv; - do_div(fvco, (pdiv << sdiv)); - - return (unsigned long)fvco; -} - -static inline unsigned long s3c6400_get_epll(unsigned long baseclk) -{ - return s3c_get_pll6553x(baseclk, __raw_readl(S3C_EPLL_CON0), - __raw_readl(S3C_EPLL_CON1)); -} -- cgit v1.1