From 1124d2f9186ec9e42e1c3f78c20199ba2cb597e2 Mon Sep 17 00:00:00 2001 From: Paul Walmsley Date: Tue, 21 Dec 2010 21:08:14 -0700 Subject: OMAP2/3: SRAM: add comment about crashes during a TLB miss Some users were observing crashes during the execution of CORE DVFS code from OCM RAM -- a locally-modified copy of the linux-omap code. Richard Woodruff tracked this down to a DTLB miss which had been inadvertently and intermittently caused by the local modifications. (The TLB miss caused the ARM MMU to attempt to walk the page tables stored in SDRAM, which was not possible since SDRAM is off-line for a portion of the CORE DVFS OCM RAM code.) Add a note to the OMAP2 & OMAP3 CORE DVFS SRAM code to warn others that changes may result in crashes here if they are not carefully tested. Signed-off-by: Paul Walmsley Cc: Richard Woodruff Cc: Jon Hunter Cc: Nishanth Menon --- arch/arm/mach-omap2/sram243x.S | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'arch/arm/mach-omap2/sram243x.S') diff --git a/arch/arm/mach-omap2/sram243x.S b/arch/arm/mach-omap2/sram243x.S index 9ea87f6..f900758 100644 --- a/arch/arm/mach-omap2/sram243x.S +++ b/arch/arm/mach-omap2/sram243x.S @@ -21,6 +21,12 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA + * + * Richard Woodruff notes that any changes to this code must be carefully + * audited and tested to ensure that they don't cause a TLB miss while + * the SDRAM is inaccessible. Such a situation will crash the system + * since it will cause the ARM MMU to attempt to walk the page tables. + * These crashes may be intermittent. */ #include #include -- cgit v1.1