From 3863c74b512c1afd3ce6b2f81d8dea9f1d860968 Mon Sep 17 00:00:00 2001 From: Thara Gopinath Date: Tue, 8 Dec 2009 16:33:15 -0700 Subject: OMAP3: PM: Fix for MPU power domain MEM BANK position MPU power domain bank 0 bits are displayed in position of bank 1 in PWRSTS and PREPWRSTS registers. So read them from correct position Signed-off-by: Thara Gopinath Signed-off-by: Kevin Hilman Signed-off-by: Paul Walmsley --- arch/arm/mach-omap2/powerdomain.c | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'arch/arm/mach-omap2/powerdomain.c') diff --git a/arch/arm/mach-omap2/powerdomain.c b/arch/arm/mach-omap2/powerdomain.c index 47d5768..26b3f3e 100644 --- a/arch/arm/mach-omap2/powerdomain.c +++ b/arch/arm/mach-omap2/powerdomain.c @@ -983,6 +983,9 @@ int pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank) if (pwrdm->banks < (bank + 1)) return -EEXIST; + if (pwrdm->flags & PWRDM_HAS_MPU_QUIRK) + bank = 1; + /* * The register bit names below may not correspond to the * actual names of the bits in each powerdomain's register, @@ -1030,6 +1033,9 @@ int pwrdm_read_prev_mem_pwrst(struct powerdomain *pwrdm, u8 bank) if (pwrdm->banks < (bank + 1)) return -EEXIST; + if (pwrdm->flags & PWRDM_HAS_MPU_QUIRK) + bank = 1; + /* * The register bit names below may not correspond to the * actual names of the bits in each powerdomain's register, -- cgit v1.1