From 247c445c0fbd52c77e497ff5bfcf0dceb8afea8d Mon Sep 17 00:00:00 2001 From: Santosh Shilimkar Date: Wed, 9 May 2012 20:38:35 +0530 Subject: ARM: OMAP5: Add the WakeupGen IP updates OMAP4 and OMAP5 share same WakeupGen IP with below few udpates on OMAP5. - Additional 32 interrupt support is added w.r.t OMAP4 design. - The AUX CORE boot registers are now made accessible from non-secure SW. - SAR offset are changed and PTMSYNC* registers are removed from SAR. Patch updates the WakeupGen code accordingly. Signed-off-by: R Sricharan Signed-off-by: Santosh Shilimkar --- arch/arm/mach-omap2/include/mach/omap-wakeupgen.h | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'arch/arm/mach-omap2/include') diff --git a/arch/arm/mach-omap2/include/mach/omap-wakeupgen.h b/arch/arm/mach-omap2/include/mach/omap-wakeupgen.h index 548de90b..b0fd16f 100644 --- a/arch/arm/mach-omap2/include/mach/omap-wakeupgen.h +++ b/arch/arm/mach-omap2/include/mach/omap-wakeupgen.h @@ -11,15 +11,20 @@ #ifndef OMAP_ARCH_WAKEUPGEN_H #define OMAP_ARCH_WAKEUPGEN_H +/* OMAP4 and OMAP5 has same base address */ +#define OMAP_WKUPGEN_BASE 0x48281000 + #define OMAP_WKG_CONTROL_0 0x00 #define OMAP_WKG_ENB_A_0 0x10 #define OMAP_WKG_ENB_B_0 0x14 #define OMAP_WKG_ENB_C_0 0x18 #define OMAP_WKG_ENB_D_0 0x1c +#define OMAP_WKG_ENB_E_0 0x20 #define OMAP_WKG_ENB_A_1 0x410 #define OMAP_WKG_ENB_B_1 0x414 #define OMAP_WKG_ENB_C_1 0x418 #define OMAP_WKG_ENB_D_1 0x41c +#define OMAP_WKG_ENB_E_1 0x420 #define OMAP_AUX_CORE_BOOT_0 0x800 #define OMAP_AUX_CORE_BOOT_1 0x804 #define OMAP_PTMSYNCREQ_MASK 0xc00 @@ -28,4 +33,6 @@ #define OMAP_TIMESTAMPCYCLEHI 0xc0c extern int __init omap_wakeupgen_init(void); +extern void __iomem *omap_get_wakeupgen_base(void); +extern int omap_secure_apis_support(void); #endif -- cgit v1.1