From 57b317f912b3f4b05c834818c73d7c8ea22642f7 Mon Sep 17 00:00:00 2001 From: Kisoo Yu Date: Tue, 24 Apr 2012 14:54:15 -0700 Subject: ARM: EXYNOS: Add pre-divider and fout mux clocks for bpll and mpll The fout clock of BPLL and MPLL have a selectable source on EXYNOS5250. The clock options are a fixed divided by 2 clock and the output of the PLL itself. Add support for these new clock instances. Signed-off-by: Kisoo Yu Signed-off-by: Thomas Abraham [kgene.kim@samsung.com: moved common pll stuff into s5p-clock.c] Signed-off-by: Kukjin Kim --- arch/arm/mach-exynos/include/mach/regs-clock.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/arm/mach-exynos/include/mach') diff --git a/arch/arm/mach-exynos/include/mach/regs-clock.h b/arch/arm/mach-exynos/include/mach/regs-clock.h index dba83e9..b78b5f3 100644 --- a/arch/arm/mach-exynos/include/mach/regs-clock.h +++ b/arch/arm/mach-exynos/include/mach/regs-clock.h @@ -322,6 +322,8 @@ #define EXYNOS5_CLKSRC_CDREX EXYNOS_CLKREG(0x20200) #define EXYNOS5_CLKDIV_CDREX EXYNOS_CLKREG(0x20500) +#define EXYNOS5_PLL_DIV2_SEL EXYNOS_CLKREG(0x20A24) + #define EXYNOS5_EPLL_LOCK EXYNOS_CLKREG(0x10030) #define EXYNOS5_EPLLCON0_LOCKED_SHIFT (29) -- cgit v1.1