From 79f08d9ed217318b4f325b7fcf8f26dcd0e41689 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Mon, 21 Oct 2013 11:07:04 +0200 Subject: ARM: drop for !ARCH_MULTIPLATFORM, too MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit While isn't used for multi-platform builds since long it still is for "normal" builds. As the previous patches fix all sites to not make use of this per-platform file, it can go now for good also for platforms that are not (yet) converted to multi-platform. While at it there are no users of CLOCK_TICK_RATE any more, so also drop the dummy #define. Signed-off-by: Uwe Kleine-König --- arch/arm/mach-clps711x/include/mach/timex.h | 2 -- 1 file changed, 2 deletions(-) delete mode 100644 arch/arm/mach-clps711x/include/mach/timex.h (limited to 'arch/arm/mach-clps711x') diff --git a/arch/arm/mach-clps711x/include/mach/timex.h b/arch/arm/mach-clps711x/include/mach/timex.h deleted file mode 100644 index de6fd19..0000000 --- a/arch/arm/mach-clps711x/include/mach/timex.h +++ /dev/null @@ -1,2 +0,0 @@ -/* Bogus value */ -#define CLOCK_TICK_RATE 512000 -- cgit v1.1 From 32c6c01b0e58c38c4f4256091633f6b342987e28 Mon Sep 17 00:00:00 2001 From: Alexander Shiyan Date: Sat, 15 Feb 2014 12:05:31 +0400 Subject: ARM: clps711x: Remove EP72XX_ROM_BOOT option CLPS711X CPUs have 128 bytes of on-chip Boot ROM with an instruction sequence that configure UART1 to receive up to 2 Kbytes of serial data which is then placed in the on-chip SRAM. Once the download is complete, the program counter jumps to SRAM to begin executed the downloaded data. The purpose of this mode is to allow the downloaded code to facilitate programming of FLASH or other ROM device. Selection of the internal Boot ROM is accomplished at power-on-reset time. No reason to keep this special (develop only) mode in the kernel. This patch removes EP72XX_ROM_BOOT kernel symbol. Signed-off-by: Alexander Shiyan Signed-off-by: Arnd Bergmann --- arch/arm/mach-clps711x/Kconfig | 14 -------------- arch/arm/mach-clps711x/include/mach/hardware.h | 17 ----------------- 2 files changed, 31 deletions(-) (limited to 'arch/arm/mach-clps711x') diff --git a/arch/arm/mach-clps711x/Kconfig b/arch/arm/mach-clps711x/Kconfig index bea6295..f711498 100644 --- a/arch/arm/mach-clps711x/Kconfig +++ b/arch/arm/mach-clps711x/Kconfig @@ -33,20 +33,6 @@ config ARCH_P720T Say Y here if you intend to run this kernel on the ARM Prospector 720T. -config EP72XX_ROM_BOOT - bool "EP721x/EP731x ROM boot" - help - If you say Y here, your CLPS711x-based kernel will use the bootstrap - mode memory map instead of the normal memory map. - - Processors derived from the Cirrus CLPS711X core support two boot - modes. Normal mode boots from the external memory device at CS0. - Bootstrap mode rearranges parts of the memory map, placing an - internal 128 byte bootstrap ROM at CS0. This option performs the - address map changes required to support booting in this mode. - - You almost surely want to say N here. - endmenu endif diff --git a/arch/arm/mach-clps711x/include/mach/hardware.h b/arch/arm/mach-clps711x/include/mach/hardware.h index c5a8ea6..5d6afda 100644 --- a/arch/arm/mach-clps711x/include/mach/hardware.h +++ b/arch/arm/mach-clps711x/include/mach/hardware.h @@ -38,13 +38,6 @@ #define clps_writel(val,off) writel(val, CLPS711X_VIRT_BASE + (off)) #endif -/* - * The physical addresses that the external chip select signals map to is - * dependent on the setting of the nMEDCHG signal on EP7211 and EP7212 - * processors. CONFIG_EP72XX_BOOT_ROM is only available if these - * processors are in use. - */ -#ifndef CONFIG_EP72XX_ROM_BOOT #define CS0_PHYS_BASE (0x00000000) #define CS1_PHYS_BASE (0x10000000) #define CS2_PHYS_BASE (0x20000000) @@ -53,16 +46,6 @@ #define CS5_PHYS_BASE (0x50000000) #define CS6_PHYS_BASE (0x60000000) #define CS7_PHYS_BASE (0x70000000) -#else -#define CS0_PHYS_BASE (0x70000000) -#define CS1_PHYS_BASE (0x60000000) -#define CS2_PHYS_BASE (0x50000000) -#define CS3_PHYS_BASE (0x40000000) -#define CS4_PHYS_BASE (0x30000000) -#define CS5_PHYS_BASE (0x20000000) -#define CS6_PHYS_BASE (0x10000000) -#define CS7_PHYS_BASE (0x00000000) -#endif #define CLPS711X_SRAM_BASE CS6_PHYS_BASE #define CLPS711X_SRAM_SIZE (48 * 1024) -- cgit v1.1