From f5178ddd2f09de8b1cfc5e19043892e8b24666cb Mon Sep 17 00:00:00 2001 From: Nicolas Pitre Date: Tue, 3 May 2011 15:30:34 -0400 Subject: ARM: PJ4: remove the ARMv6 compatible cache method entries The Marvell PJ4 is ARMv7 capable, so we don't support it in ARMv6 mode anymore. Signed-off-by: Nicolas Pitre Acked-by: Saeed Bishara Acked-by: Haojian Zhuang --- arch/arm/boot/compressed/head.S | 6 ------ 1 file changed, 6 deletions(-) (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S index adf583c..a36f452 100644 --- a/arch/arm/boot/compressed/head.S +++ b/arch/arm/boot/compressed/head.S @@ -735,12 +735,6 @@ proc_types: W(b) __armv4_mmu_cache_off W(b) __armv6_mmu_cache_flush - .word 0x560f5810 @ Marvell PJ4 ARMv6 - .word 0xff0ffff0 - W(b) __armv4_mmu_cache_on - W(b) __armv4_mmu_cache_off - W(b) __armv6_mmu_cache_flush - .word 0x000f0000 @ new CPU Id .word 0x000f0000 W(b) __armv7_mmu_cache_on -- cgit v1.1