From c5fa4fdcdbe5f52c3e36892cc81f9378339b00ce Mon Sep 17 00:00:00 2001 From: Viresh Kumar Date: Fri, 23 Mar 2012 00:17:43 +0530 Subject: ARM: SPEAr3xx: Add device-tree support to SPEAr3xx architecture This patch adds a generic target for SPEAr3xx machines that can be configured via the device-tree. Currently the following devices are supported via the devicetree: - VIC interrupts - PL011 UART - PL061 GPIO - PL110 CLCD - SP805 WDT - Synopsys DW I2C - Synopsys DW ethernet - ST FSMC-NAND - ST SPEAR-SMI - ST SPEAR-KEYBOARD - ST SPEAR-RTC - ARASAN SDHCI-SPEAR - SPEAR-EHCI - SPEAR-OHCI Other peripheral devices will follow in later patches. This also removes IO_ADDRESS macro and creates 16 MB static mappings instead of 4K for individual peripherals. This is done to have efficient TLB lookup for any I/O windows that are located closely together. ioremap() on this range will return this mapping only instead of creating another. Signed-off-by: Viresh Kumar --- arch/arm/boot/dts/spear300-evb.dts | 179 +++++++++++++++++++++++++++++++++++++ arch/arm/boot/dts/spear300.dtsi | 72 +++++++++++++++ arch/arm/boot/dts/spear310-evb.dts | 107 ++++++++++++++++++++++ arch/arm/boot/dts/spear310.dtsi | 75 ++++++++++++++++ arch/arm/boot/dts/spear320-evb.dts | 108 ++++++++++++++++++++++ arch/arm/boot/dts/spear320.dtsi | 90 +++++++++++++++++++ arch/arm/boot/dts/spear3xx.dtsi | 136 ++++++++++++++++++++++++++++ 7 files changed, 767 insertions(+) create mode 100644 arch/arm/boot/dts/spear300-evb.dts create mode 100644 arch/arm/boot/dts/spear300.dtsi create mode 100644 arch/arm/boot/dts/spear310-evb.dts create mode 100644 arch/arm/boot/dts/spear310.dtsi create mode 100644 arch/arm/boot/dts/spear320-evb.dts create mode 100644 arch/arm/boot/dts/spear320.dtsi create mode 100644 arch/arm/boot/dts/spear3xx.dtsi (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/dts/spear300-evb.dts b/arch/arm/boot/dts/spear300-evb.dts new file mode 100644 index 0000000..f2ee9917 --- /dev/null +++ b/arch/arm/boot/dts/spear300-evb.dts @@ -0,0 +1,179 @@ +/* + * DTS file for SPEAr300 Evaluation Baord + * + * Copyright 2012 Viresh Kumar + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; +/include/ "spear300.dtsi" + +/ { + model = "ST SPEAr300 Evaluation Board"; + compatible = "st,spear300-evb", "st,spear300"; + #address-cells = <1>; + #size-cells = <1>; + + memory { + reg = <0 0x40000000>; + }; + + ahb { + clcd@60000000 { + status = "okay"; + }; + + fsmc: flash@94000000 { + status = "okay"; + }; + + gmac: eth@e0800000 { + status = "okay"; + }; + + sdhci@70000000 { + int-gpio = <&gpio1 0 0>; + power-gpio = <&gpio1 2 1>; + status = "okay"; + }; + + smi: flash@fc000000 { + status = "okay"; + }; + + spi0: spi@d0100000 { + status = "okay"; + }; + + ehci@e1800000 { + status = "okay"; + }; + + ohci@e1900000 { + status = "okay"; + }; + + ohci@e2100000 { + status = "okay"; + }; + + apb { + gpio0: gpio@fc980000 { + status = "okay"; + }; + + gpio1: gpio@a9000000 { + status = "okay"; + }; + + i2c0: i2c@d0180000 { + status = "okay"; + }; + + kbd@a0000000 { + linux,keymap = < 0x00010000 + 0x00020100 + 0x00030200 + 0x00040300 + 0x00050400 + 0x00060500 + 0x00070600 + 0x00080700 + 0x00090800 + 0x000a0001 + 0x000c0101 + 0x000d0201 + 0x000e0301 + 0x000f0401 + 0x00100501 + 0x00110601 + 0x00120701 + 0x00130801 + 0x00140002 + 0x00150102 + 0x00160202 + 0x00170302 + 0x00180402 + 0x00190502 + 0x001a0602 + 0x001b0702 + 0x001c0802 + 0x001d0003 + 0x001e0103 + 0x001f0203 + 0x00200303 + 0x00210403 + 0x00220503 + 0x00230603 + 0x00240703 + 0x00250803 + 0x00260004 + 0x00270104 + 0x00280204 + 0x00290304 + 0x002a0404 + 0x002b0504 + 0x002c0604 + 0x002d0704 + 0x002e0804 + 0x002f0005 + 0x00300105 + 0x00310205 + 0x00320305 + 0x00330405 + 0x00340505 + 0x00350605 + 0x00360705 + 0x00370805 + 0x00380006 + 0x00390106 + 0x003a0206 + 0x003b0306 + 0x003c0406 + 0x003d0506 + 0x003e0606 + 0x003f0706 + 0x00400806 + 0x00410007 + 0x00420107 + 0x00430207 + 0x00440307 + 0x00450407 + 0x00460507 + 0x00470607 + 0x00480707 + 0x00490807 + 0x004a0008 + 0x004b0108 + 0x004c0208 + 0x004d0308 + 0x004e0408 + 0x004f0508 + 0x00500608 + 0x00510708 + 0x00520808 >; + autorepeat; + st,mode = <0>; + status = "okay"; + }; + + rtc@fc900000 { + status = "okay"; + }; + + serial@d0000000 { + status = "okay"; + }; + + wdt@fc880000 { + status = "okay"; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/spear300.dtsi b/arch/arm/boot/dts/spear300.dtsi new file mode 100644 index 0000000..f9fcbf4 --- /dev/null +++ b/arch/arm/boot/dts/spear300.dtsi @@ -0,0 +1,72 @@ +/* + * DTS file for SPEAr300 SoC + * + * Copyright 2012 Viresh Kumar + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/include/ "spear3xx.dtsi" + +/ { + ahb { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges = <0x60000000 0x60000000 0x50000000 + 0xd0000000 0xd0000000 0x30000000>; + + clcd@60000000 { + compatible = "arm,clcd-pl110", "arm,primecell"; + reg = <0x60000000 0x1000>; + interrupts = <30>; + status = "disabled"; + }; + + fsmc: flash@94000000 { + compatible = "st,spear600-fsmc-nand"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x94000000 0x1000 /* FSMC Register */ + 0x80000000 0x0010>; /* NAND Base */ + reg-names = "fsmc_regs", "nand_data"; + st,ale-off = <0x20000>; + st,cle-off = <0x10000>; + status = "disabled"; + }; + + sdhci@70000000 { + compatible = "st,sdhci-spear"; + reg = <0x70000000 0x100>; + interrupts = <1>; + status = "disabled"; + }; + + apb { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges = <0xa0000000 0xa0000000 0x10000000 + 0xd0000000 0xd0000000 0x30000000>; + + gpio1: gpio@a9000000 { + #gpio-cells = <2>; + compatible = "arm,pl061", "arm,primecell"; + gpio-controller; + reg = <0xa9000000 0x1000>; + status = "disabled"; + }; + + kbd@a0000000 { + compatible = "st,spear300-kbd"; + reg = <0xa0000000 0x1000>; + status = "disabled"; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/spear310-evb.dts b/arch/arm/boot/dts/spear310-evb.dts new file mode 100644 index 0000000..ec19d7b --- /dev/null +++ b/arch/arm/boot/dts/spear310-evb.dts @@ -0,0 +1,107 @@ +/* + * DTS file for SPEAr310 Evaluation Baord + * + * Copyright 2012 Viresh Kumar + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; +/include/ "spear310.dtsi" + +/ { + model = "ST SPEAr310 Evaluation Board"; + compatible = "st,spear310-evb", "st,spear310"; + #address-cells = <1>; + #size-cells = <1>; + + memory { + reg = <0 0x40000000>; + }; + + ahb { + fsmc: flash@44000000 { + status = "okay"; + }; + + gmac: eth@e0800000 { + status = "okay"; + }; + + smi: flash@fc000000 { + status = "okay"; + clock-rate=<50000000>; + + flash@f8000000 { + label = "m25p64"; + reg = <0xf8000000 0x800000>; + #address-cells = <1>; + #size-cells = <1>; + st,smi-fast-mode; + }; + }; + + spi0: spi@d0100000 { + status = "okay"; + }; + + ehci@e1800000 { + status = "okay"; + }; + + ohci@e1900000 { + status = "okay"; + }; + + ohci@e2100000 { + status = "okay"; + }; + + apb { + gpio0: gpio@fc980000 { + status = "okay"; + }; + + i2c0: i2c@d0180000 { + status = "okay"; + }; + + rtc@fc900000 { + status = "okay"; + }; + + serial@d0000000 { + status = "okay"; + }; + + serial@b2000000 { + status = "okay"; + }; + + serial@b2080000 { + status = "okay"; + }; + + serial@b2100000 { + status = "okay"; + }; + + serial@b2180000 { + status = "okay"; + }; + + serial@b2200000 { + status = "okay"; + }; + + wdt@fc880000 { + status = "okay"; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/spear310.dtsi b/arch/arm/boot/dts/spear310.dtsi new file mode 100644 index 0000000..dc7fa14 --- /dev/null +++ b/arch/arm/boot/dts/spear310.dtsi @@ -0,0 +1,75 @@ +/* + * DTS file for SPEAr310 SoC + * + * Copyright 2012 Viresh Kumar + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/include/ "spear3xx.dtsi" + +/ { + ahb { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges = <0x40000000 0x40000000 0x10000000 + 0xb0000000 0xb0000000 0x10000000 + 0xd0000000 0xd0000000 0x30000000>; + + fsmc: flash@44000000 { + compatible = "st,spear600-fsmc-nand"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x44000000 0x1000 /* FSMC Register */ + 0x40000000 0x0010>; /* NAND Base */ + reg-names = "fsmc_regs", "nand_data"; + st,ale-off = <0x10000>; + st,cle-off = <0x20000>; + status = "disabled"; + }; + + apb { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges = <0xb0000000 0xb0000000 0x10000000 + 0xd0000000 0xd0000000 0x30000000>; + + serial@b2000000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0xb2000000 0x1000>; + status = "disabled"; + }; + + serial@b2080000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0xb2080000 0x1000>; + status = "disabled"; + }; + + serial@b2100000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0xb2100000 0x1000>; + status = "disabled"; + }; + + serial@b2180000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0xb2180000 0x1000>; + status = "disabled"; + }; + + serial@b2200000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0xb2200000 0x1000>; + status = "disabled"; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/spear320-evb.dts b/arch/arm/boot/dts/spear320-evb.dts new file mode 100644 index 0000000..5681a97 --- /dev/null +++ b/arch/arm/boot/dts/spear320-evb.dts @@ -0,0 +1,108 @@ +/* + * DTS file for SPEAr320 Evaluation Baord + * + * Copyright 2012 Viresh Kumar + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; +/include/ "spear320.dtsi" + +/ { + model = "ST SPEAr300 Evaluation Board"; + compatible = "st,spear300-evb", "st,spear300"; + #address-cells = <1>; + #size-cells = <1>; + + memory { + reg = <0 0x40000000>; + }; + + ahb { + clcd@90000000 { + status = "okay"; + }; + + fsmc: flash@4c000000 { + status = "okay"; + }; + + gmac: eth@e0800000 { + status = "okay"; + }; + + sdhci@70000000 { + power-gpio = <&gpio0 2 1>; + power_always_enb; + status = "okay"; + }; + + smi: flash@fc000000 { + status = "okay"; + }; + + spi0: spi@d0100000 { + status = "okay"; + }; + + spi1: spi@a5000000 { + status = "okay"; + }; + + spi2: spi@a6000000 { + status = "okay"; + }; + + ehci@e1800000 { + status = "okay"; + }; + + ohci@e1900000 { + status = "okay"; + }; + + ohci@e2100000 { + status = "okay"; + }; + + apb { + gpio0: gpio@fc980000 { + status = "okay"; + }; + + i2c0: i2c@d0180000 { + status = "okay"; + }; + + i2c1: i2c@a7000000 { + status = "okay"; + }; + + rtc@fc900000 { + status = "okay"; + }; + + serial@d0000000 { + status = "okay"; + }; + + serial@a3000000 { + status = "okay"; + }; + + serial@a4000000 { + status = "okay"; + }; + + wdt@fc880000 { + status = "okay"; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/spear320.dtsi b/arch/arm/boot/dts/spear320.dtsi new file mode 100644 index 0000000..9a0267a --- /dev/null +++ b/arch/arm/boot/dts/spear320.dtsi @@ -0,0 +1,90 @@ +/* + * DTS file for SPEAr320 SoC + * + * Copyright 2012 Viresh Kumar + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/include/ "spear3xx.dtsi" + +/ { + ahb { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges = <0x40000000 0x40000000 0x70000000 + 0xd0000000 0xd0000000 0x30000000>; + + clcd@90000000 { + compatible = "arm,clcd-pl110", "arm,primecell"; + reg = <0x90000000 0x1000>; + interrupts = <33>; + status = "disabled"; + }; + + fsmc: flash@4c000000 { + compatible = "st,spear600-fsmc-nand"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x4c000000 0x1000 /* FSMC Register */ + 0x50000000 0x0010>; /* NAND Base */ + reg-names = "fsmc_regs", "nand_data"; + st,ale-off = <0x20000>; + st,cle-off = <0x10000>; + status = "disabled"; + }; + + sdhci@70000000 { + compatible = "st,sdhci-spear"; + reg = <0x70000000 0x100>; + interrupts = <29>; + status = "disabled"; + }; + + spi1: spi@a5000000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0xa5000000 0x1000>; + status = "disabled"; + }; + + spi2: spi@a6000000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0xa6000000 0x1000>; + status = "disabled"; + }; + + apb { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges = <0xa0000000 0xa0000000 0x10000000 + 0xd0000000 0xd0000000 0x30000000>; + + i2c1: i2c@a7000000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,designware-i2c"; + reg = <0xa7000000 0x1000>; + status = "disabled"; + }; + + serial@a3000000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0xa3000000 0x1000>; + status = "disabled"; + }; + + serial@a4000000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0xa4000000 0x1000>; + status = "disabled"; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/spear3xx.dtsi b/arch/arm/boot/dts/spear3xx.dtsi new file mode 100644 index 0000000..924a6f6 --- /dev/null +++ b/arch/arm/boot/dts/spear3xx.dtsi @@ -0,0 +1,136 @@ +/* + * DTS file for all SPEAr3xx SoCs + * + * Copyright 2012 Viresh Kumar + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/include/ "skeleton.dtsi" + +/ { + interrupt-parent = <&vic>; + + cpus { + cpu@0 { + compatible = "arm,arm926ejs"; + }; + }; + + memory { + device_type = "memory"; + reg = <0 0x40000000>; + }; + + ahb { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges = <0xd0000000 0xd0000000 0x30000000>; + + vic: interrupt-controller@f1100000 { + compatible = "arm,pl190-vic"; + interrupt-controller; + reg = <0xf1100000 0x1000>; + #interrupt-cells = <1>; + }; + + gmac: eth@e0800000 { + compatible = "st,spear600-gmac"; + reg = <0xe0800000 0x8000>; + interrupts = <23 22>; + interrupt-names = "macirq", "eth_wake_irq"; + status = "disabled"; + }; + + smi: flash@fc000000 { + compatible = "st,spear600-smi"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0xfc000000 0x1000>; + interrupts = <9>; + status = "disabled"; + }; + + spi0: spi@d0100000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0xd0100000 0x1000>; + interrupts = <20>; + status = "disabled"; + }; + + ehci@e1800000 { + compatible = "st,spear600-ehci", "usb-ehci"; + reg = <0xe1800000 0x1000>; + interrupts = <26>; + status = "disabled"; + }; + + ohci@e1900000 { + compatible = "st,spear600-ohci", "usb-ohci"; + reg = <0xe1900000 0x1000>; + interrupts = <25>; + status = "disabled"; + }; + + ohci@e2100000 { + compatible = "st,spear600-ohci", "usb-ohci"; + reg = <0xe2100000 0x1000>; + interrupts = <27>; + status = "disabled"; + }; + + apb { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges = <0xd0000000 0xd0000000 0x30000000>; + + gpio0: gpio@fc980000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0xfc980000 0x1000>; + interrupts = <11>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + status = "disabled"; + }; + + i2c0: i2c@d0180000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,designware-i2c"; + reg = <0xd0180000 0x1000>; + interrupts = <21>; + status = "disabled"; + }; + + rtc@fc900000 { + compatible = "st,spear-rtc"; + reg = <0xfc900000 0x1000>; + interrupts = <10>; + status = "disabled"; + }; + + serial@d0000000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0xd0000000 0x1000>; + interrupts = <19>; + status = "disabled"; + }; + + wdt@fc880000 { + compatible = "arm,sp805", "arm,primecell"; + reg = <0xfc880000 0x1000>; + interrupts = <12>; + status = "disabled"; + }; + }; + }; +}; -- cgit v1.1 From 0b7ee71794b043de8a02d8887b69a57e4003106a Mon Sep 17 00:00:00 2001 From: Viresh Kumar Date: Mon, 26 Mar 2012 10:29:23 +0530 Subject: SPEAr: Add PL080 DMA support for 3xx and 6xx Both SPEAr3xx and SPEAr6xx families have one instance of ARM PL080 DMA controller. This patch adds in support for that. Signed-off-by: Viresh Kumar --- arch/arm/boot/dts/spear300-evb.dts | 4 ++++ arch/arm/boot/dts/spear310-evb.dts | 4 ++++ arch/arm/boot/dts/spear320-evb.dts | 4 ++++ arch/arm/boot/dts/spear3xx.dtsi | 8 ++++++++ arch/arm/boot/dts/spear600-evb.dts | 4 ++++ arch/arm/boot/dts/spear600.dtsi | 8 ++++++++ 6 files changed, 32 insertions(+) (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/dts/spear300-evb.dts b/arch/arm/boot/dts/spear300-evb.dts index f2ee9917..eaecc29 100644 --- a/arch/arm/boot/dts/spear300-evb.dts +++ b/arch/arm/boot/dts/spear300-evb.dts @@ -29,6 +29,10 @@ status = "okay"; }; + dma@fc400000 { + status = "okay"; + }; + fsmc: flash@94000000 { status = "okay"; }; diff --git a/arch/arm/boot/dts/spear310-evb.dts b/arch/arm/boot/dts/spear310-evb.dts index ec19d7b..c86af33 100644 --- a/arch/arm/boot/dts/spear310-evb.dts +++ b/arch/arm/boot/dts/spear310-evb.dts @@ -25,6 +25,10 @@ }; ahb { + dma@fc400000 { + status = "okay"; + }; + fsmc: flash@44000000 { status = "okay"; }; diff --git a/arch/arm/boot/dts/spear320-evb.dts b/arch/arm/boot/dts/spear320-evb.dts index 5681a97..d43de71 100644 --- a/arch/arm/boot/dts/spear320-evb.dts +++ b/arch/arm/boot/dts/spear320-evb.dts @@ -29,6 +29,10 @@ status = "okay"; }; + dma@fc400000 { + status = "okay"; + }; + fsmc: flash@4c000000 { status = "okay"; }; diff --git a/arch/arm/boot/dts/spear3xx.dtsi b/arch/arm/boot/dts/spear3xx.dtsi index 924a6f6..0ae7c8e 100644 --- a/arch/arm/boot/dts/spear3xx.dtsi +++ b/arch/arm/boot/dts/spear3xx.dtsi @@ -40,6 +40,14 @@ #interrupt-cells = <1>; }; + dma@fc400000 { + compatible = "arm,pl080", "arm,primecell"; + reg = <0xfc400000 0x1000>; + interrupt-parent = <&vic>; + interrupts = <8>; + status = "disabled"; + }; + gmac: eth@e0800000 { compatible = "st,spear600-gmac"; reg = <0xe0800000 0x8000>; diff --git a/arch/arm/boot/dts/spear600-evb.dts b/arch/arm/boot/dts/spear600-evb.dts index 636292e..790a7a8 100644 --- a/arch/arm/boot/dts/spear600-evb.dts +++ b/arch/arm/boot/dts/spear600-evb.dts @@ -24,6 +24,10 @@ }; ahb { + dma@fc400000 { + status = "okay"; + }; + gmac: ethernet@e0800000 { phy-mode = "gmii"; status = "okay"; diff --git a/arch/arm/boot/dts/spear600.dtsi b/arch/arm/boot/dts/spear600.dtsi index ebe0885..d777e3a 100644 --- a/arch/arm/boot/dts/spear600.dtsi +++ b/arch/arm/boot/dts/spear600.dtsi @@ -45,6 +45,14 @@ #interrupt-cells = <1>; }; + dma@fc400000 { + compatible = "arm,pl080", "arm,primecell"; + reg = <0xfc400000 0x1000>; + interrupt-parent = <&vic1>; + interrupts = <10>; + status = "disabled"; + }; + gmac: ethernet@e0800000 { compatible = "st,spear600-gmac"; reg = <0xe0800000 0x8000>; -- cgit v1.1 From e0373607855d033283b19014c8f14b90b3836924 Mon Sep 17 00:00:00 2001 From: Viresh Kumar Date: Thu, 29 Mar 2012 08:30:19 +0530 Subject: SPEAr3xx: Add pinctrl support for boards Signed-off-by: Viresh Kumar Acked-by: Linus Walleij Reviewed-by: Stephen Warren --- arch/arm/boot/dts/spear300-evb.dts | 38 ++++++++++++++++++++++++ arch/arm/boot/dts/spear300.dtsi | 5 ++++ arch/arm/boot/dts/spear310-evb.dts | 61 ++++++++++++++++++++++++++++++++++++++ arch/arm/boot/dts/spear310.dtsi | 5 ++++ arch/arm/boot/dts/spear320-evb.dts | 61 ++++++++++++++++++++++++++++++++++++++ arch/arm/boot/dts/spear320.dtsi | 7 ++++- 6 files changed, 176 insertions(+), 1 deletion(-) (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/dts/spear300-evb.dts b/arch/arm/boot/dts/spear300-evb.dts index eaecc29..402ca0d 100644 --- a/arch/arm/boot/dts/spear300-evb.dts +++ b/arch/arm/boot/dts/spear300-evb.dts @@ -25,6 +25,44 @@ }; ahb { + pinmux@99000000 { + st,pinmux-mode = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinmux { + i2c0 { + st,pins = "i2c0_grp"; + st,function = "i2c0"; + }; + ssp0 { + st,pins = "ssp0_grp"; + st,function = "ssp0"; + }; + mii0 { + st,pins = "mii0_grp"; + st,function = "mii0"; + }; + uart0 { + st,pins = "uart0_grp"; + st,function = "uart0"; + }; + clcd { + st,pins = "clcd_pfmode_grp"; + st,function = "clcd"; + }; + sdhci { + st,pins = "sdhci_4bit_grp"; + st,function = "sdhci"; + }; + gpio1 { + st,pins = "gpio1_4_to_7_grp", + "gpio1_0_to_3_grp"; + st,function = "gpio1"; + }; + }; + }; + clcd@60000000 { status = "okay"; }; diff --git a/arch/arm/boot/dts/spear300.dtsi b/arch/arm/boot/dts/spear300.dtsi index f9fcbf4..01c5e35 100644 --- a/arch/arm/boot/dts/spear300.dtsi +++ b/arch/arm/boot/dts/spear300.dtsi @@ -21,6 +21,11 @@ ranges = <0x60000000 0x60000000 0x50000000 0xd0000000 0xd0000000 0x30000000>; + pinmux@99000000 { + compatible = "st,spear300-pinmux"; + reg = <0x99000000 0x1000>; + }; + clcd@60000000 { compatible = "arm,clcd-pl110", "arm,primecell"; reg = <0x60000000 0x1000>; diff --git a/arch/arm/boot/dts/spear310-evb.dts b/arch/arm/boot/dts/spear310-evb.dts index c86af33..6d95317 100644 --- a/arch/arm/boot/dts/spear310-evb.dts +++ b/arch/arm/boot/dts/spear310-evb.dts @@ -25,6 +25,67 @@ }; ahb { + pinmux@b4000000 { + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinmux { + gpio0 { + st,pins = "gpio0_pin0_grp", + "gpio0_pin1_grp", + "gpio0_pin2_grp", + "gpio0_pin3_grp", + "gpio0_pin4_grp", + "gpio0_pin5_grp"; + st,function = "gpio0"; + }; + i2c0 { + st,pins = "i2c0_grp"; + st,function = "i2c0"; + }; + mii0 { + st,pins = "mii0_grp"; + st,function = "mii0"; + }; + ssp0 { + st,pins = "ssp0_grp"; + st,function = "ssp0"; + }; + uart0 { + st,pins = "uart0_grp"; + st,function = "uart0"; + }; + emi { + st,pins = "emi_cs_0_to_5_grp"; + st,function = "emi"; + }; + fsmc { + st,pins = "fsmc_grp"; + st,function = "fsmc"; + }; + uart1 { + st,pins = "uart1_grp"; + st,function = "uart1"; + }; + uart2 { + st,pins = "uart2_grp"; + st,function = "uart2"; + }; + uart3 { + st,pins = "uart3_grp"; + st,function = "uart3"; + }; + uart4 { + st,pins = "uart4_grp"; + st,function = "uart4"; + }; + uart5 { + st,pins = "uart5_grp"; + st,function = "uart5"; + }; + }; + }; + dma@fc400000 { status = "okay"; }; diff --git a/arch/arm/boot/dts/spear310.dtsi b/arch/arm/boot/dts/spear310.dtsi index dc7fa14..e47081c 100644 --- a/arch/arm/boot/dts/spear310.dtsi +++ b/arch/arm/boot/dts/spear310.dtsi @@ -22,6 +22,11 @@ 0xb0000000 0xb0000000 0x10000000 0xd0000000 0xd0000000 0x30000000>; + pinmux@b4000000 { + compatible = "st,spear310-pinmux"; + reg = <0xb4000000 0x1000>; + }; + fsmc: flash@44000000 { compatible = "st,spear600-fsmc-nand"; #address-cells = <1>; diff --git a/arch/arm/boot/dts/spear320-evb.dts b/arch/arm/boot/dts/spear320-evb.dts index d43de71..0c6463b 100644 --- a/arch/arm/boot/dts/spear320-evb.dts +++ b/arch/arm/boot/dts/spear320-evb.dts @@ -25,6 +25,67 @@ }; ahb { + pinmux@b3000000 { + st,pinmux-mode = <3>; + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinmux { + i2c0 { + st,pins = "i2c0_grp"; + st,function = "i2c0"; + }; + mii0 { + st,pins = "mii0_grp"; + st,function = "mii0"; + }; + ssp0 { + st,pins = "ssp0_grp"; + st,function = "ssp0"; + }; + uart0 { + st,pins = "uart0_grp"; + st,function = "uart0"; + }; + sdhci { + st,pins = "sdhci_cd_51_grp"; + st,function = "sdhci"; + }; + i2s { + st,pins = "i2s_grp"; + st,function = "i2s"; + }; + uart1 { + st,pins = "uart1_grp"; + st,function = "uart1"; + }; + uart2 { + st,pins = "uart2_grp"; + st,function = "uart2"; + }; + can0 { + st,pins = "can0_grp"; + st,function = "can0"; + }; + can1 { + st,pins = "can1_grp"; + st,function = "can1"; + }; + mii2 { + st,pins = "mii2_grp"; + st,function = "mii2"; + }; + pwm0_1 { + st,pins = "pwm0_1_pin_14_15_grp"; + st,function = "pwm0_1"; + }; + pwm2 { + st,pins = "pwm2_pin_13_grp"; + st,function = "pwm2"; + }; + }; + }; + clcd@90000000 { status = "okay"; }; diff --git a/arch/arm/boot/dts/spear320.dtsi b/arch/arm/boot/dts/spear320.dtsi index 9a0267a..5372ca3 100644 --- a/arch/arm/boot/dts/spear320.dtsi +++ b/arch/arm/boot/dts/spear320.dtsi @@ -18,9 +18,14 @@ #address-cells = <1>; #size-cells = <1>; compatible = "simple-bus"; - ranges = <0x40000000 0x40000000 0x70000000 + ranges = <0x40000000 0x40000000 0x80000000 0xd0000000 0xd0000000 0x30000000>; + pinmux@b3000000 { + compatible = "st,spear320-pinmux"; + reg = <0xb3000000 0x1000>; + }; + clcd@90000000 { compatible = "arm,clcd-pl110", "arm,primecell"; reg = <0x90000000 0x1000>; -- cgit v1.1 From fa599c333d3d66846545026b41bcf36d1350fe30 Mon Sep 17 00:00:00 2001 From: Viresh Kumar Date: Tue, 24 Apr 2012 11:15:39 +0530 Subject: ARM: SPEAr3xx: Correct keyboard data passed from DT keyboard data passed via DT is in wrong format. Fix it. Signed-off-by: Viresh Kumar Signed-off-by: Arnd Bergmann --- arch/arm/boot/dts/spear300-evb.dts | 162 ++++++++++++++++++------------------- 1 file changed, 81 insertions(+), 81 deletions(-) (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/dts/spear300-evb.dts b/arch/arm/boot/dts/spear300-evb.dts index eaecc29..6a79d69 100644 --- a/arch/arm/boot/dts/spear300-evb.dts +++ b/arch/arm/boot/dts/spear300-evb.dts @@ -81,87 +81,87 @@ }; kbd@a0000000 { - linux,keymap = < 0x00010000 - 0x00020100 - 0x00030200 - 0x00040300 - 0x00050400 - 0x00060500 - 0x00070600 - 0x00080700 - 0x00090800 - 0x000a0001 - 0x000c0101 - 0x000d0201 - 0x000e0301 - 0x000f0401 - 0x00100501 - 0x00110601 - 0x00120701 - 0x00130801 - 0x00140002 - 0x00150102 - 0x00160202 - 0x00170302 - 0x00180402 - 0x00190502 - 0x001a0602 - 0x001b0702 - 0x001c0802 - 0x001d0003 - 0x001e0103 - 0x001f0203 - 0x00200303 - 0x00210403 - 0x00220503 - 0x00230603 - 0x00240703 - 0x00250803 - 0x00260004 - 0x00270104 - 0x00280204 - 0x00290304 - 0x002a0404 - 0x002b0504 - 0x002c0604 - 0x002d0704 - 0x002e0804 - 0x002f0005 - 0x00300105 - 0x00310205 - 0x00320305 - 0x00330405 - 0x00340505 - 0x00350605 - 0x00360705 - 0x00370805 - 0x00380006 - 0x00390106 - 0x003a0206 - 0x003b0306 - 0x003c0406 - 0x003d0506 - 0x003e0606 - 0x003f0706 - 0x00400806 - 0x00410007 - 0x00420107 - 0x00430207 - 0x00440307 - 0x00450407 - 0x00460507 - 0x00470607 - 0x00480707 - 0x00490807 - 0x004a0008 - 0x004b0108 - 0x004c0208 - 0x004d0308 - 0x004e0408 - 0x004f0508 - 0x00500608 - 0x00510708 - 0x00520808 >; + linux,keymap = < 0x00000001 + 0x00010002 + 0x00020003 + 0x00030004 + 0x00040005 + 0x00050006 + 0x00060007 + 0x00070008 + 0x00080009 + 0x0100000a + 0x0101000c + 0x0102000d + 0x0103000e + 0x0104000f + 0x01050010 + 0x01060011 + 0x01070012 + 0x01080013 + 0x02000014 + 0x02010015 + 0x02020016 + 0x02030017 + 0x02040018 + 0x02050019 + 0x0206001a + 0x0207001b + 0x0208001c + 0x0300001d + 0x0301001e + 0x0302001f + 0x03030020 + 0x03040021 + 0x03050022 + 0x03060023 + 0x03070024 + 0x03080025 + 0x04000026 + 0x04010027 + 0x04020028 + 0x04030029 + 0x0404002a + 0x0405002b + 0x0406002c + 0x0407002d + 0x0408002e + 0x0500002f + 0x05010030 + 0x05020031 + 0x05030032 + 0x05040033 + 0x05050034 + 0x05060035 + 0x05070036 + 0x05080037 + 0x06000038 + 0x06010039 + 0x0602003a + 0x0603003b + 0x0604003c + 0x0605003d + 0x0606003e + 0x0607003f + 0x06080040 + 0x07000041 + 0x07010042 + 0x07020043 + 0x07030044 + 0x07040045 + 0x07050046 + 0x07060047 + 0x07070048 + 0x07080049 + 0x0800004a + 0x0801004b + 0x0802004c + 0x0803004d + 0x0804004e + 0x0805004f + 0x08060050 + 0x08070051 + 0x08080052 >; autorepeat; st,mode = <0>; status = "okay"; -- cgit v1.1 From 30551c0108e0d2fed48778a6bbd52843088bcb7b Mon Sep 17 00:00:00 2001 From: Viresh Kumar Date: Sat, 21 Apr 2012 13:15:37 +0530 Subject: SPEAr: Add DT bindings for SPEAr's timer All SPEAr SoC's use ST's Timer module. This patch adds device tree probing capability for that. Signed-off-by: Viresh Kumar Signed-off-by: Arnd Bergmann --- arch/arm/boot/dts/spear3xx.dtsi | 6 ++++++ arch/arm/boot/dts/spear600.dtsi | 6 ++++++ 2 files changed, 12 insertions(+) (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/dts/spear3xx.dtsi b/arch/arm/boot/dts/spear3xx.dtsi index 0ae7c8e..91072553 100644 --- a/arch/arm/boot/dts/spear3xx.dtsi +++ b/arch/arm/boot/dts/spear3xx.dtsi @@ -139,6 +139,12 @@ interrupts = <12>; status = "disabled"; }; + + timer@f0000000 { + compatible = "st,spear-timer"; + reg = <0xf0000000 0x400>; + interrupts = <2>; + }; }; }; }; diff --git a/arch/arm/boot/dts/spear600.dtsi b/arch/arm/boot/dts/spear600.dtsi index d777e3a..089f0a4 100644 --- a/arch/arm/boot/dts/spear600.dtsi +++ b/arch/arm/boot/dts/spear600.dtsi @@ -177,6 +177,12 @@ interrupts = <28>; status = "disabled"; }; + + timer@f0000000 { + compatible = "st,spear-timer"; + reg = <0xf0000000 0x400>; + interrupts = <16>; + }; }; }; }; -- cgit v1.1 From 30a0d03776ff2d7ee5ec72d515d8e3cc6d2f0c62 Mon Sep 17 00:00:00 2001 From: Viresh Kumar Date: Tue, 1 May 2012 18:09:22 +0530 Subject: SPEAr: Add SMI NOR partition info in dts files This patch adds NOR partitions in all SPEAr boards dts files. Signed-off-by: Viresh Kumar Acked-by: Arnd Bergmann Acked-by: Stefan Roese Signed-off-by: Arnd Bergmann --- arch/arm/boot/dts/spear300-evb.dts | 25 +++++++++++++++++++++++++ arch/arm/boot/dts/spear310-evb.dts | 20 ++++++++++++++++++-- arch/arm/boot/dts/spear320-evb.dts | 25 +++++++++++++++++++++++++ arch/arm/boot/dts/spear600-evb.dts | 29 +++++++++++++++++++++++++++++ 4 files changed, 97 insertions(+), 2 deletions(-) (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/dts/spear300-evb.dts b/arch/arm/boot/dts/spear300-evb.dts index 6a79d69..bf491a3 100644 --- a/arch/arm/boot/dts/spear300-evb.dts +++ b/arch/arm/boot/dts/spear300-evb.dts @@ -49,6 +49,31 @@ smi: flash@fc000000 { status = "okay"; + clock-rate=<50000000>; + + flash@f8000000 { + #address-cells = <1>; + #size-cells = <1>; + reg = <0xf8000000 0x800000>; + st,smi-fast-mode; + + partition@0 { + label = "xloader"; + reg = <0x0 0x10000>; + }; + partition@10000 { + label = "u-boot"; + reg = <0x10000 0x40000>; + }; + partition@50000 { + label = "linux"; + reg = <0x50000 0x2c0000>; + }; + partition@310000 { + label = "rootfs"; + reg = <0x310000 0x4f0000>; + }; + }; }; spi0: spi@d0100000 { diff --git a/arch/arm/boot/dts/spear310-evb.dts b/arch/arm/boot/dts/spear310-evb.dts index c86af33..f7ecb0c 100644 --- a/arch/arm/boot/dts/spear310-evb.dts +++ b/arch/arm/boot/dts/spear310-evb.dts @@ -42,11 +42,27 @@ clock-rate=<50000000>; flash@f8000000 { - label = "m25p64"; - reg = <0xf8000000 0x800000>; #address-cells = <1>; #size-cells = <1>; + reg = <0xf8000000 0x800000>; st,smi-fast-mode; + + partition@0 { + label = "xloader"; + reg = <0x0 0x10000>; + }; + partition@10000 { + label = "u-boot"; + reg = <0x10000 0x40000>; + }; + partition@50000 { + label = "linux"; + reg = <0x50000 0x2c0000>; + }; + partition@310000 { + label = "rootfs"; + reg = <0x310000 0x4f0000>; + }; }; }; diff --git a/arch/arm/boot/dts/spear320-evb.dts b/arch/arm/boot/dts/spear320-evb.dts index d43de71..8fb59d8 100644 --- a/arch/arm/boot/dts/spear320-evb.dts +++ b/arch/arm/boot/dts/spear320-evb.dts @@ -49,6 +49,31 @@ smi: flash@fc000000 { status = "okay"; + clock-rate=<50000000>; + + flash@f8000000 { + #address-cells = <1>; + #size-cells = <1>; + reg = <0xf8000000 0x800000>; + st,smi-fast-mode; + + partition@0 { + label = "xloader"; + reg = <0x0 0x10000>; + }; + partition@10000 { + label = "u-boot"; + reg = <0x10000 0x40000>; + }; + partition@50000 { + label = "linux"; + reg = <0x50000 0x2c0000>; + }; + partition@310000 { + label = "rootfs"; + reg = <0x310000 0x4f0000>; + }; + }; }; spi0: spi@d0100000 { diff --git a/arch/arm/boot/dts/spear600-evb.dts b/arch/arm/boot/dts/spear600-evb.dts index 790a7a8..1119c22 100644 --- a/arch/arm/boot/dts/spear600-evb.dts +++ b/arch/arm/boot/dts/spear600-evb.dts @@ -33,6 +33,35 @@ status = "okay"; }; + smi: flash@fc000000 { + status = "okay"; + clock-rate=<50000000>; + + flash@f8000000 { + #address-cells = <1>; + #size-cells = <1>; + reg = <0xf8000000 0x800000>; + st,smi-fast-mode; + + partition@0 { + label = "xloader"; + reg = <0x0 0x10000>; + }; + partition@10000 { + label = "u-boot"; + reg = <0x10000 0x40000>; + }; + partition@50000 { + label = "linux"; + reg = <0x50000 0x2c0000>; + }; + partition@310000 { + label = "rootfs"; + reg = <0x310000 0x4f0000>; + }; + }; + }; + apb { serial@d0000000 { status = "okay"; -- cgit v1.1 From 07658d9a659ba2e297cead3872ad4be8ec38b5b9 Mon Sep 17 00:00:00 2001 From: Viresh Kumar Date: Mon, 16 Apr 2012 23:57:51 +0530 Subject: SPEAr13xx: Add dts and dtsi files This patch adds machines/boards dts{i} files for SPEAr1310 and SPEAr1340. Both are based on ARM, Cortex A9 processor family. Signed-off-by: Viresh Kumar --- arch/arm/boot/dts/spear1310-evb.dts | 292 ++++++++++++++++++++++++++++++++++ arch/arm/boot/dts/spear1310.dtsi | 184 +++++++++++++++++++++ arch/arm/boot/dts/spear1340-evb.dts | 308 ++++++++++++++++++++++++++++++++++++ arch/arm/boot/dts/spear1340.dtsi | 56 +++++++ arch/arm/boot/dts/spear13xx.dtsi | 262 ++++++++++++++++++++++++++++++ 5 files changed, 1102 insertions(+) create mode 100644 arch/arm/boot/dts/spear1310-evb.dts create mode 100644 arch/arm/boot/dts/spear1310.dtsi create mode 100644 arch/arm/boot/dts/spear1340-evb.dts create mode 100644 arch/arm/boot/dts/spear1340.dtsi create mode 100644 arch/arm/boot/dts/spear13xx.dtsi (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/dts/spear1310-evb.dts b/arch/arm/boot/dts/spear1310-evb.dts new file mode 100644 index 0000000..8314e41 --- /dev/null +++ b/arch/arm/boot/dts/spear1310-evb.dts @@ -0,0 +1,292 @@ +/* + * DTS file for SPEAr1310 Evaluation Baord + * + * Copyright 2012 Viresh Kumar + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; +/include/ "spear1310.dtsi" + +/ { + model = "ST SPEAr1310 Evaluation Board"; + compatible = "st,spear1310-evb", "st,spear1310"; + #address-cells = <1>; + #size-cells = <1>; + + memory { + reg = <0 0x40000000>; + }; + + ahb { + pinmux@e0700000 { + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinmux { + i2c0-pmx { + st,pins = "i2c0_grp"; + st,function = "i2c0"; + }; + i2s1 { + st,pins = "i2s1_grp"; + st,function = "i2s1"; + }; + gpio { + st,pins = "arm_gpio_grp"; + st,function = "arm_gpio"; + }; + eth { + st,pins = "gmii_grp"; + st,function = "gmii"; + }; + ssp0 { + st,pins = "ssp0_grp"; + st,function = "ssp0"; + }; + kbd { + st,pins = "keyboard_6x6_grp"; + st,function = "keyboard"; + }; + sdhci { + st,pins = "sdhci_grp"; + st,function = "sdhci"; + }; + smi-pmx { + st,pins = "smi_2_chips_grp"; + st,function = "smi"; + }; + uart0 { + st,pins = "uart0_grp"; + st,function = "uart0"; + }; + rs485 { + st,pins = "rs485_0_1_tdm_0_1_grp"; + st,function = "rs485_0_1_tdm_0_1"; + }; + i2c1_2 { + st,pins = "i2c_1_2_grp"; + st,function = "i2c_1_2"; + }; + pci { + st,pins = "pcie0_grp","pcie1_grp", + "pcie2_grp"; + st,function = "pci"; + }; + smii { + st,pins = "smii_0_1_2_grp"; + st,function = "smii_0_1_2"; + }; + nand { + st,pins = "nand_8bit_grp", + "nand_16bit_grp"; + st,function = "nand"; + }; + }; + }; + + ahci@b1000000 { + status = "okay"; + }; + + cf@b2800000 { + status = "okay"; + }; + + dma@ea800000 { + status = "okay"; + }; + + dma@eb000000 { + status = "okay"; + }; + + fsmc: flash@b0000000 { + status = "okay"; + }; + + gmac0: eth@e2000000 { + status = "okay"; + }; + + sdhci@b3000000 { + status = "okay"; + }; + + smi: flash@ea000000 { + status = "okay"; + clock-rate=<50000000>; + + flash@e6000000 { + #address-cells = <1>; + #size-cells = <1>; + reg = <0xe6000000 0x800000>; + st,smi-fast-mode; + + partition@0 { + label = "xloader"; + reg = <0x0 0x10000>; + }; + partition@10000 { + label = "u-boot"; + reg = <0x10000 0x40000>; + }; + partition@50000 { + label = "linux"; + reg = <0x50000 0x2c0000>; + }; + partition@310000 { + label = "rootfs"; + reg = <0x310000 0x4f0000>; + }; + }; + }; + + spi0: spi@e0100000 { + status = "okay"; + }; + + ehci@e4800000 { + status = "okay"; + }; + + ehci@e5800000 { + status = "okay"; + }; + + ohci@e4000000 { + status = "okay"; + }; + + ohci@e5000000 { + status = "okay"; + }; + + apb { + adc@e0080000 { + status = "okay"; + }; + + gpio0: gpio@e0600000 { + status = "okay"; + }; + + gpio1: gpio@e0680000 { + status = "okay"; + }; + + i2c0: i2c@e0280000 { + status = "okay"; + }; + + i2c1: i2c@5cd00000 { + status = "okay"; + }; + + kbd@e0300000 { + linux,keymap = < 0x00000001 + 0x00010002 + 0x00020003 + 0x00030004 + 0x00040005 + 0x00050006 + 0x00060007 + 0x00070008 + 0x00080009 + 0x0100000a + 0x0101000c + 0x0102000d + 0x0103000e + 0x0104000f + 0x01050010 + 0x01060011 + 0x01070012 + 0x01080013 + 0x02000014 + 0x02010015 + 0x02020016 + 0x02030017 + 0x02040018 + 0x02050019 + 0x0206001a + 0x0207001b + 0x0208001c + 0x0300001d + 0x0301001e + 0x0302001f + 0x03030020 + 0x03040021 + 0x03050022 + 0x03060023 + 0x03070024 + 0x03080025 + 0x04000026 + 0x04010027 + 0x04020028 + 0x04030029 + 0x0404002a + 0x0405002b + 0x0406002c + 0x0407002d + 0x0408002e + 0x0500002f + 0x05010030 + 0x05020031 + 0x05030032 + 0x05040033 + 0x05050034 + 0x05060035 + 0x05070036 + 0x05080037 + 0x06000038 + 0x06010039 + 0x0602003a + 0x0603003b + 0x0604003c + 0x0605003d + 0x0606003e + 0x0607003f + 0x06080040 + 0x07000041 + 0x07010042 + 0x07020043 + 0x07030044 + 0x07040045 + 0x07050046 + 0x07060047 + 0x07070048 + 0x07080049 + 0x0800004a + 0x0801004b + 0x0802004c + 0x0803004d + 0x0804004e + 0x0805004f + 0x08060050 + 0x08070051 + 0x08080052 >; + autorepeat; + st,mode = <0>; + status = "okay"; + }; + + rtc@e0580000 { + status = "okay"; + }; + + serial@e0000000 { + status = "okay"; + }; + + wdt@ec800620 { + status = "okay"; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/spear1310.dtsi b/arch/arm/boot/dts/spear1310.dtsi new file mode 100644 index 0000000..9e61da4 --- /dev/null +++ b/arch/arm/boot/dts/spear1310.dtsi @@ -0,0 +1,184 @@ +/* + * DTS file for all SPEAr1310 SoCs + * + * Copyright 2012 Viresh Kumar + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/include/ "spear13xx.dtsi" + +/ { + compatible = "st,spear1310"; + + ahb { + ahci@b1000000 { + compatible = "snps,spear-ahci"; + reg = <0xb1000000 0x10000>; + interrupts = <0 68 0x4>; + status = "disabled"; + }; + + ahci@b1800000 { + compatible = "snps,spear-ahci"; + reg = <0xb1800000 0x10000>; + interrupts = <0 69 0x4>; + status = "disabled"; + }; + + ahci@b4000000 { + compatible = "snps,spear-ahci"; + reg = <0xb4000000 0x10000>; + interrupts = <0 70 0x4>; + status = "disabled"; + }; + + gmac1: eth@5c400000 { + compatible = "st,spear600-gmac"; + reg = <0x5c400000 0x8000>; + interrupts = <0 95 0x4>; + interrupt-names = "macirq"; + status = "disabled"; + }; + + gmac2: eth@5c500000 { + compatible = "st,spear600-gmac"; + reg = <0x5c500000 0x8000>; + interrupts = <0 96 0x4>; + interrupt-names = "macirq"; + status = "disabled"; + }; + + gmac3: eth@5c600000 { + compatible = "st,spear600-gmac"; + reg = <0x5c600000 0x8000>; + interrupts = <0 97 0x4>; + interrupt-names = "macirq"; + status = "disabled"; + }; + + gmac4: eth@5c700000 { + compatible = "st,spear600-gmac"; + reg = <0x5c700000 0x8000>; + interrupts = <0 98 0x4>; + interrupt-names = "macirq"; + status = "disabled"; + }; + + spi1: spi@5d400000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0x5d400000 0x1000>; + interrupts = <0 99 0x4>; + status = "disabled"; + }; + + apb { + i2c1: i2c@5cd00000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,designware-i2c"; + reg = <0x5cd00000 0x1000>; + interrupts = <0 87 0x4>; + status = "disabled"; + }; + + i2c2: i2c@5ce00000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,designware-i2c"; + reg = <0x5ce00000 0x1000>; + interrupts = <0 88 0x4>; + status = "disabled"; + }; + + i2c3: i2c@5cf00000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,designware-i2c"; + reg = <0x5cf00000 0x1000>; + interrupts = <0 89 0x4>; + status = "disabled"; + }; + + i2c4: i2c@5d000000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,designware-i2c"; + reg = <0x5d000000 0x1000>; + interrupts = <0 90 0x4>; + status = "disabled"; + }; + + i2c5: i2c@5d100000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,designware-i2c"; + reg = <0x5d100000 0x1000>; + interrupts = <0 91 0x4>; + status = "disabled"; + }; + + i2c6: i2c@5d200000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,designware-i2c"; + reg = <0x5d200000 0x1000>; + interrupts = <0 92 0x4>; + status = "disabled"; + }; + + i2c7: i2c@5d300000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,designware-i2c"; + reg = <0x5d300000 0x1000>; + interrupts = <0 93 0x4>; + status = "disabled"; + }; + + serial@5c800000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x5c800000 0x1000>; + interrupts = <0 82 0x4>; + status = "disabled"; + }; + + serial@5c900000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x5c900000 0x1000>; + interrupts = <0 83 0x4>; + status = "disabled"; + }; + + serial@5ca00000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x5ca00000 0x1000>; + interrupts = <0 84 0x4>; + status = "disabled"; + }; + + serial@5cb00000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x5cb00000 0x1000>; + interrupts = <0 85 0x4>; + status = "disabled"; + }; + + serial@5cc00000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x5cc00000 0x1000>; + interrupts = <0 86 0x4>; + status = "disabled"; + }; + + thermal@e07008c4 { + st,thermal-flags = <0x7000>; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/spear1340-evb.dts b/arch/arm/boot/dts/spear1340-evb.dts new file mode 100644 index 0000000..0d8472e --- /dev/null +++ b/arch/arm/boot/dts/spear1340-evb.dts @@ -0,0 +1,308 @@ +/* + * DTS file for SPEAr1340 Evaluation Baord + * + * Copyright 2012 Viresh Kumar + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; +/include/ "spear1340.dtsi" + +/ { + model = "ST SPEAr1340 Evaluation Board"; + compatible = "st,spear1340-evb", "st,spear1340"; + #address-cells = <1>; + #size-cells = <1>; + + memory { + reg = <0 0x40000000>; + }; + + ahb { + pinmux@e0700000 { + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinmux { + pads_as_gpio { + st,pins = "pads_as_gpio_grp"; + st,function = "pads_as_gpio"; + }; + fsmc { + st,pins = "fsmc_8bit_grp"; + st,function = "fsmc"; + }; + kbd { + st,pins = "keyboard_row_col_grp", + "keyboard_col5_grp"; + st,function = "keyboard"; + }; + uart0 { + st,pins = "uart0_grp", "uart0_enh_grp"; + st,function = "uart0"; + }; + i2c0-pmx { + st,pins = "i2c0_grp"; + st,function = "i2c0"; + }; + i2c1-pmx { + st,pins = "i2c1_grp"; + st,function = "i2c1"; + }; + spdif-in { + st,pins = "spdif_in_grp"; + st,function = "spdif_in"; + }; + spdif-out { + st,pins = "spdif_out_grp"; + st,function = "spdif_out"; + }; + ssp0 { + st,pins = "ssp0_grp", "ssp0_cs1_grp", + "ssp0_cs3_grp"; + st,function = "ssp0"; + }; + pwm { + st,pins = "pwm2_grp", "pwm3_grp"; + st,function = "pwm"; + }; + smi-pmx { + st,pins = "smi_grp"; + st,function = "smi"; + }; + i2s { + st,pins = "i2s_in_grp", "i2s_out_grp"; + st,function = "i2s"; + }; + gmac { + st,pins = "gmii_grp", "rgmii_grp"; + st,function = "gmac"; + }; + cam3 { + st,pins = "cam3_grp"; + st,function = "cam3"; + }; + cec0 { + st,pins = "cec0_grp"; + st,function = "cec0"; + }; + cec1 { + st,pins = "cec1_grp"; + st,function = "cec1"; + }; + sdhci { + st,pins = "sdhci_grp"; + st,function = "sdhci"; + }; + clcd { + st,pins = "clcd_grp"; + st,function = "clcd"; + }; + sata { + st,pins = "sata_grp"; + st,function = "sata"; + }; + }; + }; + + dma@ea800000 { + status = "okay"; + }; + + dma@eb000000 { + status = "okay"; + }; + + fsmc: flash@b0000000 { + status = "okay"; + }; + + gmac0: eth@e2000000 { + status = "okay"; + }; + + sdhci@b3000000 { + status = "okay"; + }; + + smi: flash@ea000000 { + status = "okay"; + clock-rate=<50000000>; + + flash@e6000000 { + #address-cells = <1>; + #size-cells = <1>; + reg = <0xe6000000 0x800000>; + st,smi-fast-mode; + + partition@0 { + label = "xloader"; + reg = <0x0 0x10000>; + }; + partition@10000 { + label = "u-boot"; + reg = <0x10000 0x40000>; + }; + partition@50000 { + label = "linux"; + reg = <0x50000 0x2c0000>; + }; + partition@310000 { + label = "rootfs"; + reg = <0x310000 0x4f0000>; + }; + }; + }; + + spi0: spi@e0100000 { + status = "okay"; + }; + + ehci@e4800000 { + status = "okay"; + }; + + ehci@e5800000 { + status = "okay"; + }; + + ohci@e4000000 { + status = "okay"; + }; + + ohci@e5000000 { + status = "okay"; + }; + + apb { + adc@e0080000 { + status = "okay"; + }; + + gpio0: gpio@e0600000 { + status = "okay"; + }; + + gpio1: gpio@e0680000 { + status = "okay"; + }; + + i2c0: i2c@e0280000 { + status = "okay"; + }; + + i2c1: i2c@b4000000 { + status = "okay"; + }; + + kbd@e0300000 { + linux,keymap = < 0x00000001 + 0x00010002 + 0x00020003 + 0x00030004 + 0x00040005 + 0x00050006 + 0x00060007 + 0x00070008 + 0x00080009 + 0x0100000a + 0x0101000c + 0x0102000d + 0x0103000e + 0x0104000f + 0x01050010 + 0x01060011 + 0x01070012 + 0x01080013 + 0x02000014 + 0x02010015 + 0x02020016 + 0x02030017 + 0x02040018 + 0x02050019 + 0x0206001a + 0x0207001b + 0x0208001c + 0x0300001d + 0x0301001e + 0x0302001f + 0x03030020 + 0x03040021 + 0x03050022 + 0x03060023 + 0x03070024 + 0x03080025 + 0x04000026 + 0x04010027 + 0x04020028 + 0x04030029 + 0x0404002a + 0x0405002b + 0x0406002c + 0x0407002d + 0x0408002e + 0x0500002f + 0x05010030 + 0x05020031 + 0x05030032 + 0x05040033 + 0x05050034 + 0x05060035 + 0x05070036 + 0x05080037 + 0x06000038 + 0x06010039 + 0x0602003a + 0x0603003b + 0x0604003c + 0x0605003d + 0x0606003e + 0x0607003f + 0x06080040 + 0x07000041 + 0x07010042 + 0x07020043 + 0x07030044 + 0x07040045 + 0x07050046 + 0x07060047 + 0x07070048 + 0x07080049 + 0x0800004a + 0x0801004b + 0x0802004c + 0x0803004d + 0x0804004e + 0x0805004f + 0x08060050 + 0x08070051 + 0x08080052 >; + autorepeat; + st,mode = <0>; + status = "okay"; + }; + + rtc@e0580000 { + status = "okay"; + }; + + serial@e0000000 { + status = "okay"; + }; + + serial@b4100000 { + status = "okay"; + }; + + wdt@ec800620 { + status = "okay"; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/spear1340.dtsi b/arch/arm/boot/dts/spear1340.dtsi new file mode 100644 index 0000000..a26fc47 --- /dev/null +++ b/arch/arm/boot/dts/spear1340.dtsi @@ -0,0 +1,56 @@ +/* + * DTS file for all SPEAr1340 SoCs + * + * Copyright 2012 Viresh Kumar + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/include/ "spear13xx.dtsi" + +/ { + compatible = "st,spear1340"; + + ahb { + ahci@b1000000 { + compatible = "snps,spear-ahci"; + reg = <0xb1000000 0x10000>; + interrupts = <0 72 0x4>; + status = "disabled"; + }; + + spi1: spi@5d400000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0x5d400000 0x1000>; + interrupts = <0 99 0x4>; + status = "disabled"; + }; + + apb { + i2c1: i2c@b4000000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,designware-i2c"; + reg = <0xb4000000 0x1000>; + interrupts = <0 104 0x4>; + status = "disabled"; + }; + + serial@b4100000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0xb4100000 0x1000>; + interrupts = <0 105 0x4>; + status = "disabled"; + }; + + thermal@e07008c4 { + st,thermal-flags = <0x2a00>; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/spear13xx.dtsi b/arch/arm/boot/dts/spear13xx.dtsi new file mode 100644 index 0000000..1f8e1e1 --- /dev/null +++ b/arch/arm/boot/dts/spear13xx.dtsi @@ -0,0 +1,262 @@ +/* + * DTS file for all SPEAr13xx SoCs + * + * Copyright 2012 Viresh Kumar + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/include/ "skeleton.dtsi" + +/ { + interrupt-parent = <&gic>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "arm,cortex-a9"; + reg = <0>; + next-level-cache = <&L2>; + }; + + cpu@1 { + compatible = "arm,cortex-a9"; + reg = <1>; + next-level-cache = <&L2>; + }; + }; + + gic: interrupt-controller@ec801000 { + compatible = "arm,cortex-a9-gic"; + interrupt-controller; + #interrupt-cells = <3>; + reg = < 0xec801000 0x1000 >, + < 0xec800100 0x0100 >; + }; + + pmu { + compatible = "arm,cortex-a9-pmu"; + interrupts = <0 8 0x04 + 0 9 0x04>; + }; + + L2: l2-cache { + compatible = "arm,pl310-cache"; + reg = <0xed000000 0x1000>; + cache-unified; + cache-level = <2>; + }; + + memory { + name = "memory"; + device_type = "memory"; + reg = <0 0x40000000>; + }; + + chosen { + bootargs = "console=ttyAMA0,115200"; + }; + + ahb { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges = <0x50000000 0x50000000 0x10000000 + 0xb0000000 0xb0000000 0x10000000 + 0xe0000000 0xe0000000 0x10000000>; + + sdhci@b3000000 { + compatible = "st,sdhci-spear"; + reg = <0xb3000000 0x100>; + interrupts = <0 28 0x4>; + status = "disabled"; + }; + + cf@b2800000 { + compatible = "arasan,cf-spear1340"; + reg = <0xb2800000 0x100>; + interrupts = <0 29 0x4>; + status = "disabled"; + }; + + dma@ea800000 { + compatible = "snps,dma-spear1340"; + reg = <0xea800000 0x1000>; + interrupts = <0 19 0x4>; + status = "disabled"; + }; + + dma@eb000000 { + compatible = "snps,dma-spear1340"; + reg = <0xeb000000 0x1000>; + interrupts = <0 59 0x4>; + status = "disabled"; + }; + + fsmc: flash@b0000000 { + compatible = "st,spear600-fsmc-nand"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0xb0000000 0x1000 /* FSMC Register */ + 0xb0800000 0x0010>; /* NAND Base */ + reg-names = "fsmc_regs", "nand_data"; + interrupts = <0 20 0x4 + 0 21 0x4 + 0 22 0x4 + 0 23 0x4>; + st,ale-off = <0x20000>; + st,cle-off = <0x10000>; + status = "disabled"; + }; + + gmac0: eth@e2000000 { + compatible = "st,spear600-gmac"; + reg = <0xe2000000 0x8000>; + interrupts = <0 23 0x4 + 0 24 0x4>; + interrupt-names = "macirq", "eth_wake_irq"; + status = "disabled"; + }; + + smi: flash@ea000000 { + compatible = "st,spear600-smi"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0xea000000 0x1000>; + interrupts = <0 30 0x4>; + status = "disabled"; + }; + + spi0: spi@e0100000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0xe0100000 0x1000>; + interrupts = <0 31 0x4>; + status = "disabled"; + }; + + ehci@e4800000 { + compatible = "st,spear600-ehci", "usb-ehci"; + reg = <0xe4800000 0x1000>; + interrupts = <0 64 0x4>; + status = "disabled"; + }; + + ehci@e5800000 { + compatible = "st,spear600-ehci", "usb-ehci"; + reg = <0xe5800000 0x1000>; + interrupts = <0 66 0x4>; + status = "disabled"; + }; + + ohci@e4000000 { + compatible = "st,spear600-ohci", "usb-ohci"; + reg = <0xe4000000 0x1000>; + interrupts = <0 65 0x4>; + status = "disabled"; + }; + + ohci@e5000000 { + compatible = "st,spear600-ohci", "usb-ohci"; + reg = <0xe5000000 0x1000>; + interrupts = <0 67 0x4>; + status = "disabled"; + }; + + apb { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges = <0x50000000 0x50000000 0x10000000 + 0xb0000000 0xb0000000 0x10000000 + 0xe0000000 0xe0000000 0x10000000>; + + gpio0: gpio@e0600000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0xe0600000 0x1000>; + interrupts = <0 24 0x4>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + status = "disabled"; + }; + + gpio1: gpio@e0680000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0xe0680000 0x1000>; + interrupts = <0 25 0x4>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + status = "disabled"; + }; + + kbd@e0300000 { + compatible = "st,spear300-kbd"; + reg = <0xe0300000 0x1000>; + status = "disabled"; + }; + + i2c0: i2c@e0280000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,designware-i2c"; + reg = <0xe0280000 0x1000>; + interrupts = <0 41 0x4>; + status = "disabled"; + }; + + rtc@e0580000 { + compatible = "st,spear-rtc"; + reg = <0xe0580000 0x1000>; + interrupts = <0 36 0x4>; + status = "disabled"; + }; + + serial@e0000000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0xe0000000 0x1000>; + interrupts = <0 36 0x4>; + status = "disabled"; + }; + + adc@e0080000 { + compatible = "st,spear600-adc"; + reg = <0xe0080000 0x1000>; + interrupts = <0 44 0x4>; + status = "disabled"; + }; + + timer@e0380000 { + compatible = "st,spear-timer"; + reg = <0xe0380000 0x400>; + interrupts = <0 37 0x4>; + }; + + timer@ec800600 { + compatible = "arm,cortex-a9-twd-timer"; + reg = <0xec800600 0x20>; + interrupts = <1 13 0x301>; + }; + + wdt@ec800620 { + compatible = "arm,cortex-a9-twd-wdt"; + reg = <0xec800620 0x20>; + status = "disabled"; + }; + + thermal@e07008c4 { + compatible = "st,thermal-spear1340"; + reg = <0xe07008c4 0x4>; + }; + }; + }; +}; -- cgit v1.1