From 387720c93812f1e702c20c667cb003a356e24a6c Mon Sep 17 00:00:00 2001 From: Marc Zyngier Date: Wed, 18 Jan 2017 09:27:28 +0000 Subject: ARM: DTS: Fix register map for virt-capable GIC Since everybody copied my own mistake from the DT binding example, let's address all the offenders in one swift go. Most of them got the CPU interface size wrong (4kB, while it should be 8kB), except for both keystone platforms which got the control interface wrong (4kB instead of 8kB). In a few cases where I knew for sure what implementation was used, I've added the "arm,gic-400" compatible string. I'm 99% sure that this is what everyone is using, but short of having the TRM for all the other SoCs, I've left them alone. Acked-by: Shawn Guo Acked-by: Tony Lindgren Acked-by: Santosh Shilimkar Acked-by: Krzysztof Kozlowski Acked-by: Maxime Ripard Acked-by: Antoine Tenart Acked-by: Arnd Bergmann Acked-by: Matthias Brugger Acked-by: Heiko Stuebner Reviewed-by: Javier Martinez Canillas Signed-off-by: Marc Zyngier Signed-off-by: Arnd Bergmann --- arch/arm/boot/dts/sun7i-a20.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm/boot/dts/sun7i-a20.dtsi') diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi index 34d613b..8e970c4 100644 --- a/arch/arm/boot/dts/sun7i-a20.dtsi +++ b/arch/arm/boot/dts/sun7i-a20.dtsi @@ -1613,9 +1613,9 @@ }; gic: interrupt-controller@01c81000 { - compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic"; + compatible = "arm,gic-400", "arm,cortex-a7-gic", "arm,cortex-a15-gic"; reg = <0x01c81000 0x1000>, - <0x01c82000 0x1000>, + <0x01c82000 0x2000>, <0x01c84000 0x2000>, <0x01c86000 0x2000>; interrupt-controller; -- cgit v1.1