From f74ba117dab86b35e15f8b5a8d913145f3e72ca1 Mon Sep 17 00:00:00 2001 From: Addy Ke Date: Thu, 4 Dec 2014 10:49:35 +0800 Subject: ARM: dts: rockchip: set dw_mmc max-freq 150Mhz All of mmc controllers include SDMMC, SDIO0, SDIO1, and EMMC on RK3288 are limited to 150Mhz. It was mainly caused by two reasons: - RK3288's IO pad(except DDR IO pad) is generic, which can only support the max of 150Mhz. - Mmc controller was designed at 150Mhz, and the pressure test by IC team was based on this freequency point. Signed-off-by: Addy Ke Reviewed-by: Doug Anderson Tested-by: Doug Anderson Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3288.dtsi | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/arm/boot/dts/rk3288.dtsi') diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi index fd19f007..3aad41d 100644 --- a/arch/arm/boot/dts/rk3288.dtsi +++ b/arch/arm/boot/dts/rk3288.dtsi @@ -151,6 +151,7 @@ sdmmc: dwmmc@ff0c0000 { compatible = "rockchip,rk3288-dw-mshc"; + clock-freq-min-max = <400000 150000000>; clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>; clock-names = "biu", "ciu"; fifo-depth = <0x100>; @@ -161,6 +162,7 @@ sdio0: dwmmc@ff0d0000 { compatible = "rockchip,rk3288-dw-mshc"; + clock-freq-min-max = <400000 150000000>; clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>; clock-names = "biu", "ciu"; fifo-depth = <0x100>; @@ -171,6 +173,7 @@ sdio1: dwmmc@ff0e0000 { compatible = "rockchip,rk3288-dw-mshc"; + clock-freq-min-max = <400000 150000000>; clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>; clock-names = "biu", "ciu"; fifo-depth = <0x100>; @@ -181,6 +184,7 @@ emmc: dwmmc@ff0f0000 { compatible = "rockchip,rk3288-dw-mshc"; + clock-freq-min-max = <400000 150000000>; clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>; clock-names = "biu", "ciu"; fifo-depth = <0x100>; -- cgit v1.1 From eecfe981cecd82791a72668a416727cb50935bdb Mon Sep 17 00:00:00 2001 From: Chris Zhong Date: Mon, 1 Dec 2014 16:52:19 +0800 Subject: ARM: dts: rockchip: add RK3288 suspend support add pmu sram node for suspend, add global_pwroff pinctrl. The pmu sram is used to store the resume code. global_pwroff is held low level at work, it would be pull to high when entering suspend. reference this in the board DTS file since some boards need it. Signed-off-by: Tony Xie Signed-off-by: Chris Zhong Reviewed-by: Doug Anderson Tested-by: Doug Anderson Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3288.dtsi | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) (limited to 'arch/arm/boot/dts/rk3288.dtsi') diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi index 3aad41d..2a878a3 100644 --- a/arch/arm/boot/dts/rk3288.dtsi +++ b/arch/arm/boot/dts/rk3288.dtsi @@ -506,6 +506,11 @@ }; }; + sram@ff720000 { + compatible = "rockchip,rk3288-pmu-sram", "mmio-sram"; + reg = <0xff720000 0x1000>; + }; + pmu: power-management@ff730000 { compatible = "rockchip,rk3288-pmu", "syscon"; reg = <0xff730000 0x100>; @@ -729,6 +734,24 @@ bias-disable; }; + sleep { + global_pwroff: global-pwroff { + rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>; + }; + + ddrio_pwroff: ddrio-pwroff { + rockchip,pins = <0 1 RK_FUNC_1 &pcfg_pull_none>; + }; + + ddr0_retention: ddr0-retention { + rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_up>; + }; + + ddr1_retention: ddr1-retention { + rockchip,pins = <0 3 RK_FUNC_1 &pcfg_pull_up>; + }; + }; + i2c0 { i2c0_xfer: i2c0-xfer { rockchip,pins = <0 15 RK_FUNC_1 &pcfg_pull_none>, -- cgit v1.1 From a29cb8c45d445a1ad812a0f7b3676926d08053f0 Mon Sep 17 00:00:00 2001 From: Daniel Kurtz Date: Fri, 10 Oct 2014 20:26:14 +0800 Subject: ARM: dts: rockchip: Add rk3288 vop and display-subsystem Add devicetree nodes for rk3288 VOP (Video Output Processors), and the top level display-subsystem root node. Later patches add endpoints (eDP, HDMI, LVDS, etc) that attach to the VOPs' output ports. Signed-off-by: Daniel Kurtz Signed-off-by: Mark yao Reviewed-by: Stephane Marchesin Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3288.dtsi | 39 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 39 insertions(+) (limited to 'arch/arm/boot/dts/rk3288.dtsi') diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi index 2a878a3..1d22238 100644 --- a/arch/arm/boot/dts/rk3288.dtsi +++ b/arch/arm/boot/dts/rk3288.dtsi @@ -149,6 +149,11 @@ clock-frequency = <24000000>; }; + display-subsystem { + compatible = "rockchip,display-subsystem"; + ports = <&vopl_out>, <&vopb_out>; + }; + sdmmc: dwmmc@ff0c0000 { compatible = "rockchip,rk3288-dw-mshc"; clock-freq-min-max = <400000 150000000>; @@ -566,6 +571,23 @@ status = "disabled"; }; + vopb: vop@ff930000 { + compatible = "rockchip,rk3288-vop"; + reg = <0xff930000 0x19c>; + interrupts = ; + clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>; + clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; + resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>; + reset-names = "axi", "ahb", "dclk"; + iommus = <&vopb_mmu>; + status = "disabled"; + + vopb_out: port { + #address-cells = <1>; + #size-cells = <0>; + }; + }; + vopb_mmu: iommu@ff930300 { compatible = "rockchip,iommu"; reg = <0xff930300 0x100>; @@ -575,6 +597,23 @@ status = "disabled"; }; + vopl: vop@ff940000 { + compatible = "rockchip,rk3288-vop"; + reg = <0xff940000 0x19c>; + interrupts = ; + clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>; + clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; + resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>; + reset-names = "axi", "ahb", "dclk"; + iommus = <&vopl_mmu>; + status = "disabled"; + + vopl_out: port { + #address-cells = <1>; + #size-cells = <0>; + }; + }; + vopl_mmu: iommu@ff940300 { compatible = "rockchip,iommu"; reg = <0xff940300 0x100>; -- cgit v1.1 From d5a1df48d051838ec83bcb56a6debc7e347ae1f9 Mon Sep 17 00:00:00 2001 From: Andy Yan Date: Tue, 4 Nov 2014 13:13:14 +0800 Subject: ARM: dts: rockchip: add rk3288 hdmi nodes Add an hdmi node, and also add hdmi endpoints to vopb and vopl output port nodes. Signed-off-by: Andy Yan Signed-off-by: Yakir Yang Reviewed-by: Daniel Kurtz Tested-by: Daniel Kurtz Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3288.dtsi | 37 +++++++++++++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) (limited to 'arch/arm/boot/dts/rk3288.dtsi') diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi index 1d22238..c7235fa 100644 --- a/arch/arm/boot/dts/rk3288.dtsi +++ b/arch/arm/boot/dts/rk3288.dtsi @@ -585,6 +585,11 @@ vopb_out: port { #address-cells = <1>; #size-cells = <0>; + + vopb_out_hdmi: endpoint@0 { + reg = <0>; + remote-endpoint = <&hdmi_in_vopb>; + }; }; }; @@ -611,6 +616,11 @@ vopl_out: port { #address-cells = <1>; #size-cells = <0>; + + vopl_out_hdmi: endpoint@0 { + reg = <0>; + remote-endpoint = <&hdmi_in_vopl>; + }; }; }; @@ -623,6 +633,33 @@ status = "disabled"; }; + hdmi: hdmi@ff980000 { + compatible = "rockchip,rk3288-dw-hdmi"; + reg = <0xff980000 0x20000>; + reg-io-width = <4>; + ddc-i2c-bus = <&i2c5>; + rockchip,grf = <&grf>; + interrupts = ; + clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>; + clock-names = "iahb", "isfr"; + status = "disabled"; + + ports { + hdmi_in: port { + #address-cells = <1>; + #size-cells = <0>; + hdmi_in_vopb: endpoint@0 { + reg = <0>; + remote-endpoint = <&vopb_out_hdmi>; + }; + hdmi_in_vopl: endpoint@1 { + reg = <1>; + remote-endpoint = <&vopl_out_hdmi>; + }; + }; + }; + }; + gic: interrupt-controller@ffc01000 { compatible = "arm,gic-400"; interrupt-controller; -- cgit v1.1 From e48cc181bf9abe0eeaaa884d3ec82e185a6285da Mon Sep 17 00:00:00 2001 From: Daniel Lezcano Date: Sun, 25 Jan 2015 10:42:59 +0100 Subject: ARM: dts: rockchip: Add rockchip timer node for rk3288 The rk3288 board uses the architected timers and these ones are shutdown when the cpu is powered down. There is a need of a broadcast timer in this case to ensure proper wakeup when the cpus are in sleep mode and a timer expires. Add the timer node for the broadcast timer. Signed-off-by: Daniel Lezcano Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3288.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'arch/arm/boot/dts/rk3288.dtsi') diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi index c7235fa..37847c1 100644 --- a/arch/arm/boot/dts/rk3288.dtsi +++ b/arch/arm/boot/dts/rk3288.dtsi @@ -149,6 +149,14 @@ clock-frequency = <24000000>; }; + timer: timer@ff810000 { + compatible = "rockchip,rk3288-timer"; + reg = <0xff810000 0x20>; + interrupts = ; + clocks = <&xin24m>, <&cru PCLK_TIMER>; + clock-names = "timer", "pclk"; + }; + display-subsystem { compatible = "rockchip,display-subsystem"; ports = <&vopl_out>, <&vopb_out>; -- cgit v1.1 From 39d05162a530b8e58119952dd60c7204e8512f0d Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Tue, 20 Jan 2015 21:12:16 +0100 Subject: ARM: dts: rockchip: add rk3288 watchdog clock Add the clock property for the watchdog on rk3288 socs. Signed-off-by: Heiko Stuebner Reviewed-by: Doug Anderson Tested-by: Doug Anderson --- arch/arm/boot/dts/rk3288.dtsi | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm/boot/dts/rk3288.dtsi') diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi index 37847c1..1e75a0f 100644 --- a/arch/arm/boot/dts/rk3288.dtsi +++ b/arch/arm/boot/dts/rk3288.dtsi @@ -560,6 +560,7 @@ wdt: watchdog@ff800000 { compatible = "rockchip,rk3288-wdt", "snps,dw-wdt"; reg = <0xff800000 0x100>; + clocks = <&cru PCLK_WDT>; interrupts = ; status = "disabled"; }; -- cgit v1.1 From c25d8cbcd840b2c9774a285ea728e72dd56aea2e Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Wed, 28 Jan 2015 17:23:10 +0100 Subject: ARM: dts: rockchip: move the hdmi ddc-i2c-bus property to the actual boards Currently the hdmi driver is using one of the soc i2c busses for ddc probing and while documentation always specifies i2c5 as hdmi-i2c it could very well be any other bus as well. Therefore this is a property of the board and should be specified there. Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3288.dtsi | 1 - 1 file changed, 1 deletion(-) (limited to 'arch/arm/boot/dts/rk3288.dtsi') diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi index 1e75a0f..1141850 100644 --- a/arch/arm/boot/dts/rk3288.dtsi +++ b/arch/arm/boot/dts/rk3288.dtsi @@ -646,7 +646,6 @@ compatible = "rockchip,rk3288-dw-hdmi"; reg = <0xff980000 0x20000>; reg-io-width = <4>; - ddc-i2c-bus = <&i2c5>; rockchip,grf = <&grf>; interrupts = ; clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>; -- cgit v1.1