From 6bcf60f8d557f15c85faf82ccbfc38cf986c45cc Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Mon, 14 Oct 2013 17:34:02 +0200 Subject: ARM: rockchip: add support for rk3188 and Radxa Rock board Basic devicetree files for the rk3188 SoC. Also provided is a board dts file for the upcoming Radxa Rock board using this SoC. Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3188.dtsi | 253 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 253 insertions(+) create mode 100644 arch/arm/boot/dts/rk3188.dtsi (limited to 'arch/arm/boot/dts/rk3188.dtsi') diff --git a/arch/arm/boot/dts/rk3188.dtsi b/arch/arm/boot/dts/rk3188.dtsi new file mode 100644 index 0000000..1a26b03 --- /dev/null +++ b/arch/arm/boot/dts/rk3188.dtsi @@ -0,0 +1,253 @@ +/* + * Copyright (c) 2013 MundoReader S.L. + * Author: Heiko Stuebner + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include "rk3xxx.dtsi" +#include "rk3188-clocks.dtsi" + +/ { + compatible = "rockchip,rk3188"; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + next-level-cache = <&L2>; + reg = <0x0>; + }; + cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + next-level-cache = <&L2>; + reg = <0x1>; + }; + cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + next-level-cache = <&L2>; + reg = <0x2>; + }; + cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + next-level-cache = <&L2>; + reg = <0x3>; + }; + }; + + soc { + global-timer@1013c200 { + interrupts = ; + }; + + local-timer@1013c600 { + interrupts = ; + }; + + pinctrl@20008000 { + compatible = "rockchip,rk3188-pinctrl"; + reg = <0x20008000 0xa0>, + <0x20008164 0x1a0>; + reg-names = "base", "pull"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + gpio0: gpio0@0x2000a000 { + compatible = "rockchip,rk3188-gpio-bank0"; + reg = <0x2000a000 0x100>, + <0x20004064 0x8>; + interrupts = ; + clocks = <&clk_gates8 9>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio1: gpio1@0x2003c000 { + compatible = "rockchip,gpio-bank"; + reg = <0x2003c000 0x100>; + interrupts = ; + clocks = <&clk_gates8 10>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio2: gpio2@2003e000 { + compatible = "rockchip,gpio-bank"; + reg = <0x2003e000 0x100>; + interrupts = ; + clocks = <&clk_gates8 11>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio3: gpio3@20080000 { + compatible = "rockchip,gpio-bank"; + reg = <0x20080000 0x100>; + interrupts = ; + clocks = <&clk_gates8 12>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + pcfg_pull_up: pcfg_pull_up { + bias-pull-up; + }; + + pcfg_pull_down: pcfg_pull_down { + bias-pull-down; + }; + + pcfg_pull_none: pcfg_pull_none { + bias-disable; + }; + + uart0 { + uart0_xfer: uart0-xfer { + rockchip,pins = , + ; + }; + + uart0_cts: uart0-cts { + rockchip,pins = ; + }; + + uart0_rts: uart0-rts { + rockchip,pins = ; + }; + }; + + uart1 { + uart1_xfer: uart1-xfer { + rockchip,pins = , + ; + }; + + uart1_cts: uart1-cts { + rockchip,pins = ; + }; + + uart1_rts: uart1-rts { + rockchip,pins = ; + }; + }; + + uart2 { + uart2_xfer: uart2-xfer { + rockchip,pins = , + ; + }; + /* no rts / cts for uart2 */ + }; + + uart3 { + uart3_xfer: uart3-xfer { + rockchip,pins = , + ; + }; + + uart3_cts: uart3-cts { + rockchip,pins = ; + }; + + uart3_rts: uart3-rts { + rockchip,pins = ; + }; + }; + + sd0 { + sd0_clk: sd0-clk { + rockchip,pins = ; + }; + + sd0_cmd: sd0-cmd { + rockchip,pins = ; + }; + + sd0_cd: sd0-cd { + rockchip,pins = ; + }; + + sd0_wp: sd0-wp { + rockchip,pins = ; + }; + + sd0_pwr: sd0-pwr { + rockchip,pins = ; + }; + + sd0_bus1: sd0-bus-width1 { + rockchip,pins = ; + }; + + sd0_bus4: sd0-bus-width4 { + rockchip,pins = , + , + , + ; + }; + }; + + sd1 { + sd1_clk: sd1-clk { + rockchip,pins = ; + }; + + sd1_cmd: sd1-cmd { + rockchip,pins = ; + }; + + sd1_cd: sd1-cd { + rockchip,pins = ; + }; + + sd1_wp: sd1-wp { + rockchip,pins = ; + }; + + sd1_bus1: sd1-bus-width1 { + rockchip,pins = ; + }; + + sd1_bus4: sd1-bus-width4 { + rockchip,pins = , + , + , + ; + }; + }; + }; + }; +}; -- cgit v1.1