From e16415313c9b00b1adc313e85c2c8a81febe0b98 Mon Sep 17 00:00:00 2001 From: Shawn Guo Date: Wed, 20 Feb 2013 10:32:52 +0800 Subject: pinctrl: imx: move hard-coding data into device tree Currently, all imx pinctrl drivers maintain a big array of struct imx_pin_reg which hard-codes data like register offset and mux mode setting for each pin function. Every time a new imx SoC support is added, we need to add such a big mount of data. With moving to single kernel build, it's only matter of time to be blamed on memory consuming. With DTC pre-processor support in place, the patch moves all these data into device tree by redefining the PIN_FUNC_ID in imxXX-pinfunc.h and changing the PIN_FUNC_ID parsing code a little bit. The pin id gets re-numbered based on mux register offset, or config register offset if the pin has no mux register, so that kernel can identify the pin id from register offsets provided by device tree. As a bonus point of the change, those arbitrary magic numbers standing for particular PIN_FUNC_ID in device tree sources are now replaced by macros to improve the readability of dts files. Signed-off-by: Shawn Guo Acked-by: Dong Aisheng Acked-by: Linus Walleij --- arch/arm/boot/dts/imx6q-sabreauto.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm/boot/dts/imx6q-sabreauto.dts') diff --git a/arch/arm/boot/dts/imx6q-sabreauto.dts b/arch/arm/boot/dts/imx6q-sabreauto.dts index 42c0a87..5e273ec 100644 --- a/arch/arm/boot/dts/imx6q-sabreauto.dts +++ b/arch/arm/boot/dts/imx6q-sabreauto.dts @@ -29,8 +29,8 @@ hog { pinctrl_hog: hoggrp { fsl,pins = < - 1376 0x80000000 /* MX6Q_PAD_NANDF_CS2__GPIO_6_15 */ - 13 0x80000000 /* MX6Q_PAD_SD2_DAT2__GPIO_1_13 */ + MX6Q_PAD_NANDF_CS2__GPIO6_IO15 0x80000000 + MX6Q_PAD_SD2_DAT2__GPIO1_IO13 0x80000000 >; }; }; -- cgit v1.1