From ff66a3c86e004ce83f7c6e5f459d65c87f9d02b6 Mon Sep 17 00:00:00 2001 From: Minal Shah Date: Mon, 19 May 2014 14:45:47 +0530 Subject: ARM: dts: dra7: add support for parallel NAND flash DRA7xx platform has in-build GPMC and ELM h/w engines which can be used for accessing externel NAND flash device. This patch: - adds generic DT binding in dra7.dtsi for enabling GPMC and ELM h/w engines - adds DT binding for Micron NAND Flash (MT29F2G16AADWP) present on dra7-evm *Important* On DRA7 EVM, GPMC_WPN and NAND_BOOTn are controlled by DIP switch So following board settings are required for NAND device detection: SW5.9 (GPMC_WPN) = LOW SW5.1 (NAND_BOOTn) = HIGH Signed-off-by: Minal Shah Signed-off-by: Pekon Gupta Reviewed-by: Javier Martinez Canillas Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/dra7.dtsi | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) (limited to 'arch/arm/boot/dts/dra7.dtsi') diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi index 6af8b08..a8a0cee 100644 --- a/arch/arm/boot/dts/dra7.dtsi +++ b/arch/arm/boot/dts/dra7.dtsi @@ -964,6 +964,26 @@ dr_mode = "otg"; }; }; + + elm: elm@48078000 { + compatible = "ti,am3352-elm"; + reg = <0x48078000 0xfc0>; /* device IO registers */ + interrupts = ; + ti,hwmods = "elm"; + status = "disabled"; + }; + + gpmc: gpmc@50000000 { + compatible = "ti,am3352-gpmc"; + ti,hwmods = "gpmc"; + reg = <0x50000000 0x37c>; /* device IO registers */ + interrupts = ; + gpmc,num-cs = <8>; + gpmc,num-waitpins = <2>; + #address-cells = <2>; + #size-cells = <1>; + status = "disabled"; + }; }; }; -- cgit v1.1