From e2a93ecc7fc469dab52323c11a2d8ceaa62aac7b Mon Sep 17 00:00:00 2001 From: Lennert Buytenhek Date: Mon, 29 Nov 2010 10:06:57 +0100 Subject: ARM: Use genirq definitions from kernel/irq/Kconfig. Signed-off-by: Lennert Buytenhek --- arch/arm/Kconfig | 18 ++---------------- 1 file changed, 2 insertions(+), 16 deletions(-) (limited to 'arch/arm/Kconfig') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index e2f8011..99829a2 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -26,6 +26,8 @@ config ARM select HAVE_REGS_AND_STACK_ACCESS_API select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V7)) select HAVE_C_RECORDMCOUNT + select HAVE_GENERIC_HARDIRQS + select HAVE_SPARSE_IRQ help The ARM series is a line of low-power-consumption RISC chip designs licensed by ARM Ltd and targeted at embedded applications and @@ -97,10 +99,6 @@ config MCA (and especially the web page given there) before attempting to build an MCA bus kernel. -config GENERIC_HARDIRQS - bool - default y - config STACKTRACE_SUPPORT bool default y @@ -180,9 +178,6 @@ config FIQ config ARCH_MTD_XIP bool -config GENERIC_HARDIRQS_NO__DO_IRQ - def_bool y - config ARM_L1_CACHE_SHIFT_6 bool help @@ -1452,15 +1447,6 @@ config HW_PERF_EVENTS Enable hardware performance counter support for perf events. If disabled, perf events will use software events only. -config SPARSE_IRQ - def_bool n - help - This enables support for sparse irqs. This is useful in general - as most CPUs have a fairly sparse array of IRQ vectors, which - the irq_desc then maps directly on to. Systems with a high - number of off-chip IRQs will want to treat this as - experimental until they have been independently verified. - source "mm/Kconfig" config FORCE_MAX_ZONEORDER -- cgit v1.1