From daeeb438c052e3763617c636943e07a8f3684e9e Mon Sep 17 00:00:00 2001 From: Eugeniy Paltsev Date: Fri, 25 Aug 2017 20:39:14 +0300 Subject: ARC: clk: introduce HSDK pll driver HSDK board manages its clocks using various PLLs. These PLL have same dividers and corresponding control registers mapped to different addresses. So we add one common driver for such PLLs. Each PLL on HSDK board consists of three dividers: IDIV, FBDIV and ODIV. Output clock value is managed using these dividers. We add pre-defined tables with supported rate values and appropriate configurations of IDIV, FBDIV and ODIV for each value. As of today we add support for PLLs that generate clock for the HSDK arc cpus, system, ddr, AXI tunnel and hdmi. By this patch we add support for several plls (arc cpus pll and others), so we had to use two different init types: CLK_OF_DECLARE for arc cpus pll and regular probing for others plls. Signed-off-by: Eugeniy Paltsev Reviewed-by: Vineet Gupta Signed-off-by: Stephen Boyd --- MAINTAINERS | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'MAINTAINERS') diff --git a/MAINTAINERS b/MAINTAINERS index c571fcf..cf704c7d 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -12738,6 +12738,12 @@ F: drivers/clocksource/arc_timer.c F: drivers/tty/serial/arc_uart.c T: git git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc.git +SYNOPSYS ARC HSDK SDP pll clock driver +M: Eugeniy Paltsev +S: Supported +F: drivers/clk/clk-hsdk-pll.c +F: Documentation/devicetree/bindings/clock/snps,hsdk-pll-clock.txt + SYNOPSYS ARC SDP platform support M: Alexey Brodkin S: Supported -- cgit v1.1