From 3414666d34bb50f91965d16eab98a5fd7c8af08c Mon Sep 17 00:00:00 2001 From: Gabriel FERNANDEZ Date: Tue, 15 Jul 2014 17:20:21 +0200 Subject: clk: st: Adds Flexgen clock binding A Flexgen structure is composed by: - a clock cross bar (represented by a mux element) - a pre and final dividers (represented by a divider and gate elements) Signed-off-by: Gabriel Fernandez Acked-by: Peter Griffin Signed-off-by: Mike Turquette --- Documentation/devicetree/bindings/clock/st/st,clkgen.txt | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'Documentation/devicetree/bindings/clock/st/st,clkgen.txt') diff --git a/Documentation/devicetree/bindings/clock/st/st,clkgen.txt b/Documentation/devicetree/bindings/clock/st/st,clkgen.txt index 427bad8..78978f1 100644 --- a/Documentation/devicetree/bindings/clock/st/st,clkgen.txt +++ b/Documentation/devicetree/bindings/clock/st/st,clkgen.txt @@ -32,6 +32,10 @@ address is common of all subnode. vcc_node { ... }; + + flexgen_node { + ... + }; ... }; @@ -45,6 +49,7 @@ Each subnode should use the binding discribe in [2]..[7] [5] Documentation/devicetree/bindings/clock/st,clkgen-prediv.txt [6] Documentation/devicetree/bindings/clock/st,vcc.txt [7] Documentation/devicetree/bindings/clock/st,quadfs.txt +[8] Documentation/devicetree/bindings/clock/st,flexgen.txt Required properties: -- cgit v1.1