From ba0f00b9fcb02b10cc9929fec660f86d1af6a41a Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Fri, 16 Nov 2007 14:54:46 +0000 Subject: [MIPS] Malta: Enable tickless and highres timers. Most Malta use an FPGA CPU card which rarely is good for more than 40MHz. So the performance penalta of the regular timer interrupt, especially for the VSMP kernel model is significant, even at a mere 100Hz. Signed-off-by: Ralf Baechle --- arch/mips/configs/malta_defconfig | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/mips/configs/malta_defconfig b/arch/mips/configs/malta_defconfig index fbd2d80..4b7e43c 100644 --- a/arch/mips/configs/malta_defconfig +++ b/arch/mips/configs/malta_defconfig @@ -49,10 +49,13 @@ CONFIG_RWSEM_GENERIC_SPINLOCK=y CONFIG_GENERIC_FIND_NEXT_BIT=y CONFIG_GENERIC_HWEIGHT=y CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_GENERIC_CLOCKEVENTS=y CONFIG_GENERIC_TIME=y +CONFIG_GENERIC_CMOS_UPDATE=y CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y # CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ is not set CONFIG_ARCH_MAY_HAVE_PC_FDC=y +CONFIG_CEVT_R4K=y CONFIG_DMA_NONCOHERENT=y CONFIG_DMA_NEED_PCI_MAP_STATE=y CONFIG_EARLY_PRINTK=y @@ -76,6 +79,10 @@ CONFIG_MIPS_L1_CACHE_SHIFT=5 # # CPU selection # +CONFIG_TICK_ONESHOT=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y # CONFIG_CPU_LOONGSON2 is not set # CONFIG_CPU_MIPS32_R1 is not set CONFIG_CPU_MIPS32_R2=y @@ -253,6 +260,7 @@ CONFIG_HW_HAS_PCI=y CONFIG_PCI=y # CONFIG_ARCH_SUPPORTS_MSI is not set CONFIG_MMU=y +CONFIG_I8253=y # # PCCARD (PCMCIA/CardBus) support -- cgit v1.1