From b704882e70d87d7f56db5ff17e2253f3fa90e4f3 Mon Sep 17 00:00:00 2001 From: Tony Luck Date: Thu, 20 Nov 2008 13:27:12 -0800 Subject: [IA64] Rationalize kernel mode alignment checking Itanium processors can handle some misaligned data accesses. They also provide a mode where all such accesses are forced to trap. The kernel was schizophrenic about use of this mode: * Base kernel code ran in permissive mode where the only traps generated were from those cases that the h/w could not handle. * Interrupt, syscall and trap code ran in strict mode where all unaligned accesses caused traps to the 0x5a00 unaligned reference vector. Use strict alignment checking throughout the kernel, but make sure that we continue to let user mode use more relaxed mode as the default. Signed-off-by: Tony Luck --- arch/ia64/kernel/entry.S | 1 + arch/ia64/kernel/head.S | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/ia64/kernel/entry.S b/arch/ia64/kernel/entry.S index 7ef0c59..d435f4a 100644 --- a/arch/ia64/kernel/entry.S +++ b/arch/ia64/kernel/entry.S @@ -499,6 +499,7 @@ GLOBAL_ENTRY(prefetch_stack) END(prefetch_stack) GLOBAL_ENTRY(kernel_execve) + rum psr.ac mov r15=__NR_execve // put syscall number in place break __BREAK_SYSCALL br.ret.sptk.many rp diff --git a/arch/ia64/kernel/head.S b/arch/ia64/kernel/head.S index 66e491d..59301c4 100644 --- a/arch/ia64/kernel/head.S +++ b/arch/ia64/kernel/head.S @@ -260,7 +260,7 @@ start_ap: * Switch into virtual mode: */ movl r16=(IA64_PSR_IT|IA64_PSR_IC|IA64_PSR_DT|IA64_PSR_RT|IA64_PSR_DFH|IA64_PSR_BN \ - |IA64_PSR_DI) + |IA64_PSR_DI|IA64_PSR_AC) ;; mov cr.ipsr=r16 movl r17=1f -- cgit v1.1