From dddfd098523953b65706fb3647cb33a8fbb6d904 Mon Sep 17 00:00:00 2001 From: Javier Martinez Canillas Date: Thu, 15 Jun 2017 20:49:21 +0200 Subject: dt-bindings: mfd: Add retu/tahvo ASIC chips bindings There are Device Tree source files defining a device node for the retu/tahvo I2C chip, but there isn't a DT binding document for it. Signed-off-by: Javier Martinez Canillas Acked-by: Rob Herring Acked-by: Aaro Koskinen Acked-by: Tony Lindgren Signed-off-by: Lee Jones --- Documentation/devicetree/bindings/mfd/retu.txt | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) create mode 100644 Documentation/devicetree/bindings/mfd/retu.txt diff --git a/Documentation/devicetree/bindings/mfd/retu.txt b/Documentation/devicetree/bindings/mfd/retu.txt new file mode 100644 index 0000000..8762423 --- /dev/null +++ b/Documentation/devicetree/bindings/mfd/retu.txt @@ -0,0 +1,25 @@ +* Device tree bindings for Nokia Retu and Tahvo multi-function device + +Retu and Tahvo are a multi-function devices found on Nokia Internet +Tablets (770, N800 and N810). The Retu chip provides watchdog timer +and power button control functionalities while Tahvo chip provides +USB transceiver functionality. + +Required properties: +- compatible: "nokia,retu" or "nokia,tahvo" +- reg: Specifies the CBUS slave address of the ASIC chip +- interrupts: The interrupt line the device is connected to +- interrupt-parent: The parent interrupt controller + +Example: + +cbus0 { + compatible = "i2c-cbus-gpio"; + ... + retu: retu@1 { + compatible = "nokia,retu"; + interrupt-parent = <&gpio4>; + interrupts = <12 IRQ_TYPE_EDGE_RISING>; + reg = <0x1>; + }; +}; -- cgit v1.1 From 408bc03bb1d5aea34dd444fd6f1f566a5303793d Mon Sep 17 00:00:00 2001 From: Javier Martinez Canillas Date: Thu, 15 Jun 2017 20:49:22 +0200 Subject: mfd: retu: Drop -mfd suffix from I2C device ID name It's not correct to encode the subsystem in the I2C device name, so drop the -mfd suffix. To maintain bisect-ability, change driver and platform code / DTS users in the same patch. Suggested-by: Lee Jones Signed-off-by: Javier Martinez Canillas Acked-by: Rob Herring Acked-by: Aaro Koskinen Acked-by: Tony Lindgren Reviewed-by: Wolfram Sang Signed-off-by: Lee Jones --- arch/arm/boot/dts/omap2420-n8x0-common.dtsi | 4 ++-- arch/arm/mach-omap1/board-nokia770.c | 4 ++-- drivers/mfd/retu-mfd.c | 4 ++-- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm/boot/dts/omap2420-n8x0-common.dtsi b/arch/arm/boot/dts/omap2420-n8x0-common.dtsi index 7e5ffc5..1b06430 100644 --- a/arch/arm/boot/dts/omap2420-n8x0-common.dtsi +++ b/arch/arm/boot/dts/omap2420-n8x0-common.dtsi @@ -15,8 +15,8 @@ >; #address-cells = <1>; #size-cells = <0>; - retu_mfd: retu@1 { - compatible = "retu-mfd"; + retu: retu@1 { + compatible = "retu"; interrupt-parent = <&gpio4>; interrupts = <12 IRQ_TYPE_EDGE_RISING>; reg = <0x1>; diff --git a/arch/arm/mach-omap1/board-nokia770.c b/arch/arm/mach-omap1/board-nokia770.c index ee8d9f5..06243c0 100644 --- a/arch/arm/mach-omap1/board-nokia770.c +++ b/arch/arm/mach-omap1/board-nokia770.c @@ -233,10 +233,10 @@ static struct platform_device nokia770_cbus_device = { static struct i2c_board_info nokia770_i2c_board_info_2[] __initdata = { { - I2C_BOARD_INFO("retu-mfd", 0x01), + I2C_BOARD_INFO("retu", 0x01), }, { - I2C_BOARD_INFO("tahvo-mfd", 0x02), + I2C_BOARD_INFO("tahvo", 0x02), }, }; diff --git a/drivers/mfd/retu-mfd.c b/drivers/mfd/retu-mfd.c index d4c114a..53e1d38 100644 --- a/drivers/mfd/retu-mfd.c +++ b/drivers/mfd/retu-mfd.c @@ -302,8 +302,8 @@ static int retu_remove(struct i2c_client *i2c) } static const struct i2c_device_id retu_id[] = { - { "retu-mfd", 0 }, - { "tahvo-mfd", 0 }, + { "retu", 0 }, + { "tahvo", 0 }, { } }; MODULE_DEVICE_TABLE(i2c, retu_id); -- cgit v1.1 From c05581d88578a0870c0d246bc25bb3e7daa6d951 Mon Sep 17 00:00:00 2001 From: Javier Martinez Canillas Date: Thu, 15 Jun 2017 20:49:24 +0200 Subject: ARM: dts: n8x0: Add vendor prefix to retu node The retu device node doesn't have a vendor prefix in its compatible string, fix it by adding one. Signed-off-by: Javier Martinez Canillas Acked-by: Rob Herring Acked-by: Aaro Koskinen Acked-by: Tony Lindgren Reviewed-by: Wolfram Sang Signed-off-by: Lee Jones --- arch/arm/boot/dts/omap2420-n8x0-common.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/omap2420-n8x0-common.dtsi b/arch/arm/boot/dts/omap2420-n8x0-common.dtsi index 1b06430..9188623 100644 --- a/arch/arm/boot/dts/omap2420-n8x0-common.dtsi +++ b/arch/arm/boot/dts/omap2420-n8x0-common.dtsi @@ -16,7 +16,7 @@ #address-cells = <1>; #size-cells = <0>; retu: retu@1 { - compatible = "retu"; + compatible = "nokia,retu"; interrupt-parent = <&gpio4>; interrupts = <12 IRQ_TYPE_EDGE_RISING>; reg = <0x1>; -- cgit v1.1 From 46c20bdfd1a47c3ef3c0d31afdc7ac61a16baed1 Mon Sep 17 00:00:00 2001 From: Javier Martinez Canillas Date: Thu, 15 Jun 2017 20:49:23 +0200 Subject: mfd: retu: Add OF device ID table The driver doesn't have a struct of_device_id table but supported devices are registered via Device Trees. This is working on the assumption that a I2C device registered via OF will always match a legacy I2C device ID and that the MODALIAS reported will always be of the form i2c:. But this could change in the future so the correct approach is to have a OF device ID table if the devices are registered via OF. Signed-off-by: Javier Martinez Canillas Acked-by: Rob Herring Acked-by: Aaro Koskinen Acked-by: Tony Lindgren Reviewed-by: Wolfram Sang Signed-off-by: Lee Jones --- drivers/mfd/retu-mfd.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/mfd/retu-mfd.c b/drivers/mfd/retu-mfd.c index 53e1d38..e7d27b7 100644 --- a/drivers/mfd/retu-mfd.c +++ b/drivers/mfd/retu-mfd.c @@ -308,9 +308,17 @@ static const struct i2c_device_id retu_id[] = { }; MODULE_DEVICE_TABLE(i2c, retu_id); +static const struct of_device_id retu_of_match[] = { + { .compatible = "nokia,retu" }, + { .compatible = "nokia,tahvo" }, + { } +}; +MODULE_DEVICE_TABLE(of, retu_of_match); + static struct i2c_driver retu_driver = { .driver = { .name = "retu-mfd", + .of_match_table = retu_of_match, }, .probe = retu_probe, .remove = retu_remove, -- cgit v1.1 From 7da48df734f227861032841255bb2aefe0802270 Mon Sep 17 00:00:00 2001 From: Javier Martinez Canillas Date: Thu, 15 Jun 2017 20:49:25 +0200 Subject: i2c: i2c-cbus-gpio: Add vendor prefix to retu node in example The example contains a device node for a retu device, but its compatible string doesn't have a vendor prefix. While being there, drop the -mfd suffix since isn't correct. Signed-off-by: Javier Martinez Canillas Acked-by: Rob Herring Acked-by: Aaro Koskinen Acked-by: Tony Lindgren Reviewed-by: Wolfram Sang Signed-off-by: Lee Jones --- Documentation/devicetree/bindings/i2c/i2c-cbus-gpio.txt | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/i2c/i2c-cbus-gpio.txt b/Documentation/devicetree/bindings/i2c/i2c-cbus-gpio.txt index 8ce9cd2..c143948 100644 --- a/Documentation/devicetree/bindings/i2c/i2c-cbus-gpio.txt +++ b/Documentation/devicetree/bindings/i2c/i2c-cbus-gpio.txt @@ -20,8 +20,8 @@ i2c@0 { #address-cells = <1>; #size-cells = <0>; - retu-mfd: retu@1 { - compatible = "retu-mfd"; + retu: retu@1 { + compatible = "nokia,retu"; reg = <0x1>; }; }; -- cgit v1.1 From 8002c4e73e00a8d22b5e1301b00fc83bf0537d2d Mon Sep 17 00:00:00 2001 From: Javier Martinez Canillas Date: Thu, 15 Jun 2017 20:49:26 +0200 Subject: dt-bindings: mfd: Add TI tps6105x chip bindings There are Device Tree source files defining a device node for the tps61050/61052 I2C chip but there isn't a binding document for it. Signed-off-by: Javier Martinez Canillas Acked-by: Rob Herring Acked-by: Tony Lindgren Signed-off-by: Lee Jones --- Documentation/devicetree/bindings/mfd/tps6105x.txt | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) create mode 100644 Documentation/devicetree/bindings/mfd/tps6105x.txt diff --git a/Documentation/devicetree/bindings/mfd/tps6105x.txt b/Documentation/devicetree/bindings/mfd/tps6105x.txt new file mode 100644 index 0000000..93602c7 --- /dev/null +++ b/Documentation/devicetree/bindings/mfd/tps6105x.txt @@ -0,0 +1,17 @@ +* Device tree bindings for TI TPS61050/61052 Boost Converters + +The TP61050/TPS61052 is a high-power "white LED driver". The +device provides LED, GPIO and regulator functionalities. + +Required properties: +- compatible: "ti,tps61050" or "ti,tps61052" +- reg: Specifies the I2C slave address + +Example: + +i2c0 { + tps61052@33 { + compatible = "ti,tps61052"; + reg = <0x33>; + }; +}; -- cgit v1.1 From 125b249ea57ca908cdffc959f12924b059502c4d Mon Sep 17 00:00:00 2001 From: Javier Martinez Canillas Date: Thu, 15 Jun 2017 20:49:27 +0200 Subject: mfd: tps6105x: Add OF device ID table The driver doesn't have a struct of_device_id table but supported devices are registered via Device Trees. This is working on the assumption that a I2C device registered via OF will always match a legacy I2C device ID and that the MODALIAS reported will always be of the form i2c:. But this could change in the future so the correct approach is to have a OF device ID table if the devices are registered via OF. Signed-off-by: Javier Martinez Canillas Acked-by: Rob Herring Acked-by: Tony Lindgren Signed-off-by: Lee Jones --- drivers/mfd/tps6105x.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/mfd/tps6105x.c b/drivers/mfd/tps6105x.c index baa12ea..187848c 100644 --- a/drivers/mfd/tps6105x.c +++ b/drivers/mfd/tps6105x.c @@ -173,9 +173,17 @@ static const struct i2c_device_id tps6105x_id[] = { }; MODULE_DEVICE_TABLE(i2c, tps6105x_id); +static const struct of_device_id tps6105x_of_match[] = { + { .compatible = "ti,tps61050" }, + { .compatible = "ti,tps61052" }, + { }, +}; +MODULE_DEVICE_TABLE(of, tps6105x_of_match); + static struct i2c_driver tps6105x_driver = { .driver = { .name = "tps6105x", + .of_match_table = tps6105x_of_match, }, .probe = tps6105x_probe, .remove = tps6105x_remove, -- cgit v1.1 From ea5ae803192eb2b03e0bd23db63d2f355fd23eda Mon Sep 17 00:00:00 2001 From: Javier Martinez Canillas Date: Thu, 15 Jun 2017 20:49:28 +0200 Subject: ARM: ux500: Add vendor prefix to tps61052 node The tps61052 device node doesn't have a vendor prefix in its compatible string, fix it by adding one. Signed-off-by: Javier Martinez Canillas Acked-by: Rob Herring Acked-by: Tony Lindgren Reviewed-by: Linus Walleij Signed-off-by: Lee Jones --- arch/arm/boot/dts/ste-hrefprev60.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/ste-hrefprev60.dtsi b/arch/arm/boot/dts/ste-hrefprev60.dtsi index 5882a26..3f14b4d 100644 --- a/arch/arm/boot/dts/ste-hrefprev60.dtsi +++ b/arch/arm/boot/dts/ste-hrefprev60.dtsi @@ -30,7 +30,7 @@ i2c@80004000 { tps61052@33 { - compatible = "tps61052"; + compatible = "ti,tps61052"; reg = <0x33>; }; -- cgit v1.1 From 0335a9554b4d6acc2d17efe752bff54ce59b57eb Mon Sep 17 00:00:00 2001 From: Wolfram Sang Date: Mon, 14 Aug 2017 18:34:22 +0200 Subject: mfd: dm355evm_msp: Move header file out of I2C realm include/linux/i2c is not for client devices. Move the header file to a more appropriate location. Signed-off-by: Wolfram Sang Acked-by: Alexandre Belloni Acked-by: Dmitry Torokhov Signed-off-by: Lee Jones --- drivers/input/misc/dm355evm_keys.c | 2 +- drivers/mfd/dm355evm_msp.c | 2 +- drivers/rtc/rtc-dm355evm.c | 2 +- include/linux/i2c/dm355evm_msp.h | 79 -------------------------------------- include/linux/mfd/dm355evm_msp.h | 79 ++++++++++++++++++++++++++++++++++++++ 5 files changed, 82 insertions(+), 82 deletions(-) delete mode 100644 include/linux/i2c/dm355evm_msp.h create mode 100644 include/linux/mfd/dm355evm_msp.h diff --git a/drivers/input/misc/dm355evm_keys.c b/drivers/input/misc/dm355evm_keys.c index bab256e..c803db6 100644 --- a/drivers/input/misc/dm355evm_keys.c +++ b/drivers/input/misc/dm355evm_keys.c @@ -15,7 +15,7 @@ #include #include -#include +#include #include diff --git a/drivers/mfd/dm355evm_msp.c b/drivers/mfd/dm355evm_msp.c index 86eca61..2a27567 100644 --- a/drivers/mfd/dm355evm_msp.c +++ b/drivers/mfd/dm355evm_msp.c @@ -18,7 +18,7 @@ #include #include #include -#include +#include /* diff --git a/drivers/rtc/rtc-dm355evm.c b/drivers/rtc/rtc-dm355evm.c index f225cd8..97d8259 100644 --- a/drivers/rtc/rtc-dm355evm.c +++ b/drivers/rtc/rtc-dm355evm.c @@ -13,7 +13,7 @@ #include #include -#include +#include #include diff --git a/include/linux/i2c/dm355evm_msp.h b/include/linux/i2c/dm355evm_msp.h deleted file mode 100644 index 3724703..0000000 --- a/include/linux/i2c/dm355evm_msp.h +++ /dev/null @@ -1,79 +0,0 @@ -/* - * dm355evm_msp.h - support MSP430 microcontroller on DM355EVM board - */ -#ifndef __LINUX_I2C_DM355EVM_MSP -#define __LINUX_I2C_DM355EVM_MSP - -/* - * Written against Spectrum's writeup for the A4 firmware revision, - * and tweaked to match source and rev D2 schematics by removing CPLD - * and NOR flash hooks (which were last appropriate in rev B boards). - * - * Note that the firmware supports a flavor of write posting ... to be - * sure a write completes, issue another read or write. - */ - -/* utilities to access "registers" emulated by msp430 firmware */ -extern int dm355evm_msp_write(u8 value, u8 reg); -extern int dm355evm_msp_read(u8 reg); - - -/* command/control registers */ -#define DM355EVM_MSP_COMMAND 0x00 -# define MSP_COMMAND_NULL 0 -# define MSP_COMMAND_RESET_COLD 1 -# define MSP_COMMAND_RESET_WARM 2 -# define MSP_COMMAND_RESET_WARM_I 3 -# define MSP_COMMAND_POWEROFF 4 -# define MSP_COMMAND_IR_REINIT 5 -#define DM355EVM_MSP_STATUS 0x01 -# define MSP_STATUS_BAD_OFFSET BIT(0) -# define MSP_STATUS_BAD_COMMAND BIT(1) -# define MSP_STATUS_POWER_ERROR BIT(2) -# define MSP_STATUS_RXBUF_OVERRUN BIT(3) -#define DM355EVM_MSP_RESET 0x02 /* 0 bits == in reset */ -# define MSP_RESET_DC5 BIT(0) -# define MSP_RESET_TVP5154 BIT(2) -# define MSP_RESET_IMAGER BIT(3) -# define MSP_RESET_ETHERNET BIT(4) -# define MSP_RESET_SYS BIT(5) -# define MSP_RESET_AIC33 BIT(7) - -/* GPIO registers ... bit patterns mostly match the source MSP ports */ -#define DM355EVM_MSP_LED 0x03 /* active low (MSP P4) */ -#define DM355EVM_MSP_SWITCH1 0x04 /* (MSP P5, masked) */ -# define MSP_SWITCH1_SW6_1 BIT(0) -# define MSP_SWITCH1_SW6_2 BIT(1) -# define MSP_SWITCH1_SW6_3 BIT(2) -# define MSP_SWITCH1_SW6_4 BIT(3) -# define MSP_SWITCH1_J1 BIT(4) /* NTSC/PAL */ -# define MSP_SWITCH1_MSP_INT BIT(5) /* active low */ -#define DM355EVM_MSP_SWITCH2 0x05 /* (MSP P6, masked) */ -# define MSP_SWITCH2_SW10 BIT(3) -# define MSP_SWITCH2_SW11 BIT(4) -# define MSP_SWITCH2_SW12 BIT(5) -# define MSP_SWITCH2_SW13 BIT(6) -# define MSP_SWITCH2_SW14 BIT(7) -#define DM355EVM_MSP_SDMMC 0x06 /* (MSP P2, masked) */ -# define MSP_SDMMC_0_WP BIT(1) -# define MSP_SDMMC_0_CD BIT(2) /* active low */ -# define MSP_SDMMC_1_WP BIT(3) -# define MSP_SDMMC_1_CD BIT(4) /* active low */ -#define DM355EVM_MSP_FIRMREV 0x07 /* not a GPIO (out of order) */ -#define DM355EVM_MSP_VIDEO_IN 0x08 /* (MSP P3, masked) */ -# define MSP_VIDEO_IMAGER BIT(7) /* low == tvp5146 */ - -/* power supply registers are currently omitted */ - -/* RTC registers */ -#define DM355EVM_MSP_RTC_0 0x12 /* LSB */ -#define DM355EVM_MSP_RTC_1 0x13 -#define DM355EVM_MSP_RTC_2 0x14 -#define DM355EVM_MSP_RTC_3 0x15 /* MSB */ - -/* input event queue registers; code == ((HIGH << 8) | LOW) */ -#define DM355EVM_MSP_INPUT_COUNT 0x16 /* decrement by reading LOW */ -#define DM355EVM_MSP_INPUT_HIGH 0x17 -#define DM355EVM_MSP_INPUT_LOW 0x18 - -#endif /* __LINUX_I2C_DM355EVM_MSP */ diff --git a/include/linux/mfd/dm355evm_msp.h b/include/linux/mfd/dm355evm_msp.h new file mode 100644 index 0000000..3724703 --- /dev/null +++ b/include/linux/mfd/dm355evm_msp.h @@ -0,0 +1,79 @@ +/* + * dm355evm_msp.h - support MSP430 microcontroller on DM355EVM board + */ +#ifndef __LINUX_I2C_DM355EVM_MSP +#define __LINUX_I2C_DM355EVM_MSP + +/* + * Written against Spectrum's writeup for the A4 firmware revision, + * and tweaked to match source and rev D2 schematics by removing CPLD + * and NOR flash hooks (which were last appropriate in rev B boards). + * + * Note that the firmware supports a flavor of write posting ... to be + * sure a write completes, issue another read or write. + */ + +/* utilities to access "registers" emulated by msp430 firmware */ +extern int dm355evm_msp_write(u8 value, u8 reg); +extern int dm355evm_msp_read(u8 reg); + + +/* command/control registers */ +#define DM355EVM_MSP_COMMAND 0x00 +# define MSP_COMMAND_NULL 0 +# define MSP_COMMAND_RESET_COLD 1 +# define MSP_COMMAND_RESET_WARM 2 +# define MSP_COMMAND_RESET_WARM_I 3 +# define MSP_COMMAND_POWEROFF 4 +# define MSP_COMMAND_IR_REINIT 5 +#define DM355EVM_MSP_STATUS 0x01 +# define MSP_STATUS_BAD_OFFSET BIT(0) +# define MSP_STATUS_BAD_COMMAND BIT(1) +# define MSP_STATUS_POWER_ERROR BIT(2) +# define MSP_STATUS_RXBUF_OVERRUN BIT(3) +#define DM355EVM_MSP_RESET 0x02 /* 0 bits == in reset */ +# define MSP_RESET_DC5 BIT(0) +# define MSP_RESET_TVP5154 BIT(2) +# define MSP_RESET_IMAGER BIT(3) +# define MSP_RESET_ETHERNET BIT(4) +# define MSP_RESET_SYS BIT(5) +# define MSP_RESET_AIC33 BIT(7) + +/* GPIO registers ... bit patterns mostly match the source MSP ports */ +#define DM355EVM_MSP_LED 0x03 /* active low (MSP P4) */ +#define DM355EVM_MSP_SWITCH1 0x04 /* (MSP P5, masked) */ +# define MSP_SWITCH1_SW6_1 BIT(0) +# define MSP_SWITCH1_SW6_2 BIT(1) +# define MSP_SWITCH1_SW6_3 BIT(2) +# define MSP_SWITCH1_SW6_4 BIT(3) +# define MSP_SWITCH1_J1 BIT(4) /* NTSC/PAL */ +# define MSP_SWITCH1_MSP_INT BIT(5) /* active low */ +#define DM355EVM_MSP_SWITCH2 0x05 /* (MSP P6, masked) */ +# define MSP_SWITCH2_SW10 BIT(3) +# define MSP_SWITCH2_SW11 BIT(4) +# define MSP_SWITCH2_SW12 BIT(5) +# define MSP_SWITCH2_SW13 BIT(6) +# define MSP_SWITCH2_SW14 BIT(7) +#define DM355EVM_MSP_SDMMC 0x06 /* (MSP P2, masked) */ +# define MSP_SDMMC_0_WP BIT(1) +# define MSP_SDMMC_0_CD BIT(2) /* active low */ +# define MSP_SDMMC_1_WP BIT(3) +# define MSP_SDMMC_1_CD BIT(4) /* active low */ +#define DM355EVM_MSP_FIRMREV 0x07 /* not a GPIO (out of order) */ +#define DM355EVM_MSP_VIDEO_IN 0x08 /* (MSP P3, masked) */ +# define MSP_VIDEO_IMAGER BIT(7) /* low == tvp5146 */ + +/* power supply registers are currently omitted */ + +/* RTC registers */ +#define DM355EVM_MSP_RTC_0 0x12 /* LSB */ +#define DM355EVM_MSP_RTC_1 0x13 +#define DM355EVM_MSP_RTC_2 0x14 +#define DM355EVM_MSP_RTC_3 0x15 /* MSB */ + +/* input event queue registers; code == ((HIGH << 8) | LOW) */ +#define DM355EVM_MSP_INPUT_COUNT 0x16 /* decrement by reading LOW */ +#define DM355EVM_MSP_INPUT_HIGH 0x17 +#define DM355EVM_MSP_INPUT_LOW 0x18 + +#endif /* __LINUX_I2C_DM355EVM_MSP */ -- cgit v1.1 From 9787076c43a86f3465d46aa344cc3e2f607ae72f Mon Sep 17 00:00:00 2001 From: Wolfram Sang Date: Mon, 14 Aug 2017 18:34:23 +0200 Subject: mfd: tps65010: Move header file out of I2C realm include/linux/i2c is not for client devices. Move the header file to a more appropriate location. Signed-off-by: Wolfram Sang Acked-by: Greg Kroah-Hartman Acked-by: Krzysztof Kozlowski Acked-by: Bartlomiej Zolnierkiewicz Acked-by: Tony Lindgren Signed-off-by: Lee Jones --- arch/arm/mach-omap1/board-h2-mmc.c | 2 +- arch/arm/mach-omap1/board-h2.c | 2 +- arch/arm/mach-omap1/board-h3-mmc.c | 2 +- arch/arm/mach-omap1/board-h3.c | 2 +- arch/arm/mach-omap1/board-osk.c | 2 +- arch/arm/mach-s3c24xx/mach-osiris-dvs.c | 2 +- arch/arm/mach-s3c24xx/mach-osiris.c | 2 +- drivers/mfd/tps65010.c | 2 +- drivers/usb/host/ohci-omap.c | 2 +- drivers/usb/phy/phy-isp1301-omap.c | 2 +- drivers/video/fbdev/omap/lcd_h3.c | 2 +- include/linux/i2c/tps65010.h | 205 -------------------------------- include/linux/mfd/tps65010.h | 205 ++++++++++++++++++++++++++++++++ 13 files changed, 216 insertions(+), 216 deletions(-) delete mode 100644 include/linux/i2c/tps65010.h create mode 100644 include/linux/mfd/tps65010.h diff --git a/arch/arm/mach-omap1/board-h2-mmc.c b/arch/arm/mach-omap1/board-h2-mmc.c index 357be2d..91bda9c 100644 --- a/arch/arm/mach-omap1/board-h2-mmc.c +++ b/arch/arm/mach-omap1/board-h2-mmc.c @@ -14,7 +14,7 @@ #include #include #include -#include +#include #include "board-h2.h" #include "mmc.h" diff --git a/arch/arm/mach-omap1/board-h2.c b/arch/arm/mach-omap1/board-h2.c index 675254e..dece47d 100644 --- a/arch/arm/mach-omap1/board-h2.c +++ b/arch/arm/mach-omap1/board-h2.c @@ -28,7 +28,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/arch/arm/mach-omap1/board-h3-mmc.c b/arch/arm/mach-omap1/board-h3-mmc.c index 4f58bfa..692c267 100644 --- a/arch/arm/mach-omap1/board-h3-mmc.c +++ b/arch/arm/mach-omap1/board-h3-mmc.c @@ -14,7 +14,7 @@ #include #include -#include +#include #include "common.h" #include "board-h3.h" diff --git a/arch/arm/mach-omap1/board-h3.c b/arch/arm/mach-omap1/board-h3.c index e62f9d4..6d32bee 100644 --- a/arch/arm/mach-omap1/board-h3.c +++ b/arch/arm/mach-omap1/board-h3.c @@ -28,7 +28,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/arch/arm/mach-omap1/board-osk.c b/arch/arm/mach-omap1/board-osk.c index 4dfb995..f20361b 100644 --- a/arch/arm/mach-omap1/board-osk.c +++ b/arch/arm/mach-omap1/board-osk.c @@ -38,7 +38,7 @@ #include #include #include -#include +#include #include #include diff --git a/arch/arm/mach-s3c24xx/mach-osiris-dvs.c b/arch/arm/mach-s3c24xx/mach-osiris-dvs.c index 262ab07..6cac7da1 100644 --- a/arch/arm/mach-s3c24xx/mach-osiris-dvs.c +++ b/arch/arm/mach-s3c24xx/mach-osiris-dvs.c @@ -17,7 +17,7 @@ #include #include -#include +#include #include #include diff --git a/arch/arm/mach-s3c24xx/mach-osiris.c b/arch/arm/mach-s3c24xx/mach-osiris.c index 70b0eb7..64b1a0b 100644 --- a/arch/arm/mach-s3c24xx/mach-osiris.c +++ b/arch/arm/mach-s3c24xx/mach-osiris.c @@ -24,7 +24,7 @@ #include #include -#include +#include #include #include diff --git a/drivers/mfd/tps65010.c b/drivers/mfd/tps65010.c index d829a61..2ab6738 100644 --- a/drivers/mfd/tps65010.c +++ b/drivers/mfd/tps65010.c @@ -32,7 +32,7 @@ #include #include -#include +#include #include diff --git a/drivers/usb/host/ohci-omap.c b/drivers/usb/host/ohci-omap.c index a4d814b..91393ec 100644 --- a/drivers/usb/host/ohci-omap.c +++ b/drivers/usb/host/ohci-omap.c @@ -53,7 +53,7 @@ #define DRIVER_DESC "OHCI OMAP driver" #ifdef CONFIG_TPS65010 -#include +#include #else #define LOW 0 diff --git a/drivers/usb/phy/phy-isp1301-omap.c b/drivers/usb/phy/phy-isp1301-omap.c index 042c5a8..c6052c8 100644 --- a/drivers/usb/phy/phy-isp1301-omap.c +++ b/drivers/usb/phy/phy-isp1301-omap.c @@ -96,7 +96,7 @@ struct isp1301 { #if IS_REACHABLE(CONFIG_TPS65010) -#include +#include #else diff --git a/drivers/video/fbdev/omap/lcd_h3.c b/drivers/video/fbdev/omap/lcd_h3.c index 9d2da14..796f463 100644 --- a/drivers/video/fbdev/omap/lcd_h3.c +++ b/drivers/video/fbdev/omap/lcd_h3.c @@ -21,7 +21,7 @@ #include #include -#include +#include #include #include "omapfb.h" diff --git a/include/linux/i2c/tps65010.h b/include/linux/i2c/tps65010.h deleted file mode 100644 index 08aa922..0000000 --- a/include/linux/i2c/tps65010.h +++ /dev/null @@ -1,205 +0,0 @@ -/* linux/i2c/tps65010.h - * - * Functions to access TPS65010 power management device. - * - * Copyright (C) 2004 Dirk Behme - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - */ - -#ifndef __LINUX_I2C_TPS65010_H -#define __LINUX_I2C_TPS65010_H - -/* - * ---------------------------------------------------------------------------- - * Registers, all 8 bits - * ---------------------------------------------------------------------------- - */ - -#define TPS_CHGSTATUS 0x01 -# define TPS_CHG_USB (1 << 7) -# define TPS_CHG_AC (1 << 6) -# define TPS_CHG_THERM (1 << 5) -# define TPS_CHG_TERM (1 << 4) -# define TPS_CHG_TAPER_TMO (1 << 3) -# define TPS_CHG_CHG_TMO (1 << 2) -# define TPS_CHG_PRECHG_TMO (1 << 1) -# define TPS_CHG_TEMP_ERR (1 << 0) -#define TPS_REGSTATUS 0x02 -# define TPS_REG_ONOFF (1 << 7) -# define TPS_REG_COVER (1 << 6) -# define TPS_REG_UVLO (1 << 5) -# define TPS_REG_NO_CHG (1 << 4) /* tps65013 */ -# define TPS_REG_PG_LD02 (1 << 3) -# define TPS_REG_PG_LD01 (1 << 2) -# define TPS_REG_PG_MAIN (1 << 1) -# define TPS_REG_PG_CORE (1 << 0) -#define TPS_MASK1 0x03 -#define TPS_MASK2 0x04 -#define TPS_ACKINT1 0x05 -#define TPS_ACKINT2 0x06 -#define TPS_CHGCONFIG 0x07 -# define TPS_CHARGE_POR (1 << 7) /* 65010/65012 */ -# define TPS65013_AUA (1 << 7) /* 65011/65013 */ -# define TPS_CHARGE_RESET (1 << 6) -# define TPS_CHARGE_FAST (1 << 5) -# define TPS_CHARGE_CURRENT (3 << 3) -# define TPS_VBUS_500MA (1 << 2) -# define TPS_VBUS_CHARGING (1 << 1) -# define TPS_CHARGE_ENABLE (1 << 0) -#define TPS_LED1_ON 0x08 -#define TPS_LED1_PER 0x09 -#define TPS_LED2_ON 0x0a -#define TPS_LED2_PER 0x0b -#define TPS_VDCDC1 0x0c -# define TPS_ENABLE_LP (1 << 3) -#define TPS_VDCDC2 0x0d -# define TPS_LP_COREOFF (1 << 7) -# define TPS_VCORE_1_8V (7<<4) -# define TPS_VCORE_1_5V (6 << 4) -# define TPS_VCORE_1_4V (5 << 4) -# define TPS_VCORE_1_3V (4 << 4) -# define TPS_VCORE_1_2V (3 << 4) -# define TPS_VCORE_1_1V (2 << 4) -# define TPS_VCORE_1_0V (1 << 4) -# define TPS_VCORE_0_85V (0 << 4) -# define TPS_VCORE_LP_1_2V (3 << 2) -# define TPS_VCORE_LP_1_1V (2 << 2) -# define TPS_VCORE_LP_1_0V (1 << 2) -# define TPS_VCORE_LP_0_85V (0 << 2) -# define TPS_VIB (1 << 1) -# define TPS_VCORE_DISCH (1 << 0) -#define TPS_VREGS1 0x0e -# define TPS_LDO2_ENABLE (1 << 7) -# define TPS_LDO2_OFF (1 << 6) -# define TPS_VLDO2_3_0V (3 << 4) -# define TPS_VLDO2_2_75V (2 << 4) -# define TPS_VLDO2_2_5V (1 << 4) -# define TPS_VLDO2_1_8V (0 << 4) -# define TPS_LDO1_ENABLE (1 << 3) -# define TPS_LDO1_OFF (1 << 2) -# define TPS_VLDO1_3_0V (3 << 0) -# define TPS_VLDO1_2_75V (2 << 0) -# define TPS_VLDO1_2_5V (1 << 0) -# define TPS_VLDO1_ADJ (0 << 0) -#define TPS_MASK3 0x0f -#define TPS_DEFGPIO 0x10 - -/* - * ---------------------------------------------------------------------------- - * Macros used by exported functions - * ---------------------------------------------------------------------------- - */ - -#define LED1 1 -#define LED2 2 -#define OFF 0 -#define ON 1 -#define BLINK 2 -#define GPIO1 1 -#define GPIO2 2 -#define GPIO3 3 -#define GPIO4 4 -#define LOW 0 -#define HIGH 1 - -/* - * ---------------------------------------------------------------------------- - * Exported functions - * ---------------------------------------------------------------------------- - */ - -/* Draw from VBUS: - * 0 mA -- DON'T DRAW (might supply power instead) - * 100 mA -- usb unit load (slowest charge rate) - * 500 mA -- usb high power (fast battery charge) - */ -extern int tps65010_set_vbus_draw(unsigned mA); - -/* tps65010_set_gpio_out_value parameter: - * gpio: GPIO1, GPIO2, GPIO3 or GPIO4 - * value: LOW or HIGH - */ -extern int tps65010_set_gpio_out_value(unsigned gpio, unsigned value); - -/* tps65010_set_led parameter: - * led: LED1 or LED2 - * mode: ON, OFF or BLINK - */ -extern int tps65010_set_led(unsigned led, unsigned mode); - -/* tps65010_set_vib parameter: - * value: ON or OFF - */ -extern int tps65010_set_vib(unsigned value); - -/* tps65010_set_low_pwr parameter: - * mode: ON or OFF - */ -extern int tps65010_set_low_pwr(unsigned mode); - -/* tps65010_config_vregs1 parameter: - * value to be written to VREGS1 register - * Note: The complete register is written, set all bits you need - */ -extern int tps65010_config_vregs1(unsigned value); - -/* tps65013_set_low_pwr parameter: - * mode: ON or OFF - */ -extern int tps65013_set_low_pwr(unsigned mode); - -/* tps65010_set_vdcdc2 - * value to be written to VDCDC2 - */ -extern int tps65010_config_vdcdc2(unsigned value); - -struct i2c_client; - -/** - * struct tps65010_board - packages GPIO and LED lines - * @base: the GPIO number to assign to GPIO-1 - * @outmask: bit (N-1) is set to allow GPIO-N to be used as an - * (open drain) output - * @setup: optional callback issued once the GPIOs are valid - * @teardown: optional callback issued before the GPIOs are invalidated - * @context: optional parameter passed to setup() and teardown() - * - * Board data may be used to package the GPIO (and LED) lines for use - * in by the generic GPIO and LED frameworks. The first four GPIOs - * starting at gpio_base are GPIO1..GPIO4. The next two are LED1/nPG - * and LED2 (with hardware blinking capability, not currently exposed). - * - * The @setup callback may be used with the kind of board-specific glue - * which hands the (now-valid) GPIOs to other drivers, or which puts - * devices in their initial states using these GPIOs. - */ -struct tps65010_board { - int base; - unsigned outmask; - - int (*setup)(struct i2c_client *client, void *context); - int (*teardown)(struct i2c_client *client, void *context); - void *context; -}; - -#endif /* __LINUX_I2C_TPS65010_H */ - diff --git a/include/linux/mfd/tps65010.h b/include/linux/mfd/tps65010.h new file mode 100644 index 0000000..a1fb9bc --- /dev/null +++ b/include/linux/mfd/tps65010.h @@ -0,0 +1,205 @@ +/* linux/mfd/tps65010.h + * + * Functions to access TPS65010 power management device. + * + * Copyright (C) 2004 Dirk Behme + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#ifndef __LINUX_I2C_TPS65010_H +#define __LINUX_I2C_TPS65010_H + +/* + * ---------------------------------------------------------------------------- + * Registers, all 8 bits + * ---------------------------------------------------------------------------- + */ + +#define TPS_CHGSTATUS 0x01 +# define TPS_CHG_USB (1 << 7) +# define TPS_CHG_AC (1 << 6) +# define TPS_CHG_THERM (1 << 5) +# define TPS_CHG_TERM (1 << 4) +# define TPS_CHG_TAPER_TMO (1 << 3) +# define TPS_CHG_CHG_TMO (1 << 2) +# define TPS_CHG_PRECHG_TMO (1 << 1) +# define TPS_CHG_TEMP_ERR (1 << 0) +#define TPS_REGSTATUS 0x02 +# define TPS_REG_ONOFF (1 << 7) +# define TPS_REG_COVER (1 << 6) +# define TPS_REG_UVLO (1 << 5) +# define TPS_REG_NO_CHG (1 << 4) /* tps65013 */ +# define TPS_REG_PG_LD02 (1 << 3) +# define TPS_REG_PG_LD01 (1 << 2) +# define TPS_REG_PG_MAIN (1 << 1) +# define TPS_REG_PG_CORE (1 << 0) +#define TPS_MASK1 0x03 +#define TPS_MASK2 0x04 +#define TPS_ACKINT1 0x05 +#define TPS_ACKINT2 0x06 +#define TPS_CHGCONFIG 0x07 +# define TPS_CHARGE_POR (1 << 7) /* 65010/65012 */ +# define TPS65013_AUA (1 << 7) /* 65011/65013 */ +# define TPS_CHARGE_RESET (1 << 6) +# define TPS_CHARGE_FAST (1 << 5) +# define TPS_CHARGE_CURRENT (3 << 3) +# define TPS_VBUS_500MA (1 << 2) +# define TPS_VBUS_CHARGING (1 << 1) +# define TPS_CHARGE_ENABLE (1 << 0) +#define TPS_LED1_ON 0x08 +#define TPS_LED1_PER 0x09 +#define TPS_LED2_ON 0x0a +#define TPS_LED2_PER 0x0b +#define TPS_VDCDC1 0x0c +# define TPS_ENABLE_LP (1 << 3) +#define TPS_VDCDC2 0x0d +# define TPS_LP_COREOFF (1 << 7) +# define TPS_VCORE_1_8V (7<<4) +# define TPS_VCORE_1_5V (6 << 4) +# define TPS_VCORE_1_4V (5 << 4) +# define TPS_VCORE_1_3V (4 << 4) +# define TPS_VCORE_1_2V (3 << 4) +# define TPS_VCORE_1_1V (2 << 4) +# define TPS_VCORE_1_0V (1 << 4) +# define TPS_VCORE_0_85V (0 << 4) +# define TPS_VCORE_LP_1_2V (3 << 2) +# define TPS_VCORE_LP_1_1V (2 << 2) +# define TPS_VCORE_LP_1_0V (1 << 2) +# define TPS_VCORE_LP_0_85V (0 << 2) +# define TPS_VIB (1 << 1) +# define TPS_VCORE_DISCH (1 << 0) +#define TPS_VREGS1 0x0e +# define TPS_LDO2_ENABLE (1 << 7) +# define TPS_LDO2_OFF (1 << 6) +# define TPS_VLDO2_3_0V (3 << 4) +# define TPS_VLDO2_2_75V (2 << 4) +# define TPS_VLDO2_2_5V (1 << 4) +# define TPS_VLDO2_1_8V (0 << 4) +# define TPS_LDO1_ENABLE (1 << 3) +# define TPS_LDO1_OFF (1 << 2) +# define TPS_VLDO1_3_0V (3 << 0) +# define TPS_VLDO1_2_75V (2 << 0) +# define TPS_VLDO1_2_5V (1 << 0) +# define TPS_VLDO1_ADJ (0 << 0) +#define TPS_MASK3 0x0f +#define TPS_DEFGPIO 0x10 + +/* + * ---------------------------------------------------------------------------- + * Macros used by exported functions + * ---------------------------------------------------------------------------- + */ + +#define LED1 1 +#define LED2 2 +#define OFF 0 +#define ON 1 +#define BLINK 2 +#define GPIO1 1 +#define GPIO2 2 +#define GPIO3 3 +#define GPIO4 4 +#define LOW 0 +#define HIGH 1 + +/* + * ---------------------------------------------------------------------------- + * Exported functions + * ---------------------------------------------------------------------------- + */ + +/* Draw from VBUS: + * 0 mA -- DON'T DRAW (might supply power instead) + * 100 mA -- usb unit load (slowest charge rate) + * 500 mA -- usb high power (fast battery charge) + */ +extern int tps65010_set_vbus_draw(unsigned mA); + +/* tps65010_set_gpio_out_value parameter: + * gpio: GPIO1, GPIO2, GPIO3 or GPIO4 + * value: LOW or HIGH + */ +extern int tps65010_set_gpio_out_value(unsigned gpio, unsigned value); + +/* tps65010_set_led parameter: + * led: LED1 or LED2 + * mode: ON, OFF or BLINK + */ +extern int tps65010_set_led(unsigned led, unsigned mode); + +/* tps65010_set_vib parameter: + * value: ON or OFF + */ +extern int tps65010_set_vib(unsigned value); + +/* tps65010_set_low_pwr parameter: + * mode: ON or OFF + */ +extern int tps65010_set_low_pwr(unsigned mode); + +/* tps65010_config_vregs1 parameter: + * value to be written to VREGS1 register + * Note: The complete register is written, set all bits you need + */ +extern int tps65010_config_vregs1(unsigned value); + +/* tps65013_set_low_pwr parameter: + * mode: ON or OFF + */ +extern int tps65013_set_low_pwr(unsigned mode); + +/* tps65010_set_vdcdc2 + * value to be written to VDCDC2 + */ +extern int tps65010_config_vdcdc2(unsigned value); + +struct i2c_client; + +/** + * struct tps65010_board - packages GPIO and LED lines + * @base: the GPIO number to assign to GPIO-1 + * @outmask: bit (N-1) is set to allow GPIO-N to be used as an + * (open drain) output + * @setup: optional callback issued once the GPIOs are valid + * @teardown: optional callback issued before the GPIOs are invalidated + * @context: optional parameter passed to setup() and teardown() + * + * Board data may be used to package the GPIO (and LED) lines for use + * in by the generic GPIO and LED frameworks. The first four GPIOs + * starting at gpio_base are GPIO1..GPIO4. The next two are LED1/nPG + * and LED2 (with hardware blinking capability, not currently exposed). + * + * The @setup callback may be used with the kind of board-specific glue + * which hands the (now-valid) GPIOs to other drivers, or which puts + * devices in their initial states using these GPIOs. + */ +struct tps65010_board { + int base; + unsigned outmask; + + int (*setup)(struct i2c_client *client, void *context); + int (*teardown)(struct i2c_client *client, void *context); + void *context; +}; + +#endif /* __LINUX_I2C_TPS65010_H */ + -- cgit v1.1 From 9d6105e19f617406aea46dd19281080c7c5ae0d8 Mon Sep 17 00:00:00 2001 From: Elaine Zhang Date: Mon, 21 Aug 2017 03:28:34 +0200 Subject: mfd: rk808: Fix up the chip id get failed the rk8xx chip id is: ((MSB << 8) | LSB) & 0xfff0 Signed-off-by: Elaine Zhang Signed-off-by: Joseph Chen Signed-off-by: Heiko Stuebner Signed-off-by: Lee Jones --- drivers/mfd/rk808.c | 21 +++++++++++++++------ include/linux/mfd/rk808.h | 1 + 2 files changed, 16 insertions(+), 6 deletions(-) diff --git a/drivers/mfd/rk808.c b/drivers/mfd/rk808.c index fd087cb..8e60eba 100644 --- a/drivers/mfd/rk808.c +++ b/drivers/mfd/rk808.c @@ -325,7 +325,7 @@ static int rk808_probe(struct i2c_client *client, void (*pm_pwroff_fn)(void); int nr_pre_init_regs; int nr_cells; - int pm_off = 0; + int pm_off = 0, msb, lsb; int ret; int i; @@ -333,14 +333,23 @@ static int rk808_probe(struct i2c_client *client, if (!rk808) return -ENOMEM; - rk808->variant = i2c_smbus_read_word_data(client, RK808_ID_MSB); - if (rk808->variant < 0) { - dev_err(&client->dev, "Failed to read the chip id at 0x%02x\n", + /* Read chip variant */ + msb = i2c_smbus_read_byte_data(client, RK808_ID_MSB); + if (msb < 0) { + dev_err(&client->dev, "failed to read the chip id at 0x%x\n", RK808_ID_MSB); - return rk808->variant; + return msb; } - dev_dbg(&client->dev, "Chip id: 0x%x\n", (unsigned int)rk808->variant); + lsb = i2c_smbus_read_byte_data(client, RK808_ID_LSB); + if (lsb < 0) { + dev_err(&client->dev, "failed to read the chip id at 0x%x\n", + RK808_ID_LSB); + return lsb; + } + + rk808->variant = ((msb << 8) | lsb) & RK8XX_ID_MSK; + dev_info(&client->dev, "chip id: 0x%x\n", (unsigned int)rk808->variant); switch (rk808->variant) { case RK808_ID: diff --git a/include/linux/mfd/rk808.h b/include/linux/mfd/rk808.h index 83701ef..54feb14 100644 --- a/include/linux/mfd/rk808.h +++ b/include/linux/mfd/rk808.h @@ -298,6 +298,7 @@ enum rk818_reg { #define VOUT_LO_INT BIT(0) #define CLK32KOUT2_EN BIT(0) +#define RK8XX_ID_MSK 0xfff0 enum { BUCK_ILMIN_50MA, BUCK_ILMIN_100MA, -- cgit v1.1 From a5247ca6708ff7dc089d2774c131455774153eb6 Mon Sep 17 00:00:00 2001 From: Elaine Zhang Date: Mon, 21 Aug 2017 03:28:35 +0200 Subject: mfd: rk808: Add rk805 regs addr and ID Signed-off-by: Elaine Zhang Signed-off-by: Joseph Chen Signed-off-by: Heiko Stuebner Signed-off-by: Lee Jones --- include/linux/mfd/rk808.h | 120 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 120 insertions(+) diff --git a/include/linux/mfd/rk808.h b/include/linux/mfd/rk808.h index 54feb14..d315659 100644 --- a/include/linux/mfd/rk808.h +++ b/include/linux/mfd/rk808.h @@ -206,6 +206,97 @@ enum rk818_reg { #define RK818_USB_ILMIN_2000MA 0x7 #define RK818_USB_CHG_SD_VSEL_MASK 0x70 +/* RK805 */ +enum rk805_reg { + RK805_ID_DCDC1, + RK805_ID_DCDC2, + RK805_ID_DCDC3, + RK805_ID_DCDC4, + RK805_ID_LDO1, + RK805_ID_LDO2, + RK805_ID_LDO3, +}; + +/* CONFIG REGISTER */ +#define RK805_VB_MON_REG 0x21 +#define RK805_THERMAL_REG 0x22 + +/* POWER CHANNELS ENABLE REGISTER */ +#define RK805_DCDC_EN_REG 0x23 +#define RK805_SLP_DCDC_EN_REG 0x25 +#define RK805_SLP_LDO_EN_REG 0x26 +#define RK805_LDO_EN_REG 0x27 + +/* BUCK AND LDO CONFIG REGISTER */ +#define RK805_BUCK_LDO_SLP_LP_EN_REG 0x2A +#define RK805_BUCK1_CONFIG_REG 0x2E +#define RK805_BUCK1_ON_VSEL_REG 0x2F +#define RK805_BUCK1_SLP_VSEL_REG 0x30 +#define RK805_BUCK2_CONFIG_REG 0x32 +#define RK805_BUCK2_ON_VSEL_REG 0x33 +#define RK805_BUCK2_SLP_VSEL_REG 0x34 +#define RK805_BUCK3_CONFIG_REG 0x36 +#define RK805_BUCK4_CONFIG_REG 0x37 +#define RK805_BUCK4_ON_VSEL_REG 0x38 +#define RK805_BUCK4_SLP_VSEL_REG 0x39 +#define RK805_LDO1_ON_VSEL_REG 0x3B +#define RK805_LDO1_SLP_VSEL_REG 0x3C +#define RK805_LDO2_ON_VSEL_REG 0x3D +#define RK805_LDO2_SLP_VSEL_REG 0x3E +#define RK805_LDO3_ON_VSEL_REG 0x3F +#define RK805_LDO3_SLP_VSEL_REG 0x40 + +/* INTERRUPT REGISTER */ +#define RK805_PWRON_LP_INT_TIME_REG 0x47 +#define RK805_PWRON_DB_REG 0x48 +#define RK805_DEV_CTRL_REG 0x4B +#define RK805_INT_STS_REG 0x4C +#define RK805_INT_STS_MSK_REG 0x4D +#define RK805_GPIO_IO_POL_REG 0x50 +#define RK805_OUT_REG 0x52 +#define RK805_ON_SOURCE_REG 0xAE +#define RK805_OFF_SOURCE_REG 0xAF + +#define RK805_NUM_REGULATORS 7 + +#define RK805_PWRON_FALL_RISE_INT_EN 0x0 +#define RK805_PWRON_FALL_RISE_INT_MSK 0x81 + +/* RK805 IRQ Definitions */ +#define RK805_IRQ_PWRON_RISE 0 +#define RK805_IRQ_VB_LOW 1 +#define RK805_IRQ_PWRON 2 +#define RK805_IRQ_PWRON_LP 3 +#define RK805_IRQ_HOTDIE 4 +#define RK805_IRQ_RTC_ALARM 5 +#define RK805_IRQ_RTC_PERIOD 6 +#define RK805_IRQ_PWRON_FALL 7 + +#define RK805_IRQ_PWRON_RISE_MSK BIT(0) +#define RK805_IRQ_VB_LOW_MSK BIT(1) +#define RK805_IRQ_PWRON_MSK BIT(2) +#define RK805_IRQ_PWRON_LP_MSK BIT(3) +#define RK805_IRQ_HOTDIE_MSK BIT(4) +#define RK805_IRQ_RTC_ALARM_MSK BIT(5) +#define RK805_IRQ_RTC_PERIOD_MSK BIT(6) +#define RK805_IRQ_PWRON_FALL_MSK BIT(7) + +#define RK805_PWR_RISE_INT_STATUS BIT(0) +#define RK805_VB_LOW_INT_STATUS BIT(1) +#define RK805_PWRON_INT_STATUS BIT(2) +#define RK805_PWRON_LP_INT_STATUS BIT(3) +#define RK805_HOTDIE_INT_STATUS BIT(4) +#define RK805_ALARM_INT_STATUS BIT(5) +#define RK805_PERIOD_INT_STATUS BIT(6) +#define RK805_PWR_FALL_INT_STATUS BIT(7) + +#define RK805_BUCK1_2_ILMAX_MASK (3 << 6) +#define RK805_BUCK3_4_ILMAX_MASK (3 << 3) +#define RK805_RTC_PERIOD_INT_MASK (1 << 6) +#define RK805_RTC_ALARM_INT_MASK (1 << 5) +#define RK805_INT_ALARM_EN (1 << 3) +#define RK805_INT_TIMER_EN (1 << 2) + /* RK808 IRQ Definitions */ #define RK808_IRQ_VOUT_LO 0 #define RK808_IRQ_VB_LO 1 @@ -298,7 +389,14 @@ enum rk818_reg { #define VOUT_LO_INT BIT(0) #define CLK32KOUT2_EN BIT(0) +#define TEMP115C 0x0c +#define TEMP_HOTDIE_MSK 0x0c +#define SLP_SD_MSK (0x3 << 2) +#define SHUTDOWN_FUN (0x2 << 2) +#define SLEEP_FUN (0x1 << 2) #define RK8XX_ID_MSK 0xfff0 +#define FPWM_MODE BIT(7) + enum { BUCK_ILMIN_50MA, BUCK_ILMIN_100MA, @@ -322,6 +420,28 @@ enum { }; enum { + RK805_BUCK1_2_ILMAX_2500MA, + RK805_BUCK1_2_ILMAX_3000MA, + RK805_BUCK1_2_ILMAX_3500MA, + RK805_BUCK1_2_ILMAX_4000MA, +}; + +enum { + RK805_BUCK3_ILMAX_1500MA, + RK805_BUCK3_ILMAX_2000MA, + RK805_BUCK3_ILMAX_2500MA, + RK805_BUCK3_ILMAX_3000MA, +}; + +enum { + RK805_BUCK4_ILMAX_2000MA, + RK805_BUCK4_ILMAX_2500MA, + RK805_BUCK4_ILMAX_3000MA, + RK805_BUCK4_ILMAX_3500MA, +}; + +enum { + RK805_ID = 0x8050, RK808_ID = 0x0000, RK818_ID = 0x8181, }; -- cgit v1.1 From c4e0d344c1f086c6675f2a22ea6ea71330fb0b57 Mon Sep 17 00:00:00 2001 From: Elaine Zhang Date: Mon, 21 Aug 2017 03:28:36 +0200 Subject: regulator: rk808: Add regulator driver for RK805 Add support for the rk805 regulator. The regulator module consists of 4 DCDCs, 3 LDOs. The output voltages are configurable and are meant to supply power to the main processor and other components. Signed-off-by: Elaine Zhang Signed-off-by: Joseph Chen Acked-by: Mark Brown Signed-off-by: Heiko Stuebner Signed-off-by: Lee Jones --- drivers/regulator/Kconfig | 4 +- drivers/regulator/rk808-regulator.c | 130 ++++++++++++++++++++++++++++++++++++ 2 files changed, 132 insertions(+), 2 deletions(-) diff --git a/drivers/regulator/Kconfig b/drivers/regulator/Kconfig index 99b9362..008ab58 100644 --- a/drivers/regulator/Kconfig +++ b/drivers/regulator/Kconfig @@ -687,11 +687,11 @@ config REGULATOR_RC5T583 outputs which can be controlled by i2c communication. config REGULATOR_RK808 - tristate "Rockchip RK808/RK818 Power regulators" + tristate "Rockchip RK805/RK808/RK818 Power regulators" depends on MFD_RK808 help Select this option to enable the power regulator of ROCKCHIP - PMIC RK808 and RK818. + PMIC RK805,RK808 and RK818. This driver supports the control of different power rails of device through regulator interface. The device supports multiple DCDC/LDO outputs which can be controlled by i2c communication. diff --git a/drivers/regulator/rk808-regulator.c b/drivers/regulator/rk808-regulator.c index a16d814..213b687 100644 --- a/drivers/regulator/rk808-regulator.c +++ b/drivers/regulator/rk808-regulator.c @@ -65,6 +65,27 @@ /* max steps for increase voltage of Buck1/2, equal 100mv*/ #define MAX_STEPS_ONE_TIME 8 +#define RK805_DESC(_id, _match, _supply, _min, _max, _step, _vreg, \ + _vmask, _ereg, _emask, _etime) \ + [_id] = { \ + .name = (_match), \ + .supply_name = (_supply), \ + .of_match = of_match_ptr(_match), \ + .regulators_node = of_match_ptr("regulators"), \ + .type = REGULATOR_VOLTAGE, \ + .id = (_id), \ + .n_voltages = (((_max) - (_min)) / (_step) + 1), \ + .owner = THIS_MODULE, \ + .min_uV = (_min) * 1000, \ + .uV_step = (_step) * 1000, \ + .vsel_reg = (_vreg), \ + .vsel_mask = (_vmask), \ + .enable_reg = (_ereg), \ + .enable_mask = (_emask), \ + .enable_time = (_etime), \ + .ops = &rk805_reg_ops, \ + } + #define RK8XX_DESC(_id, _match, _supply, _min, _max, _step, _vreg, \ _vmask, _ereg, _emask, _etime) \ [_id] = { \ @@ -298,6 +319,28 @@ static int rk808_set_suspend_voltage_range(struct regulator_dev *rdev, int uv) sel); } +static int rk805_set_suspend_enable(struct regulator_dev *rdev) +{ + unsigned int reg; + + reg = rdev->desc->enable_reg + RK808_SLP_SET_OFF_REG_OFFSET; + + return regmap_update_bits(rdev->regmap, reg, + rdev->desc->enable_mask, + rdev->desc->enable_mask); +} + +static int rk805_set_suspend_disable(struct regulator_dev *rdev) +{ + unsigned int reg; + + reg = rdev->desc->enable_reg + RK808_SLP_SET_OFF_REG_OFFSET; + + return regmap_update_bits(rdev->regmap, reg, + rdev->desc->enable_mask, + 0); +} + static int rk808_set_suspend_enable(struct regulator_dev *rdev) { unsigned int reg; @@ -320,6 +363,27 @@ static int rk808_set_suspend_disable(struct regulator_dev *rdev) rdev->desc->enable_mask); } +static struct regulator_ops rk805_reg_ops = { + .list_voltage = regulator_list_voltage_linear, + .map_voltage = regulator_map_voltage_linear, + .get_voltage_sel = regulator_get_voltage_sel_regmap, + .set_voltage_sel = regulator_set_voltage_sel_regmap, + .enable = regulator_enable_regmap, + .disable = regulator_disable_regmap, + .is_enabled = regulator_is_enabled_regmap, + .set_suspend_voltage = rk808_set_suspend_voltage, + .set_suspend_enable = rk805_set_suspend_enable, + .set_suspend_disable = rk805_set_suspend_disable, +}; + +static struct regulator_ops rk805_switch_ops = { + .enable = regulator_enable_regmap, + .disable = regulator_disable_regmap, + .is_enabled = regulator_is_enabled_regmap, + .set_suspend_enable = rk805_set_suspend_enable, + .set_suspend_disable = rk805_set_suspend_disable, +}; + static struct regulator_ops rk808_buck1_2_ops = { .list_voltage = regulator_list_voltage_linear, .map_voltage = regulator_map_voltage_linear, @@ -369,6 +433,68 @@ static struct regulator_ops rk808_switch_ops = { .set_suspend_disable = rk808_set_suspend_disable, }; +static const struct regulator_desc rk805_reg[] = { + { + .name = "DCDC_REG1", + .supply_name = "vcc1", + .of_match = of_match_ptr("DCDC_REG1"), + .regulators_node = of_match_ptr("regulators"), + .id = RK805_ID_DCDC1, + .ops = &rk805_reg_ops, + .type = REGULATOR_VOLTAGE, + .min_uV = 712500, + .uV_step = 12500, + .n_voltages = 64, + .vsel_reg = RK805_BUCK1_ON_VSEL_REG, + .vsel_mask = RK818_BUCK_VSEL_MASK, + .enable_reg = RK805_DCDC_EN_REG, + .enable_mask = BIT(0), + .owner = THIS_MODULE, + }, { + .name = "DCDC_REG2", + .supply_name = "vcc2", + .of_match = of_match_ptr("DCDC_REG2"), + .regulators_node = of_match_ptr("regulators"), + .id = RK805_ID_DCDC2, + .ops = &rk805_reg_ops, + .type = REGULATOR_VOLTAGE, + .min_uV = 712500, + .uV_step = 12500, + .n_voltages = 64, + .vsel_reg = RK805_BUCK2_ON_VSEL_REG, + .vsel_mask = RK818_BUCK_VSEL_MASK, + .enable_reg = RK805_DCDC_EN_REG, + .enable_mask = BIT(1), + .owner = THIS_MODULE, + }, { + .name = "DCDC_REG3", + .supply_name = "vcc3", + .of_match = of_match_ptr("DCDC_REG3"), + .regulators_node = of_match_ptr("regulators"), + .id = RK805_ID_DCDC3, + .ops = &rk805_switch_ops, + .type = REGULATOR_VOLTAGE, + .n_voltages = 1, + .enable_reg = RK805_DCDC_EN_REG, + .enable_mask = BIT(2), + .owner = THIS_MODULE, + }, + + RK805_DESC(RK805_ID_DCDC4, "DCDC_REG4", "vcc4", 800, 3400, 100, + RK805_BUCK4_ON_VSEL_REG, RK818_BUCK4_VSEL_MASK, + RK805_DCDC_EN_REG, BIT(3), 0), + + RK805_DESC(RK805_ID_LDO1, "LDO_REG1", "vcc5", 800, 3400, 100, + RK805_LDO1_ON_VSEL_REG, RK818_LDO_VSEL_MASK, RK805_LDO_EN_REG, + BIT(0), 400), + RK805_DESC(RK805_ID_LDO2, "LDO_REG2", "vcc5", 800, 3400, 100, + RK805_LDO2_ON_VSEL_REG, RK818_LDO_VSEL_MASK, RK805_LDO_EN_REG, + BIT(1), 400), + RK805_DESC(RK805_ID_LDO3, "LDO_REG3", "vcc6", 800, 3400, 100, + RK805_LDO3_ON_VSEL_REG, RK818_LDO_VSEL_MASK, RK805_LDO_EN_REG, + BIT(2), 400), +}; + static const struct regulator_desc rk808_reg[] = { { .name = "DCDC_REG1", @@ -625,6 +751,10 @@ static int rk808_regulator_probe(struct platform_device *pdev) platform_set_drvdata(pdev, pdata); switch (rk808->variant) { + case RK805_ID: + regulators = rk805_reg; + nregulators = RK805_NUM_REGULATORS; + break; case RK808_ID: regulators = rk808_reg; nregulators = RK808_NUM_REGULATORS; -- cgit v1.1 From 990f05f6a5213be50ff48bf0461e2db254817b0c Mon Sep 17 00:00:00 2001 From: Elaine Zhang Date: Mon, 21 Aug 2017 03:28:38 +0200 Subject: mfd: rk808: Add RK805 support The RK805 chip is a Power Management IC (PMIC) for multimedia and handheld devices. It contains the following components: - Regulators - RTC - Clocking Both RK808 and RK805 chips are using a similar register map, so we can reuse the RTC and Clocking functionality. Signed-off-by: Elaine Zhang Signed-off-by: Joseph Chen Signed-off-by: Heiko Stuebner Signed-off-by: Lee Jones --- drivers/mfd/Kconfig | 4 +- drivers/mfd/rk808.c | 108 ++++++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 110 insertions(+), 2 deletions(-) diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig index 94ad2c1..38d3ea4 100644 --- a/drivers/mfd/Kconfig +++ b/drivers/mfd/Kconfig @@ -951,13 +951,13 @@ config MFD_RC5T583 different functionality of the device. config MFD_RK808 - tristate "Rockchip RK808/RK818 Power Management Chip" + tristate "Rockchip RK805/RK808/RK818 Power Management Chip" depends on I2C && OF select MFD_CORE select REGMAP_I2C select REGMAP_IRQ help - If you say yes here you get support for the RK808 and RK818 + If you say yes here you get support for the RK805, RK808 and RK818 Power Management chips. This driver provides common support for accessing the device through I2C interface. The device supports multiple sub-devices diff --git a/drivers/mfd/rk808.c b/drivers/mfd/rk808.c index 8e60eba..18329c8 100644 --- a/drivers/mfd/rk808.c +++ b/drivers/mfd/rk808.c @@ -70,6 +70,14 @@ static const struct regmap_config rk818_regmap_config = { .volatile_reg = rk808_is_volatile_reg, }; +static const struct regmap_config rk805_regmap_config = { + .reg_bits = 8, + .val_bits = 8, + .max_register = RK805_OFF_SOURCE_REG, + .cache_type = REGCACHE_RBTREE, + .volatile_reg = rk808_is_volatile_reg, +}; + static const struct regmap_config rk808_regmap_config = { .reg_bits = 8, .val_bits = 8, @@ -86,6 +94,16 @@ static struct resource rtc_resources[] = { } }; +static const struct mfd_cell rk805s[] = { + { .name = "rk808-clkout", }, + { .name = "rk808-regulator", }, + { + .name = "rk808-rtc", + .num_resources = ARRAY_SIZE(rtc_resources), + .resources = &rtc_resources[0], + }, +}; + static const struct mfd_cell rk808s[] = { { .name = "rk808-clkout", }, { .name = "rk808-regulator", }, @@ -106,6 +124,20 @@ static const struct mfd_cell rk818s[] = { }, }; +static const struct rk808_reg_data rk805_pre_init_reg[] = { + {RK805_BUCK1_CONFIG_REG, RK805_BUCK1_2_ILMAX_MASK, + RK805_BUCK1_2_ILMAX_4000MA}, + {RK805_BUCK2_CONFIG_REG, RK805_BUCK1_2_ILMAX_MASK, + RK805_BUCK1_2_ILMAX_4000MA}, + {RK805_BUCK3_CONFIG_REG, RK805_BUCK3_4_ILMAX_MASK, + RK805_BUCK3_ILMAX_3000MA}, + {RK805_BUCK4_CONFIG_REG, RK805_BUCK3_4_ILMAX_MASK, + RK805_BUCK4_ILMAX_3500MA}, + {RK805_BUCK4_CONFIG_REG, BUCK_ILMIN_MASK, BUCK_ILMIN_400MA}, + {RK805_GPIO_IO_POL_REG, SLP_SD_MSK, SLEEP_FUN}, + {RK805_THERMAL_REG, TEMP_HOTDIE_MSK, TEMP115C}, +}; + static const struct rk808_reg_data rk808_pre_init_reg[] = { { RK808_BUCK3_CONFIG_REG, BUCK_ILMIN_MASK, BUCK_ILMIN_150MA }, { RK808_BUCK4_CONFIG_REG, BUCK_ILMIN_MASK, BUCK_ILMIN_200MA }, @@ -135,6 +167,41 @@ static const struct rk808_reg_data rk818_pre_init_reg[] = { VB_LO_SEL_3500MV }, }; +static const struct regmap_irq rk805_irqs[] = { + [RK805_IRQ_PWRON_RISE] = { + .mask = RK805_IRQ_PWRON_RISE_MSK, + .reg_offset = 0, + }, + [RK805_IRQ_VB_LOW] = { + .mask = RK805_IRQ_VB_LOW_MSK, + .reg_offset = 0, + }, + [RK805_IRQ_PWRON] = { + .mask = RK805_IRQ_PWRON_MSK, + .reg_offset = 0, + }, + [RK805_IRQ_PWRON_LP] = { + .mask = RK805_IRQ_PWRON_LP_MSK, + .reg_offset = 0, + }, + [RK805_IRQ_HOTDIE] = { + .mask = RK805_IRQ_HOTDIE_MSK, + .reg_offset = 0, + }, + [RK805_IRQ_RTC_ALARM] = { + .mask = RK805_IRQ_RTC_ALARM_MSK, + .reg_offset = 0, + }, + [RK805_IRQ_RTC_PERIOD] = { + .mask = RK805_IRQ_RTC_PERIOD_MSK, + .reg_offset = 0, + }, + [RK805_IRQ_PWRON_FALL] = { + .mask = RK805_IRQ_PWRON_FALL_MSK, + .reg_offset = 0, + }, +}; + static const struct regmap_irq rk808_irqs[] = { /* INT_STS */ [RK808_IRQ_VOUT_LO] = { @@ -247,6 +314,17 @@ static const struct regmap_irq rk818_irqs[] = { }, }; +static struct regmap_irq_chip rk805_irq_chip = { + .name = "rk805", + .irqs = rk805_irqs, + .num_irqs = ARRAY_SIZE(rk805_irqs), + .num_regs = 1, + .status_base = RK805_INT_STS_REG, + .mask_base = RK805_INT_STS_MSK_REG, + .ack_base = RK805_INT_STS_REG, + .init_ack_masked = true, +}; + static const struct regmap_irq_chip rk808_irq_chip = { .name = "rk808", .irqs = rk808_irqs, @@ -272,6 +350,25 @@ static const struct regmap_irq_chip rk818_irq_chip = { }; static struct i2c_client *rk808_i2c_client; + +static void rk805_device_shutdown(void) +{ + int ret; + struct rk808 *rk808 = i2c_get_clientdata(rk808_i2c_client); + + if (!rk808) { + dev_warn(&rk808_i2c_client->dev, + "have no rk805, so do nothing here\n"); + return; + } + + ret = regmap_update_bits(rk808->regmap, + RK805_DEV_CTRL_REG, + DEV_OFF, DEV_OFF); + if (ret) + dev_err(&rk808_i2c_client->dev, "power off error!\n"); +} + static void rk808_device_shutdown(void) { int ret; @@ -309,6 +406,7 @@ static void rk818_device_shutdown(void) } static const struct of_device_id rk808_of_match[] = { + { .compatible = "rockchip,rk805" }, { .compatible = "rockchip,rk808" }, { .compatible = "rockchip,rk818" }, { }, @@ -352,6 +450,15 @@ static int rk808_probe(struct i2c_client *client, dev_info(&client->dev, "chip id: 0x%x\n", (unsigned int)rk808->variant); switch (rk808->variant) { + case RK805_ID: + rk808->regmap_cfg = &rk805_regmap_config; + rk808->regmap_irq_chip = &rk805_irq_chip; + pre_init_reg = rk805_pre_init_reg; + nr_pre_init_regs = ARRAY_SIZE(rk805_pre_init_reg); + cells = rk805s; + nr_cells = ARRAY_SIZE(rk805s); + pm_pwroff_fn = rk805_device_shutdown; + break; case RK808_ID: rk808->regmap_cfg = &rk808_regmap_config; rk808->regmap_irq_chip = &rk808_irq_chip; @@ -444,6 +551,7 @@ static int rk808_remove(struct i2c_client *client) } static const struct i2c_device_id rk808_ids[] = { + { "rk805" }, { "rk808" }, { "rk818" }, { }, -- cgit v1.1 From d9e616897432d53b40ced69c6c2b1365351d99ac Mon Sep 17 00:00:00 2001 From: Elaine Zhang Date: Mon, 21 Aug 2017 03:28:37 +0200 Subject: mfd: dt-bindings: Add RK805 device tree bindings document Add device tree bindings documentation for Rockchip's RK805 PMIC. Signed-off-by: Elaine Zhang Signed-off-by: Joseph Chen Acked-by: Rob Herring Signed-off-by: Heiko Stuebner Signed-off-by: Lee Jones --- Documentation/devicetree/bindings/mfd/rk808.txt | 22 +++++++++++++++++++++- 1 file changed, 21 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/mfd/rk808.txt b/Documentation/devicetree/bindings/mfd/rk808.txt index 9636ae8..91b6522 100644 --- a/Documentation/devicetree/bindings/mfd/rk808.txt +++ b/Documentation/devicetree/bindings/mfd/rk808.txt @@ -1,11 +1,14 @@ RK8XX Power Management Integrated Circuit The rk8xx family current members: +rk805 rk808 rk818 Required properties: -- compatible: "rockchip,rk808", "rockchip,rk818" +- compatible: "rockchip,rk805" +- compatible: "rockchip,rk808" +- compatible: "rockchip,rk818" - reg: I2C slave address - interrupt-parent: The parent interrupt controller. - interrupts: the interrupt outputs of the controller. @@ -18,6 +21,14 @@ Optional properties: - rockchip,system-power-controller: Telling whether or not this pmic is controlling the system power. +Optional RK805 properties: +- vcc1-supply: The input supply for DCDC_REG1 +- vcc2-supply: The input supply for DCDC_REG2 +- vcc3-supply: The input supply for DCDC_REG3 +- vcc4-supply: The input supply for DCDC_REG4 +- vcc5-supply: The input supply for LDO_REG1 and LDO_REG2 +- vcc6-supply: The input supply for LDO_REG3 + Optional RK808 properties: - vcc1-supply: The input supply for DCDC_REG1 - vcc2-supply: The input supply for DCDC_REG2 @@ -56,6 +67,15 @@ by a child node of the 'regulators' node. /* standard regulator bindings here */ }; +Following regulators of the RK805 PMIC regulators are supported. Note that +the 'n' in regulator name, as in DCDC_REGn or LDOn, represents the DCDC or LDO +number as described in RK805 datasheet. + + - DCDC_REGn + - valid values for n are 1 to 4. + - LDO_REGn + - valid values for n are 1 to 3 + Following regulators of the RK808 PMIC block are supported. Note that the 'n' in regulator name, as in DCDC_REGn or LDOn, represents the DCDC or LDO number as described in RK808 datasheet. -- cgit v1.1 From 5b0bb001d37175324e613488ac6a8e981d473c11 Mon Sep 17 00:00:00 2001 From: Joseph Chen Date: Mon, 21 Aug 2017 03:28:39 +0200 Subject: pinctrl: dt-bindings: Add bindings for Rockchip RK805 PMIC Signed-off-by: Joseph Chen Acked-by: Linus Walleij Acked-by: Rob Herring Signed-off-by: Heiko Stuebner Signed-off-by: Lee Jones --- .../devicetree/bindings/pinctrl/pinctrl-rk805.txt | 63 ++++++++++++++++++++++ 1 file changed, 63 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/pinctrl-rk805.txt diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-rk805.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-rk805.txt new file mode 100644 index 0000000..eee3dc2 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-rk805.txt @@ -0,0 +1,63 @@ +Pincontrol driver for RK805 Power management IC. + +RK805 has 2 pins which can be configured as GPIO output only. + +Please refer file +for details of the common pinctrl bindings used by client devices, +including the meaning of the phrase "pin configuration node". + +Optional Pinmux properties: +-------------------------- +Following properties are required if default setting of pins are required +at boot. +- pinctrl-names: A pinctrl state named per . +- pinctrl[0...n]: Properties to contain the phandle for pinctrl states per + . + +The pin configurations are defined as child of the pinctrl states node. Each +sub-node have following properties: + +Required properties: +------------------ +- #gpio-cells: Should be two. The first cell is the pin number and the + second is the GPIO flags. + +- gpio-controller: Marks the device node as a GPIO controller. + +- pins: List of pins. Valid values of pins properties are: gpio0, gpio1. + +First 2 properties must be added in the RK805 PMIC node, documented in +Documentation/devicetree/bindings/mfd/rk808.txt + +Optional properties: +------------------- +Following are optional properties defined as pinmux DT binding document +. Absence of properties will leave the configuration +on default. + function, + output-low, + output-high. + +Valid values for function properties are: gpio. + +Theres is also not customised properties for any GPIO. + +Example: +-------- +rk805: rk805@18 { + compatible = "rockchip,rk805"; + ... + gpio-controller; + #gpio-cells = <2>; + + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int_l>, <&rk805_default>; + + rk805_default: pinmux { + gpio01 { + pins = "gpio0", "gpio1"; + function = "gpio"; + output-high; + }; + }; +}; -- cgit v1.1 From ea479996c79bbd631e014c2492d268bb05e86f9a Mon Sep 17 00:00:00 2001 From: Joseph Chen Date: Mon, 21 Aug 2017 03:28:40 +0200 Subject: pinctrl: Add pinctrl driver for the RK805 PMIC RK805 is one of Rockchip PMICs family, it has 2 output only GPIOs. This driver is also designed for other Rockchip PMICs to expend. Different PMIC maybe have different pin features, for example, RK816 has one pin which can be used for TS or GPIO(input/out). The mainly difference between PMICs pins are pinmux, direction and output value, that is 'struct rk805_pin_config'. Signed-off-by: Joseph Chen Acked-by: Linus Walleij Signed-off-by: Heiko Stuebner Signed-off-by: Lee Jones --- drivers/pinctrl/Kconfig | 9 + drivers/pinctrl/Makefile | 1 + drivers/pinctrl/pinctrl-rk805.c | 493 ++++++++++++++++++++++++++++++++++++++++ 3 files changed, 503 insertions(+) create mode 100644 drivers/pinctrl/pinctrl-rk805.c diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index e14b46c..124fe2c 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -331,6 +331,15 @@ config PINCTRL_INGENIC select GENERIC_PINMUX_FUNCTIONS select REGMAP_MMIO +config PINCTRL_RK805 + tristate "Pinctrl and GPIO driver for RK805 PMIC" + depends on MFD_RK808 + select GPIOLIB + select PINMUX + select GENERIC_PINCONF + help + This selects the pinctrl driver for RK805. + source "drivers/pinctrl/aspeed/Kconfig" source "drivers/pinctrl/bcm/Kconfig" source "drivers/pinctrl/berlin/Kconfig" diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile index 2bc641d..792ffae 100644 --- a/drivers/pinctrl/Makefile +++ b/drivers/pinctrl/Makefile @@ -42,6 +42,7 @@ obj-$(CONFIG_PINCTRL_TB10X) += pinctrl-tb10x.o obj-$(CONFIG_PINCTRL_ST) += pinctrl-st.o obj-$(CONFIG_PINCTRL_ZYNQ) += pinctrl-zynq.o obj-$(CONFIG_PINCTRL_INGENIC) += pinctrl-ingenic.o +obj-$(CONFIG_PINCTRL_RK805) += pinctrl-rk805.o obj-$(CONFIG_ARCH_ASPEED) += aspeed/ obj-y += bcm/ diff --git a/drivers/pinctrl/pinctrl-rk805.c b/drivers/pinctrl/pinctrl-rk805.c new file mode 100644 index 0000000..b0bfd30 --- /dev/null +++ b/drivers/pinctrl/pinctrl-rk805.c @@ -0,0 +1,493 @@ +/* + * Pinctrl driver for Rockchip RK805 PMIC + * + * Copyright (c) 2017, Fuzhou Rockchip Electronics Co., Ltd + * + * Author: Joseph Chen + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * Based on the pinctrl-as3722 driver + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "core.h" +#include "pinconf.h" +#include "pinctrl-utils.h" + +struct rk805_pin_function { + const char *name; + const char *const *groups; + unsigned int ngroups; + int mux_option; +}; + +struct rk805_pin_group { + const char *name; + const unsigned int pins[1]; + unsigned int npins; +}; + +/* + * @reg: gpio setting register; + * @fun_mask: functions select mask value, when set is gpio; + * @dir_mask: input or output mask value, when set is output, otherwise input; + * @val_mask: gpio set value, when set is level high, otherwise low; + * + * Different PMIC has different pin features, belowing 3 mask members are not + * all necessary for every PMIC. For example, RK805 has 2 pins that can be used + * as output only GPIOs, so func_mask and dir_mask are not needed. RK816 has 1 + * pin that can be used as TS/GPIO, so fun_mask, dir_mask and val_mask are all + * necessary. + */ +struct rk805_pin_config { + u8 reg; + u8 fun_msk; + u8 dir_msk; + u8 val_msk; +}; + +struct rk805_pctrl_info { + struct rk808 *rk808; + struct device *dev; + struct pinctrl_dev *pctl; + struct gpio_chip gpio_chip; + struct pinctrl_desc pinctrl_desc; + const struct rk805_pin_function *functions; + unsigned int num_functions; + const struct rk805_pin_group *groups; + int num_pin_groups; + const struct pinctrl_pin_desc *pins; + unsigned int num_pins; + struct rk805_pin_config *pin_cfg; +}; + +enum rk805_pinmux_option { + RK805_PINMUX_GPIO, +}; + +enum { + RK805_GPIO0, + RK805_GPIO1, +}; + +static const char *const rk805_gpio_groups[] = { + "gpio0", + "gpio1", +}; + +/* RK805: 2 output only GPIOs */ +static const struct pinctrl_pin_desc rk805_pins_desc[] = { + PINCTRL_PIN(RK805_GPIO0, "gpio0"), + PINCTRL_PIN(RK805_GPIO1, "gpio1"), +}; + +static const struct rk805_pin_function rk805_pin_functions[] = { + { + .name = "gpio", + .groups = rk805_gpio_groups, + .ngroups = ARRAY_SIZE(rk805_gpio_groups), + .mux_option = RK805_PINMUX_GPIO, + }, +}; + +static const struct rk805_pin_group rk805_pin_groups[] = { + { + .name = "gpio0", + .pins = { RK805_GPIO0 }, + .npins = 1, + }, + { + .name = "gpio1", + .pins = { RK805_GPIO1 }, + .npins = 1, + }, +}; + +#define RK805_GPIO0_VAL_MSK BIT(0) +#define RK805_GPIO1_VAL_MSK BIT(1) + +static struct rk805_pin_config rk805_gpio_cfgs[] = { + { + .reg = RK805_OUT_REG, + .val_msk = RK805_GPIO0_VAL_MSK, + }, + { + .reg = RK805_OUT_REG, + .val_msk = RK805_GPIO1_VAL_MSK, + }, +}; + +/* generic gpio chip */ +static int rk805_gpio_get(struct gpio_chip *chip, unsigned int offset) +{ + struct rk805_pctrl_info *pci = gpiochip_get_data(chip); + int ret, val; + + ret = regmap_read(pci->rk808->regmap, pci->pin_cfg[offset].reg, &val); + if (ret) { + dev_err(pci->dev, "get gpio%d value failed\n", offset); + return ret; + } + + return !!(val & pci->pin_cfg[offset].val_msk); +} + +static void rk805_gpio_set(struct gpio_chip *chip, + unsigned int offset, + int value) +{ + struct rk805_pctrl_info *pci = gpiochip_get_data(chip); + int ret; + + ret = regmap_update_bits(pci->rk808->regmap, + pci->pin_cfg[offset].reg, + pci->pin_cfg[offset].val_msk, + value ? pci->pin_cfg[offset].val_msk : 0); + if (ret) + dev_err(pci->dev, "set gpio%d value %d failed\n", + offset, value); +} + +static int rk805_gpio_direction_input(struct gpio_chip *chip, + unsigned int offset) +{ + return pinctrl_gpio_direction_input(chip->base + offset); +} + +static int rk805_gpio_direction_output(struct gpio_chip *chip, + unsigned int offset, int value) +{ + rk805_gpio_set(chip, offset, value); + return pinctrl_gpio_direction_output(chip->base + offset); +} + +static int rk805_gpio_get_direction(struct gpio_chip *chip, unsigned int offset) +{ + struct rk805_pctrl_info *pci = gpiochip_get_data(chip); + unsigned int val; + int ret; + + /* default output*/ + if (!pci->pin_cfg[offset].dir_msk) + return 0; + + ret = regmap_read(pci->rk808->regmap, + pci->pin_cfg[offset].reg, + &val); + if (ret) { + dev_err(pci->dev, "get gpio%d direction failed\n", offset); + return ret; + } + + return !(val & pci->pin_cfg[offset].dir_msk); +} + +static struct gpio_chip rk805_gpio_chip = { + .label = "rk805-gpio", + .request = gpiochip_generic_request, + .free = gpiochip_generic_free, + .get_direction = rk805_gpio_get_direction, + .get = rk805_gpio_get, + .set = rk805_gpio_set, + .direction_input = rk805_gpio_direction_input, + .direction_output = rk805_gpio_direction_output, + .can_sleep = true, + .base = -1, + .owner = THIS_MODULE, +}; + +/* generic pinctrl */ +static int rk805_pinctrl_get_groups_count(struct pinctrl_dev *pctldev) +{ + struct rk805_pctrl_info *pci = pinctrl_dev_get_drvdata(pctldev); + + return pci->num_pin_groups; +} + +static const char *rk805_pinctrl_get_group_name(struct pinctrl_dev *pctldev, + unsigned int group) +{ + struct rk805_pctrl_info *pci = pinctrl_dev_get_drvdata(pctldev); + + return pci->groups[group].name; +} + +static int rk805_pinctrl_get_group_pins(struct pinctrl_dev *pctldev, + unsigned int group, + const unsigned int **pins, + unsigned int *num_pins) +{ + struct rk805_pctrl_info *pci = pinctrl_dev_get_drvdata(pctldev); + + *pins = pci->groups[group].pins; + *num_pins = pci->groups[group].npins; + + return 0; +} + +static const struct pinctrl_ops rk805_pinctrl_ops = { + .get_groups_count = rk805_pinctrl_get_groups_count, + .get_group_name = rk805_pinctrl_get_group_name, + .get_group_pins = rk805_pinctrl_get_group_pins, + .dt_node_to_map = pinconf_generic_dt_node_to_map_pin, + .dt_free_map = pinctrl_utils_free_map, +}; + +static int rk805_pinctrl_get_funcs_count(struct pinctrl_dev *pctldev) +{ + struct rk805_pctrl_info *pci = pinctrl_dev_get_drvdata(pctldev); + + return pci->num_functions; +} + +static const char *rk805_pinctrl_get_func_name(struct pinctrl_dev *pctldev, + unsigned int function) +{ + struct rk805_pctrl_info *pci = pinctrl_dev_get_drvdata(pctldev); + + return pci->functions[function].name; +} + +static int rk805_pinctrl_get_func_groups(struct pinctrl_dev *pctldev, + unsigned int function, + const char *const **groups, + unsigned int *const num_groups) +{ + struct rk805_pctrl_info *pci = pinctrl_dev_get_drvdata(pctldev); + + *groups = pci->functions[function].groups; + *num_groups = pci->functions[function].ngroups; + + return 0; +} + +static int _rk805_pinctrl_set_mux(struct pinctrl_dev *pctldev, + unsigned int offset, + int mux) +{ + struct rk805_pctrl_info *pci = pinctrl_dev_get_drvdata(pctldev); + int ret; + + if (!pci->pin_cfg[offset].fun_msk) + return 0; + + if (mux == RK805_PINMUX_GPIO) { + ret = regmap_update_bits(pci->rk808->regmap, + pci->pin_cfg[offset].reg, + pci->pin_cfg[offset].fun_msk, + pci->pin_cfg[offset].fun_msk); + if (ret) { + dev_err(pci->dev, "set gpio%d GPIO failed\n", offset); + return ret; + } + } else { + dev_err(pci->dev, "Couldn't find function mux %d\n", mux); + return -EINVAL; + } + + return 0; +} + +static int rk805_pinctrl_set_mux(struct pinctrl_dev *pctldev, + unsigned int function, + unsigned int group) +{ + struct rk805_pctrl_info *pci = pinctrl_dev_get_drvdata(pctldev); + int mux = pci->functions[function].mux_option; + int offset = group; + + return _rk805_pinctrl_set_mux(pctldev, offset, mux); +} + +static int rk805_pmx_gpio_set_direction(struct pinctrl_dev *pctldev, + struct pinctrl_gpio_range *range, + unsigned int offset, bool input) +{ + struct rk805_pctrl_info *pci = pinctrl_dev_get_drvdata(pctldev); + int ret; + + /* switch to gpio function */ + ret = _rk805_pinctrl_set_mux(pctldev, offset, RK805_PINMUX_GPIO); + if (ret) { + dev_err(pci->dev, "set gpio%d mux failed\n", offset); + return ret; + } + + /* set direction */ + if (!pci->pin_cfg[offset].dir_msk) + return 0; + + ret = regmap_update_bits(pci->rk808->regmap, + pci->pin_cfg[offset].reg, + pci->pin_cfg[offset].dir_msk, + input ? 0 : pci->pin_cfg[offset].dir_msk); + if (ret) { + dev_err(pci->dev, "set gpio%d direction failed\n", offset); + return ret; + } + + return ret; +} + +static const struct pinmux_ops rk805_pinmux_ops = { + .get_functions_count = rk805_pinctrl_get_funcs_count, + .get_function_name = rk805_pinctrl_get_func_name, + .get_function_groups = rk805_pinctrl_get_func_groups, + .set_mux = rk805_pinctrl_set_mux, + .gpio_set_direction = rk805_pmx_gpio_set_direction, +}; + +static int rk805_pinconf_get(struct pinctrl_dev *pctldev, + unsigned int pin, unsigned long *config) +{ + struct rk805_pctrl_info *pci = pinctrl_dev_get_drvdata(pctldev); + enum pin_config_param param = pinconf_to_config_param(*config); + u32 arg = 0; + + switch (param) { + case PIN_CONFIG_OUTPUT: + arg = rk805_gpio_get(&pci->gpio_chip, pin); + break; + default: + dev_err(pci->dev, "Properties not supported\n"); + return -ENOTSUPP; + } + + *config = pinconf_to_config_packed(param, (u16)arg); + + return 0; +} + +static int rk805_pinconf_set(struct pinctrl_dev *pctldev, + unsigned int pin, unsigned long *configs, + unsigned int num_configs) +{ + struct rk805_pctrl_info *pci = pinctrl_dev_get_drvdata(pctldev); + enum pin_config_param param; + u32 i, arg = 0; + + for (i = 0; i < num_configs; i++) { + param = pinconf_to_config_param(configs[i]); + arg = pinconf_to_config_argument(configs[i]); + + switch (param) { + case PIN_CONFIG_OUTPUT: + rk805_gpio_set(&pci->gpio_chip, pin, arg); + rk805_pmx_gpio_set_direction(pctldev, NULL, pin, false); + break; + default: + dev_err(pci->dev, "Properties not supported\n"); + return -ENOTSUPP; + } + } + + return 0; +} + +static const struct pinconf_ops rk805_pinconf_ops = { + .pin_config_get = rk805_pinconf_get, + .pin_config_set = rk805_pinconf_set, +}; + +static struct pinctrl_desc rk805_pinctrl_desc = { + .name = "rk805-pinctrl", + .pctlops = &rk805_pinctrl_ops, + .pmxops = &rk805_pinmux_ops, + .confops = &rk805_pinconf_ops, + .owner = THIS_MODULE, +}; + +static int rk805_pinctrl_probe(struct platform_device *pdev) +{ + struct rk805_pctrl_info *pci; + int ret; + + pci = devm_kzalloc(&pdev->dev, sizeof(*pci), GFP_KERNEL); + if (!pci) + return -ENOMEM; + + pci->dev = &pdev->dev; + pci->dev->of_node = pdev->dev.parent->of_node; + pci->rk808 = dev_get_drvdata(pdev->dev.parent); + + pci->pinctrl_desc = rk805_pinctrl_desc; + pci->gpio_chip = rk805_gpio_chip; + pci->gpio_chip.parent = &pdev->dev; + pci->gpio_chip.of_node = pdev->dev.parent->of_node; + + platform_set_drvdata(pdev, pci); + + switch (pci->rk808->variant) { + case RK805_ID: + pci->pins = rk805_pins_desc; + pci->num_pins = ARRAY_SIZE(rk805_pins_desc); + pci->functions = rk805_pin_functions; + pci->num_functions = ARRAY_SIZE(rk805_pin_functions); + pci->groups = rk805_pin_groups; + pci->num_pin_groups = ARRAY_SIZE(rk805_pin_groups); + pci->pinctrl_desc.pins = rk805_pins_desc; + pci->pinctrl_desc.npins = ARRAY_SIZE(rk805_pins_desc); + pci->pin_cfg = rk805_gpio_cfgs; + pci->gpio_chip.ngpio = ARRAY_SIZE(rk805_gpio_cfgs); + break; + default: + dev_err(&pdev->dev, "unsupported RK805 ID %lu\n", + pci->rk808->variant); + return -EINVAL; + } + + /* Add gpio chip */ + ret = devm_gpiochip_add_data(&pdev->dev, &pci->gpio_chip, pci); + if (ret < 0) { + dev_err(&pdev->dev, "Couldn't add gpiochip\n"); + return ret; + } + + /* Add pinctrl */ + pci->pctl = devm_pinctrl_register(&pdev->dev, &pci->pinctrl_desc, pci); + if (IS_ERR(pci->pctl)) { + dev_err(&pdev->dev, "Couldn't add pinctrl\n"); + return PTR_ERR(pci->pctl); + } + + /* Add pin range */ + ret = gpiochip_add_pin_range(&pci->gpio_chip, dev_name(&pdev->dev), + 0, 0, pci->gpio_chip.ngpio); + if (ret < 0) { + dev_err(&pdev->dev, "Couldn't add gpiochip pin range\n"); + return ret; + } + + return 0; +} + +static struct platform_driver rk805_pinctrl_driver = { + .probe = rk805_pinctrl_probe, + .driver = { + .name = "rk805-pinctrl", + }, +}; +module_platform_driver(rk805_pinctrl_driver); + +MODULE_DESCRIPTION("RK805 pin control and GPIO driver"); +MODULE_AUTHOR("Joseph Chen "); +MODULE_LICENSE("GPL v2"); -- cgit v1.1 From 8d249b67c785d48c5aa526b47495f7c88a62f73e Mon Sep 17 00:00:00 2001 From: Joseph Chen Date: Mon, 21 Aug 2017 03:28:41 +0200 Subject: mfd: rk808: Add RK805 pinctrl support Signed-off-by: Joseph Chen Acked-by: Linus Walleij Signed-off-by: Heiko Stuebner Signed-off-by: Lee Jones --- drivers/mfd/rk808.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/mfd/rk808.c b/drivers/mfd/rk808.c index 18329c8..c803d2d 100644 --- a/drivers/mfd/rk808.c +++ b/drivers/mfd/rk808.c @@ -97,6 +97,7 @@ static struct resource rtc_resources[] = { static const struct mfd_cell rk805s[] = { { .name = "rk808-clkout", }, { .name = "rk808-regulator", }, + { .name = "rk805-pinctrl", }, { .name = "rk808-rtc", .num_resources = ARRAY_SIZE(rtc_resources), -- cgit v1.1 From f7c22398f5e95c995a34d4f196d53cfc32562aed Mon Sep 17 00:00:00 2001 From: Joseph Chen Date: Mon, 21 Aug 2017 03:28:42 +0200 Subject: mfd: rk808: Add RK805 power key support Signed-off-by: Joseph Chen Signed-off-by: Heiko Stuebner Signed-off-by: Lee Jones --- drivers/mfd/rk808.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/drivers/mfd/rk808.c b/drivers/mfd/rk808.c index c803d2d..216fbf6 100644 --- a/drivers/mfd/rk808.c +++ b/drivers/mfd/rk808.c @@ -94,6 +94,19 @@ static struct resource rtc_resources[] = { } }; +static struct resource rk805_key_resources[] = { + { + .start = RK805_IRQ_PWRON_FALL, + .end = RK805_IRQ_PWRON_FALL, + .flags = IORESOURCE_IRQ, + }, + { + .start = RK805_IRQ_PWRON_RISE, + .end = RK805_IRQ_PWRON_RISE, + .flags = IORESOURCE_IRQ, + } +}; + static const struct mfd_cell rk805s[] = { { .name = "rk808-clkout", }, { .name = "rk808-regulator", }, @@ -103,6 +116,10 @@ static const struct mfd_cell rk805s[] = { .num_resources = ARRAY_SIZE(rtc_resources), .resources = &rtc_resources[0], }, + { .name = "rk805-pwrkey", + .num_resources = ARRAY_SIZE(rk805_key_resources), + .resources = &rk805_key_resources[0], + }, }; static const struct mfd_cell rk808s[] = { -- cgit v1.1 From a205425658dead19bb1b8ac00584aed98e60dde2 Mon Sep 17 00:00:00 2001 From: Wolfram Sang Date: Mon, 14 Aug 2017 18:34:24 +0200 Subject: mfd: twl: Move header file out of I2C realm include/linux/i2c is not for client devices. Move the header file to a more appropriate location. Signed-off-by: Wolfram Sang Acked-by: Greg Kroah-Hartman Acked-by: Alexandre Belloni Acked-by: Mark Brown Acked-by: Sebastian Reichel Acked-by: Jonathan Cameron Acked-by: Dmitry Torokhov Acked-by: Kishon Vijay Abraham I Acked-by: Bartlomiej Zolnierkiewicz Acked-by: Thierry Reding Acked-by: Tony Lindgren Acked-by: Daniel Thompson Acked-by: Linus Walleij Acked-by: Guenter Roeck Signed-off-by: Lee Jones --- arch/arm/mach-omap2/common.h | 2 +- arch/arm/mach-omap2/omap_twl.c | 2 +- drivers/gpio/gpio-twl4030.c | 2 +- drivers/iio/adc/twl4030-madc.c | 2 +- drivers/iio/adc/twl6030-gpadc.c | 2 +- drivers/input/keyboard/twl4030_keypad.c | 2 +- drivers/input/misc/twl4030-pwrbutton.c | 2 +- drivers/input/misc/twl4030-vibra.c | 2 +- drivers/mfd/twl-core.c | 6 +- drivers/mfd/twl4030-audio.c | 2 +- drivers/mfd/twl4030-irq.c | 2 +- drivers/mfd/twl4030-power.c | 2 +- drivers/mfd/twl6030-irq.c | 2 +- drivers/phy/ti/phy-twl4030-usb.c | 2 +- drivers/power/supply/twl4030_charger.c | 2 +- drivers/pwm/pwm-twl-led.c | 2 +- drivers/pwm/pwm-twl.c | 2 +- drivers/regulator/twl-regulator.c | 2 +- drivers/regulator/twl6030-regulator.c | 2 +- drivers/rtc/rtc-twl.c | 2 +- drivers/usb/phy/phy-twl6030-usb.c | 2 +- drivers/video/backlight/pandora_bl.c | 2 +- drivers/watchdog/twl4030_wdt.c | 2 +- include/linux/i2c/twl.h | 876 -------------------------------- include/linux/mfd/twl.h | 876 ++++++++++++++++++++++++++++++++ sound/soc/codecs/twl4030.c | 2 +- 26 files changed, 902 insertions(+), 902 deletions(-) delete mode 100644 include/linux/i2c/twl.h create mode 100644 include/linux/mfd/twl.h diff --git a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h index 8cc6338..b5ad7fc 100644 --- a/arch/arm/mach-omap2/common.h +++ b/arch/arm/mach-omap2/common.h @@ -29,7 +29,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/arch/arm/mach-omap2/omap_twl.c b/arch/arm/mach-omap2/omap_twl.c index 1346b3a..295124b 100644 --- a/arch/arm/mach-omap2/omap_twl.c +++ b/arch/arm/mach-omap2/omap_twl.c @@ -16,7 +16,7 @@ #include #include #include -#include +#include #include "soc.h" #include "voltage.h" diff --git a/drivers/gpio/gpio-twl4030.c b/drivers/gpio/gpio-twl4030.c index 24f388e..9b511df 100644 --- a/drivers/gpio/gpio-twl4030.c +++ b/drivers/gpio/gpio-twl4030.c @@ -35,7 +35,7 @@ #include #include -#include +#include /* * The GPIO "subchip" supports 18 GPIOs which can be configured as diff --git a/drivers/iio/adc/twl4030-madc.c b/drivers/iio/adc/twl4030-madc.c index bd3d37f..1edd99f 100644 --- a/drivers/iio/adc/twl4030-madc.c +++ b/drivers/iio/adc/twl4030-madc.c @@ -35,7 +35,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/drivers/iio/adc/twl6030-gpadc.c b/drivers/iio/adc/twl6030-gpadc.c index becbb0a..bc0e60b 100644 --- a/drivers/iio/adc/twl6030-gpadc.c +++ b/drivers/iio/adc/twl6030-gpadc.c @@ -33,7 +33,7 @@ #include #include #include -#include +#include #include #include diff --git a/drivers/input/keyboard/twl4030_keypad.c b/drivers/input/keyboard/twl4030_keypad.c index 39e72b3..f9f98ef 100644 --- a/drivers/input/keyboard/twl4030_keypad.c +++ b/drivers/input/keyboard/twl4030_keypad.c @@ -30,7 +30,7 @@ #include #include #include -#include +#include #include #include diff --git a/drivers/input/misc/twl4030-pwrbutton.c b/drivers/input/misc/twl4030-pwrbutton.c index 1c13005..b307cca 100644 --- a/drivers/input/misc/twl4030-pwrbutton.c +++ b/drivers/input/misc/twl4030-pwrbutton.c @@ -27,7 +27,7 @@ #include #include #include -#include +#include #define PWR_PWRON_IRQ (1 << 0) diff --git a/drivers/input/misc/twl4030-vibra.c b/drivers/input/misc/twl4030-vibra.c index caa5a62..6c51d40 100644 --- a/drivers/input/misc/twl4030-vibra.c +++ b/drivers/input/misc/twl4030-vibra.c @@ -28,7 +28,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/drivers/mfd/twl-core.c b/drivers/mfd/twl-core.c index c64615d..2a09dde 100644 --- a/drivers/mfd/twl-core.c +++ b/drivers/mfd/twl-core.c @@ -44,7 +44,7 @@ #include #include -#include +#include /* Register descriptions for audio */ #include @@ -173,7 +173,7 @@ static struct twl_private *twl_priv; static struct twl_mapping twl4030_map[] = { /* * NOTE: don't change this table without updating the - * defines for TWL4030_MODULE_* + * defines for TWL4030_MODULE_* * so they continue to match the order in this table. */ @@ -344,7 +344,7 @@ static const struct regmap_config twl4030_regmap_config[4] = { static struct twl_mapping twl6030_map[] = { /* * NOTE: don't change this table without updating the - * defines for TWL4030_MODULE_* + * defines for TWL4030_MODULE_* * so they continue to match the order in this table. */ diff --git a/drivers/mfd/twl4030-audio.c b/drivers/mfd/twl4030-audio.c index 0a16064..da16bf4 100644 --- a/drivers/mfd/twl4030-audio.c +++ b/drivers/mfd/twl4030-audio.c @@ -30,7 +30,7 @@ #include #include #include -#include +#include #include #include diff --git a/drivers/mfd/twl4030-irq.c b/drivers/mfd/twl4030-irq.c index 378c02d..b16c16f 100644 --- a/drivers/mfd/twl4030-irq.c +++ b/drivers/mfd/twl4030-irq.c @@ -33,7 +33,7 @@ #include #include #include -#include +#include #include "twl-core.h" diff --git a/drivers/mfd/twl4030-power.c b/drivers/mfd/twl4030-power.c index f4b2c29..6b36932 100644 --- a/drivers/mfd/twl4030-power.c +++ b/drivers/mfd/twl4030-power.c @@ -25,7 +25,7 @@ #include #include -#include +#include #include #include #include diff --git a/drivers/mfd/twl6030-irq.c b/drivers/mfd/twl6030-irq.c index 5357450..e3ec8df 100644 --- a/drivers/mfd/twl6030-irq.c +++ b/drivers/mfd/twl6030-irq.c @@ -35,7 +35,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/drivers/phy/ti/phy-twl4030-usb.c b/drivers/phy/ti/phy-twl4030-usb.c index 2990b39..28f4990 100644 --- a/drivers/phy/ti/phy-twl4030-usb.c +++ b/drivers/phy/ti/phy-twl4030-usb.c @@ -36,7 +36,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/drivers/power/supply/twl4030_charger.c b/drivers/power/supply/twl4030_charger.c index 9dff1b4..a5915f4 100644 --- a/drivers/power/supply/twl4030_charger.c +++ b/drivers/power/supply/twl4030_charger.c @@ -18,7 +18,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/drivers/pwm/pwm-twl-led.c b/drivers/pwm/pwm-twl-led.c index 21eff99..0115362 100644 --- a/drivers/pwm/pwm-twl-led.c +++ b/drivers/pwm/pwm-twl-led.c @@ -24,7 +24,7 @@ #include #include #include -#include +#include #include /* diff --git a/drivers/pwm/pwm-twl.c b/drivers/pwm/pwm-twl.c index 9de617b..b7a45be 100644 --- a/drivers/pwm/pwm-twl.c +++ b/drivers/pwm/pwm-twl.c @@ -21,7 +21,7 @@ #include #include #include -#include +#include #include /* diff --git a/drivers/regulator/twl-regulator.c b/drivers/regulator/twl-regulator.c index 6c9ec84..a4456db5 100644 --- a/drivers/regulator/twl-regulator.c +++ b/drivers/regulator/twl-regulator.c @@ -20,7 +20,7 @@ #include #include #include -#include +#include #include /* diff --git a/drivers/regulator/twl6030-regulator.c b/drivers/regulator/twl6030-regulator.c index 56aada3..219cbd9 100644 --- a/drivers/regulator/twl6030-regulator.c +++ b/drivers/regulator/twl6030-regulator.c @@ -21,7 +21,7 @@ #include #include #include -#include +#include #include struct twlreg_info { diff --git a/drivers/rtc/rtc-twl.c b/drivers/rtc/rtc-twl.c index c18c392..3472e79 100644 --- a/drivers/rtc/rtc-twl.c +++ b/drivers/rtc/rtc-twl.c @@ -31,7 +31,7 @@ #include #include -#include +#include enum twl_class { TWL_4030 = 0, diff --git a/drivers/usb/phy/phy-twl6030-usb.c b/drivers/usb/phy/phy-twl6030-usb.c index 628b600..b5dc077 100644 --- a/drivers/usb/phy/phy-twl6030-usb.c +++ b/drivers/usb/phy/phy-twl6030-usb.c @@ -28,7 +28,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/drivers/video/backlight/pandora_bl.c b/drivers/video/backlight/pandora_bl.c index 5d8bb8b..a186bc6 100644 --- a/drivers/video/backlight/pandora_bl.c +++ b/drivers/video/backlight/pandora_bl.c @@ -16,7 +16,7 @@ #include #include #include -#include +#include #include #define TWL_PWM0_ON 0x00 diff --git a/drivers/watchdog/twl4030_wdt.c b/drivers/watchdog/twl4030_wdt.c index 9bf3cc0..569fe85 100644 --- a/drivers/watchdog/twl4030_wdt.c +++ b/drivers/watchdog/twl4030_wdt.c @@ -24,7 +24,7 @@ #include #include #include -#include +#include #define TWL4030_WATCHDOG_CFG_REG_OFFS 0x3 diff --git a/include/linux/i2c/twl.h b/include/linux/i2c/twl.h deleted file mode 100644 index 9ad7828..0000000 --- a/include/linux/i2c/twl.h +++ /dev/null @@ -1,876 +0,0 @@ -/* - * twl4030.h - header for TWL4030 PM and audio CODEC device - * - * Copyright (C) 2005-2006 Texas Instruments, Inc. - * - * Based on tlv320aic23.c: - * Copyright (c) by Kai Svahn - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - * - */ - -#ifndef __TWL_H_ -#define __TWL_H_ - -#include -#include - -/* - * Using the twl4030 core we address registers using a pair - * { module id, relative register offset } - * which that core then maps to the relevant - * { i2c slave, absolute register address } - * - * The module IDs are meaningful only to the twl4030 core code, - * which uses them as array indices to look up the first register - * address each module uses within a given i2c slave. - */ - -/* Module IDs for similar functionalities found in twl4030/twl6030 */ -enum twl_module_ids { - TWL_MODULE_USB, - TWL_MODULE_PIH, - TWL_MODULE_MAIN_CHARGE, - TWL_MODULE_PM_MASTER, - TWL_MODULE_PM_RECEIVER, - - TWL_MODULE_RTC, - TWL_MODULE_PWM, - TWL_MODULE_LED, - TWL_MODULE_SECURED_REG, - - TWL_MODULE_LAST, -}; - -/* Modules only available in twl4030 series */ -enum twl4030_module_ids { - TWL4030_MODULE_AUDIO_VOICE = TWL_MODULE_LAST, - TWL4030_MODULE_GPIO, - TWL4030_MODULE_INTBR, - TWL4030_MODULE_TEST, - TWL4030_MODULE_KEYPAD, - - TWL4030_MODULE_MADC, - TWL4030_MODULE_INTERRUPTS, - TWL4030_MODULE_PRECHARGE, - TWL4030_MODULE_BACKUP, - TWL4030_MODULE_INT, - - TWL5031_MODULE_ACCESSORY, - TWL5031_MODULE_INTERRUPTS, - - TWL4030_MODULE_LAST, -}; - -/* Modules only available in twl6030 series */ -enum twl6030_module_ids { - TWL6030_MODULE_ID0 = TWL_MODULE_LAST, - TWL6030_MODULE_ID1, - TWL6030_MODULE_ID2, - TWL6030_MODULE_GPADC, - TWL6030_MODULE_GASGAUGE, - - TWL6030_MODULE_LAST, -}; - -/* Until the clients has been converted to use TWL_MODULE_LED */ -#define TWL4030_MODULE_LED TWL_MODULE_LED - -#define GPIO_INTR_OFFSET 0 -#define KEYPAD_INTR_OFFSET 1 -#define BCI_INTR_OFFSET 2 -#define MADC_INTR_OFFSET 3 -#define USB_INTR_OFFSET 4 -#define CHARGERFAULT_INTR_OFFSET 5 -#define BCI_PRES_INTR_OFFSET 9 -#define USB_PRES_INTR_OFFSET 10 -#define RTC_INTR_OFFSET 11 - -/* - * Offset from TWL6030_IRQ_BASE / pdata->irq_base - */ -#define PWR_INTR_OFFSET 0 -#define HOTDIE_INTR_OFFSET 12 -#define SMPSLDO_INTR_OFFSET 13 -#define BATDETECT_INTR_OFFSET 14 -#define SIMDETECT_INTR_OFFSET 15 -#define MMCDETECT_INTR_OFFSET 16 -#define GASGAUGE_INTR_OFFSET 17 -#define USBOTG_INTR_OFFSET 4 -#define CHARGER_INTR_OFFSET 2 -#define RSV_INTR_OFFSET 0 - -/* INT register offsets */ -#define REG_INT_STS_A 0x00 -#define REG_INT_STS_B 0x01 -#define REG_INT_STS_C 0x02 - -#define REG_INT_MSK_LINE_A 0x03 -#define REG_INT_MSK_LINE_B 0x04 -#define REG_INT_MSK_LINE_C 0x05 - -#define REG_INT_MSK_STS_A 0x06 -#define REG_INT_MSK_STS_B 0x07 -#define REG_INT_MSK_STS_C 0x08 - -/* MASK INT REG GROUP A */ -#define TWL6030_PWR_INT_MASK 0x07 -#define TWL6030_RTC_INT_MASK 0x18 -#define TWL6030_HOTDIE_INT_MASK 0x20 -#define TWL6030_SMPSLDOA_INT_MASK 0xC0 - -/* MASK INT REG GROUP B */ -#define TWL6030_SMPSLDOB_INT_MASK 0x01 -#define TWL6030_BATDETECT_INT_MASK 0x02 -#define TWL6030_SIMDETECT_INT_MASK 0x04 -#define TWL6030_MMCDETECT_INT_MASK 0x08 -#define TWL6030_GPADC_INT_MASK 0x60 -#define TWL6030_GASGAUGE_INT_MASK 0x80 - -/* MASK INT REG GROUP C */ -#define TWL6030_USBOTG_INT_MASK 0x0F -#define TWL6030_CHARGER_CTRL_INT_MASK 0x10 -#define TWL6030_CHARGER_FAULT_INT_MASK 0x60 - -#define TWL6030_MMCCTRL 0xEE -#define VMMC_AUTO_OFF (0x1 << 3) -#define SW_FC (0x1 << 2) -#define STS_MMC 0x1 - -#define TWL6030_CFG_INPUT_PUPD3 0xF2 -#define MMC_PU (0x1 << 3) -#define MMC_PD (0x1 << 2) - -#define TWL_SIL_TYPE(rev) ((rev) & 0x00FFFFFF) -#define TWL_SIL_REV(rev) ((rev) >> 24) -#define TWL_SIL_5030 0x09002F -#define TWL5030_REV_1_0 0x00 -#define TWL5030_REV_1_1 0x10 -#define TWL5030_REV_1_2 0x30 - -#define TWL4030_CLASS_ID 0x4030 -#define TWL6030_CLASS_ID 0x6030 -unsigned int twl_rev(void); -#define GET_TWL_REV (twl_rev()) -#define TWL_CLASS_IS(class, id) \ -static inline int twl_class_is_ ##class(void) \ -{ \ - return ((id) == (GET_TWL_REV)) ? 1 : 0; \ -} - -TWL_CLASS_IS(4030, TWL4030_CLASS_ID) -TWL_CLASS_IS(6030, TWL6030_CLASS_ID) - -/* Set the regcache bypass for the regmap associated with the nodule */ -int twl_set_regcache_bypass(u8 mod_no, bool enable); - -/* - * Read and write several 8-bit registers at once. - */ -int twl_i2c_write(u8 mod_no, u8 *value, u8 reg, unsigned num_bytes); -int twl_i2c_read(u8 mod_no, u8 *value, u8 reg, unsigned num_bytes); - -/* - * Read and write single 8-bit registers - */ -static inline int twl_i2c_write_u8(u8 mod_no, u8 val, u8 reg) { - return twl_i2c_write(mod_no, &val, reg, 1); -} - -static inline int twl_i2c_read_u8(u8 mod_no, u8 *val, u8 reg) { - return twl_i2c_read(mod_no, val, reg, 1); -} - -static inline int twl_i2c_write_u16(u8 mod_no, u16 val, u8 reg) { - val = cpu_to_le16(val); - return twl_i2c_write(mod_no, (u8*) &val, reg, 2); -} - -static inline int twl_i2c_read_u16(u8 mod_no, u16 *val, u8 reg) { - int ret; - ret = twl_i2c_read(mod_no, (u8*) val, reg, 2); - *val = le16_to_cpu(*val); - return ret; -} - -int twl_get_type(void); -int twl_get_version(void); -int twl_get_hfclk_rate(void); - -int twl6030_interrupt_unmask(u8 bit_mask, u8 offset); -int twl6030_interrupt_mask(u8 bit_mask, u8 offset); - -/* Card detect Configuration for MMC1 Controller on OMAP4 */ -#ifdef CONFIG_TWL4030_CORE -int twl6030_mmc_card_detect_config(void); -#else -static inline int twl6030_mmc_card_detect_config(void) -{ - pr_debug("twl6030_mmc_card_detect_config not supported\n"); - return 0; -} -#endif - -/* MMC1 Controller on OMAP4 uses Phoenix irq for Card detect */ -#ifdef CONFIG_TWL4030_CORE -int twl6030_mmc_card_detect(struct device *dev, int slot); -#else -static inline int twl6030_mmc_card_detect(struct device *dev, int slot) -{ - pr_debug("Call back twl6030_mmc_card_detect not supported\n"); - return -EIO; -} -#endif -/*----------------------------------------------------------------------*/ - -/* - * NOTE: at up to 1024 registers, this is a big chip. - * - * Avoid putting register declarations in this file, instead of into - * a driver-private file, unless some of the registers in a block - * need to be shared with other drivers. One example is blocks that - * have Secondary IRQ Handler (SIH) registers. - */ - -#define TWL4030_SIH_CTRL_EXCLEN_MASK BIT(0) -#define TWL4030_SIH_CTRL_PENDDIS_MASK BIT(1) -#define TWL4030_SIH_CTRL_COR_MASK BIT(2) - -/*----------------------------------------------------------------------*/ - -/* - * GPIO Block Register offsets (use TWL4030_MODULE_GPIO) - */ - -#define REG_GPIODATAIN1 0x0 -#define REG_GPIODATAIN2 0x1 -#define REG_GPIODATAIN3 0x2 -#define REG_GPIODATADIR1 0x3 -#define REG_GPIODATADIR2 0x4 -#define REG_GPIODATADIR3 0x5 -#define REG_GPIODATAOUT1 0x6 -#define REG_GPIODATAOUT2 0x7 -#define REG_GPIODATAOUT3 0x8 -#define REG_CLEARGPIODATAOUT1 0x9 -#define REG_CLEARGPIODATAOUT2 0xA -#define REG_CLEARGPIODATAOUT3 0xB -#define REG_SETGPIODATAOUT1 0xC -#define REG_SETGPIODATAOUT2 0xD -#define REG_SETGPIODATAOUT3 0xE -#define REG_GPIO_DEBEN1 0xF -#define REG_GPIO_DEBEN2 0x10 -#define REG_GPIO_DEBEN3 0x11 -#define REG_GPIO_CTRL 0x12 -#define REG_GPIOPUPDCTR1 0x13 -#define REG_GPIOPUPDCTR2 0x14 -#define REG_GPIOPUPDCTR3 0x15 -#define REG_GPIOPUPDCTR4 0x16 -#define REG_GPIOPUPDCTR5 0x17 -#define REG_GPIO_ISR1A 0x19 -#define REG_GPIO_ISR2A 0x1A -#define REG_GPIO_ISR3A 0x1B -#define REG_GPIO_IMR1A 0x1C -#define REG_GPIO_IMR2A 0x1D -#define REG_GPIO_IMR3A 0x1E -#define REG_GPIO_ISR1B 0x1F -#define REG_GPIO_ISR2B 0x20 -#define REG_GPIO_ISR3B 0x21 -#define REG_GPIO_IMR1B 0x22 -#define REG_GPIO_IMR2B 0x23 -#define REG_GPIO_IMR3B 0x24 -#define REG_GPIO_EDR1 0x28 -#define REG_GPIO_EDR2 0x29 -#define REG_GPIO_EDR3 0x2A -#define REG_GPIO_EDR4 0x2B -#define REG_GPIO_EDR5 0x2C -#define REG_GPIO_SIH_CTRL 0x2D - -/* Up to 18 signals are available as GPIOs, when their - * pins are not assigned to another use (such as ULPI/USB). - */ -#define TWL4030_GPIO_MAX 18 - -/*----------------------------------------------------------------------*/ - -/*Interface Bit Register (INTBR) offsets - *(Use TWL_4030_MODULE_INTBR) - */ - -#define REG_IDCODE_7_0 0x00 -#define REG_IDCODE_15_8 0x01 -#define REG_IDCODE_16_23 0x02 -#define REG_IDCODE_31_24 0x03 -#define REG_GPPUPDCTR1 0x0F -#define REG_UNLOCK_TEST_REG 0x12 - -/*I2C1 and I2C4(SR) SDA/SCL pull-up control bits */ - -#define I2C_SCL_CTRL_PU BIT(0) -#define I2C_SDA_CTRL_PU BIT(2) -#define SR_I2C_SCL_CTRL_PU BIT(4) -#define SR_I2C_SDA_CTRL_PU BIT(6) - -#define TWL_EEPROM_R_UNLOCK 0x49 - -/*----------------------------------------------------------------------*/ - -/* - * Keypad register offsets (use TWL4030_MODULE_KEYPAD) - * ... SIH/interrupt only - */ - -#define TWL4030_KEYPAD_KEYP_ISR1 0x11 -#define TWL4030_KEYPAD_KEYP_IMR1 0x12 -#define TWL4030_KEYPAD_KEYP_ISR2 0x13 -#define TWL4030_KEYPAD_KEYP_IMR2 0x14 -#define TWL4030_KEYPAD_KEYP_SIR 0x15 /* test register */ -#define TWL4030_KEYPAD_KEYP_EDR 0x16 -#define TWL4030_KEYPAD_KEYP_SIH_CTRL 0x17 - -/*----------------------------------------------------------------------*/ - -/* - * Multichannel ADC register offsets (use TWL4030_MODULE_MADC) - * ... SIH/interrupt only - */ - -#define TWL4030_MADC_ISR1 0x61 -#define TWL4030_MADC_IMR1 0x62 -#define TWL4030_MADC_ISR2 0x63 -#define TWL4030_MADC_IMR2 0x64 -#define TWL4030_MADC_SIR 0x65 /* test register */ -#define TWL4030_MADC_EDR 0x66 -#define TWL4030_MADC_SIH_CTRL 0x67 - -/*----------------------------------------------------------------------*/ - -/* - * Battery charger register offsets (use TWL4030_MODULE_INTERRUPTS) - */ - -#define TWL4030_INTERRUPTS_BCIISR1A 0x0 -#define TWL4030_INTERRUPTS_BCIISR2A 0x1 -#define TWL4030_INTERRUPTS_BCIIMR1A 0x2 -#define TWL4030_INTERRUPTS_BCIIMR2A 0x3 -#define TWL4030_INTERRUPTS_BCIISR1B 0x4 -#define TWL4030_INTERRUPTS_BCIISR2B 0x5 -#define TWL4030_INTERRUPTS_BCIIMR1B 0x6 -#define TWL4030_INTERRUPTS_BCIIMR2B 0x7 -#define TWL4030_INTERRUPTS_BCISIR1 0x8 /* test register */ -#define TWL4030_INTERRUPTS_BCISIR2 0x9 /* test register */ -#define TWL4030_INTERRUPTS_BCIEDR1 0xa -#define TWL4030_INTERRUPTS_BCIEDR2 0xb -#define TWL4030_INTERRUPTS_BCIEDR3 0xc -#define TWL4030_INTERRUPTS_BCISIHCTRL 0xd - -/*----------------------------------------------------------------------*/ - -/* - * Power Interrupt block register offsets (use TWL4030_MODULE_INT) - */ - -#define TWL4030_INT_PWR_ISR1 0x0 -#define TWL4030_INT_PWR_IMR1 0x1 -#define TWL4030_INT_PWR_ISR2 0x2 -#define TWL4030_INT_PWR_IMR2 0x3 -#define TWL4030_INT_PWR_SIR 0x4 /* test register */ -#define TWL4030_INT_PWR_EDR1 0x5 -#define TWL4030_INT_PWR_EDR2 0x6 -#define TWL4030_INT_PWR_SIH_CTRL 0x7 - -/*----------------------------------------------------------------------*/ - -/* - * Accessory Interrupts - */ -#define TWL5031_ACIIMR_LSB 0x05 -#define TWL5031_ACIIMR_MSB 0x06 -#define TWL5031_ACIIDR_LSB 0x07 -#define TWL5031_ACIIDR_MSB 0x08 -#define TWL5031_ACCISR1 0x0F -#define TWL5031_ACCIMR1 0x10 -#define TWL5031_ACCISR2 0x11 -#define TWL5031_ACCIMR2 0x12 -#define TWL5031_ACCSIR 0x13 -#define TWL5031_ACCEDR1 0x14 -#define TWL5031_ACCSIHCTRL 0x15 - -/*----------------------------------------------------------------------*/ - -/* - * Battery Charger Controller - */ - -#define TWL5031_INTERRUPTS_BCIISR1 0x0 -#define TWL5031_INTERRUPTS_BCIIMR1 0x1 -#define TWL5031_INTERRUPTS_BCIISR2 0x2 -#define TWL5031_INTERRUPTS_BCIIMR2 0x3 -#define TWL5031_INTERRUPTS_BCISIR 0x4 -#define TWL5031_INTERRUPTS_BCIEDR1 0x5 -#define TWL5031_INTERRUPTS_BCIEDR2 0x6 -#define TWL5031_INTERRUPTS_BCISIHCTRL 0x7 - -/*----------------------------------------------------------------------*/ - -/* - * PM Master module register offsets (use TWL4030_MODULE_PM_MASTER) - */ - -#define TWL4030_PM_MASTER_CFG_P1_TRANSITION 0x00 -#define TWL4030_PM_MASTER_CFG_P2_TRANSITION 0x01 -#define TWL4030_PM_MASTER_CFG_P3_TRANSITION 0x02 -#define TWL4030_PM_MASTER_CFG_P123_TRANSITION 0x03 -#define TWL4030_PM_MASTER_STS_BOOT 0x04 -#define TWL4030_PM_MASTER_CFG_BOOT 0x05 -#define TWL4030_PM_MASTER_SHUNDAN 0x06 -#define TWL4030_PM_MASTER_BOOT_BCI 0x07 -#define TWL4030_PM_MASTER_CFG_PWRANA1 0x08 -#define TWL4030_PM_MASTER_CFG_PWRANA2 0x09 -#define TWL4030_PM_MASTER_BACKUP_MISC_STS 0x0b -#define TWL4030_PM_MASTER_BACKUP_MISC_CFG 0x0c -#define TWL4030_PM_MASTER_BACKUP_MISC_TST 0x0d -#define TWL4030_PM_MASTER_PROTECT_KEY 0x0e -#define TWL4030_PM_MASTER_STS_HW_CONDITIONS 0x0f -#define TWL4030_PM_MASTER_P1_SW_EVENTS 0x10 -#define TWL4030_PM_MASTER_P2_SW_EVENTS 0x11 -#define TWL4030_PM_MASTER_P3_SW_EVENTS 0x12 -#define TWL4030_PM_MASTER_STS_P123_STATE 0x13 -#define TWL4030_PM_MASTER_PB_CFG 0x14 -#define TWL4030_PM_MASTER_PB_WORD_MSB 0x15 -#define TWL4030_PM_MASTER_PB_WORD_LSB 0x16 -#define TWL4030_PM_MASTER_SEQ_ADD_W2P 0x1c -#define TWL4030_PM_MASTER_SEQ_ADD_P2A 0x1d -#define TWL4030_PM_MASTER_SEQ_ADD_A2W 0x1e -#define TWL4030_PM_MASTER_SEQ_ADD_A2S 0x1f -#define TWL4030_PM_MASTER_SEQ_ADD_S2A12 0x20 -#define TWL4030_PM_MASTER_SEQ_ADD_S2A3 0x21 -#define TWL4030_PM_MASTER_SEQ_ADD_WARM 0x22 -#define TWL4030_PM_MASTER_MEMORY_ADDRESS 0x23 -#define TWL4030_PM_MASTER_MEMORY_DATA 0x24 - -#define TWL4030_PM_MASTER_KEY_CFG1 0xc0 -#define TWL4030_PM_MASTER_KEY_CFG2 0x0c - -#define TWL4030_PM_MASTER_KEY_TST1 0xe0 -#define TWL4030_PM_MASTER_KEY_TST2 0x0e - -#define TWL4030_PM_MASTER_GLOBAL_TST 0xb6 - -/*----------------------------------------------------------------------*/ - -/* Power bus message definitions */ - -/* The TWL4030/5030 splits its power-management resources (the various - * regulators, clock and reset lines) into 3 processor groups - P1, P2 and - * P3. These groups can then be configured to transition between sleep, wait-on - * and active states by sending messages to the power bus. See Section 5.4.2 - * Power Resources of TWL4030 TRM - */ - -/* Processor groups */ -#define DEV_GRP_NULL 0x0 -#define DEV_GRP_P1 0x1 /* P1: all OMAP devices */ -#define DEV_GRP_P2 0x2 /* P2: all Modem devices */ -#define DEV_GRP_P3 0x4 /* P3: all peripheral devices */ - -/* Resource groups */ -#define RES_GRP_RES 0x0 /* Reserved */ -#define RES_GRP_PP 0x1 /* Power providers */ -#define RES_GRP_RC 0x2 /* Reset and control */ -#define RES_GRP_PP_RC 0x3 -#define RES_GRP_PR 0x4 /* Power references */ -#define RES_GRP_PP_PR 0x5 -#define RES_GRP_RC_PR 0x6 -#define RES_GRP_ALL 0x7 /* All resource groups */ - -#define RES_TYPE2_R0 0x0 -#define RES_TYPE2_R1 0x1 -#define RES_TYPE2_R2 0x2 - -#define RES_TYPE_R0 0x0 -#define RES_TYPE_ALL 0x7 - -/* Resource states */ -#define RES_STATE_WRST 0xF -#define RES_STATE_ACTIVE 0xE -#define RES_STATE_SLEEP 0x8 -#define RES_STATE_OFF 0x0 - -/* Power resources */ - -/* Power providers */ -#define RES_VAUX1 1 -#define RES_VAUX2 2 -#define RES_VAUX3 3 -#define RES_VAUX4 4 -#define RES_VMMC1 5 -#define RES_VMMC2 6 -#define RES_VPLL1 7 -#define RES_VPLL2 8 -#define RES_VSIM 9 -#define RES_VDAC 10 -#define RES_VINTANA1 11 -#define RES_VINTANA2 12 -#define RES_VINTDIG 13 -#define RES_VIO 14 -#define RES_VDD1 15 -#define RES_VDD2 16 -#define RES_VUSB_1V5 17 -#define RES_VUSB_1V8 18 -#define RES_VUSB_3V1 19 -#define RES_VUSBCP 20 -#define RES_REGEN 21 -/* Reset and control */ -#define RES_NRES_PWRON 22 -#define RES_CLKEN 23 -#define RES_SYSEN 24 -#define RES_HFCLKOUT 25 -#define RES_32KCLKOUT 26 -#define RES_RESET 27 -/* Power Reference */ -#define RES_MAIN_REF 28 - -#define TOTAL_RESOURCES 28 -/* - * Power Bus Message Format ... these can be sent individually by Linux, - * but are usually part of downloaded scripts that are run when various - * power events are triggered. - * - * Broadcast Message (16 Bits): - * DEV_GRP[15:13] MT[12] RES_GRP[11:9] RES_TYPE2[8:7] RES_TYPE[6:4] - * RES_STATE[3:0] - * - * Singular Message (16 Bits): - * DEV_GRP[15:13] MT[12] RES_ID[11:4] RES_STATE[3:0] - */ - -#define MSG_BROADCAST(devgrp, grp, type, type2, state) \ - ( (devgrp) << 13 | 1 << 12 | (grp) << 9 | (type2) << 7 \ - | (type) << 4 | (state)) - -#define MSG_SINGULAR(devgrp, id, state) \ - ((devgrp) << 13 | 0 << 12 | (id) << 4 | (state)) - -#define MSG_BROADCAST_ALL(devgrp, state) \ - ((devgrp) << 5 | (state)) - -#define MSG_BROADCAST_REF MSG_BROADCAST_ALL -#define MSG_BROADCAST_PROV MSG_BROADCAST_ALL -#define MSG_BROADCAST__CLK_RST MSG_BROADCAST_ALL -/*----------------------------------------------------------------------*/ - -struct twl4030_clock_init_data { - bool ck32k_lowpwr_enable; -}; - -struct twl4030_bci_platform_data { - int *battery_tmp_tbl; - unsigned int tblsize; - int bb_uvolt; /* voltage to charge backup battery */ - int bb_uamp; /* current for backup battery charging */ -}; - -/* TWL4030_GPIO_MAX (18) GPIOs, with interrupts */ -struct twl4030_gpio_platform_data { - /* package the two LED signals as output-only GPIOs? */ - bool use_leds; - - /* gpio-n should control VMMC(n+1) if BIT(n) in mmc_cd is set */ - u8 mmc_cd; - - /* if BIT(N) is set, or VMMC(n+1) is linked, debounce GPIO-N */ - u32 debounce; - - /* For gpio-N, bit (1 << N) in "pullups" is set if that pullup - * should be enabled. Else, if that bit is set in "pulldowns", - * that pulldown is enabled. Don't waste power by letting any - * digital inputs float... - */ - u32 pullups; - u32 pulldowns; - - int (*setup)(struct device *dev, - unsigned gpio, unsigned ngpio); - int (*teardown)(struct device *dev, - unsigned gpio, unsigned ngpio); -}; - -struct twl4030_madc_platform_data { - int irq_line; -}; - -/* Boards have unique mappings of {row, col} --> keycode. - * Column and row are 8 bits each, but range only from 0..7. - * a PERSISTENT_KEY is "always on" and never reported. - */ -#define PERSISTENT_KEY(r, c) KEY((r), (c), KEY_RESERVED) - -struct twl4030_keypad_data { - const struct matrix_keymap_data *keymap_data; - unsigned rows; - unsigned cols; - bool rep; -}; - -enum twl4030_usb_mode { - T2_USB_MODE_ULPI = 1, - T2_USB_MODE_CEA2011_3PIN = 2, -}; - -struct twl4030_usb_data { - enum twl4030_usb_mode usb_mode; - unsigned long features; - - int (*phy_init)(struct device *dev); - int (*phy_exit)(struct device *dev); - /* Power on/off the PHY */ - int (*phy_power)(struct device *dev, int iD, int on); - /* enable/disable phy clocks */ - int (*phy_set_clock)(struct device *dev, int on); - /* suspend/resume of phy */ - int (*phy_suspend)(struct device *dev, int suspend); -}; - -struct twl4030_ins { - u16 pmb_message; - u8 delay; -}; - -struct twl4030_script { - struct twl4030_ins *script; - unsigned size; - u8 flags; -#define TWL4030_WRST_SCRIPT (1<<0) -#define TWL4030_WAKEUP12_SCRIPT (1<<1) -#define TWL4030_WAKEUP3_SCRIPT (1<<2) -#define TWL4030_SLEEP_SCRIPT (1<<3) -}; - -struct twl4030_resconfig { - u8 resource; - u8 devgroup; /* Processor group that Power resource belongs to */ - u8 type; /* Power resource addressed, 6 / broadcast message */ - u8 type2; /* Power resource addressed, 3 / broadcast message */ - u8 remap_off; /* off state remapping */ - u8 remap_sleep; /* sleep state remapping */ -}; - -struct twl4030_power_data { - struct twl4030_script **scripts; - unsigned num; - struct twl4030_resconfig *resource_config; - struct twl4030_resconfig *board_config; -#define TWL4030_RESCONFIG_UNDEF ((u8)-1) - bool use_poweroff; /* Board is wired for TWL poweroff */ - bool ac_charger_quirk; /* Disable AC charger on board */ -}; - -extern int twl4030_remove_script(u8 flags); -extern void twl4030_power_off(void); - -struct twl4030_codec_data { - unsigned int digimic_delay; /* in ms */ - unsigned int ramp_delay_value; - unsigned int offset_cncl_path; - unsigned int hs_extmute:1; - int hs_extmute_gpio; -}; - -struct twl4030_vibra_data { - unsigned int coexist; -}; - -struct twl4030_audio_data { - unsigned int audio_mclk; - struct twl4030_codec_data *codec; - struct twl4030_vibra_data *vibra; - - /* twl6040 */ - int audpwron_gpio; /* audio power-on gpio */ - int naudint_irq; /* audio interrupt */ - unsigned int irq_base; -}; - -struct twl4030_platform_data { - struct twl4030_clock_init_data *clock; - struct twl4030_bci_platform_data *bci; - struct twl4030_gpio_platform_data *gpio; - struct twl4030_madc_platform_data *madc; - struct twl4030_keypad_data *keypad; - struct twl4030_usb_data *usb; - struct twl4030_power_data *power; - struct twl4030_audio_data *audio; - - /* Common LDO regulators for TWL4030/TWL6030 */ - struct regulator_init_data *vdac; - struct regulator_init_data *vaux1; - struct regulator_init_data *vaux2; - struct regulator_init_data *vaux3; - struct regulator_init_data *vdd1; - struct regulator_init_data *vdd2; - struct regulator_init_data *vdd3; - /* TWL4030 LDO regulators */ - struct regulator_init_data *vpll1; - struct regulator_init_data *vpll2; - struct regulator_init_data *vmmc1; - struct regulator_init_data *vmmc2; - struct regulator_init_data *vsim; - struct regulator_init_data *vaux4; - struct regulator_init_data *vio; - struct regulator_init_data *vintana1; - struct regulator_init_data *vintana2; - struct regulator_init_data *vintdig; - /* TWL6030 LDO regulators */ - struct regulator_init_data *vmmc; - struct regulator_init_data *vpp; - struct regulator_init_data *vusim; - struct regulator_init_data *vana; - struct regulator_init_data *vcxio; - struct regulator_init_data *vusb; - struct regulator_init_data *clk32kg; - struct regulator_init_data *v1v8; - struct regulator_init_data *v2v1; - /* TWL6032 LDO regulators */ - struct regulator_init_data *ldo1; - struct regulator_init_data *ldo2; - struct regulator_init_data *ldo3; - struct regulator_init_data *ldo4; - struct regulator_init_data *ldo5; - struct regulator_init_data *ldo6; - struct regulator_init_data *ldo7; - struct regulator_init_data *ldoln; - struct regulator_init_data *ldousb; - /* TWL6032 DCDC regulators */ - struct regulator_init_data *smps3; - struct regulator_init_data *smps4; - struct regulator_init_data *vio6025; -}; - -struct twl_regulator_driver_data { - int (*set_voltage)(void *data, int target_uV); - int (*get_voltage)(void *data); - void *data; - unsigned long features; -}; -/* chip-specific feature flags, for twl_regulator_driver_data.features */ -#define TWL4030_VAUX2 BIT(0) /* pre-5030 voltage ranges */ -#define TPS_SUBSET BIT(1) /* tps659[23]0 have fewer LDOs */ -#define TWL5031 BIT(2) /* twl5031 has different registers */ -#define TWL6030_CLASS BIT(3) /* TWL6030 class */ -#define TWL6032_SUBCLASS BIT(4) /* TWL6032 has changed registers */ -#define TWL4030_ALLOW_UNSUPPORTED BIT(5) /* Some voltages are possible - * but not officially supported. - * This flag is necessary to - * enable them. - */ - -/*----------------------------------------------------------------------*/ - -int twl4030_sih_setup(struct device *dev, int module, int irq_base); - -/* Offsets to Power Registers */ -#define TWL4030_VDAC_DEV_GRP 0x3B -#define TWL4030_VDAC_DEDICATED 0x3E -#define TWL4030_VAUX1_DEV_GRP 0x17 -#define TWL4030_VAUX1_DEDICATED 0x1A -#define TWL4030_VAUX2_DEV_GRP 0x1B -#define TWL4030_VAUX2_DEDICATED 0x1E -#define TWL4030_VAUX3_DEV_GRP 0x1F -#define TWL4030_VAUX3_DEDICATED 0x22 - -static inline int twl4030charger_usb_en(int enable) { return 0; } - -/*----------------------------------------------------------------------*/ - -/* Linux-specific regulator identifiers ... for now, we only support - * the LDOs, and leave the three buck converters alone. VDD1 and VDD2 - * need to tie into hardware based voltage scaling (cpufreq etc), while - * VIO is generally fixed. - */ - -/* TWL4030 SMPS/LDO's */ -/* EXTERNAL dc-to-dc buck converters */ -#define TWL4030_REG_VDD1 0 -#define TWL4030_REG_VDD2 1 -#define TWL4030_REG_VIO 2 - -/* EXTERNAL LDOs */ -#define TWL4030_REG_VDAC 3 -#define TWL4030_REG_VPLL1 4 -#define TWL4030_REG_VPLL2 5 /* not on all chips */ -#define TWL4030_REG_VMMC1 6 -#define TWL4030_REG_VMMC2 7 /* not on all chips */ -#define TWL4030_REG_VSIM 8 /* not on all chips */ -#define TWL4030_REG_VAUX1 9 /* not on all chips */ -#define TWL4030_REG_VAUX2_4030 10 /* (twl4030-specific) */ -#define TWL4030_REG_VAUX2 11 /* (twl5030 and newer) */ -#define TWL4030_REG_VAUX3 12 /* not on all chips */ -#define TWL4030_REG_VAUX4 13 /* not on all chips */ - -/* INTERNAL LDOs */ -#define TWL4030_REG_VINTANA1 14 -#define TWL4030_REG_VINTANA2 15 -#define TWL4030_REG_VINTDIG 16 -#define TWL4030_REG_VUSB1V5 17 -#define TWL4030_REG_VUSB1V8 18 -#define TWL4030_REG_VUSB3V1 19 - -/* TWL6030 SMPS/LDO's */ -/* EXTERNAL dc-to-dc buck convertor controllable via SR */ -#define TWL6030_REG_VDD1 30 -#define TWL6030_REG_VDD2 31 -#define TWL6030_REG_VDD3 32 - -/* Non SR compliant dc-to-dc buck convertors */ -#define TWL6030_REG_VMEM 33 -#define TWL6030_REG_V2V1 34 -#define TWL6030_REG_V1V29 35 -#define TWL6030_REG_V1V8 36 - -/* EXTERNAL LDOs */ -#define TWL6030_REG_VAUX1_6030 37 -#define TWL6030_REG_VAUX2_6030 38 -#define TWL6030_REG_VAUX3_6030 39 -#define TWL6030_REG_VMMC 40 -#define TWL6030_REG_VPP 41 -#define TWL6030_REG_VUSIM 42 -#define TWL6030_REG_VANA 43 -#define TWL6030_REG_VCXIO 44 -#define TWL6030_REG_VDAC 45 -#define TWL6030_REG_VUSB 46 - -/* INTERNAL LDOs */ -#define TWL6030_REG_VRTC 47 -#define TWL6030_REG_CLK32KG 48 - -/* LDOs on 6025 have different names */ -#define TWL6032_REG_LDO2 49 -#define TWL6032_REG_LDO4 50 -#define TWL6032_REG_LDO3 51 -#define TWL6032_REG_LDO5 52 -#define TWL6032_REG_LDO1 53 -#define TWL6032_REG_LDO7 54 -#define TWL6032_REG_LDO6 55 -#define TWL6032_REG_LDOLN 56 -#define TWL6032_REG_LDOUSB 57 - -/* 6025 DCDC supplies */ -#define TWL6032_REG_SMPS3 58 -#define TWL6032_REG_SMPS4 59 -#define TWL6032_REG_VIO 60 - - -#endif /* End of __TWL4030_H */ diff --git a/include/linux/mfd/twl.h b/include/linux/mfd/twl.h new file mode 100644 index 0000000..9ad7828 --- /dev/null +++ b/include/linux/mfd/twl.h @@ -0,0 +1,876 @@ +/* + * twl4030.h - header for TWL4030 PM and audio CODEC device + * + * Copyright (C) 2005-2006 Texas Instruments, Inc. + * + * Based on tlv320aic23.c: + * Copyright (c) by Kai Svahn + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#ifndef __TWL_H_ +#define __TWL_H_ + +#include +#include + +/* + * Using the twl4030 core we address registers using a pair + * { module id, relative register offset } + * which that core then maps to the relevant + * { i2c slave, absolute register address } + * + * The module IDs are meaningful only to the twl4030 core code, + * which uses them as array indices to look up the first register + * address each module uses within a given i2c slave. + */ + +/* Module IDs for similar functionalities found in twl4030/twl6030 */ +enum twl_module_ids { + TWL_MODULE_USB, + TWL_MODULE_PIH, + TWL_MODULE_MAIN_CHARGE, + TWL_MODULE_PM_MASTER, + TWL_MODULE_PM_RECEIVER, + + TWL_MODULE_RTC, + TWL_MODULE_PWM, + TWL_MODULE_LED, + TWL_MODULE_SECURED_REG, + + TWL_MODULE_LAST, +}; + +/* Modules only available in twl4030 series */ +enum twl4030_module_ids { + TWL4030_MODULE_AUDIO_VOICE = TWL_MODULE_LAST, + TWL4030_MODULE_GPIO, + TWL4030_MODULE_INTBR, + TWL4030_MODULE_TEST, + TWL4030_MODULE_KEYPAD, + + TWL4030_MODULE_MADC, + TWL4030_MODULE_INTERRUPTS, + TWL4030_MODULE_PRECHARGE, + TWL4030_MODULE_BACKUP, + TWL4030_MODULE_INT, + + TWL5031_MODULE_ACCESSORY, + TWL5031_MODULE_INTERRUPTS, + + TWL4030_MODULE_LAST, +}; + +/* Modules only available in twl6030 series */ +enum twl6030_module_ids { + TWL6030_MODULE_ID0 = TWL_MODULE_LAST, + TWL6030_MODULE_ID1, + TWL6030_MODULE_ID2, + TWL6030_MODULE_GPADC, + TWL6030_MODULE_GASGAUGE, + + TWL6030_MODULE_LAST, +}; + +/* Until the clients has been converted to use TWL_MODULE_LED */ +#define TWL4030_MODULE_LED TWL_MODULE_LED + +#define GPIO_INTR_OFFSET 0 +#define KEYPAD_INTR_OFFSET 1 +#define BCI_INTR_OFFSET 2 +#define MADC_INTR_OFFSET 3 +#define USB_INTR_OFFSET 4 +#define CHARGERFAULT_INTR_OFFSET 5 +#define BCI_PRES_INTR_OFFSET 9 +#define USB_PRES_INTR_OFFSET 10 +#define RTC_INTR_OFFSET 11 + +/* + * Offset from TWL6030_IRQ_BASE / pdata->irq_base + */ +#define PWR_INTR_OFFSET 0 +#define HOTDIE_INTR_OFFSET 12 +#define SMPSLDO_INTR_OFFSET 13 +#define BATDETECT_INTR_OFFSET 14 +#define SIMDETECT_INTR_OFFSET 15 +#define MMCDETECT_INTR_OFFSET 16 +#define GASGAUGE_INTR_OFFSET 17 +#define USBOTG_INTR_OFFSET 4 +#define CHARGER_INTR_OFFSET 2 +#define RSV_INTR_OFFSET 0 + +/* INT register offsets */ +#define REG_INT_STS_A 0x00 +#define REG_INT_STS_B 0x01 +#define REG_INT_STS_C 0x02 + +#define REG_INT_MSK_LINE_A 0x03 +#define REG_INT_MSK_LINE_B 0x04 +#define REG_INT_MSK_LINE_C 0x05 + +#define REG_INT_MSK_STS_A 0x06 +#define REG_INT_MSK_STS_B 0x07 +#define REG_INT_MSK_STS_C 0x08 + +/* MASK INT REG GROUP A */ +#define TWL6030_PWR_INT_MASK 0x07 +#define TWL6030_RTC_INT_MASK 0x18 +#define TWL6030_HOTDIE_INT_MASK 0x20 +#define TWL6030_SMPSLDOA_INT_MASK 0xC0 + +/* MASK INT REG GROUP B */ +#define TWL6030_SMPSLDOB_INT_MASK 0x01 +#define TWL6030_BATDETECT_INT_MASK 0x02 +#define TWL6030_SIMDETECT_INT_MASK 0x04 +#define TWL6030_MMCDETECT_INT_MASK 0x08 +#define TWL6030_GPADC_INT_MASK 0x60 +#define TWL6030_GASGAUGE_INT_MASK 0x80 + +/* MASK INT REG GROUP C */ +#define TWL6030_USBOTG_INT_MASK 0x0F +#define TWL6030_CHARGER_CTRL_INT_MASK 0x10 +#define TWL6030_CHARGER_FAULT_INT_MASK 0x60 + +#define TWL6030_MMCCTRL 0xEE +#define VMMC_AUTO_OFF (0x1 << 3) +#define SW_FC (0x1 << 2) +#define STS_MMC 0x1 + +#define TWL6030_CFG_INPUT_PUPD3 0xF2 +#define MMC_PU (0x1 << 3) +#define MMC_PD (0x1 << 2) + +#define TWL_SIL_TYPE(rev) ((rev) & 0x00FFFFFF) +#define TWL_SIL_REV(rev) ((rev) >> 24) +#define TWL_SIL_5030 0x09002F +#define TWL5030_REV_1_0 0x00 +#define TWL5030_REV_1_1 0x10 +#define TWL5030_REV_1_2 0x30 + +#define TWL4030_CLASS_ID 0x4030 +#define TWL6030_CLASS_ID 0x6030 +unsigned int twl_rev(void); +#define GET_TWL_REV (twl_rev()) +#define TWL_CLASS_IS(class, id) \ +static inline int twl_class_is_ ##class(void) \ +{ \ + return ((id) == (GET_TWL_REV)) ? 1 : 0; \ +} + +TWL_CLASS_IS(4030, TWL4030_CLASS_ID) +TWL_CLASS_IS(6030, TWL6030_CLASS_ID) + +/* Set the regcache bypass for the regmap associated with the nodule */ +int twl_set_regcache_bypass(u8 mod_no, bool enable); + +/* + * Read and write several 8-bit registers at once. + */ +int twl_i2c_write(u8 mod_no, u8 *value, u8 reg, unsigned num_bytes); +int twl_i2c_read(u8 mod_no, u8 *value, u8 reg, unsigned num_bytes); + +/* + * Read and write single 8-bit registers + */ +static inline int twl_i2c_write_u8(u8 mod_no, u8 val, u8 reg) { + return twl_i2c_write(mod_no, &val, reg, 1); +} + +static inline int twl_i2c_read_u8(u8 mod_no, u8 *val, u8 reg) { + return twl_i2c_read(mod_no, val, reg, 1); +} + +static inline int twl_i2c_write_u16(u8 mod_no, u16 val, u8 reg) { + val = cpu_to_le16(val); + return twl_i2c_write(mod_no, (u8*) &val, reg, 2); +} + +static inline int twl_i2c_read_u16(u8 mod_no, u16 *val, u8 reg) { + int ret; + ret = twl_i2c_read(mod_no, (u8*) val, reg, 2); + *val = le16_to_cpu(*val); + return ret; +} + +int twl_get_type(void); +int twl_get_version(void); +int twl_get_hfclk_rate(void); + +int twl6030_interrupt_unmask(u8 bit_mask, u8 offset); +int twl6030_interrupt_mask(u8 bit_mask, u8 offset); + +/* Card detect Configuration for MMC1 Controller on OMAP4 */ +#ifdef CONFIG_TWL4030_CORE +int twl6030_mmc_card_detect_config(void); +#else +static inline int twl6030_mmc_card_detect_config(void) +{ + pr_debug("twl6030_mmc_card_detect_config not supported\n"); + return 0; +} +#endif + +/* MMC1 Controller on OMAP4 uses Phoenix irq for Card detect */ +#ifdef CONFIG_TWL4030_CORE +int twl6030_mmc_card_detect(struct device *dev, int slot); +#else +static inline int twl6030_mmc_card_detect(struct device *dev, int slot) +{ + pr_debug("Call back twl6030_mmc_card_detect not supported\n"); + return -EIO; +} +#endif +/*----------------------------------------------------------------------*/ + +/* + * NOTE: at up to 1024 registers, this is a big chip. + * + * Avoid putting register declarations in this file, instead of into + * a driver-private file, unless some of the registers in a block + * need to be shared with other drivers. One example is blocks that + * have Secondary IRQ Handler (SIH) registers. + */ + +#define TWL4030_SIH_CTRL_EXCLEN_MASK BIT(0) +#define TWL4030_SIH_CTRL_PENDDIS_MASK BIT(1) +#define TWL4030_SIH_CTRL_COR_MASK BIT(2) + +/*----------------------------------------------------------------------*/ + +/* + * GPIO Block Register offsets (use TWL4030_MODULE_GPIO) + */ + +#define REG_GPIODATAIN1 0x0 +#define REG_GPIODATAIN2 0x1 +#define REG_GPIODATAIN3 0x2 +#define REG_GPIODATADIR1 0x3 +#define REG_GPIODATADIR2 0x4 +#define REG_GPIODATADIR3 0x5 +#define REG_GPIODATAOUT1 0x6 +#define REG_GPIODATAOUT2 0x7 +#define REG_GPIODATAOUT3 0x8 +#define REG_CLEARGPIODATAOUT1 0x9 +#define REG_CLEARGPIODATAOUT2 0xA +#define REG_CLEARGPIODATAOUT3 0xB +#define REG_SETGPIODATAOUT1 0xC +#define REG_SETGPIODATAOUT2 0xD +#define REG_SETGPIODATAOUT3 0xE +#define REG_GPIO_DEBEN1 0xF +#define REG_GPIO_DEBEN2 0x10 +#define REG_GPIO_DEBEN3 0x11 +#define REG_GPIO_CTRL 0x12 +#define REG_GPIOPUPDCTR1 0x13 +#define REG_GPIOPUPDCTR2 0x14 +#define REG_GPIOPUPDCTR3 0x15 +#define REG_GPIOPUPDCTR4 0x16 +#define REG_GPIOPUPDCTR5 0x17 +#define REG_GPIO_ISR1A 0x19 +#define REG_GPIO_ISR2A 0x1A +#define REG_GPIO_ISR3A 0x1B +#define REG_GPIO_IMR1A 0x1C +#define REG_GPIO_IMR2A 0x1D +#define REG_GPIO_IMR3A 0x1E +#define REG_GPIO_ISR1B 0x1F +#define REG_GPIO_ISR2B 0x20 +#define REG_GPIO_ISR3B 0x21 +#define REG_GPIO_IMR1B 0x22 +#define REG_GPIO_IMR2B 0x23 +#define REG_GPIO_IMR3B 0x24 +#define REG_GPIO_EDR1 0x28 +#define REG_GPIO_EDR2 0x29 +#define REG_GPIO_EDR3 0x2A +#define REG_GPIO_EDR4 0x2B +#define REG_GPIO_EDR5 0x2C +#define REG_GPIO_SIH_CTRL 0x2D + +/* Up to 18 signals are available as GPIOs, when their + * pins are not assigned to another use (such as ULPI/USB). + */ +#define TWL4030_GPIO_MAX 18 + +/*----------------------------------------------------------------------*/ + +/*Interface Bit Register (INTBR) offsets + *(Use TWL_4030_MODULE_INTBR) + */ + +#define REG_IDCODE_7_0 0x00 +#define REG_IDCODE_15_8 0x01 +#define REG_IDCODE_16_23 0x02 +#define REG_IDCODE_31_24 0x03 +#define REG_GPPUPDCTR1 0x0F +#define REG_UNLOCK_TEST_REG 0x12 + +/*I2C1 and I2C4(SR) SDA/SCL pull-up control bits */ + +#define I2C_SCL_CTRL_PU BIT(0) +#define I2C_SDA_CTRL_PU BIT(2) +#define SR_I2C_SCL_CTRL_PU BIT(4) +#define SR_I2C_SDA_CTRL_PU BIT(6) + +#define TWL_EEPROM_R_UNLOCK 0x49 + +/*----------------------------------------------------------------------*/ + +/* + * Keypad register offsets (use TWL4030_MODULE_KEYPAD) + * ... SIH/interrupt only + */ + +#define TWL4030_KEYPAD_KEYP_ISR1 0x11 +#define TWL4030_KEYPAD_KEYP_IMR1 0x12 +#define TWL4030_KEYPAD_KEYP_ISR2 0x13 +#define TWL4030_KEYPAD_KEYP_IMR2 0x14 +#define TWL4030_KEYPAD_KEYP_SIR 0x15 /* test register */ +#define TWL4030_KEYPAD_KEYP_EDR 0x16 +#define TWL4030_KEYPAD_KEYP_SIH_CTRL 0x17 + +/*----------------------------------------------------------------------*/ + +/* + * Multichannel ADC register offsets (use TWL4030_MODULE_MADC) + * ... SIH/interrupt only + */ + +#define TWL4030_MADC_ISR1 0x61 +#define TWL4030_MADC_IMR1 0x62 +#define TWL4030_MADC_ISR2 0x63 +#define TWL4030_MADC_IMR2 0x64 +#define TWL4030_MADC_SIR 0x65 /* test register */ +#define TWL4030_MADC_EDR 0x66 +#define TWL4030_MADC_SIH_CTRL 0x67 + +/*----------------------------------------------------------------------*/ + +/* + * Battery charger register offsets (use TWL4030_MODULE_INTERRUPTS) + */ + +#define TWL4030_INTERRUPTS_BCIISR1A 0x0 +#define TWL4030_INTERRUPTS_BCIISR2A 0x1 +#define TWL4030_INTERRUPTS_BCIIMR1A 0x2 +#define TWL4030_INTERRUPTS_BCIIMR2A 0x3 +#define TWL4030_INTERRUPTS_BCIISR1B 0x4 +#define TWL4030_INTERRUPTS_BCIISR2B 0x5 +#define TWL4030_INTERRUPTS_BCIIMR1B 0x6 +#define TWL4030_INTERRUPTS_BCIIMR2B 0x7 +#define TWL4030_INTERRUPTS_BCISIR1 0x8 /* test register */ +#define TWL4030_INTERRUPTS_BCISIR2 0x9 /* test register */ +#define TWL4030_INTERRUPTS_BCIEDR1 0xa +#define TWL4030_INTERRUPTS_BCIEDR2 0xb +#define TWL4030_INTERRUPTS_BCIEDR3 0xc +#define TWL4030_INTERRUPTS_BCISIHCTRL 0xd + +/*----------------------------------------------------------------------*/ + +/* + * Power Interrupt block register offsets (use TWL4030_MODULE_INT) + */ + +#define TWL4030_INT_PWR_ISR1 0x0 +#define TWL4030_INT_PWR_IMR1 0x1 +#define TWL4030_INT_PWR_ISR2 0x2 +#define TWL4030_INT_PWR_IMR2 0x3 +#define TWL4030_INT_PWR_SIR 0x4 /* test register */ +#define TWL4030_INT_PWR_EDR1 0x5 +#define TWL4030_INT_PWR_EDR2 0x6 +#define TWL4030_INT_PWR_SIH_CTRL 0x7 + +/*----------------------------------------------------------------------*/ + +/* + * Accessory Interrupts + */ +#define TWL5031_ACIIMR_LSB 0x05 +#define TWL5031_ACIIMR_MSB 0x06 +#define TWL5031_ACIIDR_LSB 0x07 +#define TWL5031_ACIIDR_MSB 0x08 +#define TWL5031_ACCISR1 0x0F +#define TWL5031_ACCIMR1 0x10 +#define TWL5031_ACCISR2 0x11 +#define TWL5031_ACCIMR2 0x12 +#define TWL5031_ACCSIR 0x13 +#define TWL5031_ACCEDR1 0x14 +#define TWL5031_ACCSIHCTRL 0x15 + +/*----------------------------------------------------------------------*/ + +/* + * Battery Charger Controller + */ + +#define TWL5031_INTERRUPTS_BCIISR1 0x0 +#define TWL5031_INTERRUPTS_BCIIMR1 0x1 +#define TWL5031_INTERRUPTS_BCIISR2 0x2 +#define TWL5031_INTERRUPTS_BCIIMR2 0x3 +#define TWL5031_INTERRUPTS_BCISIR 0x4 +#define TWL5031_INTERRUPTS_BCIEDR1 0x5 +#define TWL5031_INTERRUPTS_BCIEDR2 0x6 +#define TWL5031_INTERRUPTS_BCISIHCTRL 0x7 + +/*----------------------------------------------------------------------*/ + +/* + * PM Master module register offsets (use TWL4030_MODULE_PM_MASTER) + */ + +#define TWL4030_PM_MASTER_CFG_P1_TRANSITION 0x00 +#define TWL4030_PM_MASTER_CFG_P2_TRANSITION 0x01 +#define TWL4030_PM_MASTER_CFG_P3_TRANSITION 0x02 +#define TWL4030_PM_MASTER_CFG_P123_TRANSITION 0x03 +#define TWL4030_PM_MASTER_STS_BOOT 0x04 +#define TWL4030_PM_MASTER_CFG_BOOT 0x05 +#define TWL4030_PM_MASTER_SHUNDAN 0x06 +#define TWL4030_PM_MASTER_BOOT_BCI 0x07 +#define TWL4030_PM_MASTER_CFG_PWRANA1 0x08 +#define TWL4030_PM_MASTER_CFG_PWRANA2 0x09 +#define TWL4030_PM_MASTER_BACKUP_MISC_STS 0x0b +#define TWL4030_PM_MASTER_BACKUP_MISC_CFG 0x0c +#define TWL4030_PM_MASTER_BACKUP_MISC_TST 0x0d +#define TWL4030_PM_MASTER_PROTECT_KEY 0x0e +#define TWL4030_PM_MASTER_STS_HW_CONDITIONS 0x0f +#define TWL4030_PM_MASTER_P1_SW_EVENTS 0x10 +#define TWL4030_PM_MASTER_P2_SW_EVENTS 0x11 +#define TWL4030_PM_MASTER_P3_SW_EVENTS 0x12 +#define TWL4030_PM_MASTER_STS_P123_STATE 0x13 +#define TWL4030_PM_MASTER_PB_CFG 0x14 +#define TWL4030_PM_MASTER_PB_WORD_MSB 0x15 +#define TWL4030_PM_MASTER_PB_WORD_LSB 0x16 +#define TWL4030_PM_MASTER_SEQ_ADD_W2P 0x1c +#define TWL4030_PM_MASTER_SEQ_ADD_P2A 0x1d +#define TWL4030_PM_MASTER_SEQ_ADD_A2W 0x1e +#define TWL4030_PM_MASTER_SEQ_ADD_A2S 0x1f +#define TWL4030_PM_MASTER_SEQ_ADD_S2A12 0x20 +#define TWL4030_PM_MASTER_SEQ_ADD_S2A3 0x21 +#define TWL4030_PM_MASTER_SEQ_ADD_WARM 0x22 +#define TWL4030_PM_MASTER_MEMORY_ADDRESS 0x23 +#define TWL4030_PM_MASTER_MEMORY_DATA 0x24 + +#define TWL4030_PM_MASTER_KEY_CFG1 0xc0 +#define TWL4030_PM_MASTER_KEY_CFG2 0x0c + +#define TWL4030_PM_MASTER_KEY_TST1 0xe0 +#define TWL4030_PM_MASTER_KEY_TST2 0x0e + +#define TWL4030_PM_MASTER_GLOBAL_TST 0xb6 + +/*----------------------------------------------------------------------*/ + +/* Power bus message definitions */ + +/* The TWL4030/5030 splits its power-management resources (the various + * regulators, clock and reset lines) into 3 processor groups - P1, P2 and + * P3. These groups can then be configured to transition between sleep, wait-on + * and active states by sending messages to the power bus. See Section 5.4.2 + * Power Resources of TWL4030 TRM + */ + +/* Processor groups */ +#define DEV_GRP_NULL 0x0 +#define DEV_GRP_P1 0x1 /* P1: all OMAP devices */ +#define DEV_GRP_P2 0x2 /* P2: all Modem devices */ +#define DEV_GRP_P3 0x4 /* P3: all peripheral devices */ + +/* Resource groups */ +#define RES_GRP_RES 0x0 /* Reserved */ +#define RES_GRP_PP 0x1 /* Power providers */ +#define RES_GRP_RC 0x2 /* Reset and control */ +#define RES_GRP_PP_RC 0x3 +#define RES_GRP_PR 0x4 /* Power references */ +#define RES_GRP_PP_PR 0x5 +#define RES_GRP_RC_PR 0x6 +#define RES_GRP_ALL 0x7 /* All resource groups */ + +#define RES_TYPE2_R0 0x0 +#define RES_TYPE2_R1 0x1 +#define RES_TYPE2_R2 0x2 + +#define RES_TYPE_R0 0x0 +#define RES_TYPE_ALL 0x7 + +/* Resource states */ +#define RES_STATE_WRST 0xF +#define RES_STATE_ACTIVE 0xE +#define RES_STATE_SLEEP 0x8 +#define RES_STATE_OFF 0x0 + +/* Power resources */ + +/* Power providers */ +#define RES_VAUX1 1 +#define RES_VAUX2 2 +#define RES_VAUX3 3 +#define RES_VAUX4 4 +#define RES_VMMC1 5 +#define RES_VMMC2 6 +#define RES_VPLL1 7 +#define RES_VPLL2 8 +#define RES_VSIM 9 +#define RES_VDAC 10 +#define RES_VINTANA1 11 +#define RES_VINTANA2 12 +#define RES_VINTDIG 13 +#define RES_VIO 14 +#define RES_VDD1 15 +#define RES_VDD2 16 +#define RES_VUSB_1V5 17 +#define RES_VUSB_1V8 18 +#define RES_VUSB_3V1 19 +#define RES_VUSBCP 20 +#define RES_REGEN 21 +/* Reset and control */ +#define RES_NRES_PWRON 22 +#define RES_CLKEN 23 +#define RES_SYSEN 24 +#define RES_HFCLKOUT 25 +#define RES_32KCLKOUT 26 +#define RES_RESET 27 +/* Power Reference */ +#define RES_MAIN_REF 28 + +#define TOTAL_RESOURCES 28 +/* + * Power Bus Message Format ... these can be sent individually by Linux, + * but are usually part of downloaded scripts that are run when various + * power events are triggered. + * + * Broadcast Message (16 Bits): + * DEV_GRP[15:13] MT[12] RES_GRP[11:9] RES_TYPE2[8:7] RES_TYPE[6:4] + * RES_STATE[3:0] + * + * Singular Message (16 Bits): + * DEV_GRP[15:13] MT[12] RES_ID[11:4] RES_STATE[3:0] + */ + +#define MSG_BROADCAST(devgrp, grp, type, type2, state) \ + ( (devgrp) << 13 | 1 << 12 | (grp) << 9 | (type2) << 7 \ + | (type) << 4 | (state)) + +#define MSG_SINGULAR(devgrp, id, state) \ + ((devgrp) << 13 | 0 << 12 | (id) << 4 | (state)) + +#define MSG_BROADCAST_ALL(devgrp, state) \ + ((devgrp) << 5 | (state)) + +#define MSG_BROADCAST_REF MSG_BROADCAST_ALL +#define MSG_BROADCAST_PROV MSG_BROADCAST_ALL +#define MSG_BROADCAST__CLK_RST MSG_BROADCAST_ALL +/*----------------------------------------------------------------------*/ + +struct twl4030_clock_init_data { + bool ck32k_lowpwr_enable; +}; + +struct twl4030_bci_platform_data { + int *battery_tmp_tbl; + unsigned int tblsize; + int bb_uvolt; /* voltage to charge backup battery */ + int bb_uamp; /* current for backup battery charging */ +}; + +/* TWL4030_GPIO_MAX (18) GPIOs, with interrupts */ +struct twl4030_gpio_platform_data { + /* package the two LED signals as output-only GPIOs? */ + bool use_leds; + + /* gpio-n should control VMMC(n+1) if BIT(n) in mmc_cd is set */ + u8 mmc_cd; + + /* if BIT(N) is set, or VMMC(n+1) is linked, debounce GPIO-N */ + u32 debounce; + + /* For gpio-N, bit (1 << N) in "pullups" is set if that pullup + * should be enabled. Else, if that bit is set in "pulldowns", + * that pulldown is enabled. Don't waste power by letting any + * digital inputs float... + */ + u32 pullups; + u32 pulldowns; + + int (*setup)(struct device *dev, + unsigned gpio, unsigned ngpio); + int (*teardown)(struct device *dev, + unsigned gpio, unsigned ngpio); +}; + +struct twl4030_madc_platform_data { + int irq_line; +}; + +/* Boards have unique mappings of {row, col} --> keycode. + * Column and row are 8 bits each, but range only from 0..7. + * a PERSISTENT_KEY is "always on" and never reported. + */ +#define PERSISTENT_KEY(r, c) KEY((r), (c), KEY_RESERVED) + +struct twl4030_keypad_data { + const struct matrix_keymap_data *keymap_data; + unsigned rows; + unsigned cols; + bool rep; +}; + +enum twl4030_usb_mode { + T2_USB_MODE_ULPI = 1, + T2_USB_MODE_CEA2011_3PIN = 2, +}; + +struct twl4030_usb_data { + enum twl4030_usb_mode usb_mode; + unsigned long features; + + int (*phy_init)(struct device *dev); + int (*phy_exit)(struct device *dev); + /* Power on/off the PHY */ + int (*phy_power)(struct device *dev, int iD, int on); + /* enable/disable phy clocks */ + int (*phy_set_clock)(struct device *dev, int on); + /* suspend/resume of phy */ + int (*phy_suspend)(struct device *dev, int suspend); +}; + +struct twl4030_ins { + u16 pmb_message; + u8 delay; +}; + +struct twl4030_script { + struct twl4030_ins *script; + unsigned size; + u8 flags; +#define TWL4030_WRST_SCRIPT (1<<0) +#define TWL4030_WAKEUP12_SCRIPT (1<<1) +#define TWL4030_WAKEUP3_SCRIPT (1<<2) +#define TWL4030_SLEEP_SCRIPT (1<<3) +}; + +struct twl4030_resconfig { + u8 resource; + u8 devgroup; /* Processor group that Power resource belongs to */ + u8 type; /* Power resource addressed, 6 / broadcast message */ + u8 type2; /* Power resource addressed, 3 / broadcast message */ + u8 remap_off; /* off state remapping */ + u8 remap_sleep; /* sleep state remapping */ +}; + +struct twl4030_power_data { + struct twl4030_script **scripts; + unsigned num; + struct twl4030_resconfig *resource_config; + struct twl4030_resconfig *board_config; +#define TWL4030_RESCONFIG_UNDEF ((u8)-1) + bool use_poweroff; /* Board is wired for TWL poweroff */ + bool ac_charger_quirk; /* Disable AC charger on board */ +}; + +extern int twl4030_remove_script(u8 flags); +extern void twl4030_power_off(void); + +struct twl4030_codec_data { + unsigned int digimic_delay; /* in ms */ + unsigned int ramp_delay_value; + unsigned int offset_cncl_path; + unsigned int hs_extmute:1; + int hs_extmute_gpio; +}; + +struct twl4030_vibra_data { + unsigned int coexist; +}; + +struct twl4030_audio_data { + unsigned int audio_mclk; + struct twl4030_codec_data *codec; + struct twl4030_vibra_data *vibra; + + /* twl6040 */ + int audpwron_gpio; /* audio power-on gpio */ + int naudint_irq; /* audio interrupt */ + unsigned int irq_base; +}; + +struct twl4030_platform_data { + struct twl4030_clock_init_data *clock; + struct twl4030_bci_platform_data *bci; + struct twl4030_gpio_platform_data *gpio; + struct twl4030_madc_platform_data *madc; + struct twl4030_keypad_data *keypad; + struct twl4030_usb_data *usb; + struct twl4030_power_data *power; + struct twl4030_audio_data *audio; + + /* Common LDO regulators for TWL4030/TWL6030 */ + struct regulator_init_data *vdac; + struct regulator_init_data *vaux1; + struct regulator_init_data *vaux2; + struct regulator_init_data *vaux3; + struct regulator_init_data *vdd1; + struct regulator_init_data *vdd2; + struct regulator_init_data *vdd3; + /* TWL4030 LDO regulators */ + struct regulator_init_data *vpll1; + struct regulator_init_data *vpll2; + struct regulator_init_data *vmmc1; + struct regulator_init_data *vmmc2; + struct regulator_init_data *vsim; + struct regulator_init_data *vaux4; + struct regulator_init_data *vio; + struct regulator_init_data *vintana1; + struct regulator_init_data *vintana2; + struct regulator_init_data *vintdig; + /* TWL6030 LDO regulators */ + struct regulator_init_data *vmmc; + struct regulator_init_data *vpp; + struct regulator_init_data *vusim; + struct regulator_init_data *vana; + struct regulator_init_data *vcxio; + struct regulator_init_data *vusb; + struct regulator_init_data *clk32kg; + struct regulator_init_data *v1v8; + struct regulator_init_data *v2v1; + /* TWL6032 LDO regulators */ + struct regulator_init_data *ldo1; + struct regulator_init_data *ldo2; + struct regulator_init_data *ldo3; + struct regulator_init_data *ldo4; + struct regulator_init_data *ldo5; + struct regulator_init_data *ldo6; + struct regulator_init_data *ldo7; + struct regulator_init_data *ldoln; + struct regulator_init_data *ldousb; + /* TWL6032 DCDC regulators */ + struct regulator_init_data *smps3; + struct regulator_init_data *smps4; + struct regulator_init_data *vio6025; +}; + +struct twl_regulator_driver_data { + int (*set_voltage)(void *data, int target_uV); + int (*get_voltage)(void *data); + void *data; + unsigned long features; +}; +/* chip-specific feature flags, for twl_regulator_driver_data.features */ +#define TWL4030_VAUX2 BIT(0) /* pre-5030 voltage ranges */ +#define TPS_SUBSET BIT(1) /* tps659[23]0 have fewer LDOs */ +#define TWL5031 BIT(2) /* twl5031 has different registers */ +#define TWL6030_CLASS BIT(3) /* TWL6030 class */ +#define TWL6032_SUBCLASS BIT(4) /* TWL6032 has changed registers */ +#define TWL4030_ALLOW_UNSUPPORTED BIT(5) /* Some voltages are possible + * but not officially supported. + * This flag is necessary to + * enable them. + */ + +/*----------------------------------------------------------------------*/ + +int twl4030_sih_setup(struct device *dev, int module, int irq_base); + +/* Offsets to Power Registers */ +#define TWL4030_VDAC_DEV_GRP 0x3B +#define TWL4030_VDAC_DEDICATED 0x3E +#define TWL4030_VAUX1_DEV_GRP 0x17 +#define TWL4030_VAUX1_DEDICATED 0x1A +#define TWL4030_VAUX2_DEV_GRP 0x1B +#define TWL4030_VAUX2_DEDICATED 0x1E +#define TWL4030_VAUX3_DEV_GRP 0x1F +#define TWL4030_VAUX3_DEDICATED 0x22 + +static inline int twl4030charger_usb_en(int enable) { return 0; } + +/*----------------------------------------------------------------------*/ + +/* Linux-specific regulator identifiers ... for now, we only support + * the LDOs, and leave the three buck converters alone. VDD1 and VDD2 + * need to tie into hardware based voltage scaling (cpufreq etc), while + * VIO is generally fixed. + */ + +/* TWL4030 SMPS/LDO's */ +/* EXTERNAL dc-to-dc buck converters */ +#define TWL4030_REG_VDD1 0 +#define TWL4030_REG_VDD2 1 +#define TWL4030_REG_VIO 2 + +/* EXTERNAL LDOs */ +#define TWL4030_REG_VDAC 3 +#define TWL4030_REG_VPLL1 4 +#define TWL4030_REG_VPLL2 5 /* not on all chips */ +#define TWL4030_REG_VMMC1 6 +#define TWL4030_REG_VMMC2 7 /* not on all chips */ +#define TWL4030_REG_VSIM 8 /* not on all chips */ +#define TWL4030_REG_VAUX1 9 /* not on all chips */ +#define TWL4030_REG_VAUX2_4030 10 /* (twl4030-specific) */ +#define TWL4030_REG_VAUX2 11 /* (twl5030 and newer) */ +#define TWL4030_REG_VAUX3 12 /* not on all chips */ +#define TWL4030_REG_VAUX4 13 /* not on all chips */ + +/* INTERNAL LDOs */ +#define TWL4030_REG_VINTANA1 14 +#define TWL4030_REG_VINTANA2 15 +#define TWL4030_REG_VINTDIG 16 +#define TWL4030_REG_VUSB1V5 17 +#define TWL4030_REG_VUSB1V8 18 +#define TWL4030_REG_VUSB3V1 19 + +/* TWL6030 SMPS/LDO's */ +/* EXTERNAL dc-to-dc buck convertor controllable via SR */ +#define TWL6030_REG_VDD1 30 +#define TWL6030_REG_VDD2 31 +#define TWL6030_REG_VDD3 32 + +/* Non SR compliant dc-to-dc buck convertors */ +#define TWL6030_REG_VMEM 33 +#define TWL6030_REG_V2V1 34 +#define TWL6030_REG_V1V29 35 +#define TWL6030_REG_V1V8 36 + +/* EXTERNAL LDOs */ +#define TWL6030_REG_VAUX1_6030 37 +#define TWL6030_REG_VAUX2_6030 38 +#define TWL6030_REG_VAUX3_6030 39 +#define TWL6030_REG_VMMC 40 +#define TWL6030_REG_VPP 41 +#define TWL6030_REG_VUSIM 42 +#define TWL6030_REG_VANA 43 +#define TWL6030_REG_VCXIO 44 +#define TWL6030_REG_VDAC 45 +#define TWL6030_REG_VUSB 46 + +/* INTERNAL LDOs */ +#define TWL6030_REG_VRTC 47 +#define TWL6030_REG_CLK32KG 48 + +/* LDOs on 6025 have different names */ +#define TWL6032_REG_LDO2 49 +#define TWL6032_REG_LDO4 50 +#define TWL6032_REG_LDO3 51 +#define TWL6032_REG_LDO5 52 +#define TWL6032_REG_LDO1 53 +#define TWL6032_REG_LDO7 54 +#define TWL6032_REG_LDO6 55 +#define TWL6032_REG_LDOLN 56 +#define TWL6032_REG_LDOUSB 57 + +/* 6025 DCDC supplies */ +#define TWL6032_REG_SMPS3 58 +#define TWL6032_REG_SMPS4 59 +#define TWL6032_REG_VIO 60 + + +#endif /* End of __TWL4030_H */ diff --git a/sound/soc/codecs/twl4030.c b/sound/soc/codecs/twl4030.c index a2104d6..bd86a2d 100644 --- a/sound/soc/codecs/twl4030.c +++ b/sound/soc/codecs/twl4030.c @@ -28,7 +28,7 @@ #include #include #include -#include +#include #include #include #include -- cgit v1.1 From a7a0db07e9ffd55278b080b0a8e466853075f2c7 Mon Sep 17 00:00:00 2001 From: Fabrice Gasnier Date: Mon, 28 Aug 2017 12:04:06 +0200 Subject: dt-bindings: mfd: Add STM32 LPTimer binding Add documentation for STMicroelectronics STM32 Low-Power Timer binding. Signed-off-by: Fabrice Gasnier Acked-by: Jonathan Cameron Acked-by: Rob Herring Signed-off-by: Lee Jones --- .../devicetree/bindings/mfd/stm32-lptimer.txt | 48 ++++++++++++++++++++++ 1 file changed, 48 insertions(+) create mode 100644 Documentation/devicetree/bindings/mfd/stm32-lptimer.txt diff --git a/Documentation/devicetree/bindings/mfd/stm32-lptimer.txt b/Documentation/devicetree/bindings/mfd/stm32-lptimer.txt new file mode 100644 index 0000000..2a9ff29 --- /dev/null +++ b/Documentation/devicetree/bindings/mfd/stm32-lptimer.txt @@ -0,0 +1,48 @@ +STMicroelectronics STM32 Low-Power Timer + +The STM32 Low-Power Timer (LPTIM) is a 16-bit timer that provides several +functions: +- PWM output (with programmable prescaler, configurable polarity) +- Quadrature encoder, counter +- Trigger source for STM32 ADC/DAC (LPTIM_OUT) + +Required properties: +- compatible: Must be "st,stm32-lptimer". +- reg: Offset and length of the device's register set. +- clocks: Phandle to the clock used by the LP Timer module. +- clock-names: Must be "mux". +- #address-cells: Should be '<1>'. +- #size-cells: Should be '<0>'. + +Optional subnodes: +- pwm: See ../pwm/pwm-stm32-lp.txt +- counter: See ../iio/timer/stm32-lptimer-cnt.txt +- trigger: See ../iio/timer/stm32-lptimer-trigger.txt + +Example: + + timer@40002400 { + compatible = "st,stm32-lptimer"; + reg = <0x40002400 0x400>; + clocks = <&timer_clk>; + clock-names = "mux"; + #address-cells = <1>; + #size-cells = <0>; + + pwm { + compatible = "st,stm32-pwm-lp"; + pinctrl-names = "default"; + pinctrl-0 = <&lppwm1_pins>; + }; + + trigger@0 { + compatible = "st,stm32-lptimer-trigger"; + reg = <0>; + }; + + counter { + compatible = "st,stm32-lptimer-counter"; + pinctrl-names = "default"; + pinctrl-0 = <&lptim1_in_pins>; + }; + }; -- cgit v1.1 From e8924005b4e7964313536547d4b73406330be26d Mon Sep 17 00:00:00 2001 From: Fabrice Gasnier Date: Mon, 28 Aug 2017 12:04:07 +0200 Subject: mfd: Add STM32 LPTimer driver STM32 Low-Power Timer hardware block can be used for: - PWM generation - IIO trigger (in sync with PWM) - IIO quadrature encoder counter PWM and IIO timer configuration are mixed in the same registers so we need a multi fonction driver to be able to share those registers. Signed-off-by: Fabrice Gasnier Signed-off-by: Lee Jones --- drivers/mfd/Kconfig | 14 +++++ drivers/mfd/Makefile | 1 + drivers/mfd/stm32-lptimer.c | 107 ++++++++++++++++++++++++++++++++++++++ include/linux/mfd/stm32-lptimer.h | 62 ++++++++++++++++++++++ 4 files changed, 184 insertions(+) create mode 100644 drivers/mfd/stm32-lptimer.c create mode 100644 include/linux/mfd/stm32-lptimer.h diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig index 94ad2c1..fe76db9 100644 --- a/drivers/mfd/Kconfig +++ b/drivers/mfd/Kconfig @@ -1723,6 +1723,20 @@ config MFD_STW481X in various ST Microelectronics and ST-Ericsson embedded Nomadik series. +config MFD_STM32_LPTIMER + tristate "Support for STM32 Low-Power Timer" + depends on (ARCH_STM32 && OF) || COMPILE_TEST + select MFD_CORE + select REGMAP + select REGMAP_MMIO + help + Select this option to enable STM32 Low-Power Timer driver + used for PWM, IIO Trigger, IIO Encoder and Counter. Shared + resources are also dealt with here. + + To compile this driver as a module, choose M here: the + module will be called stm32-lptimer. + config MFD_STM32_TIMERS tristate "Support for STM32 Timers" depends on (ARCH_STM32 && OF) || COMPILE_TEST diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile index 080793b..b80b1a3 100644 --- a/drivers/mfd/Makefile +++ b/drivers/mfd/Makefile @@ -221,5 +221,6 @@ obj-$(CONFIG_MFD_MT6397) += mt6397-core.o obj-$(CONFIG_MFD_ALTERA_A10SR) += altera-a10sr.o obj-$(CONFIG_MFD_SUN4I_GPADC) += sun4i-gpadc.o +obj-$(CONFIG_MFD_STM32_LPTIMER) += stm32-lptimer.o obj-$(CONFIG_MFD_STM32_TIMERS) += stm32-timers.o obj-$(CONFIG_MFD_MXS_LRADC) += mxs-lradc.o diff --git a/drivers/mfd/stm32-lptimer.c b/drivers/mfd/stm32-lptimer.c new file mode 100644 index 0000000..075330a --- /dev/null +++ b/drivers/mfd/stm32-lptimer.c @@ -0,0 +1,107 @@ +/* + * STM32 Low-Power Timer parent driver. + * + * Copyright (C) STMicroelectronics 2017 + * + * Author: Fabrice Gasnier + * + * Inspired by Benjamin Gaignard's stm32-timers driver + * + * License terms: GNU General Public License (GPL), version 2 + */ + +#include +#include +#include + +#define STM32_LPTIM_MAX_REGISTER 0x3fc + +static const struct regmap_config stm32_lptimer_regmap_cfg = { + .reg_bits = 32, + .val_bits = 32, + .reg_stride = sizeof(u32), + .max_register = STM32_LPTIM_MAX_REGISTER, +}; + +static int stm32_lptimer_detect_encoder(struct stm32_lptimer *ddata) +{ + u32 val; + int ret; + + /* + * Quadrature encoder mode bit can only be written and read back when + * Low-Power Timer supports it. + */ + ret = regmap_update_bits(ddata->regmap, STM32_LPTIM_CFGR, + STM32_LPTIM_ENC, STM32_LPTIM_ENC); + if (ret) + return ret; + + ret = regmap_read(ddata->regmap, STM32_LPTIM_CFGR, &val); + if (ret) + return ret; + + ret = regmap_update_bits(ddata->regmap, STM32_LPTIM_CFGR, + STM32_LPTIM_ENC, 0); + if (ret) + return ret; + + ddata->has_encoder = !!(val & STM32_LPTIM_ENC); + + return 0; +} + +static int stm32_lptimer_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct stm32_lptimer *ddata; + struct resource *res; + void __iomem *mmio; + int ret; + + ddata = devm_kzalloc(dev, sizeof(*ddata), GFP_KERNEL); + if (!ddata) + return -ENOMEM; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + mmio = devm_ioremap_resource(dev, res); + if (IS_ERR(mmio)) + return PTR_ERR(mmio); + + ddata->regmap = devm_regmap_init_mmio_clk(dev, "mux", mmio, + &stm32_lptimer_regmap_cfg); + if (IS_ERR(ddata->regmap)) + return PTR_ERR(ddata->regmap); + + ddata->clk = devm_clk_get(dev, NULL); + if (IS_ERR(ddata->clk)) + return PTR_ERR(ddata->clk); + + ret = stm32_lptimer_detect_encoder(ddata); + if (ret) + return ret; + + platform_set_drvdata(pdev, ddata); + + return devm_of_platform_populate(&pdev->dev); +} + +static const struct of_device_id stm32_lptimer_of_match[] = { + { .compatible = "st,stm32-lptimer", }, + {}, +}; +MODULE_DEVICE_TABLE(of, stm32_lptimer_of_match); + +static struct platform_driver stm32_lptimer_driver = { + .probe = stm32_lptimer_probe, + .driver = { + .name = "stm32-lptimer", + .of_match_table = stm32_lptimer_of_match, + }, +}; +module_platform_driver(stm32_lptimer_driver); + +MODULE_AUTHOR("Fabrice Gasnier "); +MODULE_DESCRIPTION("STMicroelectronics STM32 Low-Power Timer"); +MODULE_ALIAS("platform:stm32-lptimer"); +MODULE_LICENSE("GPL v2"); diff --git a/include/linux/mfd/stm32-lptimer.h b/include/linux/mfd/stm32-lptimer.h new file mode 100644 index 0000000..77c7cf4 --- /dev/null +++ b/include/linux/mfd/stm32-lptimer.h @@ -0,0 +1,62 @@ +/* + * STM32 Low-Power Timer parent driver. + * + * Copyright (C) STMicroelectronics 2017 + * + * Author: Fabrice Gasnier + * + * Inspired by Benjamin Gaignard's stm32-timers driver + * + * License terms: GNU General Public License (GPL), version 2 + */ + +#ifndef _LINUX_STM32_LPTIMER_H_ +#define _LINUX_STM32_LPTIMER_H_ + +#include +#include + +#define STM32_LPTIM_ISR 0x00 /* Interrupt and Status Reg */ +#define STM32_LPTIM_ICR 0x04 /* Interrupt Clear Reg */ +#define STM32_LPTIM_IER 0x08 /* Interrupt Enable Reg */ +#define STM32_LPTIM_CFGR 0x0C /* Configuration Reg */ +#define STM32_LPTIM_CR 0x10 /* Control Reg */ +#define STM32_LPTIM_CMP 0x14 /* Compare Reg */ +#define STM32_LPTIM_ARR 0x18 /* Autoreload Reg */ +#define STM32_LPTIM_CNT 0x1C /* Counter Reg */ + +/* STM32_LPTIM_ISR - bit fields */ +#define STM32_LPTIM_CMPOK_ARROK GENMASK(4, 3) +#define STM32_LPTIM_ARROK BIT(4) +#define STM32_LPTIM_CMPOK BIT(3) + +/* STM32_LPTIM_ICR - bit fields */ +#define STM32_LPTIM_CMPOKCF_ARROKCF GENMASK(4, 3) + +/* STM32_LPTIM_CR - bit fields */ +#define STM32_LPTIM_CNTSTRT BIT(2) +#define STM32_LPTIM_ENABLE BIT(0) + +/* STM32_LPTIM_CFGR - bit fields */ +#define STM32_LPTIM_ENC BIT(24) +#define STM32_LPTIM_COUNTMODE BIT(23) +#define STM32_LPTIM_WAVPOL BIT(21) +#define STM32_LPTIM_PRESC GENMASK(11, 9) +#define STM32_LPTIM_CKPOL GENMASK(2, 1) + +/* STM32_LPTIM_ARR */ +#define STM32_LPTIM_MAX_ARR 0xFFFF + +/** + * struct stm32_lptimer - STM32 Low-Power Timer data assigned by parent device + * @clk: clock reference for this instance + * @regmap: register map reference for this instance + * @has_encoder: indicates this Low-Power Timer supports encoder mode + */ +struct stm32_lptimer { + struct clk *clk; + struct regmap *regmap; + bool has_encoder; +}; + +#endif -- cgit v1.1 From e70a540b4e023045a85529edbd04da73a0c72a12 Mon Sep 17 00:00:00 2001 From: Fabrice Gasnier Date: Mon, 28 Aug 2017 12:04:09 +0200 Subject: pwm: Add STM32 LPTimer PWM driver Add support for single PWM channel on Low-Power Timer, that can be found on some STM32 platforms. Signed-off-by: Fabrice Gasnier Acked-by: Thierry Reding Signed-off-by: Lee Jones --- drivers/pwm/Kconfig | 10 ++ drivers/pwm/Makefile | 1 + drivers/pwm/pwm-stm32-lp.c | 246 +++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 257 insertions(+) create mode 100644 drivers/pwm/pwm-stm32-lp.c diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig index 313c107..7cb982b 100644 --- a/drivers/pwm/Kconfig +++ b/drivers/pwm/Kconfig @@ -417,6 +417,16 @@ config PWM_STM32 To compile this driver as a module, choose M here: the module will be called pwm-stm32. +config PWM_STM32_LP + tristate "STMicroelectronics STM32 PWM LP" + depends on MFD_STM32_LPTIMER || COMPILE_TEST + help + Generic PWM framework driver for STMicroelectronics STM32 SoCs + with Low-Power Timer (LPTIM). + + To compile this driver as a module, choose M here: the module + will be called pwm-stm32-lp. + config PWM_STMPE bool "STMPE expander PWM export" depends on MFD_STMPE diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile index 93da1f7..a3a4bee 100644 --- a/drivers/pwm/Makefile +++ b/drivers/pwm/Makefile @@ -40,6 +40,7 @@ obj-$(CONFIG_PWM_SAMSUNG) += pwm-samsung.o obj-$(CONFIG_PWM_SPEAR) += pwm-spear.o obj-$(CONFIG_PWM_STI) += pwm-sti.o obj-$(CONFIG_PWM_STM32) += pwm-stm32.o +obj-$(CONFIG_PWM_STM32_LP) += pwm-stm32-lp.o obj-$(CONFIG_PWM_STMPE) += pwm-stmpe.o obj-$(CONFIG_PWM_SUN4I) += pwm-sun4i.o obj-$(CONFIG_PWM_TEGRA) += pwm-tegra.o diff --git a/drivers/pwm/pwm-stm32-lp.c b/drivers/pwm/pwm-stm32-lp.c new file mode 100644 index 0000000..9793b29 --- /dev/null +++ b/drivers/pwm/pwm-stm32-lp.c @@ -0,0 +1,246 @@ +/* + * STM32 Low-Power Timer PWM driver + * + * Copyright (C) STMicroelectronics 2017 + * + * Author: Gerald Baeza + * + * License terms: GNU General Public License (GPL), version 2 + * + * Inspired by Gerald Baeza's pwm-stm32 driver + */ + +#include +#include +#include +#include +#include +#include + +struct stm32_pwm_lp { + struct pwm_chip chip; + struct clk *clk; + struct regmap *regmap; +}; + +static inline struct stm32_pwm_lp *to_stm32_pwm_lp(struct pwm_chip *chip) +{ + return container_of(chip, struct stm32_pwm_lp, chip); +} + +/* STM32 Low-Power Timer is preceded by a configurable power-of-2 prescaler */ +#define STM32_LPTIM_MAX_PRESCALER 128 + +static int stm32_pwm_lp_apply(struct pwm_chip *chip, struct pwm_device *pwm, + struct pwm_state *state) +{ + struct stm32_pwm_lp *priv = to_stm32_pwm_lp(chip); + unsigned long long prd, div, dty; + struct pwm_state cstate; + u32 val, mask, cfgr, presc = 0; + bool reenable; + int ret; + + pwm_get_state(pwm, &cstate); + reenable = !cstate.enabled; + + if (!state->enabled) { + if (cstate.enabled) { + /* Disable LP timer */ + ret = regmap_write(priv->regmap, STM32_LPTIM_CR, 0); + if (ret) + return ret; + /* disable clock to PWM counter */ + clk_disable(priv->clk); + } + return 0; + } + + /* Calculate the period and prescaler value */ + div = (unsigned long long)clk_get_rate(priv->clk) * state->period; + do_div(div, NSEC_PER_SEC); + prd = div; + while (div > STM32_LPTIM_MAX_ARR) { + presc++; + if ((1 << presc) > STM32_LPTIM_MAX_PRESCALER) { + dev_err(priv->chip.dev, "max prescaler exceeded\n"); + return -EINVAL; + } + div = prd >> presc; + } + prd = div; + + /* Calculate the duty cycle */ + dty = prd * state->duty_cycle; + do_div(dty, state->period); + + if (!cstate.enabled) { + /* enable clock to drive PWM counter */ + ret = clk_enable(priv->clk); + if (ret) + return ret; + } + + ret = regmap_read(priv->regmap, STM32_LPTIM_CFGR, &cfgr); + if (ret) + goto err; + + if ((FIELD_GET(STM32_LPTIM_PRESC, cfgr) != presc) || + (FIELD_GET(STM32_LPTIM_WAVPOL, cfgr) != state->polarity)) { + val = FIELD_PREP(STM32_LPTIM_PRESC, presc); + val |= FIELD_PREP(STM32_LPTIM_WAVPOL, state->polarity); + mask = STM32_LPTIM_PRESC | STM32_LPTIM_WAVPOL; + + /* Must disable LP timer to modify CFGR */ + reenable = true; + ret = regmap_write(priv->regmap, STM32_LPTIM_CR, 0); + if (ret) + goto err; + + ret = regmap_update_bits(priv->regmap, STM32_LPTIM_CFGR, mask, + val); + if (ret) + goto err; + } + + if (reenable) { + /* Must (re)enable LP timer to modify CMP & ARR */ + ret = regmap_write(priv->regmap, STM32_LPTIM_CR, + STM32_LPTIM_ENABLE); + if (ret) + goto err; + } + + ret = regmap_write(priv->regmap, STM32_LPTIM_ARR, prd - 1); + if (ret) + goto err; + + ret = regmap_write(priv->regmap, STM32_LPTIM_CMP, prd - (1 + dty)); + if (ret) + goto err; + + /* ensure CMP & ARR registers are properly written */ + ret = regmap_read_poll_timeout(priv->regmap, STM32_LPTIM_ISR, val, + (val & STM32_LPTIM_CMPOK_ARROK), + 100, 1000); + if (ret) { + dev_err(priv->chip.dev, "ARR/CMP registers write issue\n"); + goto err; + } + ret = regmap_write(priv->regmap, STM32_LPTIM_ICR, + STM32_LPTIM_CMPOKCF_ARROKCF); + if (ret) + goto err; + + if (reenable) { + /* Start LP timer in continuous mode */ + ret = regmap_update_bits(priv->regmap, STM32_LPTIM_CR, + STM32_LPTIM_CNTSTRT, + STM32_LPTIM_CNTSTRT); + if (ret) { + regmap_write(priv->regmap, STM32_LPTIM_CR, 0); + goto err; + } + } + + return 0; +err: + if (!cstate.enabled) + clk_disable(priv->clk); + + return ret; +} + +static void stm32_pwm_lp_get_state(struct pwm_chip *chip, + struct pwm_device *pwm, + struct pwm_state *state) +{ + struct stm32_pwm_lp *priv = to_stm32_pwm_lp(chip); + unsigned long rate = clk_get_rate(priv->clk); + u32 val, presc, prd; + u64 tmp; + + regmap_read(priv->regmap, STM32_LPTIM_CR, &val); + state->enabled = !!FIELD_GET(STM32_LPTIM_ENABLE, val); + /* Keep PWM counter clock refcount in sync with PWM initial state */ + if (state->enabled) + clk_enable(priv->clk); + + regmap_read(priv->regmap, STM32_LPTIM_CFGR, &val); + presc = FIELD_GET(STM32_LPTIM_PRESC, val); + state->polarity = FIELD_GET(STM32_LPTIM_WAVPOL, val); + + regmap_read(priv->regmap, STM32_LPTIM_ARR, &prd); + tmp = prd + 1; + tmp = (tmp << presc) * NSEC_PER_SEC; + state->period = DIV_ROUND_CLOSEST_ULL(tmp, rate); + + regmap_read(priv->regmap, STM32_LPTIM_CMP, &val); + tmp = prd - val; + tmp = (tmp << presc) * NSEC_PER_SEC; + state->duty_cycle = DIV_ROUND_CLOSEST_ULL(tmp, rate); +} + +static const struct pwm_ops stm32_pwm_lp_ops = { + .owner = THIS_MODULE, + .apply = stm32_pwm_lp_apply, + .get_state = stm32_pwm_lp_get_state, +}; + +static int stm32_pwm_lp_probe(struct platform_device *pdev) +{ + struct stm32_lptimer *ddata = dev_get_drvdata(pdev->dev.parent); + struct stm32_pwm_lp *priv; + int ret; + + priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->regmap = ddata->regmap; + priv->clk = ddata->clk; + priv->chip.base = -1; + priv->chip.dev = &pdev->dev; + priv->chip.ops = &stm32_pwm_lp_ops; + priv->chip.npwm = 1; + + ret = pwmchip_add(&priv->chip); + if (ret < 0) + return ret; + + platform_set_drvdata(pdev, priv); + + return 0; +} + +static int stm32_pwm_lp_remove(struct platform_device *pdev) +{ + struct stm32_pwm_lp *priv = platform_get_drvdata(pdev); + unsigned int i; + + for (i = 0; i < priv->chip.npwm; i++) + if (pwm_is_enabled(&priv->chip.pwms[i])) + pwm_disable(&priv->chip.pwms[i]); + + return pwmchip_remove(&priv->chip); +} + +static const struct of_device_id stm32_pwm_lp_of_match[] = { + { .compatible = "st,stm32-pwm-lp", }, + {}, +}; +MODULE_DEVICE_TABLE(of, stm32_pwm_lp_of_match); + +static struct platform_driver stm32_pwm_lp_driver = { + .probe = stm32_pwm_lp_probe, + .remove = stm32_pwm_lp_remove, + .driver = { + .name = "stm32-pwm-lp", + .of_match_table = of_match_ptr(stm32_pwm_lp_of_match), + }, +}; +module_platform_driver(stm32_pwm_lp_driver); + +MODULE_ALIAS("platform:stm32-pwm-lp"); +MODULE_DESCRIPTION("STMicroelectronics STM32 PWM LP driver"); +MODULE_LICENSE("GPL v2"); -- cgit v1.1 From efd11ad164bf78c2ac1d9d8c27257bbdba494388 Mon Sep 17 00:00:00 2001 From: Fabrice Gasnier Date: Mon, 28 Aug 2017 12:04:08 +0200 Subject: dt-bindings: pwm: Add STM32 LPTimer PWM binding Add documentation for STMicroelectronics STM32 Low-Power Timer PWM binding. Signed-off-by: Fabrice Gasnier Acked-by: Rob Herring Signed-off-by: Lee Jones --- .../devicetree/bindings/pwm/pwm-stm32-lp.txt | 24 ++++++++++++++++++++++ 1 file changed, 24 insertions(+) create mode 100644 Documentation/devicetree/bindings/pwm/pwm-stm32-lp.txt diff --git a/Documentation/devicetree/bindings/pwm/pwm-stm32-lp.txt b/Documentation/devicetree/bindings/pwm/pwm-stm32-lp.txt new file mode 100644 index 0000000..f8338d1 --- /dev/null +++ b/Documentation/devicetree/bindings/pwm/pwm-stm32-lp.txt @@ -0,0 +1,24 @@ +STMicroelectronics STM32 Low-Power Timer PWM + +STM32 Low-Power Timer provides single channel PWM. + +Must be a sub-node of an STM32 Low-Power Timer device tree node. +See ../mfd/stm32-lptimer.txt for details about the parent node. + +Required parameters: +- compatible: Must be "st,stm32-pwm-lp". + +Optional properties: +- pinctrl-names: Set to "default". +- pinctrl-0: Phandle pointing to pin configuration node for PWM. + +Example: + timer@40002400 { + compatible = "st,stm32-lptimer"; + ... + pwm { + compatible = "st,stm32-pwm-lp"; + pinctrl-names = "default"; + pinctrl-0 = <&lppwm1_pins>; + }; + }; -- cgit v1.1 From 5dae3c90fe76f18815945177498e680e711a4347 Mon Sep 17 00:00:00 2001 From: Fabrice Gasnier Date: Mon, 28 Aug 2017 12:04:10 +0200 Subject: dt-bindings: iio: Add STM32 LPTimer trigger binding Add documentation for STMicroelectronics STM32 Low-Power Timer Trigger binding. Signed-off-by: Fabrice Gasnier Acked-by: Jonathan Cameron Acked-by: Rob Herring Signed-off-by: Lee Jones --- .../bindings/iio/timer/stm32-lptimer-trigger.txt | 23 ++++++++++++++++++++++ 1 file changed, 23 insertions(+) create mode 100644 Documentation/devicetree/bindings/iio/timer/stm32-lptimer-trigger.txt diff --git a/Documentation/devicetree/bindings/iio/timer/stm32-lptimer-trigger.txt b/Documentation/devicetree/bindings/iio/timer/stm32-lptimer-trigger.txt new file mode 100644 index 0000000..85e6806 --- /dev/null +++ b/Documentation/devicetree/bindings/iio/timer/stm32-lptimer-trigger.txt @@ -0,0 +1,23 @@ +STMicroelectronics STM32 Low-Power Timer Trigger + +STM32 Low-Power Timer provides trigger source (LPTIM output) that can be used +by STM32 internal ADC and/or DAC. + +Must be a sub-node of an STM32 Low-Power Timer device tree node. +See ../mfd/stm32-lptimer.txt for details about the parent node. + +Required properties: +- compatible: Must be "st,stm32-lptimer-trigger". +- reg: Identify trigger hardware block. Must be 0, 1 or 2 + respectively for lptimer1, lptimer2 or lptimer3 + trigger output. + +Example: + timer@40002400 { + compatible = "st,stm32-lptimer"; + ... + trigger@0 { + compatible = "st,stm32-lptimer-trigger"; + reg = <0>; + }; + }; -- cgit v1.1 From b01ced2b504b2592af6703533c62cb9d1cdc1c6c Mon Sep 17 00:00:00 2001 From: Fabrice Gasnier Date: Mon, 28 Aug 2017 12:04:11 +0200 Subject: iio: trigger: Add STM32 LPTimer trigger driver Add support for LPTIMx_OUT triggers that can be found on some STM32 devices. These triggers can be used then by ADC or DAC. Typical usage is to configure LPTimer as PWM output (via pwm-stm32-lp) and have synchronised analog conversions with these triggers. Signed-off-by: Fabrice Gasnier Reviewed-by: Jonathan Cameron Signed-off-by: Lee Jones --- drivers/iio/trigger/Kconfig | 11 +++ drivers/iio/trigger/Makefile | 1 + drivers/iio/trigger/stm32-lptimer-trigger.c | 118 ++++++++++++++++++++++++++ include/linux/iio/timer/stm32-lptim-trigger.h | 27 ++++++ 4 files changed, 157 insertions(+) create mode 100644 drivers/iio/trigger/stm32-lptimer-trigger.c create mode 100644 include/linux/iio/timer/stm32-lptim-trigger.h diff --git a/drivers/iio/trigger/Kconfig b/drivers/iio/trigger/Kconfig index e4d4e63..a633d2c 100644 --- a/drivers/iio/trigger/Kconfig +++ b/drivers/iio/trigger/Kconfig @@ -24,6 +24,17 @@ config IIO_INTERRUPT_TRIGGER To compile this driver as a module, choose M here: the module will be called iio-trig-interrupt. +config IIO_STM32_LPTIMER_TRIGGER + tristate "STM32 Low-Power Timer Trigger" + depends on MFD_STM32_LPTIMER || COMPILE_TEST + help + Select this option to enable STM32 Low-Power Timer Trigger. + This can be used as trigger source for STM32 internal ADC + and/or DAC. + + To compile this driver as a module, choose M here: the + module will be called stm32-lptimer-trigger. + config IIO_STM32_TIMER_TRIGGER tristate "STM32 Timer Trigger" depends on (ARCH_STM32 && OF && MFD_STM32_TIMERS) || COMPILE_TEST diff --git a/drivers/iio/trigger/Makefile b/drivers/iio/trigger/Makefile index 5c4ecd3..0a72a2a 100644 --- a/drivers/iio/trigger/Makefile +++ b/drivers/iio/trigger/Makefile @@ -6,6 +6,7 @@ obj-$(CONFIG_IIO_HRTIMER_TRIGGER) += iio-trig-hrtimer.o obj-$(CONFIG_IIO_INTERRUPT_TRIGGER) += iio-trig-interrupt.o +obj-$(CONFIG_IIO_STM32_LPTIMER_TRIGGER) += stm32-lptimer-trigger.o obj-$(CONFIG_IIO_STM32_TIMER_TRIGGER) += stm32-timer-trigger.o obj-$(CONFIG_IIO_SYSFS_TRIGGER) += iio-trig-sysfs.o obj-$(CONFIG_IIO_TIGHTLOOP_TRIGGER) += iio-trig-loop.o diff --git a/drivers/iio/trigger/stm32-lptimer-trigger.c b/drivers/iio/trigger/stm32-lptimer-trigger.c new file mode 100644 index 0000000..241eae6 --- /dev/null +++ b/drivers/iio/trigger/stm32-lptimer-trigger.c @@ -0,0 +1,118 @@ +/* + * STM32 Low-Power Timer Trigger driver + * + * Copyright (C) STMicroelectronics 2017 + * + * Author: Fabrice Gasnier . + * + * License terms: GNU General Public License (GPL), version 2 + * + * Inspired by Benjamin Gaignard's stm32-timer-trigger driver + */ + +#include +#include +#include +#include + +/* List Low-Power Timer triggers */ +static const char * const stm32_lptim_triggers[] = { + LPTIM1_OUT, + LPTIM2_OUT, + LPTIM3_OUT, +}; + +struct stm32_lptim_trigger { + struct device *dev; + const char *trg; +}; + +static int stm32_lptim_validate_device(struct iio_trigger *trig, + struct iio_dev *indio_dev) +{ + if (indio_dev->modes & INDIO_HARDWARE_TRIGGERED) + return 0; + + return -EINVAL; +} + +static const struct iio_trigger_ops stm32_lptim_trigger_ops = { + .owner = THIS_MODULE, + .validate_device = stm32_lptim_validate_device, +}; + +/** + * is_stm32_lptim_trigger + * @trig: trigger to be checked + * + * return true if the trigger is a valid STM32 IIO Low-Power Timer Trigger + * either return false + */ +bool is_stm32_lptim_trigger(struct iio_trigger *trig) +{ + return (trig->ops == &stm32_lptim_trigger_ops); +} +EXPORT_SYMBOL(is_stm32_lptim_trigger); + +static int stm32_lptim_setup_trig(struct stm32_lptim_trigger *priv) +{ + struct iio_trigger *trig; + + trig = devm_iio_trigger_alloc(priv->dev, "%s", priv->trg); + if (!trig) + return -ENOMEM; + + trig->dev.parent = priv->dev->parent; + trig->ops = &stm32_lptim_trigger_ops; + iio_trigger_set_drvdata(trig, priv); + + return devm_iio_trigger_register(priv->dev, trig); +} + +static int stm32_lptim_trigger_probe(struct platform_device *pdev) +{ + struct stm32_lptim_trigger *priv; + u32 index; + int ret; + + priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + if (of_property_read_u32(pdev->dev.of_node, "reg", &index)) + return -EINVAL; + + if (index >= ARRAY_SIZE(stm32_lptim_triggers)) + return -EINVAL; + + priv->dev = &pdev->dev; + priv->trg = stm32_lptim_triggers[index]; + + ret = stm32_lptim_setup_trig(priv); + if (ret) + return ret; + + platform_set_drvdata(pdev, priv); + + return 0; +} + +static const struct of_device_id stm32_lptim_trig_of_match[] = { + { .compatible = "st,stm32-lptimer-trigger", }, + {}, +}; +MODULE_DEVICE_TABLE(of, stm32_lptim_trig_of_match); + +static struct platform_driver stm32_lptim_trigger_driver = { + .probe = stm32_lptim_trigger_probe, + .driver = { + .name = "stm32-lptimer-trigger", + .of_match_table = stm32_lptim_trig_of_match, + }, +}; +module_platform_driver(stm32_lptim_trigger_driver); + +MODULE_AUTHOR("Fabrice Gasnier "); +MODULE_ALIAS("platform:stm32-lptimer-trigger"); +MODULE_DESCRIPTION("STMicroelectronics STM32 LPTIM trigger driver"); +MODULE_LICENSE("GPL v2"); diff --git a/include/linux/iio/timer/stm32-lptim-trigger.h b/include/linux/iio/timer/stm32-lptim-trigger.h new file mode 100644 index 0000000..34d59bf --- /dev/null +++ b/include/linux/iio/timer/stm32-lptim-trigger.h @@ -0,0 +1,27 @@ +/* + * Copyright (C) STMicroelectronics 2017 + * + * Author: Fabrice Gasnier + * + * License terms: GNU General Public License (GPL), version 2 + */ + +#ifndef _STM32_LPTIM_TRIGGER_H_ +#define _STM32_LPTIM_TRIGGER_H_ + +#include +#include + +#define LPTIM1_OUT "lptim1_out" +#define LPTIM2_OUT "lptim2_out" +#define LPTIM3_OUT "lptim3_out" + +#if IS_ENABLED(CONFIG_IIO_STM32_LPTIMER_TRIGGER) +bool is_stm32_lptim_trigger(struct iio_trigger *trig); +#else +static inline bool is_stm32_lptim_trigger(struct iio_trigger *trig) +{ + return false; +} +#endif +#endif -- cgit v1.1 From 717e6922de754c3aa5da5a1e417683cc899efe1c Mon Sep 17 00:00:00 2001 From: Fabrice Gasnier Date: Mon, 28 Aug 2017 12:04:12 +0200 Subject: dt-bindings: iio: Add STM32 LPTimer quadrature encoder and counter Add documentation for STMicroelectronics STM32 Low-Power Timer quadrature encoder and counter binding. Signed-off-by: Fabrice Gasnier Acked-by: Jonathan Cameron Acked-by: Rob Herring Signed-off-by: Lee Jones --- .../bindings/iio/counter/stm32-lptimer-cnt.txt | 27 ++++++++++++++++++++++ 1 file changed, 27 insertions(+) create mode 100644 Documentation/devicetree/bindings/iio/counter/stm32-lptimer-cnt.txt diff --git a/Documentation/devicetree/bindings/iio/counter/stm32-lptimer-cnt.txt b/Documentation/devicetree/bindings/iio/counter/stm32-lptimer-cnt.txt new file mode 100644 index 0000000..a04aa5c --- /dev/null +++ b/Documentation/devicetree/bindings/iio/counter/stm32-lptimer-cnt.txt @@ -0,0 +1,27 @@ +STMicroelectronics STM32 Low-Power Timer quadrature encoder and counter + +STM32 Low-Power Timer provides several counter modes. It can be used as: +- quadrature encoder to detect angular position and direction of rotary + elements, from IN1 and IN2 input signals. +- simple counter from IN1 input signal. + +Must be a sub-node of an STM32 Low-Power Timer device tree node. +See ../mfd/stm32-lptimer.txt for details about the parent node. + +Required properties: +- compatible: Must be "st,stm32-lptimer-counter". +- pinctrl-names: Set to "default". +- pinctrl-0: List of phandles pointing to pin configuration nodes, + to set IN1/IN2 pins in mode of operation for Low-Power + Timer input on external pin. + +Example: + timer@40002400 { + compatible = "st,stm32-lptimer"; + ... + counter { + compatible = "st,stm32-lptimer-counter"; + pinctrl-names = "default"; + pinctrl-0 = <&lptim1_in_pins>; + }; + }; -- cgit v1.1 From d8958824cf0714cc4ddcf320cf12028277ad55c4 Mon Sep 17 00:00:00 2001 From: Fabrice Gasnier Date: Mon, 28 Aug 2017 12:04:13 +0200 Subject: iio: counter: Add support for STM32 LPTimer Add support for STM32 Low-Power Timer, that can be used as counter or quadrature encoder. Signed-off-by: Fabrice Gasnier Reviewed-by: Jonathan Cameron Signed-off-by: Lee Jones --- .../ABI/testing/sysfs-bus-iio-lptimer-stm32 | 57 +++ drivers/iio/counter/Kconfig | 9 + drivers/iio/counter/Makefile | 1 + drivers/iio/counter/stm32-lptimer-cnt.c | 383 +++++++++++++++++++++ 4 files changed, 450 insertions(+) create mode 100644 Documentation/ABI/testing/sysfs-bus-iio-lptimer-stm32 create mode 100644 drivers/iio/counter/stm32-lptimer-cnt.c diff --git a/Documentation/ABI/testing/sysfs-bus-iio-lptimer-stm32 b/Documentation/ABI/testing/sysfs-bus-iio-lptimer-stm32 new file mode 100644 index 0000000..ad2cc63 --- /dev/null +++ b/Documentation/ABI/testing/sysfs-bus-iio-lptimer-stm32 @@ -0,0 +1,57 @@ +What: /sys/bus/iio/devices/iio:deviceX/in_count0_preset +KernelVersion: 4.13 +Contact: fabrice.gasnier@st.com +Description: + Reading returns the current preset value. Writing sets the + preset value. Encoder counts continuously from 0 to preset + value, depending on direction (up/down). + +What: /sys/bus/iio/devices/iio:deviceX/in_count_quadrature_mode_available +KernelVersion: 4.13 +Contact: fabrice.gasnier@st.com +Description: + Reading returns the list possible quadrature modes. + +What: /sys/bus/iio/devices/iio:deviceX/in_count0_quadrature_mode +KernelVersion: 4.13 +Contact: fabrice.gasnier@st.com +Description: + Configure the device counter quadrature modes: + - non-quadrature: + Encoder IN1 input servers as the count input (up + direction). + - quadrature: + Encoder IN1 and IN2 inputs are mixed to get direction + and count. + +What: /sys/bus/iio/devices/iio:deviceX/in_count_polarity_available +KernelVersion: 4.13 +Contact: fabrice.gasnier@st.com +Description: + Reading returns the list possible active edges. + +What: /sys/bus/iio/devices/iio:deviceX/in_count0_polarity +KernelVersion: 4.13 +Contact: fabrice.gasnier@st.com +Description: + Configure the device encoder/counter active edge: + - rising-edge + - falling-edge + - both-edges + + In non-quadrature mode, device counts up on active edge. + In quadrature mode, encoder counting scenarios are as follows: + ---------------------------------------------------------------- + | Active | Level on | IN1 signal | IN2 signal | + | edge | opposite |------------------------------------------ + | | signal | Rising | Falling | Rising | Falling | + ---------------------------------------------------------------- + | Rising | High -> | Down | - | Up | - | + | edge | Low -> | Up | - | Down | - | + ---------------------------------------------------------------- + | Falling | High -> | - | Up | - | Down | + | edge | Low -> | - | Down | - | Up | + ---------------------------------------------------------------- + | Both | High -> | Down | Up | Up | Down | + | edges | Low -> | Up | Down | Down | Up | + ---------------------------------------------------------------- diff --git a/drivers/iio/counter/Kconfig b/drivers/iio/counter/Kconfig index b37e5fc..474e1ac 100644 --- a/drivers/iio/counter/Kconfig +++ b/drivers/iio/counter/Kconfig @@ -21,4 +21,13 @@ config 104_QUAD_8 The base port addresses for the devices may be configured via the base array module parameter. +config STM32_LPTIMER_CNT + tristate "STM32 LP Timer encoder counter driver" + depends on MFD_STM32_LPTIMER || COMPILE_TEST + help + Select this option to enable STM32 Low-Power Timer quadrature encoder + and counter driver. + + To compile this driver as a module, choose M here: the + module will be called stm32-lptimer-cnt. endmenu diff --git a/drivers/iio/counter/Makefile b/drivers/iio/counter/Makefile index 007e884..1b9a896 100644 --- a/drivers/iio/counter/Makefile +++ b/drivers/iio/counter/Makefile @@ -5,3 +5,4 @@ # When adding new entries keep the list in alphabetical order obj-$(CONFIG_104_QUAD_8) += 104-quad-8.o +obj-$(CONFIG_STM32_LPTIMER_CNT) += stm32-lptimer-cnt.o diff --git a/drivers/iio/counter/stm32-lptimer-cnt.c b/drivers/iio/counter/stm32-lptimer-cnt.c new file mode 100644 index 0000000..1c5909b --- /dev/null +++ b/drivers/iio/counter/stm32-lptimer-cnt.c @@ -0,0 +1,383 @@ +/* + * STM32 Low-Power Timer Encoder and Counter driver + * + * Copyright (C) STMicroelectronics 2017 + * + * Author: Fabrice Gasnier + * + * Inspired by 104-quad-8 and stm32-timer-trigger drivers. + * + * License terms: GNU General Public License (GPL), version 2 + */ + +#include +#include +#include +#include +#include + +struct stm32_lptim_cnt { + struct device *dev; + struct regmap *regmap; + struct clk *clk; + u32 preset; + u32 polarity; + u32 quadrature_mode; +}; + +static int stm32_lptim_is_enabled(struct stm32_lptim_cnt *priv) +{ + u32 val; + int ret; + + ret = regmap_read(priv->regmap, STM32_LPTIM_CR, &val); + if (ret) + return ret; + + return FIELD_GET(STM32_LPTIM_ENABLE, val); +} + +static int stm32_lptim_set_enable_state(struct stm32_lptim_cnt *priv, + int enable) +{ + int ret; + u32 val; + + val = FIELD_PREP(STM32_LPTIM_ENABLE, enable); + ret = regmap_write(priv->regmap, STM32_LPTIM_CR, val); + if (ret) + return ret; + + if (!enable) { + clk_disable(priv->clk); + return 0; + } + + /* LP timer must be enabled before writing CMP & ARR */ + ret = regmap_write(priv->regmap, STM32_LPTIM_ARR, priv->preset); + if (ret) + return ret; + + ret = regmap_write(priv->regmap, STM32_LPTIM_CMP, 0); + if (ret) + return ret; + + /* ensure CMP & ARR registers are properly written */ + ret = regmap_read_poll_timeout(priv->regmap, STM32_LPTIM_ISR, val, + (val & STM32_LPTIM_CMPOK_ARROK), + 100, 1000); + if (ret) + return ret; + + ret = regmap_write(priv->regmap, STM32_LPTIM_ICR, + STM32_LPTIM_CMPOKCF_ARROKCF); + if (ret) + return ret; + + ret = clk_enable(priv->clk); + if (ret) { + regmap_write(priv->regmap, STM32_LPTIM_CR, 0); + return ret; + } + + /* Start LP timer in continuous mode */ + return regmap_update_bits(priv->regmap, STM32_LPTIM_CR, + STM32_LPTIM_CNTSTRT, STM32_LPTIM_CNTSTRT); +} + +static int stm32_lptim_setup(struct stm32_lptim_cnt *priv, int enable) +{ + u32 mask = STM32_LPTIM_ENC | STM32_LPTIM_COUNTMODE | + STM32_LPTIM_CKPOL | STM32_LPTIM_PRESC; + u32 val; + + /* Setup LP timer encoder/counter and polarity, without prescaler */ + if (priv->quadrature_mode) + val = enable ? STM32_LPTIM_ENC : 0; + else + val = enable ? STM32_LPTIM_COUNTMODE : 0; + val |= FIELD_PREP(STM32_LPTIM_CKPOL, enable ? priv->polarity : 0); + + return regmap_update_bits(priv->regmap, STM32_LPTIM_CFGR, mask, val); +} + +static int stm32_lptim_write_raw(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, + int val, int val2, long mask) +{ + struct stm32_lptim_cnt *priv = iio_priv(indio_dev); + int ret; + + switch (mask) { + case IIO_CHAN_INFO_ENABLE: + if (val < 0 || val > 1) + return -EINVAL; + + /* Check nobody uses the timer, or already disabled/enabled */ + ret = stm32_lptim_is_enabled(priv); + if ((ret < 0) || (!ret && !val)) + return ret; + if (val && ret) + return -EBUSY; + + ret = stm32_lptim_setup(priv, val); + if (ret) + return ret; + return stm32_lptim_set_enable_state(priv, val); + + default: + return -EINVAL; + } +} + +static int stm32_lptim_read_raw(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, + int *val, int *val2, long mask) +{ + struct stm32_lptim_cnt *priv = iio_priv(indio_dev); + u32 dat; + int ret; + + switch (mask) { + case IIO_CHAN_INFO_RAW: + ret = regmap_read(priv->regmap, STM32_LPTIM_CNT, &dat); + if (ret) + return ret; + *val = dat; + return IIO_VAL_INT; + + case IIO_CHAN_INFO_ENABLE: + ret = stm32_lptim_is_enabled(priv); + if (ret < 0) + return ret; + *val = ret; + return IIO_VAL_INT; + + case IIO_CHAN_INFO_SCALE: + /* Non-quadrature mode: scale = 1 */ + *val = 1; + *val2 = 0; + if (priv->quadrature_mode) { + /* + * Quadrature encoder mode: + * - both edges, quarter cycle, scale is 0.25 + * - either rising/falling edge scale is 0.5 + */ + if (priv->polarity > 1) + *val2 = 2; + else + *val2 = 1; + } + return IIO_VAL_FRACTIONAL_LOG2; + + default: + return -EINVAL; + } +} + +static const struct iio_info stm32_lptim_cnt_iio_info = { + .read_raw = stm32_lptim_read_raw, + .write_raw = stm32_lptim_write_raw, + .driver_module = THIS_MODULE, +}; + +static const char *const stm32_lptim_quadrature_modes[] = { + "non-quadrature", + "quadrature", +}; + +static int stm32_lptim_get_quadrature_mode(struct iio_dev *indio_dev, + const struct iio_chan_spec *chan) +{ + struct stm32_lptim_cnt *priv = iio_priv(indio_dev); + + return priv->quadrature_mode; +} + +static int stm32_lptim_set_quadrature_mode(struct iio_dev *indio_dev, + const struct iio_chan_spec *chan, + unsigned int type) +{ + struct stm32_lptim_cnt *priv = iio_priv(indio_dev); + + if (stm32_lptim_is_enabled(priv)) + return -EBUSY; + + priv->quadrature_mode = type; + + return 0; +} + +static const struct iio_enum stm32_lptim_quadrature_mode_en = { + .items = stm32_lptim_quadrature_modes, + .num_items = ARRAY_SIZE(stm32_lptim_quadrature_modes), + .get = stm32_lptim_get_quadrature_mode, + .set = stm32_lptim_set_quadrature_mode, +}; + +static const char * const stm32_lptim_cnt_polarity[] = { + "rising-edge", "falling-edge", "both-edges", +}; + +static int stm32_lptim_cnt_get_polarity(struct iio_dev *indio_dev, + const struct iio_chan_spec *chan) +{ + struct stm32_lptim_cnt *priv = iio_priv(indio_dev); + + return priv->polarity; +} + +static int stm32_lptim_cnt_set_polarity(struct iio_dev *indio_dev, + const struct iio_chan_spec *chan, + unsigned int type) +{ + struct stm32_lptim_cnt *priv = iio_priv(indio_dev); + + if (stm32_lptim_is_enabled(priv)) + return -EBUSY; + + priv->polarity = type; + + return 0; +} + +static const struct iio_enum stm32_lptim_cnt_polarity_en = { + .items = stm32_lptim_cnt_polarity, + .num_items = ARRAY_SIZE(stm32_lptim_cnt_polarity), + .get = stm32_lptim_cnt_get_polarity, + .set = stm32_lptim_cnt_set_polarity, +}; + +static ssize_t stm32_lptim_cnt_get_preset(struct iio_dev *indio_dev, + uintptr_t private, + const struct iio_chan_spec *chan, + char *buf) +{ + struct stm32_lptim_cnt *priv = iio_priv(indio_dev); + + return snprintf(buf, PAGE_SIZE, "%u\n", priv->preset); +} + +static ssize_t stm32_lptim_cnt_set_preset(struct iio_dev *indio_dev, + uintptr_t private, + const struct iio_chan_spec *chan, + const char *buf, size_t len) +{ + struct stm32_lptim_cnt *priv = iio_priv(indio_dev); + int ret; + + if (stm32_lptim_is_enabled(priv)) + return -EBUSY; + + ret = kstrtouint(buf, 0, &priv->preset); + if (ret) + return ret; + + if (priv->preset > STM32_LPTIM_MAX_ARR) + return -EINVAL; + + return len; +} + +/* LP timer with encoder */ +static const struct iio_chan_spec_ext_info stm32_lptim_enc_ext_info[] = { + { + .name = "preset", + .shared = IIO_SEPARATE, + .read = stm32_lptim_cnt_get_preset, + .write = stm32_lptim_cnt_set_preset, + }, + IIO_ENUM("polarity", IIO_SEPARATE, &stm32_lptim_cnt_polarity_en), + IIO_ENUM_AVAILABLE("polarity", &stm32_lptim_cnt_polarity_en), + IIO_ENUM("quadrature_mode", IIO_SEPARATE, + &stm32_lptim_quadrature_mode_en), + IIO_ENUM_AVAILABLE("quadrature_mode", &stm32_lptim_quadrature_mode_en), + {} +}; + +static const struct iio_chan_spec stm32_lptim_enc_channels = { + .type = IIO_COUNT, + .channel = 0, + .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | + BIT(IIO_CHAN_INFO_ENABLE) | + BIT(IIO_CHAN_INFO_SCALE), + .ext_info = stm32_lptim_enc_ext_info, + .indexed = 1, +}; + +/* LP timer without encoder (counter only) */ +static const struct iio_chan_spec_ext_info stm32_lptim_cnt_ext_info[] = { + { + .name = "preset", + .shared = IIO_SEPARATE, + .read = stm32_lptim_cnt_get_preset, + .write = stm32_lptim_cnt_set_preset, + }, + IIO_ENUM("polarity", IIO_SEPARATE, &stm32_lptim_cnt_polarity_en), + IIO_ENUM_AVAILABLE("polarity", &stm32_lptim_cnt_polarity_en), + {} +}; + +static const struct iio_chan_spec stm32_lptim_cnt_channels = { + .type = IIO_COUNT, + .channel = 0, + .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | + BIT(IIO_CHAN_INFO_ENABLE) | + BIT(IIO_CHAN_INFO_SCALE), + .ext_info = stm32_lptim_cnt_ext_info, + .indexed = 1, +}; + +static int stm32_lptim_cnt_probe(struct platform_device *pdev) +{ + struct stm32_lptimer *ddata = dev_get_drvdata(pdev->dev.parent); + struct stm32_lptim_cnt *priv; + struct iio_dev *indio_dev; + + if (IS_ERR_OR_NULL(ddata)) + return -EINVAL; + + indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*priv)); + if (!indio_dev) + return -ENOMEM; + + priv = iio_priv(indio_dev); + priv->dev = &pdev->dev; + priv->regmap = ddata->regmap; + priv->clk = ddata->clk; + priv->preset = STM32_LPTIM_MAX_ARR; + + indio_dev->name = dev_name(&pdev->dev); + indio_dev->dev.parent = &pdev->dev; + indio_dev->dev.of_node = pdev->dev.of_node; + indio_dev->info = &stm32_lptim_cnt_iio_info; + if (ddata->has_encoder) + indio_dev->channels = &stm32_lptim_enc_channels; + else + indio_dev->channels = &stm32_lptim_cnt_channels; + indio_dev->num_channels = 1; + + platform_set_drvdata(pdev, priv); + + return devm_iio_device_register(&pdev->dev, indio_dev); +} + +static const struct of_device_id stm32_lptim_cnt_of_match[] = { + { .compatible = "st,stm32-lptimer-counter", }, + {}, +}; +MODULE_DEVICE_TABLE(of, stm32_lptim_cnt_of_match); + +static struct platform_driver stm32_lptim_cnt_driver = { + .probe = stm32_lptim_cnt_probe, + .driver = { + .name = "stm32-lptimer-counter", + .of_match_table = stm32_lptim_cnt_of_match, + }, +}; +module_platform_driver(stm32_lptim_cnt_driver); + +MODULE_AUTHOR("Fabrice Gasnier "); +MODULE_ALIAS("platform:stm32-lptimer-counter"); +MODULE_DESCRIPTION("STMicroelectronics STM32 LPTIM counter driver"); +MODULE_LICENSE("GPL v2"); -- cgit v1.1 From f0b638a7f6dba2eb6bf99fc648eab77f7ad5e59f Mon Sep 17 00:00:00 2001 From: Fabrice Gasnier Date: Mon, 28 Aug 2017 12:04:14 +0200 Subject: iio: adc: stm32: add support for lptimer triggers STM32 ADC supports hardware triggers like STM32 Low-Power Timer. For instance, STM32H7 ADC may be triggered by instances 1, 2 or 3. Add hardware triggered mode so Low-Power Timer Trigger driver can validate device. Signed-off-by: Fabrice Gasnier Acked-by: Jonathan Cameron Signed-off-by: Lee Jones --- drivers/iio/adc/stm32-adc.c | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/drivers/iio/adc/stm32-adc.c b/drivers/iio/adc/stm32-adc.c index 5bfcc1f..1147d7e 100644 --- a/drivers/iio/adc/stm32-adc.c +++ b/drivers/iio/adc/stm32-adc.c @@ -25,6 +25,7 @@ #include #include #include +#include #include #include #include @@ -182,6 +183,11 @@ enum stm32_adc_extsel { STM32_EXT13, STM32_EXT14, STM32_EXT15, + STM32_EXT16, + STM32_EXT17, + STM32_EXT18, + STM32_EXT19, + STM32_EXT20, }; /** @@ -480,6 +486,9 @@ static struct stm32_adc_trig_info stm32h7_adc_trigs[] = { { TIM4_TRGO, STM32_EXT12 }, { TIM6_TRGO, STM32_EXT13 }, { TIM3_CH4, STM32_EXT15 }, + { LPTIM1_OUT, STM32_EXT18 }, + { LPTIM2_OUT, STM32_EXT19 }, + { LPTIM3_OUT, STM32_EXT20 }, {}, }; @@ -995,7 +1004,8 @@ static int stm32_adc_get_trig_extsel(struct iio_dev *indio_dev, * Checking both stm32 timer trigger type and trig name * should be safe against arbitrary trigger names. */ - if (is_stm32_timer_trigger(trig) && + if ((is_stm32_timer_trigger(trig) || + is_stm32_lptim_trigger(trig)) && !strcmp(adc->cfg->trigs[i].name, trig->name)) { return adc->cfg->trigs[i].extsel; } @@ -1634,7 +1644,7 @@ static int stm32_adc_probe(struct platform_device *pdev) indio_dev->dev.parent = &pdev->dev; indio_dev->dev.of_node = pdev->dev.of_node; indio_dev->info = &stm32_adc_iio_info; - indio_dev->modes = INDIO_DIRECT_MODE; + indio_dev->modes = INDIO_DIRECT_MODE | INDIO_HARDWARE_TRIGGERED; platform_set_drvdata(pdev, adc); -- cgit v1.1 From ff827cf5698b111b2e5f825cb9ee508115f94e8a Mon Sep 17 00:00:00 2001 From: Dan Carpenter Date: Fri, 30 Jun 2017 11:02:21 +0300 Subject: mfd: twl-core: Improve the documentation Saying it "returns the result" seems tautological. The read function does not return num_bytes on success, it returns zero on success. I noticed this discrepancy because some of the callers were checking for >= 0. Signed-off-by: Dan Carpenter Signed-off-by: Lee Jones --- drivers/mfd/twl-core.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/mfd/twl-core.c b/drivers/mfd/twl-core.c index 2a09dde..d3133a3 100644 --- a/drivers/mfd/twl-core.c +++ b/drivers/mfd/twl-core.c @@ -448,7 +448,7 @@ static struct regmap *twl_get_regmap(u8 mod_no) * @reg: register address (just offset will do) * @num_bytes: number of bytes to transfer * - * Returns the result of operation - 0 is success + * Returns 0 on success or else a negative error code. */ int twl_i2c_write(u8 mod_no, u8 *value, u8 reg, unsigned num_bytes) { @@ -476,7 +476,7 @@ EXPORT_SYMBOL(twl_i2c_write); * @reg: register address (just offset will do) * @num_bytes: number of bytes to transfer * - * Returns result of operation - num_bytes is success else failure. + * Returns 0 on success or else a negative error code. */ int twl_i2c_read(u8 mod_no, u8 *value, u8 reg, unsigned num_bytes) { -- cgit v1.1 From e26ae3660b9ca2d180131670ae5388580dcf19b3 Mon Sep 17 00:00:00 2001 From: Colin Ian King Date: Fri, 30 Jun 2017 10:33:27 +0100 Subject: mfd: rtsx: Make arrays depth and cd_mask static const Don't populate the arrays depath and cd_mask on the stack but make them static const. Makes the object code smaller: text data bss dec hex filename 25413 7216 448 33077 8135 drivers/mfd/rtsx_pcr.o text data bss dec hex filename 25151 7360 448 32959 80bf drivers/mfd/rtsx_pcr.o Signed-off-by: Colin Ian King Signed-off-by: Lee Jones --- drivers/mfd/rtsx_pcr.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/mfd/rtsx_pcr.c b/drivers/mfd/rtsx_pcr.c index a0ac89d..3cf69e5 100644 --- a/drivers/mfd/rtsx_pcr.c +++ b/drivers/mfd/rtsx_pcr.c @@ -644,7 +644,7 @@ int rtsx_pci_switch_clock(struct rtsx_pcr *pcr, unsigned int card_clock, { int err, clk; u8 n, clk_divider, mcu_cnt, div; - u8 depth[] = { + static const u8 depth[] = { [RTSX_SSC_DEPTH_4M] = SSC_DEPTH_4M, [RTSX_SSC_DEPTH_2M] = SSC_DEPTH_2M, [RTSX_SSC_DEPTH_1M] = SSC_DEPTH_1M, @@ -768,7 +768,7 @@ EXPORT_SYMBOL_GPL(rtsx_pci_card_power_off); int rtsx_pci_card_exclusive_check(struct rtsx_pcr *pcr, int card) { - unsigned int cd_mask[] = { + static const unsigned int cd_mask[] = { [RTSX_SD_CARD] = SD_EXIST, [RTSX_MS_CARD] = MS_EXIST }; -- cgit v1.1 From 45f80a9f78f1bcf87c09ae120a68011efe35128a Mon Sep 17 00:00:00 2001 From: Sebastian Reichel Date: Fri, 30 Jun 2017 16:35:03 +0200 Subject: mfd: da9052: Fix manual ADC read after timed out read It is possible that under heavy system load, the counter in the completion struct, used for waiting for end of AD conversion, gets incremented twice. To make sure the driver recovers from this situation, the completion struct should be reinitialized. Signed-off-by: Sebastian Reichel Signed-off-by: Lee Jones --- drivers/mfd/da9052-core.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/mfd/da9052-core.c b/drivers/mfd/da9052-core.c index a23a3a1..433add4 100644 --- a/drivers/mfd/da9052-core.c +++ b/drivers/mfd/da9052-core.c @@ -387,6 +387,8 @@ int da9052_adc_manual_read(struct da9052 *da9052, unsigned char channel) mutex_lock(&da9052->auxadc_lock); + reinit_completion(&da9052->done); + /* Channel gets activated on enabling the Conversion bit */ mux_sel = chan_mux[channel] | DA9052_ADC_MAN_MAN_CONV; -- cgit v1.1 From 0953075112d7626474b0bb88690f5f1ab93ec803 Mon Sep 17 00:00:00 2001 From: Julia Lawall Date: Thu, 4 May 2017 22:10:54 +0200 Subject: mfd: max8925-i2c: Drop unnecessary static Drop static on a local variable, when the variable is initialized before any use, on every possible execution path through the function. The static has no benefit, and dropping it reduces the code size. The semantic patch that fixes this problem is as follows: (http://coccinelle.lip6.fr/) // @bad exists@ position p; identifier x; type T; @@ static T x@p; ... x = <+...x...+> @@ identifier x; expression e; type T; position p != bad.p; @@ -static T x@p; ... when != x when strict ?x = e; // The change in code size is indicates by the following output from the size command. before: text data bss dec hex filename 2579 240 16 2835 b13 drivers/mfd/max8925-i2c.o after: text data bss dec hex filename 2531 240 8 2779 adb drivers/mfd/max8925-i2c.o Signed-off-by: Julia Lawall Acked-by: Kees Cook Signed-off-by: Lee Jones --- drivers/mfd/max8925-i2c.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/mfd/max8925-i2c.c b/drivers/mfd/max8925-i2c.c index 5c80aea..1006323 100644 --- a/drivers/mfd/max8925-i2c.c +++ b/drivers/mfd/max8925-i2c.c @@ -151,7 +151,7 @@ static int max8925_probe(struct i2c_client *client, const struct i2c_device_id *id) { struct max8925_platform_data *pdata = dev_get_platdata(&client->dev); - static struct max8925_chip *chip; + struct max8925_chip *chip; struct device_node *node = client->dev.of_node; if (node && !pdata) { -- cgit v1.1 From 2042f3c29f2f11129434de8a610878e8a15b4174 Mon Sep 17 00:00:00 2001 From: Christophe JAILLET Date: Wed, 5 Jul 2017 07:50:54 +0200 Subject: mfd: max8998: Fix potential NULL pointer dereference if 'max8998_i2c_parse_dt_pdata() fails (when out of memory), a NULL pointer dereference will occur in the error handling code. Return directly instead. Fixes: ee999fb3f17f("mfd: max8998: Add support for Device Tree") Signed-off-by: Christophe JAILLET Signed-off-by: Lee Jones --- drivers/mfd/max8998.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/mfd/max8998.c b/drivers/mfd/max8998.c index 4c33b80..b1d3f70 100644 --- a/drivers/mfd/max8998.c +++ b/drivers/mfd/max8998.c @@ -192,10 +192,8 @@ static int max8998_i2c_probe(struct i2c_client *i2c, if (IS_ENABLED(CONFIG_OF) && i2c->dev.of_node) { pdata = max8998_i2c_parse_dt_pdata(&i2c->dev); - if (IS_ERR(pdata)) { - ret = PTR_ERR(pdata); - goto err; - } + if (IS_ERR(pdata)) + return PTR_ERR(pdata); } i2c_set_clientdata(i2c, max8998); -- cgit v1.1 From 5368b06dba4b911654221f3aad92b3298392a59a Mon Sep 17 00:00:00 2001 From: Sebastian Reichel Date: Mon, 3 Jul 2017 10:39:59 +0200 Subject: dt-bindings: mfd: da9052: Support TSI as ADC DA9052 allows using the touchscreen input pins as general purpose analogue input pin by wiring analogue inputs to X+, X-, Y+ and Y- and providing a reference voltage at TSIREF pin. Signed-off-by: Sebastian Reichel Acked-by: Rob Herring Signed-off-by: Lee Jones --- Documentation/devicetree/bindings/mfd/da9052-i2c.txt | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/Documentation/devicetree/bindings/mfd/da9052-i2c.txt b/Documentation/devicetree/bindings/mfd/da9052-i2c.txt index 9554292..57fa74e 100644 --- a/Documentation/devicetree/bindings/mfd/da9052-i2c.txt +++ b/Documentation/devicetree/bindings/mfd/da9052-i2c.txt @@ -4,6 +4,14 @@ Required properties: - compatible : Should be "dlg,da9052", "dlg,da9053-aa", "dlg,da9053-ab", or "dlg,da9053-bb" +Optional properties: +- dlg,tsi-as-adc : Boolean, if set the X+, X-, Y+, Y- touchscreen + input lines are used as general purpose analogue + input. +- tsiref-supply: Phandle to the regulator, which provides the reference + voltage for the TSIREF pin. Must be provided when the + touchscreen pins are used for ADC purposes. + Sub-nodes: - regulators : Contain the regulator nodes. The DA9052/53 regulators are bound using their names as listed below: -- cgit v1.1 From 52557dc624df7de5808c5c26476f3a8863bb0128 Mon Sep 17 00:00:00 2001 From: Arvind Yadav Date: Mon, 10 Jul 2017 11:07:22 +0530 Subject: mfd: ab8500-core: Constify attribute_group structures attribute_groups are not supposed to change at runtime. All functions working with attribute_groups provided by work with const attribute_group. So mark the non-const structs as const. File size before: text data bss dec hex filename 16298 1009 184 17491 4453 drivers/mfd/ab8500-core.o File size After adding 'const': text data bss dec hex filename 16490 817 184 17491 4453 drivers/mfd/ab8500-core.o Signed-off-by: Arvind Yadav Signed-off-by: Lee Jones --- drivers/mfd/ab8500-core.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/mfd/ab8500-core.c b/drivers/mfd/ab8500-core.c index 8511c06..30d09d1 100644 --- a/drivers/mfd/ab8500-core.c +++ b/drivers/mfd/ab8500-core.c @@ -1059,15 +1059,15 @@ static struct attribute *ab9540_sysfs_entries[] = { NULL, }; -static struct attribute_group ab8500_attr_group = { +static const struct attribute_group ab8500_attr_group = { .attrs = ab8500_sysfs_entries, }; -static struct attribute_group ab8505_attr_group = { +static const struct attribute_group ab8505_attr_group = { .attrs = ab8505_sysfs_entries, }; -static struct attribute_group ab9540_attr_group = { +static const struct attribute_group ab9540_attr_group = { .attrs = ab9540_sysfs_entries, }; -- cgit v1.1 From 757bce527da57ad9fbb91d97455e17c5716375d4 Mon Sep 17 00:00:00 2001 From: Ludovic Desroches Date: Tue, 11 Jul 2017 09:40:13 +0200 Subject: mfd: syscon: Update Atmel SMC binding doc MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit A new compatible string is introduced for SMC on sama5d2 to manage a different layout of the registers. Signed-off-by: Ludovic Desroches │Acked-by: Rob Herring Signed-off-by: Lee Jones --- Documentation/devicetree/bindings/mfd/atmel-smc.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/mfd/atmel-smc.txt b/Documentation/devicetree/bindings/mfd/atmel-smc.txt index 26eeed3..1103ce2 100644 --- a/Documentation/devicetree/bindings/mfd/atmel-smc.txt +++ b/Documentation/devicetree/bindings/mfd/atmel-smc.txt @@ -8,6 +8,7 @@ Required properties: - compatible: Should be one of the following "atmel,at91sam9260-smc", "syscon" "atmel,sama5d3-smc", "syscon" + "atmel,sama5d2-smc", "syscon" - reg: Contains offset/length value of the SMC memory region. -- cgit v1.1 From 5c8f124893c4a691bdae5e9258cb0bca44653f08 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Mon, 17 Jul 2017 11:28:55 +0200 Subject: mfd: Kconfig: Add missing Kconfig dependency for TPS65086 MTF_CORE should be enabled when driver is enabled. Without this patch you can configure: CONFIG_MFD_CORE is not set CONFIG_MFD_TPS65086=y ... which ends up with compilation error: drivers/mfd/tps65086.o: In function `tps65086_probe': drivers/mfd/tps65086.c:110: undefined reference to `mfd_add_devices' drivers/mfd/tps65086.c:110:(.text+0x128): relocation truncated to fit: \ R_AARCH64_CALL26 against undefined symbol `mfd_add_devices' Signed-off-by: Michal Simek Signed-off-by: Lee Jones --- drivers/mfd/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig index 7a01e70a..42fb90a 100644 --- a/drivers/mfd/Kconfig +++ b/drivers/mfd/Kconfig @@ -1294,6 +1294,7 @@ config TPS6507X config MFD_TPS65086 tristate "TI TPS65086 Power Management Integrated Chips (PMICs)" + select MFD_CORE select REGMAP select REGMAP_IRQ select REGMAP_I2C -- cgit v1.1 From 876368c3caa59b174d9a6ac28b7e88a9a9544eac Mon Sep 17 00:00:00 2001 From: Guodong Xu Date: Thu, 20 Jul 2017 15:32:40 +0800 Subject: mfd: hi6421-pmic: Change license text to shorter form Change license text to a shorter form of GPLv2. Signed-off-by: Guodong Xu Acked-by: Arnd Bergmann Signed-off-by: Lee Jones --- drivers/mfd/hi6421-pmic-core.c | 13 ++----------- 1 file changed, 2 insertions(+), 11 deletions(-) diff --git a/drivers/mfd/hi6421-pmic-core.c b/drivers/mfd/hi6421-pmic-core.c index 3fd703f..ad9e3d8 100644 --- a/drivers/mfd/hi6421-pmic-core.c +++ b/drivers/mfd/hi6421-pmic-core.c @@ -9,17 +9,8 @@ * Author: Guodong Xu * * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. */ #include -- cgit v1.1 From 568e5476cf2b8dfdcf123a67b88fb724beb5487c Mon Sep 17 00:00:00 2001 From: Guodong Xu Date: Thu, 20 Jul 2017 15:32:41 +0800 Subject: mfd: hi6421-pmic: Update dev_err messages Update dev_err messages to make them more readable. Signed-off-by: Guodong Xu Acked-by: Arnd Bergmann Signed-off-by: Lee Jones --- drivers/mfd/hi6421-pmic-core.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/mfd/hi6421-pmic-core.c b/drivers/mfd/hi6421-pmic-core.c index ad9e3d8..b1139d4 100644 --- a/drivers/mfd/hi6421-pmic-core.c +++ b/drivers/mfd/hi6421-pmic-core.c @@ -52,8 +52,8 @@ static int hi6421_pmic_probe(struct platform_device *pdev) pmic->regmap = devm_regmap_init_mmio_clk(&pdev->dev, NULL, base, &hi6421_regmap_config); if (IS_ERR(pmic->regmap)) { - dev_err(&pdev->dev, - "regmap init failed: %ld\n", PTR_ERR(pmic->regmap)); + dev_err(&pdev->dev, "Failed to initialise Regmap: %ld\n", + PTR_ERR(pmic->regmap)); return PTR_ERR(pmic->regmap); } @@ -70,7 +70,7 @@ static int hi6421_pmic_probe(struct platform_device *pdev) ret = devm_mfd_add_devices(&pdev->dev, 0, hi6421_devs, ARRAY_SIZE(hi6421_devs), NULL, 0, NULL); if (ret) { - dev_err(&pdev->dev, "add mfd devices failed: %d\n", ret); + dev_err(&pdev->dev, "Failed to add child devices: %d\n", ret); return ret; } -- cgit v1.1 From ec58871fb9c50429d6b5570066a7166da8faf086 Mon Sep 17 00:00:00 2001 From: Guodong Xu Date: Thu, 20 Jul 2017 15:32:42 +0800 Subject: mfd: hi6421-pmic: Add support for HiSilicon Hi6421v530 Add support for HiSilicon Hi6421v530 PMIC. Hi6421v530 communicates with main SoC via memory-mapped I/O. Hi6421v530 and Hi6421 are PMIC chips from the same vendor, HiSilicon, but at different revisions. They share the same memory-mapped I/O design. They differ in integrated devices, such as regulator details, LDO voltage points. Signed-off-by: Guodong Xu Signed-off-by: Wang Xiaoyin Acked-by: Arnd Bergmann Signed-off-by: Lee Jones --- drivers/mfd/hi6421-pmic-core.c | 70 ++++++++++++++++++++++++++++++----------- include/linux/mfd/hi6421-pmic.h | 5 +++ 2 files changed, 57 insertions(+), 18 deletions(-) diff --git a/drivers/mfd/hi6421-pmic-core.c b/drivers/mfd/hi6421-pmic-core.c index b1139d4..6fb7ba2 100644 --- a/drivers/mfd/hi6421-pmic-core.c +++ b/drivers/mfd/hi6421-pmic-core.c @@ -1,9 +1,9 @@ /* - * Device driver for Hi6421 IC + * Device driver for Hi6421 PMIC * * Copyright (c) <2011-2014> HiSilicon Technologies Co., Ltd. * http://www.hisilicon.com - * Copyright (c) <2013-2014> Linaro Ltd. + * Copyright (c) <2013-2017> Linaro Ltd. * http://www.linaro.org * * Author: Guodong Xu @@ -16,16 +16,20 @@ #include #include #include +#include #include -#include +#include #include #include -#include static const struct mfd_cell hi6421_devs[] = { { .name = "hi6421-regulator", }, }; +static const struct mfd_cell hi6421v530_devs[] = { + { .name = "hi6421v530-regulator", }, +}; + static const struct regmap_config hi6421_regmap_config = { .reg_bits = 32, .reg_stride = 4, @@ -33,12 +37,33 @@ static const struct regmap_config hi6421_regmap_config = { .max_register = HI6421_REG_TO_BUS_ADDR(HI6421_REG_MAX), }; +static const struct of_device_id of_hi6421_pmic_match[] = { + { + .compatible = "hisilicon,hi6421-pmic", + .data = (void *)HI6421 + }, + { + .compatible = "hisilicon,hi6421v530-pmic", + .data = (void *)HI6421_V530 + }, + { }, +}; +MODULE_DEVICE_TABLE(of, of_hi6421_pmic_match); + static int hi6421_pmic_probe(struct platform_device *pdev) { struct hi6421_pmic *pmic; struct resource *res; + const struct of_device_id *id; + const struct mfd_cell *subdevs; + enum hi6421_type type; void __iomem *base; - int ret; + int n_subdevs, ret; + + id = of_match_device(of_hi6421_pmic_match, &pdev->dev); + if (!id) + return -EINVAL; + type = (enum hi6421_type)id->data; pmic = devm_kzalloc(&pdev->dev, sizeof(*pmic), GFP_KERNEL); if (!pmic) @@ -57,18 +82,33 @@ static int hi6421_pmic_probe(struct platform_device *pdev) return PTR_ERR(pmic->regmap); } - /* set over-current protection debounce 8ms */ - regmap_update_bits(pmic->regmap, HI6421_OCP_DEB_CTRL_REG, + platform_set_drvdata(pdev, pmic); + + switch (type) { + case HI6421: + /* set over-current protection debounce 8ms */ + regmap_update_bits(pmic->regmap, HI6421_OCP_DEB_CTRL_REG, (HI6421_OCP_DEB_SEL_MASK | HI6421_OCP_EN_DEBOUNCE_MASK | HI6421_OCP_AUTO_STOP_MASK), (HI6421_OCP_DEB_SEL_8MS | HI6421_OCP_EN_DEBOUNCE_ENABLE)); - platform_set_drvdata(pdev, pmic); + subdevs = hi6421_devs; + n_subdevs = ARRAY_SIZE(hi6421_devs); + break; + case HI6421_V530: + subdevs = hi6421v530_devs; + n_subdevs = ARRAY_SIZE(hi6421v530_devs); + break; + default: + dev_err(&pdev->dev, "Unknown device type %d\n", + (unsigned int)type); + return -EINVAL; + } - ret = devm_mfd_add_devices(&pdev->dev, 0, hi6421_devs, - ARRAY_SIZE(hi6421_devs), NULL, 0, NULL); + ret = devm_mfd_add_devices(&pdev->dev, PLATFORM_DEVID_NONE, + subdevs, n_subdevs, NULL, 0, NULL); if (ret) { dev_err(&pdev->dev, "Failed to add child devices: %d\n", ret); return ret; @@ -77,16 +117,10 @@ static int hi6421_pmic_probe(struct platform_device *pdev) return 0; } -static const struct of_device_id of_hi6421_pmic_match_tbl[] = { - { .compatible = "hisilicon,hi6421-pmic", }, - { }, -}; -MODULE_DEVICE_TABLE(of, of_hi6421_pmic_match_tbl); - static struct platform_driver hi6421_pmic_driver = { .driver = { - .name = "hi6421_pmic", - .of_match_table = of_hi6421_pmic_match_tbl, + .name = "hi6421_pmic", + .of_match_table = of_hi6421_pmic_match, }, .probe = hi6421_pmic_probe, }; diff --git a/include/linux/mfd/hi6421-pmic.h b/include/linux/mfd/hi6421-pmic.h index 587273e..2580c08 100644 --- a/include/linux/mfd/hi6421-pmic.h +++ b/include/linux/mfd/hi6421-pmic.h @@ -38,4 +38,9 @@ struct hi6421_pmic { struct regmap *regmap; }; +enum hi6421_type { + HI6421 = 0, + HI6421_V530, +}; + #endif /* __HI6421_PMIC_H */ -- cgit v1.1 From d3ea212720948acff862b4c842d5b464ad338841 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 17 Jul 2017 22:45:12 +0200 Subject: mfd: Add ROHM BD9571MWV-M MFD PMIC driver Add the MFD part of the ROHM BD9571MWV-M PMIC driver and MAINTAINERS entry. The MFD part only specifies the regmap bits for the PMIC and binds the subdevs together. Signed-off-by: Marek Vasut Signed-off-by: Lee Jones --- MAINTAINERS | 11 ++ drivers/mfd/Kconfig | 14 +++ drivers/mfd/Makefile | 1 + drivers/mfd/bd9571mwv.c | 230 ++++++++++++++++++++++++++++++++++++++++++ include/linux/mfd/bd9571mwv.h | 115 +++++++++++++++++++++ 5 files changed, 371 insertions(+) create mode 100644 drivers/mfd/bd9571mwv.c create mode 100644 include/linux/mfd/bd9571mwv.h diff --git a/MAINTAINERS b/MAINTAINERS index 1c3feff..0876e3e 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -11280,6 +11280,17 @@ L: linux-serial@vger.kernel.org S: Odd Fixes F: drivers/tty/serial/rp2.* +ROHM MULTIFUNCTION BD9571MWV-M PMIC DEVICE DRIVERS +M: Marek Vasut +L: linux-kernel@vger.kernel.org +L: linux-renesas-soc@vger.kernel.org +S: Supported +F: drivers/mfd/bd9571mwv.c +F: drivers/regulator/bd9571mwv-regulator.c +F: drivers/gpio/gpio-bd9571mwv.c +F: include/linux/mfd/bd9571mwv.h +F: Documentation/devicetree/bindings/mfd/bd9571mwv.txt + ROSE NETWORK LAYER M: Ralf Baechle L: linux-hams@vger.kernel.org diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig index 42fb90a..79e4ec6 100644 --- a/drivers/mfd/Kconfig +++ b/drivers/mfd/Kconfig @@ -133,6 +133,20 @@ config MFD_BCM590XX help Support for the BCM590xx PMUs from Broadcom +config MFD_BD9571MWV + tristate "ROHM BD9571MWV PMIC" + select MFD_CORE + select REGMAP_I2C + select REGMAP_IRQ + depends on I2C + help + Support for the ROHM BD9571MWV PMIC, which contains single + voltage regulator, voltage sampling units, GPIO block and + watchdog block. + + This driver can also be built as a module. If so, the module + will be called bd9571mwv. + config MFD_AC100 tristate "X-Powers AC100" select MFD_CORE diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile index b80b1a3..21e19a5 100644 --- a/drivers/mfd/Makefile +++ b/drivers/mfd/Makefile @@ -10,6 +10,7 @@ obj-$(CONFIG_MFD_ACT8945A) += act8945a.o obj-$(CONFIG_MFD_SM501) += sm501.o obj-$(CONFIG_MFD_ASIC3) += asic3.o tmio_core.o obj-$(CONFIG_MFD_BCM590XX) += bcm590xx.o +obj-$(CONFIG_MFD_BD9571MWV) += bd9571mwv.o cros_ec_core-objs := cros_ec.o cros_ec_core-$(CONFIG_ACPI) += cros_ec_acpi_gpe.o obj-$(CONFIG_MFD_CROS_EC) += cros_ec_core.o diff --git a/drivers/mfd/bd9571mwv.c b/drivers/mfd/bd9571mwv.c new file mode 100644 index 0000000..64e088d --- /dev/null +++ b/drivers/mfd/bd9571mwv.c @@ -0,0 +1,230 @@ +/* + * ROHM BD9571MWV-M MFD driver + * + * Copyright (C) 2017 Marek Vasut + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether expressed or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License version 2 for more details. + * + * Based on the TPS65086 driver + */ + +#include +#include +#include +#include + +#include + +static const struct mfd_cell bd9571mwv_cells[] = { + { .name = "bd9571mwv-regulator", }, + { .name = "bd9571mwv-gpio", }, +}; + +static const struct regmap_range bd9571mwv_readable_yes_ranges[] = { + regmap_reg_range(BD9571MWV_VENDOR_CODE, BD9571MWV_PRODUCT_REVISION), + regmap_reg_range(BD9571MWV_AVS_SET_MONI, BD9571MWV_AVS_DVFS_VID(3)), + regmap_reg_range(BD9571MWV_VD18_VID, BD9571MWV_VD33_VID), + regmap_reg_range(BD9571MWV_DVFS_VINIT, BD9571MWV_DVFS_VINIT), + regmap_reg_range(BD9571MWV_DVFS_SETVMAX, BD9571MWV_DVFS_MONIVDAC), + regmap_reg_range(BD9571MWV_GPIO_IN, BD9571MWV_GPIO_IN), + regmap_reg_range(BD9571MWV_GPIO_INT, BD9571MWV_GPIO_INTMASK), + regmap_reg_range(BD9571MWV_INT_INTREQ, BD9571MWV_INT_INTMASK), +}; + +static const struct regmap_access_table bd9571mwv_readable_table = { + .yes_ranges = bd9571mwv_readable_yes_ranges, + .n_yes_ranges = ARRAY_SIZE(bd9571mwv_readable_yes_ranges), +}; + +static const struct regmap_range bd9571mwv_writable_yes_ranges[] = { + regmap_reg_range(BD9571MWV_AVS_VD09_VID(0), BD9571MWV_AVS_VD09_VID(3)), + regmap_reg_range(BD9571MWV_DVFS_SETVID, BD9571MWV_DVFS_SETVID), + regmap_reg_range(BD9571MWV_GPIO_DIR, BD9571MWV_GPIO_OUT), + regmap_reg_range(BD9571MWV_GPIO_INT_SET, BD9571MWV_GPIO_INTMASK), + regmap_reg_range(BD9571MWV_INT_INTREQ, BD9571MWV_INT_INTMASK), +}; + +static const struct regmap_access_table bd9571mwv_writable_table = { + .yes_ranges = bd9571mwv_writable_yes_ranges, + .n_yes_ranges = ARRAY_SIZE(bd9571mwv_writable_yes_ranges), +}; + +static const struct regmap_range bd9571mwv_volatile_yes_ranges[] = { + regmap_reg_range(BD9571MWV_GPIO_IN, BD9571MWV_GPIO_IN), + regmap_reg_range(BD9571MWV_GPIO_INT, BD9571MWV_GPIO_INT), + regmap_reg_range(BD9571MWV_INT_INTREQ, BD9571MWV_INT_INTREQ), +}; + +static const struct regmap_access_table bd9571mwv_volatile_table = { + .yes_ranges = bd9571mwv_volatile_yes_ranges, + .n_yes_ranges = ARRAY_SIZE(bd9571mwv_volatile_yes_ranges), +}; + +static const struct regmap_config bd9571mwv_regmap_config = { + .reg_bits = 8, + .val_bits = 8, + .cache_type = REGCACHE_RBTREE, + .rd_table = &bd9571mwv_readable_table, + .wr_table = &bd9571mwv_writable_table, + .volatile_table = &bd9571mwv_volatile_table, + .max_register = 0xff, +}; + +static const struct regmap_irq bd9571mwv_irqs[] = { + REGMAP_IRQ_REG(BD9571MWV_IRQ_MD1, 0, + BD9571MWV_INT_INTREQ_MD1_INT), + REGMAP_IRQ_REG(BD9571MWV_IRQ_MD2_E1, 0, + BD9571MWV_INT_INTREQ_MD2_E1_INT), + REGMAP_IRQ_REG(BD9571MWV_IRQ_MD2_E2, 0, + BD9571MWV_INT_INTREQ_MD2_E2_INT), + REGMAP_IRQ_REG(BD9571MWV_IRQ_PROT_ERR, 0, + BD9571MWV_INT_INTREQ_PROT_ERR_INT), + REGMAP_IRQ_REG(BD9571MWV_IRQ_GP, 0, + BD9571MWV_INT_INTREQ_GP_INT), + REGMAP_IRQ_REG(BD9571MWV_IRQ_128H_OF, 0, + BD9571MWV_INT_INTREQ_128H_OF_INT), + REGMAP_IRQ_REG(BD9571MWV_IRQ_WDT_OF, 0, + BD9571MWV_INT_INTREQ_WDT_OF_INT), + REGMAP_IRQ_REG(BD9571MWV_IRQ_BKUP_TRG, 0, + BD9571MWV_INT_INTREQ_BKUP_TRG_INT), +}; + +static struct regmap_irq_chip bd9571mwv_irq_chip = { + .name = "bd9571mwv", + .status_base = BD9571MWV_INT_INTREQ, + .mask_base = BD9571MWV_INT_INTMASK, + .ack_base = BD9571MWV_INT_INTREQ, + .init_ack_masked = true, + .num_regs = 1, + .irqs = bd9571mwv_irqs, + .num_irqs = ARRAY_SIZE(bd9571mwv_irqs), +}; + +static int bd9571mwv_identify(struct bd9571mwv *bd) +{ + struct device *dev = bd->dev; + unsigned int value; + int ret; + + ret = regmap_read(bd->regmap, BD9571MWV_VENDOR_CODE, &value); + if (ret) { + dev_err(dev, "Failed to read vendor code register (ret=%i)\n", + ret); + return ret; + } + + if (value != BD9571MWV_VENDOR_CODE_VAL) { + dev_err(dev, "Invalid vendor code ID %02x (expected %02x)\n", + value, BD9571MWV_VENDOR_CODE_VAL); + return -EINVAL; + } + + ret = regmap_read(bd->regmap, BD9571MWV_PRODUCT_CODE, &value); + if (ret) { + dev_err(dev, "Failed to read product code register (ret=%i)\n", + ret); + return ret; + } + + if (value != BD9571MWV_PRODUCT_CODE_VAL) { + dev_err(dev, "Invalid product code ID %02x (expected %02x)\n", + value, BD9571MWV_PRODUCT_CODE_VAL); + return -EINVAL; + } + + ret = regmap_read(bd->regmap, BD9571MWV_PRODUCT_REVISION, &value); + if (ret) { + dev_err(dev, "Failed to read revision register (ret=%i)\n", + ret); + return ret; + } + + dev_info(dev, "Device: BD9571MWV rev. %d\n", value & 0xff); + + return 0; +} + +static int bd9571mwv_probe(struct i2c_client *client, + const struct i2c_device_id *ids) +{ + struct bd9571mwv *bd; + int ret; + + bd = devm_kzalloc(&client->dev, sizeof(*bd), GFP_KERNEL); + if (!bd) + return -ENOMEM; + + i2c_set_clientdata(client, bd); + bd->dev = &client->dev; + bd->irq = client->irq; + + bd->regmap = devm_regmap_init_i2c(client, &bd9571mwv_regmap_config); + if (IS_ERR(bd->regmap)) { + dev_err(bd->dev, "Failed to initialize register map\n"); + return PTR_ERR(bd->regmap); + } + + ret = bd9571mwv_identify(bd); + if (ret) + return ret; + + ret = regmap_add_irq_chip(bd->regmap, bd->irq, IRQF_ONESHOT, 0, + &bd9571mwv_irq_chip, &bd->irq_data); + if (ret) { + dev_err(bd->dev, "Failed to register IRQ chip\n"); + return ret; + } + + ret = mfd_add_devices(bd->dev, PLATFORM_DEVID_AUTO, bd9571mwv_cells, + ARRAY_SIZE(bd9571mwv_cells), NULL, 0, + regmap_irq_get_domain(bd->irq_data)); + if (ret) { + regmap_del_irq_chip(bd->irq, bd->irq_data); + return ret; + } + + return 0; +} + +static int bd9571mwv_remove(struct i2c_client *client) +{ + struct bd9571mwv *bd = i2c_get_clientdata(client); + + regmap_del_irq_chip(bd->irq, bd->irq_data); + + return 0; +} + +static const struct of_device_id bd9571mwv_of_match_table[] = { + { .compatible = "rohm,bd9571mwv", }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, bd9571mwv_of_match_table); + +static const struct i2c_device_id bd9571mwv_id_table[] = { + { "bd9571mwv", 0 }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(i2c, bd9571mwv_id_table); + +static struct i2c_driver bd9571mwv_driver = { + .driver = { + .name = "bd9571mwv", + .of_match_table = bd9571mwv_of_match_table, + }, + .probe = bd9571mwv_probe, + .remove = bd9571mwv_remove, + .id_table = bd9571mwv_id_table, +}; +module_i2c_driver(bd9571mwv_driver); + +MODULE_AUTHOR("Marek Vasut "); +MODULE_DESCRIPTION("BD9571MWV PMIC Driver"); +MODULE_LICENSE("GPL v2"); diff --git a/include/linux/mfd/bd9571mwv.h b/include/linux/mfd/bd9571mwv.h new file mode 100644 index 0000000..f0708ba --- /dev/null +++ b/include/linux/mfd/bd9571mwv.h @@ -0,0 +1,115 @@ +/* + * ROHM BD9571MWV-M driver + * + * Copyright (C) 2017 Marek Vasut + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether expressed or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License version 2 for more details. + * + * Based on the TPS65086 driver + */ + +#ifndef __LINUX_MFD_BD9571MWV_H +#define __LINUX_MFD_BD9571MWV_H + +#include +#include + +/* List of registers for BD9571MWV */ +#define BD9571MWV_VENDOR_CODE 0x00 +#define BD9571MWV_VENDOR_CODE_VAL 0xdb +#define BD9571MWV_PRODUCT_CODE 0x01 +#define BD9571MWV_PRODUCT_CODE_VAL 0x60 +#define BD9571MWV_PRODUCT_REVISION 0x02 + +#define BD9571MWV_I2C_FUSA_MODE 0x10 +#define BD9571MWV_I2C_MD2_E1_BIT_1 0x11 +#define BD9571MWV_I2C_MD2_E1_BIT_2 0x12 + +#define BD9571MWV_BKUP_MODE_CNT 0x20 +#define BD9571MWV_BKUP_MODE_STATUS 0x21 +#define BD9571MWV_BKUP_RECOVERY_CNT 0x22 +#define BD9571MWV_BKUP_CTRL_TIM_CNT 0x23 +#define BD9571MWV_WAITBKUP_WDT_CNT 0x24 +#define BD9571MWV_128H_TIM_CNT 0x26 +#define BD9571MWV_QLLM_CNT 0x27 + +#define BD9571MWV_AVS_SET_MONI 0x31 +#define BD9571MWV_AVS_SET_MONI_MASK 0x3 +#define BD9571MWV_AVS_VD09_VID(n) (0x32 + (n)) +#define BD9571MWV_AVS_DVFS_VID(n) (0x36 + (n)) + +#define BD9571MWV_VD18_VID 0x42 +#define BD9571MWV_VD25_VID 0x43 +#define BD9571MWV_VD33_VID 0x44 + +#define BD9571MWV_DVFS_VINIT 0x50 +#define BD9571MWV_DVFS_SETVMAX 0x52 +#define BD9571MWV_DVFS_BOOSTVID 0x53 +#define BD9571MWV_DVFS_SETVID 0x54 +#define BD9571MWV_DVFS_MONIVDAC 0x55 +#define BD9571MWV_DVFS_PGD_CNT 0x56 + +#define BD9571MWV_GPIO_DIR 0x60 +#define BD9571MWV_GPIO_OUT 0x61 +#define BD9571MWV_GPIO_IN 0x62 +#define BD9571MWV_GPIO_DEB 0x63 +#define BD9571MWV_GPIO_INT_SET 0x64 +#define BD9571MWV_GPIO_INT 0x65 +#define BD9571MWV_GPIO_INTMASK 0x66 + +#define BD9571MWV_REG_KEEP(n) (0x70 + (n)) + +#define BD9571MWV_PMIC_INTERNAL_STATUS 0x80 +#define BD9571MWV_PROT_ERROR_STATUS0 0x81 +#define BD9571MWV_PROT_ERROR_STATUS1 0x82 +#define BD9571MWV_PROT_ERROR_STATUS2 0x83 +#define BD9571MWV_PROT_ERROR_STATUS3 0x84 +#define BD9571MWV_PROT_ERROR_STATUS4 0x85 + +#define BD9571MWV_INT_INTREQ 0x90 +#define BD9571MWV_INT_INTREQ_MD1_INT BIT(0) +#define BD9571MWV_INT_INTREQ_MD2_E1_INT BIT(1) +#define BD9571MWV_INT_INTREQ_MD2_E2_INT BIT(2) +#define BD9571MWV_INT_INTREQ_PROT_ERR_INT BIT(3) +#define BD9571MWV_INT_INTREQ_GP_INT BIT(4) +#define BD9571MWV_INT_INTREQ_128H_OF_INT BIT(5) +#define BD9571MWV_INT_INTREQ_WDT_OF_INT BIT(6) +#define BD9571MWV_INT_INTREQ_BKUP_TRG_INT BIT(7) +#define BD9571MWV_INT_INTMASK 0x91 + +#define BD9571MWV_ACCESS_KEY 0xff + +/* Define the BD9571MWV IRQ numbers */ +enum bd9571mwv_irqs { + BD9571MWV_IRQ_MD1, + BD9571MWV_IRQ_MD2_E1, + BD9571MWV_IRQ_MD2_E2, + BD9571MWV_IRQ_PROT_ERR, + BD9571MWV_IRQ_GP, + BD9571MWV_IRQ_128H_OF, + BD9571MWV_IRQ_WDT_OF, + BD9571MWV_IRQ_BKUP_TRG, +}; + +/** + * struct bd9571mwv - state holder for the bd9571mwv driver + * + * Device data may be used to access the BD9571MWV chip + */ +struct bd9571mwv { + struct device *dev; + struct regmap *regmap; + + /* IRQ Data */ + int irq; + struct regmap_irq_chip_data *irq_data; +}; + +#endif /* __LINUX_MFD_BD9571MWV_H */ -- cgit v1.1 From 7e312ffdd7aa68f0110f5d95416f78ea29ceb984 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Wed, 26 Jul 2017 16:28:24 +0800 Subject: dt-bindings: mfd: axp20x: Add AXP806 to supported list of chips The binding already lists compatibles and regulators for the AXP806, but it is missing from the list of supported chips at the beginning. Add it. Fixes: 204ae2963e10 ("mfd: axp20x: Add bindings for AXP806 PMIC") Signed-off-by: Chen-Yu Tsai Acked-by: Rob Herring Acked-by: Maxime Ripard Signed-off-by: Lee Jones --- Documentation/devicetree/bindings/mfd/axp20x.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/mfd/axp20x.txt b/Documentation/devicetree/bindings/mfd/axp20x.txt index aca09af..211a100 100644 --- a/Documentation/devicetree/bindings/mfd/axp20x.txt +++ b/Documentation/devicetree/bindings/mfd/axp20x.txt @@ -7,6 +7,7 @@ axp209 (X-Powers) axp221 (X-Powers) axp223 (X-Powers) axp803 (X-Powers) +axp806 (X-Powers) axp809 (X-Powers) Required properties: -- cgit v1.1 From 7303733a6ca2a68b210ebdc09cace8b0ffe8b179 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Wed, 26 Jul 2017 16:28:26 +0800 Subject: mfd: axp20x: Add support for AXP813 PMIC The X-Powers AXP813 PMIC is normally used with Allwinner's A83T SoC. It has the same range of functions as other X-Powers PMICs, such as DC-DC buck converter and linear regulator outputs, AC-IN and VBUS power supplies, power button trigger, GPIOs, ADCs, and a battery charger. Note that the IRQ table given in the datasheet is incorrect: in IRQ enable/status registers 1, there are separate IRQs for ACIN and VBUS, instead of bits [7:5] being the same as bits [4:2]. So it shares the same IRQs as the AXP803, rather than the AXP288. This patch adds basic mfd support for it, with only the power button enabled. Signed-off-by: Chen-Yu Tsai Acked-by: Maxime Ripard Signed-off-by: Lee Jones --- drivers/mfd/axp20x-rsb.c | 1 + drivers/mfd/axp20x.c | 22 ++++++++++++++++++++++ include/linux/mfd/axp20x.h | 29 +++++++++++++++++++++++++++++ 3 files changed, 52 insertions(+) diff --git a/drivers/mfd/axp20x-rsb.c b/drivers/mfd/axp20x-rsb.c index fd5c726..7ddbd9e 100644 --- a/drivers/mfd/axp20x-rsb.c +++ b/drivers/mfd/axp20x-rsb.c @@ -64,6 +64,7 @@ static const struct of_device_id axp20x_rsb_of_match[] = { { .compatible = "x-powers,axp803", .data = (void *)AXP803_ID }, { .compatible = "x-powers,axp806", .data = (void *)AXP806_ID }, { .compatible = "x-powers,axp809", .data = (void *)AXP809_ID }, + { .compatible = "x-powers,axp813", .data = (void *)AXP813_ID }, { }, }; MODULE_DEVICE_TABLE(of, axp20x_rsb_of_match); diff --git a/drivers/mfd/axp20x.c b/drivers/mfd/axp20x.c index 917b6dd..ec4271c 100644 --- a/drivers/mfd/axp20x.c +++ b/drivers/mfd/axp20x.c @@ -44,6 +44,7 @@ static const char * const axp20x_model_names[] = { "AXP803", "AXP806", "AXP809", + "AXP813", }; static const struct regmap_range axp152_writeable_ranges[] = { @@ -870,6 +871,14 @@ static struct mfd_cell axp809_cells[] = { }, }; +static struct mfd_cell axp813_cells[] = { + { + .name = "axp20x-pek", + .num_resources = ARRAY_SIZE(axp803_pek_resources), + .resources = axp803_pek_resources, + } +}; + static struct axp20x_dev *axp20x_pm_power_off; static void axp20x_power_off(void) { @@ -956,6 +965,19 @@ int axp20x_match_device(struct axp20x_dev *axp20x) axp20x->regmap_cfg = &axp22x_regmap_config; axp20x->regmap_irq_chip = &axp809_regmap_irq_chip; break; + case AXP813_ID: + axp20x->nr_cells = ARRAY_SIZE(axp813_cells); + axp20x->cells = axp813_cells; + axp20x->regmap_cfg = &axp288_regmap_config; + /* + * The IRQ table given in the datasheet is incorrect. + * In IRQ enable/status registers 1, there are separate + * IRQs for ACIN and VBUS, instead of bits [7:5] being + * the same as bits [4:2]. So it shares the same IRQs + * as the AXP803, rather than the AXP288. + */ + axp20x->regmap_irq_chip = &axp803_regmap_irq_chip; + break; default: dev_err(dev, "unsupported AXP20X ID %lu\n", axp20x->variant); return -EINVAL; diff --git a/include/linux/mfd/axp20x.h b/include/linux/mfd/axp20x.h index 965b027..e9c908c 100644 --- a/include/linux/mfd/axp20x.h +++ b/include/linux/mfd/axp20x.h @@ -23,6 +23,7 @@ enum axp20x_variants { AXP803_ID, AXP806_ID, AXP809_ID, + AXP813_ID, NR_AXP20X_VARIANTS, }; @@ -387,6 +388,34 @@ enum { AXP803_REG_ID_MAX, }; +enum { + AXP813_DCDC1 = 0, + AXP813_DCDC2, + AXP813_DCDC3, + AXP813_DCDC4, + AXP813_DCDC5, + AXP813_DCDC6, + AXP813_DCDC7, + AXP813_ALDO1, + AXP813_ALDO2, + AXP813_ALDO3, + AXP813_DLDO1, + AXP813_DLDO2, + AXP813_DLDO3, + AXP813_DLDO4, + AXP813_ELDO1, + AXP813_ELDO2, + AXP813_ELDO3, + AXP813_FLDO1, + AXP813_FLDO2, + AXP813_FLDO3, + AXP813_RTC_LDO, + AXP813_LDO_IO0, + AXP813_LDO_IO1, + AXP813_SW, + AXP813_REG_ID_MAX, +}; + /* IRQs */ enum { AXP152_IRQ_LDO0IN_CONNECT = 1, -- cgit v1.1 From 462ae14190b42febd47699d2235fa0abae67afbf Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Wed, 26 Jul 2017 16:28:25 +0800 Subject: dt-bindings: mfd: axp20x: Introduce bindings for AXP813 The X-Powers AXP813 is a PMIC designed to be paired with Allwinner's A83T SoC. There is also an AXP818, which is paired with the H8 SoC. The two models seem to be identical, apart from the external markings. This patch introduces the basic mfd and regulator bindings for the AXP813. Signed-off-by: Chen-Yu Tsai Acked-by: Rob Herring Acked-by: Maxime Ripard Signed-off-by: Lee Jones --- Documentation/devicetree/bindings/mfd/axp20x.txt | 49 +++++++++++++++++++++--- 1 file changed, 44 insertions(+), 5 deletions(-) diff --git a/Documentation/devicetree/bindings/mfd/axp20x.txt b/Documentation/devicetree/bindings/mfd/axp20x.txt index 211a100..9455503 100644 --- a/Documentation/devicetree/bindings/mfd/axp20x.txt +++ b/Documentation/devicetree/bindings/mfd/axp20x.txt @@ -9,6 +9,12 @@ axp223 (X-Powers) axp803 (X-Powers) axp806 (X-Powers) axp809 (X-Powers) +axp813 (X-Powers) + +The AXP813 is 2 chips packaged into 1. The 2 chips do not share anything +other than the packaging. Pins are routed separately. As such they should +be treated as separate entities. The other half is an AC100 RTC/codec +combo chip. Please see ./ac100.txt for its bindings. Required properties: - compatible: should be one of: @@ -20,6 +26,7 @@ Required properties: * "x-powers,axp803" * "x-powers,axp806" * "x-powers,axp809" + * "x-powers,axp813" - reg: The I2C slave address or RSB hardware address for the AXP chip - interrupt-parent: The parent interrupt controller - interrupts: SoC NMI / GPIO interrupt connected to the PMIC's IRQ pin @@ -29,12 +36,14 @@ Required properties: Optional properties: - x-powers,dcdc-freq: defines the work frequency of DC-DC in KHz AXP152/20X: range: 750-1875, Default: 1.5 MHz - AXP22X/80X: range: 1800-4050, Default: 3 MHz + AXP22X/8XX: range: 1800-4050, Default: 3 MHz -- x-powers,drive-vbus-en: axp221 / axp223 only boolean, set this when the - N_VBUSEN pin is used as an output pin to control an external - regulator to drive the OTG VBus, rather then as an input pin - which signals whether the board is driving OTG VBus or not. +- x-powers,drive-vbus-en: boolean, set this when the N_VBUSEN pin is + used as an output pin to control an external + regulator to drive the OTG VBus, rather then + as an input pin which signals whether the + board is driving OTG VBus or not. + (axp221 / axp223 / axp813 only) - x-powers,master-mode: Boolean (axp806 only). Set this when the PMIC is wired for master mode. The default is slave mode. @@ -172,6 +181,36 @@ LDO_IO1 : LDO : ips-supply : GPIO 1 RTC_LDO : LDO : ips-supply : always on SW : On/Off Switch : swin-supply +AXP813 regulators, type, and corresponding input supply names: + +Regulator Type Supply Name Notes +--------- ---- ----------- ----- +DCDC1 : DC-DC buck : vin1-supply +DCDC2 : DC-DC buck : vin2-supply : poly-phase capable +DCDC3 : DC-DC buck : vin3-supply : poly-phase capable +DCDC4 : DC-DC buck : vin4-supply +DCDC5 : DC-DC buck : vin5-supply : poly-phase capable +DCDC6 : DC-DC buck : vin6-supply : poly-phase capable +DCDC7 : DC-DC buck : vin7-supply +ALDO1 : LDO : aldoin-supply : shared supply +ALDO2 : LDO : aldoin-supply : shared supply +ALDO3 : LDO : aldoin-supply : shared supply +DLDO1 : LDO : dldoin-supply : shared supply +DLDO2 : LDO : dldoin-supply : shared supply +DLDO3 : LDO : dldoin-supply : shared supply +DLDO4 : LDO : dldoin-supply : shared supply +ELDO1 : LDO : eldoin-supply : shared supply +ELDO2 : LDO : eldoin-supply : shared supply +ELDO3 : LDO : eldoin-supply : shared supply +FLDO1 : LDO : fldoin-supply : shared supply +FLDO2 : LDO : fldoin-supply : shared supply +FLDO3 : LDO : fldoin-supply : shared supply +LDO_IO0 : LDO : ips-supply : GPIO 0 +LDO_IO1 : LDO : ips-supply : GPIO 1 +RTC_LDO : LDO : ips-supply : always on +SW : On/Off Switch : swin-supply +DRIVEVBUS : Enable output : drivevbus-supply : external regulator + Example: axp209: pmic@34 { -- cgit v1.1 From f446363374e4c31fecad2cf95d877b4631de9890 Mon Sep 17 00:00:00 2001 From: Quentin Schulz Date: Wed, 26 Jul 2017 16:28:27 +0800 Subject: mfd: axp20x: Use correct platform device ID for many PEK According to their datasheets, the AXP221, AXP223, AXP288, AXP803, AXP809 and AXP813 PEK have different values for startup time bits from the AXP20X, let's use the platform device id with the correct values. Signed-off-by: Quentin Schulz Signed-off-by: Chen-Yu Tsai Acked-by: Maxime Ripard Signed-off-by: Lee Jones --- drivers/mfd/axp20x.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/mfd/axp20x.c b/drivers/mfd/axp20x.c index ec4271c..336de66 100644 --- a/drivers/mfd/axp20x.c +++ b/drivers/mfd/axp20x.c @@ -677,7 +677,7 @@ static struct mfd_cell axp20x_cells[] = { static struct mfd_cell axp221_cells[] = { { - .name = "axp20x-pek", + .name = "axp221-pek", .num_resources = ARRAY_SIZE(axp22x_pek_resources), .resources = axp22x_pek_resources, }, { @@ -702,7 +702,7 @@ static struct mfd_cell axp221_cells[] = { static struct mfd_cell axp223_cells[] = { { - .name = "axp20x-pek", + .name = "axp221-pek", .num_resources = ARRAY_SIZE(axp22x_pek_resources), .resources = axp22x_pek_resources, }, { @@ -835,7 +835,7 @@ static struct mfd_cell axp288_cells[] = { .resources = axp288_fuel_gauge_resources, }, { - .name = "axp20x-pek", + .name = "axp221-pek", .num_resources = ARRAY_SIZE(axp288_power_button_resources), .resources = axp288_power_button_resources, }, @@ -846,7 +846,7 @@ static struct mfd_cell axp288_cells[] = { static struct mfd_cell axp803_cells[] = { { - .name = "axp20x-pek", + .name = "axp221-pek", .num_resources = ARRAY_SIZE(axp803_pek_resources), .resources = axp803_pek_resources, }, @@ -862,7 +862,7 @@ static struct mfd_cell axp806_cells[] = { static struct mfd_cell axp809_cells[] = { { - .name = "axp20x-pek", + .name = "axp221-pek", .num_resources = ARRAY_SIZE(axp809_pek_resources), .resources = axp809_pek_resources, }, { @@ -873,7 +873,7 @@ static struct mfd_cell axp809_cells[] = { static struct mfd_cell axp813_cells[] = { { - .name = "axp20x-pek", + .name = "axp221-pek", .num_resources = ARRAY_SIZE(axp803_pek_resources), .resources = axp803_pek_resources, } -- cgit v1.1 From b0f3ab20e76499db12b0bbadb5737d9870f10418 Mon Sep 17 00:00:00 2001 From: Ludovic Desroches Date: Tue, 18 Jul 2017 15:22:19 +0200 Subject: mfd: syscon: atmel-smc: Add helper to retrieve register layout For HSMC controller, the register layout depends on the device i.e. the offset of setup, pulse, cycle, mode and timings registers is not the same. An helper is added to provide the correct register layout. Fixes: fe9d7cb22ef3 ("mfd: syscon: atmel-smc: Add new helpers to ease SMC regs manipulation") Suggested-by: Boris Brezillon Signed-off-by: Ludovic Desroches Acked-by: Boris Brezillon Acked-by: Nicolas Ferre Acked-by: Alexandre Belloni Signed-off-by: Lee Jones --- drivers/memory/atmel-ebi.c | 13 +++++-- drivers/mfd/atmel-smc.c | 67 +++++++++++++++++++++++++------- drivers/mtd/nand/atmel/nand-controller.c | 10 +++-- include/linux/mfd/syscon/atmel-smc.h | 32 ++++++++++----- 4 files changed, 92 insertions(+), 30 deletions(-) diff --git a/drivers/memory/atmel-ebi.c b/drivers/memory/atmel-ebi.c index ebf69ff..c00a7c7 100644 --- a/drivers/memory/atmel-ebi.c +++ b/drivers/memory/atmel-ebi.c @@ -51,6 +51,7 @@ struct atmel_ebi { struct { struct regmap *regmap; struct clk *clk; + const struct atmel_hsmc_reg_layout *layout; } smc; struct device *dev; @@ -84,8 +85,8 @@ static void at91sam9_ebi_get_config(struct atmel_ebi_dev *ebid, static void sama5_ebi_get_config(struct atmel_ebi_dev *ebid, struct atmel_ebi_dev_config *conf) { - atmel_hsmc_cs_conf_get(ebid->ebi->smc.regmap, conf->cs, - &conf->smcconf); + atmel_hsmc_cs_conf_get(ebid->ebi->smc.regmap, ebid->ebi->smc.layout, + conf->cs, &conf->smcconf); } static const struct atmel_smc_timing_xlate timings_xlate_table[] = { @@ -287,8 +288,8 @@ static void at91sam9_ebi_apply_config(struct atmel_ebi_dev *ebid, static void sama5_ebi_apply_config(struct atmel_ebi_dev *ebid, struct atmel_ebi_dev_config *conf) { - atmel_hsmc_cs_conf_apply(ebid->ebi->smc.regmap, conf->cs, - &conf->smcconf); + atmel_hsmc_cs_conf_apply(ebid->ebi->smc.regmap, ebid->ebi->smc.layout, + conf->cs, &conf->smcconf); } static int atmel_ebi_dev_setup(struct atmel_ebi *ebi, struct device_node *np, @@ -527,6 +528,10 @@ static int atmel_ebi_probe(struct platform_device *pdev) if (IS_ERR(ebi->smc.regmap)) return PTR_ERR(ebi->smc.regmap); + ebi->smc.layout = atmel_hsmc_get_reg_layout(smc_np); + if (IS_ERR(ebi->smc.layout)) + return PTR_ERR(ebi->smc.layout); + ebi->smc.clk = of_clk_get(smc_np, 0); if (IS_ERR(ebi->smc.clk)) { if (PTR_ERR(ebi->smc.clk) != -ENOENT) diff --git a/drivers/mfd/atmel-smc.c b/drivers/mfd/atmel-smc.c index 20cc0ea..7d77948 100644 --- a/drivers/mfd/atmel-smc.c +++ b/drivers/mfd/atmel-smc.c @@ -258,19 +258,21 @@ EXPORT_SYMBOL_GPL(atmel_smc_cs_conf_apply); * atmel_hsmc_cs_conf_apply - apply an SMC CS conf * @regmap: the HSMC regmap * @cs: the CS id + * @layout: the layout of registers * @conf the SMC CS conf to apply * * Applies an SMC CS configuration. * Only valid on post-sama5 SoCs. */ -void atmel_hsmc_cs_conf_apply(struct regmap *regmap, int cs, - const struct atmel_smc_cs_conf *conf) +void atmel_hsmc_cs_conf_apply(struct regmap *regmap, + const struct atmel_hsmc_reg_layout *layout, + int cs, const struct atmel_smc_cs_conf *conf) { - regmap_write(regmap, ATMEL_HSMC_SETUP(cs), conf->setup); - regmap_write(regmap, ATMEL_HSMC_PULSE(cs), conf->pulse); - regmap_write(regmap, ATMEL_HSMC_CYCLE(cs), conf->cycle); - regmap_write(regmap, ATMEL_HSMC_TIMINGS(cs), conf->timings); - regmap_write(regmap, ATMEL_HSMC_MODE(cs), conf->mode); + regmap_write(regmap, ATMEL_HSMC_SETUP(layout, cs), conf->setup); + regmap_write(regmap, ATMEL_HSMC_PULSE(layout, cs), conf->pulse); + regmap_write(regmap, ATMEL_HSMC_CYCLE(layout, cs), conf->cycle); + regmap_write(regmap, ATMEL_HSMC_TIMINGS(layout, cs), conf->timings); + regmap_write(regmap, ATMEL_HSMC_MODE(layout, cs), conf->mode); } EXPORT_SYMBOL_GPL(atmel_hsmc_cs_conf_apply); @@ -297,18 +299,55 @@ EXPORT_SYMBOL_GPL(atmel_smc_cs_conf_get); * atmel_hsmc_cs_conf_get - retrieve the current SMC CS conf * @regmap: the HSMC regmap * @cs: the CS id + * @layout: the layout of registers * @conf: the SMC CS conf object to store the current conf * * Retrieve the SMC CS configuration. * Only valid on post-sama5 SoCs. */ -void atmel_hsmc_cs_conf_get(struct regmap *regmap, int cs, - struct atmel_smc_cs_conf *conf) +void atmel_hsmc_cs_conf_get(struct regmap *regmap, + const struct atmel_hsmc_reg_layout *layout, + int cs, struct atmel_smc_cs_conf *conf) { - regmap_read(regmap, ATMEL_HSMC_SETUP(cs), &conf->setup); - regmap_read(regmap, ATMEL_HSMC_PULSE(cs), &conf->pulse); - regmap_read(regmap, ATMEL_HSMC_CYCLE(cs), &conf->cycle); - regmap_read(regmap, ATMEL_HSMC_TIMINGS(cs), &conf->timings); - regmap_read(regmap, ATMEL_HSMC_MODE(cs), &conf->mode); + regmap_read(regmap, ATMEL_HSMC_SETUP(layout, cs), &conf->setup); + regmap_read(regmap, ATMEL_HSMC_PULSE(layout, cs), &conf->pulse); + regmap_read(regmap, ATMEL_HSMC_CYCLE(layout, cs), &conf->cycle); + regmap_read(regmap, ATMEL_HSMC_TIMINGS(layout, cs), &conf->timings); + regmap_read(regmap, ATMEL_HSMC_MODE(layout, cs), &conf->mode); } EXPORT_SYMBOL_GPL(atmel_hsmc_cs_conf_get); + +static const struct atmel_hsmc_reg_layout sama5d3_reg_layout = { + .timing_regs_offset = 0x600, +}; + +static const struct atmel_hsmc_reg_layout sama5d2_reg_layout = { + .timing_regs_offset = 0x700, +}; + +static const struct of_device_id atmel_smc_ids[] = { + { .compatible = "atmel,at91sam9260-smc", .data = NULL }, + { .compatible = "atmel,sama5d3-smc", .data = &sama5d3_reg_layout }, + { .compatible = "atmel,sama5d2-smc", .data = &sama5d2_reg_layout }, + { /* sentinel */ }, +}; + +/** + * atmel_hsmc_get_reg_layout - retrieve the layout of HSMC registers + * @np: the HSMC regmap + * + * Retrieve the layout of HSMC registers. + * + * Returns NULL in case of SMC, a struct atmel_hsmc_reg_layout pointer + * in HSMC case, otherwise ERR_PTR(-EINVAL). + */ +const struct atmel_hsmc_reg_layout * +atmel_hsmc_get_reg_layout(struct device_node *np) +{ + const struct of_device_id *match; + + match = of_match_node(atmel_smc_ids, np); + + return match ? match->data : ERR_PTR(-EINVAL); +} +EXPORT_SYMBOL_GPL(atmel_hsmc_get_reg_layout); diff --git a/drivers/mtd/nand/atmel/nand-controller.c b/drivers/mtd/nand/atmel/nand-controller.c index ceec21b..1913ce1 100644 --- a/drivers/mtd/nand/atmel/nand-controller.c +++ b/drivers/mtd/nand/atmel/nand-controller.c @@ -247,6 +247,7 @@ struct atmel_hsmc_nand_controller { void __iomem *virt; dma_addr_t dma; } sram; + const struct atmel_hsmc_reg_layout *hsmc_layout; struct regmap *io; struct atmel_nfc_op op; struct completion complete; @@ -1442,12 +1443,12 @@ static int atmel_hsmc_nand_setup_data_interface(struct atmel_nand *nand, int csline, const struct nand_data_interface *conf) { - struct atmel_nand_controller *nc; + struct atmel_hsmc_nand_controller *nc; struct atmel_smc_cs_conf smcconf; struct atmel_nand_cs *cs; int ret; - nc = to_nand_controller(nand->base.controller); + nc = to_hsmc_nand_controller(nand->base.controller); ret = atmel_smc_nand_prepare_smcconf(nand, conf, &smcconf); if (ret) @@ -1462,7 +1463,8 @@ static int atmel_hsmc_nand_setup_data_interface(struct atmel_nand *nand, if (cs->rb.type == ATMEL_NAND_NATIVE_RB) cs->smcconf.timings |= ATMEL_HSMC_TIMINGS_RBNSEL(cs->rb.id); - atmel_hsmc_cs_conf_apply(nc->smc, cs->id, &cs->smcconf); + atmel_hsmc_cs_conf_apply(nc->base.smc, nc->hsmc_layout, cs->id, + &cs->smcconf); return 0; } @@ -2177,6 +2179,8 @@ atmel_hsmc_nand_controller_init(struct atmel_hsmc_nand_controller *nc) return -EINVAL; } + nc->hsmc_layout = atmel_hsmc_get_reg_layout(np); + nc->irq = of_irq_get(np, 0); of_node_put(np); if (nc->irq < 0) { diff --git a/include/linux/mfd/syscon/atmel-smc.h b/include/linux/mfd/syscon/atmel-smc.h index afa2661..7a367f3 100644 --- a/include/linux/mfd/syscon/atmel-smc.h +++ b/include/linux/mfd/syscon/atmel-smc.h @@ -15,21 +15,26 @@ #define _LINUX_MFD_SYSCON_ATMEL_SMC_H_ #include +#include #include #define ATMEL_SMC_SETUP(cs) (((cs) * 0x10)) -#define ATMEL_HSMC_SETUP(cs) (0x600 + ((cs) * 0x14)) +#define ATMEL_HSMC_SETUP(layout, cs) \ + ((layout)->timing_regs_offset + ((cs) * 0x14)) #define ATMEL_SMC_PULSE(cs) (((cs) * 0x10) + 0x4) -#define ATMEL_HSMC_PULSE(cs) (0x600 + ((cs) * 0x14) + 0x4) +#define ATMEL_HSMC_PULSE(layout, cs) \ + ((layout)->timing_regs_offset + ((cs) * 0x14) + 0x4) #define ATMEL_SMC_CYCLE(cs) (((cs) * 0x10) + 0x8) -#define ATMEL_HSMC_CYCLE(cs) (0x600 + ((cs) * 0x14) + 0x8) +#define ATMEL_HSMC_CYCLE(layout, cs) \ + ((layout)->timing_regs_offset + ((cs) * 0x14) + 0x8) #define ATMEL_SMC_NWE_SHIFT 0 #define ATMEL_SMC_NCS_WR_SHIFT 8 #define ATMEL_SMC_NRD_SHIFT 16 #define ATMEL_SMC_NCS_RD_SHIFT 24 #define ATMEL_SMC_MODE(cs) (((cs) * 0x10) + 0xc) -#define ATMEL_HSMC_MODE(cs) (0x600 + ((cs) * 0x14) + 0x10) +#define ATMEL_HSMC_MODE(layout, cs) \ + ((layout)->timing_regs_offset + ((cs) * 0x14) + 0x10) #define ATMEL_SMC_MODE_READMODE_MASK BIT(0) #define ATMEL_SMC_MODE_READMODE_NCS (0 << 0) #define ATMEL_SMC_MODE_READMODE_NRD (1 << 0) @@ -59,7 +64,8 @@ #define ATMEL_SMC_MODE_PS_16 (2 << 28) #define ATMEL_SMC_MODE_PS_32 (3 << 28) -#define ATMEL_HSMC_TIMINGS(cs) (0x600 + ((cs) * 0x14) + 0xc) +#define ATMEL_HSMC_TIMINGS(layout, cs) \ + ((layout)->timing_regs_offset + ((cs) * 0x14) + 0xc) #define ATMEL_HSMC_TIMINGS_OCMS BIT(12) #define ATMEL_HSMC_TIMINGS_RBNSEL(x) ((x) << 28) #define ATMEL_HSMC_TIMINGS_NFSEL BIT(31) @@ -69,6 +75,10 @@ #define ATMEL_HSMC_TIMINGS_TRR_SHIFT 16 #define ATMEL_HSMC_TIMINGS_TWB_SHIFT 24 +struct atmel_hsmc_reg_layout { + unsigned int timing_regs_offset; +}; + /** * struct atmel_smc_cs_conf - SMC CS config as described in the datasheet. * @setup: NCS/NWE/NRD setup timings (not applicable to at91rm9200) @@ -98,11 +108,15 @@ int atmel_smc_cs_conf_set_cycle(struct atmel_smc_cs_conf *conf, unsigned int shift, unsigned int ncycles); void atmel_smc_cs_conf_apply(struct regmap *regmap, int cs, const struct atmel_smc_cs_conf *conf); -void atmel_hsmc_cs_conf_apply(struct regmap *regmap, int cs, - const struct atmel_smc_cs_conf *conf); +void atmel_hsmc_cs_conf_apply(struct regmap *regmap, + const struct atmel_hsmc_reg_layout *reglayout, + int cs, const struct atmel_smc_cs_conf *conf); void atmel_smc_cs_conf_get(struct regmap *regmap, int cs, struct atmel_smc_cs_conf *conf); -void atmel_hsmc_cs_conf_get(struct regmap *regmap, int cs, - struct atmel_smc_cs_conf *conf); +void atmel_hsmc_cs_conf_get(struct regmap *regmap, + const struct atmel_hsmc_reg_layout *reglayout, + int cs, struct atmel_smc_cs_conf *conf); +const struct atmel_hsmc_reg_layout * +atmel_hsmc_get_reg_layout(struct device_node *np); #endif /* _LINUX_MFD_SYSCON_ATMEL_SMC_H_ */ -- cgit v1.1 From d9018976cdb6eefc62a7ba79a405f6c9661b08a7 Mon Sep 17 00:00:00 2001 From: Mika Westerberg Date: Fri, 28 Jul 2017 13:50:42 +0300 Subject: mfd: lpc_ich: Do not touch SPI-NOR write protection bit on Haswell/Broadwell MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit At least on Lenovo Thinkpad Yoga, the BIOS seems to monitor the SPI-NOR write protection bit and if it is flipped to read/write it assumes the BIOS configuration was changed on next reboot. It then, for unknown reasons, resets the BIOS settings back to default. We can prevent this by just leaving the write protection bit intact and let the SPI-NOR driver know whether the device is writable or not. In case of this particular Lenovo the SPI-NOR flash will be exposed as read-only. Fixes: ff00d7a32a1b ("mfd: lpc_ich: Add support for SPI serial flash host controller") Link: https://bugzilla.kernel.org/show_bug.cgi?id=195951 Reported-by: Abdó Roig-Marange Signed-off-by: Mika Westerberg Signed-off-by: Lee Jones --- drivers/mfd/lpc_ich.c | 10 ---------- 1 file changed, 10 deletions(-) diff --git a/drivers/mfd/lpc_ich.c b/drivers/mfd/lpc_ich.c index 773f155..450ae36 100644 --- a/drivers/mfd/lpc_ich.c +++ b/drivers/mfd/lpc_ich.c @@ -1119,17 +1119,7 @@ static int lpc_ich_init_spi(struct pci_dev *dev) res->start = spi_base + SPIBASE_LPT; res->end = res->start + SPIBASE_LPT_SZ - 1; - /* - * Try to make the flash chip writeable now by - * setting BCR_WPD. It it fails we tell the driver - * that it can only read the chip. - */ pci_read_config_dword(dev, BCR, &bcr); - if (!(bcr & BCR_WPD)) { - bcr |= BCR_WPD; - pci_write_config_dword(dev, BCR, bcr); - pci_read_config_dword(dev, BCR, &bcr); - } info->writeable = !!(bcr & BCR_WPD); } break; -- cgit v1.1 From 9bbf6a15ce19dd947b7fa6ad4095931ab3682da8 Mon Sep 17 00:00:00 2001 From: Rajmohan Mani Date: Fri, 28 Jul 2017 17:30:24 -0700 Subject: mfd: Add support for TPS68470 device The TPS68470 device is an advanced power management unit that powers a Compact Camera Module (CCM), generates clocks for image sensors, drives a dual LED for Flash and incorporates two LED drivers for general purpose indicators. This patch adds support for TPS68470 mfd device. Signed-off-by: Rajmohan Mani Signed-off-by: Lee Jones --- drivers/mfd/Kconfig | 18 ++++++++ drivers/mfd/Makefile | 1 + drivers/mfd/tps68470.c | 106 +++++++++++++++++++++++++++++++++++++++++++ include/linux/mfd/tps68470.h | 97 +++++++++++++++++++++++++++++++++++++++ 4 files changed, 222 insertions(+) create mode 100644 drivers/mfd/tps68470.c create mode 100644 include/linux/mfd/tps68470.h diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig index 79e4ec6..4f57725 100644 --- a/drivers/mfd/Kconfig +++ b/drivers/mfd/Kconfig @@ -1352,6 +1352,24 @@ config MFD_TPS65217 This driver can also be built as a module. If so, the module will be called tps65217. +config MFD_TPS68470 + bool "TI TPS68470 Power Management / LED chips" + depends on ACPI && I2C=y + select MFD_CORE + select REGMAP_I2C + select I2C_DESIGNWARE_PLATFORM + help + If you say yes here you get support for the TPS68470 series of + Power Management / LED chips. + + These include voltage regulators, LEDs and other features + that are often used in portable devices. + + This option is a bool as it provides an ACPI operation + region, which must be available before any of the devices + using this are probed. This option also configures the + designware-i2c driver to be built-in, for the same reason. + config MFD_TI_LP873X tristate "TI LP873X Power Management IC" depends on I2C diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile index 21e19a5..c3d0a1b 100644 --- a/drivers/mfd/Makefile +++ b/drivers/mfd/Makefile @@ -84,6 +84,7 @@ obj-$(CONFIG_MFD_TPS65910) += tps65910.o obj-$(CONFIG_MFD_TPS65912) += tps65912-core.o obj-$(CONFIG_MFD_TPS65912_I2C) += tps65912-i2c.o obj-$(CONFIG_MFD_TPS65912_SPI) += tps65912-spi.o +obj-$(CONFIG_MFD_TPS68470) += tps68470.o obj-$(CONFIG_MFD_TPS80031) += tps80031.o obj-$(CONFIG_MENELAUS) += menelaus.o diff --git a/drivers/mfd/tps68470.c b/drivers/mfd/tps68470.c new file mode 100644 index 0000000..189efae --- /dev/null +++ b/drivers/mfd/tps68470.c @@ -0,0 +1,106 @@ +/* + * TPS68470 chip Parent driver + * + * Copyright (C) 2017 Intel Corporation + * + * Authors: + * Rajmohan Mani + * Tianshu Qiu + * Jian Xu Zheng + * Yuning Pu + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation version 2. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include + +static const struct mfd_cell tps68470s[] = { + { .name = "tps68470-gpio" }, + { .name = "tps68470_pmic_opregion" }, +}; + +static const struct regmap_config tps68470_regmap_config = { + .reg_bits = 8, + .val_bits = 8, + .max_register = TPS68470_REG_MAX, +}; + +static int tps68470_chip_init(struct device *dev, struct regmap *regmap) +{ + unsigned int version; + int ret; + + /* Force software reset */ + ret = regmap_write(regmap, TPS68470_REG_RESET, TPS68470_REG_RESET_MASK); + if (ret) + return ret; + + ret = regmap_read(regmap, TPS68470_REG_REVID, &version); + if (ret) { + dev_err(dev, "Failed to read revision register: %d\n", ret); + return ret; + } + + dev_info(dev, "TPS68470 REVID: 0x%x\n", version); + + return 0; +} + +static int tps68470_probe(struct i2c_client *client) +{ + struct device *dev = &client->dev; + struct regmap *regmap; + int ret; + + regmap = devm_regmap_init_i2c(client, &tps68470_regmap_config); + if (IS_ERR(regmap)) { + dev_err(dev, "devm_regmap_init_i2c Error %ld\n", + PTR_ERR(regmap)); + return PTR_ERR(regmap); + } + + i2c_set_clientdata(client, regmap); + + ret = tps68470_chip_init(dev, regmap); + if (ret < 0) { + dev_err(dev, "TPS68470 Init Error %d\n", ret); + return ret; + } + + ret = devm_mfd_add_devices(dev, PLATFORM_DEVID_NONE, tps68470s, + ARRAY_SIZE(tps68470s), NULL, 0, NULL); + if (ret < 0) { + dev_err(dev, "devm_mfd_add_devices failed: %d\n", ret); + return ret; + } + + return 0; +} + +static const struct acpi_device_id tps68470_acpi_ids[] = { + {"INT3472"}, + {}, +}; +MODULE_DEVICE_TABLE(acpi, tps68470_acpi_ids); + +static struct i2c_driver tps68470_driver = { + .driver = { + .name = "tps68470", + .acpi_match_table = tps68470_acpi_ids, + }, + .probe_new = tps68470_probe, +}; +builtin_i2c_driver(tps68470_driver); diff --git a/include/linux/mfd/tps68470.h b/include/linux/mfd/tps68470.h new file mode 100644 index 0000000..44f9d9f --- /dev/null +++ b/include/linux/mfd/tps68470.h @@ -0,0 +1,97 @@ +/* + * Copyright (c) 2017 Intel Corporation + * + * Functions to access TPS68470 power management chip. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation version 2. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __LINUX_MFD_TPS68470_H +#define __LINUX_MFD_TPS68470_H + +/* Register addresses */ +#define TPS68470_REG_POSTDIV2 0x06 +#define TPS68470_REG_BOOSTDIV 0x07 +#define TPS68470_REG_BUCKDIV 0x08 +#define TPS68470_REG_PLLSWR 0x09 +#define TPS68470_REG_XTALDIV 0x0A +#define TPS68470_REG_PLLDIV 0x0B +#define TPS68470_REG_POSTDIV 0x0C +#define TPS68470_REG_PLLCTL 0x0D +#define TPS68470_REG_PLLCTL2 0x0E +#define TPS68470_REG_CLKCFG1 0x0F +#define TPS68470_REG_CLKCFG2 0x10 +#define TPS68470_REG_GPCTL0A 0x14 +#define TPS68470_REG_GPCTL0B 0x15 +#define TPS68470_REG_GPCTL1A 0x16 +#define TPS68470_REG_GPCTL1B 0x17 +#define TPS68470_REG_GPCTL2A 0x18 +#define TPS68470_REG_GPCTL2B 0x19 +#define TPS68470_REG_GPCTL3A 0x1A +#define TPS68470_REG_GPCTL3B 0x1B +#define TPS68470_REG_GPCTL4A 0x1C +#define TPS68470_REG_GPCTL4B 0x1D +#define TPS68470_REG_GPCTL5A 0x1E +#define TPS68470_REG_GPCTL5B 0x1F +#define TPS68470_REG_GPCTL6A 0x20 +#define TPS68470_REG_GPCTL6B 0x21 +#define TPS68470_REG_SGPO 0x22 +#define TPS68470_REG_GPDI 0x26 +#define TPS68470_REG_GPDO 0x27 +#define TPS68470_REG_VCMVAL 0x3C +#define TPS68470_REG_VAUX1VAL 0x3D +#define TPS68470_REG_VAUX2VAL 0x3E +#define TPS68470_REG_VIOVAL 0x3F +#define TPS68470_REG_VSIOVAL 0x40 +#define TPS68470_REG_VAVAL 0x41 +#define TPS68470_REG_VDVAL 0x42 +#define TPS68470_REG_S_I2C_CTL 0x43 +#define TPS68470_REG_VCMCTL 0x44 +#define TPS68470_REG_VAUX1CTL 0x45 +#define TPS68470_REG_VAUX2CTL 0x46 +#define TPS68470_REG_VACTL 0x47 +#define TPS68470_REG_VDCTL 0x48 +#define TPS68470_REG_RESET 0x50 +#define TPS68470_REG_REVID 0xFF + +#define TPS68470_REG_MAX TPS68470_REG_REVID + +/* Register field definitions */ + +#define TPS68470_REG_RESET_MASK GENMASK(7, 0) +#define TPS68470_VAVAL_AVOLT_MASK GENMASK(6, 0) + +#define TPS68470_VDVAL_DVOLT_MASK GENMASK(5, 0) +#define TPS68470_VCMVAL_VCVOLT_MASK GENMASK(6, 0) +#define TPS68470_VIOVAL_IOVOLT_MASK GENMASK(6, 0) +#define TPS68470_VSIOVAL_IOVOLT_MASK GENMASK(6, 0) +#define TPS68470_VAUX1VAL_AUX1VOLT_MASK GENMASK(6, 0) +#define TPS68470_VAUX2VAL_AUX2VOLT_MASK GENMASK(6, 0) + +#define TPS68470_VACTL_EN_MASK GENMASK(0, 0) +#define TPS68470_VDCTL_EN_MASK GENMASK(0, 0) +#define TPS68470_VCMCTL_EN_MASK GENMASK(0, 0) +#define TPS68470_S_I2C_CTL_EN_MASK GENMASK(1, 0) +#define TPS68470_VAUX1CTL_EN_MASK GENMASK(0, 0) +#define TPS68470_VAUX2CTL_EN_MASK GENMASK(0, 0) +#define TPS68470_PLL_EN_MASK GENMASK(0, 0) + +#define TPS68470_CLKCFG1_MODE_A_MASK GENMASK(1, 0) +#define TPS68470_CLKCFG1_MODE_B_MASK GENMASK(3, 2) + +#define TPS68470_GPIO_CTL_REG_A(x) (TPS68470_REG_GPCTL0A + (x) * 2) +#define TPS68470_GPIO_CTL_REG_B(x) (TPS68470_REG_GPCTL0B + (x) * 2) +#define TPS68470_GPIO_MODE_MASK GENMASK(1, 0) +#define TPS68470_GPIO_MODE_IN 0 +#define TPS68470_GPIO_MODE_IN_PULLUP 1 +#define TPS68470_GPIO_MODE_OUT_CMOS 2 +#define TPS68470_GPIO_MODE_OUT_ODRAIN 3 + +#endif /* __LINUX_MFD_TPS68470_H */ -- cgit v1.1 From ea3993a9bdb77375a91e88b5e5f853474b095dd5 Mon Sep 17 00:00:00 2001 From: Axel Lin Date: Sun, 30 Jul 2017 18:58:15 +0800 Subject: mfd: lp87565: Convert to use devm_mfd_add_devices() This fixes missing mfd_remove_devices() call when unload the module. Signed-off-by: Axel Lin Reviewed-by: Keerthy Signed-off-by: Lee Jones --- drivers/mfd/lp87565.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/drivers/mfd/lp87565.c b/drivers/mfd/lp87565.c index 340ad0c..32d2a07 100644 --- a/drivers/mfd/lp87565.c +++ b/drivers/mfd/lp87565.c @@ -73,10 +73,9 @@ static int lp87565_probe(struct i2c_client *client, i2c_set_clientdata(client, lp87565); - ret = mfd_add_devices(lp87565->dev, PLATFORM_DEVID_AUTO, lp87565_cells, - ARRAY_SIZE(lp87565_cells), NULL, 0, NULL); - - return ret; + return devm_mfd_add_devices(lp87565->dev, PLATFORM_DEVID_AUTO, + lp87565_cells, ARRAY_SIZE(lp87565_cells), + NULL, 0, NULL); } static const struct i2c_device_id lp87565_id_table[] = { -- cgit v1.1 From 1ae14f8e84727d158cb6d27760e6f17eb9994cff Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Mon, 14 Aug 2017 22:02:23 +0200 Subject: mfd: intel_soc_pmic_chtwc: Turn Kconfig option into a bool The PMIC provides ACPI OpRegions which must be available for other drivers' PS0 / PS3 methods early-on as such it must be builtin as the Kconfig help text already states. Somehow its Kconfig option ended up being a tristate though, this fixes this. Signed-off-by: Hans de Goede Signed-off-by: Lee Jones --- drivers/mfd/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig index 4f57725..7bc4ee1 100644 --- a/drivers/mfd/Kconfig +++ b/drivers/mfd/Kconfig @@ -495,7 +495,7 @@ config INTEL_SOC_PMIC_BXTWC on these systems. config INTEL_SOC_PMIC_CHTWC - tristate "Support for Intel Cherry Trail Whiskey Cove PMIC" + bool "Support for Intel Cherry Trail Whiskey Cove PMIC" depends on ACPI && HAS_IOMEM && I2C=y && COMMON_CLK depends on X86 || COMPILE_TEST select MFD_CORE -- cgit v1.1 From e10feb36c98576fd7d1f24edaf2669dbfe7df21d Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 2 May 2017 14:18:15 +0200 Subject: mfd: Add ROHM BD9571MWV-M PMIC DT bindings Add DT bindings for the ROHM BD9571MWV-M PMIC. This PMIC has the following features: - multiple voltage monitors for 1V8, 2V5, 3V3 voltage rail - one voltage regulator for DVFS - two GPIOs Signed-off-by: Marek Vasut Acked-by: Rob Herring Signed-off-by: Lee Jones --- .../devicetree/bindings/mfd/bd9571mwv.txt | 49 ++++++++++++++++++++++ 1 file changed, 49 insertions(+) create mode 100644 Documentation/devicetree/bindings/mfd/bd9571mwv.txt diff --git a/Documentation/devicetree/bindings/mfd/bd9571mwv.txt b/Documentation/devicetree/bindings/mfd/bd9571mwv.txt new file mode 100644 index 0000000..9ab216a --- /dev/null +++ b/Documentation/devicetree/bindings/mfd/bd9571mwv.txt @@ -0,0 +1,49 @@ +* ROHM BD9571MWV Power Management Integrated Circuit (PMIC) bindings + +Required properties: + - compatible : Should be "rohm,bd9571mwv". + - reg : I2C slave address. + - interrupt-parent : Phandle to the parent interrupt controller. + - interrupts : The interrupt line the device is connected to. + - interrupt-controller : Marks the device node as an interrupt controller. + - #interrupt-cells : The number of cells to describe an IRQ, should be 2. + The first cell is the IRQ number. + The second cell is the flags, encoded as trigger + masks from ../interrupt-controller/interrupts.txt. + - gpio-controller : Marks the device node as a GPIO Controller. + - #gpio-cells : Should be two. The first cell is the pin number and + the second cell is used to specify flags. + See ../gpio/gpio.txt for more information. + - regulators: : List of child nodes that specify the regulator + initialization data. Child nodes must be named + after their hardware counterparts: + - vd09 + - vd18 + - vd25 + - vd33 + - dvfs + Each child node is defined using the standard + binding for regulators. + +Example: + + pmic: pmic@30 { + compatible = "rohm,bd9571mwv"; + reg = <0x30>; + interrupt-parent = <&gpio2>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-controller; + #gpio-cells = <2>; + + regulators { + dvfs: dvfs { + regulator-name = "dvfs"; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1030000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; -- cgit v1.1 From b62d8dbe419893b7aee5fac282e1da8c811cfcfb Mon Sep 17 00:00:00 2001 From: Arvind Yadav Date: Tue, 8 Aug 2017 15:24:56 +0530 Subject: mfd: t7l66xb: Handle return value of clk_prepare_enable clk_prepare_enable() can fail here and we must check its return value. we must disable clock, if t7l66xb_probe is not successful. Signed-off-by: Arvind Yadav Signed-off-by: Lee Jones --- drivers/mfd/t7l66xb.c | 17 ++++++++++++++--- 1 file changed, 14 insertions(+), 3 deletions(-) diff --git a/drivers/mfd/t7l66xb.c b/drivers/mfd/t7l66xb.c index 22c8113..43d8683 100644 --- a/drivers/mfd/t7l66xb.c +++ b/drivers/mfd/t7l66xb.c @@ -86,8 +86,11 @@ static int t7l66xb_mmc_enable(struct platform_device *mmc) struct t7l66xb *t7l66xb = platform_get_drvdata(dev); unsigned long flags; u8 dev_ctl; + int ret; - clk_prepare_enable(t7l66xb->clk32k); + ret = clk_prepare_enable(t7l66xb->clk32k); + if (ret) + return ret; raw_spin_lock_irqsave(&t7l66xb->lock, flags); @@ -286,8 +289,12 @@ static int t7l66xb_resume(struct platform_device *dev) { struct t7l66xb *t7l66xb = platform_get_drvdata(dev); struct t7l66xb_platform_data *pdata = dev_get_platdata(&dev->dev); + int ret; + + ret = clk_prepare_enable(t7l66xb->clk48m); + if (ret) + return ret; - clk_prepare_enable(t7l66xb->clk48m); if (pdata && pdata->resume) pdata->resume(dev); @@ -361,7 +368,9 @@ static int t7l66xb_probe(struct platform_device *dev) goto err_ioremap; } - clk_prepare_enable(t7l66xb->clk48m); + ret = clk_prepare_enable(t7l66xb->clk48m); + if (ret) + goto err_clk_enable; if (pdata->enable) pdata->enable(dev); @@ -386,6 +395,8 @@ static int t7l66xb_probe(struct platform_device *dev) return 0; t7l66xb_detach_irq(dev); + clk_disable_unprepare(t7l66xb->clk48m); +err_clk_enable: iounmap(t7l66xb->scr); err_ioremap: release_resource(&t7l66xb->rscr); -- cgit v1.1 From e4b91470bd79b988253ec00590e5b554042af4a7 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Florian=20R=2E=20H=C3=B6lzlwimmer?= Date: Sat, 19 Aug 2017 15:26:49 +0200 Subject: mfd: intel-lpss: Add missing PCI ID for Intel Sunrise Point LPSS devices MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This patch adds a missing PCI ID of the Intel Sunrise Point chipset to the Intel LPSS driver. It fixes a bug causing the touchpad of the Lenovo Yoga 720-15 not to be recognized. See also bug 1700657 on bugs.launchpad.net. Many thanks to CoolStar, who found this solution! Reported-by: CoolStar Tested-by: Mike Schwartz Tested-by: Björn Dahlgren Signed-off-by: Florian R. Hölzlwimmer Signed-off-by: Lee Jones --- drivers/mfd/intel-lpss-pci.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/mfd/intel-lpss-pci.c b/drivers/mfd/intel-lpss-pci.c index ad388bb..d1c46de 100644 --- a/drivers/mfd/intel-lpss-pci.c +++ b/drivers/mfd/intel-lpss-pci.c @@ -221,6 +221,7 @@ static const struct pci_device_id intel_lpss_pci_ids[] = { { PCI_VDEVICE(INTEL, 0xa12a), (kernel_ulong_t)&spt_info }, { PCI_VDEVICE(INTEL, 0xa160), (kernel_ulong_t)&spt_i2c_info }, { PCI_VDEVICE(INTEL, 0xa161), (kernel_ulong_t)&spt_i2c_info }, + { PCI_VDEVICE(INTEL, 0xa162), (kernel_ulong_t)&spt_i2c_info }, { PCI_VDEVICE(INTEL, 0xa166), (kernel_ulong_t)&spt_uart_info }, /* KBL-H */ { PCI_VDEVICE(INTEL, 0xa2a7), (kernel_ulong_t)&spt_uart_info }, -- cgit v1.1 From 6af42e5dd008535b9c1a7d2538ab19617538c3eb Mon Sep 17 00:00:00 2001 From: Arvind Yadav Date: Sun, 20 Aug 2017 00:59:37 +0530 Subject: mfd: da9055: Constify i2c_device_id i2c_device_id are not supposed to change at runtime. All functions working with i2c_device_id provided by work with const i2c_device_id. So mark the non-const structs as const. Signed-off-by: Arvind Yadav Signed-off-by: Lee Jones --- drivers/mfd/da9055-i2c.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/mfd/da9055-i2c.c b/drivers/mfd/da9055-i2c.c index b53e100..8169a5c 100644 --- a/drivers/mfd/da9055-i2c.c +++ b/drivers/mfd/da9055-i2c.c @@ -62,7 +62,7 @@ static int da9055_i2c_remove(struct i2c_client *i2c) * purposes separate). As a result there are specific DA9055 ids for PMIC * and CODEC, which must be different to operate together. */ -static struct i2c_device_id da9055_i2c_id[] = { +static const struct i2c_device_id da9055_i2c_id[] = { {"da9055-pmic", 0}, { } }; -- cgit v1.1 From 0b471aaa0e1a8f3d06c76b52c3a903f817d7052e Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Sun, 23 Jul 2017 23:02:19 -0700 Subject: mfd: intel-lpss: Put I2C and SPI controllers into reset state on suspend Commit 274e43edcda6f ("mfd: intel-lpss: Do not put device in reset state on suspend") changed the behavior on suspend by not putting LPSS controllers into reset. This was done because S3/S0ix fail if UART device is put into reset and no_console_suspend flag is enabled. Because of the above change, I2C controller gets into a bad state if it observes that the I2C lines are pulled low when power to I2C device is cut off during suspend (generally, I2C lines are pulled to power rail of the I2C device in order to ensure that there is no leakage because of the pulls when device is turned off). This results in the controller timing out for all future I2C operations after resume. It is primarily because of the following sequence of operations: During suspend: 1. I2C controller is disabled, but it is not put into reset. 2. Power to I2C device is cut off. 3. #2 results in the I2C lines being pulled low. ==> At this point the I2C controller gets into a bad state On resume: 1. Power to I2C device is enabled. 2. #2 results in the I2C lines being pulled high. 3. I2C controller is enabled. However, even after enabling the I2C controller, all future I2C xfers fail since the controller is in a bad state and does not attempt to make any transactions and hence times out. In order to ensure that the controller does not get into a bad state, this change puts it into reset if the controller type is not UART. With this change, the order of operations is: During suspend: 1. I2C controller is disabled and put into reset. 2. Power to I2C device is cut off. 3. #2 results in the I2C lines being pulled low. On resume: 1. Power to I2C device is enabled. 2. #2 results in the I2C lines being pulled high. 3. I2C controller is enabled and taken out of reset. Signed-off-by: Furquan Shaikh Signed-off-by: Lee Jones --- drivers/mfd/intel-lpss.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/mfd/intel-lpss.c b/drivers/mfd/intel-lpss.c index 70c646b..0e0ab9b 100644 --- a/drivers/mfd/intel-lpss.c +++ b/drivers/mfd/intel-lpss.c @@ -502,6 +502,14 @@ int intel_lpss_suspend(struct device *dev) for (i = 0; i < LPSS_PRIV_REG_COUNT; i++) lpss->priv_ctx[i] = readl(lpss->priv + i * 4); + /* + * If the device type is not UART, then put the controller into + * reset. UART cannot be put into reset since S3/S0ix fail when + * no_console_suspend flag is enabled. + */ + if (lpss->type != LPSS_DEV_UART) + writel(0, lpss->priv + LPSS_PRIV_RESETS); + return 0; } EXPORT_SYMBOL_GPL(intel_lpss_suspend); -- cgit v1.1 From 7e1372a4ceb80dafef5ff661a66d7b3a1a8c0a75 Mon Sep 17 00:00:00 2001 From: Arvind Yadav Date: Mon, 21 Aug 2017 23:25:27 +0530 Subject: mfd: da9052: Constify spi_device_id spi_device_id are not supposed to change at runtime. All functions working with spi_device_id provided by work with const spi_device_id. So mark the non-const structs as const. Signed-off-by: Arvind Yadav Signed-off-by: Lee Jones --- drivers/mfd/da9052-spi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/mfd/da9052-spi.c b/drivers/mfd/da9052-spi.c index b9ea1b2..abfb118 100644 --- a/drivers/mfd/da9052-spi.c +++ b/drivers/mfd/da9052-spi.c @@ -67,7 +67,7 @@ static int da9052_spi_remove(struct spi_device *spi) return 0; } -static struct spi_device_id da9052_spi_id[] = { +static const struct spi_device_id da9052_spi_id[] = { {"da9052", DA9052}, {"da9053-aa", DA9053_AA}, {"da9053-ba", DA9053_BA}, -- cgit v1.1 From 993dc737c0996c163325961fb62a0ed9fd0308b4 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Wed, 23 Aug 2017 16:44:51 +0200 Subject: mfd: omap-usb-tll: Fix register offsets gcc-8 notices that the register number calculation is wrong when the offset is an 'u8' but the number is larger than 256: drivers/mfd/omap-usb-tll.c: In function 'omap_tll_init': drivers/mfd/omap-usb-tll.c:90:46: error: overflow in conversion from 'int' to 'u8 {aka unsigned char}' chages value from 'i * 256 + 2070' to '22' [-Werror=overflow] This addresses it by always using a 32-bit offset number for the register. This is apparently an old problem that previous compilers did not find. Fixes: 16fa3dc75c22 ("mfd: omap-usb-tll: HOST TLL platform driver") Signed-off-by: Arnd Bergmann Signed-off-by: Lee Jones --- drivers/mfd/omap-usb-tll.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/mfd/omap-usb-tll.c b/drivers/mfd/omap-usb-tll.c index 6f5300b..44a5d66 100644 --- a/drivers/mfd/omap-usb-tll.c +++ b/drivers/mfd/omap-usb-tll.c @@ -131,12 +131,12 @@ static inline u32 usbtll_read(void __iomem *base, u32 reg) return readl_relaxed(base + reg); } -static inline void usbtll_writeb(void __iomem *base, u8 reg, u8 val) +static inline void usbtll_writeb(void __iomem *base, u32 reg, u8 val) { writeb_relaxed(val, base + reg); } -static inline u8 usbtll_readb(void __iomem *base, u8 reg) +static inline u8 usbtll_readb(void __iomem *base, u32 reg) { return readb_relaxed(base + reg); } -- cgit v1.1 From ce994077ce4ffb13d2a9a8e5cc17800e7136bc80 Mon Sep 17 00:00:00 2001 From: Andrey Smirnov Date: Mon, 28 Aug 2017 09:31:31 -0700 Subject: dt-bindings: mfd: Add bindings for ZII RAVE devices Add Device Tree bindings for RAVE Supervisory Processor, an MCU implementing varoius bits of housekeeping functionality (watchdoging, backlight control, LED control, etc) on RAVE family of products by Zodiac Inflight Innovations. Acked-by: Rob Herring Signed-off-by: Andrey Smirnov Signed-off-by: Lee Jones --- .../devicetree/bindings/mfd/zii,rave-sp.txt | 39 ++++++++++++++++++++++ 1 file changed, 39 insertions(+) create mode 100644 Documentation/devicetree/bindings/mfd/zii,rave-sp.txt diff --git a/Documentation/devicetree/bindings/mfd/zii,rave-sp.txt b/Documentation/devicetree/bindings/mfd/zii,rave-sp.txt new file mode 100644 index 0000000..088eff9 --- /dev/null +++ b/Documentation/devicetree/bindings/mfd/zii,rave-sp.txt @@ -0,0 +1,39 @@ +Zodiac Inflight Innovations RAVE Supervisory Processor + +RAVE Supervisory Processor communicates with SoC over UART. It is +expected that its Device Tree node is specified as a child of a node +corresponding to UART controller used for communication. + +Required parent device properties: + + - compatible: Should be one of: + - "zii,rave-sp-niu" + - "zii,rave-sp-mezz" + - "zii,rave-sp-esb" + - "zii,rave-sp-rdu1" + - "zii,rave-sp-rdu2" + + - current-speed: Should be set to baud rate SP device is using + +RAVE SP consists of the following sub-devices: + +Device Description +------ ----------- +rave-sp-wdt : Watchdog +rave-sp-nvmem : Interface to onborad EEPROM +rave-sp-backlight : Display backlight +rave-sp-hwmon : Interface to onboard hardware sensors +rave-sp-leds : Interface to onboard LEDs +rave-sp-input : Interface to onboard power button + +Example of usage: + + rdu { + compatible = "zii,rave-sp-rdu2"; + current-speed = <1000000>; + + watchdog { + compatible = "zii,rave-sp-watchdog"; + }; + }; + -- cgit v1.1 From 4d9ed62ab1425d85b25d04096cb4e74117e6dc24 Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Mon, 4 Sep 2017 15:22:41 +0200 Subject: mfd: intel_soc_pmic: Export separate mfd-cell configs for BYT and CHT Both Bay and Cherry Trail devices may be used together with a Crystal Cove PMIC. Each platform has its own variant of the PMIC, which both use the same ACPI HID, but they are not 100% compatible. Looking at the android x86 kernel sources where most of the Crystal Cove code comes from, it talks about "Valley View", "Bay Trail" and / or BYT without ever mentioning Cherry Trail, with the exception of the regulator driver. The Asus Zenfone-2 kernel code has 2 regulator drivers, one for Crystal Cove and one for what it calls Crystal Cove Plus. The Crystal Cove Plus regulator driver is the only one to mention Cherry Trail and that driver uses different register addresses then the normal (Bay Trail) Crystal Cove regulator driver, showing that at least the regulator register addresses are different. The GPIO code should work on both, and the PWM code is known to work on both and is necessary for backlight control on some Cherry Trail devices. Testing has shown that the ACPI OpRegion code otoh is causing problems on Cherry Trail devices, which is not surprising as it deals with the regulators and those have different register addresses on CHT. Specifically the ACPI OpRegion code causes the external microsd slot on a Dell Venue 8 5855 (Cherry Trail version) to not work and the eMMC to become unreliable and throw lots of errors. This commit replaces the single mfd_cell array currently used for Crystal Cove with 2 separate arrays, one for the Bay Trail variant and one for the Cherry Trail variant, note that the Cherry Trail version of the array only contains gpio and pwm cells. The PMIC OpRegion cell is deliberately not included and drivers for the other cells in the Bay Trail cell array were never upstreamed. Fixes: 7cf0a66f32 ("mfd: intel_soc_pmic: Crystal Cove support") Reported-and-tested-by: russianneuromancer Signed-off-by: Hans de Goede Reviewed-by: Andy Shevchenko Signed-off-by: Lee Jones --- drivers/mfd/intel_soc_pmic_core.c | 2 +- drivers/mfd/intel_soc_pmic_core.h | 3 ++- drivers/mfd/intel_soc_pmic_crc.c | 27 +++++++++++++++++++++++---- 3 files changed, 26 insertions(+), 6 deletions(-) diff --git a/drivers/mfd/intel_soc_pmic_core.c b/drivers/mfd/intel_soc_pmic_core.c index 13737be..2234a84 100644 --- a/drivers/mfd/intel_soc_pmic_core.c +++ b/drivers/mfd/intel_soc_pmic_core.c @@ -157,7 +157,7 @@ MODULE_DEVICE_TABLE(i2c, intel_soc_pmic_i2c_id); #if defined(CONFIG_ACPI) static const struct acpi_device_id intel_soc_pmic_acpi_match[] = { - {"INT33FD", (kernel_ulong_t)&intel_soc_pmic_config_crc}, + {"INT33FD", (kernel_ulong_t)&intel_soc_pmic_config_byt_crc}, { }, }; MODULE_DEVICE_TABLE(acpi, intel_soc_pmic_acpi_match); diff --git a/drivers/mfd/intel_soc_pmic_core.h b/drivers/mfd/intel_soc_pmic_core.h index ff2464b..90a1416 100644 --- a/drivers/mfd/intel_soc_pmic_core.h +++ b/drivers/mfd/intel_soc_pmic_core.h @@ -27,6 +27,7 @@ struct intel_soc_pmic_config { const struct regmap_irq_chip *irq_chip; }; -extern struct intel_soc_pmic_config intel_soc_pmic_config_crc; +extern struct intel_soc_pmic_config intel_soc_pmic_config_byt_crc; +extern struct intel_soc_pmic_config intel_soc_pmic_config_cht_crc; #endif /* __INTEL_SOC_PMIC_CORE_H__ */ diff --git a/drivers/mfd/intel_soc_pmic_crc.c b/drivers/mfd/intel_soc_pmic_crc.c index 4a74948..6d19a6d 100644 --- a/drivers/mfd/intel_soc_pmic_crc.c +++ b/drivers/mfd/intel_soc_pmic_crc.c @@ -80,7 +80,7 @@ static struct resource bcu_resources[] = { }, }; -static struct mfd_cell crystal_cove_dev[] = { +static struct mfd_cell crystal_cove_byt_dev[] = { { .name = "crystal_cove_pwrsrc", .num_resources = ARRAY_SIZE(pwrsrc_resources), @@ -114,6 +114,17 @@ static struct mfd_cell crystal_cove_dev[] = { }, }; +static struct mfd_cell crystal_cove_cht_dev[] = { + { + .name = "crystal_cove_gpio", + .num_resources = ARRAY_SIZE(gpio_resources), + .resources = gpio_resources, + }, + { + .name = "crystal_cove_pwm", + }, +}; + static const struct regmap_config crystal_cove_regmap_config = { .reg_bits = 8, .val_bits = 8, @@ -155,10 +166,18 @@ static const struct regmap_irq_chip crystal_cove_irq_chip = { .mask_base = CRYSTAL_COVE_REG_MIRQLVL1, }; -struct intel_soc_pmic_config intel_soc_pmic_config_crc = { +struct intel_soc_pmic_config intel_soc_pmic_config_byt_crc = { + .irq_flags = IRQF_TRIGGER_RISING, + .cell_dev = crystal_cove_byt_dev, + .n_cell_devs = ARRAY_SIZE(crystal_cove_byt_dev), + .regmap_config = &crystal_cove_regmap_config, + .irq_chip = &crystal_cove_irq_chip, +}; + +struct intel_soc_pmic_config intel_soc_pmic_config_cht_crc = { .irq_flags = IRQF_TRIGGER_RISING, - .cell_dev = crystal_cove_dev, - .n_cell_devs = ARRAY_SIZE(crystal_cove_dev), + .cell_dev = crystal_cove_cht_dev, + .n_cell_devs = ARRAY_SIZE(crystal_cove_cht_dev), .regmap_config = &crystal_cove_regmap_config, .irq_chip = &crystal_cove_irq_chip, }; -- cgit v1.1 From b01e9348e106544e50691252bf58cde239681f19 Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Mon, 4 Sep 2017 15:22:42 +0200 Subject: mfd: intel_soc_pmic: Differentiate between Bay and Cherry Trail CRC variants Both Bay and Cherry Trail devices may be used together with a Crystal Cove PMIC. Each platform has its own variant of the PMIC, which both use the same ACPI HID, but they are not 100% compatible. This commits makes the intel_soc_pmic_core code check the _HRV of the ACPI-firmware-node and selects intel_soc_pmic_config_byt_crc resp. intel_soc_pmic_config_cht_crc based on this. This fixes the Bay Trail specific ACPI OpRegion code causing problems on Cherry Trail devices. Specifically this was causing the external microsd slot on a Dell Venue 8 5855 (Cherry Trail version) to not work and the eMMC to become unreliable and throw lots of errors. Fixes: 5165238460 ("mfd: intel_soc_pmic: Core driver") Reported-and-tested-by: russianneuromancer Signed-off-by: Hans de Goede Reviewed-by: Andy Shevchenko Signed-off-by: Lee Jones --- drivers/mfd/Kconfig | 4 ++-- drivers/mfd/intel_soc_pmic_core.c | 34 ++++++++++++++++++++++++++++------ 2 files changed, 30 insertions(+), 8 deletions(-) diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig index 7bc4ee1..fc5e4fe 100644 --- a/drivers/mfd/Kconfig +++ b/drivers/mfd/Kconfig @@ -467,12 +467,12 @@ config LPC_SCH config INTEL_SOC_PMIC bool "Support for Crystal Cove PMIC" - depends on HAS_IOMEM && I2C=y && GPIOLIB && COMMON_CLK + depends on ACPI && HAS_IOMEM && I2C=y && GPIOLIB && COMMON_CLK depends on X86 || COMPILE_TEST select MFD_CORE select REGMAP_I2C select REGMAP_IRQ - select I2C_DESIGNWARE_PLATFORM if ACPI + select I2C_DESIGNWARE_PLATFORM help Select this option to enable support for Crystal Cove PMIC on some Intel SoC systems. The PMIC provides ADC, GPIO, diff --git a/drivers/mfd/intel_soc_pmic_core.c b/drivers/mfd/intel_soc_pmic_core.c index 2234a84..36adf9e 100644 --- a/drivers/mfd/intel_soc_pmic_core.c +++ b/drivers/mfd/intel_soc_pmic_core.c @@ -16,6 +16,7 @@ * Author: Zhu, Lejun */ +#include #include #include #include @@ -28,6 +29,10 @@ #include #include "intel_soc_pmic_core.h" +/* Crystal Cove PMIC shares same ACPI ID between different platforms */ +#define BYT_CRC_HRV 2 +#define CHT_CRC_HRV 3 + /* Lookup table for the Panel Enable/Disable line as GPIO signals */ static struct gpiod_lookup_table panel_gpio_table = { /* Intel GFX is consumer */ @@ -48,16 +53,33 @@ static int intel_soc_pmic_i2c_probe(struct i2c_client *i2c, const struct i2c_device_id *i2c_id) { struct device *dev = &i2c->dev; - const struct acpi_device_id *id; struct intel_soc_pmic_config *config; struct intel_soc_pmic *pmic; + unsigned long long hrv; + acpi_status status; int ret; - id = acpi_match_device(dev->driver->acpi_match_table, dev); - if (!id || !id->driver_data) + /* + * There are 2 different Crystal Cove PMICs a Bay Trail and Cherry + * Trail version, use _HRV to differentiate between the 2. + */ + status = acpi_evaluate_integer(ACPI_HANDLE(dev), "_HRV", NULL, &hrv); + if (ACPI_FAILURE(status)) { + dev_err(dev, "Failed to get PMIC hardware revision\n"); return -ENODEV; - - config = (struct intel_soc_pmic_config *)id->driver_data; + } + + switch (hrv) { + case BYT_CRC_HRV: + config = &intel_soc_pmic_config_byt_crc; + break; + case CHT_CRC_HRV: + config = &intel_soc_pmic_config_cht_crc; + break; + default: + dev_warn(dev, "Unknown hardware rev %llu, assuming BYT\n", hrv); + config = &intel_soc_pmic_config_byt_crc; + } pmic = devm_kzalloc(dev, sizeof(*pmic), GFP_KERNEL); if (!pmic) @@ -157,7 +179,7 @@ MODULE_DEVICE_TABLE(i2c, intel_soc_pmic_i2c_id); #if defined(CONFIG_ACPI) static const struct acpi_device_id intel_soc_pmic_acpi_match[] = { - {"INT33FD", (kernel_ulong_t)&intel_soc_pmic_config_byt_crc}, + { "INT33FD" }, { }, }; MODULE_DEVICE_TABLE(acpi, intel_soc_pmic_acpi_match); -- cgit v1.1