From d10db3a07e38bfb1bff92c790072d85b0bcc07eb Mon Sep 17 00:00:00 2001 From: Roel Kluin Date: Thu, 23 Apr 2009 16:27:39 +0200 Subject: i2c-pxa.c: timeouts off by 1 With `while (timeout--)' timeout reaches -1 after the loop, so the tests below are off by one. Signed-off-by: Roel Kluin Acked-by: Wolfram Sang Signed-off-by: Ben Dooks --- drivers/i2c/busses/i2c-pxa.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/i2c/busses/i2c-pxa.c b/drivers/i2c/busses/i2c-pxa.c index c1405c8..acc7143 100644 --- a/drivers/i2c/busses/i2c-pxa.c +++ b/drivers/i2c/busses/i2c-pxa.c @@ -265,10 +265,10 @@ static int i2c_pxa_wait_bus_not_busy(struct pxa_i2c *i2c) show_state(i2c); } - if (timeout <= 0) + if (timeout < 0) show_state(i2c); - return timeout <= 0 ? I2C_RETRY : 0; + return timeout < 0 ? I2C_RETRY : 0; } static int i2c_pxa_wait_master(struct pxa_i2c *i2c) @@ -612,7 +612,7 @@ static int i2c_pxa_pio_set_master(struct pxa_i2c *i2c) show_state(i2c); } - if (timeout <= 0) { + if (timeout < 0) { show_state(i2c); dev_err(&i2c->adap.dev, "i2c_pxa: timeout waiting for bus free\n"); -- cgit v1.1 From 1904b03430ade1cd621bb8b6ca8e38819a2f9267 Mon Sep 17 00:00:00 2001 From: Wolfgang Grandegger Date: Thu, 9 Apr 2009 11:59:52 +0200 Subject: i2c-mpc: bug fix for MPC52xx clock setting and printout The clock setting did not work for the MPC52xx due to a stupid bug. Furthermore, the dev info output "clock=0" for old device trees was misleading. This patch fixes both issues. Signed-off-by: Wolfgang Grandegger Acked-by: Grant Likely Signed-off-by: Ben Dooks --- drivers/i2c/busses/i2c-mpc.c | 34 ++++++++++++++++++++-------------- 1 file changed, 20 insertions(+), 14 deletions(-) diff --git a/drivers/i2c/busses/i2c-mpc.c b/drivers/i2c/busses/i2c-mpc.c index 4af5c09..dd778d7 100644 --- a/drivers/i2c/busses/i2c-mpc.c +++ b/drivers/i2c/busses/i2c-mpc.c @@ -164,7 +164,7 @@ static int i2c_wait(struct mpc_i2c *i2c, unsigned timeout, int writing) return 0; } -#ifdef CONFIG_PPC_52xx +#ifdef CONFIG_PPC_MPC52xx static const struct mpc_i2c_divider mpc_i2c_dividers_52xx[] = { {20, 0x20}, {22, 0x21}, {24, 0x22}, {26, 0x23}, {28, 0x24}, {30, 0x01}, {32, 0x25}, {34, 0x02}, @@ -188,7 +188,7 @@ static const struct mpc_i2c_divider mpc_i2c_dividers_52xx[] = { int mpc_i2c_get_fdr_52xx(struct device_node *node, u32 clock, int prescaler) { - const struct mpc52xx_i2c_divider *div = NULL; + const struct mpc_i2c_divider *div = NULL; unsigned int pvr = mfspr(SPRN_PVR); u32 divider; int i; @@ -203,7 +203,7 @@ int mpc_i2c_get_fdr_52xx(struct device_node *node, u32 clock, int prescaler) * We want to choose an FDR/DFSR that generates an I2C bus speed that * is equal to or lower than the requested speed. */ - for (i = 0; i < ARRAY_SIZE(mpc52xx_i2c_dividers); i++) { + for (i = 0; i < ARRAY_SIZE(mpc_i2c_dividers_52xx); i++) { div = &mpc_i2c_dividers_52xx[i]; /* Old MPC5200 rev A CPUs do not support the high bits */ if (div->fdr & 0xc0 && pvr == 0x80822011) @@ -219,20 +219,23 @@ static void mpc_i2c_setclock_52xx(struct device_node *node, struct mpc_i2c *i2c, u32 clock, u32 prescaler) { - int fdr = mpc52xx_i2c_get_fdr(node, clock, prescaler); + int ret, fdr; + + ret = mpc_i2c_get_fdr_52xx(node, clock, prescaler); + fdr = (ret >= 0) ? ret : 0x3f; /* backward compatibility */ - if (fdr < 0) - fdr = 0x3f; /* backward compatibility */ writeb(fdr & 0xff, i2c->base + MPC_I2C_FDR); - dev_info(i2c->dev, "clock %d Hz (fdr=%d)\n", clock, fdr); + + if (ret >= 0) + dev_info(i2c->dev, "clock %d Hz (fdr=%d)\n", clock, fdr); } -#else /* !CONFIG_PPC_52xx */ +#else /* !CONFIG_PPC_MPC52xx */ static void mpc_i2c_setclock_52xx(struct device_node *node, struct mpc_i2c *i2c, u32 clock, u32 prescaler) { } -#endif /* CONFIG_PPC_52xx*/ +#endif /* CONFIG_PPC_MPC52xx*/ #ifdef CONFIG_FSL_SOC static const struct mpc_i2c_divider mpc_i2c_dividers_8xxx[] = { @@ -321,14 +324,17 @@ static void mpc_i2c_setclock_8xxx(struct device_node *node, struct mpc_i2c *i2c, u32 clock, u32 prescaler) { - int fdr = mpc_i2c_get_fdr_8xxx(node, clock, prescaler); + int ret, fdr; + + ret = mpc_i2c_get_fdr_8xxx(node, clock, prescaler); + fdr = (ret >= 0) ? ret : 0x1031; /* backward compatibility */ - if (fdr < 0) - fdr = 0x1031; /* backward compatibility */ writeb(fdr & 0xff, i2c->base + MPC_I2C_FDR); writeb((fdr >> 8) & 0xff, i2c->base + MPC_I2C_DFSRR); - dev_info(i2c->dev, "clock %d Hz (dfsrr=%d fdr=%d)\n", - clock, fdr >> 8, fdr & 0xff); + + if (ret >= 0) + dev_info(i2c->dev, "clock %d Hz (dfsrr=%d fdr=%d)\n", + clock, fdr >> 8, fdr & 0xff); } #else /* !CONFIG_FSL_SOC */ -- cgit v1.1 From 89bc5d4a915dc6675961f797de91748bda87efcc Mon Sep 17 00:00:00 2001 From: Mark Brown Date: Thu, 9 Apr 2009 17:03:24 +0100 Subject: i2c: Enable i2c-s3c2410 for S3C64XX too This controller is also present on the S3C64xx series processors so enable the driver in Kconfig for those platforms. Signed-off-by: Mark Brown Signed-off-by: Ben Dooks --- drivers/i2c/busses/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig index a48c8ae..f1c6ca7 100644 --- a/drivers/i2c/busses/Kconfig +++ b/drivers/i2c/busses/Kconfig @@ -467,7 +467,7 @@ config I2C_PXA_SLAVE config I2C_S3C2410 tristate "S3C2410 I2C Driver" - depends on ARCH_S3C2410 + depends on ARCH_S3C2410 || ARCH_S3C64XX help Say Y here to include support for I2C controller in the Samsung S3C2410 based System-on-Chip devices. -- cgit v1.1 From 36521c271e5f93b249329ee7f321d27825970e31 Mon Sep 17 00:00:00 2001 From: Mark Ware Date: Tue, 21 Apr 2009 22:49:02 +1000 Subject: i2c-cpm: Pass dev ptr to dma_*_coherent rather than NULL Recent DMA changes result in a BUG() when NULL is passed to dma_alloc_coherent in place of a device. Signed-off-by: Mark Ware [ben-linux@fluff.org: fix patch moves] Signed-off-by: Ben Dooks --- drivers/i2c/busses/i2c-cpm.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/i2c/busses/i2c-cpm.c b/drivers/i2c/busses/i2c-cpm.c index 3fcf78e..b5db8b8 100644 --- a/drivers/i2c/busses/i2c-cpm.c +++ b/drivers/i2c/busses/i2c-cpm.c @@ -531,16 +531,16 @@ static int __devinit cpm_i2c_setup(struct cpm_i2c *cpm) rbdf = cpm->rbase; for (i = 0; i < CPM_MAXBD; i++) { - cpm->rxbuf[i] = dma_alloc_coherent( - NULL, CPM_MAX_READ + 1, &cpm->rxdma[i], GFP_KERNEL); + cpm->rxbuf[i] = dma_alloc_coherent(&cpm->ofdev->dev, + CPM_MAX_READ + 1, + &cpm->rxdma[i], GFP_KERNEL); if (!cpm->rxbuf[i]) { ret = -ENOMEM; goto out_muram; } out_be32(&rbdf[i].cbd_bufaddr, ((cpm->rxdma[i] + 1) & ~1)); - cpm->txbuf[i] = (unsigned char *)dma_alloc_coherent( - NULL, CPM_MAX_READ + 1, &cpm->txdma[i], GFP_KERNEL); + cpm->txbuf[i] = (unsigned char *)dma_alloc_coherent(&cpm->ofdev->dev, CPM_MAX_READ + 1, &cpm->txdma[i], GFP_KERNEL); if (!cpm->txbuf[i]) { ret = -ENOMEM; goto out_muram; @@ -585,10 +585,10 @@ static int __devinit cpm_i2c_setup(struct cpm_i2c *cpm) out_muram: for (i = 0; i < CPM_MAXBD; i++) { if (cpm->rxbuf[i]) - dma_free_coherent(NULL, CPM_MAX_READ + 1, + dma_free_coherent(&cpm->ofdev->dev, CPM_MAX_READ + 1, cpm->rxbuf[i], cpm->rxdma[i]); if (cpm->txbuf[i]) - dma_free_coherent(NULL, CPM_MAX_READ + 1, + dma_free_coherent(&cpm->ofdev->dev, CPM_MAX_READ + 1, cpm->txbuf[i], cpm->txdma[i]); } cpm_muram_free(cpm->dp_addr); @@ -619,9 +619,9 @@ static void cpm_i2c_shutdown(struct cpm_i2c *cpm) /* Free all memory */ for (i = 0; i < CPM_MAXBD; i++) { - dma_free_coherent(NULL, CPM_MAX_READ + 1, + dma_free_coherent(&cpm->ofdev->dev, CPM_MAX_READ + 1, cpm->rxbuf[i], cpm->rxdma[i]); - dma_free_coherent(NULL, CPM_MAX_READ + 1, + dma_free_coherent(&cpm->ofdev->dev, CPM_MAX_READ + 1, cpm->txbuf[i], cpm->txdma[i]); } -- cgit v1.1