From 6c4a057bffe9823221eab547e11fac181dc18a2b Mon Sep 17 00:00:00 2001 From: Rajendra Nayak Date: Wed, 4 Apr 2012 10:20:01 -0600 Subject: ARM: OMAP4: clock data: Force a DPLL clkdm/pwrdm ON before a relock All DPLLs except USB are in ALWON powerdomain. Make sure the clkdm/pwrdm for USB DPLL (l3init) is turned on before attempting a DPLL relock. So, mark the database accordingly. Without this fix, it was seen that DPLL relock fails while testing relock in a loop of USB DPLL. Cc: Nishanth Menon Tested-by: Ameya Palande Signed-off-by: Rajendra Nayak Signed-off-by: Paul Walmsley --- arch/arm/mach-omap2/clock44xx_data.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c index 984904f..fa6ea65 100644 --- a/arch/arm/mach-omap2/clock44xx_data.c +++ b/arch/arm/mach-omap2/clock44xx_data.c @@ -978,6 +978,7 @@ static struct clk dpll_usb_ck = { .recalc = &omap3_dpll_recalc, .round_rate = &omap2_dpll_round_rate, .set_rate = &omap3_noncore_dpll_set_rate, + .clkdm_name = "l3_init_clkdm", }; static struct clk dpll_usb_clkdcoldo_ck = { -- cgit v1.1